// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz
// SPDX-License-Identifier: CC0-1.0

`verilator_config

isolate_assignments -module "file" -var "b"
isolate_assignments -module "file" -task "set_b_d" -var "t_c*"
isolate_assignments -module "file" -function "get_31_16" -var "t_crc"
isolate_assignments -module "file" -function "get_31_16"