$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module top $end
  $var wire 1 " clk $end
  $scope module t $end
   $var wire 1 " clk $end
   $var wire 8 # in0 [7:0] $end
   $var wire 8 $ in1 [7:0] $end
   $var wire 8 % out0 [7:0] $end
   $var wire 8 & out1 [7:0] $end
   $var wire 32 ' count [31:0] $end
   $scope module i_sub0 $end
    $var wire 1 ( clk $end
    $var wire 8 ) in [7:0] $end
    $var wire 8 * out [7:0] $end
    $var wire 8 + ff [7:0] $end
   $upscope $end
   $scope module i_sub1 $end
    $var wire 1 , clk $end
    $var wire 8 - in [7:0] $end
    $var wire 8 . out [7:0] $end
    $var wire 8 / ff [7:0] $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
0"
b00010100 #
b01100100 $
b00000000 %
b00000000 &
b00000000000000000000000000000000 '
0(
b00010100 )
b00000000 *
b00000000 +
0,
b01100100 -
b00000000 .
b00000000 /
#10
1"
b00010101 #
b01100110 $
b00010101 %
b01100110 &
b00000000000000000000000000000001 '
1(
b00010101 )
b00010101 *
b00010101 +
1,
b01100110 -
b01100110 .
b01100110 /
#15
0"
0(
0,
#20
1"
b00010110 #
b01101000 $
b00010110 %
b01101000 &
b00000000000000000000000000000010 '
1(
b00010110 )
b00010110 *
b00010110 +
1,
b01101000 -
b01101000 .
b01101000 /
#25
0"
0(
0,
#30
1"
b00010111 #
b01101010 $
b00010111 %
b01101010 &
b00000000000000000000000000000011 '
1(
b00010111 )
b00010111 *
b00010111 +
1,
b01101010 -
b01101010 .
b01101010 /
#35
0"
0(
0,
#40
1"
b00011000 #
b01101100 $
b00011000 %
b01101100 &
b00000000000000000000000000000100 '
1(
b00011000 )
b00011000 *
b00011000 +
1,
b01101100 -
b01101100 .
b01101100 /