$date
Sat Mar 14 09:16:43 2026

$end
$version
Generated by VerilatedFst
$end
$timescale
1ps
$end
 $scope module top $end
  $attrbegin misc 07 $unit::state_t 4 VAL_A VAL_B VAL_C VAL_D 00 01 10 11 1 $end
  $attrbegin misc 07 t.other_state_t 3 VAL_X VAL_Y VAL_Z 00 01 10 2 $end
  $var wire 1 ! clk $end
  $scope module $unit $end
  $upscope $end
  $scope module t $end
   $var wire 1 ! clk $end
   $attrbegin misc 07 "" 1 $end
   $var logic 2 " v_enumed [1:0] $end
   $attrbegin misc 07 "" 2 $end
   $var logic 2 # v_other_enumed [1:0] $end
   $scope interface sink $end
    $attrbegin misc 07 "" 1 $end
    $var logic 2 $ state [1:0] $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end
#0
$dumpvars
b00 $
b00 #
b00 "
0!
$end
#10
1!