// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0

module t (
    input clk
);

  always @(posedge $sampled(clk)) begin
    $write("*-* All Finished *-*\n");
    $finish;
  end
endmodule