// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0

module t (
    input clk
);

  integer cyc = 0;
  reg [63:0] crc;
  reg [63:0] sum;

  // Take CRC data and apply to testblock inputs
  wire [1:0] in = crc[1:0];

  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire [1:0] out;  // From test of Test.v
  // End of automatics

  Test test (  /*AUTOINST*/
      // Outputs
      .out(out[1:0]),
      // Inputs
      .in(in[1:0])
  );

  // Aggregate outputs into a single result vector
  wire [63:0] result = {62'h0, out};

  // What checksum will we end up with
  `define EXPECTED_SUM 64'hbb2d9709592f64bd

  // Test loop
  always @(posedge clk) begin
`ifdef TEST_VERBOSE
    $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
    cyc <= cyc + 1;
    crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
    sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
    if (cyc == 0) begin
      // Setup
      crc <= 64'h5aef0c8d_d70a4497;
    end
    else if (cyc < 10) begin
      sum <= 64'h0;
    end
    else if (cyc < 90) begin
    end
    else if (cyc == 99) begin
      $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
      if (crc !== 64'hc77bb9b3784ea091) $stop;
      if (sum !== `EXPECTED_SUM) $stop;
      $write("*-* All Finished *-*\n");
      $finish;
    end
  end

endmodule

module Test (  /*AUTOARG*/
    // Outputs
    out,
    // Inputs
    in
);
  input [1:0] in;
  output reg [1:0] out;
  always @* begin
    // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
    case (in[1:0])
      2'd0, 2'd1, 2'd2, 2'd3: begin
        out = in;
      end
    endcase
  end
endmodule