// DESCRIPTION: Verilator: Verilog Test module
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of either the GNU Lesser General Public License Version 3
// or the Perl Artistic License Version 2.0.
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
// verilog_format: on

class num_gen;
  function int get_num(int x);
    return x;
  endfunction
endclass

module t;
  num_gen gen;
  bit [4:0] arr[];
  initial begin
    gen = new;
    arr = new[1];
    arr[0][gen.get_num(3)] = 1'b1;
    `checkh(arr[0][3], 1'b1);
    $finish;
  end
endmodule