// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz
// SPDX-License-Identifier: CC0-1.0

`verilator_config

sformat -task "mon_scope_name" -var "formatted"
public_flat_rd -module "sub" -var "in"
public_flat_rw -module "sub" -var "in_a"
public_flat_rw -module "sub" -var "in_b" @(posedge t.monclk)
public_flat_rw -module "sub" -var "fr_a"
public_flat_rw -module "sub" -var "fr_b" @(posedge t.monclk)
// Cover other edge declarations
public_flat_rw -module "sub" -var "fr_chk" @(posedge t.monclk or negedge t.monclk or edge t.monclk)