$date
	Sat Apr  5 13:52:51 2025

$end
$version
	fstWriter
$end
$timescale
	1ps
$end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 " cyc [31:0] $end
$var logic 1 # rstn $end
$var real_parameter 64 $ fst_gparam_real $end
$var real_parameter 64 % fst_lparam_real $end
$var real 64 $ fst_real $end
$var integer 32 & fst_integer [31:0] $end
$var bit 1 ' fst_bit $end
$var logic 1 ( fst_logic $end
$var int 32 ) fst_int [31:0] $end
$var shortint 16 * fst_shortint [15:0] $end
$var longint 64 + fst_longint [63:0] $end
$var byte 8 , fst_byte [7:0] $end
$var parameter 32 - fst_parameter [31:0] $end
$var parameter 32 . fst_lparam [31:0] $end
$var supply0 1 / fst_supply0 $end
$var supply1 1 0 fst_supply1 $end
$var tri0 1 / fst_tri0 $end
$var tri1 1 0 fst_tri1 $end
$var tri 1 1 fst_tri $end
$var wire 1 2 fst_wire $end
$var logic 5 3 state [4:0] $end
$scope module test $end
$var wire 1 ! clk $end
$var wire 1 # rstn $end
$var wire 5 3 state [4:0] $end
$var logic 5 4 state_w [4:0] $end
$var logic 5 5 state_array[0] [4:0] $end
$var logic 5 6 state_array[1] [4:0] $end
$var logic 5 7 state_array[2] [4:0] $end
$scope module unnamedblk1 $end
$var int 32 8 i [31:0] $end
$upscope $end
$scope module unnamedblk2 $end
$var int 32 9 i [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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