$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module t $end
  $var event 1 # ev_test $end
  $var wire 32 $ i [31:0] $end
  $var wire 1 % toggle $end
  $var wire 1 & clk $end
 $upscope $end
$enddefinitions $end


#0
b00000000000000000000000000000000 $
0%
0&
#10
b00000000000000000000000000000001 $
1&
#20
0&
#30
b00000000000000000000000000000010 $
1&
#40
0&
#50
b00000000000000000000000000000011 $
1&
#60
0&
#70
b00000000000000000000000000000100 $
1&
#80
0&
#90
b00000000000000000000000000000101 $
1&
#100
0&
#110
1#
b00000000000000000000000000000110 $
1%
1&
#120
0&
#130
b00000000000000000000000000000111 $
1&
#140
0&
#150
b00000000000000000000000000001000 $
1&
#160
0&
#170
b00000000000000000000000000001001 $
1&
#180
0&
#190
b00000000000000000000000000001010 $
1&
#200
0&
#210
1&