// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0

`verilator_config
hier_workers -module "Core" -workers `WORKERS
hier_workers -module "SubCore" -workers `WORKERS