module Vt_debug_emitv_t;
    input logic clk;
    input logic in;
    typedef enum logic [2:0] {
        ZERO = 3'h0,
        ONE = 3'h1
    } e_t;
    typedef struct packed {
        logic [2:0]  a;
    } ps_t;
    typedef struct {
        logic signed [2:0]  a;
    } us_t;
    typedef union {
        logic a;
    } union_t;
    const struct packed {
        logic [2:0]  a;
    } ps[0:2];
    struct {
        logic signed [2:0]  a;
    } us;
    union {
        logic a;
    } unu;
    integer signed i1;
    int signed array[0:2];
    initial begin
        array = '{0:32'sh1, 1:32'sh2, 2:32'sh3};
    end
    logic [63:32]  downto_32;
    downto_32 = 32'h0;
    function ident;
        input int signed value;
        begin : label0
            ident = value;
            disable label0;
        end
    endfunction
    Iface the_ifaces[3:0] ();
    initial begin
        begin
            if ($test$plusargs("HELLO")) begin
                $display("Hello argument found.");
            end
            if ((Pkg::FOO == 'sh0)) begin
                $write("");
            end
            if ((ZERO == 'sh0)) begin
                $write("");
            end
            if ($value$plusargs("TEST=%d", i1)) begin
                $display("value was %~", i1);
            end
            else begin
                $display("+TEST= not found");
            end
            if (downto_32[33]) begin
                $write("");
            end
            if (downto_32[(ident('sh21) - 'h20)[5:0] + 32
                +:1]) begin
                $write("");
            end
            if ((| downto_32[48:40])) begin
                $write("");
            end
            if ((| downto_32[57:55])) begin
                $write("");
            end
            if ((| downto_32[60:54])) begin
                $write("");
            end
            if (the_ifaces[2].ifsig) begin
                $write("");
            end
            #1;
            $write("After #1 delay");
        end
    end
    bit [6:5] [4:3] [2:1]  arraymanyd[10:11][12:13][14:15];
    logic [15:0]  pubflat;
    logic [15:0]  pubflat_r;
    logic [15:0]  pubflat_w;
    assign pubflat_w = pubflat;
    int signed fd;
    int signed i;
    int signed q[$];
    int signed qb[$:'sh3];
    int signed assoc[string];
    int signed assocassoc[string][real];
    int signed dyn[];
    typedef struct packed {
        logic nn1;
    } nested_named_t;
    typedef struct packed {
        struct packed {
            logic nn2;
        } nested_anonymous;
        struct packed {
            logic nn1;
        } nested_named;
        logic [11:10]  nn3;
    } nibble_t;
    struct packed {
        struct packed {
            logic nn2;
        } nested_anonymous;
        struct packed {
            logic nn1;
        } nested_named;
        logic [11:10]  nn3;
    } [5:4] nibblearray[3:2];
    task t;
        $display("stmt");
    endtask
    function f;
        input int signed v;
        begin : label1
            $display("stmt");
            f = ((v == 'sh0) ? 'sh63 : ((~ v) + 'sh1));
            disable label1;
        end
    endfunction
    initial begin
        begin : unnamedblk1
            int signed other;
            begin
                begin : unnamedblk2
                    int signed i;
                    i = 'sh0;
                    while ((i < 'sh3)) begin
                        begin
                            other = f(i);
                            $display("stmt %~ %~", 
                                     i, other);
                            t();
                        end
                        i = (i + 'h1);
                    end
                end
            end
            begin : named
                $display("stmt");
            end
        end
    end
    final begin
        begin
            $display("stmt");
        end
    end
    always @( in) begin
        begin
            $display("stmt");
        end
    end
    always @(posedge clk) begin
        begin
            $display("posedge clk");
            pubflat_r <= pubflat_w;
        end
    end
    always @(negedge clk) begin
        begin
            $display("negedge clk, pfr = %x", pubflat_r);
        end
    end
    int signed cyc;
    int signed fo;
    int signed sum;
    real r;
    string str;
    int signed mod_val;
    int signed mod_res;
    always @(posedge clk) begin
        begin
            cyc <= (cyc + 'sh1);
            r <= (r + 0.01);
            fo = cyc;
            sub.inc(fosum);
            sum = sub.f(sum);
            $display("[%0t] sum = %~", $time, sum);
            $display("a?= %d", ($c('sh1) ? $c('sh14)
                                 : $c('sh1e)));
            $c(;);
            $display("%d", $c(0));
            fd = $fopen("/dev/null");
            ;
            $fclose(fd);
            fd = $fopen("/dev/null", "r");
            ;
            $fgetc(fd);
            $fflush(fd);
            $fscanf(fd, "%d", sum);
            ;
            $fdisplay(32'h69203d20, "%~", sum);
            $fwrite(fd, "hello");
            $readmemh(string'(fd), array);
            $readmemh(string'(fd), array, 'sh0);
            $readmemh(string'(fd), array, 'sh0, 'sh0);
            sum = 'sh0;
            begin : unnamedblk3
                int signed i;
                i = 'sh0;
                begin : label2
                    while ((i < cyc)) begin
                        begin
                            sum = (sum + i);
                            if ((sum > 'sha)) begin
                                disable label2;
                            end
                            else begin
                                sum = (sum + 'sh1);
                            end
                        end
                        i = (i + 'h1);
                    end
                end
            end
            if ((cyc == 'sh63)) begin
                $finish;
            end
            if ((cyc == 'sh64)) begin
                $stop;
            end
            case (in)
                 // synopsys full_case parallel_case'sh1: begin $display("1");
                end
                default: begin $display("default");
                end
            endcase
            priority case (in)
                'sh1: begin $display("1");
                end
                default: begin $display("default");
                end
            endcase
            unique case (in)
                'sh1: begin $display("1");
                end
                default: begin $display("default");
                end
            endcase
            unique0 case (in)
                'sh1: begin $display("1");
                end
                default: begin $display("default");
                end
            endcase
            if (in) begin
                $display("1");
            end
            else begin
                $display("0");
            end
            priority if (in) begin
                $display("1");
            end
            else begin
                $display("0");
            end
            unique if (in) begin
                $display("1");
            end
            else begin
                $display("0");
            end
            unique0 if (in) begin
                $display("1");
            end
            else begin
                $display("0");
            end
            $display("%~%~", $past(cyc), $past(cyc, 
                                               'sh1));
            str = $sformatf("cyc=%~", cyc);
            ;
            $display("str = %@", str);
            $display("%% [%t] [%^] to=%o td=%d", $time, 
                     $realtime, $time, $time);
            $sscanf(40'h666f6f3d35, "foo=%d", i);
            ;
            $printtimescale;
            if ((i != 'sh5)) begin
                $stop;
            end
            sum = $random();
            sum = $random('sha);
            sum = $urandom();
            sum = $urandom('sha);
            if ((PKG_PARAM != 'sh1)) begin
                $stop;
            end
            sub.r = 62.0;
            mod_res = (mod_val % 'sh5);
            $display("%g", $log10(r));
            $display("%g", $ln(r));
            $display("%g", $exp(r));
            $display("%g", $sqrt(r));
            $display("%g", $floor(r));
            $display("%g", $ceil(r));
            $display("%g", $sin(r));
            $display("%g", $cos(r));
            $display("%g", $tan(r));
            $display("%g", $asin(r));
            $display("%g", $acos(r));
            $display("%g", $atan(r));
            $display("%g", $sinh(r));
            $display("%g", $cosh(r));
            $display("%g", $tanh(r));
            $display("%g", $asinh(r));
            $display("%g", $acosh(r));
            $display("%g", $atanh(r));
            if ($sampled(cyc[1])) begin
                $write("");
            end
            if ($rose(cyc)) begin
                $write("");
            end
            if ($fell(cyc)) begin
                $write("");
            end
            if ($stable(cyc)) begin
                $write("");
            end
            if ((! $stable(cyc))) begin
                $write("");
            end
            if ($past(cyc[1])) begin
                $write("");
            end
            if ($rose(cyc, @( clk))) begin
                $write("");
            end
            if ($fell(cyc, @( clk))) begin
                $write("");
            end
            if ($stable(cyc, @( clk))) begin
                $write("");
            end
            if ((! $stable(cyc, @( clk)))) begin
                $write("");
            end
            if ($past(cyc[1], 'sh5)) begin
                $write("");
            end
            force sum = 'sha;
            begin : unnamedblk1_1
                integer signed __Vrepeat0;
                __Vrepeat0 = 'sh2;
                while ((__Vrepeat0 > 32'h0)) begin
                    if ((sum != 'sha)) begin
                        $stop;
                    end
                    __Vrepeat0 = (__Vrepeat0 - 32'h1);
                end
            end
            release sum;
        end
    end
    property p;
    @(posedge clk) ##1 sum[0]
    endproperty
    property p1;
    @( clk) sum[0]
    endproperty
    property p2;
    @(posedge clk) disable iff (cyc == 'sh1) ##1 sum[0]
    endproperty
    assert property (@( clk) (! ##1 in)
    ) begin
    end
    else begin
    end
    initial begin
        begin
            begin : assert_simple_immediate_else
                assert ('sh0) begin
                end
                else begin
                    $display("fail");
                end
            end
            begin : assert_simple_immediate_stmt
                assert ('sh0) begin
                    $display("pass");
                end
                else begin
                end
            end
            begin : assert_simple_immediate_stmt_else
                assert ('sh0) begin
                    $display("pass");
                end
                else begin
                    $display("fail");
                end
            end
            begin : assume_simple_immediate
                assume ('sh0) begin
                end
                else begin
                end
            end
            begin : assume_simple_immediate_else
                assume ('sh0) begin
                end
                else begin
                    $display("fail");
                end
            end
            begin : assume_simple_immediate_stmt
                assume ('sh0) begin
                    $display("pass");
                end
                else begin
                end
            end
            begin : assume_simple_immediate_stmt_else
                assume ('sh0) begin
                    $display("pass");
                end
                else begin
                    $display("fail");
                end
            end
        end
    end
    always  begin
        begin : assert_observed_deferred_immediate
            assert #0 ('sh0) begin
            end
            else begin
            end
        end
    end
    always  begin
        begin : assert_observed_deferred_immediate_else
            assert #0 ('sh0) begin
            end
            else begin
                $display("fail");
            end
        end
    end
    always  begin
        begin : assert_observed_deferred_immediate_stmt
            assert #0 ('sh0) begin
                $display("pass");
            end
            else begin
            end
        end
    end
    always  begin
        begin : assert_observed_deferred_immediate_stmt_else
            assert #0 ('sh0) begin
                $display("pass");
            end
            else begin
                $display("fail");
            end
        end
    end
    always  begin
        begin : assume_observed_deferred_immediate
            assume #0 ('sh0) begin
            end
            else begin
            end
        end
    end
    always  begin
        begin : assume_observed_deferred_immediate_else
            assume #0 ('sh0) begin
            end
            else begin
                $display("fail");
            end
        end
    end
    always  begin
        begin : assume_observed_deferred_immediate_stmt
            assume #0 ('sh0) begin
                $display("pass");
            end
            else begin
            end
        end
    end
    always  begin
        begin : assume_observed_deferred_immediate_stmt_else
            assume #0 ('sh0) begin
                $display("pass");
            end
            else begin
                $display("fail");
            end
        end
    end
    always  begin
        begin : assert_final_deferred_immediate
            assert final ('sh0) begin
            end
            else begin
            end
        end
    end
    always  begin
        begin : assert_final_deferred_immediate_else
            assert final ('sh0) begin
            end
            else begin
                $display("fail");
            end
        end
    end
    always  begin
        begin : assert_final_deferred_immediate_stmt
            assert final ('sh0) begin
                $display("pass");
            end
            else begin
            end
        end
    end
    always  begin
        begin : assert_final_deferred_immediate_stmt_else
            assert final ('sh0) begin
                $display("pass");
            end
            else begin
                $display("fail");
            end
        end
    end
    always  begin
        begin : assume_final_deferred_immediate
            assume final ('sh0) begin
            end
            else begin
            end
        end
    end
    always  begin
        begin : assume_final_deferred_immediate_else
            assume final ('sh0) begin
            end
            else begin
                $display("fail");
            end
        end
    end
    always  begin
        begin : assume_final_deferred_immediate_stmt
            assume final ('sh0) begin
                $display("pass");
            end
            else begin
            end
        end
    end
    always  begin
        begin : assume_final_deferred_immediate_stmt_else
            assume final ('sh0) begin
                $display("pass");
            end
            else begin
                $display("fail");
            end
        end
    end
    property prop;
    @(posedge clk) 'sh0
    endproperty
    begin : assert_concurrent
        assert property ( prop
        ) begin
        end
        else begin
        end
    end
    begin : assert_concurrent_else
        assert property ( prop
        ) begin
        end
        else begin
            $display("fail");
        end
    end
    begin : assert_concurrent_stmt
        assert property ( prop
        ) begin
            $display("pass");
        end
        else begin
        end
    end
    begin : assert_concurrent_stmt_else
        assert property ( prop
        ) begin
            $display("pass");
        end
        else begin
            $display("fail");
        end
    end
    begin : assume_concurrent
        assume property ( prop
        ) begin
        end
        else begin
        end
    end
    begin : assume_concurrent_else
        assume property ( prop
        ) begin
        end
        else begin
            $display("fail");
        end
    end
    begin : assume_concurrent_stmt
        assume property ( prop
        ) begin
            $display("pass");
        end
        else begin
        end
    end
    begin : assume_concurrent_stmt_else
        assume property ( prop
        ) begin
            $display("pass");
        end
        else begin
            $display("fail");
        end
    end
    begin : cover_concurrent
        cover property ( prop
        ) begin
        end
    end
    begin : cover_concurrent_stmt
        cover property ( prop
        ) begin
            $display("pass");
        end
    end
    int signed a;
    int signed ao;
    initial begin
        begin : assert_intrinsic
            assert ((| $_EXPRSTMT(
                        ao = (a);
                        , );
                )) begin
            end
            else begin
            end
        end
    end
    restrict (@(posedge clk) ##1 a[0]
    );
endmodule
package Vt_debug_emitv___024unit;
    class Vt_debug_emitv_Cls;
        int signed member;
        member = 'sh1;
        task method;
            if ((this != this)) begin
                $stop;
            end
        endtask
        function new;
        endfunction
    endclass
endpackage
interface Vt_debug_emitv_Iface;
    input logic clk;
    logic ifsig;
    modport mp (
        input logic ifsig
    );
endinterface
module Vt_debug_emitv_sub;
    input logic clk;
    task inc;
        input int signed i;
        output int signed o;
        o = ({32'h1{{1'h0, i[31:1]}}} + 32'h1);
    endtask
    function f;
        input int signed v;
        begin : label3
            if ((v == 'sh0)) begin
                f = 'sh21;
                disable label3;
            end
            f = ({32'h1{{31'h0, v[2]}}} + 32'h1);
            disable label3;
        end
    endfunction
    real r;
endmodule
package Vt_debug_emitv_p;
    logic pkgvar;
endpackage
package Vt_debug_emitv_Pkg;
    logic signed [31:0]  PKG_PARAM;
    typedef enum int signed{
        FOO = 32'h0,
        BAR = 32'h1,
        BAZ = 32'h2
    } enum_t;
endpackage