$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module t $end
  $var wire 1 $ p $end
  $var wire 1 % q $end
  $var wire 1 & r $end
  $var wire 32 ' vlCoverageLineTrace_t_cover_trace_always__24_block [31:0] $end
  $scope module dut $end
   $var wire 1 $ p $end
   $var wire 1 % q $end
   $var wire 1 & r $end
   $var wire 32 # vlCoverageLineTrace_t_cover_trace_always__12_block [31:0] $end
   $var wire 32 ( vlCoverageLineTrace_t_cover_trace_always__13_expr_0 [31:0] $end
   $var wire 32 ) vlCoverageLineTrace_t_cover_trace_always__13_expr_1 [31:0] $end
   $var wire 32 * vlCoverageLineTrace_t_cover_trace_always__13_expr_2 [31:0] $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
b00000000000000000000000000000001 #
1$
0%
1&
b00000000000000000000000000000000 '
b00000000000000000000000000000000 (
b00000000000000000000000000000001 )
b00000000000000000000000000000000 *
#1
b00000000000000000000000000000001 '
b00000000000000000000000000000011 )