// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//

class Cls;
  task t;
    i.super.i = 1;  // <--- BAD: cannot dot a reference to get super
  endtask
endclass