// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // Case statements that become a "decoder" (the selector is matched against a packed constant // table at runtime), followed by cases that must not be converted to one. Each output is // compared against an equivalent reference computed without a case statement, so the reference // itself is never converted. // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on module t; logic clk = 1'b0; always #5 clk = ~clk; logic [31:0] cyc = 0; // Accept A: a 31-bit (I) selector decoded into outputs of three widths (I/Q/W result). wire [30:0] accept_a_in = 31'b1 << cyc[3:0]; logic [ 5:0] accept_a_out_0, accept_a_ref_0; logic [ 55:0] accept_a_out_1, accept_a_ref_1; logic [142:0] accept_a_out_2, accept_a_ref_2; always_comb begin casez (accept_a_in) 31'b???????_????????_????????_???????1 : accept_a_out_0 = 6'd00; 31'b???????_????????_????????_??????1? : accept_a_out_0 = 6'd01; 31'b???????_????????_????????_?????1?? : accept_a_out_0 = 6'd02; 31'b???????_????????_????????_????1??? : accept_a_out_0 = 6'd03; 31'b???????_????????_????????_???1???? : accept_a_out_0 = 6'd04; 31'b???????_????????_????????_??1????? : accept_a_out_0 = 6'd05; 31'b???????_????????_????????_?1?????? : accept_a_out_0 = 6'd06; 31'b???????_????????_????????_1??????? : accept_a_out_0 = 6'd07; 31'b???????_????????_???????1_???????? : accept_a_out_0 = 6'd08; 31'b???????_????????_??????1?_???????? : accept_a_out_0 = 6'd09; 31'b???????_????????_?????1??_???????? : accept_a_out_0 = 6'd10; 31'b???????_????????_????1???_???????? : accept_a_out_0 = 6'd11; 31'b???????_????????_???1????_???????? : accept_a_out_0 = 6'd12; 31'b???????_????????_??1?????_???????? : accept_a_out_0 = 6'd13; 31'b???????_????????_?1??????_???????? : accept_a_out_0 = 6'd14; 31'b???????_????????_1???????_???????? : accept_a_out_0 = 6'd15; 31'b???????_???????1_????????_???????? : accept_a_out_0 = 6'd16; 31'b???????_??????1?_????????_???????? : accept_a_out_0 = 6'd17; 31'b???????_?????1??_????????_???????? : accept_a_out_0 = 6'd18; 31'b???????_????1???_????????_???????? : accept_a_out_0 = 6'd19; 31'b???????_???1????_????????_???????? : accept_a_out_0 = 6'd20; 31'b???????_??1?????_????????_???????? : accept_a_out_0 = 6'd21; 31'b???????_?1??????_????????_???????? : accept_a_out_0 = 6'd22; 31'b???????_1???????_????????_???????? : accept_a_out_0 = 6'd23; 31'b??????1_????????_????????_???????? : accept_a_out_0 = 6'd24; 31'b?????1?_????????_????????_???????? : accept_a_out_0 = 6'd25; 31'b????1??_????????_????????_???????? : accept_a_out_0 = 6'd26; 31'b???1???_????????_????????_???????? : accept_a_out_0 = 6'd27; 31'b??1????_????????_????????_???????? : accept_a_out_0 = 6'd28; 31'b?1?????_????????_????????_???????? : accept_a_out_0 = 6'd29; 31'b1??????_????????_????????_???????? : accept_a_out_0 = 6'd30; default: accept_a_out_0 = '1; endcase casez (accept_a_in) 31'b???????_????????_????????_???????1 : accept_a_out_1 = 56'd0000; 31'b???????_????????_????????_??????1? : accept_a_out_1 = 56'd0100; 31'b???????_????????_????????_?????1?? : accept_a_out_1 = 56'd0200; 31'b???????_????????_????????_????1??? : accept_a_out_1 = 56'd0300; 31'b???????_????????_????????_???1???? : accept_a_out_1 = 56'd0400; 31'b???????_????????_????????_??1????? : accept_a_out_1 = 56'd0500; 31'b???????_????????_????????_?1?????? : accept_a_out_1 = 56'd0600; 31'b???????_????????_????????_1??????? : accept_a_out_1 = 56'd0700; 31'b???????_????????_???????1_???????? : accept_a_out_1 = 56'd0800; 31'b???????_????????_??????1?_???????? : accept_a_out_1 = 56'd0900; 31'b???????_????????_?????1??_???????? : accept_a_out_1 = 56'd1000; 31'b???????_????????_????1???_???????? : accept_a_out_1 = 56'd1100; 31'b???????_????????_???1????_???????? : accept_a_out_1 = 56'd1200; 31'b???????_????????_??1?????_???????? : accept_a_out_1 = 56'd1300; 31'b???????_????????_?1??????_???????? : accept_a_out_1 = 56'd1400; 31'b???????_????????_1???????_???????? : accept_a_out_1 = 56'd1500; 31'b???????_???????1_????????_???????? : accept_a_out_1 = 56'd1600; 31'b???????_??????1?_????????_???????? : accept_a_out_1 = 56'd1700; 31'b???????_?????1??_????????_???????? : accept_a_out_1 = 56'd1800; 31'b???????_????1???_????????_???????? : accept_a_out_1 = 56'd1900; 31'b???????_???1????_????????_???????? : accept_a_out_1 = 56'd2000; 31'b???????_??1?????_????????_???????? : accept_a_out_1 = 56'd2100; 31'b???????_?1??????_????????_???????? : accept_a_out_1 = 56'd2200; 31'b???????_1???????_????????_???????? : accept_a_out_1 = 56'd2300; 31'b??????1_????????_????????_???????? : accept_a_out_1 = 56'd2400; 31'b?????1?_????????_????????_???????? : accept_a_out_1 = 56'd2500; 31'b????1??_????????_????????_???????? : accept_a_out_1 = 56'd2600; 31'b???1???_????????_????????_???????? : accept_a_out_1 = 56'd2700; 31'b??1????_????????_????????_???????? : accept_a_out_1 = 56'd2800; 31'b?1?????_????????_????????_???????? : accept_a_out_1 = 56'd2900; 31'b1??????_????????_????????_???????? : accept_a_out_1 = 56'd3000; default: accept_a_out_1 = '1; endcase casez (accept_a_in) 31'b???????_????????_????????_???????1 : accept_a_out_2 = 143'd0000000000; 31'b???????_????????_????????_??????1? : accept_a_out_2 = 143'd0100000000; 31'b???????_????????_????????_?????1?? : accept_a_out_2 = 143'd0200000000; 31'b???????_????????_????????_????1??? : accept_a_out_2 = 143'd0300000000; 31'b???????_????????_????????_???1???? : accept_a_out_2 = 143'd0400000000; 31'b???????_????????_????????_??1????? : accept_a_out_2 = 143'd0500000000; 31'b???????_????????_????????_?1?????? : accept_a_out_2 = 143'd0600000000; 31'b???????_????????_????????_1??????? : accept_a_out_2 = 143'd0700000000; 31'b???????_????????_???????1_???????? : accept_a_out_2 = 143'd0800000000; 31'b???????_????????_??????1?_???????? : accept_a_out_2 = 143'd0900000000; 31'b???????_????????_?????1??_???????? : accept_a_out_2 = 143'd1000000000; 31'b???????_????????_????1???_???????? : accept_a_out_2 = 143'd1100000000; 31'b???????_????????_???1????_???????? : accept_a_out_2 = 143'd1200000000; 31'b???????_????????_??1?????_???????? : accept_a_out_2 = 143'd1300000000; 31'b???????_????????_?1??????_???????? : accept_a_out_2 = 143'd1400000000; 31'b???????_????????_1???????_???????? : accept_a_out_2 = 143'd1500000000; 31'b???????_???????1_????????_???????? : accept_a_out_2 = 143'd1600000000; 31'b???????_??????1?_????????_???????? : accept_a_out_2 = 143'd1700000000; 31'b???????_?????1??_????????_???????? : accept_a_out_2 = 143'd1800000000; 31'b???????_????1???_????????_???????? : accept_a_out_2 = 143'd1900000000; 31'b???????_???1????_????????_???????? : accept_a_out_2 = 143'd2000000000; 31'b???????_??1?????_????????_???????? : accept_a_out_2 = 143'd2100000000; 31'b???????_?1??????_????????_???????? : accept_a_out_2 = 143'd2200000000; 31'b???????_1???????_????????_???????? : accept_a_out_2 = 143'd2300000000; 31'b??????1_????????_????????_???????? : accept_a_out_2 = 143'd2400000000; 31'b?????1?_????????_????????_???????? : accept_a_out_2 = 143'd2500000000; 31'b????1??_????????_????????_???????? : accept_a_out_2 = 143'd2600000000; 31'b???1???_????????_????????_???????? : accept_a_out_2 = 143'd2700000000; 31'b??1????_????????_????????_???????? : accept_a_out_2 = 143'd2800000000; 31'b?1?????_????????_????????_???????? : accept_a_out_2 = 143'd2900000000; 31'b1??????_????????_????????_???????? : accept_a_out_2 = 143'd3000000000; default: accept_a_out_2 = '1; endcase end assign accept_a_ref_0 = 6'(cyc[3:0]); assign accept_a_ref_1 = 56'(cyc[3:0]) * 56'd100; assign accept_a_ref_2 = 143'(cyc[3:0]) * 143'd100000000; // Accept B: a 40-bit (Q) selector decoded into outputs of three widths (I/Q/W result). wire [39:0] accept_b_in = 40'b1 << cyc[5:1]; logic [ 5:0] accept_b_out_0, accept_b_ref_0; logic [ 55:0] accept_b_out_1, accept_b_ref_1; logic [142:0] accept_b_out_2, accept_b_ref_2; always_comb begin casez (accept_b_in) 40'b????????_????????_????????_????????_???????1 : accept_b_out_0 = 6'd00; 40'b????????_????????_????????_????????_??????1? : accept_b_out_0 = 6'd01; 40'b????????_????????_????????_????????_?????1?? : accept_b_out_0 = 6'd02; 40'b????????_????????_????????_????????_????1??? : accept_b_out_0 = 6'd03; 40'b????????_????????_????????_????????_???1???? : accept_b_out_0 = 6'd04; 40'b????????_????????_????????_????????_??1????? : accept_b_out_0 = 6'd05; 40'b????????_????????_????????_????????_?1?????? : accept_b_out_0 = 6'd06; 40'b????????_????????_????????_????????_1??????? : accept_b_out_0 = 6'd07; 40'b????????_????????_????????_???????1_???????? : accept_b_out_0 = 6'd08; 40'b????????_????????_????????_??????1?_???????? : accept_b_out_0 = 6'd09; 40'b????????_????????_????????_?????1??_???????? : accept_b_out_0 = 6'd10; 40'b????????_????????_????????_????1???_???????? : accept_b_out_0 = 6'd11; 40'b????????_????????_????????_???1????_???????? : accept_b_out_0 = 6'd12; 40'b????????_????????_????????_??1?????_???????? : accept_b_out_0 = 6'd13; 40'b????????_????????_????????_?1??????_???????? : accept_b_out_0 = 6'd14; 40'b????????_????????_????????_1???????_???????? : accept_b_out_0 = 6'd15; 40'b????????_????????_???????1_????????_???????? : accept_b_out_0 = 6'd16; 40'b????????_????????_??????1?_????????_???????? : accept_b_out_0 = 6'd17; 40'b????????_????????_?????1??_????????_???????? : accept_b_out_0 = 6'd18; 40'b????????_????????_????1???_????????_???????? : accept_b_out_0 = 6'd19; 40'b????????_????????_???1????_????????_???????? : accept_b_out_0 = 6'd20; 40'b????????_????????_??1?????_????????_???????? : accept_b_out_0 = 6'd21; 40'b????????_????????_?1??????_????????_???????? : accept_b_out_0 = 6'd22; 40'b????????_????????_1???????_????????_???????? : accept_b_out_0 = 6'd23; 40'b????????_???????1_????????_????????_???????? : accept_b_out_0 = 6'd24; 40'b????????_??????1?_????????_????????_???????? : accept_b_out_0 = 6'd25; 40'b????????_?????1??_????????_????????_???????? : accept_b_out_0 = 6'd26; 40'b????????_????1???_????????_????????_???????? : accept_b_out_0 = 6'd27; 40'b????????_???1????_????????_????????_???????? : accept_b_out_0 = 6'd28; 40'b????????_??1?????_????????_????????_???????? : accept_b_out_0 = 6'd29; 40'b????????_?1??????_????????_????????_???????? : accept_b_out_0 = 6'd30; 40'b????????_1???????_????????_????????_???????? : accept_b_out_0 = 6'd31; 40'b???????1_????????_????????_????????_???????? : accept_b_out_0 = 6'd32; 40'b??????1?_????????_????????_????????_???????? : accept_b_out_0 = 6'd33; 40'b?????1??_????????_????????_????????_???????? : accept_b_out_0 = 6'd34; 40'b????1???_????????_????????_????????_???????? : accept_b_out_0 = 6'd35; 40'b???1????_????????_????????_????????_???????? : accept_b_out_0 = 6'd36; 40'b??1?????_????????_????????_????????_???????? : accept_b_out_0 = 6'd37; 40'b?1??????_????????_????????_????????_???????? : accept_b_out_0 = 6'd38; 40'b1???????_????????_????????_????????_???????? : accept_b_out_0 = 6'd39; default: accept_b_out_0 = '1; endcase casez (accept_b_in) 40'b????????_????????_????????_????????_???????1 : accept_b_out_1 = 56'd0000; 40'b????????_????????_????????_????????_??????1? : accept_b_out_1 = 56'd0100; 40'b????????_????????_????????_????????_?????1?? : accept_b_out_1 = 56'd0200; 40'b????????_????????_????????_????????_????1??? : accept_b_out_1 = 56'd0300; 40'b????????_????????_????????_????????_???1???? : accept_b_out_1 = 56'd0400; 40'b????????_????????_????????_????????_??1????? : accept_b_out_1 = 56'd0500; 40'b????????_????????_????????_????????_?1?????? : accept_b_out_1 = 56'd0600; 40'b????????_????????_????????_????????_1??????? : accept_b_out_1 = 56'd0700; 40'b????????_????????_????????_???????1_???????? : accept_b_out_1 = 56'd0800; 40'b????????_????????_????????_??????1?_???????? : accept_b_out_1 = 56'd0900; 40'b????????_????????_????????_?????1??_???????? : accept_b_out_1 = 56'd1000; 40'b????????_????????_????????_????1???_???????? : accept_b_out_1 = 56'd1100; 40'b????????_????????_????????_???1????_???????? : accept_b_out_1 = 56'd1200; 40'b????????_????????_????????_??1?????_???????? : accept_b_out_1 = 56'd1300; 40'b????????_????????_????????_?1??????_???????? : accept_b_out_1 = 56'd1400; 40'b????????_????????_????????_1???????_???????? : accept_b_out_1 = 56'd1500; 40'b????????_????????_???????1_????????_???????? : accept_b_out_1 = 56'd1600; 40'b????????_????????_??????1?_????????_???????? : accept_b_out_1 = 56'd1700; 40'b????????_????????_?????1??_????????_???????? : accept_b_out_1 = 56'd1800; 40'b????????_????????_????1???_????????_???????? : accept_b_out_1 = 56'd1900; 40'b????????_????????_???1????_????????_???????? : accept_b_out_1 = 56'd2000; 40'b????????_????????_??1?????_????????_???????? : accept_b_out_1 = 56'd2100; 40'b????????_????????_?1??????_????????_???????? : accept_b_out_1 = 56'd2200; 40'b????????_????????_1???????_????????_???????? : accept_b_out_1 = 56'd2300; 40'b????????_???????1_????????_????????_???????? : accept_b_out_1 = 56'd2400; 40'b????????_??????1?_????????_????????_???????? : accept_b_out_1 = 56'd2500; 40'b????????_?????1??_????????_????????_???????? : accept_b_out_1 = 56'd2600; 40'b????????_????1???_????????_????????_???????? : accept_b_out_1 = 56'd2700; 40'b????????_???1????_????????_????????_???????? : accept_b_out_1 = 56'd2800; 40'b????????_??1?????_????????_????????_???????? : accept_b_out_1 = 56'd2900; 40'b????????_?1??????_????????_????????_???????? : accept_b_out_1 = 56'd3000; 40'b????????_1???????_????????_????????_???????? : accept_b_out_1 = 56'd3100; 40'b???????1_????????_????????_????????_???????? : accept_b_out_1 = 56'd3200; 40'b??????1?_????????_????????_????????_???????? : accept_b_out_1 = 56'd3300; 40'b?????1??_????????_????????_????????_???????? : accept_b_out_1 = 56'd3400; 40'b????1???_????????_????????_????????_???????? : accept_b_out_1 = 56'd3500; 40'b???1????_????????_????????_????????_???????? : accept_b_out_1 = 56'd3600; 40'b??1?????_????????_????????_????????_???????? : accept_b_out_1 = 56'd3700; 40'b?1??????_????????_????????_????????_???????? : accept_b_out_1 = 56'd3800; 40'b1???????_????????_????????_????????_???????? : accept_b_out_1 = 56'd3900; default: accept_b_out_1 = '1; endcase casez (accept_b_in) 40'b????????_????????_????????_????????_???????1 : accept_b_out_2 = 143'd0000000000; 40'b????????_????????_????????_????????_??????1? : accept_b_out_2 = 143'd0100000000; 40'b????????_????????_????????_????????_?????1?? : accept_b_out_2 = 143'd0200000000; 40'b????????_????????_????????_????????_????1??? : accept_b_out_2 = 143'd0300000000; 40'b????????_????????_????????_????????_???1???? : accept_b_out_2 = 143'd0400000000; 40'b????????_????????_????????_????????_??1????? : accept_b_out_2 = 143'd0500000000; 40'b????????_????????_????????_????????_?1?????? : accept_b_out_2 = 143'd0600000000; 40'b????????_????????_????????_????????_1??????? : accept_b_out_2 = 143'd0700000000; 40'b????????_????????_????????_???????1_???????? : accept_b_out_2 = 143'd0800000000; 40'b????????_????????_????????_??????1?_???????? : accept_b_out_2 = 143'd0900000000; 40'b????????_????????_????????_?????1??_???????? : accept_b_out_2 = 143'd1000000000; 40'b????????_????????_????????_????1???_???????? : accept_b_out_2 = 143'd1100000000; 40'b????????_????????_????????_???1????_???????? : accept_b_out_2 = 143'd1200000000; 40'b????????_????????_????????_??1?????_???????? : accept_b_out_2 = 143'd1300000000; 40'b????????_????????_????????_?1??????_???????? : accept_b_out_2 = 143'd1400000000; 40'b????????_????????_????????_1???????_???????? : accept_b_out_2 = 143'd1500000000; 40'b????????_????????_???????1_????????_???????? : accept_b_out_2 = 143'd1600000000; 40'b????????_????????_??????1?_????????_???????? : accept_b_out_2 = 143'd1700000000; 40'b????????_????????_?????1??_????????_???????? : accept_b_out_2 = 143'd1800000000; 40'b????????_????????_????1???_????????_???????? : accept_b_out_2 = 143'd1900000000; 40'b????????_????????_???1????_????????_???????? : accept_b_out_2 = 143'd2000000000; 40'b????????_????????_??1?????_????????_???????? : accept_b_out_2 = 143'd2100000000; 40'b????????_????????_?1??????_????????_???????? : accept_b_out_2 = 143'd2200000000; 40'b????????_????????_1???????_????????_???????? : accept_b_out_2 = 143'd2300000000; 40'b????????_???????1_????????_????????_???????? : accept_b_out_2 = 143'd2400000000; 40'b????????_??????1?_????????_????????_???????? : accept_b_out_2 = 143'd2500000000; 40'b????????_?????1??_????????_????????_???????? : accept_b_out_2 = 143'd2600000000; 40'b????????_????1???_????????_????????_???????? : accept_b_out_2 = 143'd2700000000; 40'b????????_???1????_????????_????????_???????? : accept_b_out_2 = 143'd2800000000; 40'b????????_??1?????_????????_????????_???????? : accept_b_out_2 = 143'd2900000000; 40'b????????_?1??????_????????_????????_???????? : accept_b_out_2 = 143'd3000000000; 40'b????????_1???????_????????_????????_???????? : accept_b_out_2 = 143'd3100000000; 40'b???????1_????????_????????_????????_???????? : accept_b_out_2 = 143'd3200000000; 40'b??????1?_????????_????????_????????_???????? : accept_b_out_2 = 143'd3300000000; 40'b?????1??_????????_????????_????????_???????? : accept_b_out_2 = 143'd3400000000; 40'b????1???_????????_????????_????????_???????? : accept_b_out_2 = 143'd3500000000; 40'b???1????_????????_????????_????????_???????? : accept_b_out_2 = 143'd3600000000; 40'b??1?????_????????_????????_????????_???????? : accept_b_out_2 = 143'd3700000000; 40'b?1??????_????????_????????_????????_???????? : accept_b_out_2 = 143'd3800000000; 40'b1???????_????????_????????_????????_???????? : accept_b_out_2 = 143'd3900000000; default: accept_b_out_2 = '1; endcase end assign accept_b_ref_0 = 6'(cyc[5:1]); assign accept_b_ref_1 = 56'(cyc[5:1]) * 56'd100; assign accept_b_ref_2 = 143'(cyc[5:1]) * 143'd100000000; // Accept C: a 155-bit (W) selector decoded into outputs of three widths (I/Q/W result). wire [154:0] accept_c_in = 155'b1 << cyc[5:0]; logic [ 5:0] accept_c_out_0, accept_c_ref_0; logic [ 55:0] accept_c_out_1, accept_c_ref_1; logic [142:0] accept_c_out_2, accept_c_ref_2; always_comb begin casez (accept_c_in) 155'b????????_????????_????????_????????_???????1 : accept_c_out_0 = 6'd00; 155'b????????_????????_????????_????????_??????1? : accept_c_out_0 = 6'd01; 155'b????????_????????_????????_????????_?????1?? : accept_c_out_0 = 6'd02; 155'b????????_????????_????????_????????_????1??? : accept_c_out_0 = 6'd03; 155'b????????_????????_????????_????????_???1???? : accept_c_out_0 = 6'd04; 155'b????????_????????_????????_????????_??1????? : accept_c_out_0 = 6'd05; 155'b????????_????????_????????_????????_?1?????? : accept_c_out_0 = 6'd06; 155'b????????_????????_????????_????????_1??????? : accept_c_out_0 = 6'd07; 155'b????????_????????_????????_???????1_???????? : accept_c_out_0 = 6'd08; 155'b????????_????????_????????_??????1?_???????? : accept_c_out_0 = 6'd09; 155'b????????_????????_????????_?????1??_???????? : accept_c_out_0 = 6'd10; default: accept_c_out_0 = '1; endcase casez (accept_c_in) 155'b????????_????????_????????_????????_???????1 : accept_c_out_1 = 56'd0000; 155'b????????_????????_????????_????????_??????1? : accept_c_out_1 = 56'd0100; 155'b????????_????????_????????_????????_?????1?? : accept_c_out_1 = 56'd0200; 155'b????????_????????_????????_????????_????1??? : accept_c_out_1 = 56'd0300; 155'b????????_????????_????????_????????_???1???? : accept_c_out_1 = 56'd0400; 155'b????????_????????_????????_????????_??1????? : accept_c_out_1 = 56'd0500; 155'b????????_????????_????????_????????_?1?????? : accept_c_out_1 = 56'd0600; 155'b????????_????????_????????_????????_1??????? : accept_c_out_1 = 56'd0700; 155'b????????_????????_????????_???????1_???????? : accept_c_out_1 = 56'd0800; 155'b????????_????????_????????_??????1?_???????? : accept_c_out_1 = 56'd0900; 155'b????????_????????_????????_?????1??_???????? : accept_c_out_1 = 56'd1000; default: accept_c_out_1 = '1; endcase casez (accept_c_in) 155'b????????_????????_????????_????????_???????1 : accept_c_out_2 = 143'd0000000000; 155'b????????_????????_????????_????????_??????1? : accept_c_out_2 = 143'd0100000000; 155'b????????_????????_????????_????????_?????1?? : accept_c_out_2 = 143'd0200000000; 155'b????????_????????_????????_????????_????1??? : accept_c_out_2 = 143'd0300000000; 155'b????????_????????_????????_????????_???1???? : accept_c_out_2 = 143'd0400000000; 155'b????????_????????_????????_????????_??1????? : accept_c_out_2 = 143'd0500000000; 155'b????????_????????_????????_????????_?1?????? : accept_c_out_2 = 143'd0600000000; 155'b????????_????????_????????_????????_1??????? : accept_c_out_2 = 143'd0700000000; 155'b????????_????????_????????_???????1_???????? : accept_c_out_2 = 143'd0800000000; 155'b????????_????????_????????_??????1?_???????? : accept_c_out_2 = 143'd0900000000; 155'b????????_????????_????????_?????1??_???????? : accept_c_out_2 = 143'd1000000000; default: accept_c_out_2 = '1; endcase end assign accept_c_ref_0 = cyc[5:0] <= 6'd10 ? 6'(cyc[5:0]) : ~6'd0; assign accept_c_ref_1 = cyc[5:0] <= 6'd10 ? 56'(cyc[5:0]) * 56'd100 : ~56'd0; assign accept_c_ref_2 = cyc[5:0] <= 6'd10 ? 143'(cyc[5:0]) * 143'd100000000 : ~143'd0; // Accept D: the default value is set before the case, with no default item. wire [39:0] accept_d_in = 40'b1 << cyc[4:0]; logic [4:0] accept_d_out, accept_d_ref; always_comb begin accept_d_out = '1; casez (accept_d_in) 40'b????????_????????_????????_????????_???????1 : accept_d_out = 5'd0; 40'b????????_????????_????????_????????_??????1? : accept_d_out = 5'd1; 40'b????????_????????_????????_????????_?????1?? : accept_d_out = 5'd2; 40'b????????_????????_????????_????????_????1??? : accept_d_out = 5'd3; endcase end assign accept_d_ref = cyc[4:0] <= 5'd3 ? 5'(cyc[4:0]) : 5'h1f; // Accept E: an empty default item. wire [39:0] accept_e_in = 40'b1 << cyc[4:0]; logic [4:0] accept_e_out, accept_e_ref; always_comb begin accept_e_out = '1; casez (accept_e_in) 40'b????????_????????_????????_????????_???????1 : accept_e_out = 5'd0; 40'b????????_????????_????????_????????_??????1? : accept_e_out = 5'd1; 40'b????????_????????_????????_????????_?????1?? : accept_e_out = 5'd2; 40'b????????_????????_????????_????????_????1??? : accept_e_out = 5'd3; default: begin end endcase end assign accept_e_ref = cyc[4:0] <= 5'd3 ? 5'(cyc[4:0]) : 5'h1f; // Accept F: an item with an empty body (output keeps its pre-case default). wire [39:0] accept_f_in = 40'b1 << cyc[4:0]; logic [4:0] accept_f_out, accept_f_ref; always_comb begin accept_f_out = '1; casez (accept_f_in) 40'b????????_????????_????????_????????_???1???? : begin end 40'b????????_????????_????????_????????_???????1 : accept_f_out = 5'd0; 40'b????????_????????_????????_????????_??????1? : accept_f_out = 5'd1; 40'b????????_????????_????????_????????_?????1?? : accept_f_out = 5'd2; 40'b????????_????????_????????_????????_????1??? : accept_f_out = 5'd3; default: begin end endcase end assign accept_f_ref = cyc[4:0] <= 5'd3 ? 5'(cyc[4:0]) : 5'h1f; // Accept G: non-blocking assignments. wire [23:0] accept_g_in = 24'b1 << cyc[4:0]; logic [5:0] accept_g_out, accept_g_ref; always_ff @(posedge clk) begin accept_g_out <= '1; casez (accept_g_in) 24'b????????_????????_???????1 : accept_g_out <= 6'd0; 24'b????????_????????_??????1? : accept_g_out <= 6'd1; 24'b????????_????????_?????1?? : accept_g_out <= 6'd2; 24'b????????_????????_????1??? : accept_g_out <= 6'd3; endcase end always_ff @(posedge clk) accept_g_ref <= cyc[4:0] == 5'd0 ? 6'd0 : cyc[4:0] == 5'd1 ? 6'd1 : cyc[4:0] == 5'd2 ? 6'd2 : cyc[4:0] == 5'd3 ? 6'd3 : ~6'd0; // Accept H: multiple outputs from one decoder, some items assigning only a subset. wire [23:0] accept_h_in = 24'b1 << cyc[4:0]; logic [ 5:0] accept_h_out_0, accept_h_ref_0; logic [11:0] accept_h_out_1, accept_h_ref_1; always_comb begin accept_h_out_0 = '1; accept_h_out_1 = '1; casez (accept_h_in) 24'b????????_????????_???????1 : begin accept_h_out_0 = 6'd0; accept_h_out_1 = 12'h001; end 24'b????????_????????_??????1? : accept_h_out_0 = 6'd1; 24'b????????_????????_?????1?? : accept_h_out_1 = 12'h004; 24'b????????_????????_????1??? : begin accept_h_out_0 = 6'd3; accept_h_out_1 = 12'h008; end endcase end assign accept_h_ref_0 = cyc[4:0] == 5'd0 ? 6'd0 : cyc[4:0] == 5'd1 ? 6'd1 : cyc[4:0] == 5'd3 ? 6'd3 : ~6'd0; assign accept_h_ref_1 = cyc[4:0] == 5'd0 ? 12'h001 : cyc[4:0] == 5'd2 ? 12'h004 : cyc[4:0] == 5'd3 ? 12'h008 : ~12'd0; // Accept I: multiple outputs from one decoder, non-blocking assignments. wire [23:0] accept_i_in = 24'b1 << cyc[4:0]; logic [ 5:0] accept_i_out_0, accept_i_ref_0; logic [11:0] accept_i_out_1, accept_i_ref_1; always_ff @(posedge clk) begin accept_i_out_0 <= '1; accept_i_out_1 <= '1; casez (accept_i_in) 24'b????????_????????_???????1 : begin accept_i_out_0 <= 6'd0; accept_i_out_1 <= 12'h001; end 24'b????????_????????_??????1? : begin accept_i_out_0 <= 6'd1; accept_i_out_1 <= 12'h002; end 24'b????????_????????_?????1?? : begin accept_i_out_0 <= 6'd2; accept_i_out_1 <= 12'h004; end 24'b????????_????????_????1??? : begin accept_i_out_0 <= 6'd3; accept_i_out_1 <= 12'h008; end endcase end always_ff @(posedge clk) begin accept_i_ref_0 <= cyc[4:0] == 5'd0 ? 6'd0 : cyc[4:0] == 5'd1 ? 6'd1 : cyc[4:0] == 5'd2 ? 6'd2 : cyc[4:0] == 5'd3 ? 6'd3 : ~6'd0; accept_i_ref_1 <= cyc[4:0] == 5'd0 ? 12'h001 : cyc[4:0] == 5'd1 ? 12'h002 : cyc[4:0] == 5'd2 ? 12'h004 : cyc[4:0] == 5'd3 ? 12'h008 : ~12'd0; end // Accept J: an item that can never match in 2-state (an X in casez) is skipped. // verilator lint_off CASEWITHX wire [23:0] accept_j_in = 24'b1 << cyc[4:0]; logic [5:0] accept_j_out, accept_j_ref; always_comb begin accept_j_out = '1; casez (accept_j_in) 24'b????????_????????_???????x : accept_j_out = 6'd9; // X never matches in 2-state, skipped 24'b????????_????????_??????1? : accept_j_out = 6'd1; 24'b????????_????????_?????1?? : accept_j_out = 6'd2; 24'b????????_????????_????1??? : accept_j_out = 6'd3; endcase end // verilator lint_on CASEWITHX assign accept_j_ref = cyc[4:0] == 5'd1 ? 6'd1 : cyc[4:0] == 5'd2 ? 6'd2 : cyc[4:0] == 5'd3 ? 6'd3 : ~6'd0; // Accept K: Will constant fold after converting to decoder wire [23:0] accept_k_in; logic [5:0] accept_k_out, accept_k_ref; always_ff @(posedge clk) begin accept_k_out <= '1; casez (accept_k_in) 24'b????????_????????_???????1 : accept_k_out <= 6'd0; 24'b????????_????????_??????1? : accept_k_out <= 6'd1; 24'b????????_????????_?????1?? : accept_k_out <= 6'd2; 24'b????????_????????_????1??? : accept_k_out <= 6'd3; endcase end always_ff @(posedge clk) accept_k_ref <= 6'd2; assign accept_k_in = 24'b100; // The cases below are intentionally NOT converted to a decoder. // Reject A: too few conditions to be worth the indexed load. wire [23:0] reject_a_in = 24'b1 << cyc[4:0]; logic [5:0] reject_a_out, reject_a_ref; always_comb begin reject_a_out = '1; casez (reject_a_in) 24'b????????_????????_???????1 : reject_a_out = 6'd0; 24'b????????_????????_??????1? : reject_a_out = 6'd1; endcase end assign reject_a_ref = cyc[4:0] == 5'd0 ? 6'd0 : cyc[4:0] == 5'd1 ? 6'd1 : ~6'd0; // Reject B: every condition contains an X, so none can ever match in 2-state. The case has no // matchable branches, so it must not be treated as a decoder - it just keeps the // pre-case default. // verilator lint_off CASEWITHX wire [23:0] reject_b_in = 24'b1 << cyc[4:0]; logic [5:0] reject_b_out, reject_b_ref; always_comb begin reject_b_out = 6'h2a; casez (reject_b_in) 24'b????????_????????_???????x : reject_b_out = 6'd0; 24'b????????_????????_??????x? : reject_b_out = 6'd1; 24'b????????_????????_?????x?? : reject_b_out = 6'd2; endcase end // verilator lint_on CASEWITHX assign reject_b_ref = 6'h2a; // No condition can ever match, so always the pre-default // Test driver/checker always @(posedge clk) begin `checkh(accept_a_out_0, accept_a_ref_0); `checkh(accept_a_out_1, accept_a_ref_1); `checkh(accept_a_out_2, accept_a_ref_2); `checkh(accept_b_out_0, accept_b_ref_0); `checkh(accept_b_out_1, accept_b_ref_1); `checkh(accept_b_out_2, accept_b_ref_2); `checkh(accept_c_out_0, accept_c_ref_0); `checkh(accept_c_out_1, accept_c_ref_1); `checkh(accept_c_out_2, accept_c_ref_2); `checkh(accept_d_out, accept_d_ref); `checkh(accept_e_out, accept_e_ref); `checkh(accept_f_out, accept_f_ref); `checkh(accept_g_out, accept_g_ref); `checkh(accept_h_out_0, accept_h_ref_0); `checkh(accept_h_out_1, accept_h_ref_1); `checkh(accept_i_out_0, accept_i_ref_0); `checkh(accept_i_out_1, accept_i_ref_1); `checkh(accept_j_out, accept_j_ref); `checkh(accept_k_out, accept_k_ref); `checkh(reject_a_out, reject_a_ref); `checkh(reject_b_out, reject_b_ref); cyc <= cyc + 32'd1; if (cyc[16]) begin $write("*-* All Finished *-*\n"); $finish; end end endmodule