$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module top $end
  $var wire 1 " i_clk $end
  $var wire 3 # i_d [2:0] $end
  $var wire 3 $ o_q [2:0] $end
  $scope module my_module_types $end
   $var wire 32 % MY_PARAM [31:0] $end
   $var wire 32 & MY_PARAM2 [31:0] $end
  $upscope $end
  $scope module t $end
   $var wire 1 " i_clk $end
   $var wire 3 # i_d [2:0] $end
   $var wire 3 $ o_q [2:0] $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
0"
b000 #
b000 $
b00000000000000000000000000000011 %
b00000000000000000000000000001100 &