$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module top $end
  $var wire 1 " clk $end
  $scope module $unit $end
  $upscope $end
  $scope module t $end
   $var wire 1 " clk $end
   $var wire 2 # v_enumed [1:0] $end
   $var wire 2 $ v_other_enumed [1:0] $end
   $scope module sink $end
    $var wire 2 % state [1:0] $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
0"
b00 #
b00 $
b00 %
#10
1"