$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module top $end
  $scope module t $end
   $var wire 1 ' clk $end
   $var wire 5 " state [4:0] $end
   $var wire 1 , fst_inout $end
   $var wire 32 ( cyc [31:0] $end
   $var wire 1 ) rstn $end
   $var real 64 - fst_gparam_real $end
   $var real 64 / fst_lparam_real $end
   $var real 64 - fst_real $end
   $var wire 32 1 fst_integer [31:0] $end
   $var wire 1 2 fst_bit $end
   $var wire 1 3 fst_logic $end
   $var wire 32 4 fst_int [31:0] $end
   $var wire 16 5 fst_shortint [15:0] $end
   $var wire 64 6 fst_longint [63:0] $end
   $var wire 8 8 fst_byte [7:0] $end
   $var wire 64 * fst_time [63:0] $end
   $var wire 32 9 fst_parameter [31:0] $end
   $var wire 32 : fst_lparam [31:0] $end
   $var wire 1 ; fst_supply0 $end
   $var wire 1 < fst_supply1 $end
   $var wire 1 ; fst_tri0 $end
   $var wire 1 < fst_tri1 $end
   $var wire 1 = fst_tri $end
   $var wire 1 > fst_triand $end
   $var wire 1 ? fst_trior $end
   $var wire 1 @ fst_wand $end
   $var wire 1 A fst_wor $end
   $var wire 1 B fst_wire $end
   $var wire 1 C fst_uwire $end
   $scope module test $end
    $var wire 1 ' clk $end
    $var wire 1 ) rstn $end
    $var wire 5 " state [4:0] $end
    $var wire 5 # state_w [4:0] $end
    $var wire 5 $ state_array[0] [4:0] $end
    $var wire 5 % state_array[1] [4:0] $end
    $var wire 5 & state_array[2] [4:0] $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


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