// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2003 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0

module t;

  initial begin
    fork : fblk
      begin
        $write("Forked");
      end
      begin
        $write("*-* All Finished *-*\n");
        $finish;
      end
    join : fblk
  end

endmodule