// -*- Verilog -*-
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2025 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0

//    lib.map file:
include ./t_config_libmap/lib.map;

library rtllib1 somepath -incdir somedir;
library rtllib2 somewild*;
library rtllib3 someexplicit;