$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module top $end
  $var wire 1 - clk $end
  $var wire 1 . clk2 $end
  $scope module $unit $end
   $var wire 1 2 global_bit $end
  $upscope $end
  $scope module t $end
   $var wire 1 - clk $end
   $var wire 1 . clk2 $end
   $var wire 32 / cyc [31:0] $end
   $scope module v_strp $end
    $var wire 1 0 b1 $end
    $var wire 1 " b0 $end
   $upscope $end
   $scope module v_strp2 $end
    $var wire 1 1 b1 $end
    $var wire 1 # b0 $end
   $upscope $end
   $var wire 1 $ foo $end
   $var wire 8 % unpacked_array[-7] [7:0] $end
   $var wire 8 & unpacked_array[-6] [7:0] $end
   $var wire 8 ' unpacked_array[-5] [7:0] $end
   $var wire 8 ( unpacked_array[-4] [7:0] $end
   $var wire 8 ) unpacked_array[-3] [7:0] $end
   $var wire 8 * unpacked_array[-2] [7:0] $end
   $var wire 8 + unpacked_array[-1] [7:0] $end
   $var wire 8 , unpacked_array[0] [7:0] $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
0"
0#
0$
b00000000 %
b00000000 &
b00000000 '
b00000000 (
b00000000 )
b00000000 *
b00000000 +
b00000000 ,
0-
0.
b00000000000000000000000000000000 /
00
01
02
#10
1$
1-
b00000000000000000000000000000001 /
#15
0-
#20
1"
0$
1-
b00000000000000000000000000000010 /
#25
0-
#30
0"
1$
b00000001 ,
1-
b00000000000000000000000000000011 /
#35
0-
#40
1"
0$
1-
b00000000000000000000000000000100 /
#45
0-
#50
0"
1#
1$
b00000010 ,
1-
b00000000000000000000000000000101 /
#55
0-
#60
1"
0$
1-
b00000000000000000000000000000110 /