#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

import vltest_bootstrap

test.scenarios('simulator')
test.top_filename = "t/t_instrumentation.v"

sim_filename = "t/" + test.name + ".cpp"
dpi_filename = "t/t_instrumentationDPI.cpp"
vlt_filename = "t/" + test.name + ".vlt"
log_filename = "obj_vlt/t_instrumentation/simulation_output.log"

test.compile(make_top_shell=False,
             make_main=False,
             v_flags2=["--trace --exe --instrument", sim_filename, vlt_filename, dpi_filename])
test.execute()

test.files_identical(log_filename, test.golden_filename)

test.passes()