// DESCRIPTION: Verilator: Verilog Test module
//
// Test automatic bins: bins auto[N]
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2026 by Wilson Snyder.
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0

// verilog_format: off
`define stop $stop
`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on

module t;
  logic [2:0] data;  // 3-bit: 0-7
  logic [3:0] data4;  // 4-bit signal
  logic [63:0] data64;  // 64-bit signal

  covergroup cg;
    coverpoint data {
      bins auto[4];  // Should create 4 bins: [0:1], [2:3], [4:5], [6:7]
    }
  endgroup

  // 4-bit signal with auto[4]: creates 4 equal-width bins covering [0:15]
  covergroup cg_4bit;
    coverpoint data4 {
      bins auto[4];  // Creates 4 bins: [0:3], [4:7], [8:11], [12:15]
    }
  endgroup

  // 4-bit auto bins with one value excluded by ignore_bins
  covergroup cg_4bit_excl;
    coverpoint data4 {
      ignore_bins bad = {0};  // value 0 excluded from auto expansion
      bins auto[4];
    }
  endgroup

  // 64-bit signal with auto_bin_max=2: creates 2 bins covering the full 64-bit range
  covergroup cg2;
    option.auto_bin_max = 2;
    coverpoint data64;
  endgroup

  initial begin
    automatic cg cg_inst = new;
    automatic cg_4bit cg4_inst = new;
    automatic cg_4bit_excl cg4e_inst = new;
    automatic cg2 cg2_inst = new;

    // Sample 3-bit cg: one value per bin - 4 bins: [0:1],[2:3],[4:5],[6:7]
    data = 0; cg_inst.sample();
    `checkr(cg_inst.get_inst_coverage(), 25.0);
    data = 2; cg_inst.sample();
    `checkr(cg_inst.get_inst_coverage(), 50.0);
    data = 5; cg_inst.sample();
    `checkr(cg_inst.get_inst_coverage(), 75.0);
    data = 7; cg_inst.sample();
    `checkr(cg_inst.get_inst_coverage(), 100.0);

    // Sample 4-bit bins - 4 bins: [0:3],[4:7],[8:11],[12:15]
    data4 = 0;
    cg4_inst.sample();  // bin [0:3]
    `checkr(cg4_inst.get_inst_coverage(), 25.0);
    data4 = 7;
    cg4_inst.sample();  // bin [4:7]
    `checkr(cg4_inst.get_inst_coverage(), 50.0);
    data4 = 10;
    cg4_inst.sample();  // bin [8:11]
    `checkr(cg4_inst.get_inst_coverage(), 75.0);
    data4 = 14;
    cg4_inst.sample();  // bin [12:15]
    `checkr(cg4_inst.get_inst_coverage(), 100.0);

    // Sample 4-bit with exclusion (value 0 excluded; 4 auto bins for remaining values)
    data4 = 1;
    cg4e_inst.sample();
    `checkr(cg4e_inst.get_inst_coverage(), 25.0);
    data4 = 8;
    cg4e_inst.sample();
    `checkr(cg4e_inst.get_inst_coverage(), 50.0);

    // Sample 64-bit cg2 - SKIP checkr: Verilator 64-bit bin boundary bug causes 100% at first sample
    data64 = 64'd0;
    cg2_inst.sample();
    data64 = 64'hFFFF_FFFF_FFFF_FFFF;
    cg2_inst.sample();

    $write("*-* All Finished *-*\n");
    $finish;
  end
endmodule