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2 Commits

Author SHA1 Message Date
Geza Lore 86c56e8e14 Fix true cycle detection in DFG 2025-08-05 15:04:07 +01:00
Geza Lore ce77bac99a
Break some combinational cycles in DFG (#6168) 
Added an algorithm that can break some combinational cycles in DFG, by
attempting to trace driver logic until we escape the cycle. This can
eliminate a decent portion of UNOPTFLAT warnings. E.g. due to this code:

```systemverilog
assign a[0] = .....;
assign a[1] = ~a[0];
```
 2025-07-10 18:46:45 +01:00