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12 Commits

Author SHA1 Message Date
Geza Lore ce03293128 Generate AstNode accessors via astgen 
Introduce the @astgen directives parsed by astgen, currently used for
the generation child node (operand) accessors. Please see the updated
internal documentation for details.
 2022-09-21 13:56:03 +01:00
Geza Lore 7d88e63bab astgen: generate type specific addNext, remove astNextNull 
Generate type specific static overloads of Ast<Node>::addNext, which
return the correct sub-type of the 'this' they were invoked on.

Also remove AstNode::addNextNull, which is now only used in the parser,
implement in verilog.y directly as a template function.
 2022-09-17 15:05:22 +01:00
Geza Lore 0c70a0dcbf Remove redundant 'virtual' keywords from overridden methods 
'virtual' is redundant when 'override' is present, so keep only
'override'.

Add t/t_dist_cppstyle.pl to check for this.
 2022-09-16 15:19:38 +01:00
Geza Lore 2ba39b25f1 Replace dynamic_casts with static_casts 
dynamic_cast is not free. Replace obvious instances (where the result is
unconditionally dereferenced) with static_cast in contexts with
performance implications.
 2022-09-02 12:08:34 +01:00
Wilson Snyder c335aad25f Fix --hierarchical with order-based pin connections (#3583). 2022-08-29 22:49:19 -04:00
Geza Lore 96a4b3e5a5 Update clang-format config and apply 
- Regroup and sort #include directives (like we used to, but automatic)
- Set AlwaysBreakTemplateDeclarations to true
 2022-08-05 12:00:24 +01:00
Wilson Snyder b9d7819faa Internals: Fix some cppcheck issues. Some dump functions fixed. 2022-07-30 10:01:39 -04:00
Wilson Snyder e6857df5c6 Internals: Rename Ast on non-node classes (#3262). No functional change. 
This commit has the following replacements applied:

	s/\bAstUserInUseBase\b/VNUserInUseBase/g;
        s/\bAstAttrType\b/VAttrType/g;
        s/\bAstBasicDTypeKwd\b/VBasicDTypeKwd/g;
        s/\bAstDisplayType\b/VDisplayType/g;
        s/\bAstNDeleter\b/VNDeleter/g;
        s/\bAstNRelinker\b/VNRelinker/g;
        s/\bAstNVisitor\b/VNVisitor/g;
        s/\bAstPragmaType\b/VPragmaType/g;
        s/\bAstType\b/VNType/g;
        s/\bAstUser1InUse\b/VNUser1InUse/g;
        s/\bAstUser2InUse\b/VNUser2InUse/g;
        s/\bAstUser3InUse\b/VNUser3InUse/g;
        s/\bAstUser4InUse\b/VNUser4InUse/g;
        s/\bAstUser5InUse\b/VNUser5InUse/g;
        s/\bAstVarType\b/VVarType/g;
 2022-01-02 14:03:20 -05:00
Wilson Snyder ca42be982c Copyright year update. 2022-01-01 08:26:40 -05:00
Wilson Snyder 05e12ab60e Internals: More const. No functional change intended. 2021-11-26 10:52:45 -05:00
Geza Lore dae9fa5053 Use VN_AS wherever possible and obvious. No functional change. 2021-10-22 14:06:00 +01:00
Geza Lore 17cc452f79 Add V3VariableOrder pass 
A separate V3VariableOrder pass is now used to order module variables
before Emit. All variables are now ordered together, without
consideration for whether they are ports, signals form the design, or
additional internal variables added by Verilator (which used to be
ordered and emitted as separate groups in Emit). For single threaded
models, this is performance neutral. For multi-threaded models, the
MTask affinity based sorting was slightly modified, so variables with no
MTask affinity are emitted last, otherwise the MTask affinity sets are
sorted using the TSP sorter as before, but again, ports, signals, and
internal variables are not differentiated. This yields a 2%+ speedup for
the multithreaded model on OpenTitan.
 2021-07-12 14:53:40 +01:00