From ffb02cea154805b0dd4924d60948b5be07a65707 Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Fri, 14 Feb 2025 00:33:12 +0100
Subject: [PATCH] Fix ignoring joins in stringify in preprocessor (#5777)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 src/V3PreProc.cpp                        |  5 +++++
 test_regress/t/t_preproc_strify_join.out |  3 +++
 test_regress/t/t_preproc_strify_join.py  | 24 ++++++++++++++++++++++++
 test_regress/t/t_preproc_strify_join.v   | 19 +++++++++++++++++++
 4 files changed, 51 insertions(+)
 create mode 100644 test_regress/t/t_preproc_strify_join.out
 create mode 100755 test_regress/t/t_preproc_strify_join.py
 create mode 100644 test_regress/t/t_preproc_strify_join.v

diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp
index fa41f5582..435fe64c2 100644
--- a/src/V3PreProc.cpp
+++ b/src/V3PreProc.cpp
@@ -1065,6 +1065,11 @@ int V3PreProcImp::getStateToken() {
                 // FALLTHRU, handle as with VP_SYMBOL_JOIN
             }
         }
+        if (state() == ps_STRIFY) {
+            // Ignore joins and symbol joins in stringify as they don't affect the final string
+            if (tok == VP_JOIN) goto next_tok;
+            if (tok == VP_SYMBOL_JOIN) tok = VP_SYMBOL;
+        }
         if (tok == VP_SYMBOL_JOIN  // not else if, can fallthru from above if()
             || tok == VP_DEFREF_JOIN || tok == VP_JOIN) {
             // a`` -> string doesn't include the ``, so can just grab next and continue
diff --git a/test_regress/t/t_preproc_strify_join.out b/test_regress/t/t_preproc_strify_join.out
new file mode 100644
index 000000000..b80acd35b
--- /dev/null
+++ b/test_regress/t/t_preproc_strify_join.out
@@ -0,0 +1,3 @@
+"foo-bar-qux"
+""foo-bar-qux""
+""
diff --git a/test_regress/t/t_preproc_strify_join.py b/test_regress/t/t_preproc_strify_join.py
new file mode 100755
index 000000000..981d60faf
--- /dev/null
+++ b/test_regress/t/t_preproc_strify_join.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp")
+
+test.compile(verilator_flags2=['-E -P'],
+             verilator_make_gmake=False,
+             make_top_shell=False,
+             make_main=False,
+             stdout_filename=stdout_filename)
+
+test.files_identical(stdout_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_preproc_strify_join.v b/test_regress/t/t_preproc_strify_join.v
new file mode 100644
index 000000000..88241fae5
--- /dev/null
+++ b/test_regress/t/t_preproc_strify_join.v
@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+`define FOO foo
+`define BAR bar
+`define QUX qux
+`define STRIFY `"`FOO``-```BAR``-```QUX```"
+
+`define NESTED_STRIFY `"`STRIFY```"
+
+`define EMPTY
+`define EMPTY_STRIFY `"`EMPTY```"
+
+`STRIFY
+`NESTED_STRIFY
+`EMPTY_STRIFY