diff --git a/test_regress/t/t_trace_cat_saif.cpp b/test_regress/t/t_trace_cat_saif.cpp
new file mode 100644
index 000000000..779f5cfb7
--- /dev/null
+++ b/test_regress/t/t_trace_cat_saif.cpp
@@ -0,0 +1,56 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2008 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+#include <verilated.h>
+#include <verilated_saif_c.h>
+
+#include <memory>
+
+#include VM_PREFIX_INCLUDE
+
+unsigned long long main_time = 0;
+double sc_time_stamp() { return (double)main_time; }
+
+const char* trace_name() {
+    static char name[1000];
+    VL_SNPRINTF(name, 1000, VL_STRINGIFY(TEST_OBJ_DIR) "/simpart_%04d.saif", (int)main_time);
+    return name;
+}
+
+int main(int argc, char** argv) {
+    Verilated::debug(0);
+    Verilated::traceEverOn(true);
+    Verilated::commandArgs(argc, argv);
+
+    std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"top"}};
+
+    std::unique_ptr<VerilatedSaifC> tfp{new VerilatedSaifC};
+    top->trace(tfp.get(), 99);
+
+    tfp->open(trace_name());
+
+    top->clk = 0;
+
+    while (main_time < 190) {  // Creates 2 files
+        top->clk = !top->clk;
+        top->eval();
+
+        if ((main_time % 100) == 0) {
+            tfp->close();
+            tfp->open(trace_name());
+        }
+        tfp->dump((unsigned int)(main_time));
+        ++main_time;
+    }
+    tfp->close();
+    top->final();
+    tfp.reset();
+    top.reset();
+    printf("*-* All Finished *-*\n");
+    return 0;
+}
diff --git a/test_regress/t/t_trace_cat_saif.py b/test_regress/t/t_trace_cat_saif.py
new file mode 100755
index 000000000..556b800a8
--- /dev/null
+++ b/test_regress/t/t_trace_cat_saif.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+test.top_filename = "t/t_trace_cat_fst.v"
+
+test.compile(make_top_shell=False,
+             make_main=False,
+             v_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.obj_dir + "/simpart_0000.saif", "t/" + test.name + "_0000.saif")
+test.saif_identical(test.obj_dir + "/simpart_0100.saif", "t/" + test.name + "_0100.saif")
+
+test.passes()
diff --git a/test_regress/t/t_trace_cat_saif_0000.saif b/test_regress/t/t_trace_cat_saif_0000.saif
new file mode 100644
index 000000000..36861c9e5
--- /dev/null
+++ b/test_regress/t/t_trace_cat_saif_0000.saif
@@ -0,0 +1,27 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "t")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 99)
+(INSTANCE top
+  (NET
+    (clk (T0 49) (T1 50) (TX 0) (TC 100))
+  )
+  (INSTANCE t
+    (NET
+      (clk (T0 49) (T1 50) (TX 0) (TC 100))
+      (cyc\[0\] (T0 50) (T1 49) (TX 0) (TC 49))
+      (cyc\[1\] (T0 51) (T1 48) (TX 0) (TC 24))
+      (cyc\[2\] (T0 51) (T1 48) (TX 0) (TC 12))
+      (cyc\[3\] (T0 51) (T1 48) (TX 0) (TC 6))
+      (cyc\[4\] (T0 64) (T1 35) (TX 0) (TC 3))
+      (cyc\[5\] (T0 64) (T1 35) (TX 0) (TC 1))
+      (unchanged\[1\] (T0 0) (T1 99) (TX 0) (TC 1))
+      (unchanged\[3\] (T0 0) (T1 99) (TX 0) (TC 1))
+      (unchanged\[5\] (T0 0) (T1 99) (TX 0) (TC 1))
+    )
+  )
+)
+)
diff --git a/test_regress/t/t_trace_cat_saif_0100.saif b/test_regress/t/t_trace_cat_saif_0100.saif
new file mode 100644
index 000000000..9d76b6a02
--- /dev/null
+++ b/test_regress/t/t_trace_cat_saif_0100.saif
@@ -0,0 +1,28 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "t")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 189)
+(INSTANCE top
+  (NET
+    (clk (T0 144) (T1 45) (TX 0) (TC 90))
+  )
+  (INSTANCE t
+    (NET
+      (clk (T0 144) (T1 45) (TX 0) (TC 90))
+      (cyc\[0\] (T0 145) (T1 44) (TX 0) (TC 44))
+      (cyc\[1\] (T0 144) (T1 45) (TX 0) (TC 23))
+      (cyc\[2\] (T0 144) (T1 45) (TX 0) (TC 11))
+      (cyc\[3\] (T0 144) (T1 45) (TX 0) (TC 5))
+      (cyc\[4\] (T0 132) (T1 57) (TX 0) (TC 3))
+      (cyc\[5\] (T0 161) (T1 28) (TX 0) (TC 2))
+      (cyc\[6\] (T0 128) (T1 61) (TX 0) (TC 1))
+      (unchanged\[1\] (T0 100) (T1 89) (TX 0) (TC 1))
+      (unchanged\[3\] (T0 100) (T1 89) (TX 0) (TC 1))
+      (unchanged\[5\] (T0 100) (T1 89) (TX 0) (TC 1))
+    )
+  )
+)
+)