From fdf29b970f071e7346739af613c24cc606a10728 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 11 Jan 2025 15:27:11 -0500 Subject: [PATCH] Fix VL_UNLIKELY with constructors --- src/V3EmitCFunc.h | 4 ++-- src/V3Width.cpp | 2 +- test_regress/t/t_hier_block_struct_nohier.py | 19 +++++++++++++++++++ test_regress/t/t_param_array6_noslice.py | 19 +++++++++++++++++++ 4 files changed, 41 insertions(+), 3 deletions(-) create mode 100755 test_regress/t/t_hier_block_struct_nohier.py create mode 100755 test_regress/t/t_param_array6_noslice.py diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 40c7e5423..e79109502 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -968,10 +968,10 @@ public: putns(nodep, "if ("); if (!nodep->branchPred().unknown()) { puts(nodep->branchPred().ascii()); - puts("("); + puts("(("); // Two parens, so that VL_UNLIKELY((class)) works } iterateAndNextConstNull(nodep->condp()); - if (!nodep->branchPred().unknown()) puts(")"); + if (!nodep->branchPred().unknown()) puts("))"); puts(") {\n"); iterateAndNextConstNull(nodep->thensp()); puts("}"); diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 0dca57d26..7a47de1a7 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -4574,8 +4574,8 @@ class WidthVisitor final : public VNVisitor { if (patp) { // Don't want the RHS an array - patp->dtypep(arrayDtp->subDTypep()); allConstant &= VN_IS(patp->lhssp(), Const); + patp->dtypep(arrayDtp->subDTypep()); AstNodeExpr* const valuep = patternMemberValueIterate(patp); if (VN_IS(arrayDtp, UnpackArrayDType)) { if (!newp) { diff --git a/test_regress/t/t_hier_block_struct_nohier.py b/test_regress/t/t_hier_block_struct_nohier.py new file mode 100755 index 000000000..8545961d7 --- /dev/null +++ b/test_regress/t/t_hier_block_struct_nohier.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_hier_block_struct.v" + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_array6_noslice.py b/test_regress/t/t_param_array6_noslice.py new file mode 100755 index 000000000..79f955063 --- /dev/null +++ b/test_regress/t/t_param_array6_noslice.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_param_array6.v" + +test.compile(verilator_flags2=['-fno-slice']) + +test.execute() + +test.passes()