From fd7288fec1e9e085e1a5ab5e85de3d0735b562fe Mon Sep 17 00:00:00 2001
From: Mateusz Gancarz <mgancarz@antmicro.com>
Date: Tue, 11 Feb 2025 14:31:20 +0100
Subject: [PATCH] [#72179] add SAIF trace test for do while jumps

---
 test_regress/t/t_trace_jumps_do_while_saif.py | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100755 test_regress/t/t_trace_jumps_do_while_saif.py

diff --git a/test_regress/t/t_trace_jumps_do_while_saif.py b/test_regress/t/t_trace_jumps_do_while_saif.py
new file mode 100755
index 000000000..82bf14639
--- /dev/null
+++ b/test_regress/t/t_trace_jumps_do_while_saif.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test module
+#
+# Copyright 2025 by Antmicro. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_jumps_do_while.v"
+
+test.compile(verilator_flags2=['--trace-saif'])
+
+test.execute()
+
+#TODO: add function checking if two SAIF files are identical
+#test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()