From fd60e349eedb54a1af507b1ed0e8fe69221d970b Mon Sep 17 00:00:00 2001
From: em2machine <92717390+em2machine@users.noreply.github.com>
Date: Sun, 21 Dec 2025 21:08:41 +0100
Subject: [PATCH] nested interface tests

---
 test_regress/t/t_multidriven_iface5.py | 18 +++++++
 test_regress/t/t_multidriven_iface5.v  | 69 ++++++++++++++++++++++++++
 test_regress/t/t_multidriven_iface6.py | 18 +++++++
 test_regress/t/t_multidriven_iface6.v  | 68 +++++++++++++++++++++++++
 4 files changed, 173 insertions(+)
 create mode 100755 test_regress/t/t_multidriven_iface5.py
 create mode 100644 test_regress/t/t_multidriven_iface5.v
 create mode 100755 test_regress/t/t_multidriven_iface6.py
 create mode 100644 test_regress/t/t_multidriven_iface6.v

diff --git a/test_regress/t/t_multidriven_iface5.py b/test_regress/t/t_multidriven_iface5.py
new file mode 100755
index 000000000..c6e56559a
--- /dev/null
+++ b/test_regress/t/t_multidriven_iface5.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_multidriven_iface5.v b/test_regress/t/t_multidriven_iface5.v
new file mode 100644
index 000000000..0c64246f9
--- /dev/null
+++ b/test_regress/t/t_multidriven_iface5.v
@@ -0,0 +1,69 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+// SPDX-License-Identifier: CC0-1.0
+
+// nested interface test - direct assignment + nested interface task call in same always_comb
+
+// verilog_format: off
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
+// verilog_format: on
+
+interface leaf_if;
+  logic l0;
+  task set1(); l0 = 1'b1; endtask
+endinterface
+
+interface top_if;
+  leaf_if sub();
+endinterface
+
+module mod #()(
+  input logic sel
+  ,output logic val
+);
+
+  top_if if0();
+
+  always_comb begin
+    if0.sub.l0 = 1'b0;
+    if (sel) begin
+      if0.sub.set1();
+    end
+  end
+
+  assign val = if0.sub.l0;
+
+endmodule
+
+module m_tb#()();
+
+  logic sel, val;
+
+  mod m(
+    .sel(sel)
+    ,.val(val)
+  );
+
+  initial begin
+    #1;
+    sel = 'b0;
+    `checkd(val, 1'b0);
+    #1;
+    sel = 'b1;
+    `checkd(val, 1'b1);
+    #1;
+    sel = 'b0;
+    `checkd(val, 1'b0);
+    #1;
+  end
+
+  initial begin
+    #5;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule
diff --git a/test_regress/t/t_multidriven_iface6.py b/test_regress/t/t_multidriven_iface6.py
new file mode 100755
index 000000000..c6e56559a
--- /dev/null
+++ b/test_regress/t/t_multidriven_iface6.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_multidriven_iface6.v b/test_regress/t/t_multidriven_iface6.v
new file mode 100644
index 000000000..83024eb74
--- /dev/null
+++ b/test_regress/t/t_multidriven_iface6.v
@@ -0,0 +1,68 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+// SPDX-License-Identifier: CC0-1.0
+
+// nested interface aggregator - two nested interfaces, only one driven
+
+// verilog_format: off
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
+// verilog_format: on
+
+interface chan_if;
+  logic b0;
+  task set1(); b0 = 1'b1; endtask
+endinterface
+
+interface agg_if;
+  chan_if tlb();
+  chan_if ic();
+endinterface
+
+module mod #()(
+  input logic sel
+  ,output logic val
+);
+
+  agg_if a();
+
+  always_comb begin
+    a.tlb.b0 = 1'b0;
+    if (sel) a.tlb.set1();
+  end
+
+  assign val = a.tlb.b0;
+
+endmodule
+
+module m_tb#()();
+
+  logic sel, val;
+
+  mod m(
+    .sel(sel)
+    ,.val(val)
+  );
+
+  initial begin
+    #1;
+    sel = 'b0;
+    `checkd(val, 1'b0);
+    #1;
+    sel = 'b1;
+    `checkd(val, 1'b1);
+    #1;
+    sel = 'b0;
+    `checkd(val, 1'b0);
+    #1;
+  end
+
+  initial begin
+    #5;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule