From fc975c409a617421d6efbe4374c4efac5b13777a Mon Sep 17 00:00:00 2001 From: Yilou Wang Date: Fri, 27 Mar 2026 20:16:49 +0100 Subject: [PATCH] Apply make format --- src/V3Timing.cpp | 5 ++--- src/V3Width.cpp | 8 ++------ test_regress/t/t_wait_iface_vif.py | 2 +- test_regress/t/t_wait_iface_vif.v | 2 +- 4 files changed, 6 insertions(+), 11 deletions(-) diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp index 602b7de06..275f7c1c0 100644 --- a/src/V3Timing.cpp +++ b/src/V3Timing.cpp @@ -892,9 +892,8 @@ class TimingControlVisitor final : public VNVisitor { m_underProcedure = true; // Workaround for killing `always` processes (doing that is pretty much UB) // TODO: Disallow killing `always` at runtime (throw an error) - // Do not make combinational always blocks (always @*) suspendable just because - // they need process context (e.g. for uvm_fatal's process::self()). Combo blocks - // have no timing controls and would spin forever as coroutines. + // Combo blocks (always @*) must not become coroutines -- they have no + // suspend points and would spin forever. if (hasFlags(nodep, T_HAS_PROC) && !(m_activep && m_activep->sentreep() && m_activep->sentreep()->hasCombo())) addFlags(nodep, T_SUSPENDEE); diff --git a/src/V3Width.cpp b/src/V3Width.cpp index f5b1244a8..01c5b5988 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -4464,14 +4464,10 @@ class WidthVisitor final : public VNVisitor { if (AstNodeFTask* const ftaskp = VN_CAST(m_memberMap.findMember(ifacep, nodep->name()), NodeFTask)) { UINFO(5, __FUNCTION__ << "AstNodeFTask" << nodep); - // When a function/task is called through a virtual interface, its body may - // write to interface member variables. Mark all members as sensIfacep so - // optimization passes do not constant-fold them across instances. + // VIF function may write any member; prevent constant-folding. if (adtypep->isVirtual()) { for (AstNode* itemp = ifacep->stmtsp(); itemp; itemp = itemp->nextp()) { - if (AstVar* const mvarp = VN_CAST(itemp, Var)) { - mvarp->sensIfacep(ifacep); - } + if (AstVar* const mvarp = VN_CAST(itemp, Var)) { mvarp->sensIfacep(ifacep); } } } userIterate(ftaskp, nullptr); diff --git a/test_regress/t/t_wait_iface_vif.py b/test_regress/t/t_wait_iface_vif.py index 557b1b992..164ae787b 100755 --- a/test_regress/t/t_wait_iface_vif.py +++ b/test_regress/t/t_wait_iface_vif.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wait_iface_vif.v b/test_regress/t/t_wait_iface_vif.v index efdc2a65c..f0cf919da 100755 --- a/test_regress/t/t_wait_iface_vif.v +++ b/test_regress/t/t_wait_iface_vif.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2025 PlanV GmbH +// SPDX-FileCopyrightText: 2026 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off ZERODLY */