diff --git a/bin/verilator b/bin/verilator
index 9bd192f80..ff180139a 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -981,6 +981,7 @@ It also creates internal files that can be mostly ignored:
     {each_verilog_module}.vpp		// Post-processed verilog (--debug)
     {prefix}.flags_vbin			// Verilator dependencies
     {prefix}.flags_vpp			// Pre-processor dependencies
+    {prefix}__verFiles.dat		// Timestamps for skip-identical
     {prefix}{misc}.d			// Make dependencies (-MMD)
     {prefix}{misc}.dot			// Debugging graph files (--debug)
     {prefix}{misc}.tree			// Debugging files (--debug)
diff --git a/bin/verilator_includer b/bin/verilator_includer
index 51e1ea34a..f9197a073 100755
--- a/bin/verilator_includer
+++ b/bin/verilator_includer
@@ -10,6 +10,7 @@ eval 'exec perl -wS $0 ${1+"$@"}'
 
 require 5.005;
 use warnings;
+print "// DESCR"."IPTION: Generated by verilator_includer via makefile\n";
 foreach my $param (@ARGV) {
     print "#include \"$param\"\n"
 }
diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp
index e9dfc97b6..7cc83a497 100644
--- a/src/V3EmitCSyms.cpp
+++ b/src/V3EmitCSyms.cpp
@@ -125,6 +125,11 @@ void EmitCSyms::emitInt() {
     m_ofp = &hf;
 
     ofp()->putsHeader();
+    puts("// DESCR" "IPTION: Verilator output: Symbol table internal header\n");
+    puts("//\n");
+    puts("// Internal details; most calling programs do not need this header\n");
+    puts("\n");
+
     puts("#ifndef _"+symClassName()+"_H_\n");
     puts("#define _"+symClassName()+"_H_\n");
     puts("\n");
@@ -188,6 +193,7 @@ void EmitCSyms::emitImp() {
     V3OutCFile cf (filename);
     m_ofp = &cf;
     ofp()->putsHeader();
+    puts("// DESCR" "IPTION: Verilator output: Symbol table implementation internals\n");
     puts("\n");
 
     // Includes
diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp
index b2c604bea..f6e2b4cb7 100644
--- a/src/V3EmitV.cpp
+++ b/src/V3EmitV.cpp
@@ -505,6 +505,7 @@ void V3EmitV::emitv() {
 	// All-in-one file
 	V3OutVFile of (v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__Vout.v");
 	of.putsHeader();
+	of.puts("# DESCR" "IPTION: Verilator output: Verilog representation of internal tree for debug\n");
 	EmitVFileVisitor visitor (v3Global.rootp(), &of);
     } else {
 	// Process each module in turn
diff --git a/src/V3File.cpp b/src/V3File.cpp
index a988079ed..b7baa30b7 100644
--- a/src/V3File.cpp
+++ b/src/V3File.cpp
@@ -144,6 +144,7 @@ inline void V3FileDependImp::writeTimes(const string& filename, const string& cm
     if (ofp->fail()) v3fatalSrc("Can't write "<<filename);
 
     string cmdline = stripQuotes(cmdlineIn);
+    *ofp<<"# DESCR"<<"IPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will."<<endl;
     *ofp<<"C \""<<cmdline<<"\""<<endl;
 
 #if !defined (__MINGW32__)
@@ -171,6 +172,9 @@ inline bool V3FileDependImp::checkTimes(const string& filename, const string& cm
 	UINFO(2,"   --check-times failed: no input "<<filename<<endl);
 	return false;
     }
+    {
+	string ignore;  getline(*ifp, ignore);
+    }
     {
 	char   chkDir;   *ifp>>chkDir;
 	char   quote;    *ifp>>quote;