From fc700538a57842d6662024bd756e996b4cb89997 Mon Sep 17 00:00:00 2001
From: Zhen Yan <89853352+sdjasj@users.noreply.github.com>
Date: Sat, 17 May 2025 09:57:52 +0800
Subject: [PATCH] Fix arithmetic left-shift by constants over 32 bits (#6007)
 (#6015)

---
 src/V3Number.cpp                 |  4 ++--
 test_regress/t/t_math_shiftls.py | 18 ++++++++++++++++++
 test_regress/t/t_math_shiftls.v  | 23 +++++++++++++++++++++++
 3 files changed, 43 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_math_shiftls.py
 create mode 100644 test_regress/t/t_math_shiftls.v

diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 13a1984fb..031a253ab 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -1877,8 +1877,8 @@ V3Number& V3Number::opShiftL(const V3Number& lhs, const V3Number& rhs) {
         if (rhs.bitIs1(bit)) return *this;  // shift of over 2^32 must be zero
     }
     const uint32_t rhsval = rhs.toUInt();
-    for (int bit = 0; bit < width(); ++bit) {
-        if (bit >= static_cast<int>(rhsval)) setBit(bit, lhs.bitIs(bit - rhsval));
+    for (uint32_t bit = 0; bit < static_cast<uint32_t>(width()); ++bit) {
+        if (bit >= rhsval) setBit(bit, lhs.bitIs(bit - rhsval));
     }
     return *this;
 }
diff --git a/test_regress/t/t_math_shiftls.py b/test_regress/t/t_math_shiftls.py
new file mode 100755
index 000000000..bd059b0f2
--- /dev/null
+++ b/test_regress/t/t_math_shiftls.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_math_shiftls.v b/test_regress/t/t_math_shiftls.v
new file mode 100644
index 000000000..334f1a104
--- /dev/null
+++ b/test_regress/t/t_math_shiftls.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Zhen Yan.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__, `__LINE__, (gotv), (expv)); `stop; end while(0);
+
+module top (out33);
+
+output wire [6:0] out33;
+
+    assign out33 = (7'o66 <<< 32'hFFFF_FFFF);
+
+    initial begin
+      #10;
+      `checkd(out33, '0);
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+
+endmodule