From fc302a520708d6db3ee97939917fdd9dc05524d7 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Sat, 1 Mar 2025 22:11:43 +0000
Subject: [PATCH] Fix sorting of wide SenItems (#5816)

This used to throw Error: Value too wide for 64-bits expected in this context
---
 src/V3Const.cpp                     |  4 ++--
 test_regress/t/t_alw_sen_compare.py | 16 ++++++++++++++++
 test_regress/t/t_alw_sen_compare.v  | 20 ++++++++++++++++++++
 3 files changed, 38 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_alw_sen_compare.py
 create mode 100644 test_regress/t/t_alw_sen_compare.v

diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 782b7a00b..f9dc4385c 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -2896,8 +2896,8 @@ class ConstVisitor final : public VNVisitor {
 
             if (const AstConst* const aConstp = VN_CAST(ap, Const)) {
                 const AstConst* const bConstp = VN_AS(bp, Const);
-                if (aConstp->toUQuad() < bConstp->toUQuad()) return -1;
-                if (aConstp->toUQuad() > bConstp->toUQuad()) return 1;
+                if (aConstp->num().isLtXZ(bConstp->num())) return -1;
+                if (bConstp->num().isLtXZ(aConstp->num())) return 1;
                 return 0;
             }
 
diff --git a/test_regress/t/t_alw_sen_compare.py b/test_regress/t/t_alw_sen_compare.py
new file mode 100755
index 000000000..2e9528d96
--- /dev/null
+++ b/test_regress/t/t_alw_sen_compare.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--timing"])
+
+test.passes()
diff --git a/test_regress/t/t_alw_sen_compare.v b/test_regress/t/t_alw_sen_compare.v
new file mode 100644
index 000000000..f2edfb4c0
--- /dev/null
+++ b/test_regress/t/t_alw_sen_compare.v
@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module top;
+   sub inst(
+      .a({128{1'b1}}),
+      .b({128{1'b1}})
+  );
+endmodule
+
+module sub(a, b);
+  input [127:0] a;
+  input [127:0] b;
+  always @(a or b) begin
+    $display("doesn't matter");
+  end
+endmodule