diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h
index bed5e9ec2..163c52bae 100644
--- a/src/V3ParseImp.h
+++ b/src/V3ParseImp.h
@@ -65,6 +65,7 @@ struct V3ParseBisonYYSType {
 	AstBegin*	beginp;
 	AstCase*	casep;
 	AstCaseItem*	caseitemp;
+	AstCell*	cellp;
 	AstConst*	constp;
 	AstNodeModule*	modulep;
 	AstNodeDType*	dtypep;
diff --git a/src/verilog.y b/src/verilog.y
index 182e4cbc8..9366e23d2 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1731,6 +1731,9 @@ instnameParen<nodep>:
 		id instRangeE '(' cellpinList ')'	{ $$ = new AstCell($<fl>1,*$1,GRAMMARP->m_instModule,$4,  GRAMMARP->m_instParamp,$2); }
 	|	id instRangeE 				{ $$ = new AstCell($<fl>1,*$1,GRAMMARP->m_instModule,NULL,GRAMMARP->m_instParamp,$2); }
 	//UNSUP	instRangeE '(' cellpinList ')'		{ UNSUP } // UDP
+	//			// Adding above and switching to the Verilog-Perl syntax
+	//			// causes a shift conflict due to use of idClassSel inside exprScope.
+	//			// It also breaks allowing "id foo;" instantiation syntax.
 	;
 
 instRangeE<rangep>:
diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 0920be132..c6c43efaa 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -354,7 +354,8 @@ sub new {
 	vcs_run_flags => [split(/\s+/,"+vcs+lic_wait")],
 	# NC
 	nc => 0,
-	nc_flags => [split(/\s+/,"+licqueue +nowarn+LIBNOU +define+NC=1 -q +assert +sv -c ")],
+	nc_flags => [split(/\s+/,("+licqueue +nowarn+LIBNOU +define+NC=1 -q +assert +sv -c "
+				  .($opt_trace ? " +access+r":"")))],
 	nc_flags2 => [],  # Overridden in some sim files
 	nc_run_flags => [split(/\s+/,"+licqueue -q +assert +sv -R")],
 	# Verilator
diff --git a/test_regress/t/t_udp_noname.pl b/test_regress/t/t_udp_noname.pl
new file mode 100755
index 000000000..e6cf2a5b4
--- /dev/null
+++ b/test_regress/t/t_udp_noname.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug468");
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_udp_noname.v b/test_regress/t/t_udp_noname.v
new file mode 100644
index 000000000..4ac198647
--- /dev/null
+++ b/test_regress/t/t_udp_noname.v
@@ -0,0 +1,47 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   reg  a;
+   wire  o;
+   udp (o, a);
+
+   integer cyc;  initial cyc=0;
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      a <= cyc[0];
+      if (cyc==0) begin
+      end
+      else if (cyc<90) begin
+	 if (a != !cyc[0]) $stop;
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+primitive udp(o,a);
+   output o;
+   input  a;
+`ifdef verilator
+   wire   o = ~a;
+`else
+   table
+      //o a
+      0 :  1;
+      1 :  0;
+   endtable
+`endif
+endprimitive