diff --git a/Changes b/Changes index b1e539f74..63c0327f3 100644 --- a/Changes +++ b/Changes @@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix false BLKSEQ on non-unrolled for loop indexes. [Jeff Winston] +**** Fix block comment not separating identifiers, bug311. [Gene Sullivan] + * Verilator 3.810 2011/01/03 ** Add limited support for VPI access to public signals, see docs. diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index 08b1c9fa0..ef333fc6d 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -848,8 +848,13 @@ int V3PreProcImp::getStateToken() { if (m_lexp->m_keepComments == KEEPCMT_SUB) { string rtn; rtn.assign(yyourtext(),yyourleng()); comment(rtn); - } else { + // Need to insure "foo/**/bar" becomes two tokens + insertUnreadback (" "); + } else if (m_lexp->m_keepComments) { return (tok); + } else { + // Need to insure "foo/**/bar" becomes two tokens + insertUnreadback (" "); } } // We're off or processed the comment specially. If there are newlines diff --git a/test_regress/t/t_pipe_filter.out b/test_regress/t/t_pipe_filter.out index ba6157c91..b32f7e2aa 100644 --- a/test_regress/t/t_pipe_filter.out +++ b/test_regress/t/t_pipe_filter.out @@ -1,11 +1,13 @@ `line 1 "t/t_pipe_filter.v" 1 + +`line 3 "t/t_pipe_filter.v" 0 + + - - - - - +`line 6 "t/t_pipe_filter.v" 0 + + `line 10 "t/t_pipe_filter.v" 0 @@ -19,37 +21,39 @@ example line 11; int lint_off_line_7 = 1; `line 2 "t/t_pipe_filter_inc.vh" 0 int lint_off_line_8 = 1; + - - - +`line 5 "t/t_pipe_filter_inc.vh" 0 + + `line 8 "t/t_pipe_filter_inc.vh" 0 inc line 6; -inc line 7; -inc line 8; +inc line 7; +inc line 8; inc line 9; `line 13 "t/t_pipe_filter_inc.vh" 2 `line 13 "t/t_pipe_filter.v" 0 - -`line 15 "t/t_pipe_filter.v" 0 +`line 14 "t/t_pipe_filter.v" 0 + `line 15 "t/t_pipe_filter.v" 0 `line 1 "t/t_pipe_filter_inc.vh" 1 int lint_off_line_7 = 1; `line 2 "t/t_pipe_filter_inc.vh" 0 int lint_off_line_8 = 1; + - - - +`line 5 "t/t_pipe_filter_inc.vh" 0 + + `line 8 "t/t_pipe_filter_inc.vh" 0 inc line 6; -inc line 7; -inc line 8; +inc line 7; +inc line 8; inc line 9; `line 13 "t/t_pipe_filter_inc.vh" 2 diff --git a/test_regress/t/t_preproc.out b/test_regress/t/t_preproc.out index 0b6011ebf..58bc48252 100644 --- a/test_regress/t/t_preproc.out +++ b/test_regress/t/t_preproc.out @@ -1,39 +1,38 @@ `line 1 "t/t_preproc.v" 1 + + + - - - - - -`line 7 "t/t_preproc.v" 0 +`line 5 "t/t_preproc.v" 0 + + `line 7 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 - -`line 3 "t/t_preproc_inc2.vh" 0 - - -`line 4 "t/t_preproc_inc2.vh" 0 + +`line 2 "t/t_preproc_inc2.vh" 0 + + At file "t/t_preproc_inc2.vh" line 4 `line 6 "t/t_preproc_inc2.vh" 0 `line 1 "t/t_preproc_inc3.vh" 1 `line 2 "inc3_a_filename_from_line_directive" 0 - - - + + + `line 6 "inc3_a_filename_from_line_directive" 0 - + At file "inc3_a_filename_from_line_directive" line 10 `line 12 "inc3_a_filename_from_line_directive" 0 - + `line 15 "inc3_a_filename_from_line_directive" 0 @@ -48,23 +47,24 @@ At file "t/t_preproc_inc2.vh" line 4 `line 7 "t/t_preproc.v" 0 - - +`line 9 "t/t_preproc.v" 0 + + `line 12 "t/t_preproc.v" 0 -/*verilator pass_thru comment*/ +/*verilator pass_thru comment*/ `line 14 "t/t_preproc.v" 0 -/*verilator pass_thru_comment2*/ - - +/*verilator pass_thru_comment2*/ +`line 16 "t/t_preproc.v" 0 + + `line 19 "t/t_preproc.v" 0 - -`line 22 "t/t_preproc.v" 0 + wire [3:0] q = { 1'b1 , 1'b0 , @@ -78,7 +78,7 @@ text. `line 31 "t/t_preproc.v" 0 -foo bar +foo bar foobar2 `line 36 "t/t_preproc.v" 0 @@ -92,8 +92,8 @@ foobar2 - -`line 46 "t/t_preproc.v" 0 +`line 45 "t/t_preproc.v" 0 + first part `line 46 "t/t_preproc.v" 0 second part @@ -108,7 +108,8 @@ first part c} Line_Preproc_Check 48 - +`line 50 "t/t_preproc.v" 0 + `line 52 "t/t_preproc.v" 0 @@ -160,11 +161,13 @@ bar_suffix more `line 86 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; +`line 88 "t/t_preproc.v" 0 + + - - - - +`line 91 "t/t_preproc.v" 0 + + `line 94 "t/t_preproc.v" 0 @@ -174,7 +177,7 @@ bar_suffix more initial begin - + $display("pre thrupre thrumid thrupost post: \"right side\""); $display("left side: \"right side\""); $display("left side: \"right side\""); @@ -182,25 +185,26 @@ bar_suffix more $display("na: \"right_side\""); $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\""); $display("na: \"nana\""); - $display("left_side right_side: \"left_side right_side\""); - $display(": \"\""); + $display("left_side right_side: \"left_side right_side\""); + $display(": \"\""); $display("left side: \"right side\""); $display("left side: \"right side\""); $display("standalone"); `line 115 "t/t_preproc.v" 0 - + $display("twoline: \"first second\""); - + $write("*-* All Finished *-*\n"); $finish; end endmodule - - +`line 125 "t/t_preproc.v" 0 + + `line 128 "t/t_preproc.v" 0 @@ -216,7 +220,7 @@ wire tmp_d1 = d1; `line 134 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; `line 134 "t/t_preproc.v" 0 -assign o1 = tmp_o1 ; +assign o1 = tmp_o1 ; endmodule module add2 ( input wire d2, output wire o2); @@ -225,7 +229,7 @@ wire tmp_d2 = d2; `line 137 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; `line 137 "t/t_preproc.v" 0 -assign o2 = tmp_o2 ; +assign o2 = tmp_o2 ; endmodule `line 140 "t/t_preproc.v" 0 @@ -235,8 +239,8 @@ endmodule - -`line 147 "t/t_preproc.v" 0 +`line 146 "t/t_preproc.v" 0 + @@ -250,11 +254,11 @@ endmodule `line 151 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; `line 151 "t/t_preproc.v" 0 - end endgenerate + end endgenerate - - -`line 155 "t/t_preproc.v" 0 +`line 153 "t/t_preproc.v" 0 + + module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) @@ -262,11 +266,11 @@ module prot(); `endprotected `line 160 "t/t_preproc.v" 0 endmodule + - - - -`line 165 "t/t_preproc.v" 0 +`line 163 "t/t_preproc.v" 0 + + @@ -280,17 +284,17 @@ begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more - - -`line 179 "t/t_preproc.v" 0 +`line 177 "t/t_preproc.v" 0 + + `line 180 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 - -`line 3 "t/t_preproc_inc4.vh" 0 - - + +`line 2 "t/t_preproc_inc4.vh" 0 + + `line 5 "t/t_preproc_inc4.vh" 0 @@ -310,8 +314,9 @@ begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more - - +`line 190 "t/t_preproc.v" 0 + + `line 193 "t/t_preproc.v" 0 @@ -320,16 +325,18 @@ $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); - - +`line 199 "t/t_preproc.v" 0 + + `line 202 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire - - +`line 206 "t/t_preproc.v" 0 + + `line 209 "t/t_preproc.v" 0 @@ -339,11 +346,12 @@ $blah(this.logfile,{blah.name(), " is not foo"}); `line 213 "t/t_preproc.v" 0 Line_Preproc_Check 213 - - +`line 215 "t/t_preproc.v" 0 + + `line 218 "t/t_preproc.v" 0 - + (p,q) @@ -354,21 +362,22 @@ Line_Preproc_Check 213 (x,y) Line_Preproc_Check 226 - - +`line 228 "t/t_preproc.v" 0 + + `line 231 "t/t_preproc.v" 0 -beginend beginend -"beginend" +beginend +"beginend" - - -`line 241 "t/t_preproc.v" 0 +`line 239 "t/t_preproc.v" 0 + + `\esc`def @@ -376,24 +385,24 @@ beginend `line 245 "t/t_preproc.v" 0 Not a \`define - - -`line 249 "t/t_preproc.v" 0 +`line 247 "t/t_preproc.v" 0 + + x,y)--bee submacro has comma paren - - -`line 257 "t/t_preproc.v" 0 +`line 255 "t/t_preproc.v" 0 + + $display("bits %d %d", $bits(foo), `10); - - -`line 262 "t/t_preproc.v" 0 +`line 260 "t/t_preproc.v" 0 + + @@ -401,9 +410,9 @@ $display("bits %d %d", $bits(foo), `10); - - -`line 270 "t/t_preproc.v" 0 +`line 268 "t/t_preproc.v" 0 + + @@ -441,7 +450,8 @@ $display("bits %d %d", $bits(foo), `10); `line 284 "t/t_preproc.v" 0 - \ + \ + @@ -449,17 +459,16 @@ $display("bits %d %d", $bits(foo), `10); -`line 293 "t/t_preproc.v" 0 - `line 293 "t/t_preproc.v" 0 `line 293 "t/t_preproc.v" 0 - + `line 293 "t/t_preproc.v" 0 def i - +`line 295 "t/t_preproc.v" 0 + `line 297 "t/t_preproc.v" 0 @@ -475,17 +484,17 @@ $display("bits %d %d", $bits(foo), `10); `line 307 "t/t_preproc.v" 0 -1 /*verilator NOT IN DEFINE*/ (nodef) -2 /*verilator PART OF DEFINE*/ (hasdef) +1 /*verilator NOT IN DEFINE*/ (nodef) +2 /*verilator PART OF DEFINE*/ (hasdef) 3 `line 309 "t/t_preproc.v" 0 /*verilator NOT PART - OF DEFINE*/ (nodef) + OF DEFINE*/ (nodef) `line 310 "t/t_preproc.v" 0 4 `line 310 "t/t_preproc.v" 0 /*verilator PART - OF DEFINE*/ (nodef) + OF DEFINE*/ (nodef) `line 311 "t/t_preproc.v" 0 5 also in `line 311 "t/t_preproc.v" 0 @@ -496,7 +505,8 @@ HAS a NEW `line 314 "t/t_preproc.v" 0 LINE - +`line 316 "t/t_preproc.v" 0 + `line 318 "t/t_preproc.v" 0 @@ -527,7 +537,7 @@ EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " `line 340 "t/t_preproc.v" 0 do `line 340 "t/t_preproc.v" 0 - + `line 340 "t/t_preproc.v" 0 `line 340 "t/t_preproc.v" 0 @@ -543,11 +553,12 @@ EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " `line 340 "t/t_preproc.v" 0 end `line 340 "t/t_preproc.v" 0 - + `line 340 "t/t_preproc.v" 0 while(0); - +`line 342 "t/t_preproc.v" 0 + `line 344 "t/t_preproc.v" 0 @@ -562,21 +573,19 @@ EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " `line 349 "t/t_preproc.v" 0 - -`line 351 "t/t_preproc.v" 0 + EXP: This is fooed This is fooed EXP: This is fooed_2 This is fooed_2 - -`line 357 "t/t_preproc.v" 0 +`line 356 "t/t_preproc.v" 0 + np np - - -`line 362 "t/t_preproc.v" 0 + + @@ -586,9 +595,9 @@ np - - -`line 372 "t/t_preproc.v" 0 +`line 370 "t/t_preproc.v" 0 + + @@ -603,18 +612,17 @@ np `line 382 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 - - -`line 386 "t/t_preproc.v" 0 + + `line 388 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 - -`line 3 "t/t_preproc_inc4.vh" 0 - - + +`line 2 "t/t_preproc_inc4.vh" 0 + + `line 5 "t/t_preproc_inc4.vh" 0 @@ -624,10 +632,9 @@ hello4hello4hello4hello4 `line 389 "t/t_preproc.v" 0 - - - -`line 393 "t/t_preproc.v" 0 + + + @@ -639,9 +646,8 @@ hello4hello4hello4hello4 Line_Preproc_Check 401 - - -`line 404 "t/t_preproc.v" 0 + + @@ -652,15 +658,14 @@ Line_Preproc_Check 407 BAR " `line 410 "t/t_preproc.v" 0 Line_Preproc_Check 410 - - + + `line 414 "t/t_preproc.v" 0 - -`line 418 "t/t_preproc.v" 0 + abc @@ -679,15 +684,14 @@ sonet_frame EXP: sonet_frame sonet_frame - -`line 435 "t/t_preproc.v" 0 + EXP: sonet_frame sonet_frame - -`line 441 "t/t_preproc.v" 0 +`line 440 "t/t_preproc.v" 0 + EXP: module zzz ; endmodule @@ -700,6 +704,10 @@ EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule +`line 452 "t/t_preproc.v" 0 + + +integer foo; + - -`line 454 "t/t_preproc.v" 2 +`line 457 "t/t_preproc.v" 2 diff --git a/test_regress/t/t_preproc.v b/test_regress/t/t_preproc.v index 2f172261d..022950604 100644 --- a/test_regress/t/t_preproc.v +++ b/test_regress/t/t_preproc.v @@ -450,3 +450,6 @@ module `Q1 ; endmodule module `Q1 ; endmodule //====================================================================== +// bug311 +integer/*NEED_SPACE*/foo; +//====================================================================== diff --git a/test_regress/t/t_preproc_def09.out b/test_regress/t/t_preproc_def09.out index 90131cae0..f6cec7721 100644 --- a/test_regress/t/t_preproc_def09.out +++ b/test_regress/t/t_preproc_def09.out @@ -1,14 +1,15 @@ `line 1 "t/t_preproc_def09.v" 1 + + +`line 3 "t/t_preproc_def09.v" 0 + + - - - - - - -`line 10 "t/t_preproc_def09.v" 0 +`line 8 "t/t_preproc_def09.v" 0 + + 'initial $display("start", "msg1" , "msg2", "end");' 'initial $display("start", "msg1" , "msg2" , "end");' @@ -20,12 +21,12 @@ 'initial $display("start", , , "end");' 'initial $display("start", , , "end");' 'initial $display("start", , , "end");' + + + - - - - -`line 26 "t/t_preproc_def09.v" 0 +`line 25 "t/t_preproc_def09.v" 0 + '$display(5,,2,,3);' '$display(5,,2,,3);' @@ -33,7 +34,7 @@ '$display(1 ,,"B",,3 );' '$display(5,,2,,);' '$display(5,,2,,);' - + `line 35 "t/t_preproc_def09.v" 0 @@ -50,21 +51,21 @@ '$display(1 ,,0,,"C");' '$display(5,,0,,"C");' '$display(5,,0,,"C");' - + `line 50 "t/t_preproc_def09.v" 0 'b + 1 + 42 + a' 'b + 1 + 42 + a' - -`line 55 "t/t_preproc_def09.v" 0 +`line 54 "t/t_preproc_def09.v" 0 + '"==)" "((((" () '; '"==)" "((((" () '; - -`line 60 "t/t_preproc_def09.v" 0 +`line 59 "t/t_preproc_def09.v" 0 + @@ -79,6 +80,7 @@ '(6) (eq=al) ZOT' HERE-71 - Line71 - +`line 73 "t/t_preproc_def09.v" 0 + `line 75 "t/t_preproc_def09.v" 2 diff --git a/test_regress/t/t_preproc_psl_off.out b/test_regress/t/t_preproc_psl_off.out index dfb321c53..fecd97702 100644 --- a/test_regress/t/t_preproc_psl_off.out +++ b/test_regress/t/t_preproc_psl_off.out @@ -1,29 +1,29 @@ `line 1 "t/t_preproc_psl.v" 1 + - - - +`line 4 "t/t_preproc_psl.v" 0 + + `line 7 "t/t_preproc_psl.v" 0 -/*verilator metacomment preserved*/ - -`line 9 "t/t_preproc_psl.v" 0 -/*verilator metacomment also_preserved*/ +/*verilator metacomment preserved*/ + +/*verilator metacomment also_preserved*/ `line 11 "t/t_preproc_psl.v" 0 Hello in t_preproc_psl.v - - - - + + + + `line 17 "t/t_preproc_psl.v" 0 - - - - - + + + + + `line 28 "t/t_preproc_psl.v" 0 @@ -34,13 +34,13 @@ Hello in t_preproc_psl.v `line 28 "t/t_preproc_psl.v" 0 - -`line 29 "t/t_preproc_psl.v" 0 +`line 28 "t/t_preproc_psl.v" 0 + 29 `line 31 "t/t_preproc_psl.v" 0 - - + + `line 40 "t/t_preproc_psl.v" 0 @@ -53,36 +53,37 @@ Hello in t_preproc_psl.v `line 40 "t/t_preproc_psl.v" 0 - -`line 41 "t/t_preproc_psl.v" 0 +`line 40 "t/t_preproc_psl.v" 0 + 41 `line 43 "t/t_preproc_psl.v" 0 - + `line 45 "t/t_preproc_psl.v" 0 - - - - - -`line 50 "t/t_preproc_psl.v" 0 - - - - + + + +`line 49 "t/t_preproc_psl.v" 0 + + + + + +`line 55 "t/t_preproc_psl.v" 0 + `line 57 "t/t_preproc_psl.v" 0 - -`line 62 "t/t_preproc_psl.v" 0 +`line 61 "t/t_preproc_psl.v" 0 - + + `line 65 "t/t_preproc_psl.v" 0 @@ -91,8 +92,8 @@ psl assert always sig!=90; `verilog - -`line 72 "t/t_preproc_psl.v" 0 +`line 71 "t/t_preproc_psl.v" 0 + 72 `line 74 "t/t_preproc_psl.v" 2 diff --git a/test_regress/t/t_preproc_psl_on.out b/test_regress/t/t_preproc_psl_on.out index 35550efc3..bf4bb1e57 100644 --- a/test_regress/t/t_preproc_psl_on.out +++ b/test_regress/t/t_preproc_psl_on.out @@ -1,22 +1,22 @@ `line 1 "t/t_preproc_psl.v" 1 + - - - +`line 4 "t/t_preproc_psl.v" 0 + + `line 7 "t/t_preproc_psl.v" 0 -/*verilator metacomment preserved*/ - -`line 9 "t/t_preproc_psl.v" 0 -/*verilator metacomment also_preserved*/ +/*verilator metacomment preserved*/ + +/*verilator metacomment also_preserved*/ `line 11 "t/t_preproc_psl.v" 0 Hello in t_preproc_psl.v - - - - + + + + `line 17 "t/t_preproc_psl.v" 0 psl default clock = (posedge clk); @@ -24,27 +24,26 @@ Hello in t_preproc_psl.v psl assert always cyc!=10; psl assert always cyc==3 -> mask==8'h2; psl failsx: cover {cyc==3 && mask==8'h1}; - psl fails2: + psl fails2: cover { cyc==3 && mask==8'h9}; - + fails3: always assert { cyc==3 && mask==8'h10 }; - + 29 `line 31 "t/t_preproc_psl.v" 0 + + - - - psl -`line 35 "t/t_preproc_psl.v" 0 + psl fails_ml: assert always cyc==3 -> mask==8'h21; psl fails_mlalso: assert always cyc==3 -> mask==8'h21; - + 41 `line 43 "t/t_preproc_psl.v" 0 @@ -53,24 +52,25 @@ Hello in t_preproc_psl.v `line 45 "t/t_preproc_psl.v" 0 psl fails3: assert always psl cyc==3 -> mask==8'h21; - + - -`line 50 "t/t_preproc_psl.v" 0 +`line 49 "t/t_preproc_psl.v" 0 + psl assert always psl {[*]; cyc==3; psl cyc==4; cyc==6}; - - + +`line 55 "t/t_preproc_psl.v" 0 + `line 57 "t/t_preproc_psl.v" 0 - -`line 62 "t/t_preproc_psl.v" 0 +`line 61 "t/t_preproc_psl.v" 0 + psl assert always cyc!=10; @@ -81,8 +81,8 @@ psl assert always sig!=90; `verilog - -`line 72 "t/t_preproc_psl.v" 0 +`line 71 "t/t_preproc_psl.v" 0 + 72 `line 74 "t/t_preproc_psl.v" 2