diff --git a/Changes b/Changes
index 5d5ab3be9..e824230d1 100644
--- a/Changes
+++ b/Changes
@@ -33,6 +33,7 @@ Verilator 5.033 devel
 * Fix segfault when only enum value referenced in package (#5714). [Dan Katz]
 * Fix `BLKSEQ` on suspendable processes (#5722). [Krzysztof Bieganski, Antmicro Ltd.]
 * Fix matching language extension options including dots.
+* Fix duplicate-named class variable equivalence (#5737).
 
 
 Verilator 5.032 2025-01-01
diff --git a/src/V3AstInlines.h b/src/V3AstInlines.h
index 90ebccfd8..3f6b06c7e 100644
--- a/src/V3AstInlines.h
+++ b/src/V3AstInlines.h
@@ -188,8 +188,9 @@ bool AstVarRef::sameNode(const AstVarRef* samep) const {
     if (varScopep()) {
         return (varScopep() == samep->varScopep() && access() == samep->access());
     } else {
-        return (selfPointer() == samep->selfPointer() && varp()->name() == samep->varp()->name()
-                && access() == samep->access());
+        return (selfPointer() == samep->selfPointer()
+                && classOrPackagep() == samep->classOrPackagep()
+                && varp()->name() == samep->varp()->name() && access() == samep->access());
     }
 }
 bool AstVarRef::sameNoLvalue(AstVarRef* samep) const {
@@ -197,6 +198,7 @@ bool AstVarRef::sameNoLvalue(AstVarRef* samep) const {
         return (varScopep() == samep->varScopep());
     } else {
         return (selfPointer() == samep->selfPointer()
+                && classOrPackagep() == samep->classOrPackagep()
                 && (!selfPointer().isEmpty() || !samep->selfPointer().isEmpty())
                 && varp()->name() == samep->varp()->name());
     }
diff --git a/test_regress/t/t_class_eq.py b/test_regress/t/t_class_eq.py
new file mode 100755
index 000000000..bd059b0f2
--- /dev/null
+++ b/test_regress/t/t_class_eq.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_class_eq.v b/test_regress/t/t_class_eq.v
new file mode 100644
index 000000000..d6738ae57
--- /dev/null
+++ b/test_regress/t/t_class_eq.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t();
+
+class A;
+   int num;
+   function new(int num);
+      this.num = num;
+   endfunction
+endclass
+
+class B;
+   static A obj = new(2);
+endclass
+
+class C;
+   static A obj = new(5);
+endclass
+
+   initial begin
+      #1;
+      $display("Bobj=%p Cobj=%p eq=%p", B::obj, C::obj, (B::obj == C::obj));
+      if (B::obj == C::obj) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule