Fix coverage of variables of complex types (#6250)
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@ -3895,6 +3895,7 @@ public:
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AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
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AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
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return new AstNeq{fileline(), lhsp, rhsp};
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return new AstNeq{fileline(), lhsp, rhsp};
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}
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}
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static AstNodeBiop* newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp);
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void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
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void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
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out.opNeq(lhs, rhs);
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out.opNeq(lhs, rhs);
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}
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}
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@ -317,6 +317,16 @@ AstNodeBiop* AstEqWild::newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* r
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}
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}
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}
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}
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AstNodeBiop* AstNeq::newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp) {
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if (lhsp->isString() && rhsp->isString()) {
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return new AstNeqN{fl, lhsp, rhsp};
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} else if (lhsp->isDouble() && rhsp->isDouble()) {
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return new AstNeqD{fl, lhsp, rhsp};
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} else {
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return new AstNeq{fl, lhsp, rhsp};
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}
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}
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AstExecGraph::AstExecGraph(FileLine* fileline, const string& name) VL_MT_DISABLED
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AstExecGraph::AstExecGraph(FileLine* fileline, const string& name) VL_MT_DISABLED
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: ASTGEN_SUPER_ExecGraph(fileline),
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: ASTGEN_SUPER_ExecGraph(fileline),
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m_depGraphp{new V3Graph},
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m_depGraphp{new V3Graph},
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@ -111,7 +111,7 @@ class ClockVisitor final : public VNVisitor {
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= VN_CAST(origp->dtypep()->skipRefp(), BasicDType)) {
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= VN_CAST(origp->dtypep()->skipRefp(), BasicDType)) {
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if (!bdtypep->isOpaque()) comparedp = new AstXor{nodep->fileline(), origp, changeRdp};
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if (!bdtypep->isOpaque()) comparedp = new AstXor{nodep->fileline(), origp, changeRdp};
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}
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}
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if (!comparedp) comparedp = AstEq::newTyped(nodep->fileline(), origp, changeRdp);
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if (!comparedp) comparedp = AstNeq::newTyped(nodep->fileline(), origp, changeRdp);
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AstIf* const newp = new AstIf{nodep->fileline(), comparedp, incp};
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AstIf* const newp = new AstIf{nodep->fileline(), comparedp, incp};
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// We could add another IF to detect posedges, and only increment if so.
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// We could add another IF to detect posedges, and only increment if so.
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// It's another whole branch though versus a potential memory miss.
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// It's another whole branch though versus a potential memory miss.
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@ -5,6 +5,8 @@
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// any use, without warranty, 2008 by Wilson Snyder.
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// SPDX-License-Identifier: CC0-1.0
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typedef struct packed {logic a;} str_logic;
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module t (/*AUTOARG*/
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module t (/*AUTOARG*/
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// Inputs
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// Inputs
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clk, check_real, check_array_real, check_string
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clk, check_real, check_array_real, check_string
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@ -27,6 +29,8 @@
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%000002 str_t stoggle; initial stoggle='0;
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%000002 str_t stoggle; initial stoggle='0;
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000019 str_logic strl; initial strl='0;
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union {
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union {
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real val1; // TODO use bit [7:0] here
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real val1; // TODO use bit [7:0] here
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real val2; // TODO use bit [3:0] here
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real val2; // TODO use bit [3:0] here
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@ -45,6 +49,8 @@
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} str_queue_t;
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} str_queue_t;
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str_queue_t str_queue;
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str_queue_t str_queue;
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assign strl.a = clk;
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alpha a1 (/*AUTOINST*/
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alpha a1 (/*AUTOINST*/
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// Outputs
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// Outputs
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.toggle_up (toggle_up),
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.toggle_up (toggle_up),
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@ -80,6 +86,11 @@
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.clk (clk),
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.clk (clk),
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.toggle (toggle));
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.toggle (toggle));
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mod_struct i_mod_struct (/*AUTOINST*/
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// Inputs
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.input_struct (strl));
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%000001 reg [1:0] memory[121:110];
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%000001 reg [1:0] memory[121:110];
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wire [1023:0] largeish = {992'h0, cyc};
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wire [1023:0] largeish = {992'h0, cyc};
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@ -209,3 +220,11 @@
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end
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end
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endmodule
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endmodule
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module mod_struct(/*AUTOARG*/
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// Inputs
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input_struct
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);
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000019 input str_logic input_struct;
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endmodule
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@ -4,6 +4,8 @@
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// any use, without warranty, 2008 by Wilson Snyder.
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// SPDX-License-Identifier: CC0-1.0
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typedef struct packed {logic a;} str_logic;
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module t (/*AUTOARG*/
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module t (/*AUTOARG*/
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// Inputs
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// Inputs
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clk, check_real, check_array_real, check_string
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clk, check_real, check_array_real, check_string
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@ -26,6 +28,8 @@ module t (/*AUTOARG*/
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str_t stoggle; initial stoggle='0;
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str_t stoggle; initial stoggle='0;
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str_logic strl; initial strl='0;
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union {
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union {
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real val1; // TODO use bit [7:0] here
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real val1; // TODO use bit [7:0] here
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real val2; // TODO use bit [3:0] here
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real val2; // TODO use bit [3:0] here
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@ -44,6 +48,8 @@ module t (/*AUTOARG*/
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} str_queue_t;
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} str_queue_t;
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str_queue_t str_queue;
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str_queue_t str_queue;
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assign strl.a = clk;
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alpha a1 (/*AUTOINST*/
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alpha a1 (/*AUTOINST*/
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// Outputs
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// Outputs
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.toggle_up (toggle_up),
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.toggle_up (toggle_up),
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@ -79,6 +85,11 @@ module t (/*AUTOARG*/
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.clk (clk),
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.clk (clk),
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.toggle (toggle));
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.toggle (toggle));
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mod_struct i_mod_struct (/*AUTOINST*/
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// Inputs
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.input_struct (strl));
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reg [1:0] memory[121:110];
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reg [1:0] memory[121:110];
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wire [1023:0] largeish = {992'h0, cyc};
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wire [1023:0] largeish = {992'h0, cyc};
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@ -207,3 +218,11 @@ module param #(parameter P = 2) (/*AUTOARG*/
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assign z = 1;
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assign z = 1;
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end
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end
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endmodule
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endmodule
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module mod_struct(/*AUTOARG*/
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// Inputs
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input_struct
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);
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input str_logic input_struct;
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endmodule
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@ -5,6 +5,8 @@
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// any use, without warranty, 2008 by Wilson Snyder.
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// SPDX-License-Identifier: CC0-1.0
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typedef struct packed {logic a;} str_logic;
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module t (/*AUTOARG*/
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module t (/*AUTOARG*/
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// Inputs
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// Inputs
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clk, check_real, check_array_real, check_string
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clk, check_real, check_array_real, check_string
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@ -31,6 +33,9 @@
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-000002 point: comment=stoggle.b hier=top.t
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-000002 point: comment=stoggle.b hier=top.t
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-000002 point: comment=stoggle.u.ua hier=top.t
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-000002 point: comment=stoggle.u.ua hier=top.t
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000019 str_logic strl; initial strl='0;
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+000019 point: comment=strl.a hier=top.t
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union {
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union {
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real val1; // TODO use bit [7:0] here
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real val1; // TODO use bit [7:0] here
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real val2; // TODO use bit [3:0] here
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real val2; // TODO use bit [3:0] here
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@ -62,6 +67,8 @@
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} str_queue_t;
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} str_queue_t;
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str_queue_t str_queue;
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str_queue_t str_queue;
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assign strl.a = clk;
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alpha a1 (/*AUTOINST*/
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alpha a1 (/*AUTOINST*/
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// Outputs
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// Outputs
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.toggle_up (toggle_up),
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.toggle_up (toggle_up),
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@ -97,6 +104,11 @@
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.clk (clk),
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.clk (clk),
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.toggle (toggle));
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.toggle (toggle));
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mod_struct i_mod_struct (/*AUTOINST*/
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// Inputs
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.input_struct (strl));
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%000001 reg [1:0] memory[121:110];
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%000001 reg [1:0] memory[121:110];
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-000001 point: comment=memory[110][0] hier=top.t
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-000001 point: comment=memory[110][0] hier=top.t
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-000000 point: comment=memory[110][1] hier=top.t
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-000000 point: comment=memory[110][1] hier=top.t
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@ -301,3 +313,12 @@
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end
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end
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endmodule
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endmodule
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module mod_struct(/*AUTOARG*/
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// Inputs
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input_struct
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);
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000019 input str_logic input_struct;
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+000019 point: comment=input_struct.a hier=top.t.i_mod_struct
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endmodule
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