From f9bdab65f0988d44335b6567cc96e900ef0a98fd Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Fri, 1 Aug 2025 13:24:18 +0200 Subject: [PATCH] Fix coverage of variables of complex types (#6250) --- src/V3AstNodeExpr.h | 1 + src/V3AstNodes.cpp | 10 ++++++++++ src/V3Clock.cpp | 2 +- test_regress/t/t_cover_toggle.out | 19 +++++++++++++++++++ test_regress/t/t_cover_toggle.v | 19 +++++++++++++++++++ test_regress/t/t_cover_toggle__points.out | 21 +++++++++++++++++++++ 6 files changed, 71 insertions(+), 1 deletion(-) diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index 851f9e7f4..dbc9932f3 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -3895,6 +3895,7 @@ public: AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override { return new AstNeq{fileline(), lhsp, rhsp}; } + static AstNodeBiop* newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp); void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { out.opNeq(lhs, rhs); } diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index d2184cab0..a8b488648 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -317,6 +317,16 @@ AstNodeBiop* AstEqWild::newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* r } } +AstNodeBiop* AstNeq::newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp) { + if (lhsp->isString() && rhsp->isString()) { + return new AstNeqN{fl, lhsp, rhsp}; + } else if (lhsp->isDouble() && rhsp->isDouble()) { + return new AstNeqD{fl, lhsp, rhsp}; + } else { + return new AstNeq{fl, lhsp, rhsp}; + } +} + AstExecGraph::AstExecGraph(FileLine* fileline, const string& name) VL_MT_DISABLED : ASTGEN_SUPER_ExecGraph(fileline), m_depGraphp{new V3Graph}, diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp index 72e78ad57..b9d2e2c6f 100644 --- a/src/V3Clock.cpp +++ b/src/V3Clock.cpp @@ -111,7 +111,7 @@ class ClockVisitor final : public VNVisitor { = VN_CAST(origp->dtypep()->skipRefp(), BasicDType)) { if (!bdtypep->isOpaque()) comparedp = new AstXor{nodep->fileline(), origp, changeRdp}; } - if (!comparedp) comparedp = AstEq::newTyped(nodep->fileline(), origp, changeRdp); + if (!comparedp) comparedp = AstNeq::newTyped(nodep->fileline(), origp, changeRdp); AstIf* const newp = new AstIf{nodep->fileline(), comparedp, incp}; // We could add another IF to detect posedges, and only increment if so. // It's another whole branch though versus a potential memory miss. diff --git a/test_regress/t/t_cover_toggle.out b/test_regress/t/t_cover_toggle.out index d68a87d6d..29a7dc0a1 100644 --- a/test_regress/t/t_cover_toggle.out +++ b/test_regress/t/t_cover_toggle.out @@ -5,6 +5,8 @@ // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 + typedef struct packed {logic a;} str_logic; + module t (/*AUTOARG*/ // Inputs clk, check_real, check_array_real, check_string @@ -27,6 +29,8 @@ %000002 str_t stoggle; initial stoggle='0; + 000019 str_logic strl; initial strl='0; + union { real val1; // TODO use bit [7:0] here real val2; // TODO use bit [3:0] here @@ -45,6 +49,8 @@ } str_queue_t; str_queue_t str_queue; + assign strl.a = clk; + alpha a1 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), @@ -80,6 +86,11 @@ .clk (clk), .toggle (toggle)); + mod_struct i_mod_struct (/*AUTOINST*/ + // Inputs + .input_struct (strl)); + + %000001 reg [1:0] memory[121:110]; wire [1023:0] largeish = {992'h0, cyc}; @@ -209,3 +220,11 @@ end endmodule + module mod_struct(/*AUTOARG*/ + // Inputs + input_struct + ); + + 000019 input str_logic input_struct; + endmodule + diff --git a/test_regress/t/t_cover_toggle.v b/test_regress/t/t_cover_toggle.v index 1590a813c..e41aa437a 100644 --- a/test_regress/t/t_cover_toggle.v +++ b/test_regress/t/t_cover_toggle.v @@ -4,6 +4,8 @@ // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +typedef struct packed {logic a;} str_logic; + module t (/*AUTOARG*/ // Inputs clk, check_real, check_array_real, check_string @@ -26,6 +28,8 @@ module t (/*AUTOARG*/ str_t stoggle; initial stoggle='0; + str_logic strl; initial strl='0; + union { real val1; // TODO use bit [7:0] here real val2; // TODO use bit [3:0] here @@ -44,6 +48,8 @@ module t (/*AUTOARG*/ } str_queue_t; str_queue_t str_queue; + assign strl.a = clk; + alpha a1 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), @@ -79,6 +85,11 @@ module t (/*AUTOARG*/ .clk (clk), .toggle (toggle)); + mod_struct i_mod_struct (/*AUTOINST*/ + // Inputs + .input_struct (strl)); + + reg [1:0] memory[121:110]; wire [1023:0] largeish = {992'h0, cyc}; @@ -207,3 +218,11 @@ module param #(parameter P = 2) (/*AUTOARG*/ assign z = 1; end endmodule + +module mod_struct(/*AUTOARG*/ + // Inputs + input_struct + ); + + input str_logic input_struct; +endmodule diff --git a/test_regress/t/t_cover_toggle__points.out b/test_regress/t/t_cover_toggle__points.out index f73846a2f..144f94d9f 100644 --- a/test_regress/t/t_cover_toggle__points.out +++ b/test_regress/t/t_cover_toggle__points.out @@ -5,6 +5,8 @@ // any use, without warranty, 2008 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 + typedef struct packed {logic a;} str_logic; + module t (/*AUTOARG*/ // Inputs clk, check_real, check_array_real, check_string @@ -31,6 +33,9 @@ -000002 point: comment=stoggle.b hier=top.t -000002 point: comment=stoggle.u.ua hier=top.t + 000019 str_logic strl; initial strl='0; ++000019 point: comment=strl.a hier=top.t + union { real val1; // TODO use bit [7:0] here real val2; // TODO use bit [3:0] here @@ -62,6 +67,8 @@ } str_queue_t; str_queue_t str_queue; + assign strl.a = clk; + alpha a1 (/*AUTOINST*/ // Outputs .toggle_up (toggle_up), @@ -97,6 +104,11 @@ .clk (clk), .toggle (toggle)); + mod_struct i_mod_struct (/*AUTOINST*/ + // Inputs + .input_struct (strl)); + + %000001 reg [1:0] memory[121:110]; -000001 point: comment=memory[110][0] hier=top.t -000000 point: comment=memory[110][1] hier=top.t @@ -301,3 +313,12 @@ end endmodule + module mod_struct(/*AUTOARG*/ + // Inputs + input_struct + ); + + 000019 input str_logic input_struct; ++000019 point: comment=input_struct.a hier=top.t.i_mod_struct + endmodule +