From f9adc3461d0c1e4ed60530c59ff1b7cfb0fa1a1b Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 27 Oct 2025 19:16:53 -0400 Subject: [PATCH] Tests: Fix coverage holes from t_dist_docs_options --- src/V3Const.cpp | 9 ++++--- test_regress/t/t_alw_reorder_no_acycsimp.py | 19 ++++++++++++++ test_regress/t/t_case_huge.py | 15 +++++------ test_regress/t/t_case_huge_nocase.py | 21 ++++++++++++++++ test_regress/t/t_dist_docs_options.py | 7 +----- ...llarray.py => t_opt_assemble_cellarray.py} | 1 + ...cellarray.v => t_opt_assemble_cellarray.v} | 0 .../t/t_opt_assemble_cellarray_off.py | 19 ++++++++++++++ .../{t_merge_cond.py => t_opt_merge_cond.py} | 0 .../t/{t_merge_cond.v => t_opt_merge_cond.v} | 0 ...d_blowup.py => t_opt_merge_cond_blowup.py} | 0 ...ond_blowup.v => t_opt_merge_cond_blowup.v} | 0 ...g_3409.py => t_opt_merge_cond_bug_3409.py} | 0 ...bug_3409.v => t_opt_merge_cond_bug_3409.v} | 0 ...h.py => t_opt_merge_cond_motion_branch.py} | 0 ...nch.v => t_opt_merge_cond_motion_branch.v} | 0 ...xtend.py => t_opt_merge_cond_no_extend.py} | 0 ..._extend.v => t_opt_merge_cond_no_extend.v} | 0 test_regress/t/t_opt_merge_cond_no_merge.py | 25 +++++++++++++++++++ ...otion.py => t_opt_merge_cond_no_motion.py} | 2 +- test_regress/t/t_opt_subst_off.py | 2 +- 21 files changed, 102 insertions(+), 18 deletions(-) create mode 100755 test_regress/t/t_alw_reorder_no_acycsimp.py create mode 100755 test_regress/t/t_case_huge_nocase.py rename test_regress/t/{t_cellarray.py => t_opt_assemble_cellarray.py} (88%) rename test_regress/t/{t_cellarray.v => t_opt_assemble_cellarray.v} (100%) create mode 100755 test_regress/t/t_opt_assemble_cellarray_off.py rename test_regress/t/{t_merge_cond.py => t_opt_merge_cond.py} (100%) rename test_regress/t/{t_merge_cond.v => t_opt_merge_cond.v} (100%) rename test_regress/t/{t_merge_cond_blowup.py => t_opt_merge_cond_blowup.py} (100%) rename test_regress/t/{t_merge_cond_blowup.v => t_opt_merge_cond_blowup.v} (100%) rename test_regress/t/{t_merge_cond_bug_3409.py => t_opt_merge_cond_bug_3409.py} (100%) rename test_regress/t/{t_merge_cond_bug_3409.v => t_opt_merge_cond_bug_3409.v} (100%) rename test_regress/t/{t_merge_cond_motion_branch.py => t_opt_merge_cond_motion_branch.py} (100%) rename test_regress/t/{t_merge_cond_motion_branch.v => t_opt_merge_cond_motion_branch.v} (100%) rename test_regress/t/{t_merge_cond_no_extend.py => t_opt_merge_cond_no_extend.py} (100%) rename test_regress/t/{t_merge_cond_no_extend.v => t_opt_merge_cond_no_extend.v} (100%) create mode 100755 test_regress/t/t_opt_merge_cond_no_merge.py rename test_regress/t/{t_merge_cond_no_motion.py => t_opt_merge_cond_no_motion.py} (95%) diff --git a/src/V3Const.cpp b/src/V3Const.cpp index f00476ff6..a90f1e6e6 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -934,6 +934,7 @@ class ConstVisitor final : public VNVisitor { const AstNode* m_scopep = nullptr; // Current scope const AstAttrOf* m_attrp = nullptr; // Current attribute VDouble0 m_statBitOpReduction; // Ops reduced in ConstBitOpTreeVisitor + VDouble0 m_statConcatMerge; // Concat merges VDouble0 m_statCondExprRedundant; // Conditional repeated expressions VDouble0 m_statIfCondExprRedundant; // Conditional repeated expressions const bool m_globalPass; // ConstVisitor invoked as a global pass @@ -1625,9 +1626,9 @@ class ConstVisitor final : public VNVisitor { return (rend == lstart->toSInt()); } bool ifMergeAdjacent(const AstNodeExpr* lhsp, const AstNodeExpr* rhsp) { - // called by concatmergeable to determine if {lhsp, rhsp} make sense + // Called by concatmergeable to determine if {lhsp, rhsp} make sense if (!v3Global.opt.fAssemble()) return false; // opt disabled - // two same varref + // Two same varref if (operandsSame(lhsp, rhsp)) return true; const AstSel* const lselp = VN_CAST(lhsp, Sel); const AstSel* const rselp = VN_CAST(rhsp, Sel); @@ -1660,7 +1661,7 @@ class ConstVisitor final : public VNVisitor { return false; } bool concatMergeable(const AstNodeExpr* lhsp, const AstNodeExpr* rhsp, unsigned depth) { - // determine if {a OP b, c OP d} => {a, c} OP {b, d} is advantageous + // Determine if {a OP b, c OP d} => {a, c} OP {b, d} is advantageous if (!v3Global.opt.fAssemble()) return false; // opt disabled if (lhsp->type() != rhsp->type()) return false; if (!ifConcatMergeableBiop(lhsp)) return false; @@ -1967,6 +1968,7 @@ class ConstVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(lrp), lrp); lp->dtypeChgWidthSigned(newlp->width(), newlp->width(), VSigning::UNSIGNED); UINFO(5, "merged " << nodep); + ++m_statConcatMerge; VL_DO_DANGLING(pushDeletep(rp->unlinkFrBack()), rp); nodep->replaceWithKeepDType(lp->unlinkFrBack()); VL_DO_DANGLING(pushDeletep(nodep), nodep); @@ -4135,6 +4137,7 @@ public: V3Stats::addStatSum("Optimizations, Cond redundant expressions", m_statCondExprRedundant); V3Stats::addStatSum("Optimizations, If cond redundant expressions", m_statIfCondExprRedundant); + V3Stats::addStatSum("Optimizations, Concat merges", m_statConcatMerge); } AstNode* mainAcceptEdit(AstNode* nodep) { diff --git a/test_regress/t/t_alw_reorder_no_acycsimp.py b/test_regress/t/t_alw_reorder_no_acycsimp.py new file mode 100755 index 000000000..2b1eb20e1 --- /dev/null +++ b/test_regress/t/t_alw_reorder_no_acycsimp.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = 't/t_alw_reorder.v' + +test.compile(verilator_flags2=["--stats", "-fno-acyc-simp"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_huge.py b/test_regress/t/t_case_huge.py index 7b6f76fea..f255824ab 100755 --- a/test_regress/t/t_case_huge.py +++ b/test_regress/t/t_case_huge.py @@ -13,13 +13,14 @@ test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) -if test.vlt: - test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 10) - test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', 8) -elif test.vltmt: - test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 10) - test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', 9) - test.execute() +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Cases parallelized\s+(\d+)', 11) + test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', 8) + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 10) +elif test.vltmt: + test.file_grep(test.stats, r'Optimizations, Combined CFuncs\s+(\d+)', 9) + test.file_grep(test.stats, r'Optimizations, Tables created\s+(\d+)', 10) + test.passes() diff --git a/test_regress/t/t_case_huge_nocase.py b/test_regress/t/t_case_huge_nocase.py new file mode 100755 index 000000000..27639ae10 --- /dev/null +++ b/test_regress/t/t_case_huge_nocase.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.top_filename = 't/t_case_huge.v' + +test.compile(verilator_flags2=["--stats -fno-case"]) + +test.execute() + +test.file_grep(test.stats, r'Optimizations, Cases parallelized\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_dist_docs_options.py b/test_regress/t/t_dist_docs_options.py index 0d034c49a..a454012da 100755 --- a/test_regress/t/t_dist_docs_options.py +++ b/test_regress/t/t_dist_docs_options.py @@ -29,14 +29,9 @@ Test_Waivers = [ '-gdb', # Covered: no way to test, part of --gdbbt '-rr', # Not testing; not requiring rr installation # Need testing: - '-facyc-simp', # Need test of -fno-... - '-fassemble', # Need test of -fno-... - '-fcase', # Need test of -fno-... - '-fconst', # Need test of -fno-... + '-fconst', # TODO breaks due to some needed V3Const steps '-fdfg-peephole', # Need test of -fno-... '-fdfg-peephole-', # Need test of -fno-... - '-fmerge-cond', # Need test of -fno-... - '-fsubst-const', # Need test of -fno-... ] Sums = {} diff --git a/test_regress/t/t_cellarray.py b/test_regress/t/t_opt_assemble_cellarray.py similarity index 88% rename from test_regress/t/t_cellarray.py rename to test_regress/t/t_opt_assemble_cellarray.py index 402425622..3c81426dd 100755 --- a/test_regress/t/t_cellarray.py +++ b/test_regress/t/t_opt_assemble_cellarray.py @@ -17,5 +17,6 @@ test.execute() if test.vlt_all: test.file_grep(test.stats, r'Optimizations, Gate assign merged\s+(\d+)', 28) + test.file_grep(test.stats, r'Optimizations, Concat merges\s+(\d+)', 42) test.passes() diff --git a/test_regress/t/t_cellarray.v b/test_regress/t/t_opt_assemble_cellarray.v similarity index 100% rename from test_regress/t/t_cellarray.v rename to test_regress/t/t_opt_assemble_cellarray.v diff --git a/test_regress/t/t_opt_assemble_cellarray_off.py b/test_regress/t/t_opt_assemble_cellarray_off.py new file mode 100755 index 000000000..52d34ad88 --- /dev/null +++ b/test_regress/t/t_opt_assemble_cellarray_off.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.top_filename = "t/t_opt_life.v" + +test.compile(verilator_flags2=['--stats', '-fno-assemble']) + +test.file_grep_not(test.stats, r'Optimizations, Concat merges\s+(\d+)') + +test.passes() diff --git a/test_regress/t/t_merge_cond.py b/test_regress/t/t_opt_merge_cond.py similarity index 100% rename from test_regress/t/t_merge_cond.py rename to test_regress/t/t_opt_merge_cond.py diff --git a/test_regress/t/t_merge_cond.v b/test_regress/t/t_opt_merge_cond.v similarity index 100% rename from test_regress/t/t_merge_cond.v rename to test_regress/t/t_opt_merge_cond.v diff --git a/test_regress/t/t_merge_cond_blowup.py b/test_regress/t/t_opt_merge_cond_blowup.py similarity index 100% rename from test_regress/t/t_merge_cond_blowup.py rename to test_regress/t/t_opt_merge_cond_blowup.py diff --git a/test_regress/t/t_merge_cond_blowup.v b/test_regress/t/t_opt_merge_cond_blowup.v similarity index 100% rename from test_regress/t/t_merge_cond_blowup.v rename to test_regress/t/t_opt_merge_cond_blowup.v diff --git a/test_regress/t/t_merge_cond_bug_3409.py b/test_regress/t/t_opt_merge_cond_bug_3409.py similarity index 100% rename from test_regress/t/t_merge_cond_bug_3409.py rename to test_regress/t/t_opt_merge_cond_bug_3409.py diff --git a/test_regress/t/t_merge_cond_bug_3409.v b/test_regress/t/t_opt_merge_cond_bug_3409.v similarity index 100% rename from test_regress/t/t_merge_cond_bug_3409.v rename to test_regress/t/t_opt_merge_cond_bug_3409.v diff --git a/test_regress/t/t_merge_cond_motion_branch.py b/test_regress/t/t_opt_merge_cond_motion_branch.py similarity index 100% rename from test_regress/t/t_merge_cond_motion_branch.py rename to test_regress/t/t_opt_merge_cond_motion_branch.py diff --git a/test_regress/t/t_merge_cond_motion_branch.v b/test_regress/t/t_opt_merge_cond_motion_branch.v similarity index 100% rename from test_regress/t/t_merge_cond_motion_branch.v rename to test_regress/t/t_opt_merge_cond_motion_branch.v diff --git a/test_regress/t/t_merge_cond_no_extend.py b/test_regress/t/t_opt_merge_cond_no_extend.py similarity index 100% rename from test_regress/t/t_merge_cond_no_extend.py rename to test_regress/t/t_opt_merge_cond_no_extend.py diff --git a/test_regress/t/t_merge_cond_no_extend.v b/test_regress/t/t_opt_merge_cond_no_extend.v similarity index 100% rename from test_regress/t/t_merge_cond_no_extend.v rename to test_regress/t/t_opt_merge_cond_no_extend.v diff --git a/test_regress/t/t_opt_merge_cond_no_merge.py b/test_regress/t/t_opt_merge_cond_no_merge.py new file mode 100755 index 000000000..43bbd8373 --- /dev/null +++ b/test_regress/t/t_opt_merge_cond_no_merge.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_opt_merge_cond.v" + +test.compile(verilator_flags2=["-unroll-count 64", "--stats", "-fno-merge-cond"]) + +test.execute() + +if test.vlt: + # Note, with vltmt this might be split differently, so only checking vlt + test.file_grep_not(test.stats, r'Optimizations, MergeCond merges\s+(\d+)') + test.file_grep_not(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)') + test.file_grep_not(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)') + +test.passes() diff --git a/test_regress/t/t_merge_cond_no_motion.py b/test_regress/t/t_opt_merge_cond_no_motion.py similarity index 95% rename from test_regress/t/t_merge_cond_no_motion.py rename to test_regress/t/t_opt_merge_cond_no_motion.py index 241c21a12..39f083624 100755 --- a/test_regress/t/t_merge_cond_no_motion.py +++ b/test_regress/t/t_opt_merge_cond_no_motion.py @@ -10,7 +10,7 @@ import vltest_bootstrap test.scenarios('vlt_all') -test.top_filename = "t/t_merge_cond.v" +test.top_filename = "t/t_opt_merge_cond.v" test.compile(verilator_flags2=["-unroll-count 64", "--stats", "-fno-merge-cond-motion"]) diff --git a/test_regress/t/t_opt_subst_off.py b/test_regress/t/t_opt_subst_off.py index 526a0ed97..509036fe2 100755 --- a/test_regress/t/t_opt_subst_off.py +++ b/test_regress/t/t_opt_subst_off.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator_st') test.top_filename = "t/t_opt_life.v" -test.compile(verilator_flags2=['--stats', '-fno-subst']) +test.compile(verilator_flags2=['--stats', '-fno-subst', '-fno-subst-const']) if test.vlt_all: test.file_grep_not(test.stats, r'Optimizations, Substituted temps\s+(\d+)')