diff --git a/Changes b/Changes
index 3e4174b62..9ae1a40ee 100644
--- a/Changes
+++ b/Changes
@@ -15,6 +15,14 @@ Verilator 5.051 devel
 
 **Other:**
 
+* Add comments as a branch description in coverage .info files (#7843). [Eryk Szpotanski]
+* Optimize random initialization. [Geza Lore, Testorrent USA, Inc.]
+* Fix DFG misoptimizing bound checks (#7755). [Jakub Michalski]
+* Fix unique0 case side effects (#7787). [Pawel Klopotek]
+* Fix cleaning purity cache after assertions. [Geza Lore, Testorrent USA, Inc.]
+* Fix clang++ ambiguous overload of '==' operator (#7863). [Pawel Kojma, Antmicro Ltd.]
+* Fix heap-use-after-free in `VlRNG::VlRNG()` (#7865). [Dragon-Git]
+
 
 Verilator 5.050 2026-07-01
 ==========================
diff --git a/docs/spelling.txt b/docs/spelling.txt
index a9d91f52b..f99491317 100644
--- a/docs/spelling.txt
+++ b/docs/spelling.txt
@@ -477,6 +477,7 @@ Syms
 Synopsys
 SystemC
 SystemVerilog
+Szpotanski
 Takatsukasa
 Tambe
 Tarik
@@ -537,6 +538,7 @@ Verilog
 Vighnesh
 Viktor
 Vilp
+VlRNG
 VlWide
 Vlip
 Vm
@@ -947,6 +949,7 @@ misconnected
 misconversion
 misdetecting
 misoptimized
+misoptimizing
 missized
 mk
 mno
diff --git a/test_regress/t/t_clang_overload.py b/test_regress/t/t_class_cpp_overload.py
similarity index 100%
rename from test_regress/t/t_clang_overload.py
rename to test_regress/t/t_class_cpp_overload.py
diff --git a/test_regress/t/t_clang_overload.v b/test_regress/t/t_class_cpp_overload.v
similarity index 100%
rename from test_regress/t/t_clang_overload.v
rename to test_regress/t/t_class_cpp_overload.v
diff --git a/test_regress/t/t_unique0_case.v b/test_regress/t/t_unique0_case.v
index 54cedb901..ed3f92535 100644
--- a/test_regress/t/t_unique0_case.v
+++ b/test_regress/t/t_unique0_case.v
@@ -7,7 +7,6 @@
 // verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
-`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
 // verilog_format: on
 
 module t;
@@ -18,7 +17,7 @@ module t;
     y = 0;
     x = 0;
     z = 0;
-    unique0 case(increment_x())
+    unique0 case (increment_x())
       1: begin
         y = 1;
       end