diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index cf1873b6a..8767add80 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -196,6 +196,11 @@ string AstNode::prettyName(const string& namein) VL_PURE { pos += 7; continue; } + if (0 == std::strncmp(pos, "__Viftop", 8)) { + pretty += ""; + pos += 8; + continue; + } if (pos[0] == '_' && pos[1] == '_' && pos[2] == '0' && std::isxdigit(pos[3]) && std::isxdigit(pos[4])) { char value = 0; diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 91a1ab405..524c57bc9 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -1252,6 +1252,7 @@ public: , m_name{name} { this->addVarsp(varsp); } + string verilogKwd() const override { return "modport"; } string name() const override VL_MT_STABLE { return m_name; } bool maybePointedTo() const override VL_MT_SAFE { return true; } ASTGEN_MEMBERS_AstModport; diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index bf4f6aba5..a9c75d9f5 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -726,6 +726,19 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public EmitCBaseVisitorConst { iterateConst(nodep->subDTypep()); // For post's key } } + void visit(AstIfaceRefDType* nodep) override { + if (m_arrayPost) { + puts(" ("); + if (nodep->cellp()) { + iterateConst(nodep->cellp()); + } else { + puts("????"); + } + puts(")"); + return; + } + puts(nodep->ifaceName()); + } void visit(AstRefDType* nodep) override { if (nodep->subDTypep()) { iterateConst(nodep->skipRefp()); @@ -733,6 +746,30 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public EmitCBaseVisitorConst { puts("\n???? // "s + nodep->prettyTypeName() + " -> UNLINKED\n"); } } + void visit(AstModport* nodep) override { + puts(nodep->verilogKwd()); + puts(" "); + puts(nodep->prettyName()); + puts(" (\n"); + if (nodep->varsp()) { + iterateConst(nodep->varsp()); + } else { + puts("????"); + } + puts(");\n"); + } + void visit(AstModportVarRef* nodep) override { + puts(nodep->direction().verilogKwd()); + puts(" "); + if (nodep->varp()) { + VL_RESTORER(m_suppressVarSemi); + m_suppressVarSemi = true; + iterateConst(nodep->varp()); + } else { + puts(nodep->prettyName()); + } + if (nodep->nextp()) puts(", "); + } void visit(AstNodeUOrStructDType* nodep) override { if (m_arrayPost) return; puts(nodep->verilogKwd() + " "); @@ -815,7 +852,7 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public EmitCBaseVisitorConst { } } void visit(AstVarXRef* nodep) override { - putfs(nodep, nodep->dotted()); + putfs(nodep, nodep->prettyName(nodep->dotted())); puts("."); if (nodep->varp()) { puts(nodep->varp()->prettyName()); diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out index 77d14de96..fc093919b 100644 --- a/test_regress/t/t_debug_emitv.out +++ b/test_regress/t/t_debug_emitv.out @@ -37,6 +37,7 @@ module Vt_debug_emitv_t; disable label0; end endfunction + Iface the_ifaces[3:0] (); initial begin begin if ($test$plusargs(40'h48454c4c4f)) begin @@ -70,6 +71,9 @@ module Vt_debug_emitv_t; if ((| downto_32[60:54])) begin $write(""); end + if (the_ifaces[2].ifsig) begin + $write(""); + end end end bit [6:5] [4:3] [2:1] arraymanyd[10:11][12:13][14:15]; @@ -332,7 +336,15 @@ package Vt_debug_emitv___024unit; endfunction endclass endpackage +interface Vt_debug_emitv_Iface; + input logic clk; + logic ifsig; + modport mp ( + input logic ifsig + ); +endinterface module Vt_debug_emitv_sub; + input logic clk; task inc; input int signed i; output int signed o; diff --git a/test_regress/t/t_debug_emitv.v b/test_regress/t/t_debug_emitv.v index c6b1d91b3..c886cb300 100644 --- a/test_regress/t/t_debug_emitv.v +++ b/test_regress/t/t_debug_emitv.v @@ -25,7 +25,9 @@ class Cls; endfunction endclass -interface Iface; +interface Iface ( + input clk +); logic ifsig; modport mp(input ifsig); endinterface @@ -67,6 +69,8 @@ module t (/*AUTOARG*/ return value; endfunction + Iface the_ifaces [3:0] (.*); + initial begin if ($test$plusargs("HELLO")) $display("Hello argument found."); if (Pkg::FOO == 0) $write(""); @@ -80,6 +84,7 @@ module t (/*AUTOARG*/ if (|downto_32[48:40]) $write(""); if (|downto_32[55+:3]) $write(""); if (|downto_32[60-:7]) $write(""); + if (the_ifaces[2].ifsig) $write(""); end bit [6:5][4:3][2:1] arraymanyd[10:11][12:13][14:15]; @@ -117,7 +122,7 @@ module t (/*AUTOARG*/ return v == 0 ? 99 : ~v + 1; endfunction - sub sub(); + sub sub(.*); initial begin int other; @@ -251,7 +256,7 @@ module t (/*AUTOARG*/ end endmodule -module sub(); +module sub(input logic clk); task inc(input int i, output int o); o = {1'b0, i[31:1]} + 32'd1; endtask diff --git a/test_regress/t/t_interface_virtual_bad.out b/test_regress/t/t_interface_virtual_bad.out index 7149f62ba..84ac73793 100644 --- a/test_regress/t/t_interface_virtual_bad.out +++ b/test_regress/t/t_interface_virtual_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_interface_virtual_bad.v:31:12: Operator ASSIGN expected 'PBus' interface on Assign RHS but 'q8__Viftop' is a different interface ('QBus'). +%Error: t/t_interface_virtual_bad.v:31:12: Operator ASSIGN expected 'PBus' interface on Assign RHS but 'q8' is a different interface ('QBus'). : ... note: In instance 't' 31 | v8 = q8; | ^~ @@ -6,7 +6,7 @@ : ... note: In instance 't' 35 | v8 = v8_phy; | ^~~~~~ -%Error: t/t_interface_virtual_bad.v:37:17: Operator ASSIGN expected non-interface on Assign RHS but 'p8__Viftop' is an interface. +%Error: t/t_interface_virtual_bad.v:37:17: Operator ASSIGN expected non-interface on Assign RHS but 'p8' is an interface. : ... note: In instance 't' 37 | data = p8.phy; | ^~~ @@ -18,7 +18,7 @@ : ... note: In instance 't' 39 | data = v8; | ^~ -%Error: t/t_interface_virtual_bad.v:40:14: Operator ASSIGN expected non-interface on Assign RHS but 'p8__Viftop' is an interface. +%Error: t/t_interface_virtual_bad.v:40:14: Operator ASSIGN expected non-interface on Assign RHS but 'p8' is an interface. : ... note: In instance 't' 40 | data = p8; | ^~ diff --git a/test_regress/t/t_interface_wire_bad.out b/test_regress/t/t_interface_wire_bad.out index c792bf9b6..e98a4c000 100644 --- a/test_regress/t/t_interface_wire_bad.out +++ b/test_regress/t/t_interface_wire_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_interface_wire_bad.v:17:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a__Viftop' is an interface. +%Error: t/t_interface_wire_bad.v:17:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a' is an interface. : ... note: In instance 't' 17 | wire wbad = sub.a; | ^ diff --git a/test_regress/t/t_json_only_tag.out b/test_regress/t/t_json_only_tag.out index d0864dfe4..20db5ea20 100644 --- a/test_regress/t/t_json_only_tag.out +++ b/test_regress/t/t_json_only_tag.out @@ -7,7 +7,7 @@ {"type":"VAR","name":"foo_op","addr":"(I)","loc":"d,16:11,16:17","dtypep":"(G)","origName":"foo_op","isSc":false,"isPrimaryIO":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TYPEDEF","name":"my_struct","addr":"(J)","loc":"d,25:6,25:15","dtypep":"(K)","attrPublic":false,"childDTypep": [],"attrsp": []}, {"type":"CELL","name":"itop","addr":"(L)","loc":"d,29:8,29:12","origName":"itop","recursive":false,"modp":"(M)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"VAR","name":"itop__Viftop","addr":"(N)","loc":"d,29:8,29:12","dtypep":"(O)","origName":"itop__Viftop","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"IFACEREF","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"itop","addr":"(N)","loc":"d,29:8,29:12","dtypep":"(O)","origName":"itop__Viftop","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"IFACEREF","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"this_struct","addr":"(P)","loc":"d,31:14,31:25","dtypep":"(Q)","origName":"this_struct","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"VAR","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"dotted","addr":"(R)","loc":"d,33:16,33:22","dtypep":"(S)","origName":"dotted","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"ASSIGNW","name":"","addr":"(T)","loc":"d,33:23,33:24","dtypep":"(S)", diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out index cfc91c506..c342d280c 100644 --- a/test_regress/t/t_xml_tag.out +++ b/test_regress/t/t_xml_tag.out @@ -22,7 +22,7 @@ - +