diff --git a/src/verilog.y b/src/verilog.y index 4231b47fe..3659455db 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1679,8 +1679,7 @@ modportPortsDeclList: // We track the type as with the V2k series of defines, then create as each ID is seen. modportPortsDecl: // // IEEE: modport_simple_ports_declaration - port_direction modportSimplePortOrTFPort { $$ = new AstModportVarRef{$2, *$2, GRAMMARP->m_varIO}; - GRAMMARP->m_modportImpExpActive = false;} + port_direction { GRAMMARP->m_modportImpExpActive = false; } modportSimplePortOrTFPort { $$ = $3; } // // IEEE: modport_clocking_declaration | yCLOCKING idAny/*clocking_identifier*/ { $$ = new AstModportClockingRef{$1, *$2}; } // // IEEE: yIMPORT modport_tf_port @@ -1700,19 +1699,24 @@ modportPortsDecl: { $$ = nullptr; BBUNSUP($1, "Unsupported: Modport export with prototype"); DEL($2); } // Continuations of above after a comma. // // IEEE: modport_simple_ports_declaration - | modportSimplePortOrTFPort { $$ = GRAMMARP->m_modportImpExpActive ? + | modportSimplePortOrTFPort { $$ = $1; } + ; + +modportSimplePortOrTFPort:// IEEE: modport_simple_port or modport_tf_port, depending what keyword was earlier + idAny { $$ = GRAMMARP->m_modportImpExpActive ? static_cast( new AstModportFTaskRef{ $1, *$1, GRAMMARP->m_modportImpExpLastIsExport} ) : static_cast( new AstModportVarRef{ $1, *$1, GRAMMARP->m_varIO} ); } - ; - -modportSimplePortOrTFPort:// IEEE: modport_simple_port or modport_tf_port, depending what keyword was earlier - idAny { $$ = $1; } - | '.' idAny '(' ')' { $$ = $2; BBUNSUP($1, "Unsupported: Modport dotted port name"); } - | '.' idAny '(' expr ')' { $$ = $2; BBUNSUP($1, "Unsupported: Modport dotted port name"); } + | '.' idAny '(' ')' { $$ = static_cast( + new AstModportVarRef{ + $2, *$2, GRAMMARP->m_varIO} ); + BBUNSUP($4, "Unsupported: Modport empty expression"); } + | '.' idAny '(' expr ')' { $$ = static_cast( + new AstModportVarRef{ + $2, *$2, $4, GRAMMARP->m_varIO} ); } ; //************************************************