From f7a06cb54a082408ae47b4e74205586447895c0a Mon Sep 17 00:00:00 2001
From: Julien Margetts <>
Date: Wed, 11 Dec 2019 17:15:45 -0500
Subject: [PATCH] Fix little endian cell ranges, bug1631.

Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
---
 Changes                                |  2 +
 src/V3Inst.cpp                         |  5 +-
 test_regress/t/t_inst_array_connect.pl | 20 ++++++
 test_regress/t/t_inst_array_connect.v  | 85 ++++++++++++++++++++++++++
 4 files changed, 111 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_inst_array_connect.pl
 create mode 100644 test_regress/t/t_inst_array_connect.v

diff --git a/Changes b/Changes
index 254880bea..57f7c9fbf 100644
--- a/Changes
+++ b/Changes
@@ -10,6 +10,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Update FST trace API for better performance.
 
+****  Fix little endian cell ranges, bug1631. [Julien Margetts]
+
 
 * Verilator 4.024 2019-12-08
 
diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index cb62b5055..f35a87478 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -328,8 +328,11 @@ private:
                   <<"  pd="<<pinDim.first<<","<<pinDim.second<<endl);
             if (expDim.first == pinDim.first && expDim.second == pinDim.second+1) {
                 // Connection to array, where array dimensions match the instant dimension
+                AstRange* rangep = VN_CAST(nodep->exprp()->dtypep(), UnpackArrayDType)->rangep();
+                int arraySelNum = rangep->littleEndian()
+                    ? (rangep->elementsConst() - 1 - m_instSelNum) : m_instSelNum;
                 AstNode* exprp = nodep->exprp()->unlinkFrBack();
-                exprp = new AstArraySel(exprp->fileline(), exprp, m_instSelNum);
+                exprp = new AstArraySel(exprp->fileline(), exprp, arraySelNum);
                 nodep->exprp(exprp);
             } else if (expwidth == pinwidth) {
                 // NOP: Arrayed instants: widths match so connect to each instance
diff --git a/test_regress/t/t_inst_array_connect.pl b/test_regress/t/t_inst_array_connect.pl
new file mode 100755
index 000000000..6b3b15be5
--- /dev/null
+++ b/test_regress/t/t_inst_array_connect.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_inst_array_connect.v b/test_regress/t/t_inst_array_connect.v
new file mode 100644
index 000000000..db4995f90
--- /dev/null
+++ b/test_regress/t/t_inst_array_connect.v
@@ -0,0 +1,85 @@
+// DESCRIPTION: Verilator: Verilog Test module for Issue#1631
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Julien Margetts.
+
+module t (/*AUTOARG*/
+   clk
+   );
+   input clk;
+
+   localparam N = 4;
+
+   wire [7:0] cval1[0:N-1];
+   wire [7:0] cval2[N-1:0];
+   wire [7:0] cval3[0:N-1];
+   wire [7:0] cval4[N-1:0];
+
+   wire [3:0] inc;
+
+   assign inc = 4'b0001;
+
+   // verilator lint_off LITENDIAN
+
+   COUNTER UCOUNTER1[N-1:0]
+     (
+      .clk    (clk),
+      .inc    (inc),
+      .o      (cval1) // Twisted
+      );
+
+   COUNTER UCOUNTER2[N-1:0]
+     (
+      .clk    (clk),
+      .inc    (inc),
+      .o      (cval2) // Matches
+      );
+
+   COUNTER UCOUNTER3[0:N-1]
+     (
+      .clk    (clk),
+      .inc    (inc),
+      .o      (cval3) // Matches
+      );
+
+   COUNTER UCOUNTER4[0:N-1]
+     (
+      .clk    (clk),
+      .inc    (inc),
+      .o      (cval4) // Twisted
+      );
+
+   always @(posedge clk) begin
+      if ((cval1[3] != cval2[0]) || (cval3[3] != cval4[0]))
+        $stop;
+
+      if ((cval1[0] + cval1[1] + cval1[2] + cval2[1] + cval2[2] + cval2[3] +
+           cval3[0] + cval3[1] + cval3[2] + cval4[1] + cval4[2] + cval4[3]) != 0)
+        $stop;
+
+`ifdef TEST_VERBOSE
+      $display("%d %d %d %d", cval1[0], cval1[1], cval1[2], cval1[3]);
+      $display("%d %d %d %d", cval2[0], cval2[1], cval2[2], cval2[3]);
+      $display("%d %d %d %d", cval3[0], cval3[1], cval3[2], cval3[3]);
+      $display("%d %d %d %d", cval4[0], cval4[1], cval4[2], cval4[3]);
+`endif
+
+      if (cval1[0] + cval1[3] > 3) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
+
+module COUNTER
+  (
+   input            clk,
+   input            inc,
+   output reg [7:0] o
+   );
+
+   initial o = 8'd0;  // No reset input
+
+   always @(posedge clk) if (inc) o <= o + 1;
+
+endmodule