diff --git a/Changes b/Changes index 1c7cf0e4b..360662687 100644 --- a/Changes +++ b/Changes @@ -46,6 +46,7 @@ Verilator 5.009 devel * Fix -CFLAGS to allow overriding optimization levels (#4140). [Peter Monsson] * Fix false ENUMVALUE on expressions and arrays. * Fix unnecessary verilated_std.sv waivers in --waiver-output. +* Fix missing begin block hierarchy in --xml-only cells section (#4129). [Risto Pejašinović] Verilator 5.008 2023-03-04 diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 40c782fb0..5c6a0ee2c 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -122,6 +122,7 @@ Qingyao Sun Rafal Kapuscik Raynard Qiao Richard Myers +Risto Pejašinović Robert Balas Rupert Swarbrick Ryszard Rozak diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp index 2c2404d44..c3e3cfeac 100644 --- a/src/V3EmitXml.cpp +++ b/src/V3EmitXml.cpp @@ -403,8 +403,8 @@ private: void visit(AstCell* nodep) override { if (nodep->modp()->dead()) return; if (!m_hasChildren) m_os << ">\n"; - m_os << "fileline()->xmlDetailedLocation() << " name=\"" << nodep->name() - << "\"" + m_os << "fileline()->xmlDetailedLocation() + << " name=\"" << nodep->name() << "\"" << " submodname=\"" << nodep->modName() << "\"" << " hier=\"" << m_hier + nodep->name() << "\""; const std::string hier = m_hier; @@ -419,6 +419,11 @@ private: m_hier = hier; m_hasChildren = true; } + void visit(AstBegin* nodep) override { + VL_RESTORER(m_hier); + if (nodep->name() != "") m_hier += nodep->name() + "."; + iterateChildrenConst(nodep); + } //----- void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } diff --git a/test_regress/t/t_xml_begin_hier.out b/test_regress/t/t_xml_begin_hier.out new file mode 100644 index 000000000..0a71073d6 --- /dev/null +++ b/test_regress/t/t_xml_begin_hier.out @@ -0,0 +1,82 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/test_regress/t/t_xml_begin_hier.pl b/test_regress/t/t_xml_begin_hier.pl new file mode 100755 index 000000000..d25c191ff --- /dev/null +++ b/test_regress/t/t_xml_begin_hier.pl @@ -0,0 +1,25 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2012 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; + +compile( + verilator_flags2 => ['--no-std', '--xml-only'], + verilator_make_gmake => 0, + make_top_shell => 0, + make_main => 0, + ); + +files_identical("$out_filename", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_xml_begin_hier.v b/test_regress/t/t_xml_begin_hier.v new file mode 100644 index 000000000..1e29f0133 --- /dev/null +++ b/test_regress/t/t_xml_begin_hier.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Risto Pejasinovic. +// SPDX-License-Identifier: CC0-1.0 + +module submod2 (); +endmodule + +module submod #( +)(); + if(1) begin : submod_gen + wire l1_sig; + if(1) begin : nested_gen + submod2 submod_nested(); + end + submod2 submod_l1(); + end + submod2 submod_l0(); +endmodule + +module test( +); + genvar N; + generate for(N=0; N<2; N=N+1) + begin : FOR_GENERATE + submod submod_for(); + if(1) begin + submod submod_2(); + end + submod submod_3(); + end endgenerate +endmodule