From f77dd16638a708e3218afa5ff120ba1425b6ebe8 Mon Sep 17 00:00:00 2001
From: Mateusz Gancarz <mgancarz@antmicro.com>
Date: Fri, 21 Feb 2025 11:46:51 +0100
Subject: [PATCH] [#73220] add t_trace_array_saif test with golden file

---
 test_regress/t/t_trace_array_saif.out | 51 ++++++++++++++++++---------
 test_regress/t/t_trace_array_saif.py  |  3 +-
 2 files changed, 36 insertions(+), 18 deletions(-)

diff --git a/test_regress/t/t_trace_array_saif.out b/test_regress/t/t_trace_array_saif.out
index fb5e7213f..94e14405a 100644
--- a/test_regress/t/t_trace_array_saif.out
+++ b/test_regress/t/t_trace_array_saif.out
@@ -1,20 +1,37 @@
 (SAIFILE
 (SAIFVERSION "2.0")
 (DIRECTION "backward")
-(DESIGN "foo")
-(PROGRAM_NAME "Verilator")
-(VERSION "5.032")
-(DIVIDER .)
-(TIMESCALE 1ps)
-(DURATION 60)
-(INSTANCE foo (NET
-(d[1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
-(d[2] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
-(d[3] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
-(d[4] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
-(d[32] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
-(cyc[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-(cyc[1] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
-(cyc[2] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
-(clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
-)))
+(DESIGN "t")
+(DIVIDER / )
+(TIMESCALE 1 ps)
+(DURATION 59)
+(INSTANCE top
+  (NET
+    (clk (T0 35) (T1 25) (TX 0) (TC 11))
+  )
+  (INSTANCE t
+    (NET
+      (clk (T0 35) (T1 25) (TX 0) (TC 11))
+      (cyc\[0\] (T0 30) (T1 30) (TX 0) (TC 6))
+      (cyc\[1\] (T0 40) (T1 20) (TX 0) (TC 3))
+      (cyc\[2\] (T0 40) (T1 20) (TX 0) (TC 1))
+    )
+    (INSTANCE biggie
+      (NET
+        (d\[1\] (T0 50) (T1 10) (TX 0) (TC 2))
+        (d\[2\] (T0 50) (T1 10) (TX 0) (TC 2))
+        (d\[3\] (T0 40) (T1 20) (TX 0) (TC 4))
+        (d\[4\] (T0 40) (T1 20) (TX 0) (TC 4))
+        (d\[5\] (T0 30) (T1 30) (TX 0) (TC 6))
+        (d\[6\] (T0 40) (T1 20) (TX 0) (TC 5))
+        (d\[7\] (T0 30) (T1 30) (TX 0) (TC 6))
+        (d\[8\] (T0 40) (T1 20) (TX 0) (TC 5))
+        (d\[9\] (T0 40) (T1 20) (TX 0) (TC 4))
+        (d\[10\] (T0 50) (T1 10) (TX 0) (TC 3))
+        (d\[11\] (T0 50) (T1 10) (TX 0) (TC 2))
+        (d\[12\] (T0 60) (T1 0) (TX 0) (TC 1))
+      )
+    )
+  )
+)
+)
diff --git a/test_regress/t/t_trace_array_saif.py b/test_regress/t/t_trace_array_saif.py
index bba805c29..a12a1eb83 100755
--- a/test_regress/t/t_trace_array_saif.py
+++ b/test_regress/t/t_trace_array_saif.py
@@ -11,8 +11,9 @@ import vltest_bootstrap
 
 test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_saif.out"
 
-test.compile(verilator_flags2=['--cc --trace --trace-structs'])
+test.compile(verilator_flags2=['--cc --trace-saif --trace-structs'])
 
 test.execute()