From f6424431f369e7abb349ff08ede7cc12ecb1e362 Mon Sep 17 00:00:00 2001
From: Peter Monsson <peter@monsson.dk>
Date: Mon, 23 Dec 2019 21:40:36 +0100
Subject: [PATCH] Converting line endings

---
 test_regress/t/t_assert_implication.pl     |  42 ++++----
 test_regress/t/t_assert_implication.v      | 114 ++++++++++-----------
 test_regress/t/t_assert_implication_bad.pl |  52 +++++-----
 3 files changed, 104 insertions(+), 104 deletions(-)

diff --git a/test_regress/t/t_assert_implication.pl b/test_regress/t/t_assert_implication.pl
index ba3cc8981..fd994540c 100644
--- a/test_regress/t/t_assert_implication.pl
+++ b/test_regress/t/t_assert_implication.pl
@@ -1,21 +1,21 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-
-scenarios(simulator => 1);
-
-compile(
-    verilator_flags2 => ['--assert --cc'],
-    );
-
-execute(
-    check_finished => 1,
-    );
-
-ok(1);
-1;
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--assert --cc'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assert_implication.v b/test_regress/t/t_assert_implication.v
index 090d39bdc..aaa63b0ea 100644
--- a/test_regress/t/t_assert_implication.v
+++ b/test_regress/t/t_assert_implication.v
@@ -1,57 +1,57 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2019 by Peter Monsson.
-
-module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
-
-   input clk;
-   integer cyc; initial cyc=1;
-
-   Test test (/*AUTOINST*/
-	      // Inputs
-	      .clk			(clk));
-
-   always @ (posedge clk) begin
-      if (cyc!=0) begin
-         cyc <= cyc + 1;
-         if (cyc==10) begin
-            $write("*-* All Finished *-*\n");
-            $finish;
-         end
-      end
-   end
-
-endmodule
-
-module Test
-  (
-   input clk
-   );
-
-`ifdef FAIL_ASSERT_1
-   assert property (
-     @(posedge clk)
-     1 |-> 0
-   ) else $display("wrong implication");
-`endif
-
-   assert property (
-     @(posedge clk)
-     1 |-> 1
-   );
-
-   assert property (
-     @(posedge clk)
-     0 |-> 0
-   );
-
-   assert property (
-     @(posedge clk)
-     0 |-> 1
-   );
-   
-endmodule
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Peter Monsson.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc; initial cyc=1;
+
+   Test test (/*AUTOINST*/
+	      // Inputs
+	      .clk			(clk));
+
+   always @ (posedge clk) begin
+      if (cyc!=0) begin
+         cyc <= cyc + 1;
+         if (cyc==10) begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+         end
+      end
+   end
+
+endmodule
+
+module Test
+  (
+   input clk
+   );
+
+`ifdef FAIL_ASSERT_1
+   assert property (
+     @(posedge clk)
+     1 |-> 0
+   ) else $display("wrong implication");
+`endif
+
+   assert property (
+     @(posedge clk)
+     1 |-> 1
+   );
+
+   assert property (
+     @(posedge clk)
+     0 |-> 0
+   );
+
+   assert property (
+     @(posedge clk)
+     0 |-> 1
+   );
+   
+endmodule
diff --git a/test_regress/t/t_assert_implication_bad.pl b/test_regress/t/t_assert_implication_bad.pl
index 298ea3366..eb6f2f7e3 100644
--- a/test_regress/t/t_assert_implication_bad.pl
+++ b/test_regress/t/t_assert_implication_bad.pl
@@ -1,26 +1,26 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-
-scenarios(simulator => 1);
-
-top_filename("t/t_assert_implication.v");
-
-compile(
-    v_flags2 => ['+define+FAIL_ASSERT_1'],
-    verilator_flags2 => ['--assert --cc'],
-    );
-
-execute(
-    );
-
-# We expect to get a message when this assert fires:
-file_grep($Self->{run_log_filename}, qr/wrong implication/);
-
-ok(1);
-1;
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+top_filename("t/t_assert_implication.v");
+
+compile(
+    v_flags2 => ['+define+FAIL_ASSERT_1'],
+    verilator_flags2 => ['--assert --cc'],
+    );
+
+execute(
+    );
+
+# We expect to get a message when this assert fires:
+file_grep($Self->{run_log_filename}, qr/wrong implication/);
+
+ok(1);
+1;