From f607b32938c6a732763c9e3685e27adac65a5d8b Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 30 Nov 2012 06:57:36 -0500
Subject: [PATCH] Fix crash on dotted references into dead modules, bug583.

---
 Changes                            |  2 ++
 src/V3LinkDot.cpp                  |  1 +
 test_regress/t/t_param_mem_attr.pl | 15 ++++++++++++
 test_regress/t/t_param_mem_attr.v  | 39 ++++++++++++++++++++++++++++++
 4 files changed, 57 insertions(+)
 create mode 100755 test_regress/t/t_param_mem_attr.pl
 create mode 100644 test_regress/t/t_param_mem_attr.v

diff --git a/Changes b/Changes
index bf384d337..0aad4db52 100644
--- a/Changes
+++ b/Changes
@@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix mis-optimized identical submodule subtract, bug581.  [Charlie Brej]
 
+****  Fix crash on dotted references into dead modules, bug583.  [Jeremy Bennett]
+
 ****  Fix compile issues on MSVCC, bug571, bug577.  [Amir Gonnen]
 
 ****  Fix --debug overriding preceding --dump-treei, bug580.  [Jeremy Bennett]
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index a1e6013a9..ab898c6af 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1484,6 +1484,7 @@ private:
 	}
 	nodep->fromp()->iterateAndNext(*this);
 	nodep->bitp()->iterateAndNext(*this);
+	nodep->attrp()->iterateAndNext(*this);
     }
     virtual void visit(AstBegin* nodep, AstNUser*) {
 	UINFO(5,"   "<<nodep<<endl);
diff --git a/test_regress/t/t_param_mem_attr.pl b/test_regress/t/t_param_mem_attr.pl
new file mode 100755
index 000000000..ba0e9879b
--- /dev/null
+++ b/test_regress/t/t_param_mem_attr.pl
@@ -0,0 +1,15 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+# Compile only test.
+compile (
+	 );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_mem_attr.v b/test_regress/t/t_param_mem_attr.v
new file mode 100644
index 000000000..a4eda3de4
--- /dev/null
+++ b/test_regress/t/t_param_mem_attr.v
@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// A test case for parameterized module.
+//
+// When a module is instantiatied with parameter, there will be two modules in
+// the tree and eventually one will be removed after param and deadifyModules.
+//
+// This test is to check that the removal of dead module will not cause
+// compilation error. Possible error was/is seen as:
+//
+// pure virtual method called
+// terminate called without an active exception
+// %Error: Verilator aborted.  Consider trying --debug --gdbbt
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Jie Xu.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   wire [71:0] ctrl;
+
+   memory #(.words(72)) i_memory (.clk (clk));
+
+   assign ctrl = i_memory.mem[0];
+endmodule
+
+
+// memory module, which is used with parameter
+module memory (clk);
+   input clk;
+
+   parameter words = 16384, bits = 72;
+
+   reg [bits-1 :0] mem[words-1 : 0];
+
+endmodule