diff --git a/Changes b/Changes
index 6adca2a57..7f58bb57a 100644
--- a/Changes
+++ b/Changes
@@ -18,6 +18,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Add error when `resetall inside module (IEEE 2017-22.3).
 
+****  Add cleaner error on version control conflicts in sources.
+
 ****  Fix little endian cell ranges, bug1631. [Julien Margetts]
 
 
diff --git a/src/verilog.l b/src/verilog.l
index a4412d938..4611b66e9 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -958,6 +958,11 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "`verilator_config"                   { FL_FWD; BEGIN VLT; FL_BRK; }
   "`verilog"                            { FL_FWD; BEGIN PARSEP->lastVerilogState(); FL_BRK; }
 
+  /* Errors */
+  "<<<<<<<"[^\n\r]*                     { FL_FWD; yyerrorf("version control conflict marker in file"); FL_BRK; }
+  "======="[^\n\r]*                     { FL_FWD; yyerrorf("version control conflict marker in file"); FL_BRK; }
+  ">>>>>>>"[^\n\r]*                     { FL_FWD; yyerrorf("version control conflict marker in file"); FL_BRK; }
+
   /* If add to this list also add to V3LanguageWords.h */
 }
 
diff --git a/test_regress/t/t_lint_vcmarker_bad.out b/test_regress/t/t_lint_vcmarker_bad.out
new file mode 100644
index 000000000..32354dc42
--- /dev/null
+++ b/test_regress/t/t_lint_vcmarker_bad.out
@@ -0,0 +1,10 @@
+%Error: t/t_lint_vcmarker_bad.v:8: version control conflict marker in file
+<<<<<<< HEAD   
+^~~~~~~~~~~~~~~
+%Error: t/t_lint_vcmarker_bad.v:10: version control conflict marker in file
+=======    
+^~~~~~~~~~~
+%Error: t/t_lint_vcmarker_bad.v:12: version control conflict marker in file
+>>>>>>> MERGE   
+^~~~~~~~~~~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_lint_vcmarker_bad.pl b/test_regress/t/t_lint_vcmarker_bad.pl
new file mode 100755
index 000000000..9832155f2
--- /dev/null
+++ b/test_regress/t/t_lint_vcmarker_bad.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lint_vcmarker_bad.v b/test_regress/t/t_lint_vcmarker_bad.v
new file mode 100644
index 000000000..b959c373a
--- /dev/null
+++ b/test_regress/t/t_lint_vcmarker_bad.v
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+<<<<<<< HEAD  // Intentional test: This conflict marker should be here
+   initial $display("Hello");
+=======   // Intentional test: This conflict marker should be here
+   initial $display("Goodbye");
+>>>>>>> MERGE  // Intentional test: This conflict marker should be here
+
+endmodule