diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index f3fe00acb..ee58f63d5 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -44,6 +44,7 @@ class AstNodeCoverDecl VL_NOT_FINAL : public AstNode { // Coverage counters are emitted in each module object, so duplicate // no-inline instances can keep independent counts for forcePerInstance. int m_localBinNum = 0; // Per-module coverage bin offset + bool m_perInstance = false; // Don't clone during inlining, already per instance public: AstNodeCoverDecl(VNType t, FileLine* fl, const string& page, const string& comment) : AstNode(t, fl) @@ -65,6 +66,8 @@ public: void binNum(int flag) { m_binNum = flag; } int localBinNum() const { return m_localBinNum; } void localBinNum(int flag) { m_localBinNum = flag; } + bool perInstance() const { return m_perInstance; } + void perInstance(bool flag) { m_perInstance = flag; } virtual int size() const = 0; const string& comment() const { return m_text; } // text to insert in code const string& page() const { return m_page; } @@ -74,7 +77,8 @@ public: bool sameNode(const AstNode* samep) const override { const AstNodeCoverDecl* const asamep = VN_DBG_AS(samep, NodeCoverDecl); return (fileline() == asamep->fileline() && hier() == asamep->hier() - && comment() == asamep->comment() && page() == asamep->page()); + && comment() == asamep->comment() && page() == asamep->page() + && perInstance() == asamep->perInstance()); } bool isPredictOptimizable() const override { return false; } void dataDeclp(AstNodeCoverDecl* nodep) { m_dataDeclp = nodep; } @@ -790,6 +794,9 @@ public: string name() const override VL_MT_STABLE { return m_cellp->name(); } bool maybePointedTo() const override VL_MT_SAFE { return true; } AstScope* scopep() const VL_MT_STABLE { return m_scopep; } // Pointer to scope it's under + void scopep(AstScope* nodep) { m_scopep = nodep; } + AstCellInline* cellp() const VL_MT_STABLE { return m_cellp; } // Pointer to the CellInline + void cellp(AstCellInline* nodep) { m_cellp = nodep; } string origModName() const { return m_cellp->origModName(); } // * = modp()->origName() before inlining @@ -1868,7 +1875,9 @@ public: AstNodeModule* modp() const { return m_modp; } // AstScope* aboveScopep() const VL_MT_SAFE { return m_aboveScopep; } + void aboveScopep(AstScope* nodep) { m_aboveScopep = nodep; } AstCell* aboveCellp() const { return m_aboveCellp; } + void aboveCellp(AstCell* nodep) { m_aboveCellp = nodep; } bool isTop() const VL_MT_SAFE { return aboveScopep() == nullptr; } // At top of hierarchy // Create new MODULETEMP variable under this scope AstVarScope* createTemp(const string& name, unsigned width); @@ -2276,7 +2285,6 @@ class AstVar final : public AstNode { bool m_attrSFormat : 1; // User sformat attribute bool m_attrSplitVar : 1; // declared with split_var metacomment bool m_attrFsmState : 1; // declared with fsm_state metacomment - bool m_attrFsmRegisterWrapper : 1; // connected to an fsm_register_wrapper instance bool m_attrFsmResetArc : 1; // declared with fsm_reset_arc metacomment bool m_attrFsmArcInclCond : 1; // declared with fsm_arc_include_cond metacomment bool m_constPoolEntry : 1; // Constant pool variable @@ -2341,7 +2349,6 @@ class AstVar final : public AstNode { m_attrSFormat = false; m_attrSplitVar = false; m_attrFsmState = false; - m_attrFsmRegisterWrapper = false; m_attrFsmResetArc = false; m_attrFsmArcInclCond = false; m_constPoolEntry = false; @@ -2492,7 +2499,6 @@ public: void attrSFormat(bool flag) { m_attrSFormat = flag; } void attrSplitVar(bool flag) { m_attrSplitVar = flag; } void attrFsmState(bool flag) { m_attrFsmState = flag; } - void attrFsmRegisterWrapper(bool flag) { m_attrFsmRegisterWrapper = flag; } void attrFsmResetArc(bool flag) { m_attrFsmResetArc = flag; } void attrFsmArcInclCond(bool flag) { m_attrFsmArcInclCond = flag; } bool constPoolEntry() const { return m_constPoolEntry; } @@ -2661,7 +2667,6 @@ public: bool attrSFormat() const { return m_attrSFormat; } bool attrSplitVar() const { return m_attrSplitVar; } bool attrFsmState() const { return m_attrFsmState; } - bool attrFsmRegisterWrapper() const { return m_attrFsmRegisterWrapper; } bool attrFsmResetArc() const { return m_attrFsmResetArc; } bool attrFsmArcInclCond() const { return m_attrFsmArcInclCond; } AstIface* sensIfacep() const { return m_sensIfacep; } @@ -2685,13 +2690,6 @@ public: lifetime(fromp->lifetime()); } void combineType(const AstVar* otherp); - void inlineAttrReset(const string& name) { - if (direction() == VDirection::INOUT && varType() == VVarType::WIRE) { - m_varType = VVarType::TRIWIRE; - } - m_direction = VDirection::NONE; - m_name = name; - } bool needsCReset() const { return !isIfaceParent() && !isIfaceRef() && !noReset() && !isParam() && !isStatementTemp() && !noCReset() && !(basicp() && basicp()->isEvent()); @@ -2734,6 +2732,7 @@ public: bool sameNode(const AstNode* samep) const override; bool hasDType() const override VL_MT_SAFE { return true; } AstVar* varp() const VL_MT_STABLE { return m_varp; } // [After Link] Pointer to variable + void varp(AstVar* nodep) { m_varp = nodep; } AstScope* scopep() const VL_MT_STABLE { return m_scopep; } // Pointer to scope it's under void scopep(AstScope* nodep) { m_scopep = nodep; } bool isTrace() const { return m_trace; } diff --git a/src/V3AstNodeStmt.h b/src/V3AstNodeStmt.h index c69f71a98..8d042e486 100644 --- a/src/V3AstNodeStmt.h +++ b/src/V3AstNodeStmt.h @@ -549,6 +549,7 @@ public: bool isOutputter() override { return true; } bool isPure() override { return false; } AstNodeCoverDecl* declp() const { return m_declp; } // Where defined + void declp(AstNodeCoverDecl* nodep) { m_declp = nodep; } }; class AstCoverToggle final : public AstNodeStmt { // Toggle analysis of given signal diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index c5c177958..7d5400ef0 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -2099,6 +2099,7 @@ bool AstNodeCCall::isPure() { return funcp()->dpiPure(); } void AstNodeCoverDecl::dump(std::ostream& str) const { Super::dump(str); if (localBinNum()) str << " lbin=" << localBinNum(); + if (perInstance()) str << " [PERINST]"; if (!page().empty()) str << " page=" << page(); if (!hier().empty()) str << " hier=" << hier(); if (this->dataDeclNullp()) { @@ -2118,6 +2119,7 @@ void AstNodeCoverDecl::dump(std::ostream& str) const { void AstNodeCoverDecl::dumpJson(std::ostream& str) const { dumpJsonNumFunc(str, binNum); dumpJsonNumFunc(str, localBinNum); + dumpJsonBoolFuncIf(str, perInstance); dumpJsonStrFunc(str, page); dumpJsonStrFunc(str, hier); dumpJsonGen(str); diff --git a/src/V3FsmDetect.cpp b/src/V3FsmDetect.cpp index ef7c64162..89f027914 100644 --- a/src/V3FsmDetect.cpp +++ b/src/V3FsmDetect.cpp @@ -1001,28 +1001,19 @@ class FsmDetectVisitor final : public VNVisitor { return assp; } + // Match 'state = reset ? CONST : next', an active high reset folded into the commit static AstNodeAssign* directCondStateVarAssign(AstNode* nodep, AstVarScope*& stateVscp, AstVarScope*& fromVscp, AstNodeExpr*& condp, - bool& resetActiveLow, FsmStateValue& resetValue) { AstNodeAssign* const assp = VN_CAST(nodep, NodeAssign); if (!assp) return nullptr; AstVarRef* const lhsp = VN_CAST(assp->lhsp()->baseFromp(true), VarRef); AstCond* const rhsp = VN_CAST(assp->rhsp(), Cond); if (!rhsp || !lhsp) return nullptr; - if (AstVarRef* const elsep = VN_CAST(rhsp->elsep(), VarRef)) { - if (constValueStatus(rhsp->thenp(), resetValue) != ConstValueStatus::OK) - return nullptr; - fromVscp = elsep->varScopep(); - resetActiveLow = false; - } else if (AstVarRef* const thenp = VN_CAST(rhsp->thenp(), VarRef)) { - if (constValueStatus(rhsp->elsep(), resetValue) != ConstValueStatus::OK) - return nullptr; - fromVscp = thenp->varScopep(); - resetActiveLow = true; - } else { - return nullptr; - } + AstVarRef* const elsep = VN_CAST(rhsp->elsep(), VarRef); + if (!elsep) return nullptr; + if (constValueStatus(rhsp->thenp(), resetValue) != ConstValueStatus::OK) return nullptr; + fromVscp = elsep->varScopep(); stateVscp = lhsp->varScopep(); condp = rhsp->condp(); return assp; @@ -1435,19 +1426,12 @@ class FsmDetectVisitor final : public VNVisitor { cand.hasResetCond(cand.resetCond().varScopep != nullptr); } else { AstNodeExpr* resetCondp = nullptr; - bool resetActiveLow = false; FsmStateValue resetValue; - if (AstNodeAssign* const assp = directCondStateVarAssign( - nodep, stateVscp, nextVscp, resetCondp, resetActiveLow, resetValue)) { - // Inlined wrappers can normalize into a compact active-low - // assignment form that earlier direct-register FSM support did - // not accept. The pre-inline marker is the architectural fence: - // it lets wrapper-derived registers use that shape without - // changing the meaning of unrelated legacy RTL. - if (resetActiveLow && !stateVscp->varp()->attrFsmRegisterWrapper()) return false; + // Note the active low 'reset ? next : CONST' form is not accepted + if (AstNodeAssign* const assp + = directCondStateVarAssign(nodep, stateVscp, nextVscp, resetCondp, resetValue)) { cand.resetArcs().emplace_back(resetValue, assp); cand.resetCond() = describeResetCond(resetCondp); - cand.resetCond().activeLow = resetActiveLow; cand.hasResetCond(cand.resetCond().varScopep != nullptr); } else if (!nodeStateVarAssign(nodep, stateVscp, nextVscp)) { return false; @@ -2193,6 +2177,8 @@ class FsmLowerVisitor final { graph.stateVarName(), "", statep->label()}; + // We run after scoping, so this is declared for one instance only + declp->perInstance(true); modp->addStmtsp(declp); AstNodeExpr* const guardp = andExpr(flp, @@ -2229,6 +2215,8 @@ class FsmLowerVisitor final { fromVertexp->label(), toStatep->label(), fsmTag}; + // We run after scoping, so this is declared for one instance only + declp->perInstance(true); modp->addStmtsp(declp); AstNodeExpr* guardp = nullptr; if (fromVertexp->isResetAny()) { @@ -2291,48 +2279,8 @@ public: } }; -// Wrapper FSM support has two architectural paths. If V3Inline removes the -// wrapper, the main detector will later see an ordinary parent-scope always_ff; -// this pre-inline visitor leaves just enough provenance on the q-side state -// variable for that direct path to accept wrapper-specific normalized shapes. -// If the wrapper survives, this marker is harmless and the cell-path detector -// builds a register candidate from the instance itself. -class FsmWrapperMarkerVisitor final : public VNVisitor { - static AstPin* findPin(AstCell* cellp, const string& name) { - for (AstPin* pinp = cellp->pinsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { - if (pinp->name() == name) return pinp; - } - return nullptr; - } - - void visit(AstCell* cellp) override { - if (const V3Control::FsmRegisterWrapper* const descp = fsmRegisterWrapperDesc(cellp)) { - AstPin* const qp = findPin(cellp, descp->q); - if (qp && VN_IS(qp->exprp(), VarRef)) { - AstVarRef* const qrefp = VN_AS(qp->exprp(), VarRef); - // The q-side parent variable is the point where the wrapper - // abstraction collapses into direct RTL after inlining. - // Marking only that variable keeps the provenance narrow: - // transition detection still has to prove the d/q FSM pair. - qrefp->varp()->attrFsmRegisterWrapper(true); - } - } - iterateChildren(cellp); - } - - void visit(AstNode* nodep) override { iterateChildren(nodep); } - -public: - explicit FsmWrapperMarkerVisitor(AstNetlist* rootp) { iterate(rootp); } -}; - } // namespace -void V3FsmDetect::markWrapperStateVars(AstNetlist* rootp) { - UINFO(2, __FUNCTION__ << ":"); - FsmWrapperMarkerVisitor marker{rootp}; -} - void V3FsmDetect::detect(AstNetlist* rootp) { UINFO(2, __FUNCTION__ << ":"); FsmState state; diff --git a/src/V3FsmDetect.h b/src/V3FsmDetect.h index 88faad8bd..878efe5be 100644 --- a/src/V3FsmDetect.h +++ b/src/V3FsmDetect.h @@ -24,10 +24,6 @@ class AstNetlist; class V3FsmDetect final { public: - // Mark parent-scope state variables connected through configured wrapper - // instances before inlining lowers those instances away. - static void markWrapperStateVars(AstNetlist* rootp) VL_MT_DISABLED; - // Detect FSMs while the original clocked/case structure is still visible, // then immediately lower the recovered graphs into concrete coverage // instrumentation as a second local phase in the same pass. diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index dd6616243..37e8da620 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* -// DESCRIPTION: Verilator: Add temporaries, such as for inline nodes +// DESCRIPTION: Verilator: Module inlining // // Code available from: https://verilator.org // @@ -18,9 +18,10 @@ // Each module: // Look for CELL... PRAGMA INLINE_MODULE // Replicate the cell's module -// Convert pins to wires that make assignments // Rename vars to include cell name -// Insert cell's module statements into the upper module +// Insert cell's module declarations into the upper module +// Merge each SCOPE of the cell's module into the SCOPE above it +// Reparent and rename the SCOPEs below the inlined instance // //************************************************************************* @@ -30,10 +31,9 @@ #include "V3AstUserAllocator.h" #include "V3Graph.h" -#include "V3Inst.h" #include "V3Stats.h" -#include +#include #include VL_DEFINE_DEBUG_FUNCTIONS; @@ -129,6 +129,7 @@ public: return m_flattenedSize; } // Total number of instances of this module in the whole hierarchy of the design + // Note this is the same as the number of AstScopes the module has. size_t instanceCount() const { if (!m_instanceCountValid) { m_instanceCountValid = true; @@ -251,6 +252,7 @@ class InlineModGraphBuilder final : public VNVisitor { // STATE std::unique_ptr m_graphp{new InlineModGraph}; // The graph being built InlineModModuleVertex* m_modVtxp = nullptr; // Vertex of module currently being iterated + const AstScope* m_sizedScopep = nullptr; // The scope of current module measured for size // VISITORS void visit(AstNodeModule* nodep) override { @@ -263,8 +265,8 @@ class InlineModGraphBuilder final : public VNVisitor { // Check if the module itself is not inlineable - // Inlining an interface means we no longer have a cell handle to resolve to. - // If inlining moves post-scope this can perhaps be relaxed. + // TODO: All references are resolved by now, but AstIfaceRefDType::cellp and + // the AstIntfRef records still name the interface instance, so keep it. if (VN_IS(nodep, Iface)) vtxp->setNoInlineHard("Interface"); // Never inline packages - TODO: conceptually fine, but why not? if (VN_IS(nodep, Package)) vtxp->setNoInlineHard("Package"); @@ -279,14 +281,24 @@ class InlineModGraphBuilder final : public VNVisitor { // Iterate children VL_RESTORER(m_modVtxp); + VL_RESTORER(m_sizedScopep); m_modVtxp = vtxp; + m_sizedScopep = nullptr; iterateChildrenConst(nodep); } void visit(AstClass* nodep) override { // TODO allow inlining of modules that contain classes if (m_modVtxp) m_modVtxp->setNoInlineHard("Contains class"); - iterateChildrenConst(nodep); // TODO: this is only needed or FTaskRef cleanup + } + + void visit(AstScope* nodep) override { + // Every instance of a module holds an identical copy of the module body under + // its own AstScope, so only measure the size of one of them. + if (!m_sizedScopep) m_sizedScopep = nodep; + if (m_sizedScopep != nodep) return; + if (m_modVtxp) m_modVtxp->sizeInc(); + iterateChildrenConst(nodep); } // Cells instantiate modules @@ -328,18 +340,6 @@ class InlineModGraphBuilder final : public VNVisitor { iterateChildrenConst(nodep); } - // TODO: Bit nasty to do this here, but historically present, and still necessary - void visit(AstNodeFTaskRef* nodep) override { - if (m_modVtxp) m_modVtxp->sizeInc(); - // Remove link. V3LinkDot will reestablish it after inlining. - // MethodCalls not currently supported by inliner, so keep linked - if (!nodep->classOrPackagep() && !VN_IS(nodep, MethodCall)) { - nodep->taskp(nullptr); - VIsCached::clearCacheTree(); - } - iterateChildrenConst(nodep); - } - // Base node void visit(AstNode* nodep) override { if (m_modVtxp) m_modVtxp->sizeInc(); @@ -373,384 +373,171 @@ public: } }; -//###################################################################### -// After cell is cloned, relink the new module's contents - -class InlineRelinkVisitor final : public VNVisitor { - // NODE STATE - // Input: - // See InlineVisitor - - // STATE - std::unordered_set m_renamedInterfaces; // Name of renamed interface variables - std::unordered_set - m_priorInlinedCells; // Cells previously inlined into the module being inlined here. - // Used to recognize VarXRefs whose inlinedDots was stamped by a - // prior V3Inline pass (vs. by V3Begin generate-block unrolling). - std::unordered_set - m_pinSubstitutedXRefs; // VarXRefs created by pin substitution in this relink pass. - // Their dotted/inlinedDots already represent the parent's scope - // and must not be rewritten on the immediate visit. - InlineModGraph& m_graph; // The instance graph - AstNodeModule* const m_modp; // The module we are inlining into - // The vertex of the module we are inlining into, for updating the graph - InlineModModuleVertex* const m_mVtxp = m_graph.getInlineModModuleVertexp(m_modp); - const AstCell* const m_cellp; // The cell being inlined - - size_t m_nPlaceholders = 0; // Unique identifier sequence number for placeholder variables - - // VISITORS - void visit(AstCellInline* nodep) override { - // Inlined cell under the inline cell, need to move to avoid conflicts - nodep->unlinkFrBack(); - m_modp->addInlinesp(nodep); - // Rename - nodep->name(m_cellp->name() + "__DOT__" + nodep->name()); - UINFO(6, " Inline " << nodep); - // Do CellInlines under this, but don't move them - iterateChildren(nodep); - } - void visit(AstCell* nodep) override { - // Cell under the inline cell, need to rename to avoid conflicts - nodep->name(m_cellp->name() + "__DOT__" + nodep->name()); - // Need to update graph - nodep->user4p(nullptr); // clone copied user4p, reset to make new vertex - InlineModCellVertex* const vtxp = m_graph.getInlineModCellVertexp(nodep); - m_graph.addEdge(*m_mVtxp, *vtxp); - m_graph.addEdge(*vtxp, *m_graph.getInlineModModuleVertexp(nodep->modp())); - iterateChildren(nodep); - } - void visit(AstClass* nodep) override { - nodep->name(m_cellp->name() + "__DOT__" + nodep->name()); - iterateChildren(nodep); - } - void visit(AstModule* nodep) override { - m_renamedInterfaces.clear(); - iterateChildren(nodep); - } - void visit(AstVar* nodep) override { - // Iterate won't hit AstIfaceRefDType directly as it is no longer underneath the module - if (AstIfaceRefDType* const ifacerefp = VN_CAST(nodep->dtypep(), IfaceRefDType)) { - m_renamedInterfaces.insert(nodep->name()); - // Each inlined cell that contain an interface variable need to - // copy the IfaceRefDType and point it to the newly cloned - // interface cell. - AstIfaceRefDType* const newdp = ifacerefp->cloneTree(false); - nodep->dtypep(newdp); - ifacerefp->addNextHere(newdp); - // Relink to point to newly cloned cell - if (newdp->cellp()) { - if (AstCell* const newcellp = VN_CAST(newdp->cellp()->user3p(), Cell)) { - newdp->cellp(newcellp); - newdp->cellName(newcellp->name()); - // Tag the old ifacerefp to ensure it leaves no stale - // reference to the inlined cell. - newdp->user1(false); - ifacerefp->user1(true); - } - } - } - // Variable under the inline cell, need to rename to avoid conflicts - // Also clear I/O bits, as it is now local. - const string name = m_cellp->name() + "__DOT__" + nodep->name(); - if (!nodep->isFuncLocal() && !nodep->isClassMember()) nodep->inlineAttrReset(name); - if (!m_cellp->isTrace()) nodep->trace(false); - UINFOTREE(9, nodep, "", "varchanged"); - } - void visit(AstNodeFTask* nodep) override { - // Function under the inline cell, need to rename to avoid conflicts - nodep->name(m_cellp->name() + "__DOT__" + nodep->name()); - iterateChildren(nodep); - } - void visit(AstTypedef* nodep) override { - // Typedef under the inline cell, need to rename to avoid conflicts - nodep->name(m_cellp->name() + "__DOT__" + nodep->name()); - iterateChildren(nodep); - } - void visit(AstAlias* nodep) override { - // Don't replace port variable in the alias - } - void visit(AstVarRef* nodep) override { - // If the target port is being inlined, replace reference with the - // connected expression (a Const, VarRef, or VarXRef). - AstNode* const pinExpr = nodep->varp()->user2p(); - if (!pinExpr) return; - - // If it's a constant, inline it - if (AstConst* const constp = VN_CAST(pinExpr, Const)) { - // You might think we would not try to substitute a constant for - // a written variable, but we might need to do this if for example - // there is an assignment to an input port, and that input port - // is tied to a constant on the cell we are inlining. This does - // generate an ASSIGNIN warning, but that can be downgraded to - // a warning. (Also assigning to an input can has valid uses if - // e.g. done via a hierarchical reference from outside to an input - // unconnected on the instance, so we don't want ASSIGNIN fatal.) - // Same applies when there is a static initialzier for an input. - // To avoid having to special case malformed assignment, or worse - // yet emiting code like 0 = 0, we instead substitute a placeholder - // variable that will later be pruned (it will otherwise be unreferenced). - if (!nodep->access().isReadOnly()) { - AstVar* const varp = nodep->varp(); - const std::string name - = m_cellp->name() + "__vInlPlaceholder_" + std::to_string(++m_nPlaceholders); - AstVar* const holdep = new AstVar{varp->fileline(), VVarType::VAR, name, varp}; - m_modp->addStmtsp(holdep); - AstVarRef* const newp = new AstVarRef{nodep->fileline(), holdep, nodep->access()}; - nodep->replaceWith(newp); - } else { - nodep->replaceWith(constp->cloneTree(false)); - } - VL_DO_DANGLING(nodep->deleteTree(), nodep); - return; - } - - // Handle VarRef: simple retarget - if (const AstVarRef* const vrefp = VN_CAST(pinExpr, VarRef)) { - nodep->varp(vrefp->varp()); - nodep->classOrPackagep(vrefp->classOrPackagep()); - return; - } - - // Handle VarXRef: replace VarRef with VarXRef (e.g., nested interface port) - const AstVarXRef* const xrefp = VN_AS(pinExpr, VarXRef); - AstVarXRef* const newp - = new AstVarXRef{nodep->fileline(), xrefp->name(), xrefp->dotted(), nodep->access()}; - newp->varp(xrefp->varp()); - // The pin expression came from m_modp (the parent we are inlining into), so its - // dotted/inlinedDots already describe a path in m_modp's scope. Record this xref - // so visit(AstVarXRef) leaves it alone on the immediate visit; later inline - // passes will prepend their cell names normally. - newp->inlinedDots(xrefp->inlinedDots()); - m_pinSubstitutedXRefs.insert(newp); - nodep->replaceWith(newp); - VL_DO_DANGLING(nodep->deleteTree(), nodep); - } - void visit(AstVarXRef* nodep) override { - // VarXRefs just created by pin substitution in this pass already describe a path - // in m_modp's scope (the parent we are inlining into). Leave them untouched on - // this immediate visit; subsequent inline passes will prepend their cell names. - if (m_pinSubstitutedXRefs.erase(nodep)) { - iterateChildren(nodep); - return; - } - // Track what scope it was originally under so V3LinkDot can resolve it - const string origInlinedDots = nodep->inlinedDots(); - nodep->inlinedDots(VString::dot(m_cellp->name(), ".", origInlinedDots)); - // If origInlinedDots starts with the name of a previously-inlined cell, this - // VarXRef came from that cell's body and its dotted refers to that child's - // local scope; renaming it against m_renamedInterfaces would wrongly alias it - // to a coincidentally-named var in the current module (#5120). VarXRefs whose - // inlinedDots was stamped by V3Begin generate-block unrolling are unaffected, - // since V3Begin's CellInlines have origModName "__BEGIN__" and don't appear in - // m_priorInlinedCells. - const string::size_type firstDot = origInlinedDots.find('.'); - const string firstSeg - = firstDot == string::npos ? origInlinedDots : origInlinedDots.substr(0, firstDot); - const bool fromPriorInline = m_priorInlinedCells.count(firstSeg); - for (string tryname = nodep->dotted(); true;) { - if (m_renamedInterfaces.count(tryname)) { - // matchIsRenamed: the matched name itself was created by a prior V3Inline - // rename (contains "__DOT__"). When true, we are following the chain of - // renames for the same var across nested inlines, so apply the rename - // even if the VarXRef came from a prior-inlined child. - const bool matchIsRenamed = tryname.find("__DOT__") != string::npos; - if (!fromPriorInline || matchIsRenamed) { - nodep->dotted(m_cellp->name() + "__DOT__" + nodep->dotted()); - } - break; - } - // If foo.bar, and foo is an interface, then need to search again for foo - const string::size_type pos = tryname.rfind('.'); - if (pos == string::npos || pos == 0) { - break; - } else { - tryname.resize(pos); - } - } - iterateChildren(nodep); - } - void visit(AstNodeFTaskRef* nodep) override { - // Track what scope it was originally under so V3LinkDot can resolve it - nodep->inlinedDots(VString::dot(m_cellp->name(), ".", nodep->inlinedDots())); - if (m_renamedInterfaces.count(nodep->dotted())) { - nodep->dotted(m_cellp->name() + "__DOT__" + nodep->dotted()); - } - UINFO(8, " " << nodep); - iterateChildren(nodep); - } - - // Not needed, as V3LinkDot doesn't care about typedefs - // void visit(AstRefDType* nodep) override {} - - void visit(AstScopeName* nodep) override { - // If there's a %m in the display text, we add a special node that will contain the name() - // Similar code in V3Begin - // To keep correct visual order, must add before exising - nodep->scopeAttr("__DOT__" + m_cellp->name() + nodep->scopeAttr()); - nodep->scopeEntr("__DOT__" + m_cellp->name() + nodep->scopeEntr()); - iterateChildren(nodep); - } - void visit(AstNodeCoverDecl* nodep) override { - // Fix path in coverage statements - nodep->hier(VString::dot(m_cellp->prettyName(), ".", nodep->hier())); - iterateChildren(nodep); - } - void visit(AstNode* nodep) override { iterateChildren(nodep); } - -public: - // CONSTRUCTORS - InlineRelinkVisitor(AstNodeModule* cloneModp, AstNodeModule* oldModp, AstCell* cellp, - InlineModGraph& graph) - : m_graph{graph} - , m_modp{oldModp} - , m_cellp{cellp} { - // CellInlines added by V3Begin for generate/named blocks have origModName - // "__BEGIN__"; only those added by prior V3Inline passes carry a real module - // name. Track the latter so visit(AstVarXRef) can distinguish VarXRefs - // originating from previously-inlined children. - for (AstNode* nodep = cloneModp->inlinesp(); nodep; nodep = nodep->nextp()) { - const AstCellInline* const cip = VN_CAST(nodep, CellInline); - if (cip && cip->origModName() != "__BEGIN__") { - m_priorInlinedCells.insert(cip->name()); - } - } - iterate(cloneModp); - } - ~InlineRelinkVisitor() override = default; -}; - //###################################################################### // Module inliner namespace ModuleInliner { -// A port variable in an inlined module can be connected 2 ways. -// Either add a continuous assignment between the pin expression from -// the instance and the port variable, or simply inline the pin expression -// in place of the port variable. We will prefer to do the later whenever -// possible (and sometimes required). When inlining, we need to create an -// alias for the inlined variable, in order to resovle hierarchical references -// against it later in V3Scope (and also for tracing, which is inserted -//later). Returns ture iff the given port variable should be inlined, -// and false if a continuous assignment should be used. -bool inlinePort(const AstVar* nodep) { - // Interface references are always inlined - if (nodep->isIfaceRef()) return true; - // Ref ports must be always inlined - if (nodep->direction() == VDirection::REF) return true; - // Forced signals must not be inlined. The port signal can be - // forced separately from the connected signals. - if (nodep->isForced()) return false; +// The scopes instantiated directly under each scope (that is parent -> children links) +using ScopeChildren = std::unordered_map>; - // Note: For singls marked 'public' (and not 'public_flat') inlining - // of their containing modules is disabled so they wont reach here. - - // TODO: For now, writable public signals inside the cell cannot be - // eliminated as they are entered into the VerilatedScope, and - // changes would not propagate to it when assigned. (The alias created - // for them ensures they would be read correctly, but would not - // propagate any changes.) This can be removed when the VerialtedScope - // construction in V3EmitCSyms understands aliases. - if (nodep->isSigUserRWPublic()) return false; - - // Otherwise we can repalce the variable - return true; +// Record downward links from parent scopes to their child scopes +void gatherScopes(const AstNodeModule* modp, ScopeChildren& children) { + for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) { + if (AstScope* const scopep = VN_CAST(nodep, Scope)) { + // Note the top scope is held under the AstTopScope, so is not seen here + UASSERT_OBJ(scopep->aboveScopep(), scopep, "Instance scope should have a scope above"); + children[scopep->aboveScopep()].push_back(scopep); + } else if (const AstNodeModule* const subModp = VN_CAST(nodep, NodeModule)) { + // An AstClass holds its scopes under itself + UASSERT_OBJ(VN_IS(subModp, Class), subModp, "Nested module should be a class"); + gatherScopes(subModp, children); + } + } } -// Connect the given port 'nodep' (being inlined into 'modp') to the given -// expression (from the Cell Pin) -void connectPort(AstNodeModule* modp, AstVar* nodep, AstNodeExpr* pinExprp) { - UINFO(6, "Connecting " << pinExprp); - UINFO(6, " to " << nodep); - - // Decide whether to inline the port variable or use continuous assignments - const bool inlineIt = inlinePort(nodep); - - // If we deccided to inline it, record the expression to substitute this variable with - if (inlineIt) nodep->user2p(pinExprp); - - FileLine* const flp = nodep->fileline(); - - // Helper to creates an AstVarRef reference to the port variable - const auto portRef = [&](VAccess access) { return new AstVarRef{flp, nodep, access}; }; - - // If the connected expression is a constant, add an assignment to set - // the port variable. The constant can still be inlined, in which case - // this is needed for tracing the inlined port variable. - if (AstConst* const pinp = VN_CAST(pinExprp, Const)) { - AstVarRef* const lhsp = portRef(VAccess::WRITE); - lhsp->varp()->isContinuously(true); - AstAssignW* const ap = new AstAssignW{flp, lhsp, pinp->cloneTree(false)}; - modp->addStmtsp(new AstAlways{ap}); - return; +// Rename the given scope, and all scopes below it, after the scope named by 'oldPrefix' +// (the original parent of 'scopep') has been inlined into the scope above it +void renameScopes(AstScope* scopep, const std::string& oldPrefix, const std::string& newPrefix, + const ScopeChildren& children) { + UASSERT_OBJ(VString::startsWith(scopep->name(), oldPrefix), scopep, + "Scope name should start with the name of the scope above it"); + scopep->name(newPrefix + scopep->name().substr(oldPrefix.size())); + const auto it = children.find(scopep); + if (it == children.end()) return; + for (AstScope* const childp : it->second) { + renameScopes(childp, oldPrefix, newPrefix, children); } +} - // Otherwise it must be a variable reference due to having called pinReconnectSimple - const AstNodeVarRef* const pinRefp = VN_AS(pinExprp, NodeVarRef); +// Merge the given scope (instance) of the inlined cell into the scope above it +void inlineScope(AstScope* scopep, AstCell* cellp, const std::string& prefix, + AstCellInline* newCellInlinep, ScopeChildren& children) { + AstScope* const parentScopep = scopep->aboveScopep(); + UASSERT_OBJ(parentScopep, scopep, "Inlined scope should have a scope above"); + UINFO(6, " Inline Scope " << scopep); + UINFO(6, " into " << parentScopep); - const auto pinRefAsVarRef = [&](VAccess access) -> AstVarRef* { - const AstVarRef* const vrp = VN_AS(pinRefp, VarRef); - AstVarRef* const newp = new AstVarRef{vrp->fileline(), vrp->varp(), access}; - newp->classOrPackagep(vrp->classOrPackagep()); - return newp; - }; - - const auto pinRefAsExpr = [&](VAccess access) -> AstNodeExpr* { - if (VN_IS(pinRefp, VarRef)) { - return pinRefAsVarRef(access); - } else { - const AstVarXRef* const xrp = VN_AS(pinRefp, VarXRef); - AstVarXRef* const newp - = new AstVarXRef{xrp->fileline(), xrp->name(), xrp->dotted(), access}; - newp->varp(xrp->varp()); - newp->inlinedDots(xrp->inlinedDots()); - return newp; + // Move the variables of the inlined scope into the scope above + for (AstVarScope *vscp = scopep->varsp(), *nextp; vscp; vscp = nextp) { + nextp = VN_AS(vscp->nextp(), VarScope); + // Note V3Scope attaches variables of non-virtual interface references to the + // scope of the interface instance, so only update if it is this scope + if (vscp->scopep() == scopep) vscp->scopep(parentScopep); + // If the module was cloned, point to the cloned variable + if (AstVar* const newVarp = VN_CAST(vscp->varp()->user3p(), Var)) { + vscp->varp(newVarp); + vscp->dtypeFrom(newVarp); } - }; + if (!cellp->isTrace()) vscp->trace(false); + parentScopep->addVarsp(vscp->unlinkFrBack()); + } - // If it is being inlined, create the alias for it - if (inlineIt) { - UINFO(6, "Inlining port variable: " << nodep); - if (nodep->isIfaceRef()) { - modp->addStmtsp( - new AstAliasScope{flp, portRef(VAccess::WRITE), pinRefAsExpr(VAccess::READ)}); - } else { - AstVarRef* const aliasArgsp = portRef(VAccess::WRITE); - aliasArgsp->addNext(pinRefAsVarRef(VAccess::READ)); - modp->addStmtsp(new AstAlias{flp, aliasArgsp}); + // Move the logic of the inlined scope into the scope above + for (AstNode *nodep = scopep->blocksp(), *nextp; nodep; nodep = nextp) { + nextp = nodep->nextp(); + nodep->unlinkFrBack(); + if (AstNodeFTask* const ftaskp = VN_CAST(nodep, NodeFTask)) { + ftaskp->name(prefix + ftaskp->name()); } - // They will become the same variable, so propagate file-line and variable attributes - pinRefp->varp()->fileline()->modifyStateInherit(flp); - flp->modifyStateInherit(pinRefp->varp()->fileline()); - pinRefp->varp()->propagateAttrFrom(nodep); - nodep->propagateAttrFrom(pinRefp->varp()); - return; + // If the module was cloned, point coverage increments to the cloned declarations + if (v3Global.opt.coverage()) { + nodep->foreach([&](AstCoverInc* incp) { + AstNodeCoverDecl* const declp = incp->declp(); + if (declp->perInstance()) { + // Not cloned, fix up the path here, as only this scope refers to it + declp->hier(VString::dot(cellp->prettyName(), ".", declp->hier())); + return; + } + if (AstNodeCoverDecl* const newDeclp = VN_CAST(declp->user3p(), NodeCoverDecl)) { + incp->declp(newDeclp); + } + }); + } + parentScopep->addBlocksp(nodep); } - // Otherwise create the continuous assignment between the port var and the pin expression - UINFO(6, "Not inlining port variable: " << nodep); - if (nodep->direction() == VDirection::INPUT) { - AstVarRef* const lhsp = portRef(VAccess::WRITE); - lhsp->varp()->isContinuously(true); - AstAssignW* const ap = new AstAssignW{flp, lhsp, pinRefAsExpr(VAccess::READ)}; - modp->addStmtsp(new AstAlways{ap}); - } else if (nodep->direction() == VDirection::OUTPUT) { - AstNodeVarRef* const lhsp = VN_AS(pinRefAsExpr(VAccess::WRITE), NodeVarRef); - lhsp->varp()->isContinuously(true); - AstAssignW* const ap = new AstAssignW{flp, lhsp, portRef(VAccess::READ)}; - modp->addStmtsp(new AstAlways{ap}); - } else { - pinExprp->v3fatalSrc("V3Tristate left INOUT port"); + // Move the inline records of the inlined scope into the scope above + for (AstNode *nodep = scopep->inlinesp(), *nextp; nodep; nodep = nextp) { + nextp = nodep->nextp(); + AstCellInlineScope* const cisp = VN_AS(nodep->unlinkFrBack(), CellInlineScope); + cisp->scopep(parentScopep); + // If the module was cloned, point to the cloned inline record + if (AstCellInline* const newCinlp = VN_CAST(cisp->cellp()->user3p(), CellInline)) { + cisp->cellp(newCinlp); + } + parentScopep->addInlinesp(cisp); } + // ... and add one for the instance we are inlining now + if (v3Global.opt.vpi()) { + parentScopep->addInlinesp( + new AstCellInlineScope{cellp->fileline(), parentScopep, newCellInlinep}); + } + + // Reparent and rename the scopes instantiated under the inlined scope + const std::string oldPrefix = scopep->name() + "."; + const std::string newPrefix = scopep->name() + "__DOT__"; + std::vector childScopeps; + { + const auto it = children.find(scopep); + if (it != children.end()) { + childScopeps = std::move(it->second); + children.erase(it); + } + } + for (AstScope* const childScopep : childScopeps) { + // A class scope would hang off the scope of the module declaring it, but modules + // containing classes are never inlined + UASSERT_OBJ(!VN_IS(childScopep->modp(), Class), childScopep, + "Inlined scope should not contain a class scope"); + if (AstCell* const newCellp = VN_CAST(childScopep->aboveCellp()->user3p(), Cell)) { + // If the module was cloned, point to the cloned cell + childScopep->aboveCellp(newCellp); + } + childScopep->aboveScopep(parentScopep); + renameScopes(childScopep, oldPrefix, newPrefix, children); + } + // Children of the inlined scope are now children of the scope above. Note this must + // come after the erase above, as inserting into 'children' can invalidate 'it'. + std::vector& parentChildps = children[parentScopep]; + parentChildps.erase(std::remove(parentChildps.begin(), parentChildps.end(), scopep), + parentChildps.end()); + parentChildps.insert(parentChildps.end(), childScopeps.begin(), childScopeps.end()); + + UASSERT_OBJ(!scopep->varsp() && !scopep->blocksp() && !scopep->inlinesp(), scopep, + "Inlined scope should be empty"); } // Inline 'cellp' into 'modp'. 'last' indicatest this is tha last instance of the inlined module -void inlineCell(AstNodeModule* modp, AstCell* cellp, bool last, InlineModGraph& graph) { +void inlineCell(AstNodeModule* modp, AstCell* cellp, bool last, InlineModGraph& graph, + ScopeChildren& children) { UINFO(5, " Inline Cell " << cellp); UINFO(5, " into Module " << modp); - const VNUser2InUse user2InUse; + // NODE STATE + // AstNode::user3p() -> AstNode*. The clone of this module level declaration + const VNUser3InUse user3InUse; + + VNDeleter deleter; + deleter.pushDeletep(cellp->unlinkFrBack()); + + AstNodeModule* const subModp = cellp->modp(); // The module being inlined + + // Unlink all scopes of the instantiated module, so they are not cloned with it + std::vector inlineScopeps; // Scopes under 'cellp' + std::vector otherScopeps; // Scopes under some other instance + for (AstNode *nodep = subModp->stmtsp(), *nextp; nodep; nodep = nextp) { + nextp = nodep->nextp(); + AstScope* const scopep = VN_CAST(nodep, Scope); + if (!scopep) continue; + scopep->unlinkFrBack(); + if (scopep->aboveCellp() == cellp) { + inlineScopeps.push_back(scopep); + deleter.pushDeletep(scopep); + } else { + otherScopeps.push_back(scopep); + } + } // Important: If this is the last cell, then don't clone the instantiated module but // inline the original directly. While this requires some special casing, doing so @@ -762,73 +549,107 @@ void inlineCell(AstNodeModule* modp, AstCell* cellp, bool last, InlineModGraph& // worse if we put off deleting the inlined modules until the end. Not having to clone // large trees also improves speed. - // The module we will yank the contents out of and put into 'modp' - AstNodeModule* const inlinedp = last ? cellp->modp()->unlinkFrBack() // - : cellp->modp()->cloneTree(false); + // The module we will yank the declarations out of and put into 'modp' + AstNodeModule* inlinedp; + if (last) { + inlinedp = subModp->unlinkFrBack(); + // This is the only instantiation, so all scopes are being inlined + UASSERT_OBJ(otherScopeps.empty(), cellp, "Last instance, but has other scopes"); + } else { + inlinedp = subModp->cloneTree(false); + // Compute map from the original module items to their clones + for (AstNode *ap = subModp->inlinesp(), *bp = inlinedp->inlinesp(); ap || bp; + ap = ap->nextp(), bp = bp->nextp()) { + UASSERT_OBJ(ap && bp, ap ? ap : bp, "Clone has different number of children"); + ap->user3p(bp); + } + for (AstNode *ap = subModp->stmtsp(), *bp = inlinedp->stmtsp(); ap || bp; + ap = ap->nextp(), bp = bp->nextp()) { + UASSERT_OBJ(ap && bp, ap ? ap : bp, "Clone has different number of children"); + ap->user3p(bp); + } + // Per instance coverage declarations must not be duplicated, drop the clones + if (v3Global.opt.coverageFsm()) { + for (AstNode *nodep = inlinedp->stmtsp(), *nextp; nodep; nodep = nextp) { + nextp = nodep->nextp(); + const AstNodeCoverDecl* const declp = VN_CAST(nodep, NodeCoverDecl); + if (declp && declp->perInstance()) { + VL_DO_DANGLING(deleter.pushDeletep(nodep->unlinkFrBack()), nodep); + } + } + } + // Put back the scopes of the instances we are not inlining this time + for (AstScope* const scopep : otherScopeps) subModp->addStmtsp(scopep); + } + deleter.pushDeletep(inlinedp); - // Compute map from original port variables and cells to their clones - for (AstNode *ap = cellp->modp()->stmtsp(), *bp = inlinedp->stmtsp(); ap || bp; - ap = ap->nextp(), bp = bp->nextp()) { - UASSERT_OBJ(ap && bp, ap ? ap : bp, "Clone has different number of children"); - // We only care about AstVar and AstCell, but faster to just set them all - ap->user3p(bp); + // Prefix for renaming inlined declarations + const std::string prefix = cellp->name() + "__DOT__"; + + // Move the inline records of the inlined module, renaming to avoid conflicts + for (AstNode *nodep = inlinedp->inlinesp(), *nextp; nodep; nodep = nextp) { + nextp = nodep->nextp(); + AstCellInline* const cinlp = VN_AS(nodep->unlinkFrBack(), CellInline); + cinlp->name(prefix + cinlp->name()); + modp->addInlinesp(cinlp); + } + // Create inline record for resolving hierarchical references later + AstCellInline* const newCellInlinep + = new AstCellInline{cellp->fileline(), cellp->name(), subModp->origName()}; + modp->addInlinesp(newCellInlinep); + + // Move the module level declarations of the inlined module into 'modp' + InlineModModuleVertex* const mVtxp = graph.getInlineModModuleVertexp(modp); + for (AstNode *nodep = inlinedp->stmtsp(), *nextp; nodep; nodep = nextp) { + nextp = nodep->nextp(); + nodep->unlinkFrBack(); + UASSERT_OBJ(!VN_IS(nodep, Class), nodep, + "Module containing a class should not be inlined"); + if (AstVar* const varp = VN_CAST(nodep, Var)) { + varp->name(prefix + varp->name()); + // Variable is now local to 'modp', rename to avoid conflicts and clear I/O bits + if (varp->direction() == VDirection::INOUT && varp->varType() == VVarType::WIRE) { + varp->varType(VVarType::TRIWIRE); + } + varp->direction(VDirection::NONE); + if (!cellp->isTrace()) varp->trace(false); + } else if (AstCell* const subCellp = VN_CAST(nodep, Cell)) { + subCellp->name(prefix + subCellp->name()); + // Need to update graph. Note the vertex of the original cell was either + // deleted (if 'last'), or user4p is a copy made by cloneTree, so reset it. + subCellp->user4p(nullptr); + InlineModCellVertex* const vtxp = graph.getInlineModCellVertexp(subCellp); + graph.addEdge(*mVtxp, *vtxp); + graph.addEdge(*vtxp, *graph.getInlineModModuleVertexp(subCellp->modp())); + } else if (AstTypedef* const typedefp = VN_CAST(nodep, Typedef)) { + typedefp->name(prefix + typedefp->name()); + } else if (AstNodeCoverDecl* const declp = VN_CAST(nodep, NodeCoverDecl)) { + // Fix path in coverage statements. Per instance ones are fixed in inlineScope. + if (!declp->perInstance()) { + declp->hier(VString::dot(cellp->prettyName(), ".", declp->hier())); + } + } + modp->addStmtsp(nodep); } - // Create data for resolving hierarchical references later. - modp->addInlinesp( - new AstCellInline{cellp->fileline(), cellp->name(), cellp->modp()->origName()}); - - // Connect the pins on the instance - for (AstPin* pinp = cellp->pinsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { - if (!pinp->exprp()) continue; - UINFO(6, "Connecting port " << pinp->modVarp()); - UINFO(6, " of instance " << cellp); - - // Make sure the conneccted pin expression is always a VarRef or a Const - V3Inst::pinReconnectSimple(pinp, cellp, false); - - // Warn - V3Inst::checkOutputShort(pinp); - if (!pinp->exprp()) continue; - - // Pick up the old and new port variables signal (new is the same on last instance) - const AstVar* const oldModVarp = pinp->modVarp(); - AstVar* const newModVarp = VN_AS(oldModVarp->user3p(), Var); - // Pick up the connected expression (a VarRef or Const due to pinReconnectSimple) - AstNodeExpr* const pinExprp = VN_AS(pinp->exprp(), NodeExpr); - - // Connect up the port - connectPort(modp, newModVarp, pinExprp); + // Merge each scope (instance) of the inlined cell into the scope above it + for (AstScope* const scopep : inlineScopeps) { + inlineScope(scopep, cellp, prefix, newCellInlinep, children); } - - // Cleanup var names, etc, to not conflict, relink replaced variables, adjust graph - { InlineRelinkVisitor{inlinedp, modp, cellp, graph}; } - // Move statements from the inlined module into the module we are inlining into - if (AstNode* const stmtsp = inlinedp->stmtsp()) { - modp->addStmtsp(stmtsp->unlinkFrBackWithNext()); - } - // Delete the empty shell of the inlined module - VL_DO_DANGLING(inlinedp->deleteTree(), inlinedp); - // Remove the cell we just inlined - VL_DO_DANGLING(cellp->unlinkFrBack()->deleteTree(), cellp); } // Apply all inlining decisions void process(AstNetlist* netlistp, InlineModGraph& graph) { - // NODE STATE - // Cleared entire netlist - // AstIfaceRefDType::user1() // bool; Whether the cell pointed to by this - // // AstIfaceRefDType has been inlined - // AstCell::user3p() // AstCell*. The clone - // AstVar::user3p() // AstVar*. The clone - // Cleared each cell - // AstVar::user2p() // AstVarRef*/AstConst* This port is connected to (AstPin::expr()) - const VNUser1InUse user1InUse; - const VNUser3InUse user3InUse; - // Number of inlined instances, for statistics VDouble0 m_nInlined; + // Record the scope hierarchy - we need the downward links + ScopeChildren children; + for (AstNodeModule* modp = netlistp->modulesp(); modp; + modp = VN_AS(modp->nextp(), NodeModule)) { + gatherScopes(modp, children); + } + // Gather all cells that need to be inlined (this is in topological order) std::vector cVtxps; for (V3GraphVertex& vtx : graph.vertices()) { @@ -866,19 +687,18 @@ void process(AstNetlist* netlistp, InlineModGraph& graph) { } // Do it - inlineCell(mVtx.modp(), cellp, last, graph); + inlineCell(mVtx.modp(), cellp, last, graph, children); if (dumpGraphLevel() >= 9) graph.dumpDotFilePrefixed("inlinemod-cell"); } - V3Stats::addStat("Optimizations, Inlined instances", m_nInlined); - - // Clean up AstIfaceRefDType references - // If the cell has been removed let's make sure we don't leave a - // reference to it. This dtype may still be in use by the - // AstAliasScope created earlier but that'll get cleared up later - netlistp->typeTablep()->foreach([](AstIfaceRefDType* nodep) { - if (nodep->user1()) nodep->cellp(nullptr); + // Restore varp() == varScopep()->varp() on all references, as cloning modules for + // inlining repointed some AstVarScopes. Hierarchical references can be anywhere. + netlistp->foreach([](AstNodeVarRef* refp) { + AstVarScope* const vscp = refp->varScopep(); + if (vscp && refp->varp() != vscp->varp()) refp->varp(vscp->varp()); }); + + V3Stats::addStat("Optimizations, Inlined instances", m_nInlined); } } //namespace ModuleInliner @@ -945,7 +765,7 @@ void V3Inline::inlineAll(AstNetlist* nodep) { } if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("inlinemod-decision"); - // Inline the modles we decided to inline + // Inline the modules we decided to inline ModuleInliner::process(nodep, *graphp); if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("inlinemod-inlined"); diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index b6ce2727e..36f5901f4 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -926,7 +926,9 @@ public: && connBasicp->width() == pinVarp->width()) { // Done. One to one interconnect won't need a temporary variable. } else if (!alwaysCvt && !forTristate && VN_IS(pinp->exprp(), Const)) { - // Done. Constant. + // Done. Constant. Still check for driving an output, like below. + V3Inst::checkOutputShort(pinp); + if (!pinp->exprp()) return nullptr; } else { // Make a new temp wire // UINFOTREE(9, pinp, "", "in_pin"); diff --git a/src/Verilator.cpp b/src/Verilator.cpp index fc53162f1..574b7664d 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -316,17 +316,6 @@ static void process() { v3Global.constRemoveXs(true); } - if (!(v3Global.opt.serializeOnly() && !v3Global.opt.flatten())) { - // Module inlining - // Cannot remove dead variables after this, as alias information for final - // V3Scope's V3LinkDot is in the AstVar. - if (v3Global.opt.coverageFsm()) V3FsmDetect::markWrapperStateVars(v3Global.rootp()); - if (v3Global.opt.fInline()) { - V3Inline::inlineAll(v3Global.rootp()); - V3LinkDot::linkDotArrayed(v3Global.rootp()); // Cleanup as made new modules - } - } - // Interface references feed trace file aliases and VPI name resolution if (v3Global.opt.trace() || v3Global.opt.vpi()) { V3Interface::interfaceAll(v3Global.rootp()); @@ -359,13 +348,15 @@ static void process() { // No more AstAlias after linkDotScope V3Scope::scopeAll(v3Global.rootp()); V3LinkDot::linkDotScope(v3Global.rootp()); - // FSM coverage needs scopes, but should otherwise run as early as - // possible before later lowering rewrites user-visible clocked - // case structure. This entry point runs two adjacent phases: - // detect into local graph state, then lower that completed state - // into the concrete coverage machinery. + V3Error::abortIfErrors(); + + // FSM coverage needs scopes, but should otherwise run as early as possible before + // later lowering rewrites user-visible clocked case structure. if (v3Global.opt.coverageFsm()) V3FsmDetect::detect(v3Global.rootp()); + // Module inlining + if (v3Global.opt.fInline()) V3Inline::inlineAll(v3Global.rootp()); + // Relocate classes (after linkDot) V3Class::classAll(v3Global.rootp()); } diff --git a/test_regress/t/t_cover_fsm_combo_same_warn_bad.out b/test_regress/t/t_cover_fsm_combo_same_warn_bad.out index 32f725885..1d5bbd16c 100644 --- a/test_regress/t/t_cover_fsm_combo_same_warn_bad.out +++ b/test_regress/t/t_cover_fsm_combo_same_warn_bad.out @@ -1,4 +1,5 @@ %Warning-COVERIGN: t/t_cover_fsm_combo_same_warn_bad.v:28:19: Ignoring unsupported: FSM coverage on multiple supported case statements found in the same combinational always block. Only the first candidate will be instrumented. + : ... note: In instance 't' 28 | S1: state_d = S2; | ^ t/t_cover_fsm_combo_same_warn_bad.v:24:19: ... Location of first supported candidate for 't.state_q' diff --git a/test_regress/t/t_cover_fsm_if_unknown_enum_multi_bad.out b/test_regress/t/t_cover_fsm_if_unknown_enum_multi_bad.out index 8cf3712f6..ddd15ef4e 100644 --- a/test_regress/t/t_cover_fsm_if_unknown_enum_multi_bad.out +++ b/test_regress/t/t_cover_fsm_if_unknown_enum_multi_bad.out @@ -1,33 +1,43 @@ -%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:274:19: Ignoring unsupported: FSM coverage on enum state variable 't.unknown_wide_direct_u.state_q': assigned value 40'hffffffffff is not present in the declared enum - 274 | S0: state_d = 40'hffff_ffff_ff; +%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:26:19: Ignoring unsupported: FSM coverage on enum state variable 'state_q': assigned value 3 is not present in the declared enum + : ... note: In instance 't.unknown_then_u' + 26 | S0: state_d = sel ? 2'd3 : S1; | ^ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. -%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:249:32: Ignoring unsupported: FSM coverage on enum state variable 't.unknown_if_else_target_u.state_q': assigned value 3 is not present in the declared enum - 249 | if (state_q == S0) state_d = sel ? S1 : 2'd3; - | ^ -%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:224:32: Ignoring unsupported: FSM coverage on enum state variable 't.unknown_if_then_target_u.state_q': assigned value 3 is not present in the declared enum - 224 | if (state_q == S0) state_d = sel ? 2'd3 : S1; - | ^ -%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:199:32: Ignoring unsupported: FSM coverage on enum state variable 't.unknown_if_direct_target_u.state_q': assigned value 3 is not present in the declared enum - 199 | if (state_q == S0) state_d = 2'd3; - | ^ -%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:175:5: Ignoring unsupported: FSM coverage on enum state variable 't.unknown_if_source_u.state_q': case item value 3 is not present in the declared enum - 175 | if (state_q == 2'd3) state_d = S0; - | ^~ -%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:150:7: Ignoring unsupported: FSM coverage on enum state variable 't.unknown_source_u.state_q': case item value 3 is not present in the declared enum - 150 | 2'd3: state_d = S0; - | ^~~~ -%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:126:15: Ignoring unsupported: FSM coverage on enum state variable 't.unknown_reset_u.state_q': assigned value 3 is not present in the declared enum - 126 | state_q <= 2'd3; - | ^~ -%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:79:19: Ignoring unsupported: FSM coverage on enum state variable 't.unknown_direct_u.state_q': assigned value 3 is not present in the declared enum - 79 | S0: state_d = 2'd3; - | ^ -%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:53:19: Ignoring unsupported: FSM coverage on enum state variable 't.unknown_else_u.state_q': assigned value 3 is not present in the declared enum +%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:53:19: Ignoring unsupported: FSM coverage on enum state variable 'state_q': assigned value 3 is not present in the declared enum + : ... note: In instance 't.unknown_else_u' 53 | S0: state_d = sel ? S1 : 2'd3; | ^ -%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:26:19: Ignoring unsupported: FSM coverage on enum state variable 't.unknown_then_u.state_q': assigned value 3 is not present in the declared enum - 26 | S0: state_d = sel ? 2'd3 : S1; +%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:79:19: Ignoring unsupported: FSM coverage on enum state variable 'state_q': assigned value 3 is not present in the declared enum + : ... note: In instance 't.unknown_direct_u' + 79 | S0: state_d = 2'd3; + | ^ +%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:126:15: Ignoring unsupported: FSM coverage on enum state variable 'state_q': assigned value 3 is not present in the declared enum + : ... note: In instance 't.unknown_reset_u' + 126 | state_q <= 2'd3; + | ^~ +%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:150:7: Ignoring unsupported: FSM coverage on enum state variable 'state_q': case item value 3 is not present in the declared enum + : ... note: In instance 't.unknown_source_u' + 150 | 2'd3: state_d = S0; + | ^~~~ +%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:175:5: Ignoring unsupported: FSM coverage on enum state variable 'state_q': case item value 3 is not present in the declared enum + : ... note: In instance 't.unknown_if_source_u' + 175 | if (state_q == 2'd3) state_d = S0; + | ^~ +%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:199:32: Ignoring unsupported: FSM coverage on enum state variable 'state_q': assigned value 3 is not present in the declared enum + : ... note: In instance 't.unknown_if_direct_target_u' + 199 | if (state_q == S0) state_d = 2'd3; + | ^ +%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:224:32: Ignoring unsupported: FSM coverage on enum state variable 'state_q': assigned value 3 is not present in the declared enum + : ... note: In instance 't.unknown_if_then_target_u' + 224 | if (state_q == S0) state_d = sel ? 2'd3 : S1; + | ^ +%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:249:32: Ignoring unsupported: FSM coverage on enum state variable 'state_q': assigned value 3 is not present in the declared enum + : ... note: In instance 't.unknown_if_else_target_u' + 249 | if (state_q == S0) state_d = sel ? S1 : 2'd3; + | ^ +%Warning-COVERIGN: t/t_cover_fsm_if_unknown_enum_multi_bad.v:274:19: Ignoring unsupported: FSM coverage on enum state variable 'state_q': assigned value 40'hffffffffff is not present in the declared enum + : ... note: In instance 't.unknown_wide_direct_u' + 274 | S0: state_d = 40'hffff_ffff_ff; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_cover_fsm_multi_inst.out b/test_regress/t/t_cover_fsm_multi_inst.out new file mode 100644 index 000000000..46a613220 --- /dev/null +++ b/test_regress/t/t_cover_fsm_multi_inst.out @@ -0,0 +1,15 @@ +$ verilator_coverage --report hierarchy --levels 3 coverage.dat +Hierarchy Coverage Summary: + t + fsm_state : 70.0% ( 7/10) + fsm_arc : 58.3% ( 7/12) + t.u1 + fsm_state : 80.0% (4/5) + fsm_arc : 66.7% (4/6) + t.u2 + fsm_state : 60.0% (3/5) + fsm_arc : 50.0% (3/6) +Design Unit Coverage Summary: + fsm + fsm_state : 70.0% ( 7/10) + fsm_arc : 58.3% ( 7/12) diff --git a/test_regress/t/t_cover_fsm_multi_inst.py b/test_regress/t/t_cover_fsm_multi_inst.py new file mode 100755 index 000000000..57eb5e080 --- /dev/null +++ b/test_regress/t/t_cover_fsm_multi_inst.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3, +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +from coverage_common import init_log, run_vlcov, vlcov_run_context + +test.scenarios('simulator') + +if not test.have_coroutines: + test.skip("Test requires Coroutines; ignore error since not available") + +test.compile(verilator_flags2=["--binary", "--coverage-fsm"]) + +test.execute(all_run_flags=[" +verilator+coverage+file+" + test.obj_dir + "/coverage.dat"]) + +hier_log = test.obj_dir + "/hierarchy.log" +combined_log = test.obj_dir + "/vlcov.log" + +init_log(combined_log) +run_vlcov(vlcov_run_context(test, combined_log, hier_log), + "verilator_coverage --report hierarchy --levels 3 coverage.dat", + args=["--report", "hierarchy", "--levels", "3", test.obj_dir + "/coverage.dat"]) + +test.files_identical(combined_log, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_cover_fsm_multi_inst.v b/test_regress/t/t_cover_fsm_multi_inst.v new file mode 100644 index 000000000..f6bcb9536 --- /dev/null +++ b/test_regress/t/t_cover_fsm_multi_inst.v @@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 +// SPDX-FileCopyrightText: 2026 Wilson Snyder + +module fsm(input logic clk, input logic alt); + typedef enum logic [2:0] { IDLE, RUN1A, RUN1B, RUN2, DONE } state_t; + state_t state; + initial state = IDLE; + always @(posedge clk) begin + case (state) + IDLE: state <= (alt ? RUN2 : RUN1A); + RUN1A: state <= RUN1B; + RUN1B: state <= DONE; + RUN2: state <= DONE; + DONE: state <= IDLE; + default: state <= IDLE; + endcase + end +endmodule + +module t; + logic clk = 0; + always #5 clk = ~clk; + + fsm u1(.clk(clk), .alt(1'b0)); + fsm u2(.clk(clk), .alt(1'b1)); + + initial begin + #201; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_cover_fsm_nextstate_overwrite_warn.out b/test_regress/t/t_cover_fsm_nextstate_overwrite_warn.out index 71f746138..103615b6e 100644 --- a/test_regress/t/t_cover_fsm_nextstate_overwrite_warn.out +++ b/test_regress/t/t_cover_fsm_nextstate_overwrite_warn.out @@ -1,4 +1,5 @@ -%Warning-COVERIGN: t/t_cover_fsm_nextstate_overwrite_warn.v:21:13: Ignoring unsupported: FSM coverage on case('t.state_d') when the canonical 't.state_d' = 't.state_q' default is overwritten before the case statement +%Warning-COVERIGN: t/t_cover_fsm_nextstate_overwrite_warn.v:21:13: Ignoring unsupported: FSM coverage on case('state_d') when the canonical 'state_d' = 'state_q' default is overwritten before the case statement + : ... note: In instance 't' 21 | state_d = (state_d == S0) ? S1 : S0; | ^ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest diff --git a/test_regress/t/t_cover_fsm_nonenum_unsupported_bad.out b/test_regress/t/t_cover_fsm_nonenum_unsupported_bad.out index b0abea925..c407d96fa 100644 --- a/test_regress/t/t_cover_fsm_nonenum_unsupported_bad.out +++ b/test_regress/t/t_cover_fsm_nonenum_unsupported_bad.out @@ -1,30 +1,39 @@ -%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:68:9: Ignoring unsupported: FSM coverage on non-enum state variable 't.duplicate_state' with multiple labels for the same value 0: IDLE and RESET +%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:68:9: Ignoring unsupported: FSM coverage on non-enum state variable 'duplicate_state' with multiple labels for the same value 0: IDLE and RESET + : ... note: In instance 't' 68 | RESET: duplicate_state <= IDLE; | ^~~~~ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. -%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:84:9: Ignoring unsupported: FSM coverage on non-enum state variable 't.xz_case_state' with X/Z state encoding values +%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:84:9: Ignoring unsupported: FSM coverage on non-enum state variable 'xz_case_state' with X/Z state encoding values + : ... note: In instance 't' 84 | 2'b1x: xz_case_state <= 2'h0; | ^~~~~ -%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:97:64: Ignoring unsupported: FSM coverage on non-enum state variable 't.duplicate_ternary_target_state' with multiple labels for the same value 0: IDLE and RESET +%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:97:64: Ignoring unsupported: FSM coverage on non-enum state variable 'duplicate_ternary_target_state' with multiple labels for the same value 0: IDLE and RESET + : ... note: In instance 't' 97 | IDLE: duplicate_ternary_target_state <= start ? BUSY : RESET; | ^~~~~ -%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:110:62: Ignoring unsupported: FSM coverage on non-enum state variable 't.duplicate_ternary_then_target_state' with multiple labels for the same value 0: IDLE and RESET +%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:110:62: Ignoring unsupported: FSM coverage on non-enum state variable 'duplicate_ternary_then_target_state' with multiple labels for the same value 0: IDLE and RESET + : ... note: In instance 't' 110 | IDLE: duplicate_ternary_then_target_state <= start ? RESET : BUSY; | ^~~~~ -%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:125:36: Ignoring unsupported: FSM coverage on non-enum state variable 't.duplicate_if_target_state' with multiple labels for the same value 0: IDLE and RESET +%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:125:36: Ignoring unsupported: FSM coverage on non-enum state variable 'duplicate_if_target_state' with multiple labels for the same value 0: IDLE and RESET + : ... note: In instance 't' 125 | duplicate_if_target_state <= RESET; | ^~~~~ -%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:134:57: Ignoring unsupported: FSM coverage on non-enum state variable 't.duplicate_if_ternary_then_target_state' with multiple labels for the same value 0: IDLE and RESET +%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:134:57: Ignoring unsupported: FSM coverage on non-enum state variable 'duplicate_if_ternary_then_target_state' with multiple labels for the same value 0: IDLE and RESET + : ... note: In instance 't' 134 | duplicate_if_ternary_then_target_state <= start ? RESET : BUSY; | ^~~~~ -%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:146:64: Ignoring unsupported: FSM coverage on non-enum state variable 't.duplicate_if_ternary_else_target_state' with multiple labels for the same value 0: IDLE and RESET +%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:146:64: Ignoring unsupported: FSM coverage on non-enum state variable 'duplicate_if_ternary_else_target_state' with multiple labels for the same value 0: IDLE and RESET + : ... note: In instance 't' 146 | duplicate_if_ternary_else_target_state <= start ? BUSY : RESET; | ^~~~~ -%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:201:37: Ignoring unsupported: FSM coverage on non-enum state variable 't.xz_rhs_probe_state' with non-constant target state values +%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:201:37: Ignoring unsupported: FSM coverage on non-enum state variable 'xz_rhs_probe_state' with non-constant target state values + : ... note: In instance 't' 201 | 2'h0: xz_rhs_probe_state <= 2'b0x; | ^~~~~ -%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:214:54: Ignoring unsupported: FSM coverage on non-enum state variable 't.nonconst_ternary_target_state' with non-constant target state values +%Warning-COVERIGN: t/t_cover_fsm_nonenum_unsupported_bad.v:214:54: Ignoring unsupported: FSM coverage on non-enum state variable 'nonconst_ternary_target_state' with non-constant target state values + : ... note: In instance 't' 214 | 2'h0: nonconst_ternary_target_state <= start ? 2'h1 : {1'b0, start}; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_cover_fsm_plain_always_warn_multi_bad.out b/test_regress/t/t_cover_fsm_plain_always_warn_multi_bad.out index 976c00e07..151330c24 100644 --- a/test_regress/t/t_cover_fsm_plain_always_warn_multi_bad.out +++ b/test_regress/t/t_cover_fsm_plain_always_warn_multi_bad.out @@ -1,12 +1,15 @@ -%Warning-COVERIGN: t/t_cover_fsm_plain_always_warn_multi_bad.v:86:5: Ignoring unsupported: FSM coverage on non-clocked always blocks requires a combinational sensitivity list or always_comb - 86 | case (state_q) +%Warning-COVERIGN: t/t_cover_fsm_plain_always_warn_multi_bad.v:25:5: Ignoring unsupported: FSM coverage on non-clocked always blocks requires a combinational sensitivity list or always_comb + : ... note: In instance 't.warn_edge_u' + 25 | case (state_q) | ^~~~ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. %Warning-COVERIGN: t/t_cover_fsm_plain_always_warn_multi_bad.v:55:5: Ignoring unsupported: FSM coverage on non-clocked always blocks requires a combinational sensitivity list or always_comb + : ... note: In instance 't.warn_case_next_u' 55 | case (state_d) | ^~~~ -%Warning-COVERIGN: t/t_cover_fsm_plain_always_warn_multi_bad.v:25:5: Ignoring unsupported: FSM coverage on non-clocked always blocks requires a combinational sensitivity list or always_comb - 25 | case (state_q) +%Warning-COVERIGN: t/t_cover_fsm_plain_always_warn_multi_bad.v:86:5: Ignoring unsupported: FSM coverage on non-clocked always blocks requires a combinational sensitivity list or always_comb + : ... note: In instance 't.warn_default_incl_u' + 86 | case (state_q) | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_cover_fsm_plain_always_zerohit_multi.out b/test_regress/t/t_cover_fsm_plain_always_zerohit_multi.out index 363177270..efd376e06 100644 --- a/test_regress/t/t_cover_fsm_plain_always_zerohit_multi.out +++ b/test_regress/t/t_cover_fsm_plain_always_zerohit_multi.out @@ -1,9 +1,9 @@ # SystemC::Coverage-3 -C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl28n5tfsm_arcpagev_fsm_arc/$rootot.near_canonical_state_d_case_u.state_d::S0->S1Fvt.near_canonical_state_d_case_u.state_dFfS0FtS1htop' 0 -C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl28n5tfsm_arcpagev_fsm_arc/$rootot.near_canonical_state_d_case_u.state_d::S0->S2Fvt.near_canonical_state_d_case_u.state_dFfS0FtS2htop' 0 -C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl28n5tfsm_statepagev_fsm_state/$rootot.near_canonical_state_d_case_u.state_d::S0Fvt.near_canonical_state_d_case_u.state_dFtS0htop' 0 -C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl28n5tfsm_statepagev_fsm_state/$rootot.near_canonical_state_d_case_u.state_d::S1Fvt.near_canonical_state_d_case_u.state_dFtS1htop' 0 -C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl28n5tfsm_statepagev_fsm_state/$rootot.near_canonical_state_d_case_u.state_d::S2Fvt.near_canonical_state_d_case_u.state_dFtS2htop' 0 -C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl60n5tfsm_statepagev_fsm_state/$rootot.selector_matches_noassign_u.state_q::S0Fvt.selector_matches_noassign_u.state_qFtS0htop' 0 -C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl60n5tfsm_statepagev_fsm_state/$rootot.selector_matches_noassign_u.state_q::S1Fvt.selector_matches_noassign_u.state_qFtS1htop' 0 -C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl60n5tfsm_statepagev_fsm_state/$rootot.selector_matches_noassign_u.state_q::S2Fvt.selector_matches_noassign_u.state_qFtS2htop' 0 +C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl28n5tfsm_arcpagev_fsm_arc/near_canonical_state_d_caseot.near_canonical_state_d_case_u.state_d::S0->S1Fvt.near_canonical_state_d_case_u.state_dFfS0FtS1htop.t.near_canonical_state_d_case_u' 0 +C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl28n5tfsm_arcpagev_fsm_arc/near_canonical_state_d_caseot.near_canonical_state_d_case_u.state_d::S0->S2Fvt.near_canonical_state_d_case_u.state_dFfS0FtS2htop.t.near_canonical_state_d_case_u' 0 +C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl28n5tfsm_statepagev_fsm_state/near_canonical_state_d_caseot.near_canonical_state_d_case_u.state_d::S0Fvt.near_canonical_state_d_case_u.state_dFtS0htop.t.near_canonical_state_d_case_u' 0 +C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl28n5tfsm_statepagev_fsm_state/near_canonical_state_d_caseot.near_canonical_state_d_case_u.state_d::S1Fvt.near_canonical_state_d_case_u.state_dFtS1htop.t.near_canonical_state_d_case_u' 0 +C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl28n5tfsm_statepagev_fsm_state/near_canonical_state_d_caseot.near_canonical_state_d_case_u.state_d::S2Fvt.near_canonical_state_d_case_u.state_dFtS2htop.t.near_canonical_state_d_case_u' 0 +C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl60n5tfsm_statepagev_fsm_state/selector_matches_noassignot.selector_matches_noassign_u.state_q::S0Fvt.selector_matches_noassign_u.state_qFtS0htop.t.selector_matches_noassign_u' 0 +C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl60n5tfsm_statepagev_fsm_state/selector_matches_noassignot.selector_matches_noassign_u.state_q::S1Fvt.selector_matches_noassign_u.state_qFtS1htop.t.selector_matches_noassign_u' 0 +C 'ft/t_cover_fsm_plain_always_zerohit_multi.vl60n5tfsm_statepagev_fsm_state/selector_matches_noassignot.selector_matches_noassign_u.state_q::S2Fvt.selector_matches_noassign_u.state_qFtS2htop.t.selector_matches_noassign_u' 0 diff --git a/test_regress/t/t_cover_fsm_reset_multi.out b/test_regress/t/t_cover_fsm_reset_multi.out index dd19f5207..001eaa8a9 100644 --- a/test_regress/t/t_cover_fsm_reset_multi.out +++ b/test_regress/t/t_cover_fsm_reset_multi.out @@ -1,4 +1,5 @@ %Warning-COVERIGN: t/t_cover_fsm_reset_multi.v:41:13: Ignoring unsupported: FSM coverage on reset branches with multiple assignments to the state variable + : ... note: In instance 't' 41 | state <= S1; | ^~ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest diff --git a/test_regress/t/t_cover_fsm_transition_shapes_multi.out b/test_regress/t/t_cover_fsm_transition_shapes_multi.out index 2fbc10baa..34fa47983 100644 --- a/test_regress/t/t_cover_fsm_transition_shapes_multi.out +++ b/test_regress/t/t_cover_fsm_transition_shapes_multi.out @@ -1,11 +1,11 @@ # SystemC::Coverage-3 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_arcpagev_fsm_arc/$rootot.forced_wide_u.state::31'h0->31'h1Fvt.forced_wide_u.stateFf31'h0Ft31'h1htop' 2 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_arcpagev_fsm_arc/$rootot.forced_wide_u.state::31'h1->31'h2Fvt.forced_wide_u.stateFf31'h1Ft31'h2htop' 2 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_arcpagev_fsm_arc/$rootot.forced_wide_u.state::ANY->31'h0[reset]Fvt.forced_wide_u.stateFfANYFt31'h0Fgresethtop' 1 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_statepagev_fsm_state/$rootot.forced_wide_u.state::31'h0Fvt.forced_wide_u.stateFt31'h0htop' 1 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_statepagev_fsm_state/$rootot.forced_wide_u.state::31'h1Fvt.forced_wide_u.stateFt31'h1htop' 2 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_statepagev_fsm_state/$rootot.forced_wide_u.state::31'h2Fvt.forced_wide_u.stateFt31'h2htop' 2 -C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_arcpagev_fsm_arc/$rootot.forced_if_wide_u.state::31'h0->31'h1Fvt.forced_if_wide_u.stateFf31'h0Ft31'h1htop' 4 -C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_arcpagev_fsm_arc/$rootot.forced_if_wide_u.state::31'h1->31'h0Fvt.forced_if_wide_u.stateFf31'h1Ft31'h0htop' 3 -C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_statepagev_fsm_state/$rootot.forced_if_wide_u.state::31'h0Fvt.forced_if_wide_u.stateFt31'h0htop' 3 -C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_statepagev_fsm_state/$rootot.forced_if_wide_u.state::31'h1Fvt.forced_if_wide_u.stateFt31'h1htop' 4 +C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_arcpagev_fsm_arc/fsm_forced_wideot.forced_wide_u.state::31'h0->31'h1Fvt.forced_wide_u.stateFf31'h0Ft31'h1htop.t.forced_wide_u' 2 +C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_arcpagev_fsm_arc/fsm_forced_wideot.forced_wide_u.state::31'h1->31'h2Fvt.forced_wide_u.stateFf31'h1Ft31'h2htop.t.forced_wide_u' 2 +C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_arcpagev_fsm_arc/fsm_forced_wideot.forced_wide_u.state::ANY->31'h0[reset]Fvt.forced_wide_u.stateFfANYFt31'h0Fgresethtop.t.forced_wide_u' 1 +C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_statepagev_fsm_state/fsm_forced_wideot.forced_wide_u.state::31'h0Fvt.forced_wide_u.stateFt31'h0htop.t.forced_wide_u' 1 +C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_statepagev_fsm_state/fsm_forced_wideot.forced_wide_u.state::31'h1Fvt.forced_wide_u.stateFt31'h1htop.t.forced_wide_u' 2 +C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_statepagev_fsm_state/fsm_forced_wideot.forced_wide_u.state::31'h2Fvt.forced_wide_u.stateFt31'h2htop.t.forced_wide_u' 2 +C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_arcpagev_fsm_arc/fsm_forced_if_wideot.forced_if_wide_u.state::31'h0->31'h1Fvt.forced_if_wide_u.stateFf31'h0Ft31'h1htop.t.forced_if_wide_u' 4 +C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_arcpagev_fsm_arc/fsm_forced_if_wideot.forced_if_wide_u.state::31'h1->31'h0Fvt.forced_if_wide_u.stateFf31'h1Ft31'h0htop.t.forced_if_wide_u' 3 +C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_statepagev_fsm_state/fsm_forced_if_wideot.forced_if_wide_u.state::31'h0Fvt.forced_if_wide_u.stateFt31'h0htop.t.forced_if_wide_u' 3 +C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_statepagev_fsm_state/fsm_forced_if_wideot.forced_if_wide_u.state::31'h1Fvt.forced_if_wide_u.stateFt31'h1htop.t.forced_if_wide_u' 4 diff --git a/test_regress/t/t_cover_fsm_transition_shapes_no_inline.out b/test_regress/t/t_cover_fsm_transition_shapes_no_inline.out deleted file mode 100644 index 34fa47983..000000000 --- a/test_regress/t/t_cover_fsm_transition_shapes_no_inline.out +++ /dev/null @@ -1,11 +0,0 @@ -# SystemC::Coverage-3 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_arcpagev_fsm_arc/fsm_forced_wideot.forced_wide_u.state::31'h0->31'h1Fvt.forced_wide_u.stateFf31'h0Ft31'h1htop.t.forced_wide_u' 2 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_arcpagev_fsm_arc/fsm_forced_wideot.forced_wide_u.state::31'h1->31'h2Fvt.forced_wide_u.stateFf31'h1Ft31'h2htop.t.forced_wide_u' 2 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_arcpagev_fsm_arc/fsm_forced_wideot.forced_wide_u.state::ANY->31'h0[reset]Fvt.forced_wide_u.stateFfANYFt31'h0Fgresethtop.t.forced_wide_u' 1 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_statepagev_fsm_state/fsm_forced_wideot.forced_wide_u.state::31'h0Fvt.forced_wide_u.stateFt31'h0htop.t.forced_wide_u' 1 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_statepagev_fsm_state/fsm_forced_wideot.forced_wide_u.state::31'h1Fvt.forced_wide_u.stateFt31'h1htop.t.forced_wide_u' 2 -C 'ft/t_cover_fsm_transition_shapes_multi.vl724n7tfsm_statepagev_fsm_state/fsm_forced_wideot.forced_wide_u.state::31'h2Fvt.forced_wide_u.stateFt31'h2htop.t.forced_wide_u' 2 -C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_arcpagev_fsm_arc/fsm_forced_if_wideot.forced_if_wide_u.state::31'h0->31'h1Fvt.forced_if_wide_u.stateFf31'h0Ft31'h1htop.t.forced_if_wide_u' 4 -C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_arcpagev_fsm_arc/fsm_forced_if_wideot.forced_if_wide_u.state::31'h1->31'h0Fvt.forced_if_wide_u.stateFf31'h1Ft31'h0htop.t.forced_if_wide_u' 3 -C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_statepagev_fsm_state/fsm_forced_if_wideot.forced_if_wide_u.state::31'h0Fvt.forced_if_wide_u.stateFt31'h0htop.t.forced_if_wide_u' 3 -C 'ft/t_cover_fsm_transition_shapes_multi.vl742n5tfsm_statepagev_fsm_state/fsm_forced_if_wideot.forced_if_wide_u.state::31'h1Fvt.forced_if_wide_u.stateFt31'h1htop.t.forced_if_wide_u' 4 diff --git a/test_regress/t/t_cover_fsm_transition_shapes_no_inline.py b/test_regress/t/t_cover_fsm_transition_shapes_no_inline.py index 076f1c67e..dd0925e81 100755 --- a/test_regress/t/t_cover_fsm_transition_shapes_no_inline.py +++ b/test_regress/t/t_cover_fsm_transition_shapes_no_inline.py @@ -7,16 +7,8 @@ # SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -# Same as t_cover_fsm_transition_shapes_multi, but without module inlining, so -# the coverage declarations stay in the scope of the instance that owns them. -# The emitted hierarchy is the scope name plus AstNodeCoverDecl::hier(), so hier -# must be relative to that scope. -# -# Note this golden still differs from the inlined one, which reports the top -# scope and '$root', because V3FsmDetect::detect runs after V3Inline and so only -# ever sees the flattened design. Were it to run before, V3Inline would prefix -# the instance names onto hier and both would report the same, at which point -# this test should compare against t_cover_fsm_transition_shapes_multi.out. +# Same as t_cover_fsm_transition_shapes_multi, but without module inlining, +# which must not change the coverage output. import vltest_bootstrap @@ -27,6 +19,6 @@ test.compile(verilator_flags2=['--cc --coverage-fsm', '-fno-inline']) test.execute() -test.files_identical(test.obj_dir + "/coverage.dat", "t/" + test.name + ".out") +test.files_identical(test.obj_dir + "/coverage.dat", "t/t_cover_fsm_transition_shapes_multi.out") test.passes() diff --git a/test_regress/t/t_do_while_continue_bad.out b/test_regress/t/t_do_while_continue_bad.out index 2db86ede9..289a0a81d 100644 --- a/test_regress/t/t_do_while_continue_bad.out +++ b/test_regress/t/t_do_while_continue_bad.out @@ -1,4 +1,5 @@ %Warning-INFINITELOOP: t/t_do_while_continue_bad.v:12:5: Infinite loop (condition always true) + : ... note: In instance 't' 12 | do begin | ^~ ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest diff --git a/test_regress/t/t_fsmmulti_combo_multi_warn_bad.out b/test_regress/t/t_fsmmulti_combo_multi_warn_bad.out index 367f70f55..d9f6ae2f0 100644 --- a/test_regress/t/t_fsmmulti_combo_multi_warn_bad.out +++ b/test_regress/t/t_fsmmulti_combo_multi_warn_bad.out @@ -1,4 +1,35 @@ +%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:36:21: FSM coverage: multiple supported transition candidates found in the same combinational always block. Only the first candidate will be instrumented. + : ... note: In instance 't.same_u' + 36 | B0: state_b_d = B1; + | ^ + t/t_fsmmulti_combo_multi_warn_bad.v:32:21: ... Location of first supported candidate for 't.same_u.state_a_q' + 32 | A0: state_a_d = A1; + | ^ + ... For warning description see https://verilator.org/warn/FSMMULTI?v=latest + ... Use "/* verilator lint_off FSMMULTI */" and lint_on around source to disable this message. +%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:73:19: FSM coverage: multiple supported transition candidates found for the same FSM in combinational always blocks. Only the first candidate will be instrumented. + : ... note: In instance 't.split_u' + 73 | S0: state_d = S1; + | ^ + t/t_fsmmulti_combo_multi_warn_bad.v:65:19: ... Location of first supported candidate for 't.split_u.state_q' + 65 | S0: state_d = S1; + | ^ +%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:107:5: FSM coverage: multiple supported transition candidates found in the same combinational always block. Only the first candidate will be instrumented. + : ... note: In instance 't.same_if_u' + 107 | if (state_b_q == B0) state_b_d = B1; + | ^~ + t/t_fsmmulti_combo_multi_warn_bad.v:105:5: ... Location of first supported candidate for 't.same_if_u.state_a_q' + 105 | if (state_a_q == A0) state_a_d = A1; + | ^~ +%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:140:5: FSM coverage: multiple supported transition candidates found for the same FSM in combinational always blocks. Only the first candidate will be instrumented. + : ... note: In instance 't.split_if_u' + 140 | if (state_q == S0) state_d = S1; + | ^~ + t/t_fsmmulti_combo_multi_warn_bad.v:134:5: ... Location of first supported candidate for 't.split_if_u.state_q' + 134 | if (state_q == S0) state_d = S1; + | ^~ %Warning-COVERIGN: t/t_fsmmulti_combo_multi_warn_bad.v:165:5: Ignoring unsupported: FSM coverage on multiple supported if-chain statements found in the same combinational always block. Only the first candidate will be instrumented. + : ... note: In instance 't.same_same_if_u' 165 | if (state_q == S1) state_d = S0; | ^~ t/t_fsmmulti_combo_multi_warn_bad.v:163:5: ... Location of first supported candidate for 't.same_same_if_u.state_q' @@ -6,30 +37,4 @@ | ^~ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. -%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:140:5: FSM coverage: multiple supported transition candidates found for the same FSM in combinational always blocks. Only the first candidate will be instrumented. - 140 | if (state_q == S0) state_d = S1; - | ^~ - t/t_fsmmulti_combo_multi_warn_bad.v:134:5: ... Location of first supported candidate for 't.split_if_u.state_q' - 134 | if (state_q == S0) state_d = S1; - | ^~ - ... For warning description see https://verilator.org/warn/FSMMULTI?v=latest - ... Use "/* verilator lint_off FSMMULTI */" and lint_on around source to disable this message. -%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:107:5: FSM coverage: multiple supported transition candidates found in the same combinational always block. Only the first candidate will be instrumented. - 107 | if (state_b_q == B0) state_b_d = B1; - | ^~ - t/t_fsmmulti_combo_multi_warn_bad.v:105:5: ... Location of first supported candidate for 't.same_if_u.state_a_q' - 105 | if (state_a_q == A0) state_a_d = A1; - | ^~ -%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:73:19: FSM coverage: multiple supported transition candidates found for the same FSM in combinational always blocks. Only the first candidate will be instrumented. - 73 | S0: state_d = S1; - | ^ - t/t_fsmmulti_combo_multi_warn_bad.v:65:19: ... Location of first supported candidate for 't.split_u.state_q' - 65 | S0: state_d = S1; - | ^ -%Warning-FSMMULTI: t/t_fsmmulti_combo_multi_warn_bad.v:36:21: FSM coverage: multiple supported transition candidates found in the same combinational always block. Only the first candidate will be instrumented. - 36 | B0: state_b_d = B1; - | ^ - t/t_fsmmulti_combo_multi_warn_bad.v:32:21: ... Location of first supported candidate for 't.same_u.state_a_q' - 32 | A0: state_a_d = A1; - | ^ %Error: Exiting due to diff --git a/test_regress/t/t_fsmmulti_same_bad.out b/test_regress/t/t_fsmmulti_same_bad.out index 85387cd8c..623783e1d 100644 --- a/test_regress/t/t_fsmmulti_same_bad.out +++ b/test_regress/t/t_fsmmulti_same_bad.out @@ -1,4 +1,5 @@ %Warning-COVERIGN: t/t_fsmmulti_same_bad.v:34:5: Ignoring unsupported: FSM coverage on multiple supported case statements found in the same always block. Only the first candidate will be instrumented. + : ... note: In instance 't' 34 | case (state) | ^~~~ t/t_fsmmulti_same_bad.v:29:7: ... Location of first supported candidate for 't.state' @@ -7,6 +8,7 @@ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. %Warning-COVERIGN: t/t_fsmmulti_same_bad.v:44:5: Ignoring unsupported: FSM coverage on multiple supported transition candidates found in the same always block. Only the first candidate will be instrumented. + : ... note: In instance 't' 44 | if (state_if == S1) state_if <= S2; | ^~ t/t_fsmmulti_same_bad.v:41:5: ... Location of first supported candidate for 't.state_if' diff --git a/test_regress/t/t_fsmmulti_warn_bad.out b/test_regress/t/t_fsmmulti_warn_bad.out index 69bfb07fe..6f33321f6 100644 --- a/test_regress/t/t_fsmmulti_warn_bad.out +++ b/test_regress/t/t_fsmmulti_warn_bad.out @@ -1,4 +1,5 @@ %Warning-FSMMULTI: t/t_fsmmulti_warn_bad.v:41:5: FSM coverage: multiple enum-typed case statements found in the same always block. Only the first candidate will be instrumented. + : ... note: In instance 't' 41 | case (state_b) | ^~~~ t/t_fsmmulti_warn_bad.v:37:5: ... Location of first supported candidate for 't.state_a' @@ -7,6 +8,7 @@ ... For warning description see https://verilator.org/warn/FSMMULTI?v=latest ... Use "/* verilator lint_off FSMMULTI */" and lint_on around source to disable this message. %Warning-FSMMULTI: t/t_fsmmulti_warn_bad.v:51:5: FSM coverage: multiple enum-typed transition candidates found in the same always block. Only the first candidate will be instrumented. + : ... note: In instance 't' 51 | if (state_d == D0) state_d <= D1; | ^~ t/t_fsmmulti_warn_bad.v:48:5: ... Location of first supported candidate for 't.state_c' diff --git a/test_regress/t/t_inline_task_name.py b/test_regress/t/t_inline_task_name.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_inline_task_name.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inline_task_name.v b/test_regress/t/t_inline_task_name.v new file mode 100644 index 000000000..62cc6704f --- /dev/null +++ b/test_regress/t/t_inline_task_name.v @@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 +// SPDX-FileCopyrightText: 2026 Wilson Snyder + +// verilog_format: off +`define stop $stop +`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0) +// verilog_format: on + +module t; + + logic clk = 0; + always #5 clk = ~clk; + + integer cyc = 0; + + int a_out; + int b_out; + int c_out; + + suba ua(.clk(clk), .base(32'd10), .out(a_out)); + suba ub(.clk(clk), .base(32'd20), .out(b_out)); + subb uc(.clk(clk), .base(32'd30), .out(c_out)); + + function automatic int twiddle(int x); + return x + 1; + endfunction + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 3) begin + `check(twiddle(0), 1); + `check(a_out, 12); + `check(b_out, 22); + `check(c_out, 33); + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module suba(input clk, input int base, output int out); + /*verilator inline_module*/ + + int val; + + function automatic int twiddle(int x); + return x + 2; + endfunction + + task automatic compute(input int x, output int y); + y = twiddle(x); + endtask + + always @(posedge clk) begin + compute(base, val); + out <= val; + end +endmodule + +module subb(input clk, input int base, output int out); + /*verilator no_inline_module*/ + + int val; + + function automatic int twiddle(int x); + return x + 3; + endfunction + + task automatic compute(input int x, output int y); + y = twiddle(x); + endtask + + always @(posedge clk) begin + compute(base, val); + out <= val; + end +endmodule diff --git a/test_regress/t/t_json_only_flat.out b/test_regress/t/t_json_only_flat.out index 7e43c9759..0c82ea207 100644 --- a/test_regress/t/t_json_only_flat.out +++ b/test_regress/t/t_json_only_flat.out @@ -1,257 +1,262 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","resolvedTopModuleName":"t","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","topScopep":"(F)", "modulesp": [ {"type":"MODULE","name":"$root","addr":"(G)","loc":"d,7:8,7:9","origName":"$root","verilogName":"$root","level":1,"depth":1,"modPublic":true,"unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"1ps", + "inlinesp": [ + {"type":"CELLINLINE","name":"t.cell2","addr":"(H)","loc":"d,39:8,39:13","origModName":"mod2"}, + {"type":"CELLINLINE","name":"t.cell1","addr":"(I)","loc":"d,33:5,33:10","origModName":"mod1"}, + {"type":"CELLINLINE","name":"t","addr":"(J)","loc":"d,7:8,7:9","origModName":"t"} + ], "stmtsp": [ - {"type":"VAR","name":"q","addr":"(H)","loc":"d,16:21,16:22","dtypep":"(I)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","declDirection":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic"}, - {"type":"VAR","name":"clk","addr":"(J)","loc":"d,14:9,14:12","dtypep":"(K)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"d","addr":"(L)","loc":"d,15:15,15:16","dtypep":"(I)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"CELL","name":"$unit","addr":"(M)","loc":"a,0:0,0:0","modName":"__024unit","origName":"__024unit","verilogName":"\\$unit ","modp":"(E)"}, - {"type":"VAR","name":"t.q","addr":"(N)","loc":"d,16:21,16:22","dtypep":"(I)","origName":"q","verilogName":"q","direction":"NONE","declDirection":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic"}, - {"type":"VAR","name":"t.clk","addr":"(O)","loc":"d,14:9,14:12","dtypep":"(K)","origName":"clk","verilogName":"clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"t.d","addr":"(P)","loc":"d,15:15,15:16","dtypep":"(I)","origName":"d","verilogName":"d","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"t.between","addr":"(Q)","loc":"d,18:15,18:22","dtypep":"(I)","origName":"between","verilogName":"between","direction":"NONE","declDirection":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic"}, - {"type":"VAR","name":"t.direct_named","addr":"(R)","loc":"d,19:9,19:21","dtypep":"(K)","origName":"direct_named","verilogName":"direct_named","direction":"NONE","declDirection":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic"}, - {"type":"VAR","name":"t.computed_named","addr":"(S)","loc":"d,20:9,20:23","dtypep":"(K)","origName":"computed_named","verilogName":"computed_named","direction":"NONE","declDirection":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic"}, - {"type":"VAR","name":"t.anonymous_expr","addr":"(T)","loc":"d,21:9,21:23","dtypep":"(K)","origName":"anonymous_expr","verilogName":"anonymous_expr","direction":"NONE","declDirection":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic"}, - {"type":"VAR","name":"t.S_IDLE","addr":"(U)","loc":"d,23:26,23:32","dtypep":"(V)","origName":"S_IDLE","verilogName":"S_IDLE","direction":"NONE","declDirection":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true, - "valuep": [ - {"type":"CONST","name":"2'h0","addr":"(W)","loc":"d,23:35,23:40","dtypep":"(X)"} - ]}, - {"type":"VAR","name":"t.S_FETCH","addr":"(Y)","loc":"d,24:26,24:33","dtypep":"(V)","origName":"S_FETCH","verilogName":"S_FETCH","direction":"NONE","declDirection":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true, - "valuep": [ - {"type":"CONST","name":"2'h1","addr":"(Z)","loc":"d,24:36,24:41","dtypep":"(X)"} - ]}, - {"type":"VAR","name":"t.S_EXEC","addr":"(AB)","loc":"d,25:26,25:32","dtypep":"(V)","origName":"S_EXEC","verilogName":"S_EXEC","direction":"NONE","declDirection":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true, - "valuep": [ - {"type":"CONST","name":"2'h2","addr":"(BB)","loc":"d,25:43,25:44","dtypep":"(V)"} - ]}, - {"type":"VAR","name":"t.cell2.clk","addr":"(CB)","loc":"d,62:11,62:14","dtypep":"(K)","origName":"clk","verilogName":"clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"t.cell2.d","addr":"(DB)","loc":"d,63:17,63:18","dtypep":"(I)","origName":"d","verilogName":"d","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"t.cell2.q","addr":"(EB)","loc":"d,64:23,64:24","dtypep":"(I)","origName":"q","verilogName":"q","direction":"NONE","declDirection":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic"}, - {"type":"VAR","name":"t.cell1.WIDTH","addr":"(FB)","loc":"d,48:15,48:20","dtypep":"(GB)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","declDirection":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true, - "valuep": [ - {"type":"CONST","name":"32'sh4","addr":"(HB)","loc":"d,32:14,32:15","dtypep":"(IB)"} - ]}, - {"type":"VAR","name":"t.cell1.clk","addr":"(JB)","loc":"d,50:11,50:14","dtypep":"(K)","origName":"clk","verilogName":"clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"t.cell1.d","addr":"(KB)","loc":"d,51:23,51:24","dtypep":"(I)","origName":"d","verilogName":"d","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"t.cell1.q","addr":"(LB)","loc":"d,52:30,52:31","dtypep":"(I)","origName":"q","verilogName":"q","direction":"NONE","declDirection":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"t.cell1.IGNORED","addr":"(MB)","loc":"d,55:14,55:21","dtypep":"(GB)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","declDirection":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true, - "valuep": [ - {"type":"CONST","name":"32'sh1","addr":"(NB)","loc":"d,55:24,55:25","dtypep":"(IB)"} - ]}, + {"type":"VAR","name":"q","addr":"(K)","loc":"d,16:21,16:22","dtypep":"(L)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","declDirection":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic"}, + {"type":"VAR","name":"clk","addr":"(M)","loc":"d,14:9,14:12","dtypep":"(N)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"d","addr":"(O)","loc":"d,15:15,15:16","dtypep":"(L)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"CELL","name":"$unit","addr":"(P)","loc":"a,0:0,0:0","modName":"__024unit","origName":"__024unit","verilogName":"\\$unit ","modp":"(E)"}, {"type":"TOPSCOPE","addr":"(F)","loc":"d,7:8,7:9", "scopep": [ - {"type":"SCOPE","name":"TOP","addr":"(OB)","loc":"d,7:8,7:9","modp":"(G)", + {"type":"SCOPE","name":"TOP","addr":"(Q)","loc":"d,7:8,7:9","modp":"(G)", "varsp": [ - {"type":"VARSCOPE","name":"q","addr":"(PB)","loc":"d,16:21,16:22","dtypep":"(I)","isTrace":true,"scopep":"(OB)","varp":"(H)"}, - {"type":"VARSCOPE","name":"clk","addr":"(QB)","loc":"d,14:9,14:12","dtypep":"(K)","isTrace":true,"scopep":"(OB)","varp":"(J)"}, - {"type":"VARSCOPE","name":"d","addr":"(RB)","loc":"d,15:15,15:16","dtypep":"(I)","isTrace":true,"scopep":"(OB)","varp":"(L)"}, - {"type":"VARSCOPE","name":"t.q","addr":"(SB)","loc":"d,16:21,16:22","dtypep":"(I)","isTrace":true,"scopep":"(OB)","varp":"(N)"}, - {"type":"VARSCOPE","name":"t.clk","addr":"(TB)","loc":"d,14:9,14:12","dtypep":"(K)","isTrace":true,"scopep":"(OB)","varp":"(O)"}, - {"type":"VARSCOPE","name":"t.d","addr":"(UB)","loc":"d,15:15,15:16","dtypep":"(I)","isTrace":true,"scopep":"(OB)","varp":"(P)"}, - {"type":"VARSCOPE","name":"t.between","addr":"(VB)","loc":"d,18:15,18:22","dtypep":"(I)","isTrace":true,"scopep":"(OB)","varp":"(Q)"}, - {"type":"VARSCOPE","name":"t.direct_named","addr":"(WB)","loc":"d,19:9,19:21","dtypep":"(K)","isTrace":true,"scopep":"(OB)","varp":"(R)"}, - {"type":"VARSCOPE","name":"t.computed_named","addr":"(XB)","loc":"d,20:9,20:23","dtypep":"(K)","isTrace":true,"scopep":"(OB)","varp":"(S)"}, - {"type":"VARSCOPE","name":"t.anonymous_expr","addr":"(YB)","loc":"d,21:9,21:23","dtypep":"(K)","isTrace":true,"scopep":"(OB)","varp":"(T)"}, - {"type":"VARSCOPE","name":"t.S_IDLE","addr":"(ZB)","loc":"d,23:26,23:32","dtypep":"(V)","isTrace":true,"scopep":"(OB)","varp":"(U)"}, - {"type":"VARSCOPE","name":"t.S_FETCH","addr":"(AC)","loc":"d,24:26,24:33","dtypep":"(V)","isTrace":true,"scopep":"(OB)","varp":"(Y)"}, - {"type":"VARSCOPE","name":"t.S_EXEC","addr":"(BC)","loc":"d,25:26,25:32","dtypep":"(V)","isTrace":true,"scopep":"(OB)","varp":"(AB)"}, - {"type":"VARSCOPE","name":"t.cell2.clk","addr":"(CC)","loc":"d,62:11,62:14","dtypep":"(K)","isTrace":true,"scopep":"(OB)","varp":"(CB)"}, - {"type":"VARSCOPE","name":"t.cell2.d","addr":"(DC)","loc":"d,63:17,63:18","dtypep":"(I)","isTrace":true,"scopep":"(OB)","varp":"(DB)"}, - {"type":"VARSCOPE","name":"t.cell2.q","addr":"(EC)","loc":"d,64:23,64:24","dtypep":"(I)","isTrace":true,"scopep":"(OB)","varp":"(EB)"}, - {"type":"VARSCOPE","name":"t.cell1.WIDTH","addr":"(FC)","loc":"d,48:15,48:20","dtypep":"(GB)","isTrace":true,"scopep":"(OB)","varp":"(FB)"}, - {"type":"VARSCOPE","name":"t.cell1.clk","addr":"(GC)","loc":"d,50:11,50:14","dtypep":"(K)","isTrace":true,"scopep":"(OB)","varp":"(JB)"}, - {"type":"VARSCOPE","name":"t.cell1.d","addr":"(HC)","loc":"d,51:23,51:24","dtypep":"(I)","isTrace":true,"scopep":"(OB)","varp":"(KB)"}, - {"type":"VARSCOPE","name":"t.cell1.q","addr":"(IC)","loc":"d,52:30,52:31","dtypep":"(I)","isTrace":true,"scopep":"(OB)","varp":"(LB)"}, - {"type":"VARSCOPE","name":"t.cell1.IGNORED","addr":"(JC)","loc":"d,55:14,55:21","dtypep":"(GB)","isTrace":true,"scopep":"(OB)","varp":"(MB)"} + {"type":"VARSCOPE","name":"q","addr":"(R)","loc":"d,16:21,16:22","dtypep":"(L)","isTrace":true,"scopep":"(Q)","varp":"(K)"}, + {"type":"VARSCOPE","name":"clk","addr":"(S)","loc":"d,14:9,14:12","dtypep":"(N)","isTrace":true,"scopep":"(Q)","varp":"(M)"}, + {"type":"VARSCOPE","name":"d","addr":"(T)","loc":"d,15:15,15:16","dtypep":"(L)","isTrace":true,"scopep":"(Q)","varp":"(O)"}, + {"type":"VARSCOPE","name":"t.q","addr":"(U)","loc":"d,16:21,16:22","dtypep":"(L)","isTrace":true,"scopep":"(Q)","varp":"(V)"}, + {"type":"VARSCOPE","name":"t.clk","addr":"(W)","loc":"d,14:9,14:12","dtypep":"(N)","isTrace":true,"scopep":"(Q)","varp":"(X)"}, + {"type":"VARSCOPE","name":"t.d","addr":"(Y)","loc":"d,15:15,15:16","dtypep":"(L)","isTrace":true,"scopep":"(Q)","varp":"(Z)"}, + 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{"type":"VAR","name":"t.d","addr":"(Z)","loc":"d,15:15,15:16","dtypep":"(L)","origName":"d","verilogName":"d","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"t.between","addr":"(BB)","loc":"d,18:15,18:22","dtypep":"(L)","origName":"between","verilogName":"between","direction":"NONE","declDirection":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic"}, + {"type":"VAR","name":"t.direct_named","addr":"(DB)","loc":"d,19:9,19:21","dtypep":"(N)","origName":"direct_named","verilogName":"direct_named","direction":"NONE","declDirection":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic"}, + {"type":"VAR","name":"t.computed_named","addr":"(FB)","loc":"d,20:9,20:23","dtypep":"(N)","origName":"computed_named","verilogName":"computed_named","direction":"NONE","declDirection":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic"}, + {"type":"VAR","name":"t.anonymous_expr","addr":"(HB)","loc":"d,21:9,21:23","dtypep":"(N)","origName":"anonymous_expr","verilogName":"anonymous_expr","direction":"NONE","declDirection":"NONE","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic"}, + {"type":"VAR","name":"t.S_IDLE","addr":"(KB)","loc":"d,23:26,23:32","dtypep":"(JB)","origName":"S_IDLE","verilogName":"S_IDLE","direction":"NONE","declDirection":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true, + "valuep": [ + {"type":"CONST","name":"2'h0","addr":"(CF)","loc":"d,23:35,23:40","dtypep":"(CD)"} + ]}, + {"type":"VAR","name":"t.S_FETCH","addr":"(MB)","loc":"d,24:26,24:33","dtypep":"(JB)","origName":"S_FETCH","verilogName":"S_FETCH","direction":"NONE","declDirection":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true, + "valuep": [ + {"type":"CONST","name":"2'h1","addr":"(DF)","loc":"d,24:36,24:41","dtypep":"(CD)"} + ]}, + {"type":"VAR","name":"t.S_EXEC","addr":"(OB)","loc":"d,25:26,25:32","dtypep":"(JB)","origName":"S_EXEC","verilogName":"S_EXEC","direction":"NONE","declDirection":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true, + "valuep": [ + {"type":"CONST","name":"2'h2","addr":"(EF)","loc":"d,25:43,25:44","dtypep":"(JB)"} + ]}, + {"type":"VAR","name":"t.cell2.clk","addr":"(QB)","loc":"d,62:11,62:14","dtypep":"(N)","origName":"clk","verilogName":"clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"t.cell2.d","addr":"(SB)","loc":"d,63:17,63:18","dtypep":"(L)","origName":"d","verilogName":"d","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"t.cell2.q","addr":"(UB)","loc":"d,64:23,64:24","dtypep":"(L)","origName":"q","verilogName":"q","direction":"NONE","declDirection":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic"}, + {"type":"VAR","name":"t.cell1.WIDTH","addr":"(XB)","loc":"d,48:15,48:20","dtypep":"(WB)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","declDirection":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true, + "valuep": [ + {"type":"CONST","name":"32'sh4","addr":"(FF)","loc":"d,32:14,32:15","dtypep":"(GF)"} + ]}, + {"type":"VAR","name":"t.cell1.clk","addr":"(ZB)","loc":"d,50:11,50:14","dtypep":"(N)","origName":"clk","verilogName":"clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"t.cell1.d","addr":"(BC)","loc":"d,51:23,51:24","dtypep":"(L)","origName":"d","verilogName":"d","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"t.cell1.q","addr":"(DC)","loc":"d,52:30,52:31","dtypep":"(L)","origName":"q","verilogName":"q","direction":"NONE","declDirection":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"t.cell1.IGNORED","addr":"(FC)","loc":"d,55:14,55:21","dtypep":"(WB)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","declDirection":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true, + "valuep": [ + {"type":"CONST","name":"32'sh1","addr":"(HF)","loc":"d,55:24,55:25","dtypep":"(GF)"} ]} ]}, {"type":"PACKAGE","name":"$unit","addr":"(E)","loc":"a,0:0,0:0","origName":"__024unit","verilogName":"\\$unit ","level":3,"depth":3,"inLibrary":true,"unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"1ps"} @@ -259,20 +264,20 @@ "miscsp": [ {"type":"TYPETABLE","addr":"(C)","loc":"a,0:0,0:0", "typesp": [ - {"type":"BASICDTYPE","name":"bit","addr":"(X)","loc":"d,23:35,23:40","dtypep":"(X)","keyword":"bit","range":"1:0","generic":true}, - {"type":"BASICDTYPE","name":"logic","addr":"(K)","loc":"d,27:32,27:34","dtypep":"(K)","keyword":"logic","generic":true}, - {"type":"BASICDTYPE","name":"logic","addr":"(V)","loc":"d,23:14,23:19","dtypep":"(V)","keyword":"logic","range":"1:0","generic":true}, - {"type":"BASICDTYPE","name":"logic","addr":"(GB)","loc":"d,48:15,48:20","dtypep":"(GB)","keyword":"logic","range":"31:0","generic":true,"signed":true}, - {"type":"BASICDTYPE","name":"logic","addr":"(I)","loc":"d,16:15,16:16","dtypep":"(I)","keyword":"logic","range":"3:0","generic":true}, - {"type":"BASICDTYPE","name":"logic","addr":"(SC)","loc":"d,27:26,27:27","dtypep":"(SC)","keyword":"logic","range":"1:0","generic":true,"signed":true}, - {"type":"BASICDTYPE","name":"bit","addr":"(NC)","loc":"d,27:32,27:34","dtypep":"(NC)","keyword":"bit","generic":true}, - {"type":"BASICDTYPE","name":"bit","addr":"(IB)","loc":"d,29:48,29:49","dtypep":"(IB)","keyword":"bit","range":"31:0","generic":true,"signed":true} + {"type":"BASICDTYPE","name":"bit","addr":"(CD)","loc":"d,23:35,23:40","dtypep":"(CD)","keyword":"bit","range":"1:0","generic":true}, + {"type":"BASICDTYPE","name":"logic","addr":"(N)","loc":"d,27:32,27:34","dtypep":"(N)","keyword":"logic","generic":true}, + {"type":"BASICDTYPE","name":"logic","addr":"(JB)","loc":"d,23:14,23:19","dtypep":"(JB)","keyword":"logic","range":"1:0","generic":true}, + {"type":"BASICDTYPE","name":"logic","addr":"(WB)","loc":"d,48:15,48:20","dtypep":"(WB)","keyword":"logic","range":"31:0","generic":true,"signed":true}, + {"type":"BASICDTYPE","name":"logic","addr":"(L)","loc":"d,16:15,16:16","dtypep":"(L)","keyword":"logic","range":"3:0","generic":true}, + {"type":"BASICDTYPE","name":"logic","addr":"(OC)","loc":"d,27:26,27:27","dtypep":"(OC)","keyword":"logic","range":"1:0","generic":true,"signed":true}, + {"type":"BASICDTYPE","name":"bit","addr":"(JC)","loc":"d,27:32,27:34","dtypep":"(JC)","keyword":"bit","generic":true}, + {"type":"BASICDTYPE","name":"bit","addr":"(GF)","loc":"d,29:48,29:49","dtypep":"(GF)","keyword":"bit","range":"31:0","generic":true,"signed":true} ]}, {"type":"CONSTPOOL","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(FF)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"NONE", + {"type":"MODULE","name":"@CONST-POOL@","addr":"(IF)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"NONE", "stmtsp": [ - {"type":"SCOPE","name":"@CONST-POOL@","addr":"(GF)","loc":"a,0:0,0:0","modp":"(FF)"} + {"type":"SCOPE","name":"@CONST-POOL@","addr":"(JF)","loc":"a,0:0,0:0","modp":"(IF)"} ]} ]} ]} diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.out b/test_regress/t/t_json_only_flat_no_inline_mod.out index acceb4982..c1184f579 100644 --- a/test_regress/t/t_json_only_flat_no_inline_mod.out +++ b/test_regress/t/t_json_only_flat_no_inline_mod.out @@ -1,55 +1,59 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","resolvedTopModuleName":"top","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","topScopep":"(F)", "modulesp": [ {"type":"MODULE","name":"$root","addr":"(G)","loc":"d,11:8,11:11","origName":"$root","verilogName":"$root","level":1,"depth":1,"modPublic":true,"unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"1ps", + "inlinesp": [ + {"type":"CELLINLINE","name":"top.f","addr":"(H)","loc":"d,12:7,12:8","origModName":"foo"}, + {"type":"CELLINLINE","name":"top","addr":"(I)","loc":"d,11:8,11:11","origModName":"top"} + ], "stmtsp": [ - {"type":"VAR","name":"i_clk","addr":"(H)","loc":"d,11:24,11:29","dtypep":"(I)","origName":"i_clk","verilogName":"i_clk","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"CELL","name":"$unit","addr":"(J)","loc":"a,0:0,0:0","modName":"__024unit","origName":"__024unit","verilogName":"\\$unit ","modp":"(E)"}, - {"type":"VAR","name":"top.i_clk","addr":"(K)","loc":"d,11:24,11:29","dtypep":"(I)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"top.f.i_clk","addr":"(L)","loc":"d,7:24,7:29","dtypep":"(I)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"i_clk","addr":"(J)","loc":"d,11:24,11:29","dtypep":"(K)","origName":"i_clk","verilogName":"i_clk","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"CELL","name":"$unit","addr":"(L)","loc":"a,0:0,0:0","modName":"__024unit","origName":"__024unit","verilogName":"\\$unit ","modp":"(E)"}, {"type":"TOPSCOPE","addr":"(F)","loc":"d,11:8,11:11", "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(M)","loc":"d,11:8,11:11","modp":"(G)", "varsp": [ - {"type":"VARSCOPE","name":"i_clk","addr":"(N)","loc":"d,11:24,11:29","dtypep":"(I)","isTrace":true,"scopep":"(M)","varp":"(H)"}, - {"type":"VARSCOPE","name":"top.i_clk","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(I)","isTrace":true,"scopep":"(M)","varp":"(K)"}, - {"type":"VARSCOPE","name":"top.f.i_clk","addr":"(P)","loc":"d,7:24,7:29","dtypep":"(I)","isTrace":true,"scopep":"(M)","varp":"(L)"} + {"type":"VARSCOPE","name":"i_clk","addr":"(N)","loc":"d,11:24,11:29","dtypep":"(K)","isTrace":true,"scopep":"(M)","varp":"(J)"}, + {"type":"VARSCOPE","name":"top.i_clk","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(K)","isTrace":true,"scopep":"(M)","varp":"(P)"}, + {"type":"VARSCOPE","name":"top.f.i_clk","addr":"(Q)","loc":"d,7:24,7:29","dtypep":"(K)","scopep":"(M)","varp":"(R)"} ], "blocksp": [ - {"type":"ALWAYS","addr":"(Q)","loc":"d,11:24,11:29","keyword":"cont_assign", + {"type":"ALWAYS","addr":"(S)","loc":"d,11:24,11:29","keyword":"cont_assign", "stmtsp": [ - {"type":"ASSIGNW","addr":"(R)","loc":"d,11:24,11:29","dtypep":"(I)", + {"type":"ASSIGNW","addr":"(T)","loc":"d,11:24,11:29","dtypep":"(K)", "rhsp": [ - {"type":"VARREF","name":"i_clk","addr":"(S)","loc":"d,11:24,11:29","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"(N)"} + {"type":"VARREF","name":"i_clk","addr":"(U)","loc":"d,11:24,11:29","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"(N)"} ], "lhsp": [ - {"type":"VARREF","name":"top.i_clk","addr":"(T)","loc":"d,11:24,11:29","dtypep":"(I)","access":"WR","varp":"(K)","varScopep":"(O)"} + {"type":"VARREF","name":"top.i_clk","addr":"(V)","loc":"d,11:24,11:29","dtypep":"(K)","access":"WR","varp":"(P)","varScopep":"(O)"} ]} ]}, - {"type":"ALWAYS","addr":"(U)","loc":"d,7:24,7:29","keyword":"cont_assign", + {"type":"ALWAYS","addr":"(W)","loc":"d,7:24,7:29","keyword":"cont_assign", "stmtsp": [ - {"type":"ASSIGNW","addr":"(V)","loc":"d,7:24,7:29","dtypep":"(I)", + {"type":"ASSIGNW","addr":"(X)","loc":"d,7:24,7:29","dtypep":"(K)", "rhsp": [ - {"type":"VARREF","name":"i_clk","addr":"(W)","loc":"d,7:24,7:29","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"(N)"} + {"type":"VARREF","name":"i_clk","addr":"(Y)","loc":"d,7:24,7:29","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"(N)"} ], "lhsp": [ - {"type":"VARREF","name":"top.f.i_clk","addr":"(X)","loc":"d,7:24,7:29","dtypep":"(I)","access":"WR","varp":"(L)","varScopep":"(P)"} + {"type":"VARREF","name":"top.f.i_clk","addr":"(Z)","loc":"d,7:24,7:29","dtypep":"(K)","access":"WR","varp":"(R)","varScopep":"(Q)"} ]} ]} ]} - ]} + ]}, + {"type":"VAR","name":"top.i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(K)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"top.f.i_clk","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(K)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"} ]}, {"type":"PACKAGE","name":"$unit","addr":"(E)","loc":"a,0:0,0:0","origName":"__024unit","verilogName":"\\$unit ","level":3,"depth":3,"inLibrary":true,"unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"1ps"} ], "miscsp": [ {"type":"TYPETABLE","addr":"(C)","loc":"a,0:0,0:0", "typesp": [ - {"type":"BASICDTYPE","name":"logic","addr":"(I)","loc":"d,11:18,11:23","dtypep":"(I)","keyword":"logic","generic":true} + {"type":"BASICDTYPE","name":"logic","addr":"(K)","loc":"d,11:18,11:23","dtypep":"(K)","keyword":"logic","generic":true} ]}, {"type":"CONSTPOOL","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(Y)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"NONE", + {"type":"MODULE","name":"@CONST-POOL@","addr":"(AB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"NONE", "stmtsp": [ - {"type":"SCOPE","name":"@CONST-POOL@","addr":"(Z)","loc":"a,0:0,0:0","modp":"(Y)"} + {"type":"SCOPE","name":"@CONST-POOL@","addr":"(BB)","loc":"a,0:0,0:0","modp":"(AB)"} ]} ]} ]} diff --git a/test_regress/t/t_json_only_flat_pub_mod.out b/test_regress/t/t_json_only_flat_pub_mod.out index acceb4982..c1184f579 100644 --- a/test_regress/t/t_json_only_flat_pub_mod.out +++ b/test_regress/t/t_json_only_flat_pub_mod.out @@ -1,55 +1,59 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","resolvedTopModuleName":"top","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","topScopep":"(F)", "modulesp": [ {"type":"MODULE","name":"$root","addr":"(G)","loc":"d,11:8,11:11","origName":"$root","verilogName":"$root","level":1,"depth":1,"modPublic":true,"unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"1ps", + "inlinesp": [ + {"type":"CELLINLINE","name":"top.f","addr":"(H)","loc":"d,12:7,12:8","origModName":"foo"}, + {"type":"CELLINLINE","name":"top","addr":"(I)","loc":"d,11:8,11:11","origModName":"top"} + ], "stmtsp": [ - {"type":"VAR","name":"i_clk","addr":"(H)","loc":"d,11:24,11:29","dtypep":"(I)","origName":"i_clk","verilogName":"i_clk","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"CELL","name":"$unit","addr":"(J)","loc":"a,0:0,0:0","modName":"__024unit","origName":"__024unit","verilogName":"\\$unit ","modp":"(E)"}, - {"type":"VAR","name":"top.i_clk","addr":"(K)","loc":"d,11:24,11:29","dtypep":"(I)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"top.f.i_clk","addr":"(L)","loc":"d,7:24,7:29","dtypep":"(I)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"i_clk","addr":"(J)","loc":"d,11:24,11:29","dtypep":"(K)","origName":"i_clk","verilogName":"i_clk","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"CELL","name":"$unit","addr":"(L)","loc":"a,0:0,0:0","modName":"__024unit","origName":"__024unit","verilogName":"\\$unit ","modp":"(E)"}, {"type":"TOPSCOPE","addr":"(F)","loc":"d,11:8,11:11", "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(M)","loc":"d,11:8,11:11","modp":"(G)", "varsp": [ - {"type":"VARSCOPE","name":"i_clk","addr":"(N)","loc":"d,11:24,11:29","dtypep":"(I)","isTrace":true,"scopep":"(M)","varp":"(H)"}, - {"type":"VARSCOPE","name":"top.i_clk","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(I)","isTrace":true,"scopep":"(M)","varp":"(K)"}, - {"type":"VARSCOPE","name":"top.f.i_clk","addr":"(P)","loc":"d,7:24,7:29","dtypep":"(I)","isTrace":true,"scopep":"(M)","varp":"(L)"} + {"type":"VARSCOPE","name":"i_clk","addr":"(N)","loc":"d,11:24,11:29","dtypep":"(K)","isTrace":true,"scopep":"(M)","varp":"(J)"}, + {"type":"VARSCOPE","name":"top.i_clk","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(K)","isTrace":true,"scopep":"(M)","varp":"(P)"}, + {"type":"VARSCOPE","name":"top.f.i_clk","addr":"(Q)","loc":"d,7:24,7:29","dtypep":"(K)","scopep":"(M)","varp":"(R)"} ], "blocksp": [ - {"type":"ALWAYS","addr":"(Q)","loc":"d,11:24,11:29","keyword":"cont_assign", + {"type":"ALWAYS","addr":"(S)","loc":"d,11:24,11:29","keyword":"cont_assign", "stmtsp": [ - {"type":"ASSIGNW","addr":"(R)","loc":"d,11:24,11:29","dtypep":"(I)", + {"type":"ASSIGNW","addr":"(T)","loc":"d,11:24,11:29","dtypep":"(K)", "rhsp": [ - {"type":"VARREF","name":"i_clk","addr":"(S)","loc":"d,11:24,11:29","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"(N)"} + {"type":"VARREF","name":"i_clk","addr":"(U)","loc":"d,11:24,11:29","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"(N)"} ], "lhsp": [ - {"type":"VARREF","name":"top.i_clk","addr":"(T)","loc":"d,11:24,11:29","dtypep":"(I)","access":"WR","varp":"(K)","varScopep":"(O)"} + {"type":"VARREF","name":"top.i_clk","addr":"(V)","loc":"d,11:24,11:29","dtypep":"(K)","access":"WR","varp":"(P)","varScopep":"(O)"} ]} ]}, - {"type":"ALWAYS","addr":"(U)","loc":"d,7:24,7:29","keyword":"cont_assign", + {"type":"ALWAYS","addr":"(W)","loc":"d,7:24,7:29","keyword":"cont_assign", "stmtsp": [ - {"type":"ASSIGNW","addr":"(V)","loc":"d,7:24,7:29","dtypep":"(I)", + {"type":"ASSIGNW","addr":"(X)","loc":"d,7:24,7:29","dtypep":"(K)", "rhsp": [ - {"type":"VARREF","name":"i_clk","addr":"(W)","loc":"d,7:24,7:29","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"(N)"} + {"type":"VARREF","name":"i_clk","addr":"(Y)","loc":"d,7:24,7:29","dtypep":"(K)","access":"RD","varp":"(J)","varScopep":"(N)"} ], "lhsp": [ - {"type":"VARREF","name":"top.f.i_clk","addr":"(X)","loc":"d,7:24,7:29","dtypep":"(I)","access":"WR","varp":"(L)","varScopep":"(P)"} + {"type":"VARREF","name":"top.f.i_clk","addr":"(Z)","loc":"d,7:24,7:29","dtypep":"(K)","access":"WR","varp":"(R)","varScopep":"(Q)"} ]} ]} ]} - ]} + ]}, + {"type":"VAR","name":"top.i_clk","addr":"(P)","loc":"d,11:24,11:29","dtypep":"(K)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"top.f.i_clk","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(K)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"} ]}, {"type":"PACKAGE","name":"$unit","addr":"(E)","loc":"a,0:0,0:0","origName":"__024unit","verilogName":"\\$unit ","level":3,"depth":3,"inLibrary":true,"unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"1ps"} ], "miscsp": [ {"type":"TYPETABLE","addr":"(C)","loc":"a,0:0,0:0", "typesp": [ - {"type":"BASICDTYPE","name":"logic","addr":"(I)","loc":"d,11:18,11:23","dtypep":"(I)","keyword":"logic","generic":true} + {"type":"BASICDTYPE","name":"logic","addr":"(K)","loc":"d,11:18,11:23","dtypep":"(K)","keyword":"logic","generic":true} ]}, {"type":"CONSTPOOL","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(Y)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"NONE", + {"type":"MODULE","name":"@CONST-POOL@","addr":"(AB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"NONE", "stmtsp": [ - {"type":"SCOPE","name":"@CONST-POOL@","addr":"(Z)","loc":"a,0:0,0:0","modp":"(Y)"} + {"type":"SCOPE","name":"@CONST-POOL@","addr":"(BB)","loc":"a,0:0,0:0","modp":"(AB)"} ]} ]} ]} diff --git a/test_regress/t/t_json_only_flat_vlvbound.out b/test_regress/t/t_json_only_flat_vlvbound.out index e4023ecba..adec2588e 100644 --- a/test_regress/t/t_json_only_flat_vlvbound.out +++ b/test_regress/t/t_json_only_flat_vlvbound.out @@ -1,357 +1,360 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","resolvedTopModuleName":"vlvbound_test","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","topScopep":"(F)", "modulesp": [ {"type":"MODULE","name":"$root","addr":"(G)","loc":"d,7:8,7:21","origName":"$root","verilogName":"$root","level":1,"depth":1,"modPublic":true,"unconnectedDrive":"DEFAULT_FALSE","lifetime":"NONE","timeunit":"1ps", + "inlinesp": [ + {"type":"CELLINLINE","name":"vlvbound_test","addr":"(H)","loc":"d,7:8,7:21","origModName":"vlvbound_test"} + ], "stmtsp": [ - {"type":"VAR","name":"i_a","addr":"(H)","loc":"d,8:24,8:27","dtypep":"(I)","origName":"i_a","verilogName":"i_a","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"i_b","addr":"(J)","loc":"d,9:24,9:27","dtypep":"(I)","origName":"i_b","verilogName":"i_b","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"o_a","addr":"(K)","loc":"d,10:24,10:27","dtypep":"(L)","origName":"o_a","verilogName":"o_a","isPrimaryIO":true,"direction":"OUTPUT","declDirection":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"o_b","addr":"(M)","loc":"d,11:24,11:27","dtypep":"(L)","origName":"o_b","verilogName":"o_b","isPrimaryIO":true,"direction":"OUTPUT","declDirection":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"CELL","name":"$unit","addr":"(N)","loc":"a,0:0,0:0","modName":"__024unit","origName":"__024unit","verilogName":"\\$unit ","modp":"(E)"}, - {"type":"VAR","name":"vlvbound_test.i_a","addr":"(O)","loc":"d,8:24,8:27","dtypep":"(I)","origName":"i_a","verilogName":"i_a","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"vlvbound_test.i_b","addr":"(P)","loc":"d,9:24,9:27","dtypep":"(I)","origName":"i_b","verilogName":"i_b","direction":"NONE","declDirection":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"vlvbound_test.o_a","addr":"(Q)","loc":"d,10:24,10:27","dtypep":"(L)","origName":"o_a","verilogName":"o_a","direction":"NONE","declDirection":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, - {"type":"VAR","name":"vlvbound_test.o_b","addr":"(R)","loc":"d,11:24,11:27","dtypep":"(L)","origName":"o_b","verilogName":"o_b","direction":"NONE","declDirection":"OUTPUT","icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"i_a","addr":"(I)","loc":"d,8:24,8:27","dtypep":"(J)","origName":"i_a","verilogName":"i_a","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"i_b","addr":"(K)","loc":"d,9:24,9:27","dtypep":"(J)","origName":"i_b","verilogName":"i_b","isPrimaryIO":true,"direction":"INPUT","declDirection":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"o_a","addr":"(L)","loc":"d,10:24,10:27","dtypep":"(M)","origName":"o_a","verilogName":"o_a","isPrimaryIO":true,"direction":"OUTPUT","declDirection":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"VAR","name":"o_b","addr":"(N)","loc":"d,11:24,11:27","dtypep":"(M)","origName":"o_b","verilogName":"o_b","isPrimaryIO":true,"direction":"OUTPUT","declDirection":"OUTPUT","isSigPublic":true,"icoMaybeWritten":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic"}, + {"type":"CELL","name":"$unit","addr":"(O)","loc":"a,0:0,0:0","modName":"__024unit","origName":"__024unit","verilogName":"\\$unit ","modp":"(E)"}, {"type":"TOPSCOPE","addr":"(F)","loc":"d,7:8,7:21", "scopep": [ - {"type":"SCOPE","name":"TOP","addr":"(S)","loc":"d,7:8,7:21","modp":"(G)", + {"type":"SCOPE","name":"TOP","addr":"(P)","loc":"d,7:8,7:21","modp":"(G)", "varsp": [ - {"type":"VARSCOPE","name":"i_a","addr":"(T)","loc":"d,8:24,8:27","dtypep":"(I)","isTrace":true,"scopep":"(S)","varp":"(H)"}, - {"type":"VARSCOPE","name":"i_b","addr":"(U)","loc":"d,9:24,9:27","dtypep":"(I)","isTrace":true,"scopep":"(S)","varp":"(J)"}, - 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{"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__Vfuncout","addr":"(LB)","loc":"d,14:34,14:37","dtypep":"(M)","isTrace":true,"scopep":"(P)","varp":"(MB)"}, + {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__val","addr":"(NB)","loc":"d,14:57,14:60","dtypep":"(J)","isTrace":true,"scopep":"(P)","varp":"(OB)"}, + {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__ret","addr":"(PB)","loc":"d,15:17,15:20","dtypep":"(M)","isTrace":true,"scopep":"(P)","varp":"(QB)"}, + {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(RB)","loc":"d,16:13,16:14","dtypep":"(JB)","isTrace":true,"scopep":"(P)","varp":"(SB)"} ], "blocksp": [ - {"type":"ALWAYS","addr":"(SB)","loc":"d,23:14,23:15","keyword":"cont_assign", + {"type":"ALWAYS","addr":"(TB)","loc":"d,23:14,23:15","keyword":"cont_assign", "stmtsp": [ - {"type":"COMMENT","name":"Function: foo","addr":"(TB)","loc":"d,23:16,23:19","showAt":true}, - {"type":"ASSIGN","addr":"(UB)","loc":"d,23:20,23:23","dtypep":"(I)", + {"type":"COMMENT","name":"Function: foo","addr":"(UB)","loc":"d,23:16,23:19","showAt":true}, + {"type":"ASSIGN","addr":"(VB)","loc":"d,23:20,23:23","dtypep":"(J)", "rhsp": [ - {"type":"VARREF","name":"i_a","addr":"(VB)","loc":"d,23:20,23:23","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"(T)"} + {"type":"VARREF","name":"i_a","addr":"(WB)","loc":"d,23:20,23:23","dtypep":"(J)","access":"RD","varp":"(I)","varScopep":"(Q)"} ], "lhsp": [ - {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(WB)","loc":"d,14:57,14:60","dtypep":"(I)","access":"WR","varp":"(EB)","varScopep":"(DB)"} + {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__val","addr":"(XB)","loc":"d,14:57,14:60","dtypep":"(J)","access":"WR","varp":"(FB)","varScopep":"(EB)"} ]}, - {"type":"ASSIGN","addr":"(XB)","loc":"d,14:34,14:37","dtypep":"(L)", + {"type":"ASSIGN","addr":"(YB)","loc":"d,14:34,14:37","dtypep":"(M)", "rhsp": [ - {"type":"CRESET","addr":"(YB)","loc":"d,14:34,14:37","dtypep":"(L)"} + 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{"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__ret","addr":"(DC)","loc":"d,15:17,15:20","dtypep":"(M)","access":"WR","varp":"(HB)","varScopep":"(GB)"} ]}, - {"type":"ASSIGN","addr":"(DC)","loc":"d,16:13,16:14","dtypep":"(IB)", + {"type":"ASSIGN","addr":"(EC)","loc":"d,16:13,16:14","dtypep":"(JB)", "rhsp": [ - {"type":"CRESET","addr":"(EC)","loc":"d,16:13,16:14","dtypep":"(IB)"} + {"type":"CRESET","addr":"(FC)","loc":"d,16:13,16:14","dtypep":"(JB)"} ], "lhsp": [ - {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(FC)","loc":"d,16:13,16:14","dtypep":"(IB)","access":"WR","varp":"(JB)","varScopep":"(HB)"} + {"type":"VARREF","name":"__Vfunc_vlvbound_test.foo__0__i","addr":"(GC)","loc":"d,16:13,16:14","dtypep":"(JB)","access":"WR","varp":"(KB)","varScopep":"(IB)"} ]}, - {"type":"ASSIGN","addr":"(GC)","loc":"d,17:12,17:13","dtypep":"(IB)", + {"type":"ASSIGN","addr":"(HC)","loc":"d,17:12,17:13","dtypep":"(JB)", "rhsp": [ - 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Location of other write 40 | always_comb out6 = d; | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:14: Bit [0] of signal 't.out2' have multiple combinational drivers. This can cause performance degradation. - t/t_lint_always_comb_multidriven_bad.v:28:15: ... Location of offending driver - 28 | assign out2 = d; - | ^ - t/t_lint_always_comb_multidriven_bad.v:29:20: ... Location of offending driver - 29 | always_comb out2 = 1'b0; +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:14: Bit [0] of signal 't.out6' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:40:20: ... Location of offending driver + 40 | always_comb out6 = d; + | ^ + t/t_lint_always_comb_multidriven_bad.v:41:20: ... Location of offending driver + 41 | always_comb out6 = 1'b0; + | ^ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:14: Bit [0] of signal 't.out5' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:37:20: ... Location of offending driver + 37 | always_comb out5 = 1'b0; + | ^ + t/t_lint_always_comb_multidriven_bad.v:38:20: ... Location of offending driver + 38 | always_comb out5 = d; | ^ %Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:14: Bit [0] of signal 't.out4' have multiple combinational drivers. This can cause performance degradation. t/t_lint_always_comb_multidriven_bad.v:34:20: ... Location of offending driver @@ -62,18 +69,11 @@ t/t_lint_always_comb_multidriven_bad.v:35:15: ... Location of offending driver 35 | assign out4 = d; | ^ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:14: Bit [0] of signal 't.out5' have multiple combinational drivers. This can cause performance degradation. - t/t_lint_always_comb_multidriven_bad.v:37:20: ... Location of offending driver - 37 | always_comb out5 = 1'b0; - | ^ - t/t_lint_always_comb_multidriven_bad.v:38:20: ... Location of offending driver - 38 | always_comb out5 = d; - | ^ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:14: Bit [0] of signal 't.out6' have multiple combinational drivers. This can cause performance degradation. - t/t_lint_always_comb_multidriven_bad.v:40:20: ... Location of offending driver - 40 | always_comb out6 = d; - | ^ - t/t_lint_always_comb_multidriven_bad.v:41:20: ... Location of offending driver - 41 | always_comb out6 = 1'b0; +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:14: Bit [0] of signal 't.out2' have multiple combinational drivers. This can cause performance degradation. + t/t_lint_always_comb_multidriven_bad.v:28:15: ... Location of offending driver + 28 | assign out2 = d; + | ^ + t/t_lint_always_comb_multidriven_bad.v:29:20: ... Location of offending driver + 29 | always_comb out2 = 1'b0; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_subout_bad.out b/test_regress/t/t_lint_subout_bad.out index 1fec4d7f0..3d5bfab52 100644 --- a/test_regress/t/t_lint_subout_bad.out +++ b/test_regress/t/t_lint_subout_bad.out @@ -1,14 +1,14 @@ -%Error-PORTSHORT: t/t_lint_subout_bad.v:12:14: Output port is connected to a constant pin, electrical short - : ... note: In instance 't' - 12 | sub sub1 (.out({32'b0, sig})); - | ^~~ - ... For error description see https://verilator.org/warn/PORTSHORT?v=latest -%Error-PORTSHORT: t/t_lint_subout_bad.v:13:14: Output port is connected to a constant pin, electrical short - : ... note: In instance 't' - 13 | sub sub2 (.out({32'b1, sig})); - | ^~~ %Error-PORTSHORT: t/t_lint_subout_bad.v:11:14: Output port is connected to a constant pin, electrical short : ... note: In instance 't' 11 | sub sub0 (.out(33'b0)); + | ^~~ + ... For error description see https://verilator.org/warn/PORTSHORT?v=latest +%Error-PORTSHORT: t/t_lint_subout_bad.v:12:14: Output port is connected to a constant pin, electrical short + : ... note: In instance 't' + 12 | sub sub1 (.out({32'b0, sig})); + | ^~~ +%Error-PORTSHORT: t/t_lint_subout_bad.v:13:14: Output port is connected to a constant pin, electrical short + : ... note: In instance 't' + 13 | sub sub2 (.out({32'b1, sig})); | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize_method_with_bad.out b/test_regress/t/t_randomize_method_with_bad.out index b0dc8912b..7c60a2d97 100644 --- a/test_regress/t/t_randomize_method_with_bad.out +++ b/test_regress/t/t_randomize_method_with_bad.out @@ -1,4 +1,5 @@ %Error: t/t_randomize_method_with_bad.v:18:52: Can't find definition of task/function: 'in_mod_function' + : ... note: In instance '$unit.Foo' 18 | automatic int res = foo.randomize() with { v < in_mod_function(); }; | ^~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. diff --git a/test_regress/t/t_vlcov_hier_report_runtime.out b/test_regress/t/t_vlcov_hier_report_runtime.out index 7f5a47177..169975f7d 100644 --- a/test_regress/t/t_vlcov_hier_report_runtime.out +++ b/test_regress/t/t_vlcov_hier_report_runtime.out @@ -43,9 +43,6 @@ Hierarchy Coverage Summary: fsm_state : 100.0% ( 6/ 6) fsm_arc : 85.7% ( 6/ 7) Design Unit Coverage Summary: - $root - fsm_state : 91.7% (11/12) - fsm_arc : 71.4% (10/14) cluster line : 100.0% ( 3/ 3) toggle : 68.2% (15/22) @@ -60,6 +57,8 @@ Design Unit Coverage Summary: line : 75.0% (18/24) toggle : 91.7% (44/48) branch : 75.0% (12/16) + fsm_state : 91.7% (11/12) + fsm_arc : 71.4% (10/14) tb line : 100.0% (5/5) toggle : 100.0% (4/4)