diff --git a/.bake.toml b/.bake.toml index 414bc7b5e..04f57d3d2 100644 --- a/.bake.toml +++ b/.bake.toml @@ -1,4 +1,6 @@ -# mbake configuration file +# DESCRIPTION: mbake configuration file +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: CC0-1.0 [formatter] # Indentation settings diff --git a/.clang-tidy b/.clang-tidy index c15dd3e2b..be6fec5d6 100644 --- a/.clang-tidy +++ b/.clang-tidy @@ -1,4 +1,4 @@ -Checks: '*,-hicpp*,-android-cloexec-fopen,-cert-dcl50-cpp,-cert-env33-c,-cert-err34-c,-cert-err58-cpp,-clang-analyzer-core.UndefinedBinaryOperatorResult,-clang-analyzer-security*,-cppcoreguidelines-avoid-magic-numbers,-cppcoreguidelines-no-malloc,-cppcoreguidelines-owning-memory,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-constant-array-index,-cppcoreguidelines-pro-bounds-pointer-arithmetic,-cppcoreguidelines-pro-type-const-cast,-cppcoreguidelines-pro-type-reinterpret-cast,-cppcoreguidelines-pro-type-static-cast-downcast,-cppcoreguidelines-pro-type-union-access,-cppcoreguidelines-pro-type-vararg,-cppcoreguidelines-special-member-functions,-fuchsia-*,-google-default-arguments,-google-readability-todo,-google-runtime-references,-llvm-header-guard,-llvm-include-order,-misc-string-integer-assignment,-misc-string-literal-with-embedded-nul,-modernize-use-auto,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-container-size-empty,-readability-delete-null-pointer,-readability-else-after-return,-readability-implicit-bool-conversion,-readability-named-parameter,-readability-static-accessed-through-instance,-llvmlibc-*,-altera-*' +Checks: '*,-hicpp*,-android-cloexec-fopen,-cert-dcl50-cpp,-cert-env33-c,-cert-err34-c,-cert-err58-cpp,-clang-analyzer-core.UndefinedBinaryOperatorResult,-clang-analyzer-security*,-cppcoreguidelines-avoid-magic-numbers,-cppcoreguidelines-no-malloc,-cppcoreguidelines-owning-memory,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-array-to-pointer-decay,-cppcoreguidelines-pro-bounds-constant-array-index,-cppcoreguidelines-pro-bounds-pointer-arithmetic,-cppcoreguidelines-pro-type-const-cast,-cppcoreguidelines-pro-type-reinterpret-cast,-cppcoreguidelines-pro-type-static-cast-downcast,-cppcoreguidelines-pro-type-union-access,-cppcoreguidelines-pro-type-vararg,-cppcoreguidelines-special-member-functions,-fuchsia-*,-google-default-arguments,-google-readability-todo,-google-runtime-references,-llvm-header-guard,-llvm-include-order,-misc-string-integer-assignment,-misc-string-literal-with-embedded-nul,-modernize-use-auto,-modernize-use-trailing-return-type,-readability-braces-around-statements,-readability-container-size-empty,-readability-delete-null-pointer,-readability-else-after-return,-readability-implicit-bool-conversion,-readability-named-parameter,-readability-static-accessed-through-instance,-llvmlibc-*,-altera-*,-boost-use-ranges' WarningsAsErrors: '' HeaderFilterRegex: '' FormatStyle: none diff --git a/.codecov.yml b/.codecov.yml index 75dc35efe..6ea5b4f2f 100644 --- a/.codecov.yml +++ b/.codecov.yml @@ -1,10 +1,10 @@ --- # DESCRIPTION: codecov.io config # -# Copyright 2020-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2020-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #################### # Validate: diff --git a/.github/dependabot.yml b/.github/dependabot.yml index 4aa3cdc33..cafae9a81 100644 --- a/.github/dependabot.yml +++ b/.github/dependabot.yml @@ -6,3 +6,6 @@ updates: directory: "/" schedule: interval: "weekly" + groups: + everything: + patterns: ["*"] diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index f25f1c944..148c7980c 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -110,6 +110,7 @@ jobs: run: | echo 'set man-db/auto-update false' | sudo debconf-communicate >/dev/null sudo dpkg-reconfigure man-db + sudo apt install lcov || \ sudo apt install lcov - name: Download repository archive diff --git a/.github/workflows/format.yml b/.github/workflows/format.yml index f1940067d..e027c7a04 100644 --- a/.github/workflows/format.yml +++ b/.github/workflows/format.yml @@ -28,6 +28,7 @@ jobs: env: CI_BUILD_STAGE_NAME: build run: | + sudo apt install clang-format-18 || \ sudo apt install clang-format-18 git config --global user.email "action@example.com" git config --global user.name "github action" diff --git a/.github/workflows/reusable-lint-py.yml b/.github/workflows/reusable-lint-py.yml index 53fbcf256..f4ad9b6e8 100644 --- a/.github/workflows/reusable-lint-py.yml +++ b/.github/workflows/reusable-lint-py.yml @@ -41,6 +41,7 @@ jobs: - name: Install python dependencies run: | + sudo apt install python3-clang || \ sudo apt install python3-clang make venv diff --git a/.github/workflows/reusable-rtlmeter-build.yml b/.github/workflows/reusable-rtlmeter-build.yml index 1e2bd33db..068729a0d 100644 --- a/.github/workflows/reusable-rtlmeter-build.yml +++ b/.github/workflows/reusable-rtlmeter-build.yml @@ -34,7 +34,9 @@ jobs: echo "path-exclude /usr/share/doc/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/man/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/info/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc + sudo apt update || \ sudo apt update + sudo apt install ccache mold help2man libfl-dev libgoogle-perftools-dev libsystemc-dev || \ sudo apt install ccache mold help2man libfl-dev libgoogle-perftools-dev libsystemc-dev - name: Use saved ccache diff --git a/.github/workflows/reusable-rtlmeter-run.yml b/.github/workflows/reusable-rtlmeter-run.yml index 96bf409fb..95525125f 100644 --- a/.github/workflows/reusable-rtlmeter-run.yml +++ b/.github/workflows/reusable-rtlmeter-run.yml @@ -58,7 +58,9 @@ jobs: echo "path-exclude /usr/share/doc/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/man/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc echo "path-exclude /usr/share/info/*" | sudo tee -a /etc/dpkg/dpkg.cfg.d/01_nodoc + sudo apt update || \ sudo apt update + sudo apt install ccache mold libfl-dev libgoogle-perftools-dev libsystemc-dev || \ sudo apt install ccache mold libfl-dev libgoogle-perftools-dev libsystemc-dev - name: Download Verilator installation archive diff --git a/Artistic b/Artistic deleted file mode 100644 index af71a1f91..000000000 --- a/Artistic +++ /dev/null @@ -1,197 +0,0 @@ -Artistic License 2.0 - -Copyright (c) 2000-2006, The Perl Foundation. - -Everyone is permitted to copy and distribute verbatim copies of this -license document, but changing it is not allowed. - -Preamble -******** - -This license establishes the terms under which a given free software -Package may be copied, modified, distributed, and/or redistributed. The -intent is that the Copyright Holder maintains some artistic control over -the development of that Package while still keeping the Package -available as open source and free software. - -You are always permitted to make arrangements wholly outside of this -license directly with the Copyright Holder of a given Package. If the -terms of this license do not permit the full use that you propose to -make of the Package, you should contact the Copyright Holder and seek a -different licensing arrangement. - -Definitions -*********** - -"Copyright Holder" means the individual(s) or organization(s) named in -the copyright notice for the entire Package. - -"Contributor" means any party that has contributed code or other -material to the Package, in accordance with the Copyright Holder's -procedures. - -"You" and "your" means any person who would like to copy, distribute, or -modify the Package. - -"Package" means the collection of files distributed by the Copyright -Holder, and derivatives of that collection and/or of those files. A -given Package may consist of either the Standard Version, or a Modified -Version. - -"Distribute" means providing a copy of the Package or making it -accessible to anyone else, or in the case of a company or organization, -to others outside of your company or organization. - -"Distributor Fee" means any fee that you charge for Distributing this -Package or providing support for this Package to another party. It does -not mean licensing fees. - -"Standard Version" refers to the Package if it has not been modified, or -has been modified only in ways explicitly requested by the Copyright -Holder. - -"Modified Version" means the Package, if it has been changed, and such -changes were not explicitly requested by the Copyright Holder. - -"Original License" means this Artistic License as Distributed with the -Standard Version of the Package, in its current version or as it may be -modified by The Perl Foundation in the future. - -"Source" form means the source code, documentation source, and -configuration files for the Package. - -"Compiled" form means the compiled bytecode, object code, binary, or any -other form resulting from mechanical transformation or translation of -the Source form. - -Permission for Use and Modification Without Distribution -******************************************************** - -(1) You are permitted to use the Standard Version and create and use -Modified Versions for any purpose without restriction, provided that you -do not Distribute the Modified Version. - -Permissions for Redistribution of the Standard Version -****************************************************** - -(2) You may Distribute verbatim copies of the Source form of the -Standard Version of this Package in any medium without restriction, -either gratis or for a Distributor Fee, provided that you duplicate all -of the original copyright notices and associated disclaimers. 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In addition, the -Modified Version must bear a name that is different from the name of the -Standard Version. - -(c) allow anyone who receives a copy of the Modified Version to make the -Source form of the Modified Version available to others under - -(i) the Original License or - -(ii) a license that permits the licensee to freely copy, modify and -redistribute the Modified Version using the same licensing terms that -apply to the copy that the licensee received, and requires that the -Source form of the Modified Version, and of any works derived from it, -be made freely available in that license fees are prohibited but -Distributor Fees are allowed. - -Distribution of Compiled Forms of the Standard Version or Modified -****************************************************************** -Versions without the Source -*************************** - -(5) You may Distribute Compiled forms of the Standard Version without -the Source, provided that you include complete instructions on how to -get the Source of the Standard Version. Such instructions must be valid -at the time of your distribution. If these instructions, at any time -while you are carrying out such distribution, become invalid, you must -provide new instructions on demand or cease further distribution. If -you provide valid instructions or cease distribution within thirty days -after you become aware that the instructions are invalid, then you do -not forfeit any of your rights under this license. - -(6) You may Distribute a Modified Version in Compiled form without the -Source, provided that you comply with Section 4 with respect to the -Source of the Modified Version. - -Aggregating or Linking the Package -********************************** - -(7) You may aggregate the Package (either the Standard Version or -Modified Version) with other packages and Distribute the resulting -aggregation provided that you do not charge a licensing fee for the -Package. Distributor Fees are permitted, and licensing fees for other -components in the aggregation are permitted. The terms of this license -apply to the use and Distribution of the Standard or Modified Versions -as included in the aggregation. - -(8) You are permitted to link Modified and Standard Versions with other -works, to embed the Package in a larger work of your own, or to build -stand-alone binary or bytecode versions of applications that include the -Package, and Distribute the result without restriction, provided the -result does not expose a direct interface to the Package. - -Items That are Not Considered Part of a Modified Version -******************************************************** - -(9) Works (including, but not limited to, modules and scripts) that -merely extend or make use of the Package, do not, by themselves, cause -the Package to be a Modified Version. In addition, such works are not -considered parts of the Package itself, and are not subject to the terms -of this license. - -General Provisions -****************** - -(10) Any use, modification, and distribution of the Standard or Modified -Versions is governed by this Artistic License. By using, modifying or -distributing the Package, you accept this license. Do not use, modify, -or distribute the Package, if you do not accept this license. - -(11) If your Modified Version has been derived from a Modified Version -made by someone other than you, you are nevertheless required to ensure -that your Modified Version complies with the requirements of this -license. - -(12) This license does not grant you the right to use any trademark, -service mark, tradename, or logo of the Copyright Holder. - -(13) This license includes the non-exclusive, worldwide, free-of-charge -patent license to make, have made, use, offer to sell, sell, import and -otherwise transfer the Package with respect to any patent claims -licensable by the Copyright Holder that are necessarily infringed by the -Package. If you institute patent litigation (including a cross-claim or -counterclaim) against any party alleging that the Package constitutes -direct or contributory patent infringement, then this Artistic License -to you shall terminate on the date that such litigation is filed. - -(14) Disclaimer of Warranty: THE PACKAGE IS PROVIDED BY THE COPYRIGHT -HOLDER AND CONTRIBUTORS "AS IS' AND WITHOUT ANY EXPRESS OR IMPLIED -WARRANTIES. THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -PARTICULAR PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED TO THE EXTENT -PERMITTED BY YOUR LOCAL LAW. UNLESS REQUIRED BY LAW, NO COPYRIGHT -HOLDER OR CONTRIBUTOR WILL BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING IN ANY WAY OUT OF THE USE -OF THE PACKAGE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/CMakeLists.txt b/CMakeLists.txt index 3cf9b4b91..4c391b2ab 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,10 +4,10 @@ # #***************************************************************************** # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2003-2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ @@ -16,7 +16,7 @@ cmake_minimum_required(VERSION 3.15) cmake_policy(SET CMP0091 NEW) # Use MSVC_RUNTIME_LIBRARY to select the runtime project( Verilator - VERSION 5.044 + VERSION 5.046 HOMEPAGE_URL https://verilator.org LANGUAGES CXX ) diff --git a/Changes b/Changes index 95e6062c2..cdb3948ab 100644 --- a/Changes +++ b/Changes @@ -8,6 +8,133 @@ The changes in each Verilator version are described below. The contributors that suggested or implemented a given issue are shown in []. Thanks! +Verilator 5.046 2026-02-28 +========================== + +**Important:** + +* Support #0 delays with IEEE-1800 compliant semantics (#7079). [Geza Lore, Testorrent USA, Inc.] + This may require `-no-sched-zero-delay` to maintain performance vs. previous versions. + +**Other:** + +* Add IEEE 4-state type lint checks (#3645 partial) (#6895). [Jose Drowne] +* Add VERILATOR_NUMA_STRATEGY environment variable (#6826) (#6880). [Yangyu Chen] +* Add decoded Verilog name in JSON output (#6919) (#6995). [Oleh Maksymenko] +* Add parsing of solve-before inside foreach (#6934). [Pawel Kojma, Antmicro Ltd.] +* Add error when accessing a non-static class field from a static function (#6948). [Artur Bieniek, Antmicro Ltd.] +* Add VerilatedContext::useNumaAssign and set on threads() call (#6954). [Yangyu Chen] +* Add coverage type information to verilator_coverage annotation output (#7131) (#7133) (#7148). +* Add --max-replication option (#7139). [Todd Strader] +* Support modport expression syntax + nested (#2601) (#5581) (#7005). [Leela Pakanati] +* Support nested interface as port connection (#5066) (#6986). [Leela Pakanati] +* Support solve..before constraints (#5647) (#7123). [Yilou Wang] +* Support structure initial values (#6130). +* Support proper automatic/static initialization, and remove STATICVAR warning (#6405) (#7086). +* Support vpi_put/vpi_get forcing of signals (#5933) (#6704). [Christian Hecken] +* Support detailed failure info for constraint violations (#6617) (#6883). [Yilou Wang] +* Support `unique` constraints (on 1D static arrays) (#6810) (#6878). [Srinivasan Venkataramanan] +* Support complex expressions as std::randomize arguments (#6860). [Jakub Wasilewski, Antmicro Ltd.] +* Support dynamic array elements in std::randomize (#6896). [Ryszard Rozak, Antmicro Ltd.] +* Support unbounded '$' in inside range expressions (#6935) (#6938). [Wei-Lun Chiu] +* Support `extern module` as a forward-declaration that is ignored. +* Support `foreach` with nested dots (#6991). [Krzysztof Bieganski, Antmicro Ltd.] +* Support signed multiplication in constraints (#7008). [Pawel Kojma, Antmicro Ltd.] +* Support constraint_mode() on static constraints (#7027) (#7038). [Yilou Wang] +* Support some system functions in constraint blocks (#7028) (#7036). [Yilou Wang] +* Support std::randomize() for queue, dynamic array, and associative array variables (#7044). [Yilou Wang] +* Support inherited and nested pre/post_randomize callbacks (#7049) (#7053). [Yilou Wang] +* Support `$get_initial_random_seed` (#7056) (#7069). [Srinivasan Venkataramanan] +* Support unique constraint on explicit array element subsets (#7057) (#7064). [Yilou Wang] +* Support force assignments to unpacked structs (#7060). [Ryszard Rozak, Antmicro Ltd.] +* Support function calls with random arguments in constraints (#7061) (#7083). [Yilou Wang] +* Support power expressions with constant exponent in constraints (#7073). [Kamil Danecki] +* Support `disable iff` with sequences (#7090). [Ryszard Rozak, Antmicro Ltd.] +* Support `this` keyword inside inline randomize() with {} constraint blocks (#7102) (#7113). [Yilou Wang] +* Support constraint dynamic array reduction methods without 'with' clause (#7104) (#7108). [Yilou Wang] +* Remove deprecated `--xml-only`. +* Remove deprecated `--make cmake`. +* Change JSON dumps to not include booleans that are false (#6977). +* Change metacomment extra underscore error to BADVLTPRAGMA warning (#6968). [Geza Lore, Testorrent USA, Inc.] +* Change INITIALSTATIC to also report on processes, per IEEE (#7020). +* Change automatic variables to not be traced. +* Change type definition error to show type chain with source context (#7151). +* Optimize string temporaries to not be localized (#6969). [Geza Lore, Testorrent USA, Inc.] +* Optimize wide word shifts by multiple of word size (#6970). [Geza Lore, Testorrent USA, Inc.] +* Optimize concatenations that produce unused bits in DFG (#6971). [Geza Lore, Testorrent USA, Inc.] +* Optimize more wide operation temporaries with substitution (#6972). [Geza Lore, Testorrent USA, Inc.] +* Optimize right shifts as clean (#6981). [Geza Lore, Testorrent USA, Inc.] +* Optimize temporary insertion for concatenations in DFG (#7013). [Geza Lore, Testorrent USA, Inc.] +* Optimize removing redundant variables during DFG Peephole pass (#7076). [Geza Lore, Testorrent USA, Inc.] +* Optimize additional DFG peephole Shift and Concat patterns (#7077). [Geza Lore, Testorrent USA, Inc.] +* Optimize logic and variable removal early in DFG (#7081). [Geza Lore, Testorrent USA, Inc.] +* Optimize straight line code in DFG always (#7084). [Geza Lore, Testorrent USA, Inc.] +* Optimize always blocks using local temporary variables in DFG (#7085). [Geza Lore, Testorrent USA, Inc.] +* Optimize functions inlined from packages in DFG (#7091). [Geza Lore, Testorrent USA, Inc.] +* Optimize continuous assignments with function on RHS in DFG (#7096). [Geza Lore, Testorrent USA, Inc.] +* Fix MULTIDRIVEN with task and default driver (#4045) (#6858). [em2machine] +* Fix parameterized virtual interface references that have no model references (#4286). +* Fix hierarchical interface/modport issues (#5941) (#6997). [Leela Pakanati] +* Fix extending class by a typedef (#6679) (#6855). [Alex Zhou] +* Fix variable reference lookup for module-level variables (#6741) (#6882). [Yilou Wang] +* Fix false CASEOVERLAP case item expression lint (#6825) (#6886). [Luca Colagrande] +* Fix virtual interface triggers (#6844). [Igor Zaworski, Antmicro Ltd.] +* Fix use-after-free error (#6846). [Matthew Ballance] +* Fix dynamic scheduler temporary variable locations (#6859) (#6926). [Igor Zaworski, Antmicro Ltd.] +* Fix dynamic array elements passed to ref argument (#6877). [Ryszard Rozak, Antmicro Ltd.] +* Fix large debug_str for emitted Syms headers (#6889). [Bartłomiej Chmiel, Antmicro Ltd.] +* Fix `disable iff` in simple properties (#6890). [Ryszard Rozak, Antmicro Ltd.] +* Fix #0 delays to control fork scheduling (#6891). [Artur Bieniek, Antmicro Ltd.] +* Fix member-selected randomization assignments (#6892). [Yilou Wang] +* Fix WIDTHEXTEND suppression on add/sub with single-bit signal. [Dan Katz] +* Fix segfault in V3Slice (#6899). [Pawel Kojma, Antmicro Ltd.] +* Fix unpacked array concatenation function arguments (#6900). [Pawel Kojma, Antmicro Ltd.] +* Fix signedness of packed array (#6901) (#6902). [Yutetsu TAKATSUKASA] +* Fix assignment of queue from unpacked array (#6906). +* Fix `foreach` with mid-index empty commas (#6910). +* Fix internal error when fork under always expression (#6911). +* Fix error when calling non-static method (#6916). [Artur Bieniek, Antmicro Ltd.] +* Fix memory leak in vpi_put_value and vpi_get_value (#6917). [Christian Hecken] +* Fix interface internal type reference (#6920) (#6966). [Todd Strader] +* Fix segfault after assignment pattern XOR error (#6928) (#6931). [emmettifelts] +* Fix delayed initial assignment (#6929). [Todd Strader] +* Fix event triggering (#6932) (#7072) (#7101). [Igor Zaworski, Antmicro Ltd.] +* Fix `--top-module` with underscores (#6940). [Christopher Batten] +* Fix variable randomization to better differ by seed (#6945) (#6956). [Rodrigo Batista de Moraes] +* Fix null pointer dereference in class member trigger expressions (#6946). [Cameron Waite] +* Fix type assignments for arrays of parameter types (#6955). [Todd Strader] +* Fix accessing non-rand struct member in constraints (#6960). [Pawel Kojma, Antmicro Ltd.] +* Fix associative array of events causes C++ compile error (#6962). +* Fix UNUSED / UNDRIVEN for unused functions (#6967). [Todd Strader] +* Fix non-inlined function return value clearing (#6982). +* Fix parameterized class typedef as interface type parameter (#6983) (#6984). [Leela Pakanati] +* Fix virtual interface not found internal error (#7010). [Igor Zaworski, Antmicro Ltd.] +* Fix multidimensional dynamic array elements passed to ref argument (#7023). [Ryszard Rozak, Antmicro Ltd.] +* Fix randomize() null pointer dereference (#7026). [Artur Bieniek, Antmicro Ltd.] +* Fix randc cyclic behavior broken with constraints (#7029) (#7035). [Yilou Wang] +* Fix inline foreach constraints on dynamic arrays of class objects (#7030) (#7037). [Yilou Wang] +* Fix rand_mode() on nested object variables causing Z3 solver error (#7031) (#7034). [Yilou Wang] +* Fix non-member identifiers used inside constraints (#7033). [Pawel Kojma, Antmicro Ltd.] +* Fix tracing without module inlining to match with inlining (#7041). [Geza Lore, Testorrent USA, Inc.] +* Fix scope tree in traces in hierarchical mode (#7042). [Geza Lore, Testorrent USA, Inc.] +* Fix rand_mode()/constraint_mode() when used as function arguments (#7051) (#7055). [Yilou Wang] +* Fix constraint_mode()/rand_mode() in constructor being overwritten (#7054). [Yilou Wang] +* Fix enum variables in constraint solver producing invalid enum values (#7058) (#7065). [Yilou Wang] +* Fix randomize() on null object handle crashing instead of returning 0 (#7059) (#7066). [Yilou Wang] +* Fix inside operator crash with impure expression and unsized range literals (#7063) (#7067). [Yilou Wang] +* Fix constant propagating DPI-written variables (#7074). [Geza Lore, Testorrent USA, Inc.] +* Fix conditional expressions in constraints (#7087). [Ryszard Rozak, Antmicro Ltd.] +* Fix UNSUPPORTED on $sampled in sensitivity list (#7093). [Ryszard Rozak, Antmicro Ltd.] +* Fix time to not advance after `$finish` (#7095). +* Fix associative array size() constraint generating invalid resize() call (#7103) (#7112). [Yilou Wang] +* Fix `new` shallow copy to preserve polymorphic runtime type (#7105) (#7109). [Yilou Wang] +* Fix circular class reference %p-printing causing infinite recursion (#7106). +* Fix too-short bit pack returning wrong value (#7111). +* Fix randomize of real (#7115). [Srinivasan Venkataramanan] +* Fix inlining of C functions with reloop locals (#7132). [Geza Lore, Testorrent USA, Inc.] +* Fix segfault in EmitCSyms (#7142) (#7143). [Gilberto Abram] + + Verilator 5.044 2026-01-01 ========================== @@ -361,6 +488,8 @@ Verilator 5.040 2025-08-30 * Fix wide select expansion and substitution (#6341) (#6345). [Geza Lore] * Fix upcasting class type parameters (#6344). [Krzysztof Bieganski, Antmicro Ltd.] * Fix undefined weak link for Apple GCC etc (#6348). [Congcong Cai] +* Fix emitting unbounded parameters (#6912). +* Fix syntax error on unsupported defparam array (#6915). Verilator 5.038 2025-07-08 @@ -5520,9 +5649,9 @@ Verilator 0.0 1994-07-08 Copyright ========= -Copyright 2001-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. +This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. +SPDX-FileCopyrightText: 2001-2025 Wilson Snyder SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 diff --git a/LICENSE b/LICENSE index 0a041280b..513d1c01f 100644 --- a/LICENSE +++ b/LICENSE @@ -1,165 +1,304 @@ - GNU LESSER GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 +GNU LESSER GENERAL PUBLIC LICENSE +Version 3, 29 June 2007 - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. +Copyright (C) 2007 Free Software Foundation, Inc. +Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. - This version of the GNU Lesser General Public License incorporates -the terms and conditions of version 3 of the GNU General Public -License, supplemented by the additional permissions listed below. +This version of the GNU Lesser General Public License incorporates the terms and conditions of version 3 of the GNU General Public License, supplemented by the additional permissions listed below. - 0. Additional Definitions. +0. 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For example, you may not impose a license fee, royalty, or other charge for exercise of rights granted under this License, and you may not initiate litigation (including a cross-claim or counterclaim in a lawsuit) alleging that any patent claim is infringed by making, using, selling, offering for sale, or importing the Program or any portion of it. + +11. Patents. +A “contributor” is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. The work thus licensed is called the contributor's “contributor version”. + +A contributor's “essential patent claims” are all patent claims owned or controlled by the contributor, whether already acquired or hereafter acquired, that would be infringed by some manner, permitted by this License, of making, using, or selling its contributor version, but do not include claims that would be infringed only as a consequence of further modification of the contributor version. For purposes of this definition, “control” includes the right to grant patent sublicenses in a manner consistent with the requirements of this License. + +Each contributor grants you a non-exclusive, worldwide, royalty-free patent license under the contributor's essential patent claims, to make, use, sell, offer for sale, import and otherwise run, modify and propagate the contents of its contributor version. + +In the following three paragraphs, a “patent license” is any express agreement or commitment, however denominated, not to enforce a patent (such as an express permission to practice a patent or covenant not to sue for patent infringement). To “grant” such a patent license to a party means to make such an agreement or commitment not to enforce a patent against the party. + +If you convey a covered work, knowingly relying on a patent license, and the Corresponding Source of the work is not available for anyone to copy, free of charge and under the terms of this License, through a publicly available network server or other readily accessible means, then you must either (1) cause the Corresponding Source to be so available, or (2) arrange to deprive yourself of the benefit of the patent license for this particular work, or (3) arrange, in a manner consistent with the requirements of this License, to extend the patent license to downstream recipients. “Knowingly relying” means you have actual knowledge that, but for the patent license, your conveying the covered work in a country, or your recipient's use of the covered work in a country, would infringe one or more identifiable patents in that country that you have reason to believe are valid. + +If, pursuant to or in connection with a single transaction or arrangement, you convey, or propagate by procuring conveyance of, a covered work, and grant a patent license to some of the parties receiving the covered work authorizing them to use, propagate, modify or convey a specific copy of the covered work, then the patent license you grant is automatically extended to all recipients of the covered work and works based on it. + +A patent license is “discriminatory” if it does not include within the scope of its coverage, prohibits the exercise of, or is conditioned on the non-exercise of one or more of the rights that are specifically granted under this License. You may not convey a covered work if you are a party to an arrangement with a third party that is in the business of distributing software, under which you make payment to the third party based on the extent of your activity of conveying the work, and under which the third party grants, to any of the parties who would receive the covered work from you, a discriminatory patent license (a) in connection with copies of the covered work conveyed by you (or copies made from those copies), or (b) primarily for and in connection with specific products or compilations that contain the covered work, unless you entered into that arrangement, or that patent license was granted, prior to 28 March 2007. + +Nothing in this License shall be construed as excluding or limiting any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. + +12. No Surrender of Others' Freedom. +If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot convey a covered work so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not convey it at all. For example, if you agree to terms that obligate you to collect a royalty for further conveying from those to whom you convey the Program, the only way you could satisfy both those terms and this License would be to refrain entirely from conveying the Program. + +13. Use with the GNU Affero General Public License. +Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed under version 3 of the GNU Affero General Public License into a single combined work, and to convey the resulting work. The terms of this License will continue to apply to the part which is the covered work, but the special requirements of the GNU Affero General Public License, section 13, concerning interaction through a network will apply to the combination as such. + +14. Revised Versions of this License. +The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies that a certain numbered version of the GNU General Public License “or any later version” applies to it, you have the option of following the terms and conditions either of that numbered version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of the GNU General Public License, you may choose any version ever published by the Free Software Foundation. + +If the Program specifies that a proxy can decide which future versions of the GNU General Public License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Program. + +Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version. + +15. Disclaimer of Warranty. +THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +16. Limitation of Liability. +IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +17. Interpretation of Sections 15 and 16. +If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee. + +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs + +If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the “copyright” line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + +If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an “about box”. + +You should also get your employer (if you work as a programmer) or school, if any, to sign a “copyright disclaimer” for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see . + +The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read . diff --git a/LICENSES/Apache-2.0.txt b/LICENSES/Apache-2.0.txt new file mode 100644 index 000000000..137069b82 --- /dev/null +++ b/LICENSES/Apache-2.0.txt @@ -0,0 +1,73 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. Definitions. + +"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. + +"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. + +"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. + +"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License. + +"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files. + +"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types. + +"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below). + +"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof. + +"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution." + +"Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work. + +2. Grant of Copyright License. Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form. + +3. Grant of Patent License. Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed. + +4. Redistribution. You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions: + + (a) You must give any other recipients of the Work or Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License. + + You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License. + +5. Submission of Contributions. Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions. + +6. Trademarks. This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file. + +7. Disclaimer of Warranty. Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License. + +8. Limitation of Liability. In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS + +APPENDIX: How to apply the Apache License to your work. + +To apply the Apache License to your work, attach the following boilerplate notice, with the fields enclosed by brackets "[]" replaced with your own identifying information. (Don't include the brackets!) The text should be enclosed in the appropriate comment syntax for the file format. We also recommend that a file or class name and description of purpose be included on the same "printed page" as the copyright notice for easier identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/LICENSES/Artistic-2.0.txt b/LICENSES/Artistic-2.0.txt new file mode 100644 index 000000000..eb2e968ed --- /dev/null +++ b/LICENSES/Artistic-2.0.txt @@ -0,0 +1,85 @@ +The Artistic License 2.0 + +Copyright (c) 2000-2006, The Perl Foundation. + +Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. + +Preamble + +This license establishes the terms under which a given free software Package may be copied, modified, distributed, and/or redistributed. The intent is that the Copyright Holder maintains some artistic control over the development of that Package while still keeping the Package available as open source and free software. + +You are always permitted to make arrangements wholly outside of this license directly with the Copyright Holder of a given Package. If the terms of this license do not permit the full use that you propose to make of the Package, you should contact the Copyright Holder and seek a different licensing arrangement. + +Definitions + + "Copyright Holder" means the individual(s) or organization(s) named in the copyright notice for the entire Package. + + "Contributor" means any party that has contributed code or other material to the Package, in accordance with the Copyright Holder's procedures. + + "You" and "your" means any person who would like to copy, distribute, or modify the Package. + + "Package" means the collection of files distributed by the Copyright Holder, and derivatives of that collection and/or of those files. A given Package may consist of either the Standard Version, or a Modified Version. + + "Distribute" means providing a copy of the Package or making it accessible to anyone else, or in the case of a company or organization, to others outside of your company or organization. + + "Distributor Fee" means any fee that you charge for Distributing this Package or providing support for this Package to another party. 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To “grant” such a patent license to a party means to make such an agreement or commitment not to enforce a patent against the party. + +If you convey a covered work, knowingly relying on a patent license, and the Corresponding Source of the work is not available for anyone to copy, free of charge and under the terms of this License, through a publicly available network server or other readily accessible means, then you must either (1) cause the Corresponding Source to be so available, or (2) arrange to deprive yourself of the benefit of the patent license for this particular work, or (3) arrange, in a manner consistent with the requirements of this License, to extend the patent license to downstream recipients. “Knowingly relying” means you have actual knowledge that, but for the patent license, your conveying the covered work in a country, or your recipient's use of the covered work in a country, would infringe one or more identifiable patents in that country that you have reason to believe are valid. + +If, pursuant to or in connection with a single transaction or arrangement, you convey, or propagate by procuring conveyance of, a covered work, and grant a patent license to some of the parties receiving the covered work authorizing them to use, propagate, modify or convey a specific copy of the covered work, then the patent license you grant is automatically extended to all recipients of the covered work and works based on it. + +A patent license is “discriminatory” if it does not include within the scope of its coverage, prohibits the exercise of, or is conditioned on the non-exercise of one or more of the rights that are specifically granted under this License. You may not convey a covered work if you are a party to an arrangement with a third party that is in the business of distributing software, under which you make payment to the third party based on the extent of your activity of conveying the work, and under which the third party grants, to any of the parties who would receive the covered work from you, a discriminatory patent license (a) in connection with copies of the covered work conveyed by you (or copies made from those copies), or (b) primarily for and in connection with specific products or compilations that contain the covered work, unless you entered into that arrangement, or that patent license was granted, prior to 28 March 2007. + +Nothing in this License shall be construed as excluding or limiting any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. + +12. No Surrender of Others' Freedom. +If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot convey a covered work so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not convey it at all. For example, if you agree to terms that obligate you to collect a royalty for further conveying from those to whom you convey the Program, the only way you could satisfy both those terms and this License would be to refrain entirely from conveying the Program. + +13. Use with the GNU Affero General Public License. +Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed under version 3 of the GNU Affero General Public License into a single combined work, and to convey the resulting work. The terms of this License will continue to apply to the part which is the covered work, but the special requirements of the GNU Affero General Public License, section 13, concerning interaction through a network will apply to the combination as such. + +14. Revised Versions of this License. +The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies that a certain numbered version of the GNU General Public License “or any later version” applies to it, you have the option of following the terms and conditions either of that numbered version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of the GNU General Public License, you may choose any version ever published by the Free Software Foundation. + +If the Program specifies that a proxy can decide which future versions of the GNU General Public License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Program. + +Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version. + +15. Disclaimer of Warranty. +THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +16. Limitation of Liability. +IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +17. Interpretation of Sections 15 and 16. +If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee. + +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs + +If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the “copyright” line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + +If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an “about box”. + +You should also get your employer (if you work as a programmer) or school, if any, to sign a “copyright disclaimer” for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see . + +The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read . diff --git a/LICENSES/LicenseRef-Altera-No-Warranty.txt b/LICENSES/LicenseRef-Altera-No-Warranty.txt new file mode 100644 index 000000000..10b186678 --- /dev/null +++ b/LICENSES/LicenseRef-Altera-No-Warranty.txt @@ -0,0 +1,7 @@ +This Verilog file was developed by Altera Corporation. It may be +freely copied and/or distributed at no cost. Any persons using this +file for any purpose do so at their own risk, and are responsible for +the results of such use. Altera Corporation does not guarantee that +this file is complete, correct, or fit for any particular purpose. +NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must +accompany any copy of this file. diff --git a/LICENSES/LicenseRef-IEEE-1800.txt b/LICENSES/LicenseRef-IEEE-1800.txt new file mode 100644 index 000000000..d3302aee0 --- /dev/null +++ b/LICENSES/LicenseRef-IEEE-1800.txt @@ -0,0 +1,22 @@ +This license is used on IEEE files where there is a permitted use of +standards, including copying strictly necessary to implement normative +interfaces defined by the standard. Refer to IEEE SA Operations Manual +Clause 6.1 and IEEE Standards Permission policies. + +-- + +Copyright 2024 by The Institute of Electrical and Electronics Engineers, Inc. +All rights reserved. + +IEEE, 802, and POSIX are registered trademarks in the U.S. Patent & +Trademark Office, owned by The Institute of Electrical and Electronics +Engineers, Incorporated. + +IEEE draft and approved standards are copyrighted by IEEE under US and +international copyright laws. They are made available by IEEE and are +adopted for a wide variety of both public and private uses. These include +both use, by reference, in laws and regulations, and use in private +self-regulation, standardization, and the promotion of engineering +practices and methods. By making these documents available for use and +adoption by public authorities and private users, neither IEEE nor its +licensors waive any rights in copyright to the documents. diff --git a/LICENSES/MIT.txt b/LICENSES/MIT.txt new file mode 100644 index 000000000..d817195da --- /dev/null +++ b/LICENSES/MIT.txt @@ -0,0 +1,18 @@ +MIT License + +Copyright (c) + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and +associated documentation files (the "Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the +following conditions: + +The above copyright notice and this permission notice shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT +LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO +EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/LICENSES/Unlicense.txt b/LICENSES/Unlicense.txt new file mode 100644 index 000000000..cde4ac698 --- /dev/null +++ b/LICENSES/Unlicense.txt @@ -0,0 +1,10 @@ +This is free and unencumbered software released into the public domain. + +Anyone is free to copy, modify, publish, use, compile, sell, or distribute this software, either in source code form or as a compiled binary, for any purpose, commercial or non-commercial, and by any means. + +In jurisdictions that recognize copyright laws, the author or authors of this software dedicate any and all copyright interest in the software to the public domain. We make this dedication for the benefit of the public at large and to the detriment of our heirs and +successors. We intend this dedication to be an overt act of relinquishment in perpetuity of all present and future rights to this software under copyright law. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +For more information, please refer to diff --git a/Makefile.in b/Makefile.in index 7f576d240..164e7768f 100644 --- a/Makefile.in +++ b/Makefile.in @@ -7,10 +7,10 @@ # #***************************************************************************** # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ @@ -578,6 +578,7 @@ MBAKE_FLAGS = format --config ./.bake.toml format-exec: -chmod a+x test_regress/t/*.py + -chmod a-x test_regress/t/*.v format-make mbake: $(MBAKE) --version @@ -862,7 +863,8 @@ VENV_PATH ?= .venv venv: # Create virtual environment using the python3 picked up by configure [ -e $(VENV_PATH) ] || @PYTHON3@ -m venv --system-site-packages $(VENV_PATH) - # Install python3 dependencies + # Install python3 dependencies, with explicit retry + $(VENV_PATH)/bin/pip3 install -r python-dev-requirements.txt || \ $(VENV_PATH)/bin/pip3 install -r python-dev-requirements.txt @echo @echo "Installed Python virtual environment, in:" diff --git a/README.rst b/README.rst index f8b360ad1..bec2182ad 100644 --- a/README.rst +++ b/README.rst @@ -1,5 +1,7 @@ .. Github doesn't render images unless absolute URL .. Do not know of a conditional tag, "only: github" nor "github display" works +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 |badge1| |badge2| |badge3| |badge4| |badge5| |badge7| |badge8| @@ -28,7 +30,7 @@ Welcome to Verilator * Accepts Verilog or SystemVerilog * Performs lint code-quality checks * Compiles into multithreaded C++, or SystemC - * Creates XML to front-end your own tools + * Creates JSON to front-end your own tools - |Logo| * - |verilator multithreaded performance| - **Fast** @@ -60,18 +62,20 @@ performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multithreaded .cpp and .h files, the "Verilated" code. -These Verilated C++/SystemC files are then compiled by a C++ compiler -(gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper -file, to instantiate the Verilated model. Executing the resulting -executable performs the design simulation. Verilator also supports linking -Verilated generated libraries, optionally encrypted, into other simulators. +Verilator can automatically generate a simulator executable (using +``--binary``), or users can write their own C++/SystemC wrapper to +instantiate the model. The resulting Verilated executable performs the +design simulation. Verilator also supports linking Verilator-generated +libraries, optionally encrypted, into other simulators. -Verilator may not be the best choice if you are expecting a full-featured -replacement for a closed-source Verilog simulator, need SDF annotation, -mixed-signal simulation, or are doing a quick class project (we recommend -`Icarus Verilog`_ for classwork). However, if you are looking for a path to -migrate SystemVerilog to C++/SystemC, or want high-speed simulation of -designs, Verilator is the tool for you. +Verilator supports all design constructs, most verification constructs, +intra-assignment delays (e.g, `#10`), and events. Tristate-bus (`z`) and +unknowns (`x`) are handled in limited contexts, in a special manor for +performance. It currently may not be the best choice if you are expecting a +full-featured replacement for a closed-source Verilog simulator, performing +SDF annotation, or mixed-signal simulation. However, if you are looking for +a path to migrate SystemVerilog to C++/SystemC, or want high-speed +simulation, Verilator is the tool for you. Performance @@ -132,6 +136,10 @@ organizations; please see `Verilator Commercial Support Related Projects ================ +- `Cocotb `_ - A coroutine-based cosimulation + library for writing testbenches in Python which officially supports + Verilator. + - `GTKwave `_ - Waveform viewer for Verilator traces. diff --git a/REUSE.toml b/REUSE.toml new file mode 100644 index 000000000..d0f53012e --- /dev/null +++ b/REUSE.toml @@ -0,0 +1,60 @@ +# DESCRIPTION: Verilator default licensing for "reuse lint" + +version = 1 + +[[annotations]] +path = [ + "**/.gitattributes", + "**/.gitignore", + ".clang-format", + ".clang-tidy", + ".codacy.yml", + ".devcontainer/devcontainer.json", + ".github/**", + ".pre-commit-hooks.yaml", + ".style.yapf", + "CITATION.cff", + "CPPLINT.cfg", + "docs/CONTRIBUTORS", + "docs/spelling.txt", + "docs/verilated.dox", + "examples/**/*.vc", + "install-sh", + "test_regress/.gdbinit", + "test_regress/input.vc", + "test_regress/input.xsim.vc", + "test_regress/t/*.dat", + "test_regress/t/*.gprof", + "test_regress/t/*.mem", + "test_regress/t/*.out", + "test_regress/t/*.tree", + "test_regress/t/*.vc", + "test_regress/t/t_lint_bsspace_bad.v", + "verilator.pc.in", +] +SPDX-FileCopyrightText = "2003-2026 Wilson Snyder" +SPDX-License-Identifier = "CC0-1.0" + +[[annotations]] +path = [ + "docs/_static/**", + "docs/gen/*.rst", + "docs/guide/figures/**", +] +SPDX-FileCopyrightText = "2003-2026 Wilson Snyder" +SPDX-License-Identifier = "LGPL-3.0-only OR Artistic-2.0" + +[[annotations]] +path = "test_regress/t/uvm/**" +SPDX-FileCopyrightText = [ + "2010-2017 Mentor Graphics Corporation", + "2010-2013 Synopsys, Inc.", + "2010-2018 Cadence Design Systems, Inc.", + "2013 NVIDIA Corporation", +] +SPDX-License-Identifier = "Apache-2.0" + +[[annotations]] +path = "include/gtkwave/lz4.*" +SPDX-FileCopyrightText = "2011-2023 Yann Collet" +SPDX-License-Identifier = "BSD-2-Clause" diff --git a/bin/redirect b/bin/redirect index 76bebfa90..e9411316d 100644 --- a/bin/redirect +++ b/bin/redirect @@ -1,10 +1,10 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/bin/verilator b/bin/verilator index 4cd6e160c..ab07e6201 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1,10 +1,10 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### @@ -482,11 +482,13 @@ detailed descriptions of these arguments. --quiet-stats Don't print statistics --relative-includes Resolve includes relative to current file --reloop-limit Minimum iterations for forming loops + --replication-limit Replication concatenation limit (default: 8k) --report-unoptflat Extra diagnostics for UNOPTFLAT --rr Run Verilator and record with rr --runtime-debug Enable model runtime debugging --savable Enable model save-restore --sc Create SystemC output + --sched-zero-delay Specify #0 delay support --no-skip-identical Disable skipping identical output --stats Create statistics file --stats-vars Provide statistics on variables @@ -552,8 +554,6 @@ detailed descriptions of these arguments. --x-assign Assign non-initial Xs to this value --x-initial Assign initial Xs to this value --x-initial-edge Enable initial X->0 and X->1 edge triggers - --xml-only Create XML parser output - --xml-output XML output filename -y Directory to search for modules This is a short summary of the simulation runtime arguments, i.e. for the @@ -578,6 +578,7 @@ description of these arguments. +verilator+seed+ Set random seed +verilator+V Show verbose version and config +verilator+version Show version and exit + +verilator+wno+unsatconstr+ Disable constraint warnings =head1 DISTRIBUTION diff --git a/bin/verilator_ccache_report b/bin/verilator_ccache_report index 2866adfe0..b6dc728a3 100755 --- a/bin/verilator_ccache_report +++ b/bin/verilator_ccache_report @@ -17,12 +17,13 @@ parser = argparse.ArgumentParser( For documentation see https://verilator.org/guide/latest/exe_verilator_ccache_report.html""", - epilog="""Copyright 2002-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2002-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('-o', type=pathlib.Path, metavar="OUTFILE", required=True, help='output file') parser.add_argument('logdir', type=pathlib.Path, help='log directory') diff --git a/bin/verilator_coverage b/bin/verilator_coverage index 4d828ce90..961c4cf26 100755 --- a/bin/verilator_coverage +++ b/bin/verilator_coverage @@ -1,10 +1,10 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # ###################################################################### @@ -197,6 +197,7 @@ can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. +SPDX-FileCopyrightText: 2003-2026 Wilson Snyder SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 SEE ALSO diff --git a/bin/verilator_difftree b/bin/verilator_difftree index 163a87a01..96dbbe9d7 100755 --- a/bin/verilator_difftree +++ b/bin/verilator_difftree @@ -110,12 +110,13 @@ It performs a diff between two files, or all files common between two directories, ignoring irrelevant pointer differences. Exit status is 0 if inputs are the same, 1 if different, 2 if trouble.""", - epilog="""Copyright 2005-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2005-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('--no-lineno', diff --git a/bin/verilator_gantt b/bin/verilator_gantt index 845e13c08..e01a434ff 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -613,12 +613,13 @@ Verilator_gantt creates a visual representation to help analyze Verilator For documentation see https://verilator.org/guide/latest/exe_verilator_gantt.html""", - epilog="""Copyright 2018-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2018-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--debug', action='store_true', help='enable debug') parser.add_argument('--no-vcd', help='disable creating vcd', action='store_true') diff --git a/bin/verilator_includer b/bin/verilator_includer index 648dba61a..40ca418ab 100755 --- a/bin/verilator_includer +++ b/bin/verilator_includer @@ -2,11 +2,11 @@ # mypy: disallow-untyped-defs # pylint: disable=C0114,C0209 # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify the Verilator internals under the terms -# of either the GNU Lesser General Public License Version 3 or the Perl -# Artistic License Version 2.0. +# This program is free software; you can redistribute it and/or modify the +# Verilator internals under the terms of either the GNU Lesser General +# Public License Version 3 or the Perl Artistic License Version 2.0. # +# SPDX-FileCopyrightText: 2003-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index cf47d3587..b4d3b7089 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -173,12 +173,13 @@ in each Verilog block. For documentation see https://verilator.org/guide/latest/exe_verilator_profcfunc.html""", - epilog="""Copyright 2002-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2002-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('filename', help='input gprof output to process') diff --git a/ci/ci-install.bash b/ci/ci-install.bash index 4f349cc02..fe3ed6e4e 100755 --- a/ci/ci-install.bash +++ b/ci/ci-install.bash @@ -1,11 +1,7 @@ #!/usr/bin/env bash # DESCRIPTION: Verilator: CI dependency install script # -# Copyright 2020 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# +# SPDX-FileCopyrightText: 2020 Geza Lore # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ @@ -47,7 +43,7 @@ fi install-vcddiff() { TMP_DIR="$(mktemp -d)" git clone https://github.com/veripool/vcddiff "$TMP_DIR" - git -C "${TMP_DIR}" checkout dca845020668887fd13498c772939814d9264fd5 + git -C "${TMP_DIR}" checkout 4db0d84a27e8f148b127e916fc71d650837955c5 "$MAKE" -C "${TMP_DIR}" sudo cp "${TMP_DIR}/vcddiff" /usr/local/bin } @@ -76,7 +72,9 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then sudo apt-get install bear mold fi elif [ "$CI_OS_NAME" = "osx" ]; then + brew update || brew update + brew install ccache perl gperftools autoconf bison flex help2man || brew install ccache perl gperftools autoconf bison flex help2man elif [ "$CI_OS_NAME" = "freebsd" ]; then sudo pkg install -y autoconf bison ccache gmake perl5 diff --git a/ci/ci-pages-notify.bash b/ci/ci-pages-notify.bash index 3e892f868..05bb92fe6 100755 --- a/ci/ci-pages-notify.bash +++ b/ci/ci-pages-notify.bash @@ -1,11 +1,7 @@ #!/usr/bin/env bash # DESCRIPTION: Verilator: CI script for 'pages.yml', notifies PRs # -# Copyright 2025 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# +# SPDX-FileCopyrightText: 2025 Geza Lore # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Notify PRs via comment that their coverage reports are available diff --git a/ci/ci-pages.bash b/ci/ci-pages.bash index 10d992468..ba9013621 100755 --- a/ci/ci-pages.bash +++ b/ci/ci-pages.bash @@ -1,11 +1,7 @@ #!/usr/bin/env bash # DESCRIPTION: Verilator: CI script for 'pages.yml', builds the GitHub Pages # -# Copyright 2025 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# +# SPDX-FileCopyrightText: 2025 Geza Lore # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This scipt build the content of the GitHub Pages for the repository. diff --git a/ci/ci-script.bash b/ci/ci-script.bash index 9c24bb52e..816fe6636 100755 --- a/ci/ci-script.bash +++ b/ci/ci-script.bash @@ -1,11 +1,7 @@ #!/usr/bin/env bash # DESCRIPTION: Verilator: CI main job script # -# Copyright 2020 by Geza Lore. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# +# SPDX-FileCopyrightText: 2020 Geza Lore # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ diff --git a/ci/ci-win-compile.ps1 b/ci/ci-win-compile.ps1 index 1cc694248..2722d8362 100644 --- a/ci/ci-win-compile.ps1 +++ b/ci/ci-win-compile.ps1 @@ -1,10 +1,6 @@ # DESCRIPTION: Verilator: CI Windows Power Shell - Compile Verilator # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ diff --git a/ci/ci-win-test.ps1 b/ci/ci-win-test.ps1 index 7baf9c5f3..23697fe09 100644 --- a/ci/ci-win-test.ps1 +++ b/ci/ci-win-test.ps1 @@ -1,10 +1,6 @@ # DESCRIPTION: Verilator: CI Windows Power Shell - Verilate a test # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ################################################################################ diff --git a/ci/docker/buildenv/Dockerfile b/ci/docker/buildenv/Dockerfile index 520735317..29a8c1d2d 100644 --- a/ci/docker/buildenv/Dockerfile +++ b/ci/docker/buildenv/Dockerfile @@ -1,9 +1,9 @@ # DESCRIPTION: Dockerfile for env to build and fully test Verilator # -# Copyright 2020 by Stefan Wallentowitz. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 FROM ubuntu:24.04 diff --git a/ci/docker/buildenv/README.rst b/ci/docker/buildenv/README.rst index 8a1f3deb7..146725466 100644 --- a/ci/docker/buildenv/README.rst +++ b/ci/docker/buildenv/README.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _verilator build docker container: diff --git a/ci/docker/buildenv/build.sh b/ci/docker/buildenv/build.sh index 1894ba58f..b30a34b56 100755 --- a/ci/docker/buildenv/build.sh +++ b/ci/docker/buildenv/build.sh @@ -1,10 +1,10 @@ #!/bin/bash -e # DESCRIPTION: Build Verilator (inside container) # -# Copyright 2020 by Stefan Wallentowitz. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 : "${REPO:=https://github.com/verilator/verilator}" diff --git a/ci/docker/run/Dockerfile b/ci/docker/run/Dockerfile index 32391c69f..8a6637906 100644 --- a/ci/docker/run/Dockerfile +++ b/ci/docker/run/Dockerfile @@ -1,9 +1,9 @@ # DESCRIPTION: Dockerfile for image to run Verilator inside # -# Copyright 2020 by Stefan Wallentowitz. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 FROM ubuntu:24.04 diff --git a/ci/docker/run/README.rst b/ci/docker/run/README.rst index e960d1a81..1ef7f9fb4 100644 --- a/ci/docker/run/README.rst +++ b/ci/docker/run/README.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Verilator Executable Docker Container diff --git a/ci/docker/run/hooks/build b/ci/docker/run/hooks/build index 6d2290cae..3ca74378f 100644 --- a/ci/docker/run/hooks/build +++ b/ci/docker/run/hooks/build @@ -1,10 +1,10 @@ #!/bin/bash # DESCRIPTION: Docker hub hook to pass SOURCE_COMMIT # -# Copyright 2020 by Stefan Wallentowitz. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 docker build --build-arg SOURCE_COMMIT=${SOURCE_COMMIT} -f $DOCKERFILE_PATH -t $IMAGE_NAME . diff --git a/ci/docker/run/hooks/post_push b/ci/docker/run/hooks/post_push index 6da467d3f..baf2b54b5 100755 --- a/ci/docker/run/hooks/post_push +++ b/ci/docker/run/hooks/post_push @@ -1,10 +1,10 @@ #!/bin/bash # DESCRIPTION: Docker hub hook to tag the latest release (stable) # -# Copyright 2020 by Stefan Wallentowitz. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 if [ "$SOURCE_BRANCH"="stable" ]; then diff --git a/ci/docker/run/verilator-docker b/ci/docker/run/verilator-docker index 9648c2903..0c0d59bbd 100755 --- a/ci/docker/run/verilator-docker +++ b/ci/docker/run/verilator-docker @@ -1,10 +1,10 @@ #!/bin/bash # DESCRIPTION: Wrap a verilator call to run a docker container # -# Copyright 2020 by Stefan Wallentowitz. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 docker pull verilator/verilator:$1 >/dev/null diff --git a/ci/docker/run/verilator-wrap.sh b/ci/docker/run/verilator-wrap.sh index 1a5aa6211..04dd3b98b 100755 --- a/ci/docker/run/verilator-wrap.sh +++ b/ci/docker/run/verilator-wrap.sh @@ -2,10 +2,10 @@ # DESCRIPTION: Wrap a Verilator call and copy vlt includes # (inside docker container) # -# Copyright 2020 by Stefan Wallentowitz. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2020 Stefan Wallentowitz # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 perl /usr/local/bin/verilator "$@" diff --git a/configure.ac b/configure.ac index 96e60accd..cfb627b8c 100644 --- a/configure.ac +++ b/configure.ac @@ -1,8 +1,9 @@ # DESCRIPTION: Process this file with autoconf to produce a configure script. # -# Copyright 2003-2026 by Wilson Snyder. Verilator is free software; you -# can redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Perl Artistic License Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2003-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # When releasing, also update header of Changes file, and CMakeLists.txt, @@ -11,7 +12,7 @@ # Then 'make maintainer-dist' #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) -AC_INIT([Verilator],[5.044 2026-01-01], +AC_INIT([Verilator],[5.046 2026-02-28], [https://verilator.org], [verilator],[https://verilator.org]) diff --git a/docs/CONTRIBUTING.rst b/docs/CONTRIBUTING.rst index 4b42b8f1d..7c91c9295 100644 --- a/docs/CONTRIBUTING.rst +++ b/docs/CONTRIBUTING.rst @@ -1,3 +1,6 @@ +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + Contributing to Verilator ========================= diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index a3fca586c..5ac1958e1 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -12,6 +12,7 @@ Aidan McNay Aleksander Kiryk Alex Chadwick Alex Solomatnikov +Alex Zhou Aliaksei Chapyzhenka Ameya Vikram Singh Andrea Calabrese @@ -25,10 +26,12 @@ Anthony Moore Arkadiusz Kozdra Arthur Rosa Artur Bieniek +AUDIY Aylon Chaim Porat Bartłomiej Chmiel Brian Li Cameron Kirk +Cameron Waite Chih-Mao Chen Chris Bachhuber Chris Randall @@ -135,6 +138,7 @@ Julie Schwartz Julien Margetts Justin Thiel Kaleb Barrett +Kamil Danecki Kamil Rakoczy Kanad Kanhere Kefa Chen @@ -151,6 +155,7 @@ Krzysztof Sychla Kuba Ober Lan Zongwei Larry Doolittle +Leela Pakanati Liam Braun Luca Colagrande Ludwig Rogiers @@ -257,7 +262,9 @@ Varun Koyyalagunta Vassilis Papaefstathiou Veripool API Bot Victor Besyakov +Vikash Patel Vito Gamberini +Wei-Lun Chiu William D. Jones Wilson Snyder Xi Zhang @@ -281,5 +288,6 @@ dependabot[bot] february cozzocrea sumpster em2machine +emmettifelts Àlex Torregrosa Ícaro Lima diff --git a/docs/Makefile b/docs/Makefile index c7ebd2ef6..44f5f9f1f 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -5,10 +5,10 @@ # # Code available from: https://verilator.org # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/docs/README.rst b/docs/README.rst index 0752c6a5c..5ace9194a 100644 --- a/docs/README.rst +++ b/docs/README.rst @@ -1,3 +1,6 @@ +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + Verilator Documentation ======================= diff --git a/docs/bin/vl_sphinx_extract b/docs/bin/vl_sphinx_extract index 9b1aac284..a6794e14d 100755 --- a/docs/bin/vl_sphinx_extract +++ b/docs/bin/vl_sphinx_extract @@ -37,12 +37,13 @@ parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Read a file and extract documentation data.""", - epilog=""" Copyright 2021-2026 by Wilson Snyder. This package is free software; -you can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2021-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('path', help='path to extract from') diff --git a/docs/bin/vl_sphinx_fix b/docs/bin/vl_sphinx_fix index 32c3455ec..cd0ee46ca 100755 --- a/docs/bin/vl_sphinx_fix +++ b/docs/bin/vl_sphinx_fix @@ -52,12 +52,13 @@ parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Post-process Sphinx HTML.""", - epilog=""" Copyright 2021-2026 by Wilson Snyder. This package is free software; -you can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2021-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('path', help='path to edit') diff --git a/docs/gen/ex_DIDNOTCONVERGE_msg.rst b/docs/gen/ex_DIDNOTCONVERGE_msg.rst index f86acce02..c792ab810 100644 --- a/docs/gen/ex_DIDNOTCONVERGE_msg.rst +++ b/docs/gen/ex_DIDNOTCONVERGE_msg.rst @@ -2,4 +2,4 @@ .. code-block:: -V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] a) - %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries + %Error-DIDNOTCONVERGE: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after '--converge-limit' of 100 tries diff --git a/docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst b/docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst index 77abc8534..4f3a63c82 100644 --- a/docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst +++ b/docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst @@ -1,4 +1,4 @@ .. comment: generated by t_lint_didnotconverge_nodbg_bad .. code-block:: - %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries + %Error-DIDNOTCONVERGE: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after '--converge-limit' of 100 tries diff --git a/docs/guide/changes.rst b/docs/guide/changes.rst index 7aecb111a..09264212b 100644 --- a/docs/guide/changes.rst +++ b/docs/guide/changes.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 **************** diff --git a/docs/guide/conf.py b/docs/guide/conf.py index a9392b6ab..f873c144a 100644 --- a/docs/guide/conf.py +++ b/docs/guide/conf.py @@ -1,7 +1,7 @@ # pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622 # # Configuration file for Verilator's Sphinx documentation builder. -# Copyright 2003-2026 by Wilson Snyder. +# SPDX-FileCopyrightText: 2003-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # # This file only contains overridden options. For a full list: @@ -81,7 +81,7 @@ if 'VERILATOR_SPHINX_EXTENSIONS' in os.environ: # directories to ignore when looking for source files. # This pattern also affects html_static_path and html_extra_path. exclude_patterns = [ - '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst', 'gen/ex_*', 'CONTRIBUTING.rst' + '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'gen/ex_*', 'CONTRIBUTING.rst' ] # Warn about refs diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst index f3c8eedbf..a78a3cc1b 100644 --- a/docs/guide/connecting.rst +++ b/docs/guide/connecting.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _connecting: diff --git a/docs/guide/contributing.rst b/docs/guide/contributing.rst index 80c11be2f..9975c7512 100644 --- a/docs/guide/contributing.rst +++ b/docs/guide/contributing.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ******************************* diff --git a/docs/guide/contributors.rst b/docs/guide/contributors.rst index 8f9d42dfd..782a79865 100644 --- a/docs/guide/contributors.rst +++ b/docs/guide/contributors.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ************************ @@ -29,9 +29,9 @@ Alliance `_, and `Antmicro Ltd Previous major corporate sponsors of Verilator, by providing significant contributions of time or funds include: Antmicro Ltd., Atmel Corporation, Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Fractile -Ltd., Hicamp Systems, Intel Corporation, Marvell Inc., Mindspeed -Technologies Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems -Inc., Nauticus Networks Inc., SiCortex Inc, Shunyao CAD, and Western +Ltd., Hicamp Systems, Intel Corporation, Marvell Inc., Mindspeed Technologies +Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus +Networks Inc., SiCortex Inc, Shunyao CAD, Tenstorrent USA, Inc. and Western Digital Inc. The contributors of major functionality are: Jeremy Bennett, Krzysztof diff --git a/docs/guide/control.rst b/docs/guide/control.rst new file mode 100644 index 000000000..d42afceff --- /dev/null +++ b/docs/guide/control.rst @@ -0,0 +1,348 @@ +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _verilator control files: + +======================= +Verilator Control Files +======================= + +In addition to the command line, warnings and other features for the +:command:`verilator` command may be controlled with Verilator Control +Files, not to be confused with IEEE Configurations blocks +(`config...endconfig`). Typically named with the `.vlt` extension, what +makes it a Verilator Control File is the :option:`\`verilator_config` +directive. These files, when named `.vlt`, are read before source code +files; if this behavior is undesired, name the control file with a `.v` or +other suffix. + +An example: + +.. code-block:: sv + + `verilator_config + lint_off -rule WIDTH + lint_off -rule CASEX -file "silly_vendor_code.v" + +This disables WIDTH warnings globally, and CASEX for a specific file. + +Verilator control files are fed through the normal Verilog preprocessor +prior to parsing, so "\`ifdef", "\`define", and comments may be used as if +the control file was standard Verilog code. + +Note that file or line-specific control only applies to files read after +the control file. It is therefore recommended to pass the control file to +Verilator as the first file. + +The grammar of control commands is as follows: + +.. option:: `verilator_config + + Take the remaining text and treat it as Verilator Control File commands. + See :ref:`Verilator Control Files`. + +.. option:: clock_enable -module "" -var "" + + Deprecated and has no effect (ignored). + + In versions before 5.000: + + Indicates that the signal is used to gate a clock, and the user takes + responsibility for ensuring there are no races related to it. + + Same as :option:`/*verilator&32;clock_enable*/` metacomment. + + + .. t_dist_docs_style ignore no_clocker + +.. option:: clocker -module "" [-function ""] -var "" + +.. option:: clocker -module "" [-task ""] -var "" + +.. option:: no_clocker -module "" [-function ""] -var "" + +.. option:: no_clocker -module "" [-task ""] -var "" + + Deprecated and has no effect (ignored). + + In versions before 5.042: + + Indicates whether the signal is used as clock or not. Verilator uses + this information to mark the signal and any derived signals as clocker. + See :vlopt:`--clk`. + + Same as :option:`/*verilator&32;clocker*/` metacomment. + +.. option:: coverage_block_off -file "" -line + +.. option:: coverage_block_off -module "" -block "" + + Specifies the entire begin/end block should be ignored for coverage + analysis purposes. It can either be specified as a named block or as a + filename and line number. + + Same as :option:`/*verilator&32;coverage_block_off*/` metacomment. + +.. option:: coverage_off [-file "" [-lines [ - ]]] + +.. option:: coverage_on [-file "" [-lines [ - ]]] + + Enable/disable coverage for the specified filename (or wildcard with + '\*' or '?', or all files if omitted) and range of line numbers (or all + lines if omitted). Often used to ignore an entire module for coverage + analysis purposes. + +.. option:: forceable -module "" -var "" + + Generate public `__VforceEn` and `__VforceVal` signals + that can force/release a signal from C++ code. The force control + signals are created as :option:`public_flat` signals. + + Same as :option:`/*verilator&32;forceable*/` metacomment. + +.. option:: full_case -file "" -lines + + Same as ``//synthesis full_case``. When these synthesis directives + are discovered, Verilator will either formally prove the directive to be + true, or, failing that, will insert the appropriate code to detect + failing cases at simulation runtime and print an "Assertion failed" + error message. + +.. option:: hier_block -module "" + + Specifies that the module is an unit of hierarchical Verilation. Note + that the setting is ignored unless the :vlopt:`--hierarchical` option is + specified. See :ref:`Hierarchical Verilation`. + +.. option:: hier_params -module "" + + Specifies that the module contains parameters a :vlopt:`--hierarchical` block. This option + is used internally to specify parameters for deparametrized hier block instances. + This option should not be used directly. + See :ref:`Hierarchical Verilation`. + +.. option:: hier_workers -hier-dpi "" -workers + + Specifies how many threads need to be used for scheduling hierarchical DPI + tasks. This data is inserted internally during :vlopt:`--hierarchical`, + based on value specified in `hier_workers -module`. This option + should not be used directly. See :ref:`Hierarchical Verilation`. + +.. option:: hier_workers -module "" -workers + + Specifies how many threads need to be used for scheduling given module with + :option:`/*verilator&32;hier_block*/` metacomment. This number needs to be + smaller than :vlopt:`--threads` to fit in a thread schedule. + See :ref:`Hierarchical Verilation`. + +.. option:: inline -module "" + + Specifies the module may be inlined into any modules that use this + module. Same as :option:`/*verilator&32;inline_module*/` metacomment. + + .. t_dist_docs_style ignore no_inline + +.. option:: no_inline -module "" + + Specifies the module should not be inlined into any modules that use + this module. Same as :option:`/*verilator&32;no_inline_module*/` + metacomment. + +.. option:: no_inline [-module ""] -function "" + +.. option:: no_inline [-module ""] -task "" + + Specify the function or task should not be inlined into where it is + used. This may reduce the size of the final executable when a task is + used a very large number of times. For this flag to work, the task and + tasks below it must be pure; they cannot reference any variables outside + the task itself. + + Same as :option:`/*verilator&32;no_inline_task*/` metacomment. + +.. option:: isolate_assignments -module "" -function "" + +.. option:: isolate_assignments -module "" [-function ""] -var "" + +.. option:: isolate_assignments -module "" [-task ""] -var "" + + Used to indicate that the assignments to this signal in any blocks + should be isolated into new blocks. Same as + :option:`/*verilator&32;isolate_assignments*/` metacomment. + +.. option:: lint_off [-rule ] [-file "" [-lines [ - ]]] + +.. option:: lint_off [-rule ] [-file ""] [-contents ""] [-match ""] + +.. option:: lint_on [-rule ] [-file "" [-lines [ - ]]] + + Enable/disables the specified lint warning, in the specified filename + (or wildcard with '\*' or '?', or all files if omitted) and range of + line numbers (or all lines if omitted). + + If the ``-rule`` is omitted, all lint warnings (see list in + :vlopt:`-Wno-lint`) are enabled/disabled. + + If ``-contents`` is provided, the input files must contain the given + wildcard (with '\*' or '?'), and are waived in case they match, provided + the ``-rule``, ``-file``, and ``-contents`` also match. The wildcard + should be designed to match a single line; it is unspecified if the + wildcard is allowed to match across multiple lines. The input contents + does not include :vlopt:`--std <--no-std>` standard files, nor control + files (with ``verilator_config``). Typical use for this is to match a + version number present in the Verilog sources, so that the waiver will + only apply to that version of the sources. + + If ``-match`` is provided, the linter warnings are matched against the + given wildcard (with '\*' or '?'), and are waived in case they match, + provided the ``-rule``, ``-file``, and ``-contents`` also match. The + wildcard is compared across the entire multi-line message; see + :vlopt:`--waiver-multiline`. + + When there are overlapping conflicting lint_on/lint_off directives, they + are resolved in the following priority order: + + * All lint_on/lint_off without a ``-file``, or with a ``-file "\*"``, + are processed in order of parsing. + * All lint_on/lint_off with ``-file "non-\*"`` are processed in order of + parsing. + * All lint_off with ``--match`` in order of parsing. + + If a warning is disabled with lint_off, it will not be printed, even if + the source contains a lint_on metacomment. The control file directives + and metacomments are interpreted separately and do not interact. A + warning is emitted only if not disabled either in a control file or via + metacomments. + + Before version 4.026, ``-rule`` was named ``-msg``, and + ``-msg`` remained a deprecated alias until Version 5.000. + +.. option:: parallel_case -file "" -lines + + Same as ``//synthesis parallel_case``. When these synthesis + directives are discovered, Verilator will either formally prove the + directive to be true, or, failing that, will insert the appropriate code + to detect failing cases at simulation runtime and print an "Assertion + failed" error message. + +.. option:: profile_data -hier-dpi "" -cost + + Internal profiling data inserted during :vlopt:`--hierarchical`; specifies + execution cost of a hierarchical DPI wrappers for modules with + :option:`/*verilator&32;hier_block*/` metacomment. See + :ref:`Hierarchical Verilation`. + +.. option:: profile_data -mtask "" -cost + + Feeds profile-guided optimization data into the Verilator algorithms in + order to improve model runtime performance. This option is not expected + to be used by users directly. See :ref:`Thread PGO`. + +.. option:: public [-module ""] [-task/-function ""] [-var ""] + +.. option:: public_flat [-module ""] [-task/-function ""] [(-param | -port | -var) ""] + +.. option:: public_flat_rd [-module ""] [-task/-function ""] [(-param | -port | -var) ""] + +.. option:: public_flat_rw [-module ""] [-task/-function ""] [(-param | -port | -var) ""] ["@(edge)"] + + Sets the specified signal to be public. Same as + :option:`/*verilator&32;public*/` or + :option:`/*verilator&32;public_flat*/`, etc., metacomments. See also + :ref:`VPI Example`. + + Using ``-port`` only selects matching ports, ``-param`` matches + parameters and localparams, and ``-var`` matches any signal (including + ports, parameters, and regular variables or nets). In all three, the + following ```` can contain ``*`` and ``?`` wildcard + characters that match any substring or any single character respectively. + +.. option:: sc_biguint -module "" -var "" + + Sets the input/output signal to be of ``sc_biguint<{width}>`` type. + This metacomment works for signals of any width. + Same as :option:`/*verilator&32;sc_biguint*/` metacomment. + +.. option:: sc_bv -module "" -var "" + + Sets the port to be of ``sc_bv<{width}>`` type, instead of bool, + uint32_t, or uint64_t. Same as :option:`/*verilator&32;sc_bv*/` + metacomment. + +.. option:: sformat [-module ""] [-function ""] -var "" + +.. option:: sformat [-module ""] [-task ""] -var "" + + Must be applied to the final argument of type ``input string`` of a + function or task to indicate that the function or task should pass all + remaining arguments through $sformatf. This allows the creation of DPI + functions with $display-like behavior. See the + :file:`test_regress/t/t_dpi_display.v` file for an example. + + Same as :option:`/*verilator&32;sformat*/` metacomment. + +.. option:: split_var [-module ""] [-function ""] -var "" + +.. option:: split_var [-module ""] [-task ""] -var "" + + Break the variable into multiple pieces typically to resolve UNOPTFLAT + performance issues. Typically the variables to attach this to are + recommended by Verilator itself; see :option:`UNOPTFLAT`. + + Same as :option:`/*verilator&32;split_var*/` metacomment. + +.. option:: timing_off [-file "" [-lines [ - ]]] + +.. option:: timing_on [-file "" [-lines [ - ]]] + + Enables/disables timing constructs for the specified file and lines. + When disabled, all timing control constructs in the specified source + code locations are ignored the same way as with the + :option:`--no-timing`, and code:`fork`/``join*`` blocks are + converted into ``begin``/``end`` blocks. + + Similar to :option:`/*verilator&32;timing_on*/`, + :option:`/*verilator&32;timing_off*/` meta-comments, but interpreted + independently. If either a control file, or meta-comments disable timing + constructs, they will be disabled. + + .. t_dist_docs_style ignore tracing_on + +.. option:: tracing_off [-file "" [-lines [ - ]]] + +.. option:: tracing_on [-file "" [-lines [ - ]]] + +.. option:: tracing_off [-scope "" [-levels ]] + +.. option:: tracing_on [-scope "" [-levels ]] + + Enable/disable waveform tracing for all future signals declared in + all files. + + With ``-file``, enable/disable waveform tracing in the specified + filename (or wildcard with '\*' or '?'), and ``-line`` range of line + numbers (or all lines if omitted). + + For tracing_off with ``-file``, instances below any module in the + files/ranges specified will also not be traced. To overcome this + feature, use tracing_on on the upper module declaration and on any + cells, or use the ``-scope`` flavor of the command. + + With ``-scope`` enable/disable waveform tracing for the specified scope + (or wildcard with '\*' or '?'), and optional ``--levels`` number of + levels below. These controls only operate after other + file/line/module-based controls have indicated the signal should be + traced. Matching is performed on the shortest prefix first, such that + ``tracing_on -scope "a.b" tracing_off -scope "a"`` will turn it on for + "a.b" and off for everything else "a.*". + + With ``-levels`` (used with ``-scope``), the number of levels below that + scope which the rule is to match, where 0 means all levels below, 1 the + exact level as the provided scope, and 2 means an additional level of + children below the provided scope, etc. + +.. option:: verilator_lib -module "" + + Internal use only. Marks the specified module as being a stub for a library + created by :vlopt:`--lib-create` (including when created with + :vlopt:`--hierarchical`). Required for special internal processing. diff --git a/docs/guide/copyright.rst b/docs/guide/copyright.rst index 0268b6ab8..5b9405420 100644 --- a/docs/guide/copyright.rst +++ b/docs/guide/copyright.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ********* @@ -7,7 +7,7 @@ Copyright The latest version of Verilator is available from https://verilator.org. -Copyright 2003-2026 by Wilson Snyder. This program is free software; you +Copyright 2003-2026 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/docs/guide/deprecations.rst b/docs/guide/deprecations.rst index e053befa1..b22282bf5 100644 --- a/docs/guide/deprecations.rst +++ b/docs/guide/deprecations.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Deprecations @@ -16,14 +16,3 @@ C++14 compiler support (Although this date has expired, this change is currently on hold until the Ubuntu LTS versions of GCC and clang use C++20 by default, estimated May 2028.) - -XML output - Verilator currently supports XML parser output (enabled with - `--xml-only`). Support for `--xml-*` options will be deprecated no - sooner than January 2026. - -`--make cmake` - The `--make cmake` options is deprecated and will be removed no sooner - than January 2026. Use `--make json` instead. Note that the CMake - integration shipping with Verilator (verilator-config.mk) already uses - `--make json` so no changes are necessary if using that. diff --git a/docs/guide/environment.rst b/docs/guide/environment.rst index 35481e063..bae80b97b 100644 --- a/docs/guide/environment.rst +++ b/docs/guide/environment.rst @@ -1,6 +1,8 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +.. _Environment: + Environment =========== @@ -89,6 +91,20 @@ associated programs. If set, the command to run when using the :vlopt:`--gdb` option, such as "ddd". If not specified, it will use "gdb". +.. option:: VERILATOR_NUMA_STRATEGY + + If set, controls NUMA assignment strategy for Verilator's thread pool + for Verilated simulations at runtime. + Possible values are: + + * Empty(``""``) or ``"default"``: Enables NUMA assignment that prioritizes + assigning Verilator threads to physical cores. + + * ``"none"``: Disables NUMA assignment. Let the operating system handle + thread scheduling. + + Other values may be supported in future releases. + .. option:: VERILATOR_ROOT The ``VERILATOR_ROOT`` environment variable is used in several places: diff --git a/docs/guide/example_binary.rst b/docs/guide/example_binary.rst index ecca83049..fd36fe8ce 100644 --- a/docs/guide/example_binary.rst +++ b/docs/guide/example_binary.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _example create-binary execution: diff --git a/docs/guide/example_cc.rst b/docs/guide/example_cc.rst index 007645078..2a8384e85 100644 --- a/docs/guide/example_cc.rst +++ b/docs/guide/example_cc.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _example c++ execution: diff --git a/docs/guide/example_common_install.rst b/docs/guide/example_common_install.rst index a9bd788a8..0e38fa6ff 100644 --- a/docs/guide/example_common_install.rst +++ b/docs/guide/example_common_install.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 First you need Verilator installed, see :ref:`Installation`. In brief, if diff --git a/docs/guide/example_dist.rst b/docs/guide/example_dist.rst index 5a2aad40d..f3e1765f5 100644 --- a/docs/guide/example_dist.rst +++ b/docs/guide/example_dist.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _examples in the distribution: diff --git a/docs/guide/example_sc.rst b/docs/guide/example_sc.rst index 4d236f582..349645080 100644 --- a/docs/guide/example_sc.rst +++ b/docs/guide/example_sc.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _example systemc execution: diff --git a/docs/guide/examples.rst b/docs/guide/examples.rst index da378c313..5e0b2e260 100644 --- a/docs/guide/examples.rst +++ b/docs/guide/examples.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _examples: diff --git a/docs/guide/exe_sim.rst b/docs/guide/exe_sim.rst index c8f686646..fe916c089 100644 --- a/docs/guide/exe_sim.rst +++ b/docs/guide/exe_sim.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _simulation runtime arguments: @@ -123,3 +123,11 @@ Options: .. option:: +verilator+version Displays program version and exits. + +.. option:: +verilator+wno+unsatconstr+ + + Disable unsatisfied constraint warnings at simulation runtime. When set to + 1, warnings about unsatisfied constraints during ``randomize()`` calls will + not be displayed. Defaults to 0 (warnings enabled). This can also be + controlled via the C++ API using + ``Verilated::threadContextp()->warnUnsatConstr(false)``. diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index b5e9a0edd..e3d434fa4 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =================== @@ -662,6 +662,10 @@ Summary: Rarely needed. Do not apply the DFG optimizer before inlining. +.. option:: -fno-dfg-push-down-sels + + Rarely needed. Disable DFG select/concatenation optimization. + .. option:: -fno-dfg-scoped Rarely needed. Do not apply the DFG optimizer across module scopes. @@ -1069,8 +1073,12 @@ Summary: Generates a script for the specified build tool. - Supported values are ``gmake`` for GNU Make, or ``cmake`` for CMake, or - ``json`` to create a JSON file to feed other build tools. + Supported values are ``gmake`` for GNU Make, or ``json`` to create a + JSON file to feed other build tools. + + Verilator also supports building with CMake, but CMakeLists.txt + under-the-covers uses the ``--make json`` output format. There was a + native ``--make cmake`` but it was removed in Version 5.046. Multiple options can be specified together. If no build tool is specified, gmake is assumed. The executable of gmake can be configured @@ -1508,6 +1516,14 @@ Summary: improve C++ compilation time on designs where these sequences are common; however, the effect on model performance requires benchmarking. +.. option:: --replication-limit + + Set the limit for replication concatenation (e.g. {1024{1'b1}}). Also applies + to unsized literals (e.g. '0). + + This option is on by default with a value of 8k. To disable, pass with a + value of 0. + .. option:: --report-unoptflat Enable extra diagnostics for :option:`UNOPTFLAT` warnings. This @@ -1586,6 +1602,23 @@ Summary: Specifies SystemC output mode; see also :vlopt:`--cc` option. +.. option:: --sched-zero-delay + +.. option:: --no-sched-zero-delay + + Specifies if the generated code should support ``#0`` delays with full IEEE + 1800 standard scheduling semantics. Full ``#0`` support has a simulation + performance cost. If :vlopt:`--sched-zero-delay` is used, the generated code + will fully support ``#0`` delays. If :vlopt:`--no-sched-zero-delay` is used, + the generated code will not support ``#0` delays, and simulation will fail + at runtime if a ``#0`` delay is executed. If no option is given, Verilator + will generate code with proper ``#0`` support if the input contains either a + ``#0``, or a ``#(expression)`` with a delay value unknown at compile time. + + Option :vlopt:`--no-sched-zero-delay` can be used if the input contains + ``#0`` delays, but they are known to be not executed at runtime. This can + improve simulation performance. + .. option:: --skip-identical .. option:: --no-skip-identical @@ -1729,7 +1762,7 @@ Summary: :vlopt:`--trace-vcd` instead. Using :vlopt:`--trace` without :vlopt:`--trace-fst` nor - :vlopt:`--trace-fst` requests VCD traces. + :vlopt:`--trace-saif` requests VCD traces. Using :vlopt:`--trace` :vlopt:`--trace-fst` requests FST traces. @@ -2198,23 +2231,16 @@ Summary: .. option:: --xml-only - Create XML output only, do not create any other output. + Removed in 5.046. - The XML format is intended to be used to leverage Verilator's parser and - elaboration to feed to other downstream tools. - - .. note:: - - This feature is deprecated in favor of :vlopt:`--json-only`. + Created XML output only, did not create any other output. .. option:: --xml-output - Specifies the filename for the XML output file. Using this option - automatically sets :vlopt:`--xml-only`. + Removed in 5.046. - .. note:: - - This feature is deprecated in favor of :vlopt:`--json-only`. + Specified the filename for the XML output file. Using this option + automatically set :vlopt:`--xml-only`. .. option:: -y @@ -2229,344 +2255,3 @@ Summary: user-specified directories. This allows '-y "$(pwd)"' to be used if absolute filenames are desired for error messages instead of relative filenames. - - -.. _verilator control files: - -======================= -Verilator Control Files -======================= - -In addition to the command line, warnings and other features for the -:command:`verilator` command may be controlled with Verilator Control -Files, not to be confused with IEEE Configurations blocks -(`config...endconfig`). Typically named with the `.vlt` extension, what -makes it a Verilator Control File is the :option:`\`verilator_config` -directive. These files, when named `.vlt`, are read before source code -files; if this behavior is undesired, name the control file with a `.v` or -other suffix. - -An example: - -.. code-block:: sv - - `verilator_config - lint_off -rule WIDTH - lint_off -rule CASEX -file "silly_vendor_code.v" - -This disables WIDTH warnings globally, and CASEX for a specific file. - -Verilator control files are fed through the normal Verilog preprocessor -prior to parsing, so "\`ifdef", "\`define", and comments may be used as if -the control file was standard Verilog code. - -Note that file or line-specific control only applies to files read after -the control file. It is therefore recommended to pass the control file to -Verilator as the first file. - -The grammar of control commands is as follows: - -.. option:: `verilator_config - - Take the remaining text and treat it as Verilator Control File commands. - See :ref:`Verilator Control Files`. - -.. option:: clock_enable -module "" -var "" - - Deprecated and has no effect (ignored). - - In versions before 5.000: - - Indicates that the signal is used to gate a clock, and the user takes - responsibility for ensuring there are no races related to it. - - Same as :option:`/*verilator&32;clock_enable*/` metacomment. - - - .. t_dist_docs_style ignore no_clocker - -.. option:: clocker -module "" [-function ""] -var "" - -.. option:: clocker -module "" [-task ""] -var "" - -.. option:: no_clocker -module "" [-function ""] -var "" - -.. option:: no_clocker -module "" [-task ""] -var "" - - Deprecated and has no effect (ignored). - - In versions before 5.042: - - Indicates whether the signal is used as clock or not. Verilator uses - this information to mark the signal and any derived signals as clocker. - See :vlopt:`--clk`. - - Same as :option:`/*verilator&32;clocker*/` metacomment. - -.. option:: coverage_block_off -file "" -line - -.. option:: coverage_block_off -module "" -block "" - - Specifies the entire begin/end block should be ignored for coverage - analysis purposes. It can either be specified as a named block or as a - filename and line number. - - Same as :option:`/*verilator&32;coverage_block_off*/` metacomment. - -.. option:: coverage_off [-file "" [-lines [ - ]]] - -.. option:: coverage_on [-file "" [-lines [ - ]]] - - Enable/disable coverage for the specified filename (or wildcard with - '\*' or '?', or all files if omitted) and range of line numbers (or all - lines if omitted). Often used to ignore an entire module for coverage - analysis purposes. - -.. option:: forceable -module "" -var "" - - Generate public `__VforceEn` and `__VforceVal` signals - that can force/release a signal from C++ code. The force control - signals are created as :option:`public_flat` signals. - - Same as :option:`/*verilator&32;forceable*/` metacomment. - -.. option:: full_case -file "" -lines - - Same as ``//synthesis full_case``. When these synthesis directives - are discovered, Verilator will either formally prove the directive to be - true, or, failing that, will insert the appropriate code to detect - failing cases at simulation runtime and print an "Assertion failed" - error message. - -.. option:: hier_block -module "" - - Specifies that the module is an unit of hierarchical Verilation. Note - that the setting is ignored unless the :vlopt:`--hierarchical` option is - specified. See :ref:`Hierarchical Verilation`. - -.. option:: hier_params -module "" - - Specifies that the module contains parameters a :vlopt:`--hierarchical` block. This option - is used internally to specify parameters for deparametrized hier block instances. - This option should not be used directly. - See :ref:`Hierarchical Verilation`. - -.. option:: hier_workers -hier-dpi "" -workers - - Specifies how many threads need to be used for scheduling hierarchical DPI - tasks. This data is inserted internally during :vlopt:`--hierarchical`, - based on value specified in `hier_workers -module`. This option - should not be used directly. See :ref:`Hierarchical Verilation`. - -.. option:: hier_workers -module "" -workers - - Specifies how many threads need to be used for scheduling given module with - :option:`/*verilator&32;hier_block*/` metacomment. This number needs to be - smaller than :vlopt:`--threads` to fit in a thread schedule. - See :ref:`Hierarchical Verilation`. - -.. option:: inline -module "" - - Specifies the module may be inlined into any modules that use this - module. Same as :option:`/*verilator&32;inline_module*/` metacomment. - - .. t_dist_docs_style ignore no_inline - -.. option:: no_inline -module "" - - Specifies the module should not be inlined into any modules that use - this module. Same as :option:`/*verilator&32;no_inline_module*/` - metacomment. - -.. option:: no_inline [-module ""] -function "" - -.. option:: no_inline [-module ""] -task "" - - Specify the function or task should not be inlined into where it is - used. This may reduce the size of the final executable when a task is - used a very large number of times. For this flag to work, the task and - tasks below it must be pure; they cannot reference any variables outside - the task itself. - - Same as :option:`/*verilator&32;no_inline_task*/` metacomment. - -.. option:: isolate_assignments -module "" -function "" - -.. option:: isolate_assignments -module "" [-function ""] -var "" - -.. option:: isolate_assignments -module "" [-task ""] -var "" - - Used to indicate that the assignments to this signal in any blocks - should be isolated into new blocks. Same as - :option:`/*verilator&32;isolate_assignments*/` metacomment. - -.. option:: lint_off [-rule ] [-file "" [-lines [ - ]]] - -.. option:: lint_off [-rule ] [-file ""] [-contents ""] [-match ""] - -.. option:: lint_on [-rule ] [-file "" [-lines [ - ]]] - - Enable/disables the specified lint warning, in the specified filename - (or wildcard with '\*' or '?', or all files if omitted) and range of - line numbers (or all lines if omitted). - - If the ``-rule`` is omitted, all lint warnings (see list in - :vlopt:`-Wno-lint`) are enabled/disabled. - - If ``-contents`` is provided, the input files must contain the given - wildcard (with '\*' or '?'), and are waived in case they match, provided - the ``-rule``, ``-file``, and ``-contents`` also match. The wildcard - should be designed to match a single line; it is unspecified if the - wildcard is allowed to match across multiple lines. The input contents - does not include :vlopt:`--std <--no-std>` standard files, nor control - files (with ``verilator_config``). Typical use for this is to match a - version number present in the Verilog sources, so that the waiver will - only apply to that version of the sources. - - If ``-match`` is provided, the linter warnings are matched against the - given wildcard (with '\*' or '?'), and are waived in case they match, - provided the ``-rule``, ``-file``, and ``-contents`` also match. The - wildcard is compared across the entire multi-line message; see - :vlopt:`--waiver-multiline`. - - When there are overlapping conflicting lint_on/lint_off directives, they - are resolved in the following priority order: - - * All lint_on/lint_off without a ``-file``, or with a ``-file "\*"``, - are processed in order of parsing. - * All lint_on/lint_off with ``-file "non-\*"`` are processed in order of - parsing. - * All lint_off with ``--match`` in order of parsing. - - If a warning is disabled with lint_off, it will not be printed, even if - the source contains a lint_on metacomment. The control file directives - and metacomments are interpreted separately and do not interact. A - warning is emitted only if not disabled either in a control file or via - metacomments. - - Before version 4.026, ``-rule`` was named ``-msg``, and - ``-msg`` remained a deprecated alias until Version 5.000. - -.. option:: parallel_case -file "" -lines - - Same as ``//synthesis parallel_case``. When these synthesis - directives are discovered, Verilator will either formally prove the - directive to be true, or, failing that, will insert the appropriate code - to detect failing cases at simulation runtime and print an "Assertion - failed" error message. - -.. option:: profile_data -hier-dpi "" -cost - - Internal profiling data inserted during :vlopt:`--hierarchical`; specifies - execution cost of a hierarchical DPI wrappers for modules with - :option:`/*verilator&32;hier_block*/` metacomment. See - :ref:`Hierarchical Verilation`. - -.. option:: profile_data -mtask "" -cost - - Feeds profile-guided optimization data into the Verilator algorithms in - order to improve model runtime performance. This option is not expected - to be used by users directly. See :ref:`Thread PGO`. - -.. option:: public [-module ""] [-task/-function ""] [-var ""] - -.. option:: public_flat [-module ""] [-task/-function ""] [(-param | -port | -var) ""] - -.. option:: public_flat_rd [-module ""] [-task/-function ""] [(-param | -port | -var) ""] - -.. option:: public_flat_rw [-module ""] [-task/-function ""] [(-param | -port | -var) ""] ["@(edge)"] - - Sets the specified signal to be public. Same as - :option:`/*verilator&32;public*/` or - :option:`/*verilator&32;public_flat*/`, etc., metacomments. See also - :ref:`VPI Example`. - - Using ``-port`` only selects matching ports, ``-param`` matches - parameters and localparams, and ``-var`` matches any signal (including - ports, parameters, and regular variables or nets). In all three, the - following ```` can contain ``*`` and ``?`` wildcard - characters that match any substring or any single character respectively. - -.. option:: sc_biguint -module "" -var "" - - Sets the input/output signal to be of ``sc_biguint<{width}>`` type. - This metacomment works for signals of any width. - Same as :option:`/*verilator&32;sc_biguint*/` metacomment. - -.. option:: sc_bv -module "" -var "" - - Sets the port to be of ``sc_bv<{width}>`` type, instead of bool, - uint32_t, or uint64_t. Same as :option:`/*verilator&32;sc_bv*/` - metacomment. - -.. option:: sformat [-module ""] [-function ""] -var "" - -.. option:: sformat [-module ""] [-task ""] -var "" - - Must be applied to the final argument of type ``input string`` of a - function or task to indicate that the function or task should pass all - remaining arguments through $sformatf. This allows the creation of DPI - functions with $display-like behavior. See the - :file:`test_regress/t/t_dpi_display.v` file for an example. - - Same as :option:`/*verilator&32;sformat*/` metacomment. - -.. option:: split_var [-module ""] [-function ""] -var "" - -.. option:: split_var [-module ""] [-task ""] -var "" - - Break the variable into multiple pieces typically to resolve UNOPTFLAT - performance issues. Typically the variables to attach this to are - recommended by Verilator itself; see :option:`UNOPTFLAT`. - - Same as :option:`/*verilator&32;split_var*/` metacomment. - -.. option:: timing_off [-file "" [-lines [ - ]]] - -.. option:: timing_on [-file "" [-lines [ - ]]] - - Enables/disables timing constructs for the specified file and lines. - When disabled, all timing control constructs in the specified source - code locations are ignored the same way as with the - :option:`--no-timing`, and code:`fork`/``join*`` blocks are - converted into ``begin``/``end`` blocks. - - Similar to :option:`/*verilator&32;timing_on*/`, - :option:`/*verilator&32;timing_off*/` meta-comments, but interpreted - independently. If either a control file, or meta-comments disable timing - constructs, they will be disabled. - - .. t_dist_docs_style ignore tracing_on - -.. option:: tracing_off [-file "" [-lines [ - ]]] - -.. option:: tracing_on [-file "" [-lines [ - ]]] - -.. option:: tracing_off [-scope "" [-levels ]] - -.. option:: tracing_on [-scope "" [-levels ]] - - Enable/disable waveform tracing for all future signals declared in - all files. - - With ``-file``, enable/disable waveform tracing in the specified - filename (or wildcard with '\*' or '?'), and ``-line`` range of line - numbers (or all lines if omitted). - - For tracing_off with ``-file``, instances below any module in the - files/ranges specified will also not be traced. To overcome this - feature, use tracing_on on the upper module declaration and on any - cells, or use the ``-scope`` flavor of the command. - - With ``-scope`` enable/disable waveform tracing for the specified scope - (or wildcard with '\*' or '?'), and optional ``--levels`` number of - levels below. These controls only operate after other - file/line/module-based controls have indicated the signal should be - traced. Matching is performed on the shortest prefix first, such that - ``tracing_on -scope "a.b" tracing_off -scope "a"`` will turn it on for - "a.b" and off for everything else "a.*". - - With ``-levels`` (used with ``-scope``), the number of levels below that - scope which the rule is to match, where 0 means all levels below, 1 the - exact level as the provided scope, and 2 means an additional level of - children below the provided scope, etc. diff --git a/docs/guide/exe_verilator_coverage.rst b/docs/guide/exe_verilator_coverage.rst index 030daee60..23bbd6b8f 100644 --- a/docs/guide/exe_verilator_coverage.rst +++ b/docs/guide/exe_verilator_coverage.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator_coverage @@ -79,18 +79,18 @@ verilator_coverage Arguments .. code-block:: - 100000 input logic a; // Begins with whitespace, because - // number of hits (100000) is above the min. - +100000 point: comment=a // Begins with +, because - // number of hits (100000) is above the min. - %000000 input logic b; // Begins with %, because - // number of hits (0) is below the min. - -000000 point: comment=b // Begins with -, because - // number of hits (0) is below the min. - ~000010 if (cyc!=0) begin // Begins with ~, because - // branches are below and above the min. - +000010 point: comment=if // The if branch is above the min. - -000000 point: comment=else // The else branch is below the min. + 100000 input logic a; // Begins with whitespace, because + // number of hits (100000) is above the min. + +100000 point: type=line comment=a // Begins with +, because + // number of hits (100000) is above the min. + %000000 input logic b; // Begins with %, because + // number of hits (0) is below the min. + -000000 point: type=line comment=b // Begins with -, because + // number of hits (0) is below the min. + ~000010 if (cyc!=0) begin // Begins with ~, because + // branches are below and above the min. + +000010 point: type=branch comment=if // The if branch is above the min. + -000000 point: type=branch comment=else // The else branch is below the min. .. option:: --annotate-all @@ -119,9 +119,9 @@ verilator_coverage Arguments .. code-block:: 100000 input logic a, b, c; - +100000 point: comment=a // These lines are only shown - +200000 point: comment=b // with option --annotate-points - +300000 point: comment=c // enabled. + +100000 point: type=line comment=a // These lines are only shown + +200000 point: type=line comment=b // with option --annotate-points + +300000 point: type=line comment=c // enabled. This option should be used together with :option:`--annotate`. diff --git a/docs/guide/exe_verilator_gantt.rst b/docs/guide/exe_verilator_gantt.rst index 2cf398b90..5b45969f9 100644 --- a/docs/guide/exe_verilator_gantt.rst +++ b/docs/guide/exe_verilator_gantt.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator_gantt diff --git a/docs/guide/exe_verilator_profcfunc.rst b/docs/guide/exe_verilator_profcfunc.rst index 780fe4326..c79f86436 100644 --- a/docs/guide/exe_verilator_profcfunc.rst +++ b/docs/guide/exe_verilator_profcfunc.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator_profcfunc diff --git a/docs/guide/executables.rst b/docs/guide/executables.rst index 6a50c7bc0..ac4e3f85e 100644 --- a/docs/guide/executables.rst +++ b/docs/guide/executables.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ********************************* diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index a5757e4c7..0e944860e 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =================== @@ -207,6 +207,14 @@ or "`ifdef`"'s may break other tools. 5 digits per the C standard. This extension was standardized into 1800-2009. +.. option:: $get_initial_random_seed() + + Returns an integer with the initial random seed used for the simulation. + This is the value provided via the :vlopt:`+verilator+seed+\` + runtime option. If no seed is specified, it returns the default + initialization seed (typically 0). This is not defined by IEEE + 1800-2023, but most simulators support it. + .. option:: $stacktrace Called as a task, print a stack trace. Called as a function, return a diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst index f71b70f4e..ec55a9a9c 100644 --- a/docs/guide/faq.rst +++ b/docs/guide/faq.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ****************************** diff --git a/docs/guide/files.rst b/docs/guide/files.rst index 6c4638e1d..2e5fa2225 100644 --- a/docs/guide/files.rst +++ b/docs/guide/files.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ***** @@ -112,8 +112,6 @@ In specific debug and other modes, it also creates: - JSON tree information (from --json-only) * - *{prefix}*.tree.meta.json - JSON tree metadata (from --json-only) - * - *{prefix}*.xml - - XML tree information (from --xml) * - *{prefix}*\ __cdc.txt - Clock Domain Crossing checks (from --cdc) * - *{prefix}*\ __stats.txt diff --git a/docs/guide/index.rst b/docs/guide/index.rst index 414c18bdc..5df45c271 100644 --- a/docs/guide/index.rst +++ b/docs/guide/index.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################### @@ -32,6 +32,7 @@ Verilator User's Guide languages.rst extensions.rst + control.rst executables.rst warnings.rst files.rst diff --git a/docs/guide/install-cmake.rst b/docs/guide/install-cmake.rst index 7961e857d..ac4217b73 100644 --- a/docs/guide/install-cmake.rst +++ b/docs/guide/install-cmake.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _cmakeinstallation: diff --git a/docs/guide/install.rst b/docs/guide/install.rst index 0198f496f..989c581c6 100644 --- a/docs/guide/install.rst +++ b/docs/guide/install.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _installation: diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst index d7be954fc..262a58271 100644 --- a/docs/guide/languages.rst +++ b/docs/guide/languages.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 *************** @@ -121,11 +121,6 @@ as well as all flavors of ``fork``. Compiling a Verilated design that uses these features requires a compiler with C++20 coroutine support, e.g. Clang 5, GCC 10, or newer. -``#0`` delays cause Verilator to issue the :option:`ZERODLY` warning, as -they work differently than described in the LRM. They do not schedule -process resumption in the Inactive region, though the process will get -resumed in the same time slot. - Rising/falling/turn-off delays are currently unsupported and cause the :option:`RISEFALLDLY` warning. @@ -528,6 +523,12 @@ $readmemb, $readmemh specification do not include support for readmem to multi-dimensional arrays. +$stacktrace + The `$stacktrace` system call will show the C++ stack, not the Verilog + call stack, though the function names typically correlate. To get + symbolic names, the model must have debug symbols, e.g. compile with + `-CFLAGS -ggdb -LDFLAGS -ggdb -LDFLAGS -rdynamic`. + $test$plusargs, $value$plusargs Supported, but the instantiating C++/SystemC wrapper must call diff --git a/docs/guide/overview.rst b/docs/guide/overview.rst index fa5782ee0..5ffe52ed2 100644 --- a/docs/guide/overview.rst +++ b/docs/guide/overview.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ******** diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst index 5ed589f20..fd92bb1ba 100644 --- a/docs/guide/simulating.rst +++ b/docs/guide/simulating.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _simulating: @@ -29,7 +29,7 @@ For example: - S i m u l a t i o n R e p o r t: Verilator ... - Verilator: End at simtime 123 ns; walltime 1234.001 s; speed 123 ns/s - - Verilator: cpu 22.001 s on 4 threads; alloced 123 MB + - Verilator: cpu 22.001 s on 4 threads; allocated 123 MB The information in this report is: @@ -63,7 +63,7 @@ The information in this report is: Number of simultaneous threads used. -.. describe:: "alloced 123 MB" +.. describe:: "allocated 123 MB" Total memory used during simulation in megabytes. @@ -85,8 +85,11 @@ above documentation for these options. If using Verilated multithreaded, consider overriding Verilator's default thread-to-processor assignment by using ``numactl``; see -:ref:`Multithreading`. Also, consider using profile-guided optimization; -see :ref:`Thread PGO`. +:ref:`Multithreading`. If your OS can handle thread assignment for your +design and hardware well, consider disabling Verilator's NUMA assignment by +setting the :vlopt:`VERILATOR_NUMA_STRATEGY` environment variable to +``none``; see :ref:`Environment`. Also, consider using profile-guided +optimization; see :ref:`Thread PGO`. Minor Verilog code changes can also give big wins. You should not have any :option:`UNOPTFLAT` warnings from Verilator. Fixing these warnings can @@ -292,12 +295,12 @@ combination was hit. Note that individual lines are not mutually exclusive. .. code-block:: %000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); - -000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t - -000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t - -000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t - -000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t - -000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t - -000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t + -000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t + -000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t + -000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t + -000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t + -000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t + -000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t .. _suppressing coverage: diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst index 39d2211c8..377686548 100644 --- a/docs/guide/verilating.rst +++ b/docs/guide/verilating.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ********** @@ -285,6 +285,13 @@ schedules threads using multiple hyperthreads within the same physical core. If there is no affinity already set, on Linux only, Verilator attempts to set thread-to-processor affinity in a reasonable way. +Some newer Linux kernels handle thread assignment well. If running +Verilator on such a system, automatic thread affinity may not be +beneficial and may even reduce performance. In this case, environment +variable :vlopt:`VERILATOR_NUMA_STRATEGY` may be set to ``none`` to +disable automatic thread affinity. For more information, refer to +:ref:`Environment`. + For best performance, use the :command:`numactl` program to (when the threading count fits) select unique physical cores on the same socket. The same applies for :vlopt:`--trace-threads` as well. @@ -311,6 +318,15 @@ adjusted if you want another simulator to use, e.g., socket 1, or if you Verilated with a different number of threads. To see what CPUs are actually used, use :vlopt:`--prof-exec`. +On Systems with multiple L3 clusters per socket (e.g., AMD EPYC or Ryzen), +consider using :command:`lstopo` to determine the L3 cluster topology of +the current system and :command:`numactl` to bind CPUs within a single L3 +cluster. This can improve performance for minimal communication latency +between threads. Sometimes, for model's thread counts that are more than +the core count per L3 cluster, using SMTs (hyperthreads) within a single L3 +cluster can have better performance than spreading across multiple L3 +clusters using physical cores only. Experimentation is recommended to find +the best settings for underlying hardware and model characteristics. Multithreaded Verilog and Library Support ----------------------------------------- @@ -564,7 +580,7 @@ will print a report to stdout summarizing the build. For example: - Verilator: Built from 354 MB sources in 247 modules, into 74 MB in 89 C++ files needing 0.192 MB - Verilator: Walltime 26.580 s (elab=2.096, cvt=18.268, - bld=2.100); cpu 26.548 s on 1 threads; alloced 2894.672 MB + bld=2.100); cpu 26.548 s on 1 threads; allocated 2894.672 MB The information in this report is: @@ -619,7 +635,7 @@ The information in this report is: Number of simultaneous threads used. -.. describe:: "alloced 123 MB" +.. describe:: "allocated 123 MB" Total memory used during build by Verilator executable (excludes :vlopt:`--build` compiler's usage) in megabytes. diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index fb30d158c..2e38afff8 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2026 by Wilson Snyder. +.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =================== @@ -467,7 +467,7 @@ List Of Warnings .. TODO better example Warns that the code is comparing a value in a way that will always be - constant. For example, ``X > 1`` will always be true when X is a single + constant. For example, ``X > 1`` will always be false when X is a single bit wide. Ignoring this warning will only suppress the lint check; it will @@ -1022,13 +1022,20 @@ List Of Warnings .. option:: IMPLICITSTATIC Warns that the lifetime of a task or a function was not provided and so - was implicitly set to static. The warning is suppressed when no - variables inside the task or a function are assigned to. + an enclosed variable was implicitly set to static. The warning is + suppressed when no variables inside the task or a function are assigned + to. + + Also warns that a process (e.g. "always" or "initial" statement) has + enclosed variables that were implicitly set to static. + + IEEE 1800-2023 6.21 requires this error, though Verilator treats it by + default as a warning. This is a warning because the static default differs from C++, differs from class member function/tasks. Static is a more dangerous default - then automatic as static prevents the function from being reentrant, - which may be a source of bugs, and/or performance issues. + then automatic as static prevents the function or process from being + reentrant, which may be a source of bugs, and/or performance issues. If the function is in a module, and does not require static behavior, change it to "function automatic". @@ -1123,6 +1130,16 @@ List Of Warnings simulate correctly. +.. option:: INSIDETRUE + + Warns that an ``inside`` expression contains a range with unbounded + values on both sides (``[$:$]``), which is always true. This is likely + a coding mistake. + + Ignoring this warning will only suppress the lint check; it will + simulate correctly. + + .. option:: LATCH .. TODO better example @@ -1965,13 +1982,10 @@ List Of Warnings .. option:: STATICVAR - Warns that a static variable declared in a loop with declaration assignment - was converted to automatic. Often such variables were intended to - instead be declared "automatic". + Historical, never issued since version 5.046. - Ignoring this warning may make Verilator differ from other simulators, - which will treat the variable as static. Verilator may in future versions also - treat the variable as static. + Warned that a static variable was declared in a loop with declaration + assignment, and Verilator converted it to an "automatic". .. option:: STMTDLY @@ -2273,6 +2287,20 @@ List Of Warnings unpacked struct/array inside a packed struct/array. +.. option:: UNSATCONSTR + + Warns that a ``randomize()`` call failed because one or more constraints + could not be satisfied. This warning is issued at simulation runtime + when the SMT solver determines that the combination of constraints is + unsatisfiable. + + Each unsatisfied constraint is reported with its source location to help + identify conflicting constraints. + + This warning can be disabled by setting the runtime option + ``+verilator+wno+unsatconstr+1`` or by calling + ``Verilated::threadContextp()->warnUnsatConstr(false)`` in C++. + .. option:: UNSIGNED .. TODO better example @@ -2561,6 +2589,21 @@ List Of Warnings .. option:: ZERODLY + Since version 5.046: + + Issued if neither :vlopt:`--sched-zero-delay`, nor + :vlopt:`--sched-zero-delay` is used on the command line, and the input does + not contain a compile time known ``#0`` delay, but does contain a + ``#(expressin)`` where the delay value cannot be determined at compile time. + Passing :vlopt:`--no-sched-zero-delay` can improve runtime performance if + variable delays are all known to be non-zero at runtime. + + Also issued if :vlopt:`--no-sched-zero-delay` is used on the command line, + but the input contains a compile time known ``#0`` delay. This is safe to + ignore if the reported delay is known to be not executed at runtime. + + Before version 5.046: + Warns that `#0` delays do not schedule the process to be resumed in the Inactive region. Such processes do get resumed in the same time slot somewhere in the Active region. Issued only if Verilator is run with the diff --git a/docs/internals.rst b/docs/internals.rst index b7ff0975b..37deff588 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -593,15 +593,17 @@ object. This class manages processes that await events (triggers). There is one such object per each trigger awaited by coroutines. Coroutines ``co_await`` -this object's ``trigger`` function. They are stored in two stages - -`uncommitted` and `ready`. First, they land in the `uncommitted` stage, and -cannot be resumed. The ``resume`` function resumes all coroutines from the -`ready` stage and moves `uncommitted` coroutines into `ready`. The -``commit`` function only moves `uncommitted` coroutines into `ready`. +this object's ``trigger`` function. They are stored in three stages - +`awaiting`, `fired` and `toResume`. First, they land in the `awaiting` stage, and +cannot be resumed. The ``ready`` function moves all coroutines from the +`awaiting` stage into the `fired` stage. The ``moveToResumeQueue`` function moves +`fired` coroutines into `toResume`. Finally, function `resume` resumes +all coroutines from the `toResume` stage. -This split is done to avoid self-triggering and triggering coroutines -multiple times. See the `Scheduling with timing` section for details on how -this is used. +This split is done to avoid self-triggering, triggering coroutines +multiple times and triggering coroutines in the same iteration +they were suspended. See the `Scheduling with timing` section +for details on how this is used. ``VlDynamicTriggerScheduler`` ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -719,16 +721,35 @@ in that process. When ordering code using ``V3Order``, these triggers are provided as external domains of these variables. This ensures that the necessary combinational logic is triggered after a coroutine resumption. +Every call to a `VlTriggerScheduler`'s `trigger()` method is preempt by +a call to a proper `__VbeforeTrig` function which evaluates all the necessary +triggers so, the information about order of suspension/resumption is not lost. +The triggers necessary to evaluate are ones dependent on the same events +as the `trigger()` - e.g.: if `triggers()` awaits for event `a` or `b`, then +every trigger that depends on any of those shall be evaluated. If they wouldn't +be evaluated and next coroutine after resumption would fire the event `a` then +it is impossible to get to know whether await or fire on event `a` was called +first - which is necessary to know. + There are two functions for managing timing logic called by ``_eval()``: -* ``_timing_commit()``, which commits all coroutines whose triggers were +* ``_timing_ready()``, which commits all coroutines whose triggers were not set in the current iteration, * ``_timing_resume()``, which calls `resume()` on all trigger and delay schedulers whose triggers were set in the current iteration. -Thanks to this separation, a coroutine awaiting a trigger cannot be -suspended and resumed in the same iteration, and it cannot be resumed -before it suspends. +Thanks to this separation a coroutine: +* awaiting a trigger cannot be suspended and resumed in the same iteration + (``test_regress/t/t_timing_eval_act.v``) - which is necessary to make + Verilator more predictable; this is the reason for introduction of 3rd stage + in `VlTriggerScheduler` and thanks to this it is guaranteed that downstream + logic will be evaluated before resumption (assuming that the coroutine wasn't + already triggered in previous iteration); +* cannot be resumed before it is suspended - + ``test_regress/t/t_event_control_double_excessive.v``; +* firing cannot cannot be lost + (``test_regress/t/t_event_control_double_lost.v``) - which is possible when + triggers are not evaluated right before awaiting. All coroutines are committed and resumed in the 'act' eval loop. With timing features enabled, the ``_eval()`` function takes this form: @@ -1946,35 +1967,26 @@ for programmatic processing (e.g. with `astsee `_). To enable this dump format, use :vlopt:`--dump-tree-json` or :vlopt:`--json-only`. -Structure: +The potential fields in the JSON dump can be determined by searching for +JSON in the `src/V3AstNodes.cpp` source file. The dump will only include +booleans that are true, omitting those that are false. + +Structure example: :: { - /* Attributes that are common to all types of nodes */ + /* Attributes that are common to most types of nodes */ "type": "VAR", "name": "cyc", + "verilogName": "cyc", /* By default addresses and filenames use short/stable ids rather than real value */ "addr": "(H)", "loc": "a,25:12,26:15", /* "fileid,firstLine:firstCol,lastLine:endCol" (endCol is right exclusive) */ "editNum": 602, - /* Fields that are specific to AstVar nodes: */ + /* Some fields that are specific to AstVar nodes: */ "origName": "cyc", - "isSc": false, "ioDirection": "NONE", - "isConst": false, - "isPullup": false, - "isPulldown": false, - "isUsedClock": false, - "isSigPublic": false, - "isLatched": false, - "isUsedLoopIdx": false, - "noReset": false, - "attrIsolateAssign": false, - "attrFileDescr": false, - "isDpiOpenArray": false, - "isFuncReturn": false, - "isFuncLocal": false, "attrClocker": "UNKNOWN", "lifetime": "NONE", "varType": "VAR", @@ -2645,10 +2657,11 @@ xsim_flags / xsim_flags2 / xsim_run_flags Distribution ============ -Copyright 2008-2026 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Verilator is free software; you can redistribute it and/or modify it under +the terms of either the GNU Lesser General Public License Version 3 or the +Perl Artistic License Version 2.0. +SPDX-FileCopyrightText: 2003-2026 Wilson Snyder SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png diff --git a/docs/security.rst b/docs/security.rst index 53bc500a3..4080bad92 100644 --- a/docs/security.rst +++ b/docs/security.rst @@ -1,4 +1,6 @@ .. for github, vim: syntax=reStructuredText +.. SPDX-FileCopyrightText: 2025-2026 Wilson Snyder +.. SPDX-License-Identifier: CC0-1.0 Security Policy =============== diff --git a/docs/spelling.txt b/docs/spelling.txt index 87cc53551..f883336d1 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -273,6 +273,7 @@ Laroche Laurens Lavino Leber +Leela Leendert Lem Lesik @@ -288,6 +289,7 @@ LteS Luca Lueker Luiza +Lun Lussier Lübeck MMD @@ -360,6 +362,7 @@ Ondrej Oron Oyvind PLI +Pakanati Palaniappan Patricio Peltonen @@ -413,6 +416,7 @@ Rufer Runtime Ruud Rystsov +Ryzen Rémi STandarD Salman @@ -476,7 +480,9 @@ Tarik Tariq Tejada Tengstrand +Tenstorrent Terpstra +Testorrent Thiede Thierry Thyer @@ -619,6 +625,7 @@ bitstoreal blackbox bokke bool +booleans brancoliticus buf bufif @@ -1081,6 +1088,7 @@ sc scalared sccache sccanf +sched seg setuphold sformat @@ -1089,6 +1097,7 @@ shareefj shortint shortreal signame +signedness sp specparam splitme @@ -1099,6 +1108,7 @@ src srcdir srcfile sscanf +stacktrace stderr stdin stdout @@ -1188,6 +1198,7 @@ unopt unoptflat unoptimizable unroller +unsatisfiable unsized unsup untyped diff --git a/docs/xml.rst b/docs/xml.rst deleted file mode 100644 index 1331abe27..000000000 --- a/docs/xml.rst +++ /dev/null @@ -1,78 +0,0 @@ -|Logo| - -*************************** -Verilator XML Output Format -*************************** - -Introduction -============ - -This document describes Verilator's XML output. For more general -information please see `verilator.org `__. - - -General -======= - -Verilator's XML output is enabled with the ``--xml-only`` flag. It contains -limited information about the elaborated design including files, modules, -instance hierarchy, logic and data types. There is no formal schema since -part of the structure of the XML document matches the compiled code which -would require the schema to describe legal SystemVerilog structure. The -intended usage is to enable other downstream tools to take advantage of -Verilator's parser. - - -Structure -========= - -The XML document consists of 4 sections within the top level -``verilator_xml`` element: - -````... ```` - This section contains a list of all design files read, including the - built-in constructs and the command line as their own entries. Each - ```` has an attribute ``id`` which is a short ASCII string unique - to that file. Other elements' ``loc`` attributes use this id to refer to - a particular file. - -````... ```` - All files containing Verilog module definitions are listed in this - section. This element's contents is a subset of the ```` - element's contents. - -````... ```` - The cells section of the XML document contains the design instance - hierarchy. Each instance is represented with the ```` element with - the following attributes: - - - ``loc``: The file id, first line number, last line number, first - column number and last column number of the identifier where the - module was instanced, separated by commas. - - - ``name``: The instance name. - - - ``submodname``: The module name uniquified with particular parameter - values (if any). - - - ``hier``: The full hierarchy path. - -````... ```` - The netlist section contains a number of ````... ```` - elements, each describing the contents of that module, and a single - ````... ```` element which lists all used types - used within the modules. Each type has a numeric ``id`` attribute that - is referred to by elements in the ```` elements using the - ``dtype_id`` attribute. - - -Distribution -============ - -Copyright 2020-2026 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. - -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png diff --git a/examples/cmake_hello_c/CMakeLists.txt b/examples/cmake_hello_c/CMakeLists.txt index 338cacc85..d346e95ba 100644 --- a/examples/cmake_hello_c/CMakeLists.txt +++ b/examples/cmake_hello_c/CMakeLists.txt @@ -5,8 +5,8 @@ # This is an example cmake script to build a verilog to systemc project # using cmake and verilator. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/cmake_hello_c/Makefile b/examples/cmake_hello_c/Makefile index a6bb88304..9e88ff560 100644 --- a/examples/cmake_hello_c/Makefile +++ b/examples/cmake_hello_c/Makefile @@ -6,8 +6,8 @@ # This makefile is here for testing the examples and should # generally not be added to a CMake project. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/cmake_hello_sc/CMakeLists.txt b/examples/cmake_hello_sc/CMakeLists.txt index 58d434439..444ef18be 100644 --- a/examples/cmake_hello_sc/CMakeLists.txt +++ b/examples/cmake_hello_sc/CMakeLists.txt @@ -5,8 +5,8 @@ # This is an example cmake script to build a verilog to SystemC project # using CMake and Verilator. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/cmake_hello_sc/Makefile b/examples/cmake_hello_sc/Makefile index df2a9bd52..a13e676bc 100644 --- a/examples/cmake_hello_sc/Makefile +++ b/examples/cmake_hello_sc/Makefile @@ -6,8 +6,8 @@ # This makefile is here for testing the examples and should # generally not be added to a CMake project. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/cmake_protect_lib/CMakeLists.txt b/examples/cmake_protect_lib/CMakeLists.txt index ec07f0716..6b89699e0 100644 --- a/examples/cmake_protect_lib/CMakeLists.txt +++ b/examples/cmake_protect_lib/CMakeLists.txt @@ -5,8 +5,8 @@ # This is an example cmake script to build a verilog to systemc project # using cmake and verilator. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/cmake_protect_lib/Makefile b/examples/cmake_protect_lib/Makefile index e33a41038..de3945253 100644 --- a/examples/cmake_protect_lib/Makefile +++ b/examples/cmake_protect_lib/Makefile @@ -6,8 +6,8 @@ # This makefile is here for testing the examples and should # generally not be added to a CMake project. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/cmake_tracing_c/CMakeLists.txt b/examples/cmake_tracing_c/CMakeLists.txt index 63c2a9668..5c6af729c 100644 --- a/examples/cmake_tracing_c/CMakeLists.txt +++ b/examples/cmake_tracing_c/CMakeLists.txt @@ -5,8 +5,8 @@ # This is an example cmake script to build a verilog to systemc project # using cmake and verilator. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/cmake_tracing_c/Makefile b/examples/cmake_tracing_c/Makefile index 4a14fbc1e..f5020b899 100644 --- a/examples/cmake_tracing_c/Makefile +++ b/examples/cmake_tracing_c/Makefile @@ -6,8 +6,8 @@ # This makefile is here for testing the examples and should # generally not be added to a CMake project. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/cmake_tracing_sc/CMakeLists.txt b/examples/cmake_tracing_sc/CMakeLists.txt index f1b0d203f..169f2626a 100644 --- a/examples/cmake_tracing_sc/CMakeLists.txt +++ b/examples/cmake_tracing_sc/CMakeLists.txt @@ -5,8 +5,8 @@ # This is an example cmake script to build a verilog to SystemC project # using CMake and Verilator. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/cmake_tracing_sc/Makefile b/examples/cmake_tracing_sc/Makefile index 2346cfebd..94440c73b 100644 --- a/examples/cmake_tracing_sc/Makefile +++ b/examples/cmake_tracing_sc/Makefile @@ -6,8 +6,8 @@ # This makefile is here for testing the examples and should # generally not be added to a CMake project. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/json_py/Makefile b/examples/json_py/Makefile index c5e69028c..d2be83823 100644 --- a/examples/json_py/Makefile +++ b/examples/json_py/Makefile @@ -2,8 +2,8 @@ # # DESCRIPTION: Verilator Example: XML tests # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/json_py/sub.v b/examples/json_py/sub.v index 19a635b3e..ad094e147 100644 --- a/examples/json_py/sub.v +++ b/examples/json_py/sub.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // ====================================================================== diff --git a/examples/json_py/top.v b/examples/json_py/top.v index 38a3be52b..5798106a2 100644 --- a/examples/json_py/top.v +++ b/examples/json_py/top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // ====================================================================== diff --git a/examples/json_py/vl_file_copy b/examples/json_py/vl_file_copy index 96b138fa1..42a825693 100755 --- a/examples/json_py/vl_file_copy +++ b/examples/json_py/vl_file_copy @@ -88,8 +88,8 @@ Example usage: -v Verilog library -y Directory to search for modules -This file ONLY is placed under the Creative Commons Public Domain, for -any use, without warranty, 2019 by Wilson Snyder. +This file ONLY is placed under the Creative Commons Public Domain. +SPDX-FileCopyrightText: 2019 Wilson Snyder SPDX-License-Identifier: CC0-1.0 """) parser.add_argument('-debug', '--debug', action='store_const', const=9, help='enable debug') diff --git a/examples/json_py/vl_hier_graph b/examples/json_py/vl_hier_graph index c38520816..4dd53e668 100755 --- a/examples/json_py/vl_hier_graph +++ b/examples/json_py/vl_hier_graph @@ -125,8 +125,8 @@ Example usage: -v Verilog library -y Directory to search for modules -This file ONLY is placed under the Creative Commons Public Domain, for -any use, without warranty, 2019 by Wilson Snyder. +This file ONLY is placed under the Creative Commons Public Domain. +SPDX-FileCopyrightText: 2019 Wilson Snyder SPDX-License-Identifier: CC0-1.0 """) parser.add_argument('-debug', '--debug', action='store_const', const=9, help='enable debug') diff --git a/examples/make_hello_binary/Makefile b/examples/make_hello_binary/Makefile index 476d4829a..b7c15a988 100644 --- a/examples/make_hello_binary/Makefile +++ b/examples/make_hello_binary/Makefile @@ -5,8 +5,8 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/make_hello_binary/top.v b/examples/make_hello_binary/top.v index 20ae7aa9a..10429f21f 100644 --- a/examples/make_hello_binary/top.v +++ b/examples/make_hello_binary/top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See also https://verilator.org/guide/latest/examples.html" diff --git a/examples/make_hello_c/Makefile b/examples/make_hello_c/Makefile index 95f2d3ca6..fce70fa82 100644 --- a/examples/make_hello_c/Makefile +++ b/examples/make_hello_c/Makefile @@ -5,8 +5,8 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/make_hello_c/sim_main.cpp b/examples/make_hello_c/sim_main.cpp index 1a9ace25e..47a7f42c4 100644 --- a/examples/make_hello_c/sim_main.cpp +++ b/examples/make_hello_c/sim_main.cpp @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //====================================================================== diff --git a/examples/make_hello_c/top.v b/examples/make_hello_c/top.v index 20ae7aa9a..10429f21f 100644 --- a/examples/make_hello_c/top.v +++ b/examples/make_hello_c/top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See also https://verilator.org/guide/latest/examples.html" diff --git a/examples/make_hello_sc/Makefile b/examples/make_hello_sc/Makefile index 20ee646f4..b35d8f7f5 100644 --- a/examples/make_hello_sc/Makefile +++ b/examples/make_hello_sc/Makefile @@ -5,8 +5,8 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/make_hello_sc/sc_main.cpp b/examples/make_hello_sc/sc_main.cpp index 697dcd973..b1aa4983a 100644 --- a/examples/make_hello_sc/sc_main.cpp +++ b/examples/make_hello_sc/sc_main.cpp @@ -1,8 +1,8 @@ // -*- SystemC -*- // DESCRIPTION: Verilator Example: Top level main for invoking SystemC model // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //====================================================================== diff --git a/examples/make_hello_sc/top.v b/examples/make_hello_sc/top.v index 20ae7aa9a..10429f21f 100644 --- a/examples/make_hello_sc/top.v +++ b/examples/make_hello_sc/top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See also https://verilator.org/guide/latest/examples.html" diff --git a/examples/make_protect_lib/Makefile b/examples/make_protect_lib/Makefile index f4cc7a0b0..bb64e066b 100644 --- a/examples/make_protect_lib/Makefile +++ b/examples/make_protect_lib/Makefile @@ -5,8 +5,8 @@ # This calls the object directory makefiles. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/make_protect_lib/secret_impl.v b/examples/make_protect_lib/secret_impl.v index 3f8fadf66..7aa49d274 100644 --- a/examples/make_protect_lib/secret_impl.v +++ b/examples/make_protect_lib/secret_impl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: --protect-lib example secret module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // This module will be used as libsecret.a or libsecret.so without diff --git a/examples/make_protect_lib/sim_main.cpp b/examples/make_protect_lib/sim_main.cpp index 06e5acb4d..34aa033b3 100644 --- a/examples/make_protect_lib/sim_main.cpp +++ b/examples/make_protect_lib/sim_main.cpp @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: --protect-lib example module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //====================================================================== diff --git a/examples/make_protect_lib/top.v b/examples/make_protect_lib/top.v index c8989fe42..e24740707 100644 --- a/examples/make_protect_lib/top.v +++ b/examples/make_protect_lib/top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: --protect-lib example module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See also https://verilator.org/guide/latest/examples.html" diff --git a/examples/make_tracing_c/Makefile b/examples/make_tracing_c/Makefile index 179705bff..072ecf4b5 100644 --- a/examples/make_tracing_c/Makefile +++ b/examples/make_tracing_c/Makefile @@ -5,8 +5,8 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/make_tracing_c/Makefile_obj b/examples/make_tracing_c/Makefile_obj index d18fe44e1..8362266ca 100644 --- a/examples/make_tracing_c/Makefile_obj +++ b/examples/make_tracing_c/Makefile_obj @@ -5,8 +5,8 @@ # # This is executed in the object directory, and called by ../Makefile # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ####################################################################### diff --git a/examples/make_tracing_c/sim_main.cpp b/examples/make_tracing_c/sim_main.cpp index ade094041..d1ce87c47 100644 --- a/examples/make_tracing_c/sim_main.cpp +++ b/examples/make_tracing_c/sim_main.cpp @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //====================================================================== diff --git a/examples/make_tracing_c/sub.v b/examples/make_tracing_c/sub.v index 473139c07..5d0eb939d 100644 --- a/examples/make_tracing_c/sub.v +++ b/examples/make_tracing_c/sub.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // ====================================================================== diff --git a/examples/make_tracing_c/top.v b/examples/make_tracing_c/top.v index 44393f9d2..66d7b3e15 100644 --- a/examples/make_tracing_c/top.v +++ b/examples/make_tracing_c/top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // ====================================================================== diff --git a/examples/make_tracing_sc/Makefile b/examples/make_tracing_sc/Makefile index 68d2b51ae..7f095cc89 100644 --- a/examples/make_tracing_sc/Makefile +++ b/examples/make_tracing_sc/Makefile @@ -5,8 +5,8 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ###################################################################### diff --git a/examples/make_tracing_sc/Makefile_obj b/examples/make_tracing_sc/Makefile_obj index 834bfc7ba..ef4ee6867 100644 --- a/examples/make_tracing_sc/Makefile_obj +++ b/examples/make_tracing_sc/Makefile_obj @@ -5,8 +5,8 @@ # # This is executed in the object directory, and called by ../Makefile # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2020 by Wilson Snyder. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2020 Wilson Snyder # SPDX-License-Identifier: CC0-1.0 # ####################################################################### diff --git a/examples/make_tracing_sc/sc_main.cpp b/examples/make_tracing_sc/sc_main.cpp index 208d4e43d..a0fac9206 100644 --- a/examples/make_tracing_sc/sc_main.cpp +++ b/examples/make_tracing_sc/sc_main.cpp @@ -1,8 +1,8 @@ // -*- SystemC -*- // DESCRIPTION: Verilator Example: Top level main for invoking SystemC model // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //====================================================================== diff --git a/examples/make_tracing_sc/sub.v b/examples/make_tracing_sc/sub.v index 98328fbcc..28ff688cf 100644 --- a/examples/make_tracing_sc/sub.v +++ b/examples/make_tracing_sc/sub.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // ====================================================================== diff --git a/examples/make_tracing_sc/top.v b/examples/make_tracing_sc/top.v index 8e5c42a40..31c6a0f51 100644 --- a/examples/make_tracing_sc/top.v +++ b/examples/make_tracing_sc/top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // ====================================================================== diff --git a/include/gtkwave/fst_config.h b/include/gtkwave/fst_config.h index 43fbd90ee..cd38760df 100644 --- a/include/gtkwave/fst_config.h +++ b/include/gtkwave/fst_config.h @@ -1,6 +1,7 @@ -/* This file specifically for FST usage */ -/* config.h. Generated from config.h.in by configure. */ -/* config.h.in. Generated from configure.ac by autoheader. */ +// This file specifically for FST usage +// Originally generated from config.h.in by configure. +// SPDX-FileCopyrightText: 2018-2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 /* Define to 1 if you have and it should be used (not on Ultrix). */ #if !defined(__MINGW32__) && !defined(__FreeBSD__) diff --git a/include/verilated.cpp b/include/verilated.cpp index 64d5f6736..86a891df8 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= @@ -69,6 +69,7 @@ # include // mkdir #endif #ifdef __GLIBC__ +# include # include # define _VL_HAVE_STACKTRACE #endif @@ -112,6 +113,36 @@ VerilatedContext* Verilated::s_lastContextp = nullptr; // Internal note: Globals may multi-construct, see verilated.cpp top. thread_local Verilated::ThreadLocal Verilated::t_s; +//=========================================================================== +// Warning print helper + +void vl_print_warn_error(const char* prefix, const char* filename, int linenum, + const char* msg) VL_MT_UNSAFE { + // A msg of "ERRORCODE: ..." is a code that changes to a prefix, e.g. "%Error-ERRORCODE: ..." + // This avoids changing public API of the vl_stop and related functions. + const char* msgNoCp = msg; + for (; isupper(*msgNoCp); ++msgNoCp); + if (msgNoCp[0] == ':' && msgNoCp[1] == ' ') { + const int codeWidth = static_cast(msgNoCp - msg); + msgNoCp += 2; + if (filename && filename[0]) { + VL_PRINTF( // Not VL_PRINTF_MT, already on main thread + "%s-%.*s: %s:%d: %s\n", prefix, codeWidth, msg, filename, linenum, msgNoCp); + } else { + VL_PRINTF( // Not VL_PRINTF_MT, already on main thread + "%s-%.*s: %s\n", prefix, codeWidth, msg, msgNoCp); + } + } else { + if (filename && filename[0]) { + VL_PRINTF( // Not VL_PRINTF_MT, already on main thread + "%s: %s:%d: %s\n", prefix, filename, linenum, msg); + } else { + VL_PRINTF( // Not VL_PRINTF_MT, already on main thread + "%s: %s\n", prefix, msg); + } + } +} + //=========================================================================== // User definable functions // Note a TODO is a future version of the API will pass a structure so that @@ -119,8 +150,7 @@ thread_local Verilated::ThreadLocal Verilated::t_s; #ifndef VL_USER_FINISH ///< Define this to override the vl_finish function void vl_finish(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE { - // hier is unused in the default implementation. - (void)hier; + (void)hier; // hier is unused in the default implementation. VL_PRINTF( // Not VL_PRINTF_MT, already on main thread "- %s:%d: Verilog $finish\n", filename, linenum); Verilated::threadContextp()->gotFinish(true); @@ -130,18 +160,14 @@ void vl_finish(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE #ifndef VL_USER_STOP ///< Define this to override the vl_stop function void vl_stop(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE { // $stop or $fatal reporting; would break current API to add param as to which + if (Verilated::threadContextp()->gotFinish()) return; const char* const msg = "Verilog $stop"; Verilated::threadContextp()->gotError(true); Verilated::threadContextp()->gotFinish(true); if (Verilated::threadContextp()->fatalOnError()) { vl_fatal(filename, linenum, hier, msg); } else { - if (filename && filename[0]) { - // Not VL_PRINTF_MT, already on main thread - VL_PRINTF("%%Error: %s:%d: %s\n", filename, linenum, msg); - } else { - VL_PRINTF("%%Error: %s\n", msg); - } + vl_print_warn_error("%Error", filename, linenum, msg); Verilated::runFlushCallbacks(); } } @@ -149,16 +175,10 @@ void vl_stop(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE { #ifndef VL_USER_FATAL ///< Define this to override the vl_fatal function void vl_fatal(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_UNSAFE { - // hier is unused in the default implementation. - (void)hier; + (void)hier; // hier is unused in the default implementation. Verilated::threadContextp()->gotError(true); Verilated::threadContextp()->gotFinish(true); - if (filename && filename[0]) { - // Not VL_PRINTF_MT, already on main thread - VL_PRINTF("%%Error: %s:%d: %s\n", filename, linenum, msg); - } else { - VL_PRINTF("%%Error: %s\n", msg); - } + vl_print_warn_error("%Error", filename, linenum, msg); Verilated::runFlushCallbacks(); VL_PRINTF("Aborting...\n"); // Not VL_PRINTF_MT, already on main thread @@ -185,9 +205,8 @@ void vl_stop_maybe(const char* filename, int linenum, const char* hier, bool may && Verilated::threadContextp()->errorCount() < Verilated::threadContextp()->errorLimit()) { // Do just once when cross error limit if (Verilated::threadContextp()->errorCount() == 1) { - VL_PRINTF( // Not VL_PRINTF_MT, already on main thread - "-Info: %s:%d: %s\n", filename, linenum, - "Verilog $stop, ignored due to +verilator+error+limit"); + vl_print_warn_error("-Info", filename, linenum, + "Verilog $stop, ignored due to +verilator+error+limit"); } } else { vl_stop(filename, linenum, hier); @@ -197,14 +216,8 @@ void vl_stop_maybe(const char* filename, int linenum, const char* hier, bool may #ifndef VL_USER_WARN ///< Define this to override the vl_warn function void vl_warn(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_UNSAFE { - // hier is unused in the default implementation. - (void)hier; - if (filename && filename[0]) { - // Not VL_PRINTF_MT, already on main thread - VL_PRINTF("%%Warning: %s:%d: %s\n", filename, linenum, msg); - } else { - VL_PRINTF("%%Warning: %s\n", msg); - } + (void)hier; // hier is unused in the default implementation. + vl_print_warn_error("%Warning", filename, linenum, msg); Verilated::runFlushCallbacks(); } #endif @@ -307,42 +320,72 @@ void VlProcess::randstate(const std::string& state) VL_MT_UNSAFE { //=========================================================================== // Random -- Mostly called at init time, so not inline. -VlRNG::VlRNG() VL_MT_SAFE { - // Starting point for this new class comes from the global RNG - VlRNG& fromr = vl_thread_rng(); - m_state = fromr.m_state; - // Advance the *source* so it can later generate a new number - // Xoroshiro128+ algorithm - fromr.m_state[1] ^= fromr.m_state[0]; - fromr.m_state[0] = (((fromr.m_state[0] << 55) | (fromr.m_state[0] >> 9)) ^ fromr.m_state[1] - ^ (fromr.m_state[1] << 14)); - fromr.m_state[1] = (fromr.m_state[1] << 36) | (fromr.m_state[1] >> 28); +static std::pair vl_splitmix64(uint64_t x) VL_PURE { + // SplitMix64 algorithm, copied under public domain from + // https://prng.di.unimi.it/splitmix64.c + // by Sebastiano Vigna + uint64_t z = (x += 0x9e3779b97f4a7c15ULL); + z = (z ^ (z >> 30)) * 0xbf58476d1ce4e5b9ULL; + z = (z ^ (z >> 27)) * 0x94d049bb133111ebULL; + return {x, z ^ (z >> 31)}; } + +// Xoroshiro128** algorithm, copied under public domain from +// https://xoshiro.di.unimi.it/xoroshiro128starstar.c +// by David Blackman and Sebastiano Vigna + +static uint64_t vl_rolt(const uint64_t x, int k) VL_PURE { return (x << k) | (x >> (64 - k)); } + +static std::array vl_rng_state_from_seed(uint64_t seed) VL_PURE { + const auto split1 = vl_splitmix64(seed); + const auto split2 = vl_splitmix64(split1.first); + return {split1.second, split2.second}; +} + +static uint64_t vl_rng_result(const std::array& state) VL_PURE { + const uint64_t s0 = state[0]; + return vl_rolt(s0 * 5, 7) * 9; +} + +static std::array +vl_rng_compute_new_state(const std::array& current_state) VL_PURE { + const uint64_t s0 = current_state[0]; + uint64_t s1 = current_state[1]; + + s1 ^= s0; + const uint64_t new_s0 = vl_rolt(s0, 24) ^ s1 ^ (s1 << 16); // a, b + const uint64_t new_s1 = vl_rolt(s1, 37); // c + + return {new_s0, new_s1}; +} + +VlRNG::VlRNG() VL_MT_SAFE { + VlRNG& fromr = vl_thread_rng(); + + const uint64_t s0 = vl_rng_result(fromr.m_state); + fromr.m_state = vl_rng_compute_new_state(fromr.m_state); + + const uint64_t s1 = vl_rng_result(fromr.m_state); + fromr.m_state = vl_rng_compute_new_state(fromr.m_state); + + m_state = {s0, s1}; +} + +VlRNG::VlRNG(uint64_t seed) VL_PURE { m_state = vl_rng_state_from_seed(seed); } +void VlRNG::srandom(uint64_t n) VL_MT_UNSAFE { m_state = vl_rng_state_from_seed(n); } + uint64_t VlRNG::rand64() VL_MT_UNSAFE { - // Xoroshiro128+ algorithm - const uint64_t result = m_state[0] + m_state[1]; - m_state[1] ^= m_state[0]; - m_state[0] = (((m_state[0] << 55) | (m_state[0] >> 9)) ^ m_state[1] ^ (m_state[1] << 14)); - m_state[1] = (m_state[1] << 36) | (m_state[1] >> 28); + const uint64_t result = vl_rng_result(m_state); + m_state = vl_rng_compute_new_state(m_state); return result; } uint64_t VlRNG::vl_thread_rng_rand64() VL_MT_SAFE { VlRNG& fromr = vl_thread_rng(); - const uint64_t result = fromr.m_state[0] + fromr.m_state[1]; - fromr.m_state[1] ^= fromr.m_state[0]; - fromr.m_state[0] = (((fromr.m_state[0] << 55) | (fromr.m_state[0] >> 9)) ^ fromr.m_state[1] - ^ (fromr.m_state[1] << 14)); - fromr.m_state[1] = (fromr.m_state[1] << 36) | (fromr.m_state[1] >> 28); + const uint64_t result = vl_rng_result(fromr.m_state); + fromr.m_state = vl_rng_compute_new_state(fromr.m_state); return result; } -void VlRNG::srandom(uint64_t n) VL_MT_UNSAFE { - m_state[0] = n; - m_state[1] = m_state[0]; - // Fix state as algorithm is slow to randomize if many zeros - // This causes a loss of ~ 1 bit of seed entropy, no big deal - if (VL_COUNTONES_I(m_state[0]) < 10) m_state[0] = ~m_state[0]; - if (VL_COUNTONES_I(m_state[1]) < 10) m_state[1] = ~m_state[1]; -} + std::string VlRNG::get_randstate() const VL_MT_UNSAFE { // Though not stated in IEEE, assumption is the string must be printable const char* const stateCharsp = reinterpret_cast(&m_state); @@ -387,13 +430,8 @@ VlRNG& VlRNG::vl_thread_rng() VL_MT_SAFE { if (VL_UNLIKELY(t_seedEpoch != VerilatedContextImp::randSeedEpoch())) { // Set epoch before state, to avoid race case with new seeding t_seedEpoch = VerilatedContextImp::randSeedEpoch(); - // Same as srandom() but here as needs to be VL_MT_SAFE - t_rng.m_state[0] = Verilated::threadContextp()->impp()->randSeedDefault64(); - t_rng.m_state[1] = t_rng.m_state[0]; - // Fix state as algorithm is slow to randomize if many zeros - // This causes a loss of ~ 1 bit of seed entropy, no big deal - if (VL_COUNTONES_I(t_rng.m_state[0]) < 10) t_rng.m_state[0] = ~t_rng.m_state[0]; - if (VL_COUNTONES_I(t_rng.m_state[1]) < 10) t_rng.m_state[1] = ~t_rng.m_state[1]; + t_rng.m_state + = vl_rng_state_from_seed(Verilated::threadContextp()->impp()->randSeedDefault64()); } return t_rng; } @@ -404,6 +442,8 @@ WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp) VL_MT_SAFE { return outwp; } +double VL_RANDOM_RNG_D(VlRNG& rngr) VL_MT_UNSAFE { return VL_CVT_D_Q(VL_RANDOM_RNG_Q(rngr)); } + WDataOutP VL_RANDOM_RNG_W(VlRNG& rngr, int obits, WDataOutP outwp) VL_MT_UNSAFE { for (int i = 0; i < VL_WORDS_I(obits); ++i) outwp[i] = rngr.rand64(); // Last word is unclean @@ -1882,27 +1922,68 @@ IData VL_FREAD_I(int width, int array_lsb, int array_size, void* memp, IData fpi return read_count; } +#ifdef _VL_HAVE_STACKTRACE +static std::string _vl_stacktrace_demangle(const std::string& input) VL_MT_SAFE { + static VerilatedMutex s_demangleMutex; + const VerilatedLockGuard lock{s_demangleMutex}; + + std::string result; + result.reserve(input.size()); + + std::string word; + for (const char c : input) { + if (std::isalpha(c) || c == '_') { + word += c; + } else if (!word.empty() && std::isdigit(c)) { + word += c; + } else { + if (!word.empty()) { + // abi::__cxa_demangle mallocs demangled_name + int status = 0; + char* const demangled_name + = abi::__cxa_demangle(word.c_str(), NULL, NULL, &status); + if (status == 0) { + result += std::string{demangled_name}; + std::free(demangled_name); // Free the allocated memory + } else { + result += word; + } + word.clear(); + } + result += c; + } + } + // input requires final newline, so last word can't be symbol + result += word; + return result; +} +#endif + std::string VL_STACKTRACE_N() VL_MT_SAFE { static VerilatedMutex s_stackTraceMutex; const VerilatedLockGuard lock{s_stackTraceMutex}; +#ifdef _VL_HAVE_STACKTRACE int nptrs = 0; char** strings = nullptr; -#ifdef _VL_HAVE_STACKTRACE constexpr int BT_BUF_SIZE = 100; void* buffer[BT_BUF_SIZE]; nptrs = backtrace(buffer, BT_BUF_SIZE); strings = backtrace_symbols(buffer, nptrs); -#endif // cppcheck-suppress knownConditionTrueFalse - if (!strings) return "Unable to backtrace\n"; + if (!strings) return "Unable to backtrace, call failed\n"; std::string result = "Backtrace:\n"; - for (int j = 0; j < nptrs; ++j) result += std::string{strings[j]} + "\n"s; + for (int j = 0; j < nptrs; ++j) + result += _vl_stacktrace_demangle(std::string{strings[j]} + "\n"s); + free(strings); return result; +#else + return "Unable to backtrace; not supported\n"; +#endif } void VL_STACKTRACE() VL_MT_SAFE { @@ -2805,6 +2886,7 @@ void VerilatedContext::threads(unsigned n) { "%Error: Cannot set simulation threads after the thread pool has been created."); } + m_useNumaAssign = true; if (m_threads == n) return; // To avoid unnecessary warnings m_threads = n; const unsigned threadsAvailableToProcess = VlOs::getProcessDefaultParallelism(); @@ -2815,6 +2897,8 @@ void VerilatedContext::threads(unsigned n) { } } +void VerilatedContext::useNumaAssign(bool flag) { m_useNumaAssign = flag; } + void VerilatedContext::commandArgs(int argc, const char** argv) VL_MT_SAFE_EXCLUDES(m_argMutex) { // Not locking m_argMutex here, it is done in impp()->commandArgsAddGuts // m_argMutex here is the same as in impp()->commandArgsAddGuts; @@ -3002,6 +3086,8 @@ void VerilatedContextImp::commandArgVl(const std::string& arg) { quiet(true); } else if (commandArgVlUint64(arg, "+verilator+rand+reset+", u64, 0, 2)) { randReset(static_cast(u64)); + } else if (commandArgVlUint64(arg, "+verilator+wno+unsatconstr+", u64, 0, 1)) { + warnUnsatConstr(u64 == 0); // wno means disable, so invert } else if (commandArgVlUint64(arg, "+verilator+seed+", u64, 1, std::numeric_limits::max())) { randSeed(static_cast(u64)); @@ -3105,7 +3191,7 @@ void VerilatedContext::statsPrintSummary() VL_MT_UNSAFE { uint64_t memPeak, memCurrent; VlOs::memUsageBytes(memPeak /*ref*/, memCurrent /*ref*/); const double modelMB = memPeak / 1024.0 / 1024.0; - VL_PRINTF("- Verilator: cpu %0.3f s on %u threads; alloced %0.0f MB\n", cputime, + VL_PRINTF("- Verilator: cpu %0.3f s on %u threads; allocated %0.0f MB\n", cputime, threadsInModels(), modelMB); } @@ -3378,11 +3464,10 @@ void Verilated::mkdir(const char* dirname) VL_MT_UNSAFE { void Verilated::quiesce() VL_MT_SAFE { // Wait until all threads under this evaluation are quiet - // THREADED-TODO } int Verilated::exportFuncNum(const char* namep) VL_MT_SAFE { - return VerilatedImp::exportFind(namep); + return VerilatedImp::exportFindNum(namep); } void Verilated::endOfThreadMTaskGuts(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE { @@ -3487,7 +3572,7 @@ VerilatedScope::~VerilatedScope() { void VerilatedScope::exportInsert(int finalize, const char* namep, void* cb) VL_MT_UNSAFE { // Slowpath - called once/scope*export at construction // Insert a exported function into scope table - const int funcnum = VerilatedImp::exportInsert(namep); + const int funcnum = VerilatedImp::exportInsert(namep, cb); if (!finalize) { // Need two passes so we know array size to create // Alternative is to dynamically stretch the array, which is more code, and slower. @@ -3544,6 +3629,25 @@ VerilatedVar* VerilatedScope::varFind(const char* namep) const VL_MT_SAFE_POSTIN return nullptr; } +void* VerilatedScope::exportFind(const VerilatedScope* scopep, int funcnum) VL_MT_SAFE { + if (VL_UNLIKELY(!scopep)) return exportFindNullError(funcnum); + // If function is registered only once across all scopes, fast path it. + // UVM for example expects to find uvm_polling_value_change_notify + // from a different scope than where decared. + VL_DEBUG_IFDEF(assert(funcnum < VerilatedImp::exportFlatCbs().size());); + { + void* const cbp = VerilatedImp::exportFlatCbs()[funcnum]; + if (VL_LIKELY(cbp)) return cbp; + } + // Else specific scope-based export call + if (VL_LIKELY(funcnum < scopep->m_funcnumMax)) { + // m_callbacksp must be declared, as Max'es are > 0 + void* const cbp = scopep->m_callbacksp[funcnum]; + if (VL_LIKELY(cbp)) return cbp; + } + return scopep->exportFindError(funcnum); // LCOV_EXCL_LINE +} + void* VerilatedScope::exportFindNullError(int funcnum) VL_MT_SAFE { // Slowpath - Called only when find has failed const std::string msg = ("Testbench C called '"s + VerilatedImp::exportName(funcnum) diff --git a/include/verilated.h b/include/verilated.h index 5ac6d19be..15fdab267 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -155,7 +155,10 @@ enum VerilatedVarFlags { VLVF_PUB_RD = (1 << 8), // Public readable VLVF_PUB_RW = (1 << 9), // Public writable VLVF_DPI_CLAY = (1 << 10), // DPI compatible C standard layout - VLVF_SIGNED = (1 << 11) // Signed integer + VLVF_CONTINUOUSLY = (1 << 11), // Is continously assigned + VLVF_FORCEABLE = (1 << 12), // Forceable + VLVF_SIGNED = (1 << 13), // Signed integer + VLVF_BITVAR = (1 << 14) // Four state bit (vs two state logic) }; // IEEE 1800-2023 Table 20-6 @@ -412,6 +415,7 @@ protected: std::string m_profExecFilename; // +prof+exec+file filename std::string m_profVltFilename; // +prof+vlt filename std::string m_solverProgram; // SMT solver program + bool m_warnUnsatConstr = true; // Warn on unsatisfied constraints VlOs::DeltaCpuTime m_cpuTimeStart{false}; // CPU time, starts when create first model VlOs::DeltaWallTime m_wallTimeStart{false}; // Wall time, starts when create first model std::vector m_traceBaseModelCbs; // Callbacks to traceRegisterModel @@ -430,6 +434,8 @@ protected: const std::unique_ptr m_impdatap; // Number of threads to use for simulation (size of m_threadPool + 1 for main thread) unsigned m_threads = VlOs::getProcessDefaultParallelism(); + // Use numa automatic CPU-to-thread assignment + bool m_useNumaAssign = false; // Number of threads in added models unsigned m_threadsInModels = 0; // The thread pool shared by all models added to this context @@ -596,6 +602,13 @@ public: /// Can only be called before the thread pool is created (before first model is added). void threads(unsigned n); + /// Use numa automatic CPU-to-thread assignment. + bool useNumaAssign() const VL_MT_SAFE { return m_useNumaAssign; } + /// Set numa assignment of threads to cores + /// Defaults false; set true automatically when threads() called; + /// call this to override back to false if numa assignment not wanted. + void useNumaAssign(bool flag); + /// Trace signals in models within the context; called by application code void trace(VerilatedTraceBaseC* tfp, int levels, int options = 0); /// Allow traces to at some point be enabled (disables some optimizations) @@ -651,6 +664,9 @@ public: // Internal: SMT solver program std::string solverProgram() const VL_MT_SAFE; void solverProgram(const std::string& flag) VL_MT_SAFE; + // Internal: Control display of unsatisfied constraints + bool warnUnsatConstr() const VL_MT_SAFE { return m_ns.m_warnUnsatConstr; } + void warnUnsatConstr(bool flag) VL_MT_SAFE { m_ns.m_warnUnsatConstr = flag; } // Internal: Find scope const VerilatedScope* scopeFind(const char* namep) const VL_MT_SAFE; @@ -728,15 +744,7 @@ public: // But internals only - called from verilated modules, VerilatedSyms void scopeDump() const; void* exportFindError(int funcnum) const VL_MT_SAFE; static void* exportFindNullError(int funcnum) VL_MT_SAFE; - static void* exportFind(const VerilatedScope* scopep, int funcnum) VL_MT_SAFE { - if (VL_UNLIKELY(!scopep)) return exportFindNullError(funcnum); - if (VL_LIKELY(funcnum < scopep->m_funcnumMax)) { - // m_callbacksp must be declared, as Max'es are > 0 - return scopep->m_callbacksp[funcnum]; - } else { // LCOV_EXCL_LINE - return scopep->exportFindError(funcnum); // LCOV_EXCL_LINE - } - } + static void* exportFind(const VerilatedScope* scopep, int funcnum) VL_MT_SAFE; Type type() const { return m_type; } }; diff --git a/include/verilated.mk.in b/include/verilated.mk.in index 48c15da8c..7a14bc558 100644 --- a/include/verilated.mk.in +++ b/include/verilated.mk.in @@ -2,10 +2,10 @@ ###################################################################### # DESCRIPTION: Makefile commands for all verilated target files # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### diff --git a/include/verilated.v b/include/verilated.v index 292c7f1b1..7d6780d86 100644 --- a/include/verilated.v +++ b/include/verilated.v @@ -2,10 +2,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= diff --git a/include/verilated_config.h.in b/include/verilated_config.h.in index a389bbf21..961616005 100644 --- a/include/verilated_config.h.in +++ b/include/verilated_config.h.in @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index 9fa61b1d1..123fa6dbe 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_cov.h b/include/verilated_cov.h index a2986c8e5..a6cbd2d4e 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_cov_key.h b/include/verilated_cov_key.h index e7eb7e08e..cb0a2efa9 100644 --- a/include/verilated_cov_key.h +++ b/include/verilated_cov_key.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_dpi.cpp b/include/verilated_dpi.cpp index d918ab97f..d8f75f577 100644 --- a/include/verilated_dpi.cpp +++ b/include/verilated_dpi.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= diff --git a/include/verilated_dpi.h b/include/verilated_dpi.h index bd6c8494d..cb6efff68 100644 --- a/include/verilated_dpi.h +++ b/include/verilated_dpi.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index 43d5367b2..f79e73168 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= @@ -134,7 +134,8 @@ void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, uint32_t elemen const char** itemValuesp) { const fstEnumHandle enumNum = fstWriterCreateEnumTable(m_fst, name, elements, minValbits, itemNamesp, itemValuesp); - m_local2fstdtype[dtypenum] = enumNum; + const bool newEntry = m_local2fstdtype[initUserp()].emplace(dtypenum, enumNum).second; + assert(newEntry); } // TODO: should return std::optional, but I can't have C++17 @@ -205,7 +206,9 @@ void VerilatedFst::declare(uint32_t code, const char* name, int dtypenum, if (bussed) name_ss << " [" << msb << ":" << lsb << "]"; const std::string name_str = name_ss.str(); - if (dtypenum > 0) fstWriterEmitEnumTableRef(m_fst, m_local2fstdtype[dtypenum]); + if (dtypenum > 0) { + fstWriterEmitEnumTableRef(m_fst, m_local2fstdtype.at(initUserp()).at(dtypenum)); + } fstVarDir varDir = FST_VD_IMPLICIT; switch (direction) { diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index 3ac2c2717..b2394ab07 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= @@ -53,7 +53,7 @@ private: fstWriterContext* m_fst = nullptr; std::map m_code2symbol; - std::map m_local2fstdtype; + std::map> m_local2fstdtype; vlFstHandle* m_symbolp = nullptr; // same as m_code2symbol, but as an array char* m_strbufp = nullptr; // String buffer long enough to hold maxBits() chars uint64_t m_timeui = 0; // Time to emit, 0 = not needed diff --git a/include/verilated_fst_sc.cpp b/include/verilated_fst_sc.cpp index e3bf34171..e19a491f1 100644 --- a/include/verilated_fst_sc.cpp +++ b/include/verilated_fst_sc.cpp @@ -3,10 +3,10 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_fst_sc.h b/include/verilated_fst_sc.h index 6f2cf0862..fe554add4 100644 --- a/include/verilated_fst_sc.h +++ b/include/verilated_fst_sc.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h index 75110fb5c..e3e4534ff 100644 --- a/include/verilated_funcs.h +++ b/include/verilated_funcs.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -1718,24 +1718,33 @@ static inline QData VL_PACK_Q_UQ(int obits, int lbits, const VlUnpacked& q) { VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); + if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger + const int offset = obits - q.size() * lbits; for (size_t i = 0; i < q.size(); ++i) - _vl_insert_WI(owp, q.at(q.size() - i - 1), i * lbits + lbits - 1, i * lbits); + _vl_insert_WI(owp, q.at(q.size() - i - 1), i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } static inline WDataOutP VL_PACK_W_RI(int obits, int lbits, WDataOutP owp, const VlQueue& q) { VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); + if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger + const int offset = obits - q.size() * lbits; for (size_t i = 0; i < q.size(); ++i) - _vl_insert_WI(owp, q.at(q.size() - i - 1), i * lbits + lbits - 1, i * lbits); + _vl_insert_WI(owp, q.at(q.size() - i - 1), i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } static inline WDataOutP VL_PACK_W_RI(int obits, int lbits, WDataOutP owp, const VlQueue& q) { VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); + if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger + const int offset = obits - q.size() * lbits; for (size_t i = 0; i < q.size(); ++i) - _vl_insert_WI(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1, i * lbits); + _vl_insert_WI(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } @@ -1769,8 +1778,11 @@ static inline WDataOutP VL_PACK_W_UI(int obits, int lbits, WDataOutP owp, static inline WDataOutP VL_PACK_W_RQ(int obits, int lbits, WDataOutP owp, const VlQueue& q) { VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); + if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger + const int offset = obits - q.size() * lbits; for (size_t i = 0; i < q.size(); ++i) - _vl_insert_WQ(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1, i * lbits); + _vl_insert_WQ(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } @@ -1787,8 +1799,11 @@ template static inline WDataOutP VL_PACK_W_RW(int obits, int lbits, WDataOutP owp, const VlQueue>& q) { VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); + if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger + const int offset = obits - q.size() * lbits; for (size_t i = 0; i < q.size(); ++i) - _vl_insert_WW(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1, i * lbits); + _vl_insert_WW(owp, q.at(q.size() - 1 - i), i * lbits + lbits - 1 + offset, + i * lbits + offset); return owp; } @@ -1796,8 +1811,10 @@ template static inline WDataOutP VL_PACK_W_UW(int obits, int lbits, WDataOutP owp, const VlUnpacked, N_Depth>& q) { VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); + if (VL_UNLIKELY(obits < q.size() * lbits)) return owp; // Though is illegal for q to be larger + const int offset = obits - q.size() * lbits; for (size_t i = 0; i < N_Depth; ++i) - _vl_insert_WW(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1, i * lbits); + _vl_insert_WW(owp, q[N_Depth - 1 - i], i * lbits + lbits - 1 + offset, i * lbits + offset); return owp; } @@ -1976,19 +1993,19 @@ static inline QData VL_SHIFTL_QQW(int obits, int, int rbits, QData lhs, // expression. Thus consider this when optimizing. (And perhaps have 2 funcs?) static inline IData VL_SHIFTR_III(int obits, int, int, IData lhs, IData rhs) VL_PURE { if (VL_UNLIKELY(rhs >= VL_IDATASIZE)) return 0; - return lhs >> rhs; // Small is common so assumed not clean + return lhs >> rhs; } static inline IData VL_SHIFTR_IIQ(int obits, int, int, IData lhs, QData rhs) VL_PURE { if (VL_UNLIKELY(rhs >= VL_IDATASIZE)) return 0; - return VL_CLEAN_QQ(obits, obits, lhs >> rhs); + return lhs >> rhs; } static inline QData VL_SHIFTR_QQI(int obits, int, int, QData lhs, IData rhs) VL_PURE { if (VL_UNLIKELY(rhs >= VL_QUADSIZE)) return 0; - return lhs >> rhs; // Small is common so assumed not clean + return lhs >> rhs; } static inline QData VL_SHIFTR_QQQ(int obits, int, int, QData lhs, QData rhs) VL_PURE { if (VL_UNLIKELY(rhs >= VL_QUADSIZE)) return 0; - return VL_CLEAN_QQ(obits, obits, lhs >> rhs); + return lhs >> rhs; } static inline WDataOutP VL_SHIFTR_WWI(int obits, int, int, WDataOutP owp, WDataInP const lwp, IData rd) VL_MT_SAFE { diff --git a/include/verilated_imp.h b/include/verilated_imp.h index db6f940bb..6ee4e580e 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= @@ -433,6 +433,10 @@ protected: ExportNameMap m_exportMap VL_GUARDED_BY(m_exportMutex); int m_exportNext VL_GUARDED_BY(m_exportMutex) = 0; // Next export funcnum + // No guard, as init-time loaded + std::vector m_exportFlatCbs; // Exports when only single scope registered + std::vector m_exportFlatMulti; // Multiple scopes registerd; cannot use m_exportScopes + // CONSTRUCTORS VerilatedImpData() = default; }; @@ -542,8 +546,8 @@ public: // in the design that also happen to have our same callback function. // Rather than a 2D map, the integer scheme saves 500ish ns on a likely // miss at the cost of a multiply, and all lookups move to slowpath. - static int exportInsert(const char* namep) VL_MT_SAFE { - // Slow ok - called once/function at creation +private: + static int exportInsertName(const char* namep) VL_MT_SAFE { const VerilatedLockGuard lock{s().m_exportMutex}; const auto it = s().m_exportMap.find(namep); if (it == s().m_exportMap.end()) { @@ -553,15 +557,37 @@ public: return it->second; } } - static int exportFind(const char* namep) VL_MT_SAFE { + +public: + static int exportInsert(const char* namep, void* cb) VL_MT_SAFE { + const int funcnum = VerilatedImp::exportInsertName(namep); + const VerilatedLockGuard lock{s().m_exportMutex}; + // Slow ok - called once/function at creation + if (funcnum >= s().m_exportFlatCbs.size()) { + s().m_exportFlatCbs.resize(funcnum + 1); + s().m_exportFlatMulti.resize(funcnum + 1); + } + if (!s().m_exportFlatMulti[funcnum]) { + if (s().m_exportFlatCbs[funcnum] == cb) { // Duplicate + } else if (!s().m_exportFlatCbs[funcnum]) { // First + s().m_exportFlatCbs[funcnum] = cb; + } else { // Multiple registrants + s().m_exportFlatCbs[funcnum] = nullptr; + s().m_exportFlatMulti[funcnum] = true; + } + } + return funcnum; + } + static int exportFindNum(const char* namep) VL_MT_SAFE { const VerilatedLockGuard lock{s().m_exportMutex}; const auto& it = s().m_exportMap.find(namep); if (VL_LIKELY(it != s().m_exportMap.end())) return it->second; - const std::string msg = ("%Error: Testbench C called "s + namep - + " but no such DPI export function name exists in ANY model"); + const std::string msg = "%Error: Testbench C called "s + namep + + " but no such DPI export function name exists in ANY model"; VL_FATAL_MT("unknown", 0, "", msg.c_str()); return -1; } + static const std::vector& exportFlatCbs() VL_MT_SAFE { return s().m_exportFlatCbs; } static const char* exportName(int funcnum) VL_MT_SAFE { // Slowpath; find name for given export; errors only so no map to reverse-map it const VerilatedLockGuard lock{s().m_exportMutex}; diff --git a/include/verilated_intrinsics.h b/include/verilated_intrinsics.h index b3a3996ce..6e6f568f3 100644 --- a/include/verilated_intrinsics.h +++ b/include/verilated_intrinsics.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/include/verilated_probdist.cpp b/include/verilated_probdist.cpp index 9640fd52e..e2b75d3c7 100644 --- a/include/verilated_probdist.cpp +++ b/include/verilated_probdist.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= diff --git a/include/verilated_profiler.cpp b/include/verilated_profiler.cpp index 08b66c9c8..621482bf0 100644 --- a/include/verilated_profiler.cpp +++ b/include/verilated_profiler.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2012-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_profiler.h b/include/verilated_profiler.h index 0f4565f9a..b5fb78445 100644 --- a/include/verilated_profiler.h +++ b/include/verilated_profiler.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2012-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_random.cpp b/include/verilated_random.cpp index 30d13846e..2a1f3d562 100644 --- a/include/verilated_random.cpp +++ b/include/verilated_random.cpp @@ -3,9 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU Lesser -// General Public License Version 3 or the Perl Artistic License Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= @@ -22,6 +23,7 @@ #include "verilated_random.h" +#include #include #include #include @@ -366,8 +368,131 @@ void VlRandomizer::randomConstraint(std::ostream& os, VlRNG& rngr, int bits) { os << ')'; } +size_t VlRandomizer::hashConstraints() const { + size_t h = 0; + for (const auto& c : m_constraints) { + h ^= std::hash{}(c) + 0x9e3779b9 + (h << 6) + (h >> 2); + } + return h; +} + +void VlRandomizer::enumerateRandcValues(const std::string& varName, VlRNG& rngr) { + std::vector values; + const auto varIt = m_vars.find(varName); + if (varIt == m_vars.end()) return; + const int width = varIt->second->width(); + + std::iostream& os = getSolver(); + if (!os) return; + + // Set up a single incremental solver session for enumeration + os << "(set-option :produce-models true)\n"; + os << "(set-logic QF_ABV)\n"; + os << "(define-fun __Vbv ((b Bool)) (_ BitVec 1) (ite b #b1 #b0))\n"; + os << "(define-fun __Vbool ((v (_ BitVec 1))) Bool (= #b1 v))\n"; + + // Declare all variables (solver needs full context for cross-var constraints) + for (const auto& var : m_vars) { + if (var.second->dimension() > 0) { + auto arrVarsp = std::make_shared(m_arr_vars); + var.second->setArrayInfo(arrVarsp); + } + os << "(declare-fun " << var.first << " () "; + var.second->emitType(os); + os << ")\n"; + } + + // Assert all user constraints + for (const std::string& constraint : m_constraints) { + os << "(assert (= #b1 " << constraint << "))\n"; + } + + // Incrementally enumerate all valid values for this randc variable + while (true) { + os << "(check-sat)\n"; + std::string sat; + do { std::getline(os, sat); } while (sat.empty()); + if (sat != "sat") break; + + // Read just this variable's value + os << "(get-value (" << varName << "))\n"; + char c; + os >> c; // '(' + os >> c; // '(' + std::string name, value; + os >> name; // Consume variable name token from solver output + (void)name; + std::getline(os, value, ')'); + os >> c; // ')' + + // Parse the SMT value to uint64_t + VlWide qowp; + VL_SET_WQ(qowp, 0ULL); + if (!parseSMTNum(width, qowp, value)) break; + const uint64_t numVal = (width <= 32) ? qowp[0] : VL_SET_QW(qowp); + + values.push_back(numVal); + + // Exclude this value for next iteration (incremental) + os << "(assert (not (= " << varName << " (_ bv" << numVal << " " << width << "))))\n"; + } + + os << "(reset)\n"; + + // Shuffle using Fisher-Yates + for (size_t i = values.size(); i > 1; --i) { + const size_t j = VL_RANDOM_RNG_I(rngr) % i; + std::swap(values[i - 1], values[j]); + } + + m_randcValueQueues[varName] = std::deque(values.begin(), values.end()); +} + bool VlRandomizer::next(VlRNG& rngr) { - if (m_vars.empty()) return true; + if (m_vars.empty() && m_unique_arrays.empty()) return true; + for (const std::string& baseName : m_unique_arrays) { + const auto it = m_vars.find(baseName); + const uint32_t size = m_unique_array_sizes.at(baseName); + + if (it != m_vars.end()) { + std::string distinctExpr = "(__Vbv (distinct"; + for (uint32_t i = 0; i < size; ++i) { + char hexIdx[12]; + sprintf(hexIdx, "#x%08x", i); + distinctExpr += " (select " + it->first + " " + hexIdx + ")"; + } + distinctExpr += "))"; + m_constraints.push_back(distinctExpr); + } + } + + // Randc queue-based cycling: enumerate valid values once, then pop per call + if (!m_randcVarNames.empty()) { + const size_t currentHash = hashConstraints(); + // Invalidate queues if constraints changed (e.g., constraint_mode toggled) + if (currentHash != m_randcConstraintHash) { + m_randcValueQueues.clear(); + m_randcConstraintHash = currentHash; + } + // Refill empty queues (start of new cycle) + for (const auto& name : m_randcVarNames) { + auto& queue = m_randcValueQueues[name]; + if (queue.empty()) enumerateRandcValues(name, rngr); + } + } + + // Pop randc values from queues (will be pinned in solver) + std::map randcPinned; + for (const auto& name : m_randcVarNames) { + auto& queue = m_randcValueQueues[name]; + if (queue.empty()) return false; // No valid values exist + randcPinned[name] = queue.front(); + queue.pop_front(); + } + + // If solve-before constraints are present, use phased solving + if (!m_solveBefore.empty()) return nextPhased(rngr); + std::iostream& os = getSolver(); if (!os) return false; @@ -384,13 +509,44 @@ bool VlRandomizer::next(VlRNG& rngr) { var.second->emitType(os); os << ")\n"; } + for (const std::string& constraint : m_constraints) { os << "(assert (= #b1 " << constraint << "))\n"; } + + // Pin randc values from pre-enumerated queues + for (const auto& pair : randcPinned) { + const int w = m_vars.at(pair.first)->width(); + os << "(assert (= " << pair.first << " (_ bv" << pair.second << " " << w << ")))\n"; + } + os << "(check-sat)\n"; - bool sat = parseSolution(os); + bool sat = parseSolution(os, true); if (!sat) { + // If unsat, use named assertions to get unsat-core + os << "(reset)\n"; + os << "(set-option :produce-unsat-cores true)\n"; + os << "(set-logic QF_ABV)\n"; + os << "(define-fun __Vbv ((b Bool)) (_ BitVec 1) (ite b #b1 #b0))\n"; + os << "(define-fun __Vbool ((v (_ BitVec 1))) Bool (= #b1 v))\n"; + for (const auto& var : m_vars) { + if (var.second->dimension() > 0) { + auto arrVarsp = std::make_shared(m_arr_vars); + var.second->setArrayInfo(arrVarsp); + } + os << "(declare-fun " << var.first << " () "; + var.second->emitType(os); + os << ")\n"; + } + int j = 0; + for (const std::string& constraint : m_constraints) { + os << "(assert (! (= #b1 " << constraint << ") :named cons" << j << "))\n"; + j++; + } + os << "(check-sat)\n"; + sat = parseSolution(os, true); + (void)sat; os << "(reset)\n"; return false; } @@ -399,18 +555,68 @@ bool VlRandomizer::next(VlRNG& rngr) { randomConstraint(os, rngr, _VL_SOLVER_HASH_LEN); os << ")\n"; os << "\n(check-sat)\n"; - sat = parseSolution(os); + sat = parseSolution(os, false); + (void)sat; } os << "(reset)\n"; return true; } -bool VlRandomizer::parseSolution(std::iostream& os) { +bool VlRandomizer::parseSolution(std::iostream& os, bool log) { std::string sat; do { std::getline(os, sat); } while (sat == ""); - - if (sat == "unsat") return false; + if (sat == "unsat") { + if (!log) return false; + os << "(get-unsat-core) \n"; + sat.clear(); + std::getline(os, sat); + std::vector numbers; + std::string currentNum; + for (char c : sat) { + if (std::isdigit(c)) { + currentNum += c; + numbers.push_back(std::stoi(currentNum)); + currentNum.clear(); + } + } + if (Verilated::threadContextp()->warnUnsatConstr()) { + for (int n : numbers) { + if (n < m_constraints_line.size()) { + const std::string& constraint_info = m_constraints_line[n]; + // Parse "filename:linenum source" format + size_t colon_pos = constraint_info.find(':'); + if (colon_pos != std::string::npos) { + std::string filename = constraint_info.substr(0, colon_pos); + size_t space_pos = constraint_info.find(" ", colon_pos); + std::string linenum_str; + std::string source; + if (space_pos != std::string::npos) { + linenum_str + = constraint_info.substr(colon_pos + 1, space_pos - colon_pos - 1); + source = constraint_info.substr(space_pos + 3); + } else { + linenum_str = constraint_info.substr(colon_pos + 1); + } + const int linenum = std::stoi(linenum_str); + std::string msg = "UNSATCONSTR: Unsatisfied constraint"; + if (!source.empty()) { + // Trim leading whitespace and add quotes + size_t start = source.find_first_not_of(" \t"); + if (start != std::string::npos) { + msg += ": '" + source.substr(start) + "'"; + } + } + VL_WARN_MT(filename.c_str(), linenum, "", msg.c_str()); + } else { + VL_PRINTF("%%Warning-UNSATCONSTR: Unsatisfied constraint: %s\n", + constraint_info.c_str()); + } + } + } + } + return false; + } if (sat != "sat") { std::stringstream msg; msg << "Internal: Solver error: " << sat; @@ -501,18 +707,253 @@ bool VlRandomizer::parseSolution(std::iostream& os) { return true; } -void VlRandomizer::hard(std::string&& constraint) { +void VlRandomizer::hard(std::string&& constraint, const char* filename, uint32_t linenum, + const char* source) { m_constraints.emplace_back(std::move(constraint)); + // Format constraint location: "filename:linenum source" + if (filename[0] != '\0' || source[0] != '\0') { + std::string line; + if (filename[0] != '\0') { + line = std::string(filename) + ":" + std::to_string(linenum); + if (source[0] != '\0') line += " " + std::string(source); + } else { + line = source; + } + m_constraints_line.emplace_back(std::move(line)); + } } void VlRandomizer::clearConstraints() { m_constraints.clear(); + m_constraints_line.clear(); + m_solveBefore.clear(); // Keep m_vars for class member randomization } void VlRandomizer::clearAll() { m_constraints.clear(); m_vars.clear(); + m_randcVarNames.clear(); + m_randcValueQueues.clear(); + m_randcConstraintHash = 0; +} + +void VlRandomizer::markRandc(const char* name) { m_randcVarNames.insert(name); } + +void VlRandomizer::solveBefore(const char* beforeName, const char* afterName) { + m_solveBefore.emplace_back(std::string(beforeName), std::string(afterName)); +} + +bool VlRandomizer::nextPhased(VlRNG& rngr) { + // Phased solving for solve...before constraints. + // Variables are solved in layers determined by topological sort of the + // solve-before dependency graph. Each layer is solved with ALL constraints + // (preserving the solution space) but earlier layers' values are pinned. + + // Step 1: Build dependency graph (before -> {after vars}) + std::map> graph; + std::map inDegree; + std::set solveBeforeVars; + + for (const auto& pair : m_solveBefore) { + const std::string& before = pair.first; + const std::string& after = pair.second; + // Only consider variables that are actually registered + if (m_vars.find(before) == m_vars.end() || m_vars.find(after) == m_vars.end()) continue; + graph[before].insert(after); + solveBeforeVars.insert(before); + solveBeforeVars.insert(after); + if (inDegree.find(before) == inDegree.end()) inDegree[before] = 0; + if (inDegree.find(after) == inDegree.end()) inDegree[after] = 0; + } + + // Compute in-degrees (after depends on before, so edge is before->after, + // but for solving order: before has no incoming edge from after) + // Actually: "solve x before y" means x should be solved first. + // Dependency: y depends on x. Edge: x -> y. in-degree of y increases. + for (const auto& entry : graph) { + for (const auto& to : entry.second) { inDegree[to]++; } + } + + // Step 2: Topological sort into layers (Kahn's algorithm) + std::vector> layers; + std::set remaining = solveBeforeVars; + + while (!remaining.empty()) { + std::vector currentLayer; + for (const auto& var : remaining) { + if (inDegree[var] == 0) currentLayer.push_back(var); + } + if (currentLayer.empty()) { + VL_WARN_MT("", 0, "randomize", "Circular dependency in solve-before constraints"); + return false; + } + std::sort(currentLayer.begin(), currentLayer.end()); + for (const auto& var : currentLayer) { + remaining.erase(var); + if (graph.count(var)) { + for (const auto& to : graph[var]) { inDegree[to]--; } + } + } + layers.push_back(std::move(currentLayer)); + } + + // If only one layer, no phased solving needed -- fall through to normal path + // (all solve_before vars are independent, no actual ordering required) + if (layers.size() <= 1) { + // Clear solve_before temporarily and call normal next() + const auto saved = std::move(m_solveBefore); + m_solveBefore.clear(); + const bool result = next(rngr); + m_solveBefore = std::move(saved); + return result; + } + + // Step 3: Solve phase by phase + std::map solvedValues; // varName -> SMT value literal + + for (size_t phase = 0; phase < layers.size(); phase++) { + const bool isFinalPhase = (phase == layers.size() - 1); + + std::iostream& os = getSolver(); + if (!os) return false; + + // Solver session setup + os << "(set-option :produce-models true)\n"; + os << "(set-logic QF_ABV)\n"; + os << "(define-fun __Vbv ((b Bool)) (_ BitVec 1) (ite b #b1 #b0))\n"; + os << "(define-fun __Vbool ((v (_ BitVec 1))) Bool (= #b1 v))\n"; + + // Declare ALL variables + for (const auto& var : m_vars) { + if (var.second->dimension() > 0) { + auto arrVarsp = std::make_shared(m_arr_vars); + var.second->setArrayInfo(arrVarsp); + } + os << "(declare-fun " << var.first << " () "; + var.second->emitType(os); + os << ")\n"; + } + + // Pin all previously solved variables + for (const auto& entry : solvedValues) { + os << "(assert (= " << entry.first << " " << entry.second << "))\n"; + } + + // Assert ALL constraints + for (const std::string& constraint : m_constraints) { + os << "(assert (= #b1 " << constraint << "))\n"; + } + + // Initial check-sat WITHOUT diversity (guaranteed sat if constraints are consistent) + os << "(check-sat)\n"; + + if (isFinalPhase) { + // Final phase: use parseSolution to write ALL values to memory + bool sat = parseSolution(os, true); + if (!sat) { + os << "(reset)\n"; + return false; + } + // Diversity loop (same as normal next()) + for (int i = 0; i < _VL_SOLVER_HASH_LEN_TOTAL && sat; ++i) { + os << "(assert "; + randomConstraint(os, rngr, _VL_SOLVER_HASH_LEN); + os << ")\n"; + os << "\n(check-sat)\n"; + sat = parseSolution(os, false); + (void)sat; + } + os << "(reset)\n"; + } else { + // Intermediate phase: extract values for current layer variables only + std::string satResponse; + do { std::getline(os, satResponse); } while (satResponse.empty()); + + if (satResponse != "sat") { + os << "(reset)\n"; + return false; + } + + // Build get-value variable list for this layer + const auto& layerVars = layers[phase]; + auto getValueCmd = [&]() { + os << "(get-value ("; + for (const auto& varName : layerVars) { + if (m_vars.count(varName)) os << varName << " "; + } + os << "))\n"; + }; + + // Helper to parse ((name1 value1) (name2 value2) ...) response + auto parseGetValue = [&]() -> bool { + char c; + os >> c; // outer '(' + while (true) { + os >> c; + if (c == ')') break; // outer closing + if (c != '(') return false; + std::string name; + os >> name; + + // Read value handling nested parens for (_ bvN W) format + os >> std::ws; + std::string value; + char firstChar; + os.get(firstChar); + if (firstChar == '(') { + // Compound value like (_ bv5 32) + value = "("; + int depth = 1; + while (depth > 0) { + os.get(c); + value += c; + if (c == '(') + depth++; + else if (c == ')') + depth--; + } + // Read closing ')' of the pair + os >> c; + } else { + // Atom value like #x00000005 or #b101 + value += firstChar; + while (os.get(c) && c != ')') { value += c; } + // Trim trailing whitespace + const size_t end = value.find_last_not_of(" \t\n\r"); + if (end != std::string::npos) value = value.substr(0, end + 1); + } + + solvedValues[name] = value; + } + return true; + }; + + // Get baseline values (deterministic, always valid) + getValueCmd(); + if (!parseGetValue()) { + os << "(reset)\n"; + return false; + } + + // Try diversity: add random constraint, re-check. If sat, get + // updated (more diverse) values. If unsat, keep baseline values. + os << "(assert "; + randomConstraint(os, rngr, _VL_SOLVER_HASH_LEN); + os << ")\n"; + os << "(check-sat)\n"; + satResponse.clear(); + do { std::getline(os, satResponse); } while (satResponse.empty()); + if (satResponse == "sat") { + getValueCmd(); + parseGetValue(); + } + + os << "(reset)\n"; + } + } + + return true; } #ifdef VL_DEBUG diff --git a/include/verilated_random.h b/include/verilated_random.h index 0b68eadcf..53c09f071 100644 --- a/include/verilated_random.h +++ b/include/verilated_random.h @@ -3,9 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU Lesser -// General Public License Version 3 or the Perl Artistic License Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -27,6 +28,7 @@ #include "verilated.h" +#include #include #include #include @@ -195,20 +197,32 @@ public: }; //============================================================================= - // Object holding constraints and variable references. class VlRandomizer VL_NOT_FINAL { // MEMBERS std::vector m_constraints; // Solver-dependent constraints + std::vector + m_constraints_line; // fileline content of the constraint for unsat constraints std::map> m_vars; // Solver-dependent // variables ArrayInfoMap m_arr_vars; // Tracks each element in array structures for iteration + std::vector m_unique_arrays; + std::map m_unique_array_sizes; const VlQueue* m_randmodep = nullptr; // rand_mode state; int m_index = 0; // Internal counter for key generation + std::set m_randcVarNames; // Names of randc variables for cyclic tracking + std::map> + m_randcValueQueues; // Remaining values per randc var (queue-based cycling) + size_t m_randcConstraintHash = 0; // Hash of constraints when queues were built + std::vector> + m_solveBefore; // Solve-before ordering pairs (beforeVar, afterVar) // PRIVATE METHODS void randomConstraint(std::ostream& os, VlRNG& rngr, int bits); - bool parseSolution(std::iostream& file); + bool parseSolution(std::iostream& file, bool log = false); + void enumerateRandcValues(const std::string& varName, VlRNG& rngr); + size_t hashConstraints() const; + bool nextPhased(VlRNG& rngr); // Phased solving for solve...before public: // CONSTRUCTORS @@ -315,10 +329,10 @@ public: } // --- write_var to register variables --- - // Register scalar variable (non-struct, basic type) template - typename std::enable_if::value, void>::type + typename std::enable_if::value && !IsVlUnpacked::value, + void>::type write_var(T& var, int width, const char* name, int dimension, std::uint32_t randmodeIdx = std::numeric_limits::max()) { if (m_vars.find(name) != m_vars.end()) return; @@ -356,21 +370,23 @@ public: std::uint32_t randmodeIdx = std::numeric_limits::max()) { if (dimension > 0) record_struct_arr(var, name, dimension, {}, {}); } - // Register unpacked array of non-struct types template typename std::enable_if::value, void>::type - write_var(VlUnpacked& var, int width, const char* name, int dimension, + write_var(VlUnpacked& var, uint32_t width, const std::string& name, + uint32_t dimension, std::uint32_t randmodeIdx = std::numeric_limits::max()) { + if (m_vars.find(name) != m_vars.end()) return; + m_vars[name] = std::make_shared>>( name, width, &var, dimension, randmodeIdx); + if (dimension > 0) { m_index = 0; record_arr_table(var, name, dimension, {}, {}); } } - // Register unpacked array of structs template typename std::enable_if::value, void>::type @@ -414,6 +430,12 @@ public: ++m_index; } + // This is the "Sender" API for the generated code + void rand_unique(const std::string& name, uint32_t size) { + m_unique_arrays.push_back(name); + m_unique_array_sizes[name] = size; + } + // Recursively record all elements in an unpacked array template void record_arr_table(VlUnpacked& var, const std::string& name, int dimension, @@ -569,9 +591,13 @@ public: + std::to_string(idx); } - void hard(std::string&& constraint); + void hard(std::string&& constraint, const char* filename = "", uint32_t linenum = 0, + const char* source = ""); void clearConstraints(); void clearAll(); // Clear both constraints and variables + void markRandc(const char* name); // Mark variable as randc for cyclic tracking + void solveBefore(const char* beforeName, + const char* afterName); // Register solve-before ordering void set_randmode(const VlQueue& randmode) { m_randmodep = &randmode; } #ifdef VL_DEBUG void dump() const; @@ -628,6 +654,23 @@ public: for (size_t i = 0; i < N_Depth; ++i) { basicStdRandomization(value.operator[](i), width); } return true; } + + // Queue/dynamic array randomization + template + bool basicStdRandomization(VlQueue& value, size_t width) { + for (int i = 0; i < value.size(); ++i) { basicStdRandomization(value.atWrite(i), width); } + return true; + } + + // Associative array randomization + template + bool basicStdRandomization(VlAssocArray& value, size_t width) { + T_Key key; + for (int exists = value.first(key); exists; exists = value.next(key)) { + basicStdRandomization(value.at(key), width); + } + return true; + } bool next() { return VlRandomizer::next(m_rng); } }; diff --git a/include/verilated_saif_c.cpp b/include/verilated_saif_c.cpp index 593eb83aa..83237bb2f 100644 --- a/include/verilated_saif_c.cpp +++ b/include/verilated_saif_c.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_saif_c.h b/include/verilated_saif_c.h index f1b8e5690..28f35166c 100644 --- a/include/verilated_saif_c.h +++ b/include/verilated_saif_c.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_saif_sc.h b/include/verilated_saif_sc.h index f28f2437d..e0c5a50fa 100644 --- a/include/verilated_saif_sc.h +++ b/include/verilated_saif_sc.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp index 1554e379c..0569ba0aa 100644 --- a/include/verilated_save.cpp +++ b/include/verilated_save.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_save.h b/include/verilated_save.h index 4cfb7593c..aa547af68 100644 --- a/include/verilated_save.h +++ b/include/verilated_save.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2000-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2000-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_sc.h b/include/verilated_sc.h index b6fa0af5b..d59a9f5c9 100644 --- a/include/verilated_sc.h +++ b/include/verilated_sc.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/include/verilated_sc_trace.h b/include/verilated_sc_trace.h index 47331d33d..5f53b103c 100644 --- a/include/verilated_sc_trace.h +++ b/include/verilated_sc_trace.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_std.sv b/include/verilated_std.sv index b3c53a018..b86340695 100644 --- a/include/verilated_std.sv +++ b/include/verilated_std.sv @@ -4,9 +4,10 @@ // //************************************************************************* // -// Copyright 2022-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU Lesser -// General Public License Version 3 or the Perl Artistic License Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/include/verilated_std_waiver.vlt b/include/verilated_std_waiver.vlt index b47391dc5..e4f1fbf56 100644 --- a/include/verilated_std_waiver.vlt +++ b/include/verilated_std_waiver.vlt @@ -4,9 +4,10 @@ // //************************************************************************* // -// Copyright 2022-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU Lesser -// General Public License Version 3 or the Perl Artistic License Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/include/verilated_sym_props.h b/include/verilated_sym_props.h index c19d9f787..1cdd3a990 100644 --- a/include/verilated_sym_props.h +++ b/include/verilated_sym_props.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -156,9 +156,12 @@ public: return bits; } bool isPublicRW() const { return ((m_vlflags & VLVF_PUB_RW) != 0); } + bool isForceable() const { return ((m_vlflags & VLVF_FORCEABLE) != 0); } + bool isContinuously() const { return ((m_vlflags & VLVF_CONTINUOUSLY) != 0); } // DPI compatible C standard layout bool isDpiCLayout() const { return ((m_vlflags & VLVF_DPI_CLAY) != 0); } bool isSigned() const { return ((m_vlflags & VLVF_SIGNED) != 0); } + bool isBitVar() const { return ((m_vlflags & VLVF_BITVAR) != 0); } int udims() const VL_MT_SAFE { return m_unpacked.size(); } int pdims() const VL_MT_SAFE { return m_packed.size(); } int dims() const VL_MT_SAFE { return pdims() + udims(); } diff --git a/include/verilated_syms.h b/include/verilated_syms.h index e7c8d79dd..949dbde9e 100644 --- a/include/verilated_syms.h +++ b/include/verilated_syms.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/include/verilated_threads.cpp b/include/verilated_threads.cpp index f3149d50e..d814b585c 100644 --- a/include/verilated_threads.cpp +++ b/include/verilated_threads.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2012-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= @@ -137,7 +137,7 @@ VlThreadPool::VlThreadPool(VerilatedContext* contextp, unsigned nThreads) { m_workers.push_back(new VlWorkerThread{contextp}); m_unassignedWorkers.push(i); } - m_numaStatus = numaAssign(); + m_numaStatus = numaAssign(contextp); } VlThreadPool::~VlThreadPool() { @@ -145,8 +145,15 @@ VlThreadPool::~VlThreadPool() { for (auto& i : m_workers) delete i; } -std::string VlThreadPool::numaAssign() { +std::string VlThreadPool::numaAssign(VerilatedContext* contextp) { #if defined(__linux) || defined(CPU_ZERO) || defined(VL_CPPCHECK) // Linux-like pthreads + if (contextp && !contextp->useNumaAssign()) { return "NUMA assignment not requested"; } + std::string numa_strategy = VlOs::getenvStr("VERILATOR_NUMA_STRATEGY", "default"); + if (numa_strategy == "none") { + return "no NUMA assignment requested"; + } else if (numa_strategy != "default" && numa_strategy != "") { + return "%Warning: unknown VERILATOR_NUMA_STRATEGY value '" + numa_strategy + "'"; + } // Get number of processor available to the current process const unsigned num_proc = VlOs::getProcessAvailableParallelism(); if (!num_proc) return "Can't determine number of available threads"; diff --git a/include/verilated_threads.h b/include/verilated_threads.h index 3dfa5ba4f..9ac23392b 100644 --- a/include/verilated_threads.h +++ b/include/verilated_threads.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2012-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= @@ -254,7 +254,7 @@ public: private: VL_UNCOPYABLE(VlThreadPool); - std::string numaAssign(); + std::string numaAssign(VerilatedContext* contextp); }; #endif diff --git a/include/verilated_timing.cpp b/include/verilated_timing.cpp index ea819c16d..51dd88b9a 100644 --- a/include/verilated_timing.cpp +++ b/include/verilated_timing.cpp @@ -3,9 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2022 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU Lesser -// General Public License Version 3 or the Perl Artistic License Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= @@ -66,19 +67,6 @@ void VlDelayScheduler::resume() { resumed = true; } - if (!m_zeroDelayed.empty()) { - // First, we need to move the coroutines out of the queue, as a resumed coroutine can - // suspend on #0 again, adding itself to the queue, which can result in reallocating the - // queue mid-iteration. - // We swap with the m_zeroDlyResumed field to keep the allocated buffer. - m_zeroDlyResumed.swap(m_zeroDelayed); - for (auto&& handle : m_zeroDlyResumed) handle.resume(); - m_zeroDlyResumed.clear(); - resumed = true; - // We are now in the Active region, so any coroutines added to m_zeroDelayed in the - // meantime will have to wait until the next Inactive region. - } - if (!resumed) { if (m_context.time() == 0) { // Nothing was scheduled at time 0, but resume() got called due to --x-initial-edge @@ -91,6 +79,12 @@ void VlDelayScheduler::resume() { } } +void VlDelayScheduler::resumeZeroDelay() { + m_zeroDelayesSwap.swap(m_zeroDelayed); + for (VlCoroutineHandle& handle : m_zeroDelayesSwap) handle.resume(); + m_zeroDelayesSwap.clear(); +} + uint64_t VlDelayScheduler::nextTimeSlot() const { if (!m_queue.empty()) return m_queue.cbegin()->first; if (m_zeroDelayed.empty()) @@ -100,7 +94,7 @@ uint64_t VlDelayScheduler::nextTimeSlot() const { #ifdef VL_DEBUG void VlDelayScheduler::dump() const { - if (m_queue.empty()) { + if (m_queue.empty() && m_zeroDelayed.empty()) { VL_DBG_MSGF(" No delayed processes:\n"); } else { VL_DBG_MSGF(" Delayed processes:\n"); @@ -126,44 +120,65 @@ void VlTriggerScheduler::resume(const char* eventDescription) { VL_DEBUG_IF(dump(eventDescription); VL_DBG_MSGF(" Resuming processes waiting for %s\n", eventDescription);); #endif - std::swap(m_ready, m_resumeQueue); - for (VlCoroutineHandle& coro : m_resumeQueue) coro.resume(); - m_resumeQueue.clear(); - commit(eventDescription); + for (VlCoroutineHandle& coro : m_toResume) coro.resume(); + m_toResume.clear(); } -void VlTriggerScheduler::commit(const char* eventDescription) { +void VlTriggerScheduler::moveToResumeQueue(const char* eventDescription) { #ifdef VL_DEBUG - if (!m_uncommitted.empty()) { + if (!m_fired.empty()) { + VL_DEBUG_IF(VL_DBG_MSGF(" Moving to resume queue processes waiting for %s:\n", + eventDescription); + for (const auto& susp + : m_fired) { + VL_DBG_MSGF(" - "); + susp.dump(); + }); + } +#endif + std::swap(m_fired, m_toResume); +} + +void VlTriggerScheduler::ready(const char* eventDescription) { +#ifdef VL_DEBUG + if (!m_awaiting.empty()) { VL_DEBUG_IF( VL_DBG_MSGF(" Committing processes waiting for %s:\n", eventDescription); for (const auto& susp - : m_uncommitted) { + : m_awaiting) { VL_DBG_MSGF(" - "); susp.dump(); }); } #endif - m_ready.reserve(m_ready.size() + m_uncommitted.size()); - m_ready.insert(m_ready.end(), std::make_move_iterator(m_uncommitted.begin()), - std::make_move_iterator(m_uncommitted.end())); - m_uncommitted.clear(); + const size_t expectedSize = m_fired.size() + m_awaiting.size(); + if (m_fired.capacity() < expectedSize) m_fired.reserve(expectedSize * 2); + m_fired.insert(m_fired.end(), std::make_move_iterator(m_awaiting.begin()), + std::make_move_iterator(m_awaiting.end())); + m_awaiting.clear(); } #ifdef VL_DEBUG void VlTriggerScheduler::dump(const char* eventDescription) const { - if (m_ready.empty()) { - VL_DBG_MSGF(" No ready processes waiting for %s\n", eventDescription); + if (m_toResume.empty()) { + VL_DBG_MSGF(" No process to resume waiting for %s\n", eventDescription); } else { - for (const auto& susp : m_ready) { - VL_DBG_MSGF(" Ready processes waiting for %s:\n", eventDescription); + for (const auto& susp : m_toResume) { + VL_DBG_MSGF(" Processes to resume waiting for %s:\n", eventDescription); VL_DBG_MSGF(" - "); susp.dump(); } } - if (!m_uncommitted.empty()) { - VL_DBG_MSGF(" Uncommitted processes waiting for %s:\n", eventDescription); - for (const auto& susp : m_uncommitted) { + if (!m_fired.empty()) { + VL_DBG_MSGF(" Triggered processes waiting for %s:\n", eventDescription); + for (const auto& susp : m_awaiting) { + VL_DBG_MSGF(" - "); + susp.dump(); + } + } + if (!m_awaiting.empty()) { + VL_DBG_MSGF(" Not triggered processes waiting for %s:\n", eventDescription); + for (const auto& susp : m_awaiting) { VL_DBG_MSGF(" - "); susp.dump(); } diff --git a/include/verilated_timing.h b/include/verilated_timing.h index 35b7d1ea7..a657ac458 100644 --- a/include/verilated_timing.h +++ b/include/verilated_timing.h @@ -3,9 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2022 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU Lesser -// General Public License Version 3 or the Perl Artistic License Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -27,6 +28,7 @@ #include "verilated.h" +#include #include // clang-format off @@ -169,9 +171,8 @@ class VlDelayScheduler final { VerilatedContext& m_context; VlDelayedCoroutineQueue m_queue; // Coroutines to be restored at a certain simulation time std::vector m_zeroDelayed; // Coroutines waiting for #0 - std::vector m_zeroDlyResumed; // Coroutines that waited for #0 and are - // to be resumed. Kept as a field to avoid - // reallocation. + // Coroutines that waited for #0 and are being resumed now. As member to avoid reallocations + std::vector m_zeroDelayesSwap; public: // CONSTRUCTORS @@ -180,6 +181,8 @@ public: // METHODS // Resume coroutines waiting for the current simulation time void resume(); + // Resume coroutines waiting for #0 + void resumeZeroDelay(); // Returns the simulation time of the next time slot (aborts if there are no delayed // coroutines) uint64_t nextTimeSlot() const; @@ -187,9 +190,10 @@ public: bool empty() const { return m_queue.empty() && m_zeroDelayed.empty(); } // Are there coroutines to resume at the current simulation time? bool awaitingCurrentTime() const { - return (!m_queue.empty() && (m_queue.cbegin()->first <= m_context.time())) - || !m_zeroDelayed.empty(); + return (!m_queue.empty() && (m_queue.cbegin()->first <= m_context.time())); } + // Are there coroutines to resume in the inactive region after a #0 delay? + bool awaitingZeroDelay() const { return !m_zeroDelayed.empty(); } #ifdef VL_DEBUG void dump() const; #endif @@ -206,7 +210,8 @@ public: bool await_ready() const { return false; } // Always suspend void await_suspend(std::coroutine_handle<> coro) { - if (phase == VlDelayPhase::ACTIVE) { + // Both active delays and fork..join_none #0 are resumed out of the time queue. + if (phase != VlDelayPhase::INACTIVE) { queue.emplace(delay, VlCoroutineHandle{coro, process, fileline}); } else { queueZeroDelay.emplace_back(VlCoroutineHandle{coro, process, fileline}); @@ -215,15 +220,14 @@ public: void await_resume() const {} }; - const VlDelayPhase phase = (delay == 0) ? VlDelayPhase::INACTIVE : VlDelayPhase::ACTIVE; -#ifdef VL_DEBUG - if (phase == VlDelayPhase::INACTIVE) { - VL_WARN_MT(filename, lineno, VL_UNKNOWN, - "Encountered #0 delay. #0 scheduling support is incomplete and the " - "process will be resumed before combinational logic evaluation."); + VlDelayPhase phase; + if (delay != 0) { + // UINT64_MAX is a sentinel for synthetic fork..join_none delays. + if (delay == std::numeric_limits::max()) delay = 0; + phase = VlDelayPhase::ACTIVE; + } else { + phase = VlDelayPhase::INACTIVE; } -#endif - return Awaitable{process, m_queue, m_zeroDelayed, m_context.time() + delay, phase, VlFileLineDebug{filename, lineno}}; @@ -232,38 +236,40 @@ public: //============================================================================= // VlTriggerScheduler stores coroutines to be resumed by a trigger. It does not keep track of its -// trigger, relying on calling code to resume when appropriate. Coroutines are kept in two stages -// - 'uncommitted' and 'ready'. Whenever a coroutine is suspended, it lands in the 'uncommitted' -// stage. Only when commit() is called, these coroutines get moved to the 'ready' stage. That's -// when they can be resumed. This is done to avoid resuming processes before they start waiting. +// trigger, relying on calling code to resume when appropriate. Coroutines are kept in three stages +// - 'awaiting', 'fired' and 'toResume'. Whenever a coroutine is suspended, it lands in the +// 'awaiting' stage. Only when ready() is called, these coroutines get moved to the 'fired' stage. +// When moveToResumeQueue() is begin called all coroutines from 'ready' are moved to 'toResume'. +// That's when they can be resumed. This is done to avoid resuming processes before they start +// waiting. class VlTriggerScheduler final { // TYPES using VlCoroutineVec = std::vector; // MEMBERS - VlCoroutineVec m_uncommitted; // Coroutines suspended before commit() was called - // (not resumable) - VlCoroutineVec m_ready; // Coroutines that can be resumed (all coros from m_uncommitted are - // moved here in commit()) - VlCoroutineVec m_resumeQueue; // Coroutines being resumed by resume(); kept as a field to - // avoid reallocation. Resumed coroutines are moved to - // m_resumeQueue to allow adding coroutines to m_ready - // during resume(). Outside of resume() should always be empty. + VlCoroutineVec m_awaiting; // Coroutines suspended before ready() was called + // (not resumable) + VlCoroutineVec m_fired; // Coroutines that were triggered (all coros from m_awaiting are moved + // here in ready()) + VlCoroutineVec m_toResume; // Coroutines to resume in next resumePrep() + // - moved here in commit() public: // METHODS - // Resumes all coroutines from the 'ready' stage + // Resumes all coroutines from the m_toResume void resume(const char* eventDescription = VL_UNKNOWN); - // Moves all coroutines from m_uncommitted to m_ready - void commit(const char* eventDescription = VL_UNKNOWN); + // Moves all coroutines from m_fired to m_toResume + void moveToResumeQueue(const char* eventDescription = VL_UNKNOWN); + // Moves all coroutines from m_awaiting to m_fired + void ready(const char* eventDescription = VL_UNKNOWN); // Are there no coroutines awaiting? - bool empty() const { return m_ready.empty() && m_uncommitted.empty(); } + bool empty() const { return m_fired.empty() && m_awaiting.empty(); } #ifdef VL_DEBUG void dump(const char* eventDescription) const; #endif // Used by coroutines for co_awaiting a certain trigger - auto trigger(bool commit, VlProcessRef process, const char* eventDescription = VL_UNKNOWN, + auto trigger(bool ready, VlProcessRef process, const char* eventDescription = VL_UNKNOWN, const char* filename = VL_UNKNOWN, int lineno = 0) { VL_DEBUG_IF(VL_DBG_MSGF(" Suspending process waiting for %s at %s:%d\n", eventDescription, filename, lineno);); @@ -278,8 +284,7 @@ public: } void await_resume() const {} }; - return Awaitable{commit ? m_ready : m_uncommitted, process, - VlFileLineDebug{filename, lineno}}; + return Awaitable{ready ? m_fired : m_awaiting, process, VlFileLineDebug{filename, lineno}}; } }; diff --git a/include/verilated_trace.h b/include/verilated_trace.h index 38071b67a..15e3cd964 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= @@ -233,22 +233,41 @@ private: }; const uint32_t m_fidx; // The index of the tracing function void* const m_userp; // The user pointer to pass to the callback (the symbol table) - CallbackRecord(initCb_t cb, void* userp) + const bool m_isLibInstance; // Whether the callback is for a --lib-create instance + const std::string m_name; // The name of the instance callback is for + const uint32_t m_nTraceCodes; // The number of trace codes used by callback + CallbackRecord(initCb_t cb, void* userp, bool isLibInstance, const std::string& name, + uint32_t nTraceCodes) : m_initCb{cb} , m_fidx{0} - , m_userp{userp} {} + , m_userp{userp} + , m_isLibInstance{isLibInstance} + , m_name{name} + , m_nTraceCodes{nTraceCodes} {} CallbackRecord(dumpCb_t cb, uint32_t fidx, void* userp) : m_dumpCb{cb} , m_fidx{fidx} - , m_userp{userp} {} + , m_userp{userp} + , m_isLibInstance{false} // Don't care + , m_name{} // Don't care + , m_nTraceCodes{0} // Don't care + {} CallbackRecord(dumpOffloadCb_t cb, uint32_t fidx, void* userp) : m_dumpOffloadCb{cb} , m_fidx{fidx} - , m_userp{userp} {} + , m_userp{userp} + , m_isLibInstance{false} // Don't care + , m_name{} // Don't care + , m_nTraceCodes{0} // Don't care + {} CallbackRecord(cleanupCb_t cb, void* userp) : m_cleanupCb{cb} , m_fidx{0} - , m_userp{userp} {} + , m_userp{userp} + , m_isLibInstance{false} // Don't care + , m_name{} // Don't care + , m_nTraceCodes{0} // Don't care + {} }; bool m_offload = false; // Use the offload thread @@ -292,6 +311,7 @@ private: uint32_t m_nextCode = 0; // Next code number to assign uint32_t m_numSignals = 0; // Number of distinct signals uint32_t m_maxBits = 0; // Number of bits in the widest signal + void* m_initUserp = nullptr; // The callback userp of the instance currently being initialized // TODO: Should keep this as a Trie, that is how it's accessed all the time. std::vector> m_dumpvars; // dumpvar() entries double m_timeRes = 1e-9; // Time resolution (ns/ms etc) @@ -359,6 +379,7 @@ protected: uint32_t nextCode() const { return m_nextCode; } uint32_t numSignals() const { return m_numSignals; } uint32_t maxBits() const { return m_maxBits; } + void* initUserp() const { return m_initUserp; } void constDump(bool value) { m_constDump = value; } void fullDump(bool value) { m_fullDump = value; } @@ -429,7 +450,8 @@ public: // Non-hot path internal interface to Verilator generated code void addModel(VerilatedModel*) VL_MT_SAFE_EXCLUDES(m_mutex); - void addInitCb(initCb_t cb, void* userp) VL_MT_SAFE; + void addInitCb(initCb_t cb, void* userp, const std::string& name, bool isLibInstance, + uint32_t nTraceCodes) VL_MT_SAFE; void addConstCb(dumpCb_t cb, uint32_t fidx, void* userp) VL_MT_SAFE; void addConstCb(dumpOffloadCb_t cb, uint32_t fidx, void* userp) VL_MT_SAFE; void addFullCb(dumpCb_t cb, uint32_t fidx, void* userp) VL_MT_SAFE; @@ -437,6 +459,7 @@ public: void addChgCb(dumpCb_t cb, uint32_t fidx, void* userp) VL_MT_SAFE; void addChgCb(dumpOffloadCb_t cb, uint32_t fidx, void* userp) VL_MT_SAFE; void addCleanupCb(cleanupCb_t cb, void* userp) VL_MT_SAFE; + void initLib(const std::string& name) VL_MT_UNSAFE; }; //============================================================================= diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h index 66e3d45eb..635e3e897 100644 --- a/include/verilated_trace_imp.h +++ b/include/verilated_trace_imp.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= @@ -312,10 +312,17 @@ void VerilatedTrace::traceInit() VL_MT_UNSAFE { m_maxBits = 0; m_sigs_enabledVec.clear(); - // Call all initialize callbacks, which will: + // Call all initialize callbacks for root (non-library) instances, which will: // - Call decl* for each signal (these eventually call ::declCode) + // - Call the initialize callbacks of library instances underneath // - Store the base code - for (const CallbackRecord& cbr : m_initCbs) cbr.m_initCb(cbr.m_userp, self(), nextCode()); + for (const CallbackRecord& cbr : m_initCbs) { + if (cbr.m_isLibInstance) continue; // Will be called from parent callback + const uint32_t baseCode = nextCode(); + m_nextCode += cbr.m_nTraceCodes; + m_initUserp = cbr.m_userp; + cbr.m_initCb(cbr.m_userp, self(), baseCode); + } if (expectedCodes && nextCode() != expectedCodes) { VL_FATAL_MT(__FILE__, __LINE__, "", @@ -352,8 +359,8 @@ void VerilatedTrace::traceInit() VL_MT_UNSAFE { // each signal, which is 'nextCode()' entries after the init callbacks // above have been run, plus up to 2 more words of metadata per signal, // plus fixed overhead of 1 for a termination flag and 3 for a time stamp - // update. - m_offloadBufferSize = nextCode() + numSignals() * 2 + 4; + // update and 2 for the buffer address. + m_offloadBufferSize = nextCode() + numSignals() * 2 + 6; // Start the worker thread m_workerThread.reset( @@ -393,8 +400,6 @@ bool VerilatedTrace::declCode(uint32_t code, const std::stri break; } - int codesNeeded = VL_WORDS_I(bits); - m_nextCode = std::max(m_nextCode, code + codesNeeded); ++m_numSignals; m_maxBits = std::max(m_maxBits, bits); return enabled; @@ -680,8 +685,10 @@ void VerilatedTrace::addCallbackRecord(std::vector -void VerilatedTrace::addInitCb(initCb_t cb, void* userp) VL_MT_SAFE { - addCallbackRecord(m_initCbs, CallbackRecord{cb, userp}); +void VerilatedTrace::addInitCb(initCb_t cb, void* userp, + const std::string& name, bool isLibInstance, + uint32_t nTraceCodes) VL_MT_SAFE { + addCallbackRecord(m_initCbs, CallbackRecord{cb, userp, isLibInstance, name, nTraceCodes}); } template <> void VerilatedTrace::addConstCb(dumpCb_t cb, uint32_t fidx, @@ -718,6 +725,20 @@ void VerilatedTrace::addCleanupCb(cleanupCb_t cb, void* user addCallbackRecord(m_cleanupCbs, CallbackRecord{cb, userp}); } +template <> +void VerilatedTrace::initLib(const std::string& name) VL_MT_SAFE { + // Note it's possible the instance doesn't exist if the lib was compiled without tracing + void* const prevInitUserp = m_initUserp; + for (const CallbackRecord& cbr : m_initCbs) { + if (cbr.m_name != name) continue; + const uint32_t baseCode = nextCode(); + m_nextCode += cbr.m_nTraceCodes; + m_initUserp = cbr.m_userp; + cbr.m_initCb(cbr.m_userp, self(), baseCode); + m_initUserp = prevInitUserp; + } +} + //========================================================================= // Primitives converting binary values to strings... diff --git a/include/verilated_types.h b/include/verilated_types.h index b7463e835..da8c94977 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -38,6 +38,10 @@ #include #include +class VlProcess; +template +class VlUnpacked; + //========================================================================= // Debug functions @@ -104,8 +108,6 @@ constexpr IData VL_CLOG2_CE_Q(QData lhs) VL_PURE { } // Metadata of processes -class VlProcess; - using VlProcessRef = std::shared_ptr; class VlProcess final { @@ -242,7 +244,7 @@ public: // having to check for construction at each call // Alternative: seed with zero and check on rand64() call VlRNG() VL_MT_SAFE; - explicit VlRNG(uint64_t seed0) VL_MT_SAFE : m_state{0x12341234UL, seed0} {} + explicit VlRNG(uint64_t seed) VL_PURE; void srandom(uint64_t n) VL_MT_UNSAFE; std::string get_randstate() const VL_MT_UNSAFE; void set_randstate(const std::string& state) VL_MT_UNSAFE; @@ -318,6 +320,7 @@ public: // These require the class object to have the thread safety lock inline IData VL_RANDOM_RNG_I(VlRNG& rngr) VL_MT_UNSAFE { return rngr.rand64(); } inline QData VL_RANDOM_RNG_Q(VlRNG& rngr) VL_MT_UNSAFE { return rngr.rand64(); } +extern double VL_RANDOM_RNG_D(VlRNG& rngr) VL_MT_UNSAFE; extern WDataOutP VL_RANDOM_RNG_W(VlRNG& rngr, int obits, WDataOutP outwp) VL_MT_UNSAFE; //=================================================================== @@ -531,6 +534,10 @@ public: m_deque.resize(size, atDefault()); } } + // Unpacked array new[]() becomes a renew_copy() + template + void renew_copy(size_t size, const VlUnpacked& rhs); + void resize(size_t size) { m_deque.resize(size, atDefault()); } // function void q.push_front(value) @@ -1606,6 +1613,11 @@ private: return a != b; } }; +// Trait to detect VlUnpacked types +template +struct IsVlUnpacked : std::false_type {}; +template +struct IsVlUnpacked> : std::true_type {}; template std::string VL_TO_STRING(const VlUnpacked& obj) { @@ -1615,6 +1627,16 @@ std::string VL_TO_STRING(const VlUnpacked& obj) { template struct VlContainsCustomStruct> : VlContainsCustomStruct {}; +template +template +void VlQueue::renew_copy( + size_t size, const VlUnpacked& rhs) { + clear(); + if (size == 0) return; + m_deque.resize(size, atDefault()); + for (size_t i = 0; i < std::min(size, N_UnpackedDepth); ++i) { m_deque[i] = rhs.m_storage[i]; } +} + //=================================================================== // Helper to apply the given indices to a target expression @@ -1863,6 +1885,11 @@ public: VlClass() {} VlClass(const VlClass& copied) {} ~VlClass() override = default; + // Polymorphic shallow clone. Overridden in each generated concrete class. + virtual VlClass* clone() const { return nullptr; } + // METHODS + virtual const char* typeName() const { return "VlClass"; } + virtual std::string to_string() const { return ""; } }; //=================================================================== @@ -1983,6 +2010,15 @@ public: VlClassRef dynamicCast() const { return VlClassRef{dynamic_cast(m_objp)}; } + // Polymorphic shallow clone (IEEE 1800-2017 8.7: new preserves runtime type) + VlClassRef clone(VlDeleter& deleter) const { + VlClass* clonedp = m_objp->clone(); + if (VL_UNLIKELY(!clonedp)) return {}; + clonedp->m_deleterp = &deleter; + VlClassRef result; + result.m_objp = dynamic_cast(clonedp); + return result; + } // Dereference operators T_Class& operator*() const { return *m_objp; } T_Class* operator->() const { return m_objp; } @@ -2024,6 +2060,30 @@ static inline bool VL_CAST_DYNAMIC(VlNull in, VlClassRef& outr) { return true; } +// For printing class references under a container, several choices: +// 1. Dump recursively the pointed-to object. Can be huge. Might be circular. +// 2. Print object type and pointer as C pointer. Astable when rerun. +// 3. Print object type and pointer as an incrementing number. Needs num storage. +// 4. Print object type alone. Avoids above issues. +template +inline std::string VL_TO_STRING(const VlClassRef& obj) { + return obj ? obj->typeName() : "null"; +} +// Entry point for string conversion (called from not under a container); +// dereference VlClassRef objects to print members +template // Default if no specialization +inline std::string VL_TO_STRING_DEREF(T_Lhs obj) { + return VL_TO_STRING(obj); +} +template // Specialization +inline std::string VL_TO_STRING_DEREF(const VlClassRef& obj) { + return obj ? obj->to_string() : "null"; +} +template // Specialization +inline std::string VL_TO_STRING_DEREF(VlClassRef& obj) { + return obj ? obj->to_string() : "null"; +} + //============================================================================= // VlSampleQueue stores samples for input clockvars in clocking blocks. At a clocking event, // samples from this queue should be written to the correct input clockvar. diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index dc6fc0f02..7ceb04fc3 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 7ff104a2a..3942055a1 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_vcd_sc.cpp b/include/verilated_vcd_sc.cpp index fe918d9d7..e367eabc5 100644 --- a/include/verilated_vcd_sc.cpp +++ b/include/verilated_vcd_sc.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_vcd_sc.h b/include/verilated_vcd_sc.h index 56ba5390f..36e4e80ed 100644 --- a/include/verilated_vcd_sc.h +++ b/include/verilated_vcd_sc.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// Copyright 2001-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2001-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index abde5bd73..7bcee1bdc 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= @@ -24,12 +24,12 @@ /// //========================================================================= +#include "verilatedos.h" #define VERILATOR_VERILATED_VPI_CPP_ -#include "verilated_vpi.h" - #include "verilated.h" #include "verilated_imp.h" +#include "verilated_vpi.h" #include "vltstd/vpi_user.h" @@ -173,20 +173,22 @@ class VerilatedVpioVarBase VL_NOT_FINAL : public VerilatedVpio { protected: const VerilatedVar* m_varp = nullptr; const VerilatedScope* m_scopep = nullptr; - std::string m_fullname; + + // Usually empty, only gets filled when fullname() is called. Has to be stored as a member so + // the char* that fullname() returns is not a temporary. + mutable std::string m_fullname; + int32_t m_indexedDim = -1; const VerilatedRange* get_range() const { return m_varp->range(m_indexedDim + 1); } public: VerilatedVpioVarBase(const VerilatedVar* varp, const VerilatedScope* scopep) : m_varp{varp} - , m_scopep{scopep} - , m_fullname{std::string{m_scopep->name()} + '.' + m_varp->name()} {} + , m_scopep{scopep} {} explicit VerilatedVpioVarBase(const VerilatedVpioVarBase* varp) { if (varp) { m_varp = varp->m_varp; m_scopep = varp->m_scopep; - m_fullname = varp->m_fullname; m_indexedDim = varp->m_indexedDim; } } @@ -223,7 +225,10 @@ public: } const VerilatedRange* rangep() const override { return get_range(); } const char* name() const override { return m_varp->name(); } - const char* fullname() const override { return m_fullname.c_str(); } + const char* fullname() const override { + if (m_fullname.empty()) m_fullname = std::string{m_scopep->name()} + '.' + m_varp->name(); + return m_fullname.c_str(); + } virtual void* varDatap() const { return m_varp->datap(); } CData* varCDatap() const { VL_DEBUG_IFDEF(assert(varp()->vltype() == VLVT_UINT8);); @@ -416,11 +421,12 @@ public: return ret; } uint32_t type() const override { - uint32_t type = vpiReg; + uint32_t type; + // TODO have V3EmitCSyms.cpp put vpiType directly into constant table switch (varp()->vltype()) { case VLVT_REAL: type = vpiRealVar; break; case VLVT_STRING: type = vpiStringVar; break; - default: break; + default: type = varp()->isBitVar() ? vpiBitVar : vpiReg; break; } if (isIndexedDimUnpacked()) return vpiRegArray; @@ -880,6 +886,7 @@ struct VerilatedVpiTimedCbsCmp final { }; class VerilatedVpiError; +void vl_vpi_put_word(const VerilatedVpioVar* vop, QData word, size_t bitCount, size_t addOffset); class VerilatedVpiImp final { enum { CB_ENUM_MAX_VALUE = cbAtEndOfSimTime + 1 }; // Maximum callback reason @@ -1075,6 +1082,66 @@ public: } s().m_inertialPuts.clear(); } + static auto getForceControlSignals(const VerilatedVpioVarBase* vop); + + // Used in the deleter of vopGuard_t, which is invoked upon + // destruction of the return value of getForceControlSignals. + // This means that it is called at the end of vpi_get_value whenever the signal + // is forceable and at the end of vpi_put_value whenever the signal is both forceable and + // either vpiForceFlag or vpiReleaseFlag is used. + // Because it is always automatically called at the end, it should not + // erase any previously issued errors or warnings. + static void releaseWithoutErrorReset(vpiHandle object) { + VerilatedVpiImp::assertOneCheck(); + VerilatedVpio* const vop = VerilatedVpio::castp(object); + VL_DO_DANGLING(delete vop, vop); + } + + static void releaseVop(VerilatedVpioVar* vop) { + releaseWithoutErrorReset(vop->castVpiHandle()); + } + + using vopGuard_t = std::unique_ptr; + + static std::size_t vlTypeSize(VerilatedVarType vltype); + static void setAllBitsToValue(const VerilatedVpioVar* vop, uint8_t bitValue) { + assert(bitValue == 0 || bitValue == 1); + const uint64_t word = (bitValue == 1) ? -1ULL : 0ULL; + const std::size_t wordSize = vlTypeSize(vop->varp()->vltype()); + assert(wordSize > 0); + const uint32_t varBits = vop->bitSize(); + const std::size_t numChunks = (varBits / wordSize); + for (std::size_t i{0}; i < numChunks; ++i) { + vl_vpi_put_word(vop, word, wordSize, i * wordSize); + } + // addOffset == varBits would trigger assertion in vl_vpi_var_access_info even if + // bitCount == 0, so first check if there is a remainder + if (varBits % wordSize != 0) + vl_vpi_put_word(vop, word, varBits % wordSize, numChunks * wordSize); + } + + // Recreates the __VforceRd signal's data vector, since __VforceRd is not publicly accessible + // in Verilated code. + template + static std::vector + createReadDataVector(const void* const baseSignalDatap, + const std::pair forceControlDatap, + const std::size_t bitCount) { + const void* const forceEnableDatap = forceControlDatap.first; + const void* const forceValueDatap = forceControlDatap.second; + assert(bitCount > 0); + const std::size_t numWords = (bitCount + (8 * sizeof(T)) - 1) / (8 * sizeof(T)); // Ceil + std::vector readData(numWords); + for (std::size_t i{0}; i < numWords; ++i) { + const T forceEnableWord = reinterpret_cast(forceEnableDatap)[i]; + const T forceValueWord = reinterpret_cast(forceValueDatap)[i]; + const T baseSignalWord = reinterpret_cast(baseSignalDatap)[i]; + const T readDataWord + = (forceEnableWord & forceValueWord) | (~forceEnableWord & baseSignalWord); + readData[i] = readDataWord; + } + return readData; + } }; //====================================================================== @@ -1229,6 +1296,49 @@ VerilatedVpiError* VerilatedVpiImp::error_info() VL_MT_UNSAFE_ONE { return s().m_errorInfop; } +auto VerilatedVpiImp::getForceControlSignals(const VerilatedVpioVarBase* const vop) { + const std::string signalName = vop->fullname(); + const std::string forceEnableSignalName = signalName + "__VforceEn"; + const std::string forceValueSignalName = signalName + "__VforceVal"; + + vpiHandle const forceEnableSignalp // NOLINT(misc-misplaced-const) + = vpi_handle_by_name(const_cast(forceEnableSignalName.c_str()), nullptr); + vpiHandle const forceValueSignalp // NOLINT(misc-misplaced-const) + = vpi_handle_by_name(const_cast(forceValueSignalName.c_str()), nullptr); + VerilatedVpioVar* forceEnableSignalVop = VerilatedVpioVar::castp(forceEnableSignalp); + VerilatedVpioVar* forceValueSignalVop = VerilatedVpioVar::castp(forceValueSignalp); + if (VL_UNLIKELY(!forceEnableSignalVop)) { + VL_VPI_ERROR_(__FILE__, __LINE__, + "%s: VPI force or release requested for '%s', but vpiHandle '%p' of enable " + "signal '%s' could not be cast to VerilatedVpioVar*. Ensure signal is " + "marked as forceable", + __func__, signalName.c_str(), forceEnableSignalp, + forceEnableSignalName.c_str()); + } + if (VL_UNLIKELY(!forceValueSignalVop)) { + VL_VPI_ERROR_(__FILE__, __LINE__, + "%s: VPI force or release requested for '%s', but vpiHandle '%p' of value " + "signal '%s' could not be cast to VerilatedVpioVar*. Ensure signal is " + "marked as forceable", + __func__, signalName.c_str(), forceValueSignalp, + forceValueSignalName.c_str()); + } + return std::pair{vopGuard_t{forceEnableSignalVop, releaseVop}, + vopGuard_t{forceValueSignalVop, releaseVop}}; +} + +std::size_t VerilatedVpiImp::vlTypeSize(const VerilatedVarType vltype) { + switch (vltype) { + case VLVT_UINT8: return sizeof(CData); break; + case VLVT_UINT16: return sizeof(SData); break; + case VLVT_UINT32: return sizeof(IData); break; + case VLVT_UINT64: return sizeof(QData); break; + case VLVT_WDATA: return sizeof(EData); break; + default: // LCOV_EXCL_START + VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported vltype (%d)", __func__, vltype); + return 0; + } // LCOV_EXCL_STOP +} //====================================================================== // VerilatedVpiError Methods @@ -1991,7 +2101,7 @@ vpiHandle vpi_register_cb(p_cb_data cb_data_p) { VL_VPI_ERROR_RESET_(); // cppcheck-suppress nullPointer if (VL_UNLIKELY(!cb_data_p)) { - VL_VPI_WARNING_(__FILE__, __LINE__, "%s : callback data pointer is null", __func__); + VL_VPI_WARNING_(__FILE__, __LINE__, "%s: VPI callback data pointer is null", __func__); return nullptr; } const PLI_INT32 reason = cb_data_p->reason; @@ -2393,8 +2503,8 @@ void vpi_get_delays(vpiHandle /*object*/, p_vpi_delay /*delay_p*/) { VL_VPI_UNIM void vpi_put_delays(vpiHandle /*object*/, p_vpi_delay /*delay_p*/) { VL_VPI_UNIMP_(); } // value processing -bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const char* fullname, - bool isGetValue) { +bool vl_check_format(const VerilatedVpioVarBase* vop, const p_vpi_value valuep, bool isGetValue) { + const VerilatedVar* varp = vop->varp(); bool status = true; if ((valuep->format == vpiVectorVal) || (valuep->format == vpiBinStrVal) || (valuep->format == vpiOctStrVal) || (valuep->format == vpiHexStrVal)) { @@ -2445,13 +2555,22 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c case VLVT_REAL: return status; default: status = false; // LCOV_EXCL_LINE } + } else if (valuep->format == vpiScalarVal) { + switch (varp->vltype()) { + case VLVT_UINT8: + case VLVT_UINT16: + case VLVT_UINT32: + case VLVT_UINT64: + case VLVT_WDATA: return status; + default: status = false; // LCOV_EXCL_LINE + } } else if (valuep->format == vpiSuppressVal) { return status; } else { status = false; } VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) for %s", __func__, - VerilatedVpiError::strFromVpiVal(valuep->format), fullname); + VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); return status; } @@ -2601,14 +2720,69 @@ void vl_vpi_put_word(const VerilatedVpioVar* vop, QData word, size_t bitCount, s void vl_vpi_get_value(const VerilatedVpioVarBase* vop, p_vpi_value valuep) { const VerilatedVar* const varp = vop->varp(); void* const varDatap = vop->varDatap(); - const char* fullname = vop->fullname(); - if (!vl_check_format(varp, valuep, fullname, true)) return; + if (!vl_check_format(vop, valuep, true)) return; // string data type is dynamic and may vary in size during simulation static thread_local std::string t_outDynamicStr; const int varBits = vop->bitSize(); + // __VforceRd already has the correct value, but that signal is not public and thus not + // present in the scope's m_varsp map, so its value has to be recreated using the __VforceEn + // and __VforceVal signals. + // TODO: Implement a way to retrieve __VforceRd, rather than needing to recreate it. + const auto forceControlSignals + = vop->varp()->isForceable() + ? VerilatedVpiImp::getForceControlSignals(vop) + : std::pair{ + VerilatedVpiImp::vopGuard_t{nullptr, VerilatedVpiImp::releaseVop}, + VerilatedVpiImp::vopGuard_t{nullptr, VerilatedVpiImp::releaseVop}}; + const VerilatedVpioVarBase* const forceEnableSignalVop = forceControlSignals.first.get(); + const VerilatedVpioVarBase* const forceValueSignalVop = forceControlSignals.second.get(); + t_vpi_error_info getForceControlSignalsError{}; + const bool errorOccurred = vpi_chk_error(&getForceControlSignalsError); + // LCOV_EXCL_START - Cannot test, since getForceControlSignals does not (currently) produce + // any notices or warnings. + if (errorOccurred && getForceControlSignalsError.level < vpiError) { + vpi_printf(getForceControlSignalsError.message); + VL_VPI_ERROR_RESET_(); + } // LCOV_EXCL_STOP + // NOLINTNEXTLINE(readability-simplify-boolean-expr); + if (VL_UNLIKELY( + (errorOccurred && getForceControlSignalsError.level >= vpiError) + || (vop->varp()->isForceable() && (!forceEnableSignalVop || !forceValueSignalVop)))) { + + // Check if getForceControlSignals provided any additional error info + const bool gotErrorMessage = vpi_chk_error(&getForceControlSignalsError); + const std::string previousErrorMessage + = gotErrorMessage + ? std::string{" Error message: "} + getForceControlSignalsError.message + : ""; + + VL_VPI_ERROR_(__FILE__, __LINE__, + "%s: Signal '%s' is marked forceable, but force " + "control signals could not be retrieved.%s", + __func__, vop->fullname(), + gotErrorMessage ? previousErrorMessage.c_str() : ""); + return; + } + + const std::function getForceableSignalWord + = [forceEnableSignalVop, forceValueSignalVop](const VerilatedVpioVarBase* baseSignalVop, + size_t bitCount, size_t addOffset) -> QData { + // variables are QData, even though signals may have different representation, because any + // extraneous bits are simply truncated upon implicit casting when this function is called. + const QData baseSignalData = vl_vpi_get_word(baseSignalVop, bitCount, addOffset); + const QData forceEnableData = vl_vpi_get_word(forceEnableSignalVop, bitCount, addOffset); + const QData forceValueData = vl_vpi_get_word(forceValueSignalVop, bitCount, addOffset); + const QData readData + = (forceEnableData & forceValueData) | (~forceEnableData & baseSignalData); + return readData; + }; + + const std::function get_word + = vop->varp()->isForceable() ? getForceableSignalWord : vl_vpi_get_word; + // We used to presume vpiValue.format = vpiIntVal or if single bit vpiScalarVal // This may cause backward compatibility issues with older code. if (valuep->format == vpiVectorVal) { @@ -2626,25 +2800,38 @@ void vl_vpi_get_value(const VerilatedVpioVarBase* vop, p_vpi_value valuep) { return; } for (int i = 0; i < words; ++i) { - t_out[i].aval = vl_vpi_get_word(vop, 32, i * 32); + t_out[i].aval = get_word(vop, 32, i * 32); t_out[i].bval = 0; } return; } else if (varp->vltype() == VLVT_UINT64 && varBits > 32) { - const QData data = vl_vpi_get_word(vop, 64, 0); + const QData data = get_word(vop, 64, 0); t_out[1].aval = static_cast(data >> 32ULL); t_out[1].bval = 0; t_out[0].aval = static_cast(data); t_out[0].bval = 0; return; } else { - t_out[0].aval = vl_vpi_get_word(vop, 32, 0); + t_out[0].aval = get_word(vop, 32, 0); t_out[0].bval = 0; return; } } else if (valuep->format == vpiBinStrVal) { t_outDynamicStr.resize(varBits); - const CData* datap = reinterpret_cast(varDatap); + + static thread_local std::vector forceReadCData; + forceReadCData + = vop->varp()->isForceable() + ? VerilatedVpiImp::createReadDataVector( + varDatap, + {forceEnableSignalVop->varDatap(), forceValueSignalVop->varDatap()}, + vop->bitSize()) + : std::vector{}; + const uint8_t* const varCDatap = vop->varp()->isForceable() + ? forceReadCData.data() + : reinterpret_cast(varDatap); + + const CData* datap = varCDatap; for (size_t i = 0; i < varBits; ++i) { const size_t pos = i + vop->bitOffset(); const char val = (datap[pos >> 3] >> (pos & 7)) & 1; @@ -2656,24 +2843,22 @@ void vl_vpi_get_value(const VerilatedVpioVarBase* vop, p_vpi_value valuep) { const int chars = (varBits + 2) / 3; t_outDynamicStr.resize(chars); for (size_t i = 0; i < chars; ++i) { - const char val = vl_vpi_get_word(vop, 3, i * 3); + const char val = get_word(vop, 3, i * 3); t_outDynamicStr[chars - i - 1] = '0' + val; } valuep->value.str = const_cast(t_outDynamicStr.c_str()); return; } else if (valuep->format == vpiDecStrVal) { if (varp->vltype() == VLVT_UINT8) { - vl_strprintf(t_outDynamicStr, "%hhu", - static_cast(vl_vpi_get_word(vop, 8, 0))); + vl_strprintf(t_outDynamicStr, "%hhu", static_cast(get_word(vop, 8, 0))); } else if (varp->vltype() == VLVT_UINT16) { vl_strprintf(t_outDynamicStr, "%hu", - static_cast(vl_vpi_get_word(vop, 16, 0))); + static_cast(get_word(vop, 16, 0))); } else if (varp->vltype() == VLVT_UINT32) { - vl_strprintf(t_outDynamicStr, "%u", - static_cast(vl_vpi_get_word(vop, 32, 0))); + vl_strprintf(t_outDynamicStr, "%u", static_cast(get_word(vop, 32, 0))); } else if (varp->vltype() == VLVT_UINT64) { vl_strprintf(t_outDynamicStr, "%llu", // lintok-format-ll - static_cast(vl_vpi_get_word(vop, 64, 0))); + static_cast(get_word(vop, 64, 0))); } valuep->value.str = const_cast(t_outDynamicStr.c_str()); return; @@ -2681,7 +2866,7 @@ void vl_vpi_get_value(const VerilatedVpioVarBase* vop, p_vpi_value valuep) { const int chars = (varBits + 3) >> 2; t_outDynamicStr.resize(chars); for (size_t i = 0; i < chars; ++i) { - const char val = vl_vpi_get_word(vop, 4, i * 4); + const char val = get_word(vop, 4, i * 4); t_outDynamicStr[chars - i - 1] = "0123456789abcdef"[static_cast(val)]; } valuep->value.str = const_cast(t_outDynamicStr.c_str()); @@ -2692,7 +2877,7 @@ void vl_vpi_get_value(const VerilatedVpioVarBase* vop, p_vpi_value valuep) { valuep->value.str = reinterpret_cast(varDatap); return; } else { - t_outDynamicStr = *(vop->varStringDatap()); + t_outDynamicStr = *vop->varStringDatap(); valuep->value.str = const_cast(t_outDynamicStr.c_str()); return; } @@ -2700,7 +2885,7 @@ void vl_vpi_get_value(const VerilatedVpioVarBase* vop, p_vpi_value valuep) { const int chars = VL_BYTES_I(varBits); t_outDynamicStr.resize(chars); for (size_t i = 0; i < chars; ++i) { - const char val = vl_vpi_get_word(vop, 8, i * 8); + const char val = get_word(vop, 8, i * 8); // other simulators replace [leading?] zero chars with spaces, replicate here. t_outDynamicStr[chars - i - 1] = val ? val : ' '; } @@ -2708,16 +2893,25 @@ void vl_vpi_get_value(const VerilatedVpioVarBase* vop, p_vpi_value valuep) { return; } } else if (valuep->format == vpiIntVal) { - valuep->value.integer = vl_vpi_get_word(vop, 32, 0); + valuep->value.integer = get_word(vop, 32, 0); return; } else if (valuep->format == vpiRealVal) { - valuep->value.real = *(vop->varRealDatap()); + // Only cover the scalar case, since reals cannot be packed (IEEE 1800, section 7.4.1), and + // unpacked arrays are not supported for forcing in Verilator (#4735). + if (vop->varp()->isForceable() && *forceEnableSignalVop->varCDatap()) + valuep->value.real = *forceValueSignalVop->varRealDatap(); + else + valuep->value.real = *vop->varRealDatap(); + + return; + } else if (valuep->format == vpiScalarVal) { + valuep->value.scalar = get_word(vop, 32, 0) ? vpi1 : vpi0; return; } else if (valuep->format == vpiSuppressVal) { return; } VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) as requested for %s", __func__, - VerilatedVpiError::strFromVpiVal(valuep->format), fullname); + VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); } void vpi_get_value(vpiHandle object, p_vpi_value valuep) { @@ -2754,55 +2948,148 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ return nullptr; } const PLI_INT32 delay_mode = flags & 0xfff; - if (const VerilatedVpioVar* const vop = VerilatedVpioVar::castp(object)) { - VL_DEBUG_IF_PLI( - VL_DBG_MSGF("- vpi: vpi_put_value name=%s fmt=%d vali=%d\n", vop->fullname(), - valuep->format, valuep->value.integer); - VL_DBG_MSGF("- vpi: varp=%p putatp=%p\n", vop->varp()->datap(), vop->varDatap());); + const PLI_INT32 forceFlag = flags & 0xfff; + if (const VerilatedVpioVar* const baseSignalVop = VerilatedVpioVar::castp(object)) { + VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_put_value name=%s fmt=%d vali=%d\n", + baseSignalVop->fullname(), valuep->format, + valuep->value.integer); + VL_DBG_MSGF("- vpi: varp=%p putatp=%p\n", + baseSignalVop->varp()->datap(), baseSignalVop->varDatap());); - if (VL_UNLIKELY(!vop->varp()->isPublicRW())) { + if (VL_UNLIKELY(!baseSignalVop->varp()->isPublicRW())) { VL_VPI_ERROR_(__FILE__, __LINE__, "vpi_put_value was used on signal marked read-only," - " use public_flat_rw instead for %s : %s", - vop->fullname(), vop->scopep()->defname()); + " use public_flat_rw instead for '%s'", + baseSignalVop->fullname()); return nullptr; } - if (!vl_check_format(vop->varp(), valuep, vop->fullname(), false)) return nullptr; + + // NOLINTNEXTLINE(readability-simplify-boolean-expr); + if (VL_UNLIKELY((forceFlag == vpiForceFlag || forceFlag == vpiReleaseFlag) + && !baseSignalVop->varp()->isForceable())) { + VL_VPI_ERROR_("", 0, "vpi_put_value used with %s on non-forceable signal '%s'", + forceFlag == vpiForceFlag ? "vpiForceFlag" : "vpiReleaseFlag", + baseSignalVop->fullname()); + return nullptr; + } + if (!vl_check_format(baseSignalVop, valuep, false)) return nullptr; if (delay_mode == vpiInertialDelay) { if (!VerilatedVpiPutHolder::canInertialDelay(valuep)) { VL_VPI_WARNING_( __FILE__, __LINE__, "%s: Unsupported p_vpi_value as requested for '%s' with vpiInertialDelay", - __func__, vop->fullname()); + __func__, baseSignalVop->fullname()); return nullptr; } - VerilatedVpiImp::inertialDelay(vop, valuep); + VerilatedVpiImp::inertialDelay(baseSignalVop, valuep); return object; } VerilatedVpiImp::evalNeeded(true); - const int varBits = vop->bitSize(); + const int varBits = baseSignalVop->bitSize(); + + const auto forceControlSignals + = baseSignalVop->varp()->isForceable() + && (forceFlag == vpiForceFlag || forceFlag == vpiReleaseFlag) + ? VerilatedVpiImp::getForceControlSignals(baseSignalVop) + : std::pair{ + VerilatedVpiImp::vopGuard_t{nullptr, VerilatedVpiImp::releaseVop}, + VerilatedVpiImp::vopGuard_t{nullptr, VerilatedVpiImp::releaseVop}}; + const VerilatedVpioVar* const forceEnableSignalVop = forceControlSignals.first.get(); + const VerilatedVpioVar* const forceValueSignalVop = forceControlSignals.second.get(); + t_vpi_error_info getForceControlSignalsError{}; + bool errorOccurred = vpi_chk_error(&getForceControlSignalsError); + // LCOV_EXCL_START - Cannot test, since getForceControlSignals does not (currently) produce + // any notices or warnings. + if (errorOccurred && getForceControlSignalsError.level < vpiError) { + vpi_printf(getForceControlSignalsError.message); + VL_VPI_ERROR_RESET_(); + } // LCOV_EXCL_STOP + // NOLINTNEXTLINE(readability-simplify-boolean-expr); + if (VL_UNLIKELY(baseSignalVop->varp()->isForceable() + && (forceFlag == vpiForceFlag || forceFlag == vpiReleaseFlag) + && (!forceEnableSignalVop || !forceValueSignalVop))) { + + // Check if getForceControlSignals provided any additional error info + const bool gotErrorMessage = vpi_chk_error(&getForceControlSignalsError); + const std::string previousErrorMessage + = gotErrorMessage + ? std::string{" Error message: "} + getForceControlSignalsError.message + : ""; + + VL_VPI_ERROR_(__FILE__, __LINE__, + "%s: Signal '%s' with vpiHandle '%p' is marked forceable, but force " + "control signals could not be retrieved.%s", + __func__, baseSignalVop->fullname(), object, + gotErrorMessage ? previousErrorMessage.c_str() : ""); + return nullptr; + } + + const VerilatedVpioVar* const valueVop + = (forceFlag == vpiForceFlag) ? forceValueSignalVop : baseSignalVop; + + if (forceFlag == vpiForceFlag) { + // Enable __VforceEn + VerilatedVpiImp::setAllBitsToValue(forceEnableSignalVop, 1); + } + if (forceFlag == vpiReleaseFlag) { + // If signal is continuously assigned, first clear the force enable bits, then get the + // (non-forced) value. Else, get the (still forced) value first, then clear the force + // enable bits. + + if (baseSignalVop->varp()->isContinuously()) + VerilatedVpiImp::setAllBitsToValue(forceEnableSignalVop, 0); + + vl_vpi_get_value(baseSignalVop, valuep); + + t_vpi_error_info baseValueGetError{}; + errorOccurred = vpi_chk_error(&baseValueGetError); + // LCOV_EXCL_START - Cannot test, because missing signal would already trigger error + // earlier, at the getForceControlSignals stage + // NOLINTNEXTLINE(readability-simplify-boolean-expr); + if (VL_UNLIKELY(errorOccurred && baseValueGetError.level >= vpiError)) { + const std::string baseValueSignalName = baseSignalVop->fullname(); + const std::string previousErrorMessage = baseValueGetError.message; + VL_VPI_ERROR_(__FILE__, __LINE__, + "%s: Could not retrieve value of signal '%s' with " + "vpiHandle '%p'. Error message: %s", + __func__, baseValueSignalName.c_str(), object, + previousErrorMessage.c_str()); + return nullptr; + } + // NOLINTNEXTLINE(readability-simplify-boolean-expr); + if (VL_UNCOVERABLE(errorOccurred && baseValueGetError.level < vpiError)) { + vpi_printf(baseValueGetError.message); + VL_VPI_ERROR_RESET_(); + } // LCOV_EXCL_STOP + + if (!baseSignalVop->varp()->isContinuously()) + VerilatedVpiImp::setAllBitsToValue(forceEnableSignalVop, 0); + + return nullptr; + } + if (valuep->format == vpiVectorVal) { if (VL_UNLIKELY(!valuep->value.vector)) return nullptr; - if (vop->varp()->vltype() == VLVT_WDATA) { + if (valueVop->varp()->vltype() == VLVT_WDATA) { const int words = VL_WORDS_I(varBits); for (int i = 0; i < words; ++i) - vl_vpi_put_word(vop, valuep->value.vector[i].aval, 32, i * 32); + vl_vpi_put_word(valueVop, valuep->value.vector[i].aval, 32, i * 32); return object; - } else if (vop->varp()->vltype() == VLVT_UINT64 && varBits > 32) { + } else if (valueVop->varp()->vltype() == VLVT_UINT64 && varBits > 32) { const QData val = (static_cast(valuep->value.vector[1].aval) << 32) | static_cast(valuep->value.vector[0].aval); - vl_vpi_put_word(vop, val, 64, 0); + vl_vpi_put_word(valueVop, val, 64, 0); return object; } else { - vl_vpi_put_word(vop, valuep->value.vector[0].aval, 32, 0); + vl_vpi_put_word(valueVop, valuep->value.vector[0].aval, 32, 0); return object; } } else if (valuep->format == vpiBinStrVal) { const int len = std::strlen(valuep->value.str); - CData* const datap = reinterpret_cast(vop->varDatap()); + CData* const datap = reinterpret_cast(valueVop->varDatap()); for (int i = 0; i < varBits; ++i) { const bool set = (i < len) && (valuep->value.str[len - i - 1] == '1'); - const size_t pos = vop->bitOffset() + i; + const size_t pos = valueVop->bitOffset() + i; if (set) datap[pos >> 3] |= 1 << (pos & 7); @@ -2819,10 +3106,10 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ "%s: Non octal character '%c' in '%s' as value %s for %s", __func__, digit + '0', valuep->value.str, VerilatedVpiError::strFromVpiVal(valuep->format), - vop->fullname()); + valueVop->fullname()); digit = 0; } - vl_vpi_put_word(vop, digit, 3, i * 3); + vl_vpi_put_word(valueVop, digit, 3, i * 3); } return object; } else if (valuep->format == vpiDecStrVal) { @@ -2833,16 +3120,17 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ if (success < 1) { VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Parsing failed for '%s' as value %s for %s", __func__, valuep->value.str, - VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); + VerilatedVpiError::strFromVpiVal(valuep->format), + valueVop->fullname()); return nullptr; } if (success > 1) { - VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Trailing garbage '%s' in '%s' as value %s for %s", __func__, - remainder, valuep->value.str, - VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); + VL_VPI_WARNING_( + __FILE__, __LINE__, "%s: Trailing garbage '%s' in '%s' as value %s for %s", + __func__, remainder, valuep->value.str, + VerilatedVpiError::strFromVpiVal(valuep->format), valueVop->fullname()); } - vl_vpi_put_word(vop, val, 64, 0); + vl_vpi_put_word(valueVop, val, 64, 0); return object; } else if (valuep->format == vpiHexStrVal) { const int chars = (varBits + 3) >> 2; @@ -2866,19 +3154,20 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ "%s: Non hex character '%c' in '%s' as value %s for %s", __func__, digit, valuep->value.str, VerilatedVpiError::strFromVpiVal(valuep->format), - vop->fullname()); + valueVop->fullname()); hex = 0; } } else { hex = 0; } // assign hex digit value to destination - vl_vpi_put_word(vop, hex, 4, i * 4); + vl_vpi_put_word(valueVop, hex, 4, i * 4); } return object; } else if (valuep->format == vpiStringVal) { - if (vop->varp()->vltype() == VLVT_STRING) { - *(vop->varStringDatap()) = valuep->value.str; + if (valueVop->varp()->vltype() == VLVT_STRING) { + // Does not use valueVop, because strings are not forceable anyway + *(baseSignalVop->varStringDatap()) = valuep->value.str; return object; } else { const int chars = VL_BYTES_I(varBits); @@ -2886,21 +3175,25 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ for (int i = 0; i < chars; ++i) { // prepend with 0 values before placing string the least significant bytes const char c = (i < len) ? valuep->value.str[len - i - 1] : 0; - vl_vpi_put_word(vop, c, 8, i * 8); + vl_vpi_put_word(valueVop, c, 8, i * 8); } } return object; } else if (valuep->format == vpiIntVal) { - vl_vpi_put_word(vop, valuep->value.integer, 64, 0); + vl_vpi_put_word(valueVop, valuep->value.integer, 64, 0); return object; } else if (valuep->format == vpiRealVal) { - if (vop->varp()->vltype() == VLVT_REAL) { - *(vop->varRealDatap()) = valuep->value.real; + if (valueVop->varp()->vltype() == VLVT_REAL) { + *(valueVop->varRealDatap()) = valuep->value.real; return object; } + } else if (valuep->format == vpiScalarVal) { + vl_vpi_put_word(valueVop, (valuep->value.scalar == vpi1 ? 1 : 0), 1, 0); + return object; } VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) as requested for %s", - __func__, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); + __func__, VerilatedVpiError::strFromVpiVal(valuep->format), + valueVop->fullname()); return nullptr; } else if (const VerilatedVpioParam* const vop = VerilatedVpioParam::castp(object)) { VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Ignoring vpi_put_value to vpiParameter: %s", @@ -3136,7 +3429,7 @@ void vl_get_value_array(vpiHandle object, p_vpi_arrayvalue arrayvalue_p, const P const unsigned size = vop->size(); if (VL_UNCOVERABLE(num > size)) { - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: requested elements (%u) exceed array size (%u)", + VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Requested elements (%u) exceed array size (%u)", __func__, num, size); return; } @@ -3336,7 +3629,7 @@ void vpi_get_value_array(vpiHandle object, p_vpi_arrayvalue arrayvalue_p, PLI_IN const int lowRange = vop->rangep()->low(); const int highRange = vop->rangep()->high(); if ((index_p[0] > highRange) || (index_p[0] < lowRange)) { - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: index %u for object %s is out of bounds [%u,%u]", + VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Index %u for object '%s' is out of bounds [%u,%u]", __func__, index_p[0], vop->fullname(), lowRange, highRange); return; } @@ -3360,7 +3653,7 @@ void vl_put_value_array(vpiHandle object, p_vpi_arrayvalue arrayvalue_p, const P const int size = vop->size(); if (VL_UNCOVERABLE(num > size)) { VL_VPI_ERROR_(__FILE__, __LINE__, - "%s: requested elements to set (%u) exceed array size (%u)", __func__, num, + "%s: Requested elements to set (%u) exceed array size (%u)", __func__, num, size); return; } @@ -3517,7 +3810,7 @@ void vpi_put_value_array(vpiHandle object, p_vpi_arrayvalue arrayvalue_p, PLI_IN const int lowRange = vop->rangep()->low(); const int highRange = vop->rangep()->high(); if ((index_p[0] > highRange) || (index_p[0] < lowRange)) { - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: index %u for object %s is out of bounds [%u,%u]", + VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Index %u for object '%s' is out of bounds [%u,%u]", __func__, index_p[0], vop->fullname(), lowRange, highRange); return; } diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h index 876195285..14ac9bff0 100644 --- a/include/verilated_vpi.h +++ b/include/verilated_vpi.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= diff --git a/include/verilatedos.h b/include/verilatedos.h index e43bd4825..b93eaae56 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/include/verilatedos_c.h b/include/verilatedos_c.h index e0db071cd..16279d8c0 100644 --- a/include/verilatedos_c.h +++ b/include/verilatedos_c.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/include/vltstd/sv_vpi_user.h b/include/vltstd/sv_vpi_user.h index fb8039c59..a52f5ebda 100644 --- a/include/vltstd/sv_vpi_user.h +++ b/include/vltstd/sv_vpi_user.h @@ -7,6 +7,11 @@ * routine declarations used by the SystemVerilog Verification Procedural * Interface (VPI) access routines. * +* This file is from the SystemVerilog IEEE 1800-2023 Annex M, +* and is placed here as mandatory interface material, permitted under IEEE +* implementation permission doctrine. +* SPDX-FileCopyrightText: 2024 The Institute of Electrical and Electronics Engineers, Inc. +* SPDX-License-Identifier: LicenseRef-IEEE-1800 **************************************************************************/ /*************************************************************************** diff --git a/include/vltstd/svdpi.h b/include/vltstd/svdpi.h index 66763bb90..fd9211538 100644 --- a/include/vltstd/svdpi.h +++ b/include/vltstd/svdpi.h @@ -7,7 +7,11 @@ * This file contains the constant definitions, structure definitions, * and routine declarations used by SystemVerilog DPI. * - * This file is from the SystemVerilog IEEE 1800-2023 Annex I. + * This file is from the SystemVerilog IEEE 1800-2023 Annex I, + * and is placed here as mandatory interface material, permitted under IEEE + * implementation permission doctrine. + * SPDX-FileCopyrightText: 2024 The Institute of Electrical and Electronics Engineers, Inc. + * SPDX-License-Identifier: LicenseRef-IEEE-1800 */ #ifndef INCLUDED_SVDPI diff --git a/include/vltstd/veriuser.h b/include/vltstd/veriuser.h index 542f3c20e..29839002b 100644 --- a/include/vltstd/veriuser.h +++ b/include/vltstd/veriuser.h @@ -3,10 +3,10 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= diff --git a/include/vltstd/vpi_user.h b/include/vltstd/vpi_user.h index b3bc11e2e..eceff1f26 100644 --- a/include/vltstd/vpi_user.h +++ b/include/vltstd/vpi_user.h @@ -7,6 +7,11 @@ * routine declarations used by the SystemVerilog Verification Procedural * Interface (VPI) access routines. * + * This file is from the SystemVerilog IEEE 1800-2023 Annex K, + * and is placed here as mandatory interface material, permitted under IEEE + * implementation permission doctrine. + * SPDX-FileCopyrightText: 2024 The Institute of Electrical and Electronics Engineers, Inc. + * SPDX-License-Identifier: LicenseRef-IEEE-1800 ******************************************************************************/ /******************************************************************************* diff --git a/nodist/clang_check_attributes b/nodist/clang_check_attributes index 59812b6bc..8a55e1bd1 100755 --- a/nodist/clang_check_attributes +++ b/nodist/clang_check_attributes @@ -1,9 +1,10 @@ #!/usr/bin/env python3 # pylint: disable=C0114,C0115,C0116,C0209,C0302,R0902,R0911,R0912,R0914,R0915,E1101 # -# Copyright 2022-2026 by Wilson Snyder. Verilator is free software; you -# can redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Apache License 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Apache License 2.0. +# SPDX-FileCopyrightText: 2022-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Apache-2.0 import argparse @@ -1087,10 +1088,13 @@ def main(): allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Check function annotations for correctness""", - epilog="""Copyright 2022-2026 by Wilson Snyder. Verilator is free software; - you can redistribute it and/or modify it under the terms of either the GNU - Lesser General Public License Version 3 or the Apache License 2.0. - SPDX-License-Identifier: LGPL-3.0-only OR Apache-2.0""") + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. + +SPDX-FileCopyrightText: 2022-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument("--verilator-root", type=str, diff --git a/nodist/dot_importer b/nodist/dot_importer index f7a96af7e..899c7dcc2 100755 --- a/nodist/dot_importer +++ b/nodist/dot_importer @@ -80,12 +80,13 @@ parser = argparse.ArgumentParser( description="""dot_importer takes a graphvis .dot file and converts into .cpp file. This x.cpp file is then manually included in V3GraphTest.cpp to verify various xsub-algorithms.""", - epilog="""Copyright 2005-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2002-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('filename', help='input .dot filename to process') diff --git a/nodist/fastcov.py b/nodist/fastcov.py index f6b7ae408..87ba96992 100755 --- a/nodist/fastcov.py +++ b/nodist/fastcov.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: MIT -# Copyright 2018-present, Bryan Gillespie +# SPDX-FileCopyrightText: 2018 Bryan Gillespie """ Author: Bryan Gillespie https://github.com/RPGillespie6/fastcov diff --git a/nodist/fuzzer/actual_fail b/nodist/fuzzer/actual_fail index bf511c73d..d819e3fbb 100755 --- a/nodist/fuzzer/actual_fail +++ b/nodist/fuzzer/actual_fail @@ -4,9 +4,7 @@ ###################################################################### # DESCRIPTION: Fuzzer result checker # -# Copyright 2019-2019 by Eric Rippey. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2019 Eric Rippey # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### diff --git a/nodist/fuzzer/all b/nodist/fuzzer/all index ce0be68ce..6333d61db 100755 --- a/nodist/fuzzer/all +++ b/nodist/fuzzer/all @@ -2,10 +2,7 @@ ###################################################################### # DESCRIPTION: Fuzzer one-line setup & run # -# Copyright 2019-2019 by Eric Rippey. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# SPDX-FileCopyrightText: 2019 Eric Rippey # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### diff --git a/nodist/fuzzer/generate_dictionary b/nodist/fuzzer/generate_dictionary index d58bd4c73..4fad733dd 100755 --- a/nodist/fuzzer/generate_dictionary +++ b/nodist/fuzzer/generate_dictionary @@ -3,9 +3,7 @@ ###################################################################### # DESCRIPTION: Fuzzer dictionary generator # -# Copyright 2019-2019 by Eric Rippey. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2019 Eric Rippey # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### diff --git a/nodist/fuzzer/run b/nodist/fuzzer/run index 216a2249e..37a7ff0be 100755 --- a/nodist/fuzzer/run +++ b/nodist/fuzzer/run @@ -2,10 +2,7 @@ ###################################################################### # DESCRIPTION: Fuzzer run script # -# Copyright 2019-2019 by Eric Rippey. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# SPDX-FileCopyrightText: 2019 Eric Rippey # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### diff --git a/nodist/fuzzer/setup_root b/nodist/fuzzer/setup_root index 5fed7ac64..4c9a370fd 100755 --- a/nodist/fuzzer/setup_root +++ b/nodist/fuzzer/setup_root @@ -2,10 +2,7 @@ ###################################################################### # DESCRIPTION: Fuzzer setup to be run as root # -# Copyright 2019-2019 by Eric Rippey. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# SPDX-FileCopyrightText: 2019 Eric Rippey # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### diff --git a/nodist/fuzzer/setup_user b/nodist/fuzzer/setup_user index 03f17c668..b344c9520 100755 --- a/nodist/fuzzer/setup_user +++ b/nodist/fuzzer/setup_user @@ -2,10 +2,7 @@ ###################################################################### # DESCRIPTION: Fuzzer setup to be run as a normal user # -# Copyright 2019-2019 by Eric Rippey. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# SPDX-FileCopyrightText: 2019 Eric Rippey # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### diff --git a/nodist/fuzzer/wrapper.cpp b/nodist/fuzzer/wrapper.cpp index 34995ad2e..268a7211a 100644 --- a/nodist/fuzzer/wrapper.cpp +++ b/nodist/fuzzer/wrapper.cpp @@ -2,10 +2,7 @@ //************************************************************************* // DESCRIPTION: Verilator fuzzing wrapper for verilator_bin // -// Copyright 2019 by Eric Rippey. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// SPDX-FileCopyrightText: 2019 Eric Rippey // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* diff --git a/nodist/install_test b/nodist/install_test index 71db851d5..d7b69ad10 100755 --- a/nodist/install_test +++ b/nodist/install_test @@ -122,12 +122,13 @@ parser = argparse.ArgumentParser( description="""install_test performs several make-and-install iterations to verify the Verilator kit. It isn't part of the normal "make test" due to the number of builds required.""", - epilog="""Copyright 2009-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2009-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--debug', action='store_const', const=9, help='enable debug') parser.add_argument('--stage', type=int, diff --git a/nodist/lint_py_test_filter b/nodist/lint_py_test_filter index f5bd89e81..3e0bdb9e9 100755 --- a/nodist/lint_py_test_filter +++ b/nodist/lint_py_test_filter @@ -43,12 +43,13 @@ parser = argparse.ArgumentParser( formatter_class=argparse.RawDescriptionHelpFormatter, description="""lint_py_test_filter is used to filter pylint output for expected errors in Verilator test_regress/*.py tests.""", - epilog="""Copyright 2024-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2024-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--debug', action='store_true', help='enable debug') diff --git a/nodist/log_changes b/nodist/log_changes index 8d016b4cd..293fb5c50 100755 --- a/nodist/log_changes +++ b/nodist/log_changes @@ -58,6 +58,8 @@ def process() -> None: author = am.group(1) if re.search(r'antmicro', email): author += ", Antmicro Ltd." + if re.search(r'tenstorrent', email): + author += ", Testorrent USA, Inc." if re.search(r'github action', author): author = "" continue @@ -118,12 +120,13 @@ parser = argparse.ArgumentParser( allow_abbrev=False, prog="log_changes", description="Create example entries for 'Changes' from parsing 'git log'", - epilog="""Copyright 2019-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2019-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--debug', action='store_true', help='enable debug') Args = parser.parse_args() diff --git a/nodist/uvm_pkg_packer b/nodist/uvm_pkg_packer index f04ad3a42..59373bfc3 100755 --- a/nodist/uvm_pkg_packer +++ b/nodist/uvm_pkg_packer @@ -47,8 +47,7 @@ def process() -> None: def print_header() -> None: print("// DESCR" "IPTION: Verilator: Concatenated UVM header for internal testing") - print("// SPDX-" - "License-Identifier: Apache-2.0") + print("// SP" + "DX-License-Identifier: Apache-2.0") print("//----------------------------------------------------------------------") print("// To recreate:") print("// Using verilator_ext_tests:") @@ -71,12 +70,13 @@ parser = argparse.ArgumentParser( formatter_class=argparse.RawDescriptionHelpFormatter, description="""uvm_pkg_packer is used to create the test_regress uvm_pkg libraries from sources in verilator_ext_test repository's tests.""", - epilog="""Copyright 2025-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2025-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--debug', action='store_true', help='enable debug') parser.add_argument('--test-name', type=str, required=True, help='name of test to run to recreate') diff --git a/nodist/verilator_saif_diff b/nodist/verilator_saif_diff index 78494b240..464a3b221 100755 --- a/nodist/verilator_saif_diff +++ b/nodist/verilator_saif_diff @@ -2,10 +2,10 @@ # pylint: disable=C0114,C0115,C0116,C0301,R0902,R0903,R0912,R0915,W0719,W0718 ###################################################################### # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import argparse diff --git a/nodist/verilog_format b/nodist/verilog_format new file mode 100755 index 000000000..b2d51d062 --- /dev/null +++ b/nodist/verilog_format @@ -0,0 +1,29 @@ +#!/bin/bash +# DESCRIPTION: Verilator: Format Verilog files in standard way. +# +# Usage: nodist/verilog_format +# +# This is currently only intended to be manually called +# to reformat on new Verilog files. +# due to verible-verilog-format issues, it is acceptable to commit +# indentation that is different from what this recommends/changes. +# +# This file ONLY is placed under the Creative Commons Public Domain. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: CC0-1.0 + +verible-verilog-format \ + --inplace \ + --wrap_end_else_clauses \ + --assignment_statement_alignment=flush-left \ + --case_items_alignment=flush-left \ + --class_member_variable_alignment=flush-left \ + --distribution_items_alignment=flush-left \ + --enum_assignment_statement_alignment=flush-left \ + --formal_parameters_alignment=flush-left \ + --module_net_variable_alignment=flush-left \ + --named_parameter_alignment=flush-left \ + --named_port_alignment=flush-left \ + --port_declarations_alignment=flush-left \ + --struct_union_members_alignment=flush-left \ + $* diff --git a/python-dev-requirements.txt b/python-dev-requirements.txt index ac57847d5..11f9fad84 100644 --- a/python-dev-requirements.txt +++ b/python-dev-requirements.txt @@ -1,7 +1,7 @@ -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # These packages are only required for developers who want to run the whole diff --git a/src/.gdbinit b/src/.gdbinit index 42e85e01e..c351a4c2e 100644 --- a/src/.gdbinit +++ b/src/.gdbinit @@ -1,9 +1,9 @@ # DESCRIPTION: Verilator: GDB startup file with useful defines # -# Copyright 2012-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2012-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 define pn diff --git a/src/.gdbinit.py b/src/.gdbinit.py index 22a43e2a6..296573445 100644 --- a/src/.gdbinit.py +++ b/src/.gdbinit.py @@ -1,11 +1,6 @@ # pylint: disable=line-too-long,invalid-name,multiple-statements,missing-function-docstring,missing-class-docstring,missing-module-docstring,no-else-return,too-few-public-methods,unused-argument -# DESCRIPTION: Verilator: GDB startup file with useful define -# -# Copyright 2023 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify the Verilator internals under the terms -# of either the GNU Lesser General Public License Version 3 or the Perl -# Artistic License Version 2.0. -# +# DESCRIPTION: Verilator: GDB startup file with useful defines +# SPDX-FileCopyrightText: 2023 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 2c9f01fe8..7efc365d6 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -4,10 +4,10 @@ # #***************************************************************************** # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ @@ -90,11 +90,9 @@ set(HEADERS V3EmitCConstInit.h V3EmitCFunc.h V3EmitCMain.h - V3EmitCMake.h V3EmitMk.h V3EmitMkJson.h V3EmitV.h - V3EmitXml.h V3Error.h V3ExecGraph.h V3Expand.h @@ -161,6 +159,7 @@ set(HEADERS V3RandSequence.h V3Randomize.h V3Reloop.h + V3Reorder.h V3Rtti.h V3Sampled.h V3Sched.h @@ -189,6 +188,7 @@ set(HEADERS V3Tristate.h V3Udp.h V3Undriven.h + V3UndrivenCapture.h V3UniqueNames.h V3Unknown.h V3Unroll.h @@ -250,6 +250,7 @@ set(COMMON_SOURCES V3DfgOptimizer.cpp V3DfgPasses.cpp V3DfgPeephole.cpp + V3DfgPushDownSels.cpp V3DfgRegularize.cpp V3DfgSynthesize.cpp V3DiagSarif.cpp @@ -261,14 +262,12 @@ set(COMMON_SOURCES V3EmitCImp.cpp V3EmitCInlines.cpp V3EmitCMain.cpp - V3EmitCMake.cpp V3EmitCModel.cpp V3EmitCPch.cpp V3EmitCSyms.cpp V3EmitMk.cpp V3EmitMkJson.cpp V3EmitV.cpp - V3EmitXml.cpp V3Error.cpp V3ExecGraph.cpp V3Expand.cpp @@ -328,6 +327,7 @@ set(COMMON_SOURCES V3RandSequence.cpp V3Randomize.cpp V3Reloop.cpp + V3Reorder.cpp V3Sampled.cpp V3Sched.cpp V3SchedAcyclic.cpp @@ -358,6 +358,7 @@ set(COMMON_SOURCES V3Tristate.cpp V3Udp.cpp V3Undriven.cpp + V3UndrivenCapture.cpp V3Unknown.cpp V3Unroll.cpp V3UnrollGen.cpp diff --git a/src/Makefile.in b/src/Makefile.in index d39ce9805..55913e5d9 100644 --- a/src/Makefile.in +++ b/src/Makefile.in @@ -7,10 +7,10 @@ # #***************************************************************************** # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index 20a6de776..cb80e1dac 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -7,10 +7,10 @@ # #***************************************************************************** # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ @@ -266,17 +266,16 @@ RAW_OBJS_PCH_ASTNOMT = \ V3DfgOptimizer.o \ V3DfgPasses.o \ V3DfgPeephole.o \ + V3DfgPushDownSels.o \ V3DfgRegularize.o \ V3DfgSynthesize.o \ V3DiagSarif.o \ V3DupFinder.o \ V3EmitCMain.o \ - V3EmitCMake.o \ V3EmitCModel.o \ V3EmitCSyms.o \ V3EmitMk.o \ V3EmitMkJson.o \ - V3EmitXml.o \ V3ExecGraph.o \ V3Expand.o \ V3Force.o \ @@ -315,6 +314,7 @@ RAW_OBJS_PCH_ASTNOMT = \ V3RandSequence.o \ V3Randomize.o \ V3Reloop.o \ + V3Reorder.o \ V3Sampled.o \ V3Sched.o \ V3SchedAcyclic.o \ @@ -341,6 +341,7 @@ RAW_OBJS_PCH_ASTNOMT = \ V3Tristate.o \ V3Udp.o \ V3Undriven.o \ + V3UndrivenCapture.o \ V3Unknown.o \ V3Unroll.o \ V3UnrollGen.o \ diff --git a/src/V3Active.cpp b/src/V3Active.cpp index c820ff134..c8122c2c4 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Active.h b/src/V3Active.h index 0f9fe17a3..0e2558c84 100644 --- a/src/V3Active.h +++ b/src/V3Active.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ActiveTop.cpp b/src/V3ActiveTop.cpp index 136b317ee..75f1abeaa 100644 --- a/src/V3ActiveTop.cpp +++ b/src/V3ActiveTop.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ActiveTop.h b/src/V3ActiveTop.h index 53c792614..a94f6c238 100644 --- a/src/V3ActiveTop.h +++ b/src/V3ActiveTop.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index 3bbff4320..e3f1a1cd6 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -24,11 +24,11 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### -// AssertDeFuture +// AssertDeFutureVisitor // If any AstFuture, then move all non-future varrefs to be one cycle behind, // see IEEE 1800-2023 16.9.4. -class AssertDeFuture final : public VNVisitor { +class AssertDeFutureVisitor final : public VNVisitor { // STATE - across all visitors AstNodeModule* const m_modp; // Module future is underneath const AstFuture* m_futurep; // First AstFuture found @@ -99,7 +99,7 @@ class AssertDeFuture final : public VNVisitor { public: // CONSTRUCTORS - explicit AssertDeFuture(AstNode* nodep, AstNodeModule* modp, unsigned pastNum) + explicit AssertDeFutureVisitor(AstNode* nodep, AstNodeModule* modp, unsigned pastNum) : m_modp{modp} , m_pastNum{pastNum} { // See if any Future before we process @@ -112,7 +112,7 @@ public: visit(nodep); // Nodep may get deleted // UINFOTREE(9, nodep, "", "defuture-ou"); } - ~AssertDeFuture() = default; + ~AssertDeFutureVisitor() = default; }; //###################################################################### @@ -394,7 +394,7 @@ class AssertVisitor final : public VNVisitor { void visitAssertionIterate(AstNodeCoverOrAssert* nodep, AstNode* failsp) { if (m_beginp && nodep->name() == "") nodep->name(m_beginp->name()); - { AssertDeFuture{nodep->propp(), m_modp, m_modPastNum++}; } + { AssertDeFutureVisitor{nodep->propp(), m_modp, m_modPastNum++}; } iterateChildren(nodep); AstSenTree* const sentreep = nodep->sentreep(); @@ -595,6 +595,7 @@ class AssertVisitor final : public VNVisitor { AstNodeExpr* propp = nullptr; for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp = VN_AS(itemp->nextp(), CaseItem)) { + AstNodeExpr* itembitp = nullptr; for (AstNodeExpr* icondp = itemp->condsp(); icondp; icondp = VN_AS(icondp->nextp(), NodeExpr)) { AstNodeExpr* onep; @@ -612,17 +613,27 @@ class AssertVisitor final : public VNVisitor { nodep->exprp()->cloneTreePure(false), icondp->cloneTreePure(false)); } + // OR together all conditions within the same case item + if (onep) { + if (itembitp) { + itembitp = new AstOr{icondp->fileline(), onep, itembitp}; + } else { + itembitp = onep; + } + } + } + if (itembitp) { if (propp) { - propp = new AstConcat{icondp->fileline(), onep, propp}; + propp = new AstConcat{itemp->fileline(), itembitp, propp}; } else { - propp = onep; + propp = itembitp; } } } // Empty case means no property if (!propp) propp = new AstConst{nodep->fileline(), AstConst::BitFalse{}}; const bool allow_none = has_default || nodep->unique0Pragma(); - // The following assertion lools as below. + // The following assertion looks as below. // if (!$onehot(propp)) begin // if (propp == '0) begin if (!allow_none) $error("none match"); end // else $error("multiple match"); @@ -686,7 +697,11 @@ class AssertVisitor final : public VNVisitor { m_inSampled = true; iterateChildren(nodep); } - nodep->replaceWith(nodep->exprp()->unlinkFrBack()); + if (nodep->exprp()) { + nodep->replaceWith(nodep->exprp()->unlinkFrBack()); + } else { + nodep->unlinkFrBack(); + } VL_DO_DANGLING(pushDeletep(nodep), nodep); } void visit(AstVarRef* nodep) override { @@ -857,21 +872,18 @@ class AssertVisitor final : public VNVisitor { switch (nodep->ctlType()) { case VAssertCtlType::ON: UINFO(9, "Generating assertctl for a module: " << m_modp); - nodep->replaceWith(new AstCExpr{ - fl, - "vlSymsp->_vm_contextp__->assertOnSet("s + std::to_string(nodep->ctlAssertTypes()) - + ", "s + std::to_string(nodep->ctlDirectiveTypes()) + ");\n"s, - 1}); + nodep->replaceWith( + new AstCStmt{fl, "vlSymsp->_vm_contextp__->assertOnSet("s + + std::to_string(nodep->ctlAssertTypes()) + ", "s + + std::to_string(nodep->ctlDirectiveTypes()) + ");\n"s}); break; case VAssertCtlType::OFF: case VAssertCtlType::KILL: { UINFO(9, "Generating assertctl for a module: " << m_modp); - nodep->replaceWith(new AstCExpr{fl, - "vlSymsp->_vm_contextp__->assertOnClear("s - + std::to_string(nodep->ctlAssertTypes()) + " ,"s - + std::to_string(nodep->ctlDirectiveTypes()) - + ");\n"s, - 1}); + nodep->replaceWith( + new AstCStmt{fl, "vlSymsp->_vm_contextp__->assertOnClear("s + + std::to_string(nodep->ctlAssertTypes()) + " ,"s + + std::to_string(nodep->ctlDirectiveTypes()) + ");\n"s}); break; } case VAssertCtlType::LOCK: diff --git a/src/V3Assert.h b/src/V3Assert.h index 939d97040..dbaac13bf 100644 --- a/src/V3Assert.h +++ b/src/V3Assert.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp index f6695f29a..f740de1c9 100644 --- a/src/V3AssertPre.cpp +++ b/src/V3AssertPre.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -54,8 +54,10 @@ private: AstSenItem* m_seniAlwaysp = nullptr; // Last sensitivity in always // Reset each assertion: AstNodeExpr* m_disablep = nullptr; // Last disable + AstIf* m_disableSeqIfp = nullptr; // Used for handling disable iff in sequences // Other: V3UniqueNames m_cycleDlyNames{"__VcycleDly"}; // Cycle delay counter name generator + V3UniqueNames m_disableCntNames{"__VdisableCnt"}; // Disable condition counter name generator bool m_inAssign = false; // True if in an AssignNode bool m_inAssignDlyLhs = false; // True if in AssignDly's LHS bool m_inSynchDrive = false; // True if in synchronous drive @@ -158,7 +160,7 @@ private: // It has to be converted to a list of ModportClockingVarRefs, // because clocking blocks are removed in this pass for (AstNode* itemp = nodep->clockingp()->itemsp(); itemp; itemp = itemp->nextp()) { - if (AstClockingItem* citemp = VN_CAST(itemp, ClockingItem)) { + if (const AstClockingItem* citemp = VN_CAST(itemp, ClockingItem)) { if (AstVar* const varp = citemp->varp() ? citemp->varp() : VN_AS(citemp->user1p(), Var)) { AstModportVarRef* const modVarp = new AstModportVarRef{ @@ -374,6 +376,11 @@ private: new AstConst{flp, 1}}}); beginp->addStmtsp(loopp); } + if (m_disableSeqIfp) { + AstIf* const disableSeqIfp = m_disableSeqIfp->cloneTree(false); + disableSeqIfp->addThensp(nodep->nextp()->unlinkFrBackWithNext()); + nodep->addNextHere(disableSeqIfp); + } nodep->replaceWith(beginp); VL_DO_DANGLING(nodep->deleteTree(), nodep); } @@ -382,6 +389,14 @@ private: nodep->v3error("Event controls cannot be used in " "synchronous drives (IEEE 1800-2023 14.16)"); } + + const AstSampled* sampledp; + if (nodep->exists([&sampledp](const AstSampled* const sp) { + sampledp = sp; + return true; + })) { + sampledp->v3warn(E_UNSUPPORTED, "Unsupported: $sampled inside sensitivity list"); + } } void visit(AstNodeVarRef* nodep) override { UINFO(8, " -varref: " << nodep); @@ -632,19 +647,72 @@ private: // Unlink and just keep a pointer to it, convert to sentree as needed m_senip = nodep->sensesp(); iterateNull(nodep->disablep()); + if (VN_AS(nodep->backp(), NodeCoverOrAssert)->type() == VAssertType::CONCURRENT) { + const AstNodeDType* const propDtp = nodep->propp()->dtypep(); + nodep->propp(new AstSampled{nodep->fileline(), nodep->propp()->unlinkFrBack()}); + nodep->propp()->dtypeFrom(propDtp); + } iterate(nodep->propp()); } void visit(AstPExpr* nodep) override { - VL_RESTORER(m_inPExpr); - m_inPExpr = true; - if (AstLogNot* const notp = VN_CAST(nodep->backp(), LogNot)) { notp->replaceWith(nodep->unlinkFrBack()); VL_DO_DANGLING(pushDeletep(notp), notp); iterate(nodep); - } else { - iterateChildren(nodep); + return; } + VL_RESTORER(m_inPExpr); + VL_RESTORER(m_disableSeqIfp); + m_inPExpr = true; + + if (m_disablep) { + const AstSampled* sampledp; + if (m_disablep->exists([&sampledp](const AstSampled* const sp) { + sampledp = sp; + return true; + })) { + sampledp->v3warn(E_UNSUPPORTED, + "Unsupported: $sampled inside disabled condition of a sequence"); + m_disablep = new AstConst{m_disablep->fileline(), AstConst::BitFalse{}}; + // always a copy is used, so remove it now + pushDeletep(m_disablep); + } + FileLine* const flp = nodep->fileline(); + // Add counter which counts times the condition turned true + AstVar* const disableCntp + = new AstVar{flp, VVarType::MODULETEMP, m_disableCntNames.get(""), + nodep->findBasicDType(VBasicDTypeKwd::UINT32)}; + disableCntp->lifetime(VLifetime::STATIC_EXPLICIT); + m_modp->addStmtsp(disableCntp); + AstVarRef* const readCntRefp = new AstVarRef{flp, disableCntp, VAccess::READ}; + AstVarRef* const writeCntRefp = new AstVarRef{flp, disableCntp, VAccess::WRITE}; + AstAssign* const incrStmtp = new AstAssign{ + flp, writeCntRefp, new AstAdd{flp, readCntRefp, new AstConst{flp, 1}}}; + AstAlways* const alwaysp + = new AstAlways{flp, VAlwaysKwd::ALWAYS, + new AstSenTree{flp, new AstSenItem{flp, VEdgeType::ET_POSEDGE, + m_disablep->cloneTree(false)}}, + incrStmtp}; + disableCntp->addNextHere(alwaysp); + + // Store value of that counter at the beginning of sequence evaluation + AstBegin* const bodyp = nodep->bodyp(); + AstVar* const initialCntp = new AstVar{flp, VVarType::BLOCKTEMP, "__VinitialCnt", + nodep->findBasicDType(VBasicDTypeKwd::UINT32)}; + initialCntp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); + bodyp->stmtsp()->addHereThisAsNext(initialCntp); + AstAssign* const assignp + = new AstAssign{flp, new AstVarRef{flp, initialCntp, VAccess::WRITE}, + readCntRefp->cloneTree(false)}; + initialCntp->addNextHere(assignp); + + m_disableSeqIfp + = new AstIf{flp, new AstEq{flp, new AstVarRef{flp, initialCntp, VAccess::READ}, + readCntRefp->cloneTree(false)}}; + // Delete it, because it is always copied before insetion to the AST + pushDeletep(m_disableSeqIfp); + } + iterateChildren(nodep); } void visit(AstNodeModule* nodep) override { VL_RESTORER(m_defaultClockingp); diff --git a/src/V3AssertPre.h b/src/V3AssertPre.h index d087e77aa..da98013a6 100644 --- a/src/V3AssertPre.h +++ b/src/V3AssertPre.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3AssertProp.cpp b/src/V3AssertProp.cpp index 131b771ee..6cc674c9f 100644 --- a/src/V3AssertProp.cpp +++ b/src/V3AssertProp.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3AssertProp.h b/src/V3AssertProp.h index afb90559d..4df165a28 100644 --- a/src/V3AssertProp.h +++ b/src/V3AssertProp.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index 156f4bf5b..fc05797e7 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -139,6 +139,13 @@ AstNode* AstNode::abovep() const { const AstNode* const firstp = firstAbovep() ? this : m_headtailp; return firstp->backp(); } +AstNode* AstNode::aboveLoopp() const { + // Returns parent node. Avoid using this, may have performance issues. + const AstNode* nodep = this; + // Backwards over peers (versus parents) + while (nodep->backp() && nodep->backp()->nextp() == nodep) nodep = nodep->backp(); + return nodep->backp(); +} string AstNode::encodeName(const string& namein) { // Encode signal name raw from parser, then not called again on same signal diff --git a/src/V3Ast.h b/src/V3Ast.h index bb1a57f8b..1051a4b31 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -540,6 +540,7 @@ public: AstNode* nextp() const VL_MT_STABLE { return m_nextp; } AstNode* backp() const VL_MT_STABLE { return m_backp; } AstNode* abovep() const; // Get parent node above, only for list head and tail + AstNode* aboveLoopp() const; // Get parent node above, may have performance issues as loops AstNode* op1p() const VL_MT_STABLE { return m_op1p; } AstNode* op2p() const VL_MT_STABLE { return m_op2p; } AstNode* op3p() const VL_MT_STABLE { return m_op3p; } @@ -609,6 +610,7 @@ public: static string vcdName(const string& namein); // Name for printing out to vcd files string prettyName() const { return prettyName(name()); } string prettyNameQ() const { return prettyNameQ(name()); } + string verilogName() const { return vpiName(origName()); } // Decoded original Verilog name // "VARREF" for error messages (NOT dtype's pretty name) string prettyTypeName() const; virtual string prettyOperatorName() const { return "operator " + prettyTypeName(); } @@ -637,6 +639,7 @@ public: int widthWords() const { return VL_WORDS_I(width()); } bool isQuad() const VL_MT_STABLE { return (width() > VL_IDATASIZE && width() <= VL_QUADSIZE); } bool isWide() const VL_MT_STABLE { return (width() > VL_QUADSIZE); } + inline bool isCHandle() const VL_MT_STABLE; inline bool isDouble() const VL_MT_STABLE; inline bool isSigned() const VL_MT_STABLE; inline bool isString() const VL_MT_STABLE; @@ -653,8 +656,9 @@ public: void user1p(void* userp) { user1u(VNUser{userp}); } void user1(int val) { user1u(VNUser{val}); } int user1() const { return user1u().toInt(); } - int user1Inc(int val = 1) { int v = user1(); user1(v + val); return v; } - int user1SetOnce() { int v = user1(); if (!v) user1(1); return v; } // Better for cache than user1Inc() + int user1Inc(int val = 1) { const int v = user1(); user1(v + val); return v; } + int user1Or(int val) { const int v = user1(); user1(v | val); return v; } + int user1SetOnce() { const int v = user1(); if (!v) user1(1); return v; } // Better for cache than user1Inc() static void user1ClearTree() { VNUser1InUse::clear(); } // Clear userp()'s across the entire tree VNUser user2u() const VL_MT_STABLE { @@ -667,8 +671,9 @@ public: void user2p(void* userp) { user2u(VNUser{userp}); } void user2(int val) { user2u(VNUser{val}); } int user2() const { return user2u().toInt(); } - int user2Inc(int val = 1) { int v = user2(); user2(v + val); return v; } - int user2SetOnce() { int v = user2(); if (!v) user2(1); return v; } // Better for cache than user2Inc() + int user2Inc(int val = 1) { const int v = user2(); user2(v + val); return v; } + int user2Or(int val) { const int v = user2(); user2(v | val); return v; } + int user2SetOnce() { const int v = user2(); if (!v) user2(1); return v; } // Better for cache than user2Inc() static void user2ClearTree() { VNUser2InUse::clear(); } // Clear userp()'s across the entire tree VNUser user3u() const VL_MT_STABLE { @@ -681,8 +686,9 @@ public: void user3p(void* userp) { user3u(VNUser{userp}); } void user3(int val) { user3u(VNUser{val}); } int user3() const { return user3u().toInt(); } - int user3Inc(int val = 1) { int v = user3(); user3(v + val); return v; } - int user3SetOnce() { int v = user3(); if (!v) user3(1); return v; } // Better for cache than user3Inc() + int user3Inc(int val = 1) { const int v = user3(); user3(v + val); return v; } + int user3Or(int val) { const int v = user3(); user3(v | val); return v; } + int user3SetOnce() { const int v = user3(); if (!v) user3(1); return v; } // Better for cache than user3Inc() static void user3ClearTree() { VNUser3InUse::clear(); } // Clear userp()'s across the entire tree VNUser user4u() const VL_MT_STABLE { @@ -695,8 +701,9 @@ public: void user4p(void* userp) { user4u(VNUser{userp}); } void user4(int val) { user4u(VNUser{val}); } int user4() const { return user4u().toInt(); } - int user4Inc(int val = 1) { int v = user4(); user4(v + val); return v; } - int user4SetOnce() { int v = user4(); if (!v) user4(1); return v; } // Better for cache than user4Inc() + int user4Or(int val) { const int v = user4(); user4(v | val); return v; } + int user4Inc(int val = 1) { const int v = user4(); user4(v + val); return v; } + int user4SetOnce() { const int v = user4(); if (!v) user4(1); return v; } // Better for cache than user4Inc() static void user4ClearTree() { VNUser4InUse::clear(); } // Clear userp()'s across the entire tree // clang-format on @@ -775,6 +782,11 @@ public: AstNodeDType* findVoidDType() const; AstNodeDType* findBitDType(int width, int widthMin, VSigning numeric) const; AstNodeDType* findLogicDType(int width, int widthMin, VSigning numeric) const; + AstNodeDType* findBitOrLogicDType(int width, int widthMin, VSigning numeric, + bool isFourstate) const { + return isFourstate ? findLogicDType(width, widthMin, numeric) + : findBitDType(width, widthMin, numeric); + } AstNodeDType* findLogicRangeDType(const VNumRange& range, int widthMin, VSigning numeric) const VL_MT_STABLE; AstNodeDType* findBitRangeDType(const VNumRange& range, int widthMin, @@ -815,6 +827,16 @@ public: if (!newp) return nodep; return static_cast(addNext(nodep, newp)); } + template + static T_NodeResult* addNextNull(T_NodeResult* nodep, T_NodeNext* newp) { + static_assert(std::is_base_of::value, + "'T_NodeResult' must be a subtype of AstNode"); + static_assert(std::is_base_of::value, + "'T_NodeNext' must be a subtype of 'T_NodeResult'"); + if (!newp) return nodep; + if (!nodep) return newp; + return static_cast(addNext(nodep, newp)); + } inline AstNode* addNext(AstNode* newp); void addNextHere(AstNode* newp); // Insert newp at this->nextp void addHereThisAsNext(AstNode* newp); // Adds at old place of this, this becomes next diff --git a/src/V3AstAttr.h b/src/V3AstAttr.h index b73bb419c..e879adfed 100644 --- a/src/V3AstAttr.h +++ b/src/V3AstAttr.h @@ -6,9 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU Lesser -// General Public License Version 3 or the Perl Artistic License Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -412,6 +413,8 @@ public: BIT, BYTE, CHANDLE, + // Void type for tagged union members (CVOID to avoid Windows VOID macro) + CVOID, EVENT, INT, INTEGER, @@ -449,6 +452,7 @@ public: "bit", "byte", "chandle", + "void", "event", "int", "integer", @@ -476,13 +480,35 @@ public: return names[m_e]; } const char* dpiType() const { - static const char* const names[] - = {"%E-unk", "svBit", "char", "void*", "char", - "int", "%E-integer", "svLogic", "long long", "double", - "short", "%E-time", "const char*", "%E-untyped", "dpiScope", - "const char*", "%E-mtaskstate", "%E-dly-sched", "%E-trig-sched", "%E-dyn-sched", - "%E-fork", "%E-proc-ref", "%E-rand-gen", "%E-stdrand-gen", "IData", - "QData", "%E-logic-implct", " MAX"}; + static const char* const names[] = {"%E-unk", + "svBit", + "char", + "void*", + "void", + "char", + "int", + "%E-integer", + "svLogic", + "long long", + "double", + "short", + "%E-time", + "const char*", + "%E-untyped", + "dpiScope", + "const char*", + "%E-mtaskstate", + "%E-dly-sched", + "%E-trig-sched", + "%E-dyn-sched", + "%E-fork", + "%E-proc-ref", + "%E-rand-gen", + "%E-stdrand-gen", + "IData", + "QData", + "%E-logic-implct", + " MAX"}; return names[m_e]; } static void selfTest() { @@ -565,6 +591,7 @@ public: || m_e == RANDOM_GENERATOR || m_e == RANDOM_STDGENERATOR || m_e == DOUBLE || m_e == UNTYPED); } + bool isCHandle() const VL_MT_SAFE { return m_e == CHANDLE; } bool isDouble() const VL_MT_SAFE { return m_e == DOUBLE; } bool isEvent() const { return m_e == EVENT; } bool isString() const VL_MT_SAFE { return m_e == STRING; } @@ -596,6 +623,7 @@ public: /* BIT: */ "BIT", /* BYTE: */ "BYTE", /* CHANDLE: */ "LONGINT", + /* CVOID: */ "", // Should not be traced /* EVENT: */ "EVENT", /* INT: */ "INT", /* INTEGER: */ "INTEGER", @@ -787,12 +815,18 @@ public: RANDOMIZER_CLEARCONSTRAINTS, RANDOMIZER_CLEARALL, RANDOMIZER_HARD, + RANDOMIZER_UNIQUE, + RANDOMIZER_MARK_RANDC, + RANDOMIZER_SOLVE_BEFORE, RANDOMIZER_WRITE_VAR, RNG_GET_RANDSTATE, RNG_SET_RANDSTATE, SCHED_ANY_TRIGGERED, SCHED_AWAITING_CURRENT_TIME, + SCHED_AWAITING_ZERO_DELAY, + SCHED_READY, SCHED_COMMIT, + SCHED_MOVE_TO_RESUME_QUEUE, SCHED_DELAY, SCHED_DO_POST_UPDATES, SCHED_ENQUEUE, @@ -800,6 +834,7 @@ public: SCHED_EVALUATION, SCHED_POST_UPDATE, SCHED_RESUME, + SCHED_RESUME_ZERO_DELAY, SCHED_RESUMPTION, SCHED_TRIGGER, UNPACKED_ASSIGN, @@ -916,12 +951,18 @@ inline std::ostream& operator<<(std::ostream& os, const VCMethod& rhs) { {RANDOMIZER_CLEARCONSTRAINTS, "clearConstraints", false}, \ {RANDOMIZER_CLEARALL, "clearAll", false}, \ {RANDOMIZER_HARD, "hard", false}, \ + {RANDOMIZER_UNIQUE, "rand_unique", false}, \ + {RANDOMIZER_MARK_RANDC, "markRandc", false}, \ + {RANDOMIZER_SOLVE_BEFORE, "solveBefore", false}, \ {RANDOMIZER_WRITE_VAR, "write_var", false}, \ {RNG_GET_RANDSTATE, "__Vm_rng.get_randstate", true}, \ {RNG_SET_RANDSTATE, "__Vm_rng.set_randstate", false}, \ {SCHED_ANY_TRIGGERED, "anyTriggered", false}, \ {SCHED_AWAITING_CURRENT_TIME, "awaitingCurrentTime", true}, \ + {SCHED_AWAITING_ZERO_DELAY, "awaitingZeroDelay", true}, \ + {SCHED_READY, "ready", false}, \ {SCHED_COMMIT, "commit", false}, \ + {SCHED_MOVE_TO_RESUME_QUEUE, "moveToResumeQueue", false}, \ {SCHED_DELAY, "delay", false}, \ {SCHED_DO_POST_UPDATES, "doPostUpdates", false}, \ {SCHED_ENQUEUE, "enqueue", false}, \ @@ -929,6 +970,7 @@ inline std::ostream& operator<<(std::ostream& os, const VCMethod& rhs) { {SCHED_EVALUATION, "evaluation", false}, \ {SCHED_POST_UPDATE, "postUpdate", false}, \ {SCHED_RESUME, "resume", false}, \ + {SCHED_RESUME_ZERO_DELAY, "resumeZeroDelay", false}, \ {SCHED_RESUMPTION, "resumption", false}, \ {SCHED_TRIGGER, "trigger", false}, \ {UNPACKED_ASSIGN, "assign", false}, \ @@ -940,7 +982,14 @@ inline std::ostream& operator<<(std::ostream& os, const VCMethod& rhs) { class VCaseType final { public: - enum en : uint8_t { CT_CASE, CT_CASEX, CT_CASEZ, CT_CASEINSIDE, CT_RANDSEQUENCE }; + enum en : uint8_t { + CT_CASE, + CT_CASEX, + CT_CASEZ, + CT_CASEINSIDE, + CT_CASEMATCHES, + CT_RANDSEQUENCE + }; enum en m_e; VCaseType() : m_e{CT_CASE} {} @@ -1019,10 +1068,6 @@ public: static const char* const names[] = {"", "input", "output", "inout", "ref", "const ref"}; return names[m_e]; } - string xmlKwd() const { // For historical reasons no "put" suffix - static const char* const names[] = {"", "in", "out", "inout", "ref", "const ref"}; - return names[m_e]; - } string prettyName() const { return verilogKwd(); } bool isAny() const { return m_e != NONE; } bool isInout() const { return m_e == INOUT; } @@ -1433,6 +1478,7 @@ public: UNROLL_FULL, FULL_CASE, PARALLEL_CASE, + VERILATOR_LIB, _ENUM_SIZE }; enum en m_e; @@ -1451,6 +1497,7 @@ public: "UNROLL_FULL", // "FULL_CASE", // "PARALLEL_CASE", // + "VERILATOR_LIB", // "_ENUM_SIZE" // }; return names[m_e]; diff --git a/src/V3AstInlines.h b/src/V3AstInlines.h index ccc03b4cd..bb7fffb45 100644 --- a/src/V3AstInlines.h +++ b/src/V3AstInlines.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -33,6 +33,9 @@ bool AstNode::width1() const { // V3Const uses to know it can optimize int AstNode::widthInstrs() const { return (!dtypep() ? 1 : (dtypep()->isWide() ? dtypep()->widthWords() : 1)); } +bool AstNode::isCHandle() const VL_MT_STABLE { + return dtypep() && dtypep()->basicp() && dtypep()->basicp()->isCHandle(); +} bool AstNode::isDouble() const VL_MT_STABLE { return dtypep() && dtypep()->basicp() && dtypep()->basicp()->isDouble(); } @@ -77,8 +80,8 @@ int AstNodeArrayDType::lo() const VL_MT_STABLE { return rangep()->loConst(); } int AstNodeArrayDType::elementsConst() const VL_MT_STABLE { return rangep()->elementsConst(); } VNumRange AstNodeArrayDType::declRange() const VL_MT_STABLE { return VNumRange{left(), right()}; } -AstFuncRef::AstFuncRef(FileLine* fl, AstFunc* taskp, AstNodeExpr* pinsp) - : ASTGEN_SUPER_FuncRef(fl, taskp->name(), pinsp) { +AstFuncRef::AstFuncRef(FileLine* fl, AstFunc* taskp, AstArg* argsp) + : ASTGEN_SUPER_FuncRef(fl, taskp->name(), argsp) { this->taskp(taskp); dtypeFrom(taskp); } @@ -126,8 +129,8 @@ int AstQueueDType::boundConst() const VL_MT_STABLE { return (constp ? constp->toSInt() : 0); } -AstTaskRef::AstTaskRef(FileLine* fl, AstTask* taskp, AstNodeExpr* pinsp) - : ASTGEN_SUPER_TaskRef(fl, taskp->name(), pinsp) { +AstTaskRef::AstTaskRef(FileLine* fl, AstTask* taskp, AstArg* argsp) + : ASTGEN_SUPER_TaskRef(fl, taskp->name(), argsp) { this->taskp(taskp); dtypeSetVoid(); } diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h index e939bc93c..4d5bd6046 100644 --- a/src/V3AstNodeDType.h +++ b/src/V3AstNodeDType.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -234,7 +234,7 @@ class AstNodeUOrStructDType VL_NOT_FINAL : public AstNodeDType { string m_name; // Name from upper typedef, if any const int m_uniqueNum; bool m_packed; - bool m_isFourstate = false; // V3Width computes + bool m_isFourstate = false; // V3Width computes; true if any member is 4-state bool m_constrainedRand = false; // True if struct has constraint expression protected: @@ -291,7 +291,7 @@ public: VNumRange declRange() const VL_MT_STABLE { return VNumRange{hi(), lo()}; } AstNodeModule* classOrPackagep() const { return m_classOrPackagep; } void classOrPackagep(AstNodeModule* classpackagep) { m_classOrPackagep = classpackagep; } - bool isConstrainedRand() { return m_constrainedRand; } + bool isConstrainedRand() const { return m_constrainedRand; } void markConstrainedRand(bool flag) { m_constrainedRand = flag; } }; @@ -458,6 +458,7 @@ public: return m.m_keyword; } bool isBitLogic() const { return keyword().isBitLogic(); } + bool isCHandle() const VL_MT_STABLE { return keyword().isCHandle(); } bool isDouble() const VL_MT_STABLE { return keyword().isDouble(); } bool isEvent() const VL_MT_STABLE { return keyword() == VBasicDTypeKwd::EVENT; } bool isForkSync() const VL_MT_SAFE { return keyword() == VBasicDTypeKwd::FORK_SYNC; } @@ -1471,19 +1472,24 @@ public: }; class AstUnionDType final : public AstNodeUOrStructDType { bool m_isSoft; // Is a "union soft" + bool m_isTagged; // Is a "union tagged" public: - // UNSUP: bool isTagged; // VSigning below is mispurposed to indicate if packed or not // isSoft implies packed - AstUnionDType(FileLine* fl, bool isSoft, VSigning numericUnpack) + AstUnionDType(FileLine* fl, bool isSoft, bool isTagged, VSigning numericUnpack) : ASTGEN_SUPER_UnionDType(fl, numericUnpack) - , m_isSoft{isSoft} { + , m_isSoft{isSoft} + , m_isTagged{isTagged} { packed(packed() | m_isSoft); } ASTGEN_MEMBERS_AstUnionDType; string verilogKwd() const override { return "union"; } bool isSoft() const { return m_isSoft; } + bool isTagged() const { return m_isTagged; } + bool sameNode(const AstNode* samep) const override; + void dump(std::ostream& str) const override; + void dumpJson(std::ostream& str) const override; }; #endif // Guard diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index 255605c4f..cbf596680 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -6,9 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU Lesser -// General Public License Version 3 or the Perl Artistic License Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -51,8 +52,8 @@ public: // METHODS void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; - // TODO: The only AstNodeExpr without dtype is AstArg. Otherwise this could be final. - bool hasDType() const override VL_MT_SAFE { return true; } + // Every expression must have a data type after V3Width + bool hasDType() const override final VL_MT_SAFE { return true; } virtual string emitVerilog() = 0; /// Format string for verilog writing; see V3EmitV // For documentation on emitC format see EmitCFunc::emitOpName virtual string emitC() = 0; @@ -218,9 +219,9 @@ public: }; class AstNodeFTaskRef VL_NOT_FINAL : public AstNodeExpr { // A reference to a task (or function) - // @astgen op1 := namep : Optional[AstNode] - // op2 used by some sub-types only - // @astgen op3 := pinsp : List[AstNodeExpr] + // op1 used by some sub-types only + // @astgen op2 := argsp : List[AstArg] + // @astgen op3 := withp : Optional[AstWith] // @astgen op4 := scopeNamep : Optional[AstScopeName] // // @astgen ptr := m_taskp : Optional[AstNodeFTask] // [AfterLink] Pointer to task referenced @@ -234,10 +235,10 @@ private: VIsCached m_purity; // Pure state protected: - AstNodeFTaskRef(VNType t, FileLine* fl, const string& name, AstNodeExpr* pinsp) + AstNodeFTaskRef(VNType t, FileLine* fl, const string& name, AstArg* argsp) : AstNodeExpr{t, fl} , m_name{name} { - addPinsp(pinsp); + addArgsp(argsp); } public: @@ -501,6 +502,53 @@ public: // === Concrete node types ===================================================== +// === AstNode === +class AstArg final : public AstNode { + // An argument to a function/task, which is either an expression, or is a placeholder for an + // omitted argument. + // @astgen op1 := exprp : Optional[AstNodeExpr] // nullptr if omitted + std::string m_name; // Argument name, or "" for number based interconnect +public: + AstArg(FileLine* fl, const std::string& name, AstNodeExpr* exprp) + : ASTGEN_SUPER_Arg(fl) + , m_name{name} { + this->exprp(exprp); + } + ASTGEN_MEMBERS_AstArg; + std::string name() const override VL_MT_STABLE { return m_name; } + void name(const std::string& name) override { m_name = name; } + bool emptyConnectNoNext() const { return !exprp() && name() == "" && !nextp(); } +}; +class AstWith final : public AstNode { + // Similar to AstArg, but this is essentially a lambda passed to a call. + // Not an AstNodeExpr as there is no concept of function values in Verilator + // The dtypep() contains the with lambda's return dtype, not a function type. + // Parents: NodeFTaskRef, CMethodHard + // Children: LambdaArgRef that declares the item variable + // Children: LambdaArgRef that declares the item.index variable + // Children: expression (equation establishing the with) + // @astgen op1 := indexArgRefp : AstLambdaArgRef + // @astgen op2 := valueArgRefp : AstLambdaArgRef + // @astgen op3 := exprp : List[AstNode] // Pins, expression and constraints + // TODO: Separate expression and constraints +public: + AstWith(FileLine* fl, AstLambdaArgRef* indexArgRefp, AstLambdaArgRef* valueArgRefp, + AstNode* exprp) + : ASTGEN_SUPER_With(fl) { + this->indexArgRefp(indexArgRefp); + this->valueArgRefp(valueArgRefp); + addExprp(exprp); + } + ASTGEN_MEMBERS_AstWith; + bool hasDType() const override { return true; } + bool sameNode(const AstNode* /*samep*/) const override { return true; } + const char* broken() const override { + BROKEN_RTN(!indexArgRefp()); // varp needed to know lambda's arg dtype + BROKEN_RTN(!valueArgRefp()); // varp needed to know lambda's arg dtype + return nullptr; + } +}; + // === AstNodeExpr === class AstAddrOfCFunc final : public AstNodeExpr { // Get address of CFunc @@ -521,28 +569,6 @@ public: bool cleanOut() const override { return true; } AstCFunc* funcp() const { return m_funcp; } }; -class AstArg final : public AstNodeExpr { - // An argument to a function/task, which is either an expression, or is a placeholder for an - // omitted argument. - // TODO: AstArg should not be AstNodeExpr, but is currently used as such widely. Fix later. - // @astgen op1 := exprp : Optional[AstNodeExpr] // nullptr if omitted - string m_name; // Pin name, or "" for number based interconnect -public: - AstArg(FileLine* fl, const string& name, AstNodeExpr* exprp) - : ASTGEN_SUPER_Arg(fl) - , m_name{name} { - this->exprp(exprp); - } - ASTGEN_MEMBERS_AstArg; - bool hasDType() const override VL_MT_SAFE { return false; } - string name() const override VL_MT_STABLE { return m_name; } // * = Pin name, ""=go by number - void name(const string& name) override { m_name = name; } - bool emptyConnectNoNext() const { return !exprp() && name() == "" && !nextp(); } - - string emitVerilog() override { V3ERROR_NA_RETURN(""); } - string emitC() override { V3ERROR_NA_RETURN(""); } - bool cleanOut() const override { V3ERROR_NA_RETURN(true); } -}; class AstAttrOf final : public AstNodeExpr { // Return a value of a attribute, for example a LSB or array LSB of a signal // @astgen op1 := fromp : Optional[AstNode] @@ -642,6 +668,7 @@ class AstCMethodHard final : public AstNodeExpr { // PARENTS: stmt/expr // @astgen op1 := fromp : AstNodeExpr // Subject of method call // @astgen op2 := pinsp : List[AstNodeExpr] // Arguments + // @astgen op3 := withp : Optional[AstWith] // With clause VCMethod m_method; // Which method to call bool m_pure = false; // Pure optimizable bool m_usePtr = false; // Use '->' not '.' @@ -672,6 +699,32 @@ public: private: void setPurity(); }; +class AstCReset final : public AstNodeExpr { + // Reset variable at startup + const bool m_constructing; // Previously cleared by constructor +public: + AstCReset(FileLine* fl, AstVar* varp, bool constructing) + : ASTGEN_SUPER_CReset(fl) + , m_constructing{constructing} { + dtypeFrom(varp); + } + ASTGEN_MEMBERS_AstCReset; + void dump(std::ostream& str) const override; + void dumpJson(std::ostream& str) const override; + bool isPure() override { return true; } + int instrCount() const override { return widthInstrs(); } + string emitVerilog() override { V3ERROR_NA_RETURN(""); } + string emitC() override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { return true; } + const char* broken() const override { + BROKEN_RTN(!VN_IS(backp(), NodeAssign)); // V3Emit* assumption + return nullptr; + } + bool sameNode(const AstNode* samep) const override { + return constructing() == VN_DBG_AS(samep, CReset)->constructing(); + } + bool constructing() const { return m_constructing; } +}; class AstCast final : public AstNodeExpr { // Cast to appropriate data type // @astgen op1 := fromp : AstNodeExpr @@ -723,7 +776,6 @@ public: this->rhsp(rhsp); } ASTGEN_MEMBERS_AstCastSize; - // No hasDType because widthing removes this node before the hasDType check string emitVerilog() override { return "((%r)'(%l))"; } string emitC() override { V3ERROR_NA_RETURN(""); } bool cleanOut() const override { V3ERROR_NA_RETURN(true); } @@ -796,16 +848,15 @@ public: void classOrPackagep(AstNodeModule* nodep) { m_classOrPackageNodep = reinterpret_cast(nodep); } - bool hasDType() const override VL_MT_SAFE { return false; } string emitVerilog() override { V3ERROR_NA_RETURN(""); } string emitC() override { V3ERROR_NA_RETURN(""); } bool cleanOut() const override { V3ERROR_NA_RETURN(true); } }; class AstConsAssoc final : public AstNodeExpr { // Construct an assoc array and return object, '{} - // @astgen op1 := defaultp : Optional[AstNode] + // @astgen op1 := defaultp : Optional[AstNodeExpr] public: - AstConsAssoc(FileLine* fl, AstNode* defaultp) + AstConsAssoc(FileLine* fl, AstNodeExpr* defaultp) : ASTGEN_SUPER_ConsAssoc(fl) { this->defaultp(defaultp); } @@ -819,8 +870,8 @@ public: }; class AstConsDynArray final : public AstNodeExpr { // Construct a queue and return object, '{}. '{lhs}, '{lhs. rhs} - // @astgen op1 := lhsp : Optional[AstNode] - // @astgen op2 := rhsp : Optional[AstNode] + // @astgen op1 := lhsp : Optional[AstNodeExpr] + // @astgen op2 := rhsp : Optional[AstNodeExpr] const bool m_lhsIsValue; // LHS constructs value inside the queue, not concat const bool m_rhsIsValue; // RHS constructs value inside the queue, not concat public: @@ -828,8 +879,8 @@ public: : ASTGEN_SUPER_ConsDynArray(fl) , m_lhsIsValue{false} , m_rhsIsValue{false} {} - explicit AstConsDynArray(FileLine* fl, bool lhsIsValue, AstNode* lhsp, bool rhsIsValue, - AstNode* rhsp) + explicit AstConsDynArray(FileLine* fl, bool lhsIsValue, AstNodeExpr* lhsp, bool rhsIsValue, + AstNodeExpr* rhsp) : ASTGEN_SUPER_ConsDynArray(fl) , m_lhsIsValue{lhsIsValue} , m_rhsIsValue{rhsIsValue} { @@ -898,8 +949,8 @@ public: }; class AstConsQueue final : public AstNodeExpr { // Construct a queue and return object, '{}. '{lhs}, '{lhs. rhs} - // @astgen op1 := lhsp : Optional[AstNode] - // @astgen op2 := rhsp : Optional[AstNode] + // @astgen op1 := lhsp : Optional[AstNodeExpr] + // @astgen op2 := rhsp : Optional[AstNodeExpr] const bool m_lhsIsValue; // LHS constructs value inside the queue, not concat const bool m_rhsIsValue; // RHS constructs value inside the queue, not concat public: @@ -907,8 +958,8 @@ public: : ASTGEN_SUPER_ConsQueue(fl) , m_lhsIsValue{false} , m_rhsIsValue{false} {} - explicit AstConsQueue(FileLine* fl, bool lhsIsValue, AstNode* lhsp, bool rhsIsValue, - AstNode* rhsp) + explicit AstConsQueue(FileLine* fl, bool lhsIsValue, AstNodeExpr* lhsp, bool rhsIsValue, + AstNodeExpr* rhsp) : ASTGEN_SUPER_ConsQueue(fl) , m_lhsIsValue{lhsIsValue} , m_rhsIsValue{rhsIsValue} { @@ -932,9 +983,9 @@ public: }; class AstConsWildcard final : public AstNodeExpr { // Construct a wildcard assoc array and return object, '{} - // @astgen op1 := defaultp : Optional[AstNode] + // @astgen op1 := defaultp : Optional[AstNodeExpr] public: - AstConsWildcard(FileLine* fl, AstNode* defaultp) + AstConsWildcard(FileLine* fl, AstNodeExpr* defaultp) : ASTGEN_SUPER_ConsWildcard(fl) { this->defaultp(defaultp); } @@ -1340,14 +1391,14 @@ public: return resultp()->isPure(); } bool sameNode(const AstNode*) const override { return true; } - bool hasResult() { return m_hasResult; } + bool hasResult() const { return m_hasResult; } void hasResult(bool flag) { m_hasResult = flag; } }; class AstFError final : public AstNodeExpr { - // @astgen op1 := filep : AstNode - // @astgen op2 := strp : AstNode + // @astgen op1 := filep : AstNodeExpr + // @astgen op2 := strp : AstNodeExpr public: - AstFError(FileLine* fl, AstNode* filep, AstNode* strp) + AstFError(FileLine* fl, AstNodeExpr* filep, AstNodeExpr* strp) : ASTGEN_SUPER_FError(fl) { this->filep(filep); this->strp(strp); @@ -1404,12 +1455,13 @@ public: bool sameNode(const AstNode* /*samep*/) const override { return true; } }; class AstFRead final : public AstNodeExpr { - // @astgen op1 := memp : AstNode // VarRef for result - // @astgen op2 := filep : AstNode // file (must be a VarRef) - // @astgen op3 := startp : Optional[AstNode] // Offset - // @astgen op4 := countp : Optional[AstNode] // Size + // @astgen op1 := memp : AstNodeExpr // VarRef for result + // @astgen op2 := filep : AstNodeExpr // file (must be a VarRef) + // @astgen op3 := startp : Optional[AstNodeExpr] // Offset + // @astgen op4 := countp : Optional[AstNodeExpr] // Size public: - AstFRead(FileLine* fl, AstNode* memp, AstNode* filep, AstNode* startp, AstNode* countp) + AstFRead(FileLine* fl, AstNodeExpr* memp, AstNodeExpr* filep, AstNodeExpr* startp, + AstNodeExpr* countp) : ASTGEN_SUPER_FRead(fl) { this->memp(memp); this->filep(filep); @@ -1429,9 +1481,9 @@ public: bool isSystemFunc() const override { return true; } }; class AstFRewind final : public AstNodeExpr { - // @astgen op1 := filep : Optional[AstNode] + // @astgen op1 := filep : Optional[AstNodeExpr] public: - AstFRewind(FileLine* fl, AstNode* filep) + AstFRewind(FileLine* fl, AstNodeExpr* filep) : ASTGEN_SUPER_FRewind(fl) { this->filep(filep); } @@ -1448,12 +1500,12 @@ public: bool sameNode(const AstNode* /*samep*/) const override { return true; } }; class AstFScanF final : public AstNodeExpr { - // @astgen op1 := exprsp : List[AstNode] // VarRefs for results - // @astgen op2 := filep : Optional[AstNode] // file (must be a VarRef) + // @astgen op1 := exprsp : List[AstNodeExpr] // VarRefs for results + // @astgen op2 := filep : Optional[AstNodeExpr] // file (must be a VarRef) string m_text; public: - AstFScanF(FileLine* fl, const string& text, AstNode* filep, AstNode* exprsp) + AstFScanF(FileLine* fl, const string& text, AstNodeExpr* filep, AstNodeExpr* exprsp) : ASTGEN_SUPER_FScanF(fl) , m_text{text} { addExprsp(exprsp); @@ -1477,11 +1529,11 @@ public: bool isSystemFunc() const override { return true; } }; class AstFSeek final : public AstNodeExpr { - // @astgen op1 := filep : AstNode // file (must be a VarRef) - // @astgen op2 := offset : Optional[AstNode] - // @astgen op3 := operation : Optional[AstNode] + // @astgen op1 := filep : AstNodeExpr // file (must be a VarRef) + // @astgen op2 := offset : Optional[AstNodeExpr] + // @astgen op3 := operation : Optional[AstNodeExpr] public: - AstFSeek(FileLine* fl, AstNode* filep, AstNode* offset, AstNode* operation) + AstFSeek(FileLine* fl, AstNodeExpr* filep, AstNodeExpr* offset, AstNodeExpr* operation) : ASTGEN_SUPER_FSeek(fl) { this->filep(filep); this->offset(offset); @@ -1500,9 +1552,9 @@ public: bool isSystemFunc() const override { return true; } }; class AstFTell final : public AstNodeExpr { - // @astgen op1 := filep : AstNode // file (must be a VarRef) + // @astgen op1 := filep : AstNodeExpr // file (must be a VarRef) public: - AstFTell(FileLine* fl, AstNode* filep) + AstFTell(FileLine* fl, AstNodeExpr* filep) : ASTGEN_SUPER_FTell(fl) { this->filep(filep); } @@ -1589,6 +1641,24 @@ public: string emitC() override { V3ERROR_NA_RETURN(""); } bool cleanOut() const override { return true; } }; +class AstGetInitialRandomSeed final : public AstNodeExpr { + // Verilog $get_initial_random_seed() +public: + explicit AstGetInitialRandomSeed(FileLine* fl) + : ASTGEN_SUPER_GetInitialRandomSeed(fl) { + dtypeSetSigned32(); + } + ASTGEN_MEMBERS_AstGetInitialRandomSeed; + string emitVerilog() override { return "$get_initial_random_seed()"; } + string emitC() final override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { return true; } + bool isGateOptimizable() const override { return false; } + bool isPredictOptimizable() const override { return true; } + bool isPure() override { return true; } + bool isSystemFunc() const override { return true; } + int instrCount() const override { return INSTR_COUNT_PLI; } + bool sameNode(const AstNode* /*samep*/) const override { return true; } +}; class AstImplication final : public AstNodeExpr { // Verilog Implication Operator // Nonoverlapped "|=>" @@ -1625,7 +1695,7 @@ class AstInitArray final : public AstNodeExpr { // Key values are C++ array style, with lo() at index 0 // Parents: ASTVAR::init() // @astgen op1 := defaultp : Optional[AstNodeExpr] // Default, if sparse - // @astgen op2 := initsp : List[AstNode] // Initial value expressions + // @astgen op2 := initsp : List[AstInitItem] // Initial value expressions // public: using KeyItemMap = std::map; @@ -1714,6 +1784,22 @@ public: bool index() const { return m_index; } bool isExprCoverageEligible() const override { return false; } }; +class AstMatches final : public AstNodeExpr { + // "matches" operator: "expr matches pattern" + // @astgen op1 := lhsp : AstNodeExpr // Expression to match + // @astgen op2 := patternp : AstNode // Pattern to match against +public: + AstMatches(FileLine* fl, AstNodeExpr* lhsp, AstNode* patternp) + : ASTGEN_SUPER_Matches(fl) { + this->lhsp(lhsp); + this->patternp(patternp); + } + ASTGEN_MEMBERS_AstMatches; + string emitVerilog() override { return "%l matches %r"; } + string emitC() override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { return false; } + bool sameNode(const AstNode* /*samep*/) const override { return true; } +}; class AstMemberSel final : public AstNodeExpr { // @astgen op1 := fromp : AstNodeExpr // @@ -1808,13 +1894,13 @@ class AstParseRef final : public AstNodeExpr { // A reference to a variable, function or task // We don't know which at parse time due to bison constraints // The link stages will replace this with AstVarRef, or AstTaskRef, etc. - // @astgen op1 := lhsp : Optional[AstNode] + // @astgen op1 := lhsp : Optional[AstNodeExpr] // @astgen op2 := ftaskrefp : Optional[AstNodeFTaskRef] string m_name; public: - AstParseRef(FileLine* fl, const string& name, AstNode* lhsp = nullptr, + AstParseRef(FileLine* fl, const string& name, AstNodeExpr* lhsp = nullptr, AstNodeFTaskRef* ftaskrefp = nullptr) : ASTGEN_SUPER_ParseRef(fl) , m_name{name} { @@ -1836,10 +1922,10 @@ public: class AstPast final : public AstNodeExpr { // Verilog $past // @astgen op1 := exprp : AstNodeExpr - // @astgen op2 := ticksp : Optional[AstNode] + // @astgen op2 := ticksp : Optional[AstNodeExpr] // @astgen op3 := sentreep : Optional[AstSenTree] public: - AstPast(FileLine* fl, AstNodeExpr* exprp, AstNode* ticksp = nullptr, + AstPast(FileLine* fl, AstNodeExpr* exprp, AstNodeExpr* ticksp = nullptr, AstSenTree* sentreep = nullptr) : ASTGEN_SUPER_Past(fl) { this->exprp(exprp); @@ -1907,14 +1993,41 @@ public: AstNodeDType* getChildDTypep() const override { return childDTypep(); } AstNodeDType* subDTypep() const VL_MT_STABLE { return dtypep() ? dtypep() : childDTypep(); } }; +class AstPatternStar final : public AstNodeExpr { + // Pattern wildcard: ".*" +public: + explicit AstPatternStar(FileLine* fl) + : ASTGEN_SUPER_PatternStar(fl) {} + ASTGEN_MEMBERS_AstPatternStar; + string emitVerilog() override { return ".*"; } + string emitC() override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { return false; } + bool sameNode(const AstNode* /*samep*/) const override { return true; } +}; +class AstPatternVar final : public AstNodeExpr { + // Pattern variable binding: ".variable" + string m_name; // Variable name +public: + AstPatternVar(FileLine* fl, const string& name) + : ASTGEN_SUPER_PatternVar(fl) + , m_name{name} {} + ASTGEN_MEMBERS_AstPatternVar; + string emitVerilog() override { return ".%k"; } + string emitC() override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { return false; } + bool sameNode(const AstNode* samep) const override { + return m_name == VN_DBG_AS(samep, PatternVar)->m_name; + } + string name() const override VL_MT_STABLE { return m_name; } +}; class AstRand final : public AstNodeExpr { // $random/$random(seed) or $urandom/$urandom(seed) // Return a random number, based upon width() - // @astgen op1 := seedp : Optional[AstNode] + // @astgen op1 := seedp : Optional[AstNodeExpr] const bool m_urandom; // $urandom vs $random public: class Reset {}; - AstRand(FileLine* fl, AstNode* seedp, bool urandom) + AstRand(FileLine* fl, AstNodeExpr* seedp, bool urandom) : ASTGEN_SUPER_Rand(fl) , m_urandom{urandom} { this->seedp(seedp); @@ -2095,13 +2208,13 @@ public: bool isSystemFunc() const override { return true; } }; class AstSScanF final : public AstNodeExpr { - // @astgen op1 := exprsp : List[AstNode] // VarRefs for results - // @astgen op2 := fromp : AstNode + // @astgen op1 := exprsp : List[AstNodeExpr] // VarRefs for results + // @astgen op2 := fromp : AstNodeExpr string m_text; VTimescale m_timeunit; // Parent module time unit public: - AstSScanF(FileLine* fl, const string& text, AstNode* fromp, AstNode* exprsp) + AstSScanF(FileLine* fl, const string& text, AstNodeExpr* fromp, AstNodeExpr* exprsp) : ASTGEN_SUPER_SScanF(fl) , m_text{text} { addExprsp(exprsp); @@ -2128,7 +2241,7 @@ public: }; class AstSampled final : public AstNodeExpr { // Verilog $sampled - // @astgen op1 := exprp : AstNode // AstNodeExpr or AstPropSpec + // @astgen op1 := exprp : AstNode public: AstSampled(FileLine* fl, AstNode* exprp) : ASTGEN_SUPER_Sampled(fl) { @@ -2190,34 +2303,13 @@ public: // Name for __Vscopep variable including children string scopePrettyDpiName() const { return scopePrettyNameFormatter(m_scopeEntr); } }; -class AstSelLoopVars final : public AstNodeExpr { - // Parser only concept "[id, id, id]" for a foreach statement - // Unlike normal selects elements is a list - // TODO: Should not be an AstNodeExpr, model foreach better - // @astgen op1 := fromp : AstNodeExpr - // @astgen op2 := elementsp : List[AstNode] -public: - AstSelLoopVars(FileLine* fl, AstNodeExpr* fromp, AstNode* elementsp) - : ASTGEN_SUPER_SelLoopVars(fl) { - this->fromp(fromp); - addElementsp(elementsp); - } - ASTGEN_MEMBERS_AstSelLoopVars; - bool sameNode(const AstNode* /*samep*/) const override { return true; } - bool maybePointedTo() const override VL_MT_SAFE { return false; } - - string emitVerilog() override { V3ERROR_NA_RETURN(""); } - string emitC() override { V3ERROR_NA_RETURN(""); } - bool cleanOut() const override { V3ERROR_NA_RETURN(true); } - bool hasDType() const override VL_MT_SAFE { return false; } -}; class AstSetAssoc final : public AstNodeExpr { // Set an assoc array element and return object, '{} - // @astgen op1 := lhsp : AstNode + // @astgen op1 := lhsp : AstNodeExpr // @astgen op2 := keyp : Optional[AstNode] // @astgen op3 := valuep : AstNodeExpr public: - AstSetAssoc(FileLine* fl, AstNode* lhsp, AstNode* keyp, AstNodeExpr* valuep) + AstSetAssoc(FileLine* fl, AstNodeExpr* lhsp, AstNode* keyp, AstNodeExpr* valuep) : ASTGEN_SUPER_SetAssoc(fl) { this->lhsp(lhsp); this->keyp(keyp); @@ -2233,11 +2325,11 @@ public: }; class AstSetWildcard final : public AstNodeExpr { // Set a wildcard assoc array element and return object, '{} - // @astgen op1 := lhsp : AstNode + // @astgen op1 := lhsp : AstNodeExpr // @astgen op2 := keyp : Optional[AstNode] // @astgen op3 := valuep : AstNodeExpr public: - AstSetWildcard(FileLine* fl, AstNode* lhsp, AstNode* keyp, AstNodeExpr* valuep) + AstSetWildcard(FileLine* fl, AstNodeExpr* lhsp, AstNode* keyp, AstNodeExpr* valuep) : ASTGEN_SUPER_SetWildcard(fl) { this->lhsp(lhsp); this->keyp(keyp); @@ -2335,9 +2427,9 @@ public: int instrCount() const override { return widthInstrs(); } }; class AstSysIgnore final : public AstNodeExpr { - // @astgen op1 := exprsp : List[AstNode] // Expressions to output (???) + // @astgen op1 := exprsp : List[AstNodeExpr] // Expressions to output (???) public: - AstSysIgnore(FileLine* fl, AstNode* exprsp) + AstSysIgnore(FileLine* fl, AstNodeExpr* exprsp) : ASTGEN_SUPER_SysIgnore(fl) { addExprsp(exprsp); } @@ -2355,9 +2447,9 @@ public: }; class AstSystemF final : public AstNodeExpr { // $system used as function - // @astgen op1 := lhsp : AstNode + // @astgen op1 := lhsp : AstNodeExpr public: - AstSystemF(FileLine* fl, AstNode* lhsp) + AstSystemF(FileLine* fl, AstNodeExpr* lhsp) : ASTGEN_SUPER_SystemF(fl) { this->lhsp(lhsp); } @@ -2374,11 +2466,49 @@ public: bool sameNode(const AstNode* /*samep*/) const override { return true; } bool isSystemFunc() const override { return true; } }; +class AstTaggedExpr final : public AstNodeExpr { + // Tagged union expression: "tagged MemberName [expr]" + // @astgen op1 := exprp : Optional[AstNodeExpr] // Optional value expression + string m_name; // Member identifier name +public: + AstTaggedExpr(FileLine* fl, const string& name, AstNodeExpr* exprp) + : ASTGEN_SUPER_TaggedExpr(fl) + , m_name{name} { + this->exprp(exprp); + } + ASTGEN_MEMBERS_AstTaggedExpr; + string emitVerilog() override { return "tagged %k"; } + string emitC() override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { return false; } + bool sameNode(const AstNode* samep) const override { + return m_name == VN_DBG_AS(samep, TaggedExpr)->m_name; + } + string name() const override VL_MT_STABLE { return m_name; } +}; +class AstTaggedPattern final : public AstNodeExpr { + // Tagged pattern for matches: "tagged MemberName [pattern]" + // @astgen op1 := patternp : Optional[AstNode] // Optional nested pattern + string m_name; // Member identifier name +public: + AstTaggedPattern(FileLine* fl, const string& name, AstNode* patternp) + : ASTGEN_SUPER_TaggedPattern(fl) + , m_name{name} { + this->patternp(patternp); + } + ASTGEN_MEMBERS_AstTaggedPattern; + string emitVerilog() override { return "tagged %k"; } + string emitC() override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const override { return false; } + bool sameNode(const AstNode* samep) const override { + return m_name == VN_DBG_AS(samep, TaggedPattern)->m_name; + } + string name() const override VL_MT_STABLE { return m_name; } +}; class AstTestPlusArgs final : public AstNodeExpr { // Search expression. If nullptr then this is a $test$plusargs instead of $value$plusargs. - // @astgen op1 := searchp : Optional[AstNode] + // @astgen op1 := searchp : Optional[AstNodeExpr] public: - AstTestPlusArgs(FileLine* fl, AstNode* searchp) + AstTestPlusArgs(FileLine* fl, AstNodeExpr* searchp) : ASTGEN_SUPER_TestPlusArgs(fl) { this->searchp(searchp); } @@ -2481,10 +2611,10 @@ public: }; class AstValuePlusArgs final : public AstNodeExpr { // Search expression. If nullptr then this is a $test$plusargs instead of $value$plusargs. - // @astgen op1 := searchp : Optional[AstNode] - // @astgen op2 := outp : AstNode // VarRef for result + // @astgen op1 := searchp : Optional[AstNodeExpr] + // @astgen op2 := outp : AstNodeExpr // VarRef for result public: - AstValuePlusArgs(FileLine* fl, AstNode* searchp, AstNode* outp) + AstValuePlusArgs(FileLine* fl, AstNodeExpr* searchp, AstNodeExpr* outp) : ASTGEN_SUPER_ValuePlusArgs(fl) { this->searchp(searchp); this->outp(outp); @@ -2500,47 +2630,16 @@ public: bool cleanOut() const override { return true; } bool sameNode(const AstNode* /*samep*/) const override { return true; } }; -class AstWith final : public AstNodeExpr { - // Used as argument to method, then to AstCMethodHard - // dtypep() contains the with lambda's return dtype - // Parents: funcref (similar to AstArg) - // Children: LambdaArgRef that declares the item variable - // Children: LambdaArgRef that declares the item.index variable - // Children: expression (equation establishing the with) - // @astgen op1 := indexArgRefp : AstLambdaArgRef - // @astgen op2 := valueArgRefp : AstLambdaArgRef - // @astgen op3 := exprp : List[AstNode] // Pins, expression and constraints - // TODO: Separate expression and constraints -public: - AstWith(FileLine* fl, AstLambdaArgRef* indexArgRefp, AstLambdaArgRef* valueArgRefp, - AstNode* exprp) - : ASTGEN_SUPER_With(fl) { - this->indexArgRefp(indexArgRefp); - this->valueArgRefp(valueArgRefp); - addExprp(exprp); - } - ASTGEN_MEMBERS_AstWith; - bool sameNode(const AstNode* /*samep*/) const override { return true; } - const char* broken() const override { - BROKEN_RTN(!indexArgRefp()); // varp needed to know lambda's arg dtype - BROKEN_RTN(!valueArgRefp()); // varp needed to know lambda's arg dtype - return nullptr; - } - - string emitVerilog() override { V3ERROR_NA_RETURN(""); } - string emitC() override { V3ERROR_NA_RETURN(""); } - bool cleanOut() const override { V3ERROR_NA_RETURN(true); } -}; class AstWithParse final : public AstNodeExpr { // In early parse, FUNC(index) WITH equation-using-index // Replaced with AstWith // Parents: expr|stmt // Children: funcref, expr // @astgen op1 := funcrefp : AstNodeExpr - // @astgen op3 := exprsp : List[AstNode] // With's parenthesis part + // @astgen op3 := exprsp : List[AstNodeExpr] // With's parenthesis part // @astgen op4 := constraintsp : List[AstNode] // With's braces part public: - AstWithParse(FileLine* fl, AstNodeExpr* funcrefp, AstNode* exprsp, + AstWithParse(FileLine* fl, AstNodeExpr* funcrefp, AstNodeExpr* exprsp, AstNode* constraintsp = nullptr) : ASTGEN_SUPER_WithParse(fl) { this->funcrefp(funcrefp); @@ -2764,6 +2863,8 @@ public: bool sizeMattersRhs() const override { return false; } }; class AstFGetS final : public AstNodeBiop { + // @astgen alias op1 := strgp + // @astgen alias op2 := filep public: AstFGetS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp) : ASTGEN_SUPER_FGetS(fl, lhsp, rhsp) {} @@ -2781,8 +2882,6 @@ public: bool sizeMattersRhs() const override { return false; } bool isSystemFunc() const override { return true; } int instrCount() const override { return widthInstrs() * 64; } - AstNode* strgp() const { return lhsp(); } - AstNode* filep() const { return rhsp(); } }; class AstFUngetC final : public AstNodeBiop { public: @@ -3580,7 +3679,7 @@ public: string emitSimpleOperator() override { return (rhsp()->isWide() || rhsp()->isQuad()) ? "" : ">>"; } - bool cleanOut() const override { return false; } + bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } bool cleanRhs() const override { return true; } // LHS size might be > output size, so don't want to force size @@ -3602,7 +3701,7 @@ public: string emitVerilog() override { return "%k(%l %f>> %r)"; } string emitC() override { return "VL_SHIFTR_%nq%lq%rq(%nw,%lw,%rw, %P, %li, %ri)"; } string emitSimpleOperator() override { return ""; } - bool cleanOut() const override { return false; } + bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } bool cleanRhs() const override { return true; } // LHS size might be > output size, so don't want to force size @@ -4064,6 +4163,7 @@ public: } string emitVerilog() override { return "%k(%l %f* %r)"; } string emitC() override { return "VL_MULS_%nq%lq%rq(%lw, %P, %li, %ri)"; } + string emitSMT() const override { return "(bvmul %l %r)"; } string emitSimpleOperator() override { return ""; } bool emitCheckMaxWords() override { return true; } bool cleanOut() const override { return false; } @@ -4172,7 +4272,7 @@ public: ASTGEN_MEMBERS_AstArraySel; void numberOperate(V3Number&, const V3Number&, const V3Number&) override { V3ERROR_NA; } string emitVerilog() override { return "%k(%l%f[%r])"; } - string emitC() override { return "%li%k[%ri]"; } + string emitC() override { V3ERROR_NA_RETURN(""); } // Special cased string emitSMT() const override { return "(select %l %r)"; } bool cleanOut() const override { return true; } bool cleanLhs() const override { return false; } @@ -4253,9 +4353,7 @@ public: ASTGEN_MEMBERS_AstWordSel; void numberOperate(V3Number&, const V3Number&, const V3Number&) override { V3ERROR_NA; } string emitVerilog() override { return "%k(%l%f[%r])"; } - string emitC() override { - return "%li[%ri]"; - } // Not %k, as usually it's a small constant rhsp + string emitC() override { V3ERROR_NA_RETURN(""); } // Special cased bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } bool cleanRhs() const override { return true; } @@ -4369,9 +4467,9 @@ class AstFuncRef final : public AstNodeFTaskRef { // A reference to a function bool m_superReference = false; // Called with super reference public: - inline AstFuncRef(FileLine* fl, AstFunc* taskp, AstNodeExpr* pinsp); - AstFuncRef(FileLine* fl, const string& name, AstNodeExpr* pinsp) - : ASTGEN_SUPER_FuncRef(fl, name, pinsp) {} + inline AstFuncRef(FileLine* fl, AstFunc* taskp, AstArg* argsp = nullptr); + AstFuncRef(FileLine* fl, const string& name, AstArg* argsp = nullptr) + : ASTGEN_SUPER_FuncRef(fl, name, argsp) {} ASTGEN_MEMBERS_AstFuncRef; bool superReference() const { return m_superReference; } void superReference(bool flag) { m_superReference = flag; } @@ -4379,17 +4477,17 @@ public: class AstMethodCall final : public AstNodeFTaskRef { // A reference to a member task (or function) // Don't need the class we are extracting from, as the "fromp()"'s datatype can get us to it - // @astgen op2 := fromp : AstNodeExpr + // @astgen op1 := fromp : AstNodeExpr // public: AstMethodCall(FileLine* fl, AstNodeExpr* fromp, VFlagChildDType, const string& name, - AstNodeExpr* pinsp) - : ASTGEN_SUPER_MethodCall(fl, name, pinsp) { + AstArg* argsp = nullptr) + : ASTGEN_SUPER_MethodCall(fl, name, argsp) { this->fromp(fromp); dtypep(nullptr); // V3Width will resolve } - AstMethodCall(FileLine* fl, AstNodeExpr* fromp, const string& name, AstNodeExpr* pinsp) - : ASTGEN_SUPER_MethodCall(fl, name, pinsp) { + AstMethodCall(FileLine* fl, AstNodeExpr* fromp, const string& name, AstArg* argsp = nullptr) + : ASTGEN_SUPER_MethodCall(fl, name, argsp) { this->fromp(fromp); } ASTGEN_MEMBERS_AstMethodCall; @@ -4400,8 +4498,8 @@ class AstNew final : public AstNodeFTaskRef { bool m_isImplicit = false; // Implicitly generated from extends args bool m_isScoped = false; // Had :: scope when parsed public: - AstNew(FileLine* fl, AstNodeExpr* pinsp, bool isScoped = false) - : ASTGEN_SUPER_New(fl, "new", pinsp) + AstNew(FileLine* fl, AstArg* argsp = nullptr, bool isScoped = false) + : ASTGEN_SUPER_New(fl, "new", argsp) , m_isScoped{isScoped} {} ASTGEN_MEMBERS_AstNew; void dump(std::ostream& str = std::cout) const override; @@ -4418,9 +4516,9 @@ class AstTaskRef final : public AstNodeFTaskRef { // A reference to a task bool m_superReference = false; // Called with super reference public: - inline AstTaskRef(FileLine* fl, AstTask* taskp, AstNodeExpr* pinsp); - AstTaskRef(FileLine* fl, const string& name, AstNodeExpr* pinsp) - : ASTGEN_SUPER_TaskRef(fl, name, pinsp) { + inline AstTaskRef(FileLine* fl, AstTask* taskp, AstArg* argsp = nullptr); + AstTaskRef(FileLine* fl, const string& name, AstArg* argsp = nullptr) + : ASTGEN_SUPER_TaskRef(fl, name, argsp) { dtypeSetVoid(); } ASTGEN_MEMBERS_AstTaskRef; @@ -4852,28 +4950,6 @@ public: int instrCount() const override { return INSTR_COUNT_DBL; } bool isSystemFunc() const override { return true; } }; -class AstCAwait final : public AstNodeUniop { - // Emit C++'s co_await expression - // @astgen alias op1 := exprp - // - // @astgen ptr := m_sentreep : Optional[AstSenTree] // Sentree related to this await -public: - AstCAwait(FileLine* fl, AstNodeExpr* exprp, AstSenTree* sentreep = nullptr) - : ASTGEN_SUPER_CAwait(fl, exprp) - , m_sentreep{sentreep} {} - ASTGEN_MEMBERS_AstCAwait; - bool isTimingControl() const override { return true; } - void dump(std::ostream& str) const override; - void dumpJson(std::ostream& str) const override; - AstSenTree* sentreep() const { return m_sentreep; } - void clearSentreep() { m_sentreep = nullptr; } - void numberOperate(V3Number& out, const V3Number& lhs) override { V3ERROR_NA; } - string emitVerilog() override { V3ERROR_NA_RETURN(""); } - string emitC() override { V3ERROR_NA_RETURN(""); } - bool cleanOut() const override { return true; } - bool cleanLhs() const override { return true; } - bool sizeMattersLhs() const override { return false; } -}; class AstCCast final : public AstNodeUniop { // Cast to C-based data type int m_size; @@ -5450,7 +5526,9 @@ public: ASTGEN_MEMBERS_AstToStringN; void numberOperate(V3Number& out, const V3Number& lhs) override { V3ERROR_NA; } string emitVerilog() override { return "$sformatf(\"%p\", %l)"; } - string emitC() override { return isWide() ? "VL_TO_STRING_W(%nw, %li)" : "VL_TO_STRING(%li)"; } + string emitC() override { + return isWide() ? "VL_TO_STRING_W(%nw, %li)" : "VL_TO_STRING_DEREF(%li)"; + } bool cleanOut() const override { return true; } bool cleanLhs() const override { return true; } bool sizeMattersLhs() const override { return false; } diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 093a7bdba..4c3558ba8 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -285,6 +285,7 @@ class AstNodeModule VL_NOT_FINAL : public AstNode { bool m_internal : 1; // Internally created bool m_recursive : 1; // Recursive module bool m_recursiveClone : 1; // If recursive, what module it clones, otherwise nullptr + bool m_verilatorLib : 1; // Module is a stub for a Verilator produced --lib-create protected: AstNodeModule(VNType t, FileLine* fl, const string& name, const string& libname) : AstNode{t, fl} @@ -301,7 +302,8 @@ protected: , m_hierParams{false} , m_internal{false} , m_recursive{false} - , m_recursiveClone{false} {} + , m_recursiveClone{false} + , m_verilatorLib{false} {} public: ASTGEN_MEMBERS_AstNodeModule; @@ -343,6 +345,8 @@ public: void recursive(bool flag) { m_recursive = flag; } void recursiveClone(bool flag) { m_recursiveClone = flag; } bool recursiveClone() const { return m_recursiveClone; } + void verilatorLib(bool flag) { m_verilatorLib = flag; } + bool verilatorLib() const { return m_verilatorLib; } VLifetime lifetime() const { return m_lifetime; } void lifetime(const VLifetime& flag) { m_lifetime = flag; } VTimescale timeunit() const { return m_timeunit; } @@ -494,6 +498,8 @@ class AstCFunc final : public AstNode { bool m_dpiImportWrapper : 1; // Wrapper for invoking DPI import prototype from generated code bool m_needProcess : 1; // Needs access to VlProcess of the caller bool m_recursive : 1; // Recursive or part of recursion + bool m_noLife : 1; // Disable V3Life on this function - has multiple calls, and reads Syms + // state int m_cost; // Function call cost public: AstCFunc(FileLine* fl, const string& name, AstScope* scopep, const string& rtnType = "") @@ -523,6 +529,7 @@ public: m_dpiImportPrototype = false; m_dpiImportWrapper = false; m_recursive = false; + m_noLife = false; m_cost = v3Global.opt.instrCountDpi(); // As proxy for unknown general DPI cost } ASTGEN_MEMBERS_AstCFunc; @@ -596,6 +603,8 @@ public: bool isCoroutine() const { return m_rtnType == "VlCoroutine"; } void recursive(bool flag) { m_recursive = flag; } bool recursive() const { return m_recursive; } + void noLife(bool flag) { m_noLife = flag; } + bool noLife() const { return m_noLife; } void cost(int cost) { m_cost = cost; } // Special methods bool emptyBody() const { @@ -759,7 +768,7 @@ class AstClassExtends final : public AstNode { // during early parse, then moves to dtype // @astgen op1 := childDTypep : Optional[AstNodeDType] // @astgen op2 := classOrPkgsp : Optional[AstNode] - // @astgen op3 := argsp : List[AstNodeExpr] + // @astgen op3 := argsp : List[AstArg] const bool m_isImplements; // class implements bool m_parameterized = false; // has parameters in its statement @@ -1247,9 +1256,11 @@ class AstNetlist final : public AstNode { // @astgen ptr := m_nbaEventp : Optional[AstVarScope] // NBA event variable // @astgen ptr := m_nbaEventTriggerp : Optional[AstVarScope] // NBA event trigger // @astgen ptr := m_topScopep : Optional[AstTopScope] // Singleton AstTopScope + // @astgen ptr := m_stlFirstIterationp: Optional[AstVarScope] // Settle first iteration flag VTimescale m_timeunit; // Global time unit VTimescale m_timeprecision; // Global time precision bool m_timescaleSpecified = false; // Input HDL specified timescale + uint32_t m_nTraceCodes = 0; // Number of trace codes used by design public: AstNetlist(); ASTGEN_MEMBERS_AstNetlist; @@ -1291,6 +1302,10 @@ public: void timeprecisionMerge(FileLine*, const VTimescale& value); void timescaleSpecified(bool specified) { m_timescaleSpecified = specified; } bool timescaleSpecified() const { return m_timescaleSpecified; } + uint32_t nTraceCodes() const { return m_nTraceCodes; } + void nTraceCodes(uint32_t value) { m_nTraceCodes = value; } + AstVarScope* stlFirstIterationp(); + void clearStlFirstIterationp() { m_stlFirstIterationp = nullptr; } }; class AstPackageExport final : public AstNode { // A package export declaration @@ -1899,6 +1914,7 @@ class AstVar final : public AstNode { bool m_isConst : 1; // Table contains constant data bool m_isContinuously : 1; // Ever assigned continuously (for force/release) bool m_hasStrengthAssignment : 1; // Is on LHS of assignment with strength specifier + bool m_hasUserInit : 1; // Has initial assignment by user at parse time bool m_isStatic : 1; // Static C variable (for Verilog see instead lifetime()) bool m_isPulldown : 1; // Tri0 bool m_isPullup : 1; // Tri1 @@ -1908,6 +1924,7 @@ class AstVar final : public AstNode { bool m_isDpiOpenArray : 1; // DPI import open array bool m_isHideLocal : 1; // Verilog local bool m_isHideProtected : 1; // Verilog protected + bool m_noCReset : 1; // Do not do automated CReset creation bool m_noReset : 1; // Do not do automated reset/randomization bool m_noSubst : 1; // Do not substitute out references bool m_substConstOnly : 1; // Only substitute if constant @@ -1951,6 +1968,7 @@ class AstVar final : public AstNode { m_isConst = false; m_isContinuously = false; m_hasStrengthAssignment = false; + m_hasUserInit = false; m_isStatic = false; m_isPulldown = false; m_isPullup = false; @@ -1960,6 +1978,7 @@ class AstVar final : public AstNode { m_isDpiOpenArray = false; m_isHideLocal = false; m_isHideProtected = false; + m_noCReset = false; m_noReset = false; m_noSubst = false; m_substConstOnly = false; @@ -2105,24 +2124,28 @@ public: if (flag) m_funcLocalSticky = true; } void funcReturn(bool flag) { m_funcReturn = flag; } + bool gotNansiType() const { return m_gotNansiType; } void gotNansiType(bool flag) { m_gotNansiType = flag; } - bool gotNansiType() { return m_gotNansiType; } + bool hasStrengthAssignment() const { return m_hasStrengthAssignment; } void hasStrengthAssignment(bool flag) { m_hasStrengthAssignment = flag; } - bool hasStrengthAssignment() { return m_hasStrengthAssignment; } - void isDpiOpenArray(bool flag) { m_isDpiOpenArray = flag; } + bool hasUserInit() const { return m_hasUserInit; } + void hasUserInit(bool flag) { m_hasUserInit = flag; } bool isDpiOpenArray() const VL_MT_SAFE { return m_isDpiOpenArray; } + void isDpiOpenArray(bool flag) { m_isDpiOpenArray = flag; } bool isHideLocal() const { return m_isHideLocal; } void isHideLocal(bool flag) { m_isHideLocal = flag; } bool isHideProtected() const { return m_isHideProtected; } void isHideProtected(bool flag) { m_isHideProtected = flag; } - void noReset(bool flag) { m_noReset = flag; } + bool noCReset() const { return m_noCReset; } + void noCReset(bool flag) { m_noCReset = flag; } bool noReset() const { return m_noReset; } - void noSubst(bool flag) { m_noSubst = flag; } + void noReset(bool flag) { m_noReset = flag; } bool noSubst() const { return m_noSubst; } - void substConstOnly(bool flag) { m_substConstOnly = flag; } + void noSubst(bool flag) { m_noSubst = flag; } bool substConstOnly() const { return m_substConstOnly; } - void overriddenParam(bool flag) { m_overridenParam = flag; } + void substConstOnly(bool flag) { m_substConstOnly = flag; } bool overriddenParam() const { return m_overridenParam; } + void overriddenParam(bool flag) { m_overridenParam = flag; } void trace(bool flag) { m_trace = flag; } void isLatched(bool flag) { m_isLatched = flag; } bool isForceable() const { return m_isForceable; } @@ -2261,7 +2284,7 @@ public: } bool needsCReset() const { return !isIfaceParent() && !isIfaceRef() && !noReset() && !isParam() && !isStatementTemp() - && !(basicp() && basicp()->isEvent()); + && !noCReset() && !(basicp() && basicp()->isEvent()); } static AstVar* scVarRecurse(AstNode* nodep); }; diff --git a/src/V3AstNodeStmt.h b/src/V3AstNodeStmt.h index 9d4d21c37..3b9b7da94 100644 --- a/src/V3AstNodeStmt.h +++ b/src/V3AstNodeStmt.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -126,13 +126,13 @@ public: } }; class AstNodeForeach VL_NOT_FINAL : public AstNodeStmt { - // @astgen op1 := arrayp : AstNode - // @astgen op2 := stmtsp : List[AstNode] + // @astgen op1 := headerp : AstForeachHeader + // @astgen op2 := bodyp : List[AstNode] public: - AstNodeForeach(VNType t, FileLine* fl, AstNode* arrayp, AstNode* stmtsp) + AstNodeForeach(VNType t, FileLine* fl, AstForeachHeader* headerp, AstNode* bodyp) : AstNodeStmt(t, fl) { - this->arrayp(arrayp); - addStmtsp(stmtsp); + this->headerp(headerp); + addBodyp(bodyp); } ASTGEN_MEMBERS_AstNodeForeach; bool isGateOptimizable() const override { return false; } @@ -213,6 +213,23 @@ public: bool isDefault() const { return condsp() == nullptr; } }; +class AstForeachHeader final : public AstNode { + // Variable reference + index enumeration "ref [id, id, id]" for a foreach statement + // @astgen op1 := fromp : AstNodeExpr + // @astgen op2 := elementsp : List[AstNode] + // AstNodeExpr/AstEmpty during parsing (only AstParseRef/AstEmpty is well formed) + // then AstVar/AstEmpty after LinkDot +public: + AstForeachHeader(FileLine* fl, AstNodeExpr* fromp, AstNode* elementsp) + : ASTGEN_SUPER_ForeachHeader(fl) { + this->fromp(fromp); + addElementsp(elementsp); + } + ASTGEN_MEMBERS_AstForeachHeader; + bool sameNode(const AstNode* /*samep*/) const override { return true; } + bool maybePointedTo() const override VL_MT_SAFE { return false; } +}; + // === AstNodeStmt === class AstAssertCtl final : public AstNodeStmt { // @astgen op1 := controlTypep : AstNodeExpr @@ -253,25 +270,25 @@ public: string verilogKwd() const override { return "break"; } bool isBrancher() const override { V3ERROR_NA_RETURN(true); } // Node removed early }; -class AstCReset final : public AstNodeStmt { - // Reset variable at startup - // @astgen op1 := varrefp : AstVarRef - const bool m_constructing; // Previously cleared by constructor +class AstCAwait final : public AstNodeStmt { + // C++'s co_await. While this is an expression in C++, in Verilator it is only used + // with void result types and always appears in statement position. There must never + // be a suspendable process that returns a value, so modeling as a statement instead. + // @astgen op1 := exprp : AstNodeExpr + // + // @astgen ptr := m_sentreep : Optional[AstSenTree] // Sentree related to this await public: - AstCReset(FileLine* fl, AstVarRef* varrefp, bool constructing) - : ASTGEN_SUPER_CReset(fl) - , m_constructing{constructing} { - this->varrefp(varrefp); + AstCAwait(FileLine* fl, AstNodeExpr* exprp, AstSenTree* sentreep = nullptr) + : ASTGEN_SUPER_CAwait(fl) + , m_sentreep{sentreep} { + this->exprp(exprp); } - ASTGEN_MEMBERS_AstCReset; + ASTGEN_MEMBERS_AstCAwait; void dump(std::ostream& str) const override; void dumpJson(std::ostream& str) const override; - bool isGateOptimizable() const override { return false; } - bool isPredictOptimizable() const override { return false; } - bool sameNode(const AstNode* samep) const override { - return constructing() == VN_DBG_AS(samep, CReset)->constructing(); - } - bool constructing() const { return m_constructing; } + bool isTimingControl() const override { return true; } + AstSenTree* sentreep() const { return m_sentreep; } + void clearSentreep() { m_sentreep = nullptr; } }; class AstCReturn final : public AstNodeStmt { // C++ return from a function @@ -391,8 +408,10 @@ public: bool casex() const { return m_casex == VCaseType::CT_CASEX; } bool casez() const { return m_casex == VCaseType::CT_CASEZ; } bool caseInside() const { return m_casex == VCaseType::CT_CASEINSIDE; } + bool caseMatches() const { return m_casex == VCaseType::CT_CASEMATCHES; } bool caseSimple() const { return m_casex == VCaseType::CT_CASE; } void caseInsideSet() { m_casex = VCaseType::CT_CASEINSIDE; } + void caseMatchesSet() { m_casex = VCaseType::CT_CASEMATCHES; } bool fullPragma() const { return m_fullPragma; } void fullPragma(bool flag) { m_fullPragma = flag; } bool parallelPragma() const { return m_parallelPragma; } @@ -737,6 +756,38 @@ public: ASTGEN_MEMBERS_AstFireEvent; bool isDelayed() const { return m_delayed; } }; +class AstInitialAutomaticStmt final : public AstNodeStmt { + // Automatic variable initialization in a statement position + // Used during early stages to record an initial initialization of a variable + // Moves later to an appropriate constructor, or AstInitialAutomatic, or + // AstCFunc normal statement + // Children: {statement list usually only with assignments} + // @astgen op1 := stmtsp : List[AstNode] +public: + AstInitialAutomaticStmt(FileLine* fl, AstNode* stmtsp) + : ASTGEN_SUPER_InitialAutomaticStmt(fl) { + addStmtsp(stmtsp); + } + ASTGEN_MEMBERS_AstInitialAutomaticStmt; + int instrCount() const override { return 0; } + bool isPure() override { return true; } +}; +class AstInitialStaticStmt final : public AstNodeStmt { + // Static variable initialization in a statement position + // Used during early stages to record a static initialization of a variable + // Moves later to an appropriate constructor, or AstInitialStatic, or + // AstCFunc normal statement + // Children: {statement list usually only with assignments} + // @astgen op1 := stmtsp : List[AstNode] +public: + AstInitialStaticStmt(FileLine* fl, AstNode* stmtsp) + : ASTGEN_SUPER_InitialStaticStmt(fl) { + addStmtsp(stmtsp); + } + ASTGEN_MEMBERS_AstInitialStaticStmt; + int instrCount() const override { return 0; } + bool isPure() override { return true; } +}; class AstJumpBlock final : public AstNodeStmt { // Block of code that might contain AstJumpGo statements as children, // which when exectued branch to right after the referenced AstJumpBlock. @@ -918,11 +969,11 @@ public: }; class AstRSProdItem final : public AstNodeStmt { // randomsquence production item - // @astgen op1 := argsp : List[AstNodeExpr] + // @astgen op1 := argsp : List[AstArg] // @astgen ptr := m_prodp : Optional[AstRSProd] // Pointer to production string m_name; // Name of block, or "" to use first production public: - AstRSProdItem(FileLine* fl, const string& name, AstNodeExpr* argsp) + AstRSProdItem(FileLine* fl, const string& name, AstArg* argsp) : ASTGEN_SUPER_RSProdItem(fl) , m_name{name} { addArgsp(argsp); @@ -1198,7 +1249,7 @@ class AstTraceDecl final : public AstNodeStmt { // Parents: {statement list} // Expression being traced - Moved to AstTraceInc by V3Trace // @astgen op1 := valuep : Optional[AstNodeExpr] - uint32_t m_code{0}; // Trace identifier code + uint32_t m_code{std::numeric_limits::max()}; // Trace identifier code uint32_t m_fidx{0}; // Trace function index const string m_showname; // Name of variable const VNumRange m_bitRange; // Property of var the trace details @@ -1230,6 +1281,7 @@ public: // Details on what we're tracing uint32_t code() const { return m_code; } void code(uint32_t code) { m_code = code; } + bool codeAssigned() const { return m_code != std::numeric_limits::max(); } uint32_t fidx() const { return m_fidx; } void fidx(uint32_t fidx) { m_fidx = fidx; } uint32_t codeInc() const { @@ -1332,6 +1384,20 @@ public: return new AstAssign{fileline(), lhsp, rhsp, controlp}; } }; +class AstAssignCont final : public AstNodeAssign { + // Continuous procedural 'assign'. See AstAssignW for non-procedural version. +public: + AstAssignCont(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, + AstNode* timingControlp = nullptr) + : ASTGEN_SUPER_AssignCont(fl, lhsp, rhsp, timingControlp) { + dtypeFrom(lhsp); + } + ASTGEN_MEMBERS_AstAssignCont; + AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override { + AstNode* const controlp = timingControlp() ? timingControlp()->cloneTree(false) : nullptr; + return new AstAssignCont{fileline(), lhsp, rhsp, controlp}; + } +}; class AstAssignDly final : public AstNodeAssign { public: AstAssignDly(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, @@ -1404,7 +1470,6 @@ class AstFork final : public AstNodeBlock { // be executed sequentially within each fork branch. // // @astgen op3 := forksp : List[AstBegin] - // @astgen op4 := parentProcessp : Optional[AstVarRef] const VJoinType m_joinType; // Join keyword type public: AstFork(FileLine* fl, VJoinType joinType, const string& name = "") @@ -1469,14 +1534,14 @@ public: class AstConstraintForeach final : public AstNodeForeach { // Constraint foreach statement public: - AstConstraintForeach(FileLine* fl, AstNodeExpr* exprp, AstNode* bodysp) - : ASTGEN_SUPER_ConstraintForeach(fl, exprp, bodysp) {} + AstConstraintForeach(FileLine* fl, AstForeachHeader* headerp, AstNode* bodyp) + : ASTGEN_SUPER_ConstraintForeach(fl, headerp, bodyp) {} ASTGEN_MEMBERS_AstConstraintForeach; }; class AstForeach final : public AstNodeForeach { public: - AstForeach(FileLine* fl, AstNode* arrayp, AstNode* stmtsp) - : ASTGEN_SUPER_Foreach(fl, arrayp, stmtsp) {} + AstForeach(FileLine* fl, AstForeachHeader* headerp, AstNode* stmtsp) + : ASTGEN_SUPER_Foreach(fl, headerp, stmtsp) {} ASTGEN_MEMBERS_AstForeach; }; diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index da7f5ba7f..5c14d9b47 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -56,7 +56,6 @@ void AstNode::dumpJsonPtr(std::ostream& os, const std::string& name, const AstNo // Shorthands for dumping fields that use func name as key #define dumpJsonNumFunc(os, func) dumpJsonNum(os, #func, func()) -#define dumpJsonBoolFunc(os, func) dumpJsonBool(os, #func, func()) #define dumpJsonBoolFuncIf(os, func) dumpJsonBoolIf(os, #func, func()) #define dumpJsonStrFunc(os, func) dumpJsonStr(os, #func, func()) #define dumpJsonPtrFunc(os, func) dumpJsonPtr(os, #func, func()) @@ -96,8 +95,8 @@ bool AstNodeFTaskRef::getPurityRecurse() const { // Unlinked yet, so treat as impure if (!taskp) return false; // First compute the purity of arguments - for (AstNode* pinp = this->pinsp(); pinp; pinp = pinp->nextp()) { - if (!pinp->isPure()) return false; + for (AstArg* argp = this->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { + if (!argp->isPure()) return false; } return taskp->isPure(); } @@ -348,7 +347,7 @@ const char* AstExecGraph::broken() const { BROKEN_RTN(!m_depGraphp); for (const V3GraphVertex& vtx : m_depGraphp->vertices()) { const ExecMTask* const mtaskp = vtx.as(); - AstCFunc* const funcp = mtaskp->funcp(); + const AstCFunc* const funcp = mtaskp->funcp(); BROKEN_RTN(!funcp || !funcp->brokeExists()); } return nullptr; @@ -356,6 +355,34 @@ const char* AstExecGraph::broken() const { AstNodeExpr* AstInsideRange::newAndFromInside(AstNodeExpr* exprp, AstNodeExpr* lhsp, AstNodeExpr* rhsp) { + const bool lhsUnbounded = VN_IS(lhsp, Unbounded); + const bool rhsUnbounded = VN_IS(rhsp, Unbounded); + + if (lhsUnbounded && rhsUnbounded) { + fileline()->v3warn(INSIDETRUE, + "Unbounded on both sides of inside range [$:$] is always true"); + VL_DO_DANGLING(exprp->deleteTree(), exprp); + VL_DO_DANGLING(lhsp->deleteTree(), lhsp); + VL_DO_DANGLING(rhsp->deleteTree(), rhsp); + return new AstConst{fileline(), AstConst::BitTrue{}}; + } + + if (lhsUnbounded) { + // [$:N] - only check expr <= rhs + // Use exprp directly (not cloned) so ExprStmt side effects are preserved + VL_DO_DANGLING(lhsp->deleteTree(), lhsp); + AstNodeExpr* const bp = new AstLte{fileline(), exprp, rhsp}; + bp->fileline()->modifyWarnOff(V3ErrorCode::CMPCONST, true); + return bp; + } else if (rhsUnbounded) { + // [N:$] - only check expr >= lhs + VL_DO_DANGLING(rhsp->deleteTree(), rhsp); + AstNodeExpr* const ap = new AstGte{fileline(), exprp, lhsp}; + ap->fileline()->modifyWarnOff(V3ErrorCode::UNSIGNED, true); + return ap; + } + + // Normal case: [N:M] - check expr >= lhs && expr <= rhs AstNodeExpr* const ap = new AstGte{fileline(), exprp, lhsp}; AstNodeExpr* lteLhsp; if (const AstExprStmt* const exprStmt = VN_CAST(exprp, ExprStmt)) { @@ -374,7 +401,7 @@ void AstCReset::dump(std::ostream& str) const { if (constructing()) str << " [CONS]"; } void AstCReset::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, constructing); + dumpJsonBoolFuncIf(str, constructing); dumpJsonGen(str); } @@ -416,8 +443,8 @@ void AstConsDynArray::dump(std::ostream& str) const { if (rhsIsValue()) str << " [RVAL]"; } void AstConsDynArray::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, lhsIsValue); - dumpJsonBoolFunc(str, rhsIsValue); + dumpJsonBoolFuncIf(str, lhsIsValue); + dumpJsonBoolFuncIf(str, rhsIsValue); dumpJsonGen(str); } @@ -427,8 +454,8 @@ void AstConsQueue::dump(std::ostream& str) const { if (rhsIsValue()) str << " [RVAL]"; } void AstConsQueue::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, lhsIsValue); - dumpJsonBoolFunc(str, rhsIsValue); + dumpJsonBoolFuncIf(str, lhsIsValue); + dumpJsonBoolFuncIf(str, rhsIsValue); dumpJsonGen(str); } void AstConstraint::dump(std::ostream& str) const { @@ -442,11 +469,11 @@ void AstConstraint::dump(std::ostream& str) const { if (isStatic()) str << " [STATIC]"; } void AstConstraint::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isExternDef); - dumpJsonBoolFunc(str, isExternExplicit); - dumpJsonBoolFunc(str, isExternProto); - dumpJsonBoolFunc(str, isKwdPure); - dumpJsonBoolFunc(str, isStatic); + dumpJsonBoolFuncIf(str, isExternDef); + dumpJsonBoolFuncIf(str, isExternExplicit); + dumpJsonBoolFuncIf(str, isExternProto); + dumpJsonBoolFuncIf(str, isKwdPure); + dumpJsonBoolFuncIf(str, isStatic); if (baseOverride().isAny()) dumpJsonStr(str, "baseOverride", baseOverride().ascii()); dumpJsonGen(str); } @@ -456,8 +483,8 @@ void AstConstraintExpr::dump(std::ostream& str) const { if (isSoft()) str << " [SOFT]"; } void AstConstraintExpr::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isDisableSoft); - dumpJsonBoolFunc(str, isSoft); + dumpJsonBoolFuncIf(str, isDisableSoft); + dumpJsonBoolFuncIf(str, isSoft); dumpJsonGen(str); } AstConst* AstConst::parseParamLiteral(FileLine* fl, const string& literal) { @@ -516,8 +543,8 @@ void AstNew::dump(std::ostream& str) const { if (isScoped()) str << " [SCOPED]"; } void AstNew::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isImplicit); - dumpJsonBoolFunc(str, isScoped); + dumpJsonBoolFuncIf(str, isImplicit); + dumpJsonBoolFuncIf(str, isScoped); dumpJsonGen(str); } @@ -565,6 +592,7 @@ void AstVar::combineType(VVarType type) { } if (type == VVarType::TRI0) m_isPulldown = true; if (type == VVarType::TRI1) m_isPullup = true; + if (type.isParam()) m_isConst = true; } string AstVar::verilogKwd() const { @@ -648,6 +676,8 @@ string AstVar::vlEnumDir() const { } else if (isSigUserRdPublic()) { out += "|VLVF_PUB_RD"; } + if (isForceable()) out += "|VLVF_FORCEABLE"; + if (isContinuously()) out += "|VLVF_CONTINUOUSLY"; // if (const AstBasicDType* const bdtypep = basicp()) { if (bdtypep->keyword().isDpiCLayout()) out += "|VLVF_DPI_CLAY"; @@ -847,8 +877,7 @@ string AstVar::dpiTmpVarType(const string& varName) const { string primitive(const AstVar* varp) const override { string type = dpiTypesToStringConverter::primitive(varp); if (varp->isWritable() || VN_IS(varp->dtypep()->skipRefp(), UnpackArrayDType)) { - if (!varp->isWritable() && varp->basicp()->keyword() == VBasicDTypeKwd::CHANDLE) - type = "const " + type; + if (!varp->isWritable() && varp->basicp()->isCHandle()) type = "const " + type; } type += ' ' + m_name + arraySuffix(varp, 0); return type; @@ -912,12 +941,21 @@ AstVar* AstVar::scVarRecurse(AstNode* nodep) { const AstNodeDType* AstNodeDType::skipRefIterp(bool skipConst, bool skipEnum, bool assertOn) const VL_MT_STABLE { static constexpr int MAX_TYPEDEF_DEPTH = 1000; + static constexpr int MAX_CHAIN_DISPLAY = 10; const AstNodeDType* nodep = this; + std::unordered_set visited; + std::vector chain; + bool isCycle = false; for (int depth = 0; depth < MAX_TYPEDEF_DEPTH; ++depth) { if (VN_IS(nodep, MemberDType) || VN_IS(nodep, ParamTypeDType) || VN_IS(nodep, RefDType) // || VN_IS(nodep, RequireDType) // || (VN_IS(nodep, ConstDType) && skipConst) // || (VN_IS(nodep, EnumDType) && skipEnum)) { + if (!visited.emplace(nodep).second) { + isCycle = true; + break; + } + if (chain.size() < static_cast(MAX_CHAIN_DISPLAY)) chain.push_back(nodep); if (const AstNodeDType* subp = nodep->subDTypep()) { nodep = subp; continue; @@ -928,7 +966,33 @@ const AstNodeDType* AstNodeDType::skipRefIterp(bool skipConst, bool skipEnum, } return nodep; } - nodep->v3error("Recursive type definition, or over " << MAX_TYPEDEF_DEPTH << " types deep"); + // Build user-facing error with type chain + V3Error::v3errorPrep(V3ErrorCode::EC_ERROR); + { + std::ostringstream& os = V3Error::v3errorStr(); + if (isCycle) { + os << "Recursive type definition"; + } else { + os << "Type definition over " << MAX_TYPEDEF_DEPTH << " types deep"; + } + bool first = true; + for (const AstNodeDType* chainp : chain) { + // Skip internal scaffolding nodes (e.g. REQUIREDTYPE) with no user-visible name + if (chainp->name().empty()) continue; + os << '\n' + << chainp->fileline()->warnOther() << "... Type chain: " << chainp->prettyTypeName() + << '\n' + << (first ? chainp->fileline()->warnContextPrimary() + : chainp->fileline()->warnContextSecondary()); + first = false; + } + if (visited.size() > static_cast(MAX_CHAIN_DISPLAY)) { + os << '\n' + << this->fileline()->warnMore() << "... and " + << (visited.size() - MAX_CHAIN_DISPLAY) << " more"; + } + } + this->v3errorEnd(V3Error::v3errorStr()); return nullptr; } @@ -1641,8 +1705,8 @@ void AstNodeProcedure::dump(std::ostream& str) const { } void AstNodeProcedure::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isSuspendable); - dumpJsonBoolFunc(str, needProcess); + dumpJsonBoolFuncIf(str, isSuspendable); + dumpJsonBoolFuncIf(str, needProcess); dumpJsonGen(str); } @@ -1746,7 +1810,7 @@ void AstCvtArrayToArray::dump(std::ostream& str) const { str << " srcElementBits=" << srcElementBits(); } void AstCvtArrayToArray::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, reverse); + dumpJsonBoolFuncIf(str, reverse); dumpJsonNumFunc(str, blockSize); dumpJsonNumFunc(str, dstElementBits); dumpJsonNumFunc(str, srcElementBits); @@ -1764,7 +1828,8 @@ void AstCell::dump(std::ostream& str) const { } void AstCell::dumpJson(std::ostream& str) const { dumpJsonStrFunc(str, origName); - dumpJsonBoolFunc(str, recursive); + dumpJsonStrFunc(str, verilogName); + dumpJsonBoolFuncIf(str, recursive); dumpJsonGen(str); } void AstCellInline::dump(std::ostream& str) const { @@ -1816,9 +1881,9 @@ void AstClass::dump(std::ostream& str) const { void AstClass::dumpJson(std::ostream& str) const { // dumpJsonNumFunc(str, declTokenNum); // Not dumped as adding token changes whole file dumpJsonBoolFuncIf(str, isCovergroup); - dumpJsonBoolFunc(str, isExtended); - dumpJsonBoolFunc(str, isInterfaceClass); - dumpJsonBoolFunc(str, isVirtual); + dumpJsonBoolFuncIf(str, isExtended); + dumpJsonBoolFuncIf(str, isInterfaceClass); + dumpJsonBoolFuncIf(str, isVirtual); if (baseOverride().isAny()) dumpJsonStr(str, "baseOverride", baseOverride().ascii()); dumpJsonGen(str); } @@ -1827,7 +1892,7 @@ void AstClassExtends::dump(std::ostream& str) const { if (isImplements()) str << " [IMPLEMENTS]"; } void AstClassExtends::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isImplements); + dumpJsonBoolFuncIf(str, isImplements); dumpJsonGen(str); } AstClass* AstClassExtends::classOrNullp() const { @@ -1876,8 +1941,8 @@ void AstClocking::dump(std::ostream& str) const { if (isGlobal()) str << " [GLOBAL]"; } void AstClocking::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isDefault); - dumpJsonBoolFunc(str, isGlobal); + dumpJsonBoolFuncIf(str, isDefault); + dumpJsonBoolFuncIf(str, isGlobal); dumpJsonGen(str); } void AstConfig::dump(std::ostream& str) const { @@ -1895,7 +1960,7 @@ void AstConfigRule::dump(std::ostream& str) const { if (isCell()) str << " [CELL]"; } void AstConfigRule::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isCell); + dumpJsonBoolFuncIf(str, isCell); dumpJsonGen(str); } void AstConfigUse::dump(std::ostream& str) const { @@ -1903,7 +1968,7 @@ void AstConfigUse::dump(std::ostream& str) const { if (isConfig()) str << " [CONFIG]"; } void AstConfigUse::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isConfig); + dumpJsonBoolFuncIf(str, isConfig); dumpJsonGen(str); } void AstDisplay::dump(std::ostream& str) const { @@ -1916,7 +1981,7 @@ void AstEnumDType::dump(std::ostream& str) const { str << " enum"; } void AstEnumDType::dumpJson(std::ostream& str) const { - dumpJsonBool(str, "enum", 1); + dumpJsonBoolIf(str, "enum", 1); dumpJsonGen(str); } void AstEnumDType::dumpSmall(std::ostream& str) const { @@ -1967,8 +2032,8 @@ void AstGenBlock::dump(std::ostream& str) const { if (unnamed()) str << " [UNNAMED]"; } void AstGenBlock::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, implied); - dumpJsonBoolFunc(str, unnamed); + dumpJsonBoolFuncIf(str, implied); + dumpJsonBoolFuncIf(str, unnamed); dumpJsonGen(str); } @@ -1990,8 +2055,8 @@ void AstIfaceRefDType::dump(std::ostream& str) const { } } void AstIfaceRefDType::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isPortDecl); - dumpJsonBoolFunc(str, isVirtual); + dumpJsonBoolFuncIf(str, isPortDecl); + dumpJsonBoolFuncIf(str, isVirtual); dumpJsonStrFunc(str, cellName); dumpJsonStrFunc(str, ifaceName); dumpJsonStrFunc(str, modportName); @@ -2108,7 +2173,7 @@ void AstMemberDType::dump(std::ostream& str) const { } void AstMemberDType::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isConstrainedRand); + dumpJsonBoolFuncIf(str, isConstrainedRand); dumpJsonStrFunc(str, name); dumpJsonStrFunc(str, tag); dumpJsonGen(str); @@ -2171,8 +2236,8 @@ void AstModportFTaskRef::dump(std::ostream& str) const { } } void AstModportFTaskRef::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isExport); - dumpJsonBoolFunc(str, isImport); + dumpJsonBoolFuncIf(str, isExport); + dumpJsonBoolFuncIf(str, isImport); dumpJsonGen(str); } void AstModportVarRef::dump(std::ostream& str) const { @@ -2196,9 +2261,9 @@ void AstModule::dump(std::ostream& str) const { if (hasGenericIface()) str << " [HASGENERICIFACE]"; } void AstModule::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isChecker); - dumpJsonBoolFunc(str, isProgram); - dumpJsonBoolFunc(str, hasGenericIface); + dumpJsonBoolFuncIf(str, isChecker); + dumpJsonBoolFuncIf(str, isProgram); + dumpJsonBoolFuncIf(str, hasGenericIface); dumpJsonGen(str); } void AstPin::dump(std::ostream& str) const { @@ -2213,8 +2278,8 @@ void AstPin::dump(std::ostream& str) const { if (svImplicit()) str << " [.SV]"; } void AstPin::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, svDotName); - dumpJsonBoolFunc(str, svImplicit); + dumpJsonBoolFuncIf(str, svDotName); + dumpJsonBoolFuncIf(str, svImplicit); dumpJsonGen(str); } string AstPin::prettyOperatorName() const { @@ -2281,8 +2346,8 @@ void AstTypedef::dump(std::ostream& str) const { } void AstTypedef::dumpJson(std::ostream& str) const { // dumpJsonNumFunc(str, declTokenNum); // Not dumped as adding token changes whole file - dumpJsonBoolFunc(str, attrPublic); - dumpJsonBoolFunc(str, isUnderClass); + dumpJsonBoolFuncIf(str, attrPublic); + dumpJsonBoolFuncIf(str, isUnderClass); dumpJsonGen(str); } void AstTypedefFwd::dump(std::ostream& str) const { @@ -2309,7 +2374,7 @@ void AstRange::dump(std::ostream& str) const { if (ascending()) str << " [ASCENDING]"; } void AstRSProdList::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, randJoin); + dumpJsonBoolFuncIf(str, randJoin); dumpJsonGen(str); } void AstRSProdList::dump(std::ostream& str) const { @@ -2317,8 +2382,8 @@ void AstRSProdList::dump(std::ostream& str) const { if (randJoin()) str << " [RANDJOIN]"; } void AstRange::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, ascending); - dumpJsonBoolFunc(str, fromBracket); + dumpJsonBoolFuncIf(str, ascending); + dumpJsonBoolFuncIf(str, fromBracket); dumpJsonGen(str); } void AstParamTypeDType::dump(std::ostream& str) const { @@ -2370,10 +2435,24 @@ void AstNodeUOrStructDType::dump(std::ostream& str) const { if (classOrPackagep()) str << " pkg=" << nodeAddr(classOrPackagep()); } void AstNodeUOrStructDType::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, packed); - dumpJsonBoolFunc(str, isFourstate); + dumpJsonBoolFuncIf(str, packed); + dumpJsonBoolFuncIf(str, isFourstate); dumpJsonGen(str); } +void AstUnionDType::dump(std::ostream& str) const { + this->AstNodeUOrStructDType::dump(str); + if (isSoft()) str << " [soft]"; + if (isTagged()) str << " [tagged]"; +} +void AstUnionDType::dumpJson(std::ostream& str) const { + this->AstNodeUOrStructDType::dumpJson(str); + dumpJsonBoolFuncIf(str, isSoft); + dumpJsonBoolFuncIf(str, isTagged); +} +bool AstUnionDType::sameNode(const AstNode* samep) const { + const AstUnionDType* const asamep = VN_DBG_AS(samep, UnionDType); + return m_isSoft == asamep->m_isSoft && m_isTagged == asamep->m_isTagged; +} string AstNodeUOrStructDType::prettyDTypeName(bool full) const { string result = verilogKwd() + "{"; if (full) { // else shorten for errors @@ -2395,8 +2474,8 @@ void AstNodeDType::dump(std::ostream& str) const { } } void AstNodeDType::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, generic); - if (isSigned() && !isDouble()) dumpJsonBool(str, "signed", 1); + dumpJsonBoolFuncIf(str, generic); + if (isSigned() && !isDouble()) dumpJsonBoolIf(str, "signed", 1); dumpJsonGen(str); } void AstNodeDType::dumpSmall(std::ostream& str) const VL_MT_STABLE { @@ -2422,7 +2501,7 @@ void AstNodeArrayDType::dump(std::ostream& str) const { str << " " << declRange(); } void AstNodeArrayDType::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isCompound); + dumpJsonBoolFuncIf(str, isCompound); dumpJsonStr(str, "declRange", cvtToStr(declRange())); dumpJsonGen(str); } @@ -2503,6 +2582,13 @@ void AstNetlist::createTopScope(AstScope* scopep) { m_topScopep = new AstTopScope{scopep->modp()->fileline(), scopep}; scopep->modp()->addStmtsp(v3Global.rootp()->topScopep()); } +AstVarScope* AstNetlist::stlFirstIterationp() { + if (!m_stlFirstIterationp) { + m_stlFirstIterationp = topScopep()->scopep()->createTemp("__VstlFirstIteration", 1); + } + AstVarScope* const vscp = m_stlFirstIterationp; + return vscp; +} void AstNodeModule::dump(std::ostream& str) const { this->AstNode::dump(str); str << " L" << level(); @@ -2515,17 +2601,20 @@ void AstNodeModule::dump(std::ostream& str) const { } else if (recursive()) { str << " [RECURSIVE]"; } + if (verilatorLib()) str << " [VERILATOR-LIB]"; str << " [" << timeunit() << "]"; if (libname() != "work") str << " libname=" << libname(); } void AstNodeModule::dumpJson(std::ostream& str) const { dumpJsonStrFunc(str, origName); + dumpJsonStrFunc(str, verilogName); dumpJsonNumFunc(str, level); - dumpJsonBoolFunc(str, modPublic); - dumpJsonBoolFunc(str, inLibrary); - dumpJsonBoolFunc(str, dead); - dumpJsonBoolFunc(str, recursiveClone); - dumpJsonBoolFunc(str, recursive); + dumpJsonBoolFuncIf(str, modPublic); + dumpJsonBoolFuncIf(str, inLibrary); + dumpJsonBoolFuncIf(str, dead); + dumpJsonBoolFuncIf(str, recursiveClone); + dumpJsonBoolFuncIf(str, recursive); + dumpJsonBoolFuncIf(str, verilatorLib); dumpJsonStr(str, "timeunit", timeunit().ascii()); if (libname() != "work") dumpJsonStr(str, "libname=", libname()); dumpJsonGen(str); @@ -2698,7 +2787,7 @@ void AstVarScope::dump(std::ostream& str) const { } } void AstVarScope::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isTrace); + dumpJsonBoolFuncIf(str, isTrace); dumpJsonGen(str); } bool AstVarScope::sameNode(const AstNode* samep) const { @@ -2749,7 +2838,7 @@ void AstVarXRef::dump(std::ostream& str) const { } } void AstVarXRef::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, containsGenBlock); + dumpJsonBoolFuncIf(str, containsGenBlock); dumpJsonStrFunc(str, dotted); dumpJsonStrFunc(str, inlinedDots); dumpJsonGen(str); @@ -2795,6 +2884,7 @@ void AstVar::dump(std::ostream& str) const { if (isLatched()) str << " [LATCHED]"; if (isUsedLoopIdx()) str << " [LOOPIDX]"; if (rand().isRandomizable()) str << " [" << rand() << "]"; + if (noCReset()) str << " [!CRST]"; if (noReset()) str << " [!RST]"; if (attrIsolateAssign()) str << " [aISO]"; if (attrFileDescr()) str << " [aFD]"; @@ -2803,6 +2893,7 @@ void AstVar::dump(std::ostream& str) const { } else if (isFuncLocal()) { str << " [FUNC]"; } + if (hasUserInit()) str << " [UINIT]"; if (isDpiOpenArray()) str << " [DPIOPENA]"; if (ignorePostWrite()) str << " [IGNPWR]"; if (ignoreSchedWrite()) str << " [IGNWR]"; @@ -2812,34 +2903,37 @@ void AstVar::dump(std::ostream& str) const { } void AstVar::dumpJson(std::ostream& str) const { dumpJsonStrFunc(str, origName); - dumpJsonBoolFunc(str, isSc); - dumpJsonBoolFunc(str, isPrimaryIO); - dumpJsonBoolFunc(str, isPrimaryClock); + dumpJsonStrFunc(str, verilogName); + dumpJsonBoolFuncIf(str, isSc); + dumpJsonBoolFuncIf(str, isPrimaryIO); + dumpJsonBoolFuncIf(str, isPrimaryClock); dumpJsonStr(str, "direction", direction().ascii()); - dumpJsonBoolFunc(str, isConst); - dumpJsonBoolFunc(str, isPullup); - dumpJsonBoolFunc(str, isPulldown); - dumpJsonBoolFunc(str, isSigPublic); - dumpJsonBoolFunc(str, isLatched); - dumpJsonBoolFunc(str, isUsedLoopIdx); - dumpJsonBoolFunc(str, noReset); - dumpJsonBoolFunc(str, attrIsolateAssign); - dumpJsonBoolFunc(str, attrFileDescr); - dumpJsonBoolFunc(str, isDpiOpenArray); - dumpJsonBoolFunc(str, isFuncReturn); - dumpJsonBoolFunc(str, isFuncLocal); - dumpJsonBoolFunc(str, isStdRandomizeArg); + dumpJsonBoolFuncIf(str, isConst); + dumpJsonBoolFuncIf(str, isPullup); + dumpJsonBoolFuncIf(str, isPulldown); + dumpJsonBoolFuncIf(str, isSigPublic); + dumpJsonBoolFuncIf(str, isLatched); + dumpJsonBoolFuncIf(str, isUsedLoopIdx); + dumpJsonBoolFuncIf(str, noCReset); + dumpJsonBoolFuncIf(str, noReset); + dumpJsonBoolFuncIf(str, attrIsolateAssign); + dumpJsonBoolFuncIf(str, attrFileDescr); + dumpJsonBoolFuncIf(str, isDpiOpenArray); + dumpJsonBoolFuncIf(str, isFuncReturn); + dumpJsonBoolFuncIf(str, isFuncLocal); + dumpJsonBoolFuncIf(str, isStdRandomizeArg); dumpJsonStr(str, "lifetime", lifetime().ascii()); dumpJsonStr(str, "varType", varType().ascii()); if (dtypep()) dumpJsonStr(str, "dtypeName", dtypep()->name()); - dumpJsonBoolFunc(str, isSigUserRdPublic); - dumpJsonBoolFunc(str, isSigUserRWPublic); - dumpJsonBoolFunc(str, isGParam); - dumpJsonBoolFunc(str, isParam); - dumpJsonBoolFunc(str, attrScBv); - dumpJsonBoolFunc(str, attrSFormat); - dumpJsonBoolFunc(str, ignorePostWrite); - dumpJsonBoolFunc(str, ignoreSchedWrite); + dumpJsonBoolFuncIf(str, isSigUserRdPublic); + dumpJsonBoolFuncIf(str, isSigUserRWPublic); + dumpJsonBoolFuncIf(str, isGParam); + dumpJsonBoolFuncIf(str, isParam); + dumpJsonBoolFuncIf(str, attrScBv); + dumpJsonBoolFuncIf(str, attrSFormat); + dumpJsonBoolFuncIf(str, hasUserInit); + dumpJsonBoolFuncIf(str, ignorePostWrite); + dumpJsonBoolFuncIf(str, ignoreSchedWrite); dumpJsonGen(str); } void AstScope::dump(std::ostream& str) const { @@ -2864,8 +2958,8 @@ void AstScopeName::dump(std::ostream& str) const { str << " scopeEntr=\"" << m_scopeEntr << "\""; } void AstScopeName::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, dpiExport); - dumpJsonBoolFunc(str, forFormat); + dumpJsonBoolFuncIf(str, dpiExport); + dumpJsonBoolFuncIf(str, forFormat); dumpJsonStr(str, "scopeAttr", m_scopeAttr); dumpJsonStr(str, "scopeEntr", m_scopeEntr); dumpJsonGen(str); @@ -2875,7 +2969,7 @@ void AstSenTree::dump(std::ostream& str) const { if (isMulti()) str << " [MULTI]"; } void AstSenTree::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isMulti); + dumpJsonBoolFuncIf(str, isMulti); dumpJsonGen(str); } void AstSenItem::dump(std::ostream& str) const { @@ -2929,7 +3023,7 @@ void AstDot::dump(std::ostream& str) const { if (colon()) str << " [::]"; } void AstDot::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, colon); + dumpJsonBoolFuncIf(str, colon); dumpJsonGen(str); } void AstActive::dump(std::ostream& str) const { @@ -3007,18 +3101,18 @@ bool AstNodeFTask::getPurityRecurse() const { return true; } void AstNodeFTask::dumpJson(std::ostream& str) const { - dumpJsonBool(str, "method", classMethod()); - dumpJsonBoolFunc(str, dpiExport); - dumpJsonBoolFunc(str, dpiImport); - dumpJsonBoolFunc(str, dpiOpenChild); - dumpJsonBoolFunc(str, dpiOpenParent); - dumpJsonBoolFunc(str, isExternDef); - dumpJsonBoolFunc(str, isExternProto); + dumpJsonBoolIf(str, "method", classMethod()); + dumpJsonBoolFuncIf(str, dpiExport); + dumpJsonBoolFuncIf(str, dpiImport); + dumpJsonBoolFuncIf(str, dpiOpenChild); + dumpJsonBoolFuncIf(str, dpiOpenParent); + dumpJsonBoolFuncIf(str, isExternDef); + dumpJsonBoolFuncIf(str, isExternProto); dumpJsonBoolFuncIf(str, isVirtual); dumpJsonBoolFuncIf(str, needProcess); - dumpJsonBoolFunc(str, prototype); - dumpJsonBoolFunc(str, recursive); - dumpJsonBoolFunc(str, taskPublic); + dumpJsonBoolFuncIf(str, prototype); + dumpJsonBoolFuncIf(str, recursive); + dumpJsonBoolFuncIf(str, taskPublic); if (baseOverride().isAny()) dumpJsonStr(str, "baseOverride", baseOverride().ascii()); dumpJsonStrFunc(str, cname); dumpJsonGen(str); @@ -3028,7 +3122,7 @@ void AstNodeBlock::dump(std::ostream& str) const { if (unnamed()) str << " [UNNAMED]"; } void AstNodeBlock::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, unnamed); + dumpJsonBoolFuncIf(str, unnamed); dumpJsonGen(str); } void AstBegin::dump(std::ostream& str) const { @@ -3037,8 +3131,8 @@ void AstBegin::dump(std::ostream& str) const { if (needProcess()) str << " [NPRC]"; } void AstBegin::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, implied); - dumpJsonBoolFunc(str, needProcess); + dumpJsonBoolFuncIf(str, implied); + dumpJsonBoolFuncIf(str, needProcess); dumpJsonGen(str); } void AstNodeCoverDecl::dump(std::ostream& str) const { @@ -3105,7 +3199,7 @@ void AstStop::dump(std::ostream& str) const { if (isFatal()) str << " [FATAL]"; } void AstStop::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isFatal); + dumpJsonBoolFuncIf(str, isFatal); dumpJsonGen(str); } void AstTraceDecl::dump(std::ostream& str) const { @@ -3156,8 +3250,8 @@ void AstCFile::dump(std::ostream& str) const { } void AstCFile::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, source); - dumpJsonBoolFunc(str, slow); + dumpJsonBoolFuncIf(str, source); + dumpJsonBoolFuncIf(str, slow); dumpJsonGen(str); } void AstCFunc::dump(std::ostream& str) const { @@ -3178,25 +3272,27 @@ void AstCFunc::dump(std::ostream& str) const { if (isCoroutine()) str << " [CORO]"; if (needProcess()) str << " [NPRC]"; if (entryPoint()) str << " [ENTRY]"; + if (noLife()) str << " [NOLIFE]"; } void AstCFunc::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, slow); - dumpJsonBoolFunc(str, isStatic); - dumpJsonBoolFunc(str, dpiExportDispatcher); - dumpJsonBoolFunc(str, dpiExportImpl); - dumpJsonBoolFunc(str, dpiImportPrototype); - dumpJsonBoolFunc(str, dpiImportWrapper); - dumpJsonBoolFunc(str, dpiContext); - dumpJsonBoolFunc(str, isConstructor); - dumpJsonBoolFunc(str, isDestructor); - dumpJsonBoolFunc(str, isVirtual); - dumpJsonBoolFunc(str, isCoroutine); - dumpJsonBoolFunc(str, needProcess); + dumpJsonBoolFuncIf(str, slow); + dumpJsonBoolFuncIf(str, isStatic); + dumpJsonBoolFuncIf(str, dpiExportDispatcher); + dumpJsonBoolFuncIf(str, dpiExportImpl); + dumpJsonBoolFuncIf(str, dpiImportPrototype); + dumpJsonBoolFuncIf(str, dpiImportWrapper); + dumpJsonBoolFuncIf(str, dpiContext); + dumpJsonBoolFuncIf(str, isConstructor); + dumpJsonBoolFuncIf(str, isDestructor); + dumpJsonBoolFuncIf(str, isVirtual); + dumpJsonBoolFuncIf(str, isCoroutine); + dumpJsonBoolFuncIf(str, needProcess); + dumpJsonBoolFuncIf(str, noLife); dumpJsonGen(str); // TODO: maybe try to shorten these flags somehow } void AstCAwait::dump(std::ostream& str) const { - this->AstNodeUniop::dump(str); + this->AstNodeStmt::dump(str); if (sentreep()) { str << " => "; sentreep()->dump(str); @@ -3270,7 +3366,7 @@ void AstCgOptionAssign::dump(std::ostream& str) const { this->AstNode::dump(str); } void AstCgOptionAssign::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, typeOption); + dumpJsonBoolFuncIf(str, typeOption); dumpJsonGen(str); } void AstDelay::dump(std::ostream& str) const { @@ -3278,7 +3374,7 @@ void AstDelay::dump(std::ostream& str) const { if (isCycleDelay()) str << " [CYCLE]"; } void AstDelay::dumpJson(std::ostream& str) const { - dumpJsonBoolFunc(str, isCycleDelay); + dumpJsonBoolFuncIf(str, isCycleDelay); dumpJsonGen(str); } diff --git a/src/V3AstUserAllocator.h b/src/V3AstUserAllocator.h index 2bcd255e0..a9c988fce 100644 --- a/src/V3AstUserAllocator.h +++ b/src/V3AstUserAllocator.h @@ -7,10 +7,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp index fc5a6ec3f..b1b02ca0a 100644 --- a/src/V3Begin.cpp +++ b/src/V3Begin.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -68,7 +68,8 @@ class BeginVisitor final : public VNVisitor { // STATE - for current visit position (use VL_RESTORER) AstNodeModule* m_modp = nullptr; // Current module AstNodeFTask* m_ftaskp = nullptr; // Current function/task - AstNode* m_liftedp = nullptr; // Local nodes we are lifting into m_ftaskp + AstNodeProcedure* m_procedurep = nullptr; // Current procedure + AstNode* m_liftedp = nullptr; // Local nodes we are lifting into m_ftaskp string m_displayScope; // Name of %m in $display/AstScopeName string m_namedScope; // Name of begin blocks above us string m_unnamedScope; // Name of begin blocks, including unnamed blocks @@ -120,17 +121,6 @@ class BeginVisitor final : public VNVisitor { } // VISITORS - void visit(AstFork* nodep) override { - dotNames(nodep->name(), nodep->fileline(), "__FORK__"); - iterateAndNextNull(nodep->stmtsp()); - { - // Keep begins in forks to group their statements together - VL_RESTORER(m_keepBegins); - m_keepBegins = true; - iterateAndNextNull(nodep->forksp()); - } - nodep->name(""); - } void visit(AstForeach* nodep) override { VL_DO_DANGLING(V3Begin::convertToWhile(nodep), nodep); } @@ -158,6 +148,11 @@ class BeginVisitor final : public VNVisitor { m_unnamedScope = ""; iterateChildren(nodep); } + void visit(AstNodeProcedure* nodep) override { + VL_RESTORER(m_procedurep); + m_procedurep = nodep; + iterateChildren(nodep); + } void visit(AstNodeFTask* nodep) override { UINFO(8, " " << nodep); // Rename it @@ -212,6 +207,27 @@ class BeginVisitor final : public VNVisitor { } VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); } + void visit(AstFork* nodep) override { + dotNames(nodep->name(), nodep->fileline(), "__FORK__"); + iterateAndNextNull(nodep->stmtsp()); + { + // Keep begins in forks to group their statements together + VL_RESTORER(m_keepBegins); + m_keepBegins = true; + iterateAndNextNull(nodep->forksp()); + } + AstNode* addsp = nullptr; + if (AstNode* const declsp = nodep->declsp()) { + declsp->unlinkFrBackWithNext(); + addsp = AstNode::addNext(addsp, declsp); + } + if (AstNode* const stmtsp = nodep->stmtsp()) { + stmtsp->unlinkFrBackWithNext(); + addsp = AstNode::addNext(addsp, stmtsp); + } + if (addsp) nodep->addHereThisAsNext(addsp); + nodep->name(""); + } void visit(AstBegin* nodep) override { // Begin blocks were only useful in variable creation, change names and delete UINFO(8, " " << nodep); @@ -246,6 +262,41 @@ class BeginVisitor final : public VNVisitor { } VL_DO_DANGLING(pushDeletep(nodep), nodep); } + void visit(AstNodeBlock* nodep) override { + // Begin/Fork blocks were only useful in variable creation, change names and delete + UINFO(8, " " << nodep); + VL_RESTORER(m_displayScope); + VL_RESTORER(m_namedScope); + VL_RESTORER(m_unnamedScope); + { + VL_RESTORER(m_keepBegins); + m_keepBegins = VN_IS(nodep, Fork); + dotNames(nodep->name(), nodep->fileline(), + VN_IS(nodep, Fork) ? "__FORK__" : "__BEGIN__"); + iterateChildren(nodep); + } + + // Cleanup + if (m_keepBegins) { + nodep->name(""); + return; + } + AstNode* addsp = nullptr; + if (AstNode* const declsp = nodep->declsp()) { + declsp->unlinkFrBackWithNext(); + addsp = AstNode::addNext(addsp, declsp); + } + if (AstNode* const stmtsp = nodep->stmtsp()) { + stmtsp->unlinkFrBackWithNext(); + addsp = AstNode::addNext(addsp, stmtsp); + } + if (addsp) { + nodep->replaceWith(addsp); + } else { + nodep->unlinkFrBack(); + } + VL_DO_DANGLING(pushDeletep(nodep), nodep); + } void visit(AstVar* nodep) override { // If static variable, move it outside a function. if (nodep->lifetime().isStatic() && m_ftaskp) { @@ -263,6 +314,28 @@ class BeginVisitor final : public VNVisitor { liftNode(nodep); } } + void visit(AstInitialAutomaticStmt* nodep) override { + // Automatic sets go at the current location + nodep->replaceWith(nodep->stmtsp()->unlinkFrBackWithNext()); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + } + void visit(AstInitialStaticStmt* nodep) override { + // As we moved static variables, move static initializers too + if (nodep->user1SetOnce()) return; // Don't double-add text's + AstNode* wasUnderp = m_ftaskp; + if (!m_ftaskp) wasUnderp = m_procedurep; + if (wasUnderp) { + if (nodep->stmtsp()) { + AstNode* const newp = new AstInitialStatic{ + nodep->fileline(), nodep->stmtsp()->unlinkFrBackWithNext()}; + wasUnderp->addHereThisAsNext(newp); + iterateChildren(newp); + } + VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); + } else { + nodep->v3fatalSrc("InitialStaticStmt under unexpected grand-parent"); + } + } void visit(AstTypedef* nodep) override { if (m_unnamedScope != "") { // Rename it @@ -471,9 +544,8 @@ static AstNode* createForeachLoopRanged(AstNodeForeach* nodep, AstNode* bodysp, } AstNode* V3Begin::convertToWhile(AstForeach* nodep) { // UINFOTREE(1, nodep, "", "foreach-old"); - const AstSelLoopVars* const loopsp = VN_CAST(nodep->arrayp(), SelLoopVars); - UASSERT_OBJ(loopsp, nodep, "No loop variables under foreach"); - AstNodeExpr* const fromp = loopsp->fromp(); + const AstForeachHeader* const headerp = nodep->headerp(); + AstNodeExpr* const fromp = headerp->fromp(); UASSERT_OBJ(fromp->dtypep(), fromp, "Missing data type"); AstNodeDType* fromDtp = fromp->dtypep()->skipRefp(); // Split into for loop @@ -486,7 +558,7 @@ AstNode* V3Begin::convertToWhile(AstForeach* nodep) { // dyn-arr and associative-arr) AstNodeExpr* subfromp = fromp->cloneTreePure(false); // Major dimension first - for (AstNode *argsp = loopsp->elementsp(), *next_argsp; argsp; argsp = next_argsp) { + for (AstNode *argsp = headerp->elementsp(), *next_argsp; argsp; argsp = next_argsp) { next_argsp = argsp->nextp(); const bool empty = VN_IS(argsp, Empty); AstVar* const varp = VN_CAST(argsp, Var); @@ -578,7 +650,7 @@ AstNode* V3Begin::convertToWhile(AstForeach* nodep) { } VL_DO_DANGLING(subfromp->deleteTree(), subfromp); // The parser validates we don't have "foreach (array[,,,])" - AstNode* const bodyp = nodep->stmtsp(); + AstNode* const bodyp = nodep->bodyp(); if (!newp) { nodep->v3warn(NOEFFECT, "foreach with no loop variable has no effect"); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); diff --git a/src/V3Begin.h b/src/V3Begin.h index df119b7f2..adc75197d 100644 --- a/src/V3Begin.h +++ b/src/V3Begin.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Branch.cpp b/src/V3Branch.cpp index b7cffb6f5..8702dfe8e 100644 --- a/src/V3Branch.cpp +++ b/src/V3Branch.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Branch.h b/src/V3Branch.h index 209c9b77b..97314a3a6 100644 --- a/src/V3Branch.h +++ b/src/V3Branch.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Broken.cpp b/src/V3Broken.cpp index 42ae66fe3..9ffef7f60 100644 --- a/src/V3Broken.cpp +++ b/src/V3Broken.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -193,6 +193,8 @@ private: UASSERT_OBJ(nodep->dtypep(), nodep, "No dtype on node with hasDType(): " << nodep->prettyTypeName()); } else { + UASSERT_OBJ(!VN_IS(nodep, NodeExpr), nodep, + "All AstNodeExpr must have a dtype post V3WidthCommit"); UASSERT_OBJ(!nodep->dtypep(), nodep, "DType on node without hasDType(): " << nodep->prettyTypeName()); } @@ -234,9 +236,8 @@ private: const size_t nWriteRefs = m_nWriteRefs; const size_t nCalls = m_nCalls; iterateConst(nodep->lhsp()); - // TODO: Enable this when #6756 is fixed // Only check if there are no calls on the LHS, as calls might return an LValue - if (false && v3Global.assertDTypesResolved() && m_nCalls == nCalls) { + if (v3Global.assertDTypesResolved() && m_nCalls == nCalls) { UASSERT_OBJ(m_nWriteRefs > nWriteRefs, nodep, "No write refs on LHS of assignment"); } processExit(nodep); @@ -275,6 +276,8 @@ private: UASSERT_OBJ( !(v3Global.assertScoped() && m_inScope && nodep->varp() && !nodep->varScopep()), nodep, "VarRef missing VarScope pointer"); + UASSERT_OBJ(!v3Global.assertScoped() || !nodep->classOrPackagep(), nodep, + "VarRef classOrPackagep must be nullptr after V3Scope"); if (m_cfuncp) { // Check if variable is an in-scope local, otherwise mark as suspect if (const AstVar* const varp = nodep->varp()) { diff --git a/src/V3Broken.h b/src/V3Broken.h index 0576aa283..b40906f0f 100644 --- a/src/V3Broken.h +++ b/src/V3Broken.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3CCtors.cpp b/src/V3CCtors.cpp index ac7d035e2..0c4092286 100644 --- a/src/V3CCtors.cpp +++ b/src/V3CCtors.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -192,12 +192,13 @@ class CCtorsVisitor final : public VNVisitor { } void visit(AstVar* nodep) override { if (nodep->needsCReset()) { + AstNode* const crstp = new AstAssign{ + nodep->fileline(), new AstVarRef{nodep->fileline(), nodep, VAccess::WRITE}, + new AstCReset{nodep->fileline(), nodep, true}}; if (m_varResetp) { - AstVarRef* const vrefp = new AstVarRef{nodep->fileline(), nodep, VAccess::WRITE}; - m_varResetp->add(new AstCReset{nodep->fileline(), vrefp, true}); + m_varResetp->add(crstp); } else if (m_cfuncp) { - AstVarRef* const vrefp = new AstVarRef{nodep->fileline(), nodep, VAccess::WRITE}; - nodep->addNextHere(new AstCReset{nodep->fileline(), vrefp, true}); + nodep->addNextHere(crstp); } } } diff --git a/src/V3CCtors.h b/src/V3CCtors.h index 07336b85c..ca8028848 100644 --- a/src/V3CCtors.h +++ b/src/V3CCtors.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3CUse.cpp b/src/V3CUse.cpp index 2fd0f76ff..ce4158542 100644 --- a/src/V3CUse.cpp +++ b/src/V3CUse.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3CUse.h b/src/V3CUse.h index 38a40fc20..d6b78cb9c 100644 --- a/src/V3CUse.h +++ b/src/V3CUse.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Case.cpp b/src/V3Case.cpp index ff4fb6727..e2baca0a5 100644 --- a/src/V3Case.cpp +++ b/src/V3Case.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -244,9 +244,13 @@ class CaseVisitor final : public VNVisitor { caseItemMap[icondp] = itemp; foundHit = true; } else if (!overlappedCondp) { - firstOverlap = i; - overlappedCondp = m_valueItem[i]; - m_caseNoOverlapsAllCovered = false; + // Overlapping case item expressions in the + // same case item are legal + if (caseItemMap[m_valueItem[i]] != itemp) { + firstOverlap = i; + overlappedCondp = m_valueItem[i]; + m_caseNoOverlapsAllCovered = false; + } } } } diff --git a/src/V3Case.h b/src/V3Case.h index 748962704..9744e96d3 100644 --- a/src/V3Case.h +++ b/src/V3Case.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Cast.cpp b/src/V3Cast.cpp index 09015cc32..7a482ec26 100644 --- a/src/V3Cast.cpp +++ b/src/V3Cast.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Cast.h b/src/V3Cast.h index 4df56dd81..387238ae9 100644 --- a/src/V3Cast.h +++ b/src/V3Cast.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Cfg.cpp b/src/V3Cfg.cpp index 910512308..954ab4d03 100644 --- a/src/V3Cfg.cpp +++ b/src/V3Cfg.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Cfg.h b/src/V3Cfg.h index e01008d26..d4cf8a9af 100644 --- a/src/V3Cfg.h +++ b/src/V3Cfg.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3CfgBuilder.cpp b/src/V3CfgBuilder.cpp index ced4306cd..5545dcf16 100644 --- a/src/V3CfgBuilder.cpp +++ b/src/V3CfgBuilder.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -81,7 +81,6 @@ class CfgBuilder final : public VNVisitorConst { // Non-representable statements void visit(AstAssignDly* nodep) override { nonRepresentable(nodep); } void visit(AstCase* nodep) override { nonRepresentable(nodep); } // V3Case will eliminate - void visit(AstCReset* nodep) override { nonRepresentable(nodep); } void visit(AstDelay* nodep) override { nonRepresentable(nodep); } // Representable non control-flow statements diff --git a/src/V3CfgLiveVariables.cpp b/src/V3CfgLiveVariables.cpp index b63ac21ef..3b6eeab70 100644 --- a/src/V3CfgLiveVariables.cpp +++ b/src/V3CfgLiveVariables.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Class.cpp b/src/V3Class.cpp index 5b2a1e7b3..43f417313 100644 --- a/src/V3Class.cpp +++ b/src/V3Class.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Class.h b/src/V3Class.h index 964ad3dc7..d16d5a49d 100644 --- a/src/V3Class.h +++ b/src/V3Class.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Clean.cpp b/src/V3Clean.cpp index 4af58adca..61f509922 100644 --- a/src/V3Clean.cpp +++ b/src/V3Clean.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Clean.h b/src/V3Clean.h index 9f4d21a28..155066e9d 100644 --- a/src/V3Clean.h +++ b/src/V3Clean.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp index 6cb97aee7..6a0b3e3fa 100644 --- a/src/V3Clock.cpp +++ b/src/V3Clock.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Clock.h b/src/V3Clock.h index 0e50ca6c6..d177074b0 100644 --- a/src/V3Clock.h +++ b/src/V3Clock.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Combine.cpp b/src/V3Combine.cpp index 435f3d90e..fe7f99c4f 100644 --- a/src/V3Combine.cpp +++ b/src/V3Combine.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Combine.h b/src/V3Combine.h index cd53962f6..e2985fc9b 100644 --- a/src/V3Combine.h +++ b/src/V3Combine.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Common.cpp b/src/V3Common.cpp index 80699df38..1d0deb257 100644 --- a/src/V3Common.cpp +++ b/src/V3Common.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -37,10 +37,6 @@ string V3Common::makeToStringCall(AstNodeDType* nodep, const std::string& lhs) { stmt += "VL_TO_STRING_W("; stmt += cvtToStr(nodep->widthWords()); stmt += ", "; - } else if (VN_IS(nodep->skipRefp(), BasicDType) && nodep->isWide()) { - stmt += "VL_TO_STRING_W("; - stmt += cvtToStr(nodep->widthWords()); - stmt += ", "; } else { stmt += "VL_TO_STRING("; } @@ -49,20 +45,6 @@ string V3Common::makeToStringCall(AstNodeDType* nodep, const std::string& lhs) { return stmt; } -static void makeVlToString(AstClass* nodep) { - AstCFunc* const funcp - = new AstCFunc{nodep->fileline(), "VL_TO_STRING", nullptr, "std::string"}; - funcp->argTypes("const VlClassRef<" + EmitCUtil::prefixNameProtect(nodep) + ">& obj"); - funcp->isMethod(false); - funcp->isConst(false); - funcp->isStatic(false); - funcp->protect(false); - AstNodeExpr* const exprp - = new AstCExpr{nodep->fileline(), "obj ? obj->to_string() : \"null\""}; - exprp->dtypeSetString(); - funcp->addStmtsp(new AstCReturn{nodep->fileline(), exprp}); - nodep->addStmtsp(funcp); -} static void makeVlToString(AstIface* nodep) { AstCFunc* const funcp = new AstCFunc{nodep->fileline(), "VL_TO_STRING", nullptr, "std::string"}; @@ -112,6 +94,7 @@ static void makeToString(AstClass* nodep) { AstCFunc* const funcp = new AstCFunc{nodep->fileline(), "to_string", nullptr, "std::string"}; funcp->isConst(true); funcp->isStatic(false); + funcp->isVirtual(true); funcp->protect(false); AstCExpr* const exprp = new AstCExpr{nodep->fileline(), R"("'{"s + to_string_middle() + "}")"}; exprp->dtypeSetString(); @@ -124,14 +107,13 @@ static void makeToStringMiddle(AstClass* nodep) { funcp->isConst(true); funcp->isStatic(false); funcp->protect(false); - funcp->addStmtsp(new AstCStmt{nodep->fileline(), "std::string out;"}); + AstNodeStmt* stmtsp = nullptr; std::string comma; for (AstNode* itemp = nodep->membersp(); itemp; itemp = itemp->nextp()) { if (const auto* const varp = VN_CAST(itemp, Var)) { + const AstBasicDType* const basicp = varp->dtypeSkipRefp()->basicp(); if (!varp->isParam() && !varp->isInternal() - && !(varp->dtypeSkipRefp()->basicp() - && (varp->dtypeSkipRefp()->basicp()->isRandomGenerator() - || varp->dtypeSkipRefp()->basicp()->isStdRandomGenerator()))) { + && !(basicp && (basicp->isRandomGenerator() || basicp->isStdRandomGenerator()))) { string stmt = "out += \""; stmt += comma; comma = ", "; @@ -140,22 +122,29 @@ static void makeToStringMiddle(AstClass* nodep) { stmt += V3Common::makeToStringCall(itemp->dtypep(), itemp->nameProtect()); stmt += ";"; nodep->user1(true); // So what we extend dumps this - funcp->addStmtsp(new AstCStmt{nodep->fileline(), stmt}); + stmtsp = AstNode::addNextNull(stmtsp, new AstCStmt{nodep->fileline(), stmt}); } } } if (nodep->extendsp()) { string stmt = "out += "; - if (!comma.empty()) stmt += "\", \"+ "; + if (!comma.empty()) stmt += "\", \" + "; // comma = ", "; // Nothing further so not needed stmt += EmitCUtil::prefixNameProtect(nodep->extendsp()->dtypep()); stmt += "::to_string_middle();"; nodep->user1(true); // So what we extend dumps this - funcp->addStmtsp(new AstCStmt{nodep->fileline(), stmt}); + stmtsp = AstNode::addNextNull(stmtsp, new AstCStmt{nodep->fileline(), stmt}); } - AstCExpr* const exprp = new AstCExpr{nodep->fileline(), "out"}; - exprp->dtypeSetString(); + AstNodeExpr* exprp; + if (stmtsp) { + funcp->addStmtsp(new AstCStmt{nodep->fileline(), "std::string out;"}); + funcp->addStmtsp(stmtsp); + exprp = new AstCExpr{nodep->fileline(), "out"}; + exprp->dtypeSetString(); + } else { // Nothing to print, return "" + exprp = new AstConst{nodep->fileline(), AstConst::String{}, ""}; + } funcp->addStmtsp(new AstCReturn{nodep->fileline(), exprp}); nodep->addStmtsp(funcp); @@ -174,7 +163,6 @@ void V3Common::commonAll() { for (AstNode* nodep = v3Global.rootp()->modulesp(); nodep; nodep = nodep->nextp()) { if (AstClass* const classp = VN_CAST(nodep, Class)) { // Create ToString methods - makeVlToString(classp); makeToString(classp); makeToStringMiddle(classp); } else if (AstIface* const ifacep = VN_CAST(nodep, Iface)) { diff --git a/src/V3Common.h b/src/V3Common.h index 7fc191730..4e1e0842d 100644 --- a/src/V3Common.h +++ b/src/V3Common.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Const.cpp b/src/V3Const.cpp index b11fa675f..7ef77be05 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -931,7 +931,7 @@ class ConstVisitor final : public VNVisitor { bool m_underRecFunc = false; // Under a recursive function AstNodeModule* m_modp = nullptr; // Current module const AstArraySel* m_selp = nullptr; // Current select - const AstNode* m_scopep = nullptr; // Current scope + const AstScope* m_scopep = nullptr; // Current scope const AstAttrOf* m_attrp = nullptr; // Current attribute VDouble0 m_statBitOpReduction; // Ops reduced in ConstBitOpTreeVisitor VDouble0 m_statConcatMerge; // Concat merges @@ -945,6 +945,20 @@ class ConstVisitor final : public VNVisitor { // METHODS + void deleteVarScopesUnder(AstNode* subtreep) { + if (!subtreep) return; + if (!m_scopep) return; + std::unordered_set varps; + subtreep->foreachAndNext([&](AstVar* varp) { varps.insert(varp); }); + if (varps.empty()) return; + for (AstVarScope *vscp = m_scopep->varsp(), *nextp; vscp; vscp = nextp) { + nextp = VN_AS(vscp->nextp(), VarScope); + if (varps.find(vscp->varp()) != varps.end()) { + VL_DO_DANGLING(pushDeletep(vscp->unlinkFrBack()), vscp); + } + } + } + V3Number constNumV(AstNode* nodep) { // Contract C width to V width (if needed, else just direct copy) // The upper zeros in the C representation can otherwise cause @@ -2977,14 +2991,9 @@ class ConstVisitor final : public VNVisitor { // UINFOTREE(1, valuep, "", "visitvaref"); iterateAndNextNull(nodep->varp()->valuep()); // May change nodep->varp()->valuep() AstNode* const valuep = nodep->varp()->valuep(); - if (nodep->access().isReadOnly() + if (nodep->access().isReadOnly() && valuep && ((!m_params // Can reduce constant wires into equations - && m_doNConst - && v3Global.opt.fConst() - // Default value, not a "known" constant for this usage - && !nodep->varp()->isClassMember() && !nodep->varp()->sensIfacep() - && !(nodep->varp()->isFuncLocal() && nodep->varp()->isNonOutput()) - && !nodep->varp()->noSubst() && !nodep->varp()->isSigPublic()) + && m_doNConst && v3Global.opt.fConst() && nodep->varp()->isConst()) || nodep->varp()->isParam())) { if (operandConst(valuep)) { const V3Number& num = VN_AS(valuep, Const)->num(); @@ -3031,6 +3040,7 @@ class ConstVisitor final : public VNVisitor { void visit(AstExprStmt* nodep) override { iterateChildren(nodep); if (!AstNode::afterCommentp(nodep->stmtsp())) { + deleteVarScopesUnder(nodep->stmtsp()); UINFO(8, "ExprStmt(...) " << nodep << " " << nodep->resultp()); nodep->replaceWith(nodep->resultp()->unlinkFrBack()); VL_DO_DANGLING(pushDeletep(nodep), nodep); @@ -3315,9 +3325,21 @@ class ConstVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(procp), procp); // Set the initial value right in the variable so we can constant propagate AstNode* const initvaluep = exprp->cloneTree(false); + varrefp->varp()->isConst(true); varrefp->varp()->valuep(initvaluep); } } + void visit(AstCReset* nodep) override { + iterateChildren(nodep); + if (!m_doNConst) return; + const AstBasicDType* const bdtypep = VN_CAST(nodep->dtypep()->skipRefp(), BasicDType); + if (!bdtypep) return; + if (!bdtypep->isZeroInit()) return; + AstConst* const newp = new AstConst{nodep->fileline(), V3Number{nodep, bdtypep}}; + UINFO(9, "CRESET(0) => CONST(0) " << nodep); + nodep->replaceWith(newp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + } void visit(AstCvtArrayToArray* nodep) override { iterateChildren(nodep); // Handle the case where we have a stream operation inside a cast conversion @@ -3395,21 +3417,31 @@ class ConstVisitor final : public VNVisitor { if (m_doNConst) { if (const AstConst* const constp = VN_CAST(nodep->condp(), Const)) { AstNode* keepp = nullptr; + AstNode* delp = nullptr; if (constp->isZero()) { UINFO(4, "IF(0,{any},{x}) => {x}: " << nodep); keepp = nodep->elsesp(); + delp = nodep->thensp(); } else if (!m_doV || constp->isNeqZero()) { // Might be X in Verilog UINFO(4, "IF(!0,{x},{any}) => {x}: " << nodep); keepp = nodep->thensp(); + delp = nodep->elsesp(); } else { UINFO(4, "IF condition is X, retaining: " << nodep); return; } + + // If we delete a branch that contains variable declarations, also delete the + // corresponding varscopes so we don't leave dangling AstVarScope::m_varp pointers. + deleteVarScopesUnder(delp); + if (keepp) { keepp->unlinkFrBackWithNext(); nodep->replaceWith(keepp); } else { nodep->unlinkFrBack(); + deleteVarScopesUnder(nodep->thensp()); + deleteVarScopesUnder(nodep->elsesp()); } VL_DO_DANGLING(pushDeletep(nodep), nodep); diff --git a/src/V3Const.h b/src/V3Const.h index 90178ec05..ef6be2ef7 100644 --- a/src/V3Const.h +++ b/src/V3Const.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Control.cpp b/src/V3Control.cpp index 412076fef..bb0eb6821 100644 --- a/src/V3Control.cpp +++ b/src/V3Control.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2010-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -466,7 +466,7 @@ public: IgnIndices data; std::vector> points = {{10, 10}, {20, 20}, {40, 40}, {10, 30}, {20, 40}}; - for (auto& it : points) { + for (const auto& it : points) { controlIgnLines.emplace_back( V3ControlIgnoresLine{V3ErrorCode::I_LINT, it.first, it.second, true}); data.emplace_back(static_cast(controlIgnLines.size() - 1)); @@ -514,7 +514,7 @@ public: UASSERT_SELFTEST(int, nextChange, std::numeric_limits::max()); // points = {{0, 0}}; - for (auto& it : points) { + for (const auto& it : points) { controlIgnLines.emplace_back( V3ControlIgnoresLine{V3ErrorCode::I_LINT, it.first, it.second, true}); data.emplace_back(static_cast(controlIgnLines.size() - 1)); diff --git a/src/V3Control.h b/src/V3Control.h index 42f4c1053..c5424a85b 100644 --- a/src/V3Control.h +++ b/src/V3Control.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2010-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp index f1f6285a7..ccb3c9326 100644 --- a/src/V3Coverage.cpp +++ b/src/V3Coverage.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Coverage.h b/src/V3Coverage.h index 6adf52bb7..97a7ad486 100644 --- a/src/V3Coverage.h +++ b/src/V3Coverage.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3CoverageJoin.cpp b/src/V3CoverageJoin.cpp index 47f8904c9..e27c5ed9e 100644 --- a/src/V3CoverageJoin.cpp +++ b/src/V3CoverageJoin.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3CoverageJoin.h b/src/V3CoverageJoin.h index fe543a0cd..9a676e9fe 100644 --- a/src/V3CoverageJoin.h +++ b/src/V3CoverageJoin.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Dead.cpp b/src/V3Dead.cpp index 12db25105..d5392d69f 100644 --- a/src/V3Dead.cpp +++ b/src/V3Dead.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -81,7 +81,7 @@ class DeadVisitor final : public VNVisitor { bool m_inAssign = false; // Currently in an assign AstNodeDType* m_curDTypep = nullptr; // Current NodeDType AstNodeModule* m_modp = nullptr; // Current module - AstSelLoopVars* m_selloopvarsp = nullptr; // Current loop vars + AstForeachHeader* m_foreachHeaderp = nullptr; // Current foreach header // STATE - Statistic tracking VDouble0 m_statFTasksDeadified; @@ -268,10 +268,10 @@ class DeadVisitor final : public VNVisitor { } checkAll(nodep); } - void visit(AstSelLoopVars* nodep) override { - // Var under a SelLoopVars means we haven't called V3Width to remove them yet - VL_RESTORER(m_selloopvarsp); - m_selloopvarsp = nodep; + void visit(AstForeachHeader* nodep) override { + // Var under a ForeachHeader means we haven't called V3Width to remove them yet + VL_RESTORER(m_foreachHeaderp); + m_foreachHeaderp = nodep; iterateChildren(nodep); checkAll(nodep); } @@ -292,9 +292,12 @@ class DeadVisitor final : public VNVisitor { void visit(AstVar* nodep) override { iterateChildren(nodep); checkAll(nodep); - if (nodep->isSigPublic() && m_modp && VN_IS(m_modp, Package)) m_modp->user1Inc(); - if (m_selloopvarsp) nodep->user1Inc(); - if (mightElimVar(nodep)) m_varsp.push_back(nodep); + if (m_foreachHeaderp) nodep->user1Inc(); + if (mightElimVar(nodep)) { + m_varsp.push_back(nodep); + } else { + if (m_modp && VN_IS(m_modp, Package)) m_modp->user1Inc(); + } } void visit(AstNodeAssign* nodep) override { // See if simple assignments to variables may be eliminated because diff --git a/src/V3Dead.h b/src/V3Dead.h index 202591654..40a059915 100644 --- a/src/V3Dead.h +++ b/src/V3Dead.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index 958ea69cf..209218b8e 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Delayed.h b/src/V3Delayed.h index 0b65281c1..582d17d47 100644 --- a/src/V3Delayed.h +++ b/src/V3Delayed.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Depth.cpp b/src/V3Depth.cpp index 04d585129..c0c96c594 100644 --- a/src/V3Depth.cpp +++ b/src/V3Depth.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Depth.h b/src/V3Depth.h index 3dd15d920..6e6e49798 100644 --- a/src/V3Depth.h +++ b/src/V3Depth.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DepthBlock.cpp b/src/V3DepthBlock.cpp index 8eea165b6..cf9ad4b7c 100644 --- a/src/V3DepthBlock.cpp +++ b/src/V3DepthBlock.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DepthBlock.h b/src/V3DepthBlock.h index 1f25fef4c..214c5ba48 100644 --- a/src/V3DepthBlock.h +++ b/src/V3DepthBlock.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp index ee957aec8..9511a44e1 100644 --- a/src/V3Descope.cpp +++ b/src/V3Descope.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Descope.h b/src/V3Descope.h index 21da1fcbd..2faaccced 100644 --- a/src/V3Descope.h +++ b/src/V3Descope.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Dfg.cpp b/src/V3Dfg.cpp index 786d63e7e..2176ea60b 100644 --- a/src/V3Dfg.cpp +++ b/src/V3Dfg.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -288,6 +288,12 @@ static void dumpDotVertex(std::ostream& os, const DfgVertex& vtx) { os << '\n'; varVtxp->dtype().astDtypep()->dumpSmall(os); os << " / F" << varVtxp->fanout(); + // Reference flags + os << " / "; + static const char* const rwmn[2][2] = {{"_", "W"}, {"R", "M"}}; + os << rwmn[varVtxp->hasExtRdRefs()][varVtxp->hasExtWrRefs()]; + os << rwmn[varVtxp->hasModRdRefs()][varVtxp->hasModWrRefs()]; + os << (varVtxp->hasDfgRefs() ? "D" : "_"); // End 'label' os << '"'; // Shape diff --git a/src/V3Dfg.h b/src/V3Dfg.h index 241de27c6..13e1e5f1a 100644 --- a/src/V3Dfg.h +++ b/src/V3Dfg.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgAstToDfg.cpp b/src/V3DfgAstToDfg.cpp index 2ca7e820e..52f2aec74 100644 --- a/src/V3DfgAstToDfg.cpp +++ b/src/V3DfgAstToDfg.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -205,7 +205,11 @@ class AstToDfgVisitor final : public VNVisitor { // Can only handle combinational logic if (nodep->sentreep()) return false; - if (kwd != VAlwaysKwd::ALWAYS && kwd != VAlwaysKwd::ALWAYS_COMB) return false; + if (kwd != VAlwaysKwd::ALWAYS // + && kwd != VAlwaysKwd::ALWAYS_COMB // + && kwd != VAlwaysKwd::CONT_ASSIGN) { + return false; + } // Potentially convertible block ++m_ctx.m_inputs; diff --git a/src/V3DfgBreakCycles.cpp b/src/V3DfgBreakCycles.cpp index 8b402e173..f44501606 100644 --- a/src/V3DfgBreakCycles.cpp +++ b/src/V3DfgBreakCycles.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgCache.cpp b/src/V3DfgCache.cpp index 3f6cdbd59..83730f789 100644 --- a/src/V3DfgCache.cpp +++ b/src/V3DfgCache.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgCache.h b/src/V3DfgCache.h index 8bff16c03..010605151 100644 --- a/src/V3DfgCache.h +++ b/src/V3DfgCache.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgColorSCCs.cpp b/src/V3DfgColorSCCs.cpp index 617726381..b1ca2bb05 100644 --- a/src/V3DfgColorSCCs.cpp +++ b/src/V3DfgColorSCCs.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgContext.h b/src/V3DfgContext.h index e6c7075a1..97c6e9659 100644 --- a/src/V3DfgContext.h +++ b/src/V3DfgContext.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -171,6 +171,22 @@ private: V3DfgPeepholeContext(V3DfgContext& ctx, const std::string& label) VL_MT_DISABLED; ~V3DfgPeepholeContext() VL_MT_DISABLED; }; +class V3DfgPushDownSelsContext final : public V3DfgSubContext { + // Only V3DfgContext can create an instance + friend class V3DfgContext; + +public: + // STATE + size_t m_pushedDown = 0; // Number of selects pushed down through concatenations + size_t m_wouldBeCyclic = 0; // Number of selects not pushed due to cycle +private: + V3DfgPushDownSelsContext(V3DfgContext& ctx, const std::string& label) + : V3DfgSubContext{ctx, label, "PushDownSels"} {} + ~V3DfgPushDownSelsContext() { + addStat("sels pushed down", m_pushedDown); + addStat("would be cyclic", m_wouldBeCyclic); + } +}; class V3DfgRegularizeContext final : public V3DfgSubContext { // Only V3DfgContext can create an instance friend class V3DfgContext; @@ -200,6 +216,27 @@ private: addStat("temporaries introduced", m_temporariesIntroduced); } }; +class V3DfgRemoveUnobservableContext final : public V3DfgSubContext { + // Only V3DfgContext can create an instance + friend class V3DfgContext; + +public: + // STATE + VDouble0 m_varsRemoved; // Number of variables removed from the Dfg + VDouble0 m_varsDeleted; // Number of variables removed from the Dfg and the Ast + VDouble0 m_logicRemoved; // Number of logic blocks removed from the Dfg + VDouble0 m_logicDeleted; // Number of logic blocks removed from the Dfg and the Ast + +private: + V3DfgRemoveUnobservableContext(V3DfgContext& ctx, const std::string& label) + : V3DfgSubContext{ctx, label, "RemoveUnobservable"} {} + ~V3DfgRemoveUnobservableContext() { + addStat("variables removed", m_varsRemoved); + addStat("variables deleted", m_varsDeleted); + addStat("logic removed", m_logicRemoved); + addStat("logic deleted", m_logicDeleted); + } +}; class V3DfgSynthesisContext final : public V3DfgSubContext { // Only V3DfgContext can create an instance friend class V3DfgContext; @@ -348,7 +385,9 @@ public: V3DfgCseContext m_cseContext1{*this, m_label + " 2nd"}; V3DfgDfgToAstContext m_dfg2AstContext{*this, m_label}; V3DfgPeepholeContext m_peepholeContext{*this, m_label}; + V3DfgPushDownSelsContext m_pushDownSelsContext{*this, m_label}; V3DfgRegularizeContext m_regularizeContext{*this, m_label}; + V3DfgRemoveUnobservableContext m_removeUnobservableContext{*this, m_label}; V3DfgSynthesisContext m_synthContext{*this, m_label}; // Node pattern collector diff --git a/src/V3DfgCse.cpp b/src/V3DfgCse.cpp index 35aaedfb8..b1f9241e5 100644 --- a/src/V3DfgCse.cpp +++ b/src/V3DfgCse.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgDataType.cpp b/src/V3DfgDataType.cpp index 1c83a4447..2b16ccdf4 100644 --- a/src/V3DfgDataType.cpp +++ b/src/V3DfgDataType.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgDataType.h b/src/V3DfgDataType.h index 9a2ed59df..6fbf6d382 100644 --- a/src/V3DfgDataType.h +++ b/src/V3DfgDataType.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgDecomposition.cpp b/src/V3DfgDecomposition.cpp index 03cc42229..51bcd0faf 100644 --- a/src/V3DfgDecomposition.cpp +++ b/src/V3DfgDecomposition.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgDfgToAst.cpp b/src/V3DfgDfgToAst.cpp index 6edefe7c1..2aadb02fb 100644 --- a/src/V3DfgDfgToAst.cpp +++ b/src/V3DfgDfgToAst.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgOptimizer.cpp b/src/V3DfgOptimizer.cpp index 7cc251bb4..682008412 100644 --- a/src/V3DfgOptimizer.cpp +++ b/src/V3DfgOptimizer.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -204,6 +204,7 @@ class DataflowExtractVisitor final : public VNVisitor { } void visit(AstNodeExpr* nodep) override { iterateChildrenConst(nodep); } + void visit(AstArg* nodep) override { iterateChildrenConst(nodep); } void visit(AstNodeVarRef* nodep) override { if (nodep->access().isWriteOrRW()) { @@ -218,8 +219,7 @@ class DataflowExtractVisitor final : public VNVisitor { } void visit(AstNode* nodep) override { - // Conservatively assume unhandled nodes are impure. This covers all AstNodeFTaskRef - // as AstNodeFTaskRef are sadly not AstNodeExpr. + // Conservatively assume unhandled nodes are impure. m_impure = true; // Still need to gather all references/force/release, etc. iterateChildrenConst(nodep); @@ -314,6 +314,10 @@ class DataflowOptimize final { // Dump the initial graph for debugging if (dumpDfgLevel() >= 8) dfg.dumpDotFilePrefixed(m_ctx.prefix() + "dfg-in"); + // Remove unobservable variabels and logic that drives only such variables + V3DfgPasses::removeUnobservable(dfg, m_ctx); + if (dumpDfgLevel() >= 8) dfg.dumpDotFilePrefixed(m_ctx.prefix() + "pruned"); + // Synthesize DfgLogic vertices V3DfgPasses::synthesize(dfg, m_ctx); if (dumpDfgLevel() >= 8) dfg.dumpDotFilePrefixed(m_ctx.prefix() + "synth"); diff --git a/src/V3DfgOptimizer.h b/src/V3DfgOptimizer.h index 4fe050b9a..a5256b213 100644 --- a/src/V3DfgOptimizer.h +++ b/src/V3DfgOptimizer.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgPasses.cpp b/src/V3DfgPasses.cpp index cd62d069e..dff67fc6d 100644 --- a/src/V3DfgPasses.cpp +++ b/src/V3DfgPasses.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -25,6 +25,82 @@ VL_DEFINE_DEBUG_FUNCTIONS; +void V3DfgPasses::removeUnobservable(DfgGraph& dfg, V3DfgContext& dfgCtx) { + V3DfgRemoveUnobservableContext& ctx = dfgCtx.m_removeUnobservableContext; + + // Enqueue all DfgLogic vertices to work list + DfgWorklist workList{dfg}; + for (DfgVertex& vtx : dfg.opVertices()) { + if (vtx.is()) workList.push_front(vtx); + } + + // Remove all logic that only drives unobservable variables + workList.foreach([&](DfgVertex& vtx) { + DfgLogic* const logicp = vtx.as(); + // Check all variables driven by this logic are removable + bool used = logicp->foreachSink([&](DfgVertex& snk) { + DfgUnresolved* const uVtxp = snk.as(); + DfgVertexVar* const vVtxp = uVtxp->firtsSinkp()->as(); + if (vVtxp->hasSinks()) return true; + if (vVtxp->isObserved()) return true; + return false; + }); + // If some are used, the logic must stay in the Ast + if (used) return; + // If impure, it must stay in the Ast + if (!logicp->isPure()) return; + // Enqueue logic driving the inputs of this logic we are about to delete + logicp->foreachSource([&](DfgVertex& src) { + DfgVertexVar* const varp = src.as(); + if (!varp->srcp()) return false; + varp->srcp()->as()->foreachSource([&](DfgVertex& driver) { + workList.push_front(*driver.as()); + return false; + }); + return false; + }); + // Delete this logic both from the Dfg and the Ast + AstNode* const nodep = logicp->nodep(); + VL_DO_DANGLING(logicp->unlinkDelete(dfg), logicp); + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); + ++ctx.m_logicDeleted; + }); + + // Remove unobservable variables + for (DfgVertexVar* const vVtxp : dfg.varVertices().unlinkable()) { + if (vVtxp->hasSinks()) continue; + if (vVtxp->isObserved()) continue; + DfgVertex* const srcp = vVtxp->srcp(); // Must be a DfgUnresolved or nullptr + AstNode* const varp = vVtxp->nodep(); + // Can delete the Ast variable too if it has no other references + const bool delAst = (!srcp || !srcp->nInputs()) // + && !vVtxp->hasExtWrRefs() // + && !vVtxp->hasModWrRefs(); + VL_DO_DANGLING(vVtxp->unlinkDelete(dfg), vVtxp); + if (srcp) VL_DO_DANGLING(srcp->unlinkDelete(dfg), srcp); + if (delAst) { + VL_DO_DANGLING(varp->unlinkFrBack()->deleteTree(), varp); + ++ctx.m_varsDeleted; + } else { + ++ctx.m_varsRemoved; + } + } + + // Finally remove logic from the Dfg if it drives no variables in the graph. + // These should only be those with side effects. + for (DfgVertex* const vtxp : dfg.opVertices().unlinkable()) { + if (!vtxp->is()) continue; + if (vtxp->hasSinks()) continue; + // Input variables will be read in Ast code, mark as such + vtxp->foreachSource([](DfgVertex& src) { + src.as()->setHasModRdRefs(); + return false; + }); + VL_DO_DANGLING(vtxp->unlinkDelete(dfg), vtxp); + ++ctx.m_logicRemoved; + } +} + void V3DfgPasses::inlineVars(DfgGraph& dfg) { for (DfgVertexVar& vtx : dfg.varVertices()) { // Nothing to inline it into @@ -178,7 +254,7 @@ void V3DfgPasses::binToOneHot(DfgGraph& dfg, V3DfgBinToOneHotContext& ctx) { if (selp->width() != 1) continue; DfgShiftL* const shiftLp = selp->fromp()->cast(); if (!shiftLp) continue; - DfgConst* const constp = shiftLp->lhsp()->cast(); + const DfgConst* const constp = shiftLp->lhsp()->cast(); if (!constp || !useOk(selp, false)) continue; if (!constp->hasValue(1)) continue; srcp = shiftLp->rhsp(); @@ -371,6 +447,10 @@ void V3DfgPasses::optimize(DfgGraph& dfg, V3DfgContext& ctx) { run("cse0 ", dumpLvl >= 4, [&]() { cse(dfg, ctx.m_cseContext0); }); run("binToOneHot ", dumpLvl >= 4, [&]() { binToOneHot(dfg, ctx.m_binToOneHotContext); }); run("peephole ", dumpLvl >= 4, [&]() { peephole(dfg, ctx.m_peepholeContext); }); + // Run only on final scoped DfgGraphs, as otherwise later DfgPeephole wold just undo this work + if (!dfg.modulep()) { + run("pushDownSels", dumpLvl >= 4, [&]() { pushDownSels(dfg, ctx.m_pushDownSelsContext); }); + } run("cse1 ", dumpLvl >= 4, [&]() { cse(dfg, ctx.m_cseContext1); }); run("output ", dumpLvl >= 3, [&]() { /* debug dump only */ }); diff --git a/src/V3DfgPasses.h b/src/V3DfgPasses.h index ccc6e384f..cd184022f 100644 --- a/src/V3DfgPasses.h +++ b/src/V3DfgPasses.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -38,6 +38,9 @@ std::unique_ptr astToDfg(AstModule&, V3DfgContext&) VL_MT_DISABLED; // Same as above, but for the entire netlist, after V3Scope std::unique_ptr astToDfg(AstNetlist&, V3DfgContext&) VL_MT_DISABLED; +// Remove unobservable variabels and logic that drives only such variables +void removeUnobservable(DfgGraph&, V3DfgContext&) VL_MT_DISABLED; + // Synthesize DfgLogic vertices into primitive operations. // Removes all DfgLogic (even those that were not synthesized). void synthesize(DfgGraph&, V3DfgContext&) VL_MT_DISABLED; @@ -76,6 +79,8 @@ uint32_t colorStronglyConnectedComponents(const DfgGraph&, DfgUserMap& void cse(DfgGraph&, V3DfgCseContext&) VL_MT_DISABLED; // Inline fully driven variables void inlineVars(DfgGraph&) VL_MT_DISABLED; +// Push down selects through concatenations +void pushDownSels(DfgGraph& dfg, V3DfgPushDownSelsContext& ctx) VL_MT_DISABLED; // Peephole optimizations void peephole(DfgGraph&, V3DfgPeepholeContext&) VL_MT_DISABLED; // Regularize graph. This must be run before converting back to Ast. diff --git a/src/V3DfgPatternStats.h b/src/V3DfgPatternStats.h index 2c9874922..538d24536 100644 --- a/src/V3DfgPatternStats.h +++ b/src/V3DfgPatternStats.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgPeephole.cpp b/src/V3DfgPeephole.cpp index f0a19769e..ae4cb85e7 100644 --- a/src/V3DfgPeephole.cpp +++ b/src/V3DfgPeephole.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -30,6 +30,7 @@ #include "V3Stats.h" #include +#include VL_DEFINE_DEBUG_FUNCTIONS; @@ -149,11 +150,7 @@ class V3DfgPeephole final : public DfgVisitor { return true; } - void addToWorkList(DfgVertex* vtxp) { - // We only process actual operation vertices - if (vtxp->is() || vtxp->is()) return; - m_workList.push_front(*vtxp); - } + void addToWorkList(DfgVertex* vtxp) { m_workList.push_front(*vtxp); } void addSourcesToWorkList(DfgVertex* vtxp) { vtxp->foreachSource([&](DfgVertex& src) { @@ -178,10 +175,17 @@ class V3DfgPeephole final : public DfgVisitor { // Otherwise we can delete it now. // Remove from cache m_cache.invalidateByValue(vtxp); + // This pass only removes variables that are either not driven in this graph, + // or are not observable outside the graph. If there is also no external write + // to the variable and no references in other graph then delete the Ast var too. + const DfgVertexVar* const varp = vtxp->cast(); + AstNode* const nodep + = varp && !varp->isVolatile() && !varp->hasDfgRefs() ? varp->nodep() : nullptr; // Should not have sinks UASSERT_OBJ(!vtxp->hasSinks(), vtxp, "Should not delete used vertex"); - // + // Delete vertex and Ast variable if any VL_DO_DANGLING(vtxp->unlinkDelete(m_dfg), vtxp); + if (nodep) VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } void replace(DfgVertex* vtxp, DfgVertex* replacementp) { @@ -800,29 +804,6 @@ class V3DfgPeephole final : public DfgVisitor { DfgSel* const replacementp = make(vtxp, lhsp, lsb - rhsp->width()); replace(vtxp, replacementp); } - } else if (!concatp->hasMultipleSinks()) { - // If the select straddles both sides, the Concat has no other use, - // then push the Sel past the Concat - APPLYING(PUSH_SEL_THROUGH_CONCAT) { - const uint32_t rSelWidth = rhsp->width() - lsb; - const uint32_t lSelWidth = width - rSelWidth; - - // The new Lhs vertex - DfgSel* const newLhsp - = make(flp, DfgDataType::packed(lSelWidth), lhsp, 0U); - - // The new Rhs vertex - DfgSel* const newRhsp - = make(flp, DfgDataType::packed(rSelWidth), rhsp, lsb); - - // The replacement Concat vertex - DfgConcat* const newConcat - = make(concatp->fileline(), vtxp->dtype(), newLhsp, newRhsp); - - // Replace this vertex - replace(vtxp, newConcat); - return; - } } } @@ -921,12 +902,9 @@ class V3DfgPeephole final : public DfgVisitor { if (replacementp) { // Replace with sel from driver APPLYING(PUSH_SEL_THROUGH_SPLICE) { + addToWorkList(varp); // In case it became redundant and can be removed replace(vtxp, replacementp); - // Special case just for this pattern: delete temporary if became unsued - if (!varp->hasSinks() && !varp->hasDfgRefs()) { - addToWorkList(splicep); // So it can be delete itself if unused - VL_DO_DANGLING(varp->unlinkDelete(m_dfg), varp); // Delete it - } + return; } } } @@ -1327,6 +1305,115 @@ class V3DfgPeephole final : public DfgVisitor { } } } + + if (DfgConst* const lConstp = lhsp->cast()) { + if (DfgCond* const rCondp = rhsp->cast()) { + if (!rCondp->hasMultipleSinks()) { + DfgVertex* const rtVtxp = rCondp->thenp(); + DfgVertex* const reVtxp = rCondp->elsep(); + APPLYING(PUSH_CONCAT_THROUGH_COND_LHS) { + DfgConcat* const thenp + = make(rtVtxp->fileline(), vtxp->dtype(), lConstp, rtVtxp); + DfgConcat* const elsep + = make(reVtxp->fileline(), vtxp->dtype(), lConstp, reVtxp); + DfgCond* const replacementp + = make(vtxp, rCondp->condp(), thenp, elsep); + replace(vtxp, replacementp); + return; + } + } + } + } + + if (DfgConst* const rConstp = rhsp->cast()) { + if (DfgCond* const lCondp = lhsp->cast()) { + if (!lCondp->hasMultipleSinks()) { + DfgVertex* const ltVtxp = lCondp->thenp(); + DfgVertex* const leVtxp = lCondp->elsep(); + APPLYING(PUSH_CONCAT_THROUGH_COND_RHS) { + DfgConcat* const thenp + = make(ltVtxp->fileline(), vtxp->dtype(), ltVtxp, rConstp); + DfgConcat* const elsep + = make(leVtxp->fileline(), vtxp->dtype(), leVtxp, rConstp); + DfgCond* const replacementp + = make(vtxp, lCondp->condp(), thenp, elsep); + replace(vtxp, replacementp); + return; + } + } + } + } + + // Attempt to narrow a concatenation that produces unused bits on the edges + { + const uint32_t vMsb = vtxp->width() - 1; // MSB of the concatenation + const uint32_t lLsb = vtxp->rhsp()->width(); // LSB of the LHS + const uint32_t rMsb = lLsb - 1; // MSB of the RHS + // Check each sink, and record the range of bits used by them + uint32_t lsb = vMsb; // LSB used by a sink + uint32_t msb = 0; // MSB used by a sink + std::vector sinkps; + bool hasCrossSink = false; // True if some sinks use bits from both sides + vtxp->foreachSink([&](DfgVertex& sink) { + sinkps.emplace_back(&sink); + // Record bits used by DfgSel sinks + if (const DfgSel* const selp = sink.cast()) { + const uint32_t selLsb = selp->lsb(); + const uint32_t selMsb = selLsb + selp->width() - 1; + lsb = std::min(lsb, selLsb); + msb = std::max(msb, selMsb); + hasCrossSink |= selMsb >= lLsb && rMsb >= selLsb; + return false; + } + // Ignore non observable variable sinks. These will be eliminated. + if (const DfgVarPacked* const varp = sink.cast()) { + if (!varp->hasSinks() && !varp->isObserved()) return false; + } + // Otherwise the whole value is used + lsb = 0; + msb = vMsb; + return true; + }); + // If not all bits are used, narrow the concatenation, but only if at least + // one select straddles both sides (DfgSel paterns will handle the rest). + if ((vMsb > msb || lsb > 0) && hasCrossSink) { + APPLYING(NARROW_CONCAT) { + FileLine* const flp = vtxp->fileline(); + + // Compute new RHS + DfgVertex* const rhsp = vtxp->rhsp(); + const uint32_t rWidth = rMsb - lsb + 1; + DfgVertex* const newRhsp + = rWidth == rhsp->width() + ? rhsp + : make(flp, DfgDataType::packed(rWidth), rhsp, lsb); + + // Compute new LHS + DfgVertex* const lhsp = vtxp->lhsp(); + const uint32_t lWidth = msb - lLsb + 1; + DfgVertex* const newLhsp + = lWidth == lhsp->width() + ? lhsp + : make(flp, DfgDataType::packed(lWidth), lhsp, 0); + + // Create the new concatenation + DfgConcat* const newConcat = make( + flp, DfgDataType::packed(msb - lsb + 1), newLhsp, newRhsp); + + // Replace Sel sinks + for (DfgVertex* const sinkp : sinkps) { + if (DfgSel* const selp = sinkp->cast()) { + replace(selp, make(selp, newConcat, selp->lsb() - lsb)); + } + } + // Also need to replace the concatenation itself, otherwise this pattern + // will match again and iteration won't terminate. This vertex is now + // effectively unused, so replace with zero. + replace(vtxp, makeZero(flp, vtxp->width())); + return; + } + } + } } void visit(DfgDiv* vtxp) override { @@ -1474,6 +1561,43 @@ class V3DfgPeephole final : public DfgVisitor { void visit(DfgShiftL* vtxp) override { if (foldBinary(vtxp)) return; if (optimizeShiftRHS(vtxp)) return; + + DfgVertex* const lhsp = vtxp->lhsp(); + DfgVertex* const rhsp = vtxp->rhsp(); + + if (DfgConst* const rConstp = rhsp->cast()) { + if (DfgConcat* const lConcatp = lhsp->cast()) { + if (!lConcatp->hasMultipleSinks() + && lConcatp->lhsp()->width() == rConstp->toU32()) { + APPLYING(REPLACE_SHIFTL_CAT) { + DfgConcat* const replacementp = make( + vtxp, lConcatp->rhsp(), + makeZero(lConcatp->fileline(), lConcatp->lhsp()->width())); + replace(vtxp, replacementp); + return; + } + } + } + + if (DfgShiftR* const lShiftRp = lhsp->cast()) { + if (!lShiftRp->hasMultipleSinks() && isSame(rConstp, lShiftRp->rhsp())) { + if (DfgConcat* const llConcatp = lShiftRp->lhsp()->cast()) { + const uint32_t shiftAmount = rConstp->toU32(); + if (!llConcatp->hasMultipleSinks() + && llConcatp->rhsp()->width() == shiftAmount) { + APPLYING(REPLACE_SHIFTRL_CAT) { + DfgConst* const zerop + = makeZero(llConcatp->fileline(), shiftAmount); + DfgConcat* const replacementp + = make(vtxp, llConcatp->lhsp(), zerop); + replace(vtxp, replacementp); + return; + } + } + } + } + } + } } void visit(DfgShiftR* vtxp) override { @@ -1689,22 +1813,58 @@ class V3DfgPeephole final : public DfgVisitor { } } + void visit(DfgVertexVar* vtxp) override { + if (vtxp->hasSinks()) return; + if (vtxp->isObserved()) return; + if (vtxp->defaultp()) return; + + // If undriven, or driven from another var, it is completely redundant. + if (!vtxp->srcp() || vtxp->srcp()->is()) { + APPLYING(REMOVE_VAR) { + deleteVertex(vtxp); + return; + } + } + + // Otherwise remove if there is only one sink that is not a removable variable + bool foundOne = false; + const bool keep = vtxp->srcp()->foreachSink([&](DfgVertex& sink) { + // Ignore non observable variable sinks. These can be eliminated. + if (const DfgVertexVar* const varp = sink.cast()) { + if (!varp->hasSinks() && !varp->isObserved()) return false; + } + if (foundOne) return true; + foundOne = true; + return false; + }); + if (!keep) { + APPLYING(REMOVE_VAR) { + deleteVertex(vtxp); + return; + } + } + } + #undef APPLYING V3DfgPeephole(DfgGraph& dfg, V3DfgPeepholeContext& ctx) : m_dfg{dfg} , m_ctx{ctx} { + // Add all variable vertices to the work list. Do this first so they are processed last. + // This order has a better chance of preserving original variables in case they are needed. + for (DfgVertexVar& vtx : m_dfg.varVertices()) addToWorkList(&vtx); + // Add all operation vertices to the work list and cache for (DfgVertex& vtx : m_dfg.opVertices()) { - m_workList.push_front(vtx); + addToWorkList(&vtx); m_cache.cache(&vtx); } // Process the work list m_workList.foreach([&](DfgVertex& vtx) { - // Remove unused vertices as we go - if (!vtx.hasSinks()) { + // Remove unused operations as we go. Some vars may be removed in the visit method. + if (!vtx.hasSinks() && !vtx.is()) { deleteVertex(&vtx); return; } diff --git a/src/V3DfgPeepholePatterns.h b/src/V3DfgPeepholePatterns.h index dbb425f96..fd0711e0c 100644 --- a/src/V3DfgPeepholePatterns.h +++ b/src/V3DfgPeepholePatterns.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -35,15 +35,17 @@ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, FOLD_UNARY) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, INLINE_ARRAYSEL_SPLICE) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, INLINE_ARRAYSEL_UNIT) \ + _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, NARROW_CONCAT) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PULL_NOTS_THROUGH_COND) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_BITWISE_OP_THROUGH_CONCAT) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_BITWISE_THROUGH_REDUCTION) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_COMPARE_OP_THROUGH_CONCAT) \ + _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_CONCAT_THROUGH_COND_LHS) \ + _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_CONCAT_THROUGH_COND_RHS) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_CONCAT_THROUGH_NOTS) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_NOT_THROUGH_COND) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_REDUCTION_THROUGH_CONCAT) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_REDUCTION_THROUGH_COND_WITH_CONST_BRANCH) \ - _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_SEL_THROUGH_CONCAT) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_SEL_THROUGH_COND) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_SEL_THROUGH_NOT) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, PUSH_SEL_THROUGH_REPLICATE) \ @@ -64,6 +66,7 @@ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REMOVE_SEL_FROM_LHS_OF_CONCAT) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REMOVE_SEL_FROM_RHS_OF_CONCAT) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REMOVE_SUB_ZERO) \ + _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REMOVE_VAR) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REMOVE_WIDTH_ONE_REDUCTION) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REMOVE_XOR_WITH_ZERO) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REPLACE_AND_OF_NOT_AND_NEQ) \ @@ -96,6 +99,8 @@ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REPLACE_OR_OF_NOT_AND_NOT) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REPLACE_OR_WITH_ONES) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REPLACE_SEL_FROM_SEL) \ + _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REPLACE_SHIFTL_CAT) \ + _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REPLACE_SHIFTRL_CAT) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REPLACE_SUB_WITH_NOT) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REPLACE_TAUTOLOGICAL_OR) \ _FOR_EACH_DFG_PEEPHOLE_OPTIMIZATION_APPLY(macro, REPLACE_TAUTOLOGICAL_OR_3) \ diff --git a/src/V3DfgPushDownSels.cpp b/src/V3DfgPushDownSels.cpp new file mode 100644 index 000000000..a784ad874 --- /dev/null +++ b/src/V3DfgPushDownSels.cpp @@ -0,0 +1,395 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Push DfgSels through DfgConcat to avoid temporaries +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* +// +// If a DfgConcat drives both a DfgSel and a DfgConcat, and would othersiwe +// not need a temporary, then push the DfgSel down to the lower DfgConcat. +// This avoids having to insert a temporary for many intermediate results. +// +// We need to be careful not to create a cycle by pushing down a DfgSel +// that in turn feeds the concat it is being redirected to. To handle this, +// we use the Pierce-Kelly algorithm to check if a cycle would be created by +// adding a new edge. See: "A Dynamic Topological Sort Algorithm for +// Directed Acyclic Graphs", David J. Pearce, Paul H.J. Kelly, 2007 +// +//************************************************************************* + +#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT + +#include "V3Dfg.h" +#include "V3DfgPasses.h" +#include "V3Error.h" + +VL_DEFINE_DEBUG_FUNCTIONS; + +class V3DfgPushDownSels final { + // TYPES + + // Each vertex has an associated State via DfgUserMap + struct State final { + // -- For Pearce-Kelly algorithm only + // Topological ordering index. For all pair of vertices (a, b), + // ord(a) < ord(b) iff there is no path from b to a in the graph. + uint32_t ord = 0; + bool visited = false; // Whether the vertex has been visited during DFS + // -- For the actial optimization only management + bool onWorklist = false; // Whether the vertex is in m_catps + }; + + // STATE + // The graph being processed - must be acyclic (DAG) + DfgGraph& m_dfg; + // Context for pass + V3DfgPushDownSelsContext& m_ctx; + // Map from DfgVertex to State + DfgUserMap m_stateMap = m_dfg.makeUserMap(); + + // STATE - Temporaries for Pearce-Kelly algorithm - as members to avoid reallocations + std::vector m_stack; // DFS stack for various steps + std::vector m_fwdVtxps; // Vertices found during forward DFS + std::vector m_bwdVtxps; // Vertices found during backward DFS - also work buffer + std::vector m_ords; // Ordering numbers reassigned in current ordering update + + // STATE - For vertex movement + std::vector m_catps; // DfgConcat vertices that may be optimizable + + // METHODS - Pearce-Kelly algorithm + void debugCheck() { + if (VL_LIKELY(!v3Global.opt.debugCheck())) return; + m_dfg.forEachVertex([&](const DfgVertex& src) { + const State& srcState = m_stateMap[src]; + UASSERT_OBJ(!srcState.visited, &src, "Visit marker not reset"); + UASSERT_OBJ(srcState.ord > 0, &src, "No ordering assigned"); + src.foreachSink([&](const DfgVertex& dst) { + const State& dstState = m_stateMap[dst]; + UASSERT_OBJ(srcState.ord < dstState.ord, &src, "Invalid ordering"); + return false; + }); + }); + } + + // Find initial topological ordering using reverse post order numbering via DFS + void initializeOrdering() { + // Start from all vertices with no inputs + m_stack.reserve(m_dfg.size()); + for (DfgVertexVar& vtx : m_dfg.varVertices()) { + if (vtx.srcp() || vtx.defaultp()) continue; + m_stack.push_back(&vtx); + } + for (DfgConst& vtx : m_dfg.constVertices()) m_stack.push_back(&vtx); + + // Reverse post order number to assign to next vertex + uint32_t rpoNext = m_dfg.size(); + + // DFS loop + while (!m_stack.empty()) { + DfgVertex& vtx = *m_stack.back(); + State& vtxState = m_stateMap[vtx]; + // If the ordering already assigned, just pop. It was visited + // through another path through a different child. + if (vtxState.ord) { + UASSERT_OBJ(vtxState.visited, &vtx, "Not visited, but ordering assigned"); + m_stack.pop_back(); + continue; + } + // When exiting a vertex, assign the reverse post order number as ordering + if (vtxState.visited) { + vtxState.ord = rpoNext--; + m_stack.pop_back(); + continue; + } + // Entering vertex. Enqueue all unvisited children. + vtxState.visited = true; + vtx.foreachSink([&](DfgVertex& dst) { + const State& dstState = m_stateMap[dst]; + if (dstState.visited) return false; + m_stack.push_back(&dst); + return false; + }); + } + + // Should reach exact zero + UASSERT(!rpoNext, "All vertics should have been visited exactly once"); + + // Reset marks + m_dfg.forEachVertex([&](DfgVertex& vtx) { m_stateMap[vtx].visited = false; }); + + // Make sure it's valid + debugCheck(); + } + + // Attempt to add an edge to the graph. Returns false if this would create + // a cycle, and in that case, no state is modified, so it is safe to then + // not add the actual edge. Otherwise returns true and updates state as + // if the edge was indeed added, so caller must add the actual edge. + bool addEdge(DfgVertex& src, DfgVertex& dst) { + UASSERT_OBJ(&src != &dst, &src, "Should be different"); + State& srcState = m_stateMap[src]; + State& dstState = m_stateMap[dst]; + // If 'dst' is after 'src' in the topological ordering, + // then ok to add edge and no need to update the ordering. + if (dstState.ord > srcState.ord) return true; + // Pearce-Kelly dicovery step + if (pkFwdDfs(src, dst)) return false; + pkBwdDfs(src, dst); + // Pearce-Kelly update step + pkReorder(); + return true; + } + + // Pearce-Kelly forward DFS discovery step. Record visited vertices. + // Returns true if a cycle would be created by adding the edge (src, dst). + bool pkFwdDfs(DfgVertex& src, DfgVertex& dst) { + const uint32_t srcOrd = m_stateMap[src].ord; + // DFS forward from dst + m_stack.push_back(&dst); + while (!m_stack.empty()) { + DfgVertex& vtx = *m_stack.back(); + m_stack.pop_back(); + State& vtxState = m_stateMap[vtx]; + + // Ignore if already visited through another path through different sink + if (vtxState.visited) continue; + + // Save vertex, mark visited + m_fwdVtxps.push_back(&vtx); + vtxState.visited = true; + + // Enqueue unvisited sinks in affeced area + const bool cyclic = vtx.foreachSink([&](DfgVertex& sink) { + State& sinkState = m_stateMap[sink]; + if (sinkState.ord == srcOrd) return true; // Stop completely if cyclic + if (sinkState.visited) return false; // Stop search if already visited + if (sinkState.ord > srcOrd) return false; // Stop search if outside critical area + m_stack.push_back(&sink); + return false; + }); + + // If would be cyclic, reset state and return true + if (cyclic) { + for (DfgVertex* const vtxp : m_fwdVtxps) m_stateMap[vtxp].visited = false; + m_fwdVtxps.clear(); + m_stack.clear(); + return true; + } + } + // Won't be cyclic, return false + return false; + } + + // Pearce-Kelly backward DFS discovery step. Record visited vertices. + void pkBwdDfs(DfgVertex& src, DfgVertex& dst) { + const uint32_t dstOrd = m_stateMap[dst].ord; + // DFS backward from src + m_stack.push_back(&src); + while (!m_stack.empty()) { + DfgVertex& vtx = *m_stack.back(); + m_stack.pop_back(); + State& vtxState = m_stateMap[vtx]; + + // Ignore if already visited through another path through different source + if (vtxState.visited) continue; + + // Save vertex, mark visited + m_bwdVtxps.push_back(&vtx); + vtxState.visited = true; + + // Enqueue unvisited sources in affeced area + vtx.foreachSource([&](DfgVertex& source) { + const State& sourceState = m_stateMap[source]; + if (sourceState.visited) return false; // Stop search if already visited + if (sourceState.ord < dstOrd) + return false; // Stop search if outside critical area + m_stack.push_back(&source); + return false; + }); + } + } + + // Pearce-Kelly reorder step + void pkReorder() { + // Sort vertices found during forward and backward search + const auto cmp = [this](const DfgVertex* const ap, const DfgVertex* const bp) { + return m_stateMap[ap].ord < m_stateMap[bp].ord; + }; + std::sort(m_bwdVtxps.begin(), m_bwdVtxps.end(), cmp); + std::sort(m_fwdVtxps.begin(), m_fwdVtxps.end(), cmp); + // Will use m_bwdVtxps for processing to avoid copying. Save the size. + const size_t bwdSize = m_bwdVtxps.size(); + // Append forward vertices to the backward list for processing + m_bwdVtxps.insert(m_bwdVtxps.end(), m_fwdVtxps.begin(), m_fwdVtxps.end()); + // Save the current ordering numbers, reset visitation marks + for (DfgVertex* const vtxp : m_bwdVtxps) { + State& state = m_stateMap[vtxp]; + state.visited = false; + m_ords.push_back(state.ord); + } + // The current ordering numbers are sorted in the two sub lists, merge them + std::inplace_merge(m_ords.begin(), m_ords.begin() + bwdSize, m_ords.end()); + // Assign new ordering + for (size_t i = 0; i < m_ords.size(); ++i) m_stateMap[m_bwdVtxps[i]].ord = m_ords[i]; + // Reset sate + m_fwdVtxps.clear(); + m_bwdVtxps.clear(); + m_ords.clear(); + // Make sure it's valid + debugCheck(); + } + + // METHODS - Vertex processing + + static bool ignoredSink(const DfgVertex& sink) { + // Ignore non observable variable sinks. These will be eliminated. + if (const DfgVarPacked* const varp = sink.cast()) { + if (!varp->hasSinks() && !varp->isObserved()) return true; + } + return false; + } + + // Find all concatenations that feed another concatenation and may be + // optimizable. These are the ones that feed a DfgSel, and no other + // observable sinks. (If there were other observable sinks, a temporary + // would be required anyway.) + void findCandidatess() { + for (DfgVertex& vtx : m_dfg.opVertices()) { + // Consider only concatenations ... + DfgConcat* const catp = vtx.cast(); + if (!catp) continue; + + // Count the various types of sinks + uint32_t nSels = 0; + uint32_t nCats = 0; + uint32_t nOther = 0; + vtx.foreachSink([&](const DfgVertex& sink) { + if (sink.is()) { + ++nSels; + } else if (sink.is()) { + ++nCats; + } else if (!ignoredSink(sink)) { + ++nOther; + } + return false; + }); + + // Consider if optimizable + if (nSels > 0 && nCats == 1 && nOther == 0) { + m_catps.push_back(catp); + m_stateMap[catp].onWorklist = true; + } + } + } + + void pushDownSels() { + // Selects driven by the current vertex. Outside loop to avoid reallocation. + std::vector selps; + selps.reserve(m_dfg.size()); + // Consider each concatenation + while (!m_catps.empty()) { + DfgConcat* const catp = m_catps.back(); + m_catps.pop_back(); + m_stateMap[catp].onWorklist = false; + + // Iterate sinks, collect selects, check if should be optimized + selps.clear(); + DfgVertex* sinkp = nullptr; // The only non DfgSel sink (ignoring some DfgVars) + const bool multipleNonSelSinks = catp->foreachSink([&](DfgVertex& sink) { + // Collect selects + if (DfgSel* const selp = sink.cast()) { + selps.emplace_back(selp); + return false; + } + // Skip ignored sinks + if (ignoredSink(sink)) return false; + // If already found a non DfgSel sink, return true + if (sinkp) return true; + // Save the non DfgSel sink + sinkp = &sink; + return false; + }); + + // It it has multiple non DfgSel sinks, it will need a temporary, so don't bother + if (multipleNonSelSinks) continue; + // We only add DfgConcats to the work list that drive a select. + UASSERT_OBJ(!selps.empty(), catp, "Should have selects"); + // If no other sink, then nothing to do + if (!sinkp) continue; + // If the only other sink is not a concatenation, then nothing to do + DfgConcat* const sinkCatp = sinkp->cast(); + if (!sinkCatp) continue; + + // Ok, we can try to push the selects down to the sink DfgConcat + const uint32_t offset = sinkCatp->rhsp() == catp ? 0 : sinkCatp->rhsp()->width(); + const uint32_t pushedDownBefore = m_ctx.m_pushedDown; + for (DfgSel* const selp : selps) { + // Don't do it if it would create a cycle + if (!addEdge(*sinkCatp, *selp)) { + ++m_ctx.m_wouldBeCyclic; + continue; + } + // Otherwise redirect the select + ++m_ctx.m_pushedDown; + selp->lsb(selp->lsb() + offset); + selp->fromp(sinkCatp); + } + // If we pushed down any selects, then we need to consider the sink concatenation + // again + State& sinkCatState = m_stateMap[sinkCatp]; + if (pushedDownBefore != m_ctx.m_pushedDown && !sinkCatState.onWorklist) { + m_catps.push_back(sinkCatp); + sinkCatState.onWorklist = true; + } + } + } + + // CONSTRUCTOR + V3DfgPushDownSels(DfgGraph& dfg, V3DfgPushDownSelsContext& ctx) + : m_dfg{dfg} + , m_ctx{ctx} { + + // Find optimization candidates + m_catps.reserve(m_dfg.size()); + findCandidatess(); + // Early exit if nothing to do + if (m_catps.empty()) return; + + // Pre-allocate storage + m_stack.reserve(m_dfg.size()); + m_fwdVtxps.reserve(m_dfg.size()); + m_bwdVtxps.reserve(m_dfg.size()); + m_ords.reserve(m_dfg.size()); + + // Initialize topologicel ordering + initializeOrdering(); + + // Sort candidates in topological order so we process them the least amount + std::sort(m_catps.begin(), m_catps.end(), + [this](const DfgConcat* const ap, const DfgConcat* const bp) { + return m_stateMap[ap].ord < m_stateMap[bp].ord; + }); + + // Push selects down to the lowest concatenation + pushDownSels(); + } + +public: + static void apply(DfgGraph& dfg, V3DfgPushDownSelsContext& ctx) { + V3DfgPushDownSels{dfg, ctx}; + } +}; + +void V3DfgPasses::pushDownSels(DfgGraph& dfg, V3DfgPushDownSelsContext& ctx) { + if (!v3Global.opt.fDfgPushDownSels()) return; + V3DfgPushDownSels::apply(dfg, ctx); +} diff --git a/src/V3DfgRegularize.cpp b/src/V3DfgRegularize.cpp index ea5ca2b69..11010f5bb 100644 --- a/src/V3DfgRegularize.cpp +++ b/src/V3DfgRegularize.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DfgSynthesize.cpp b/src/V3DfgSynthesize.cpp index 3a7c7d895..9922e8277 100644 --- a/src/V3DfgSynthesize.cpp +++ b/src/V3DfgSynthesize.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -469,7 +469,8 @@ public: // Convert AstAssign to Dfg, return true if successful. // Fills 'updates' with bindings for assigned variables. bool convert(std::vector>& updates, DfgLogic& vtx, - AstAssign* nodep) { + AstNodeAssign* nodep) { + UASSERT_OBJ(VN_IS(nodep, Assign) || VN_IS(nodep, AssignW), nodep, "Bad NodeAssign"); UASSERT_OBJ(updates.empty(), nodep, "'updates' should be empty"); VL_RESTORER(m_updatesp); VL_RESTORER(m_logicp); @@ -1034,20 +1035,20 @@ class AstToDfgSynthesize final { // Merge 'thenSymTab' into 'elseSymTab' using the given predicate to join values bool joinSymbolTables(SymTab& elseSymTab, DfgVertexVar* predicatep, const SymTab& thenSymTab) { - // Give up if something is not assigned on all paths ... Latch? - if (thenSymTab.size() != elseSymTab.size()) { - ++m_ctx.m_synt.nonSynLatch; - return false; - } + // Any variable that does not have a binding on both paths will be removed. These might be + // temporaries, loop vars, etc used only in one branch. Conversion will fail if the + // variable is actually referenced later. + std::vector toRemove; + // Join each symbol for (std::pair& pair : elseSymTab) { Variable* const varp = pair.first; // Find same variable on the else path - auto it = thenSymTab.find(varp); - // Give up if something is not assigned on all paths ... Latch? + const auto it = thenSymTab.find(varp); + // Record for removal if not assigned on both paths if (it == thenSymTab.end()) { - ++m_ctx.m_synt.nonSynLatch; - return false; + toRemove.emplace_back(varp); + continue; } // Join paths with the predicate DfgVertexVar* const thenp = it->second; @@ -1056,6 +1057,10 @@ class AstToDfgSynthesize final { if (!newp) return false; pair.second = newp; } + + // Remove variables not assigned on both paths + for (Variable* const varp : toRemove) elseSymTab.erase(varp); + // Done return true; } @@ -1311,7 +1316,8 @@ class AstToDfgSynthesize final { std::vector> updates; for (AstNodeStmt* const stmtp : stmtps) { // Regular statements - if (AstAssign* const ap = VN_CAST(stmtp, Assign)) { + AstNodeAssign* const ap = VN_CAST(stmtp, NodeAssign); + if (ap && (VN_IS(ap, Assign) || VN_IS(ap, AssignW))) { // Convert this assignment if (!m_converter.convert(updates, *m_logicp, ap)) { ++m_ctx.m_synt.nonSynConv; @@ -1922,16 +1928,22 @@ static void dfgSelectLogicForSynthesis(DfgGraph& dfg) { }); } - // Synthesize all continuous assignments and simple blocks driving exactly - // one variable. This is approximately the old default behaviour of Dfg. + // Choose some simple special cases to always synthesize for (DfgVertex& vtx : dfg.opVertices()) { DfgLogic* const logicp = vtx.cast(); if (!logicp) continue; + // Blocks corresponding to continuous assignments if (logicp->nodep()->keyword() == VAlwaysKwd::CONT_ASSIGN) { worklist.push_front(*logicp); continue; } const CfgGraph& cfg = logicp->cfg(); + // Straight line code with no branches + if (cfg.nBlocks() == 1) { + worklist.push_front(*logicp); + continue; + } + // Simple blocks driving exactly 1 variable, e.g if (rst) a = b else a = c; if (!logicp->hasMultipleSinks() && cfg.nBlocks() <= 4 && cfg.nEdges() <= 4) { worklist.push_front(*logicp); } diff --git a/src/V3DfgVertices.h b/src/V3DfgVertices.h index 5c3d0c3e0..7a6cc0da6 100644 --- a/src/V3DfgVertices.h +++ b/src/V3DfgVertices.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -140,6 +140,14 @@ public: bool hasExtWrRefs() const { return hasExtWrRefs(nodep()); } bool hasExtRefs() const { return hasExtRdRefs() || hasExtWrRefs(); } + // True iff the value of this variable is read outside this DfgGraph + bool isObserved() const { + // A DfgVarVertex is written in exactly one DfgGraph, and might be read in an arbitrary + // number of other DfgGraphs. If it's driven in this DfgGraph, it's read in others. + if (hasDfgRefs()) return srcp() || defaultp(); + return hasExtRdRefs() || hasModRdRefs(); + } + // The value of this vertex might differ from what is defined by its drivers // 'srcp' and 'defaultp'. That is, it might be assigned, possibly partially, // or abruptly outside the graph, hence it is not equivalent to its 'srcp'. @@ -457,6 +465,7 @@ class DfgLogic final : public DfgVertexVariadic { bool m_selectedForSynthesis = false; // Logic selected for synthesis bool m_nonSynthesizable = false; // Logic is not synthesizeable (by DfgSynthesis) bool m_reverted = false; // Logic was synthesized (in part if non synthesizable) then reverted + mutable uint8_t m_cachedPure = 0; // Cached purity of the logic public: DfgLogic(DfgGraph& dfg, AstAlways* nodep, AstScope* scopep, std::unique_ptr cfgp) @@ -485,6 +494,16 @@ public: void setNonSynthesizable() { m_nonSynthesizable = true; } bool reverted() const { return m_reverted; } void setReverted() { m_reverted = true; } + // Logic has no side-effect, just computes its output variables based on its input variables + bool isPure() const { + if (!m_cachedPure) { + // This is a sledgehamer, but AstNodeStmts don't compute their 'purity' properly, + // not that 'purity' makes sense for statements... We don't call this often and cached. + const bool pure = m_nodep->forall([](AstNode* nodep) { return nodep->isPure(); }); + m_cachedPure = static_cast(pure) | 0x2; + } + return m_cachedPure & 0x01; + } }; class DfgUnresolved final : public DfgVertexVariadic { diff --git a/src/V3DiagSarif.cpp b/src/V3DiagSarif.cpp index 3c6c5f1f6..81307a5f6 100644 --- a/src/V3DiagSarif.cpp +++ b/src/V3DiagSarif.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DiagSarif.h b/src/V3DiagSarif.h index da789e7a3..a57e8e7f1 100644 --- a/src/V3DiagSarif.h +++ b/src/V3DiagSarif.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DupFinder.cpp b/src/V3DupFinder.cpp index 09a47ea6d..68a07be8f 100644 --- a/src/V3DupFinder.cpp +++ b/src/V3DupFinder.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DupFinder.h b/src/V3DupFinder.h index 964cc3ba2..a278369f1 100644 --- a/src/V3DupFinder.h +++ b/src/V3DupFinder.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitC.h b/src/V3EmitC.h index be3d68d8a..922f0f8c1 100644 --- a/src/V3EmitC.h +++ b/src/V3EmitC.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitCBase.cpp b/src/V3EmitCBase.cpp index 352c4581d..667983199 100644 --- a/src/V3EmitCBase.cpp +++ b/src/V3EmitCBase.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -154,6 +154,8 @@ void EmitCBaseVisitorConst::emitCFuncDecl(const AstCFunc* funcp, const AstNodeMo if (funcp->isVirtual()) { UASSERT_OBJ(funcp->isProperMethod(), funcp, "Virtual function is not a proper method"); putns(funcp, "virtual "); + // Intentionally no emit for "override" instead, as clang will then enable warning + // on other methods where virtual vs override is needed, and this is not tracked yet } emitCFuncHeader(funcp, modp, /* withScope: */ false); if (funcp->emptyBody() && !funcp->isLoose() && !cLinkage) { @@ -176,7 +178,7 @@ void EmitCBaseVisitorConst::emitVarDecl(const AstVar* nodep, bool asRef) { } }; - if (nodep->isIO() && nodep->isSc()) { + if (nodep->isPrimaryIO() && nodep->isSc()) { UASSERT_OBJ(basicp, nodep, "Unimplemented: Outputting this data type"); if (nodep->isInout()) { putns(nodep, "sc_core::sc_inout<"); @@ -197,7 +199,7 @@ void EmitCBaseVisitorConst::emitVarDecl(const AstVar* nodep, bool asRef) { if (asRef && refNeedParens) puts(")"); emitDeclArrayBrackets(nodep); puts(";\n"); - } else if (nodep->isIO() && basicp && !basicp->isOpaque()) { + } else if (nodep->isPrimaryIO() && basicp && !basicp->isOpaque()) { if (nodep->isInout()) { putns(nodep, "VL_INOUT"); } else if (nodep->isWritable()) { diff --git a/src/V3EmitCBase.h b/src/V3EmitCBase.h index 521f4e311..236c095c0 100644 --- a/src/V3EmitCBase.h +++ b/src/V3EmitCBase.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitCConstInit.h b/src/V3EmitCConstInit.h index ab88a5332..b18a43e46 100644 --- a/src/V3EmitCConstInit.h +++ b/src/V3EmitCConstInit.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -99,6 +99,11 @@ protected: UASSERT_OBJ(!num.isFourState(), nodep, "4-state value in constant pool"); putns(nodep, num.emitC()); } + void visit(AstUnbounded* nodep) override { + // e.g. when emitting a public parameter's "$" value + // But Unbounded is only special during elaboration, so just use zero + putns(nodep, "0"); + } // Default void visit(AstNode* nodep) override { // LCOV_EXCL_START diff --git a/src/V3EmitCConstPool.cpp b/src/V3EmitCConstPool.cpp index 96954855d..5524230e4 100644 --- a/src/V3EmitCConstPool.cpp +++ b/src/V3EmitCConstPool.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp index 853f0f970..efcf167c4 100644 --- a/src/V3EmitCFunc.cpp +++ b/src/V3EmitCFunc.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -23,6 +23,8 @@ #include #include +VL_DEFINE_DEBUG_FUNCTIONS; + // We use a static char array in VL_VALUE_STRING constexpr int VL_VALUE_STRING_MAX_WIDTH = 8192; @@ -454,21 +456,22 @@ void EmitCFunc::emitCCallArgs(const AstNodeCCall* nodep, const string& selfPoint puts(")"); } -void EmitCFunc::emitDereference(AstNode* nodep, const string& pointer) { +std::string EmitCFunc::dereferenceString(const std::string& pointer) { if (pointer[0] == '(' && pointer[1] == '&') { // remove "address of" followed by immediate dereference // Note: this relies on only the form '(&OBJECT)' being used by Verilator - putns(nodep, pointer.substr(2, pointer.length() - 3)); - puts("."); + return pointer.substr(2, pointer.length() - 3) + '.'; } else { if (pointer == "vlSelf" && m_usevlSelfRef) { - puts("vlSelfRef."); + return "vlSelfRef."; } else { - putns(nodep, pointer); - puts("->"); + return pointer + "->"; } } } +void EmitCFunc::emitDereference(AstNode* nodep, const string& pointer) { + putns(nodep, dereferenceString(pointer)); +} void EmitCFunc::emitCvtPackStr(AstNode* nodep) { if (const AstConst* const constp = VN_CAST(nodep, Const)) { @@ -525,13 +528,16 @@ void EmitCFunc::emitSetVarConstant(const string& assignString, AstConst* constp) puts(";\n"); } -void EmitCFunc::emitVarReset(AstVar* varp, bool constructing) { - // 'constructing' indicates that the object was just constructed, so no need to clear it also +void EmitCFunc::emitVarReset(const string& prefix, AstVar* varp, bool constructing) { + // 'constructing' indicates that the object was just constructed, so if it is a string or + // something that starts off clear already, no need to clear it again AstNodeDType* const dtypep = varp->dtypep()->skipRefp(); const string vlSelf = VSelfPointerText::replaceThis(m_useSelfForThis, "this->"); - const string varNameProtected = (VN_IS(m_modp, Class) || varp->isFuncLocal()) - ? varp->nameProtect() - : vlSelf + varp->nameProtect(); + const string varNameProtected + = ((VN_IS(m_modp, Class) || varp->isFuncLocal()) || !prefix.empty()) + ? varp->nameProtect() + : vlSelf + varp->nameProtect(); + const string newPrefix = prefix + varNameProtected; if (varp->isIO() && m_modp->isTop() && optSystemC()) { // System C top I/O doesn't need loading, as the lower level subinst code does it.} } else if (varp->isParam()) { @@ -540,54 +546,55 @@ void EmitCFunc::emitVarReset(AstVar* varp, bool constructing) { // If an ARRAYINIT we initialize it using an initial block similar to a signal // puts("// parameter "+varp->nameProtect()+" = "+varp->valuep()->name()+"\n"); } else if (const AstInitArray* const initarp = VN_CAST(varp->valuep(), InitArray)) { + // TODO this code probably better handled as initp argument to emitVarResetRecurse + // TODO merge this functionality with V3EmitCConstInit.h visitors if (VN_IS(dtypep, AssocArrayDType)) { if (initarp->defaultp()) { - emitSetVarConstant(varNameProtected + ".atDefault()", - VN_AS(initarp->defaultp(), Const)); + emitSetVarConstant(newPrefix + ".atDefault()", VN_AS(initarp->defaultp(), Const)); } if (!constructing) puts(varNameProtected + ".clear();"); const auto& mapr = initarp->map(); for (const auto& itr : mapr) { AstNode* const valuep = itr.second->valuep(); - emitSetVarConstant(varNameProtected + ".at(" + cvtToStr(itr.first) + ")", + emitSetVarConstant(newPrefix + ".at(" + cvtToStr(itr.first) + ")", VN_AS(valuep, Const)); } } else if (VN_IS(dtypep, WildcardArrayDType)) { if (initarp->defaultp()) { - emitSetVarConstant(varNameProtected + ".atDefault()", - VN_AS(initarp->defaultp(), Const)); + emitSetVarConstant(newPrefix + ".atDefault()", VN_AS(initarp->defaultp(), Const)); } - if (!constructing) puts(varNameProtected + ".clear();"); + if (!constructing) puts(newPrefix + ".clear();"); const auto& mapr = initarp->map(); for (const auto& itr : mapr) { AstNode* const valuep = itr.second->valuep(); - emitSetVarConstant(varNameProtected + ".at(" + cvtToStr(itr.first) + ")", + emitSetVarConstant(newPrefix + ".at(" + cvtToStr(itr.first) + ")", VN_AS(valuep, Const)); } } else if (AstUnpackArrayDType* const adtypep = VN_CAST(dtypep, UnpackArrayDType)) { if (initarp->defaultp()) { puts("for (int __Vi = 0; __Vi < " + cvtToStr(adtypep->elementsConst())); puts("; ++__Vi) {\n"); - emitSetVarConstant(varNameProtected + "[__Vi]", VN_AS(initarp->defaultp(), Const)); + emitSetVarConstant(newPrefix + "[__Vi]", VN_AS(initarp->defaultp(), Const)); puts("}\n"); } const auto& mapr = initarp->map(); for (const auto& itr : mapr) { AstNode* const valuep = itr.second->valuep(); - emitSetVarConstant(varNameProtected + "[" + cvtToStr(itr.first) + "]", + emitSetVarConstant(newPrefix + "[" + cvtToStr(itr.first) + "]", VN_AS(valuep, Const)); } } else { varp->v3fatalSrc("InitArray under non-arrayed var"); } } else { - putns(varp, emitVarResetRecurse(varp, constructing, varNameProtected, dtypep, 0, "")); + putns(varp, + emitVarResetRecurse(varp, constructing, newPrefix, dtypep, 0, "", varp->valuep())); } } string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing, const string& varNameProtected, AstNodeDType* dtypep, - int depth, const string& suffix) { + int depth, const string& suffix, const AstNode* valuep) { dtypep = dtypep->skipRefp(); AstBasicDType* const basicp = dtypep->basicp(); // Returns string to do resetting, empty to do nothing (which caller should handle) @@ -597,14 +604,14 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing, const string pre = constructing ? "" : varNameProtected + suffix + ".clear();\n"; return pre + emitVarResetRecurse(varp, constructing, varNameProtected, adtypep->subDTypep(), - depth + 1, suffix + ".atDefault()" + cvtarray); + depth + 1, suffix + ".atDefault()" + cvtarray, nullptr); } else if (AstWildcardArrayDType* const adtypep = VN_CAST(dtypep, WildcardArrayDType)) { // Access std::array as C array const string cvtarray = (adtypep->subDTypep()->isWide() ? ".data()" : ""); const string pre = constructing ? "" : varNameProtected + suffix + ".clear();\n"; return pre + emitVarResetRecurse(varp, constructing, varNameProtected, adtypep->subDTypep(), - depth + 1, suffix + ".atDefault()" + cvtarray); + depth + 1, suffix + ".atDefault()" + cvtarray, nullptr); } else if (VN_IS(dtypep, CDType)) { return ""; // Constructor does it } else if (VN_IS(dtypep, ClassRefDType)) { @@ -617,14 +624,14 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing, const string pre = constructing ? "" : varNameProtected + suffix + ".clear();\n"; return pre + emitVarResetRecurse(varp, constructing, varNameProtected, adtypep->subDTypep(), - depth + 1, suffix + ".atDefault()" + cvtarray); + depth + 1, suffix + ".atDefault()" + cvtarray, nullptr); } else if (const AstQueueDType* const adtypep = VN_CAST(dtypep, QueueDType)) { // Access std::array as C array const string cvtarray = (adtypep->subDTypep()->isWide() ? ".data()" : ""); const string pre = constructing ? "" : varNameProtected + suffix + ".clear();\n"; return pre + emitVarResetRecurse(varp, constructing, varNameProtected, adtypep->subDTypep(), - depth + 1, suffix + ".atDefault()" + cvtarray); + depth + 1, suffix + ".atDefault()" + cvtarray, nullptr); } else if (VN_IS(dtypep, SampleQueueDType)) { return ""; } else if (const AstUnpackArrayDType* const adtypep = VN_CAST(dtypep, UnpackArrayDType)) { @@ -635,17 +642,17 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing, + cvtToStr(adtypep->elementsConst()) + "; ++" + ivar + ") {\n"); const string below = emitVarResetRecurse(varp, constructing, varNameProtected, adtypep->subDTypep(), - depth + 1, suffix + "[" + ivar + "]"); + depth + 1, suffix + "[" + ivar + "]", nullptr); const string post = "}\n"; return below.empty() ? "" : pre + below + post; } else if (VN_IS(dtypep, NodeUOrStructDType) && !VN_AS(dtypep, NodeUOrStructDType)->packed()) { - const auto* const sdtypep = VN_AS(dtypep, NodeUOrStructDType); + const AstNodeUOrStructDType* const sdtypep = VN_AS(dtypep, NodeUOrStructDType); string literal; for (const AstMemberDType* itemp = sdtypep->membersp(); itemp; itemp = VN_AS(itemp->nextp(), MemberDType)) { const std::string line = emitVarResetRecurse( varp, constructing, varNameProtected + suffix + "." + itemp->nameProtect(), - itemp->dtypep(), depth + 1, ""); + itemp->dtypep(), depth + 1, "", itemp->valuep()); if (!line.empty()) literal += line; } return literal; @@ -664,6 +671,8 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing, return ""; } else if (basicp && (basicp->isRandomGenerator() || basicp->isStdRandomGenerator())) { return ""; + } else if (basicp && (basicp->isEvent())) { + return "VlAssignableEvent{};\n"; } else if (basicp) { const bool zeroit = (varp->attrFileDescr() // Zero so we don't do file IO if never $fopen @@ -678,10 +687,10 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing, splitSizeInc(1); if (dtypep->isWide()) { // Handle unpacked; not basicp->isWide string out; - if (varp->valuep()) { - const AstConst* const constp = VN_AS(varp->valuep(), Const); + if (valuep) { + const AstConst* const constp = VN_AS(valuep, Const); UASSERT_OBJ(constp, varp, "non-const initializer for variable"); - for (int w = 0; w < varp->widthWords(); ++w) { + for (int w = 0; w < dtypep->widthWords(); ++w) { out += varNameProtected + suffix + "[" + cvtToStr(w) + "] = "; out += cvtToStr(constp->num().edataWord(w)) + "U;\n"; } @@ -705,7 +714,15 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing, return out; } else { string out = varNameProtected + suffix; - if (zeroit) { + if (valuep) { + out += " = "; + // TODO cleanup code shared between here, V3EmitCConstInit.h, + // EmitCFunc::emitVarReset, EmitCFunc::emitConstant + const AstConst* const constp = VN_AS(valuep, Const); + UASSERT_OBJ(constp, varp, "non-const initializer for variable"); + out += cvtToStr(constp->num().edataWord(0)) + "U;\n"; + out += ";\n"; + } else if (zeroit) { out += " = 0;\n"; } else { emitVarResetScopeHash(); diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index bb38c80f2..1684cc1ca 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -144,6 +144,8 @@ class EmitCFunc VL_NOT_FINAL : public EmitCConstInit { } m_emitDispState; protected: + VL_DEFINE_DEBUG_FUNCTIONS; + EmitCLazyDecls m_lazyDecls{*this}; // Visitor for emitting lazy declarations bool m_useSelfForThis = false; // Replace "this" with "vlSelf" bool m_usevlSelfRef = false; // Use vlSelfRef reference instead of vlSelf pointer @@ -207,15 +209,16 @@ public: AstNode* thsp); void emitCCallArgs(const AstNodeCCall* nodep, const string& selfPointer, bool inProcess); void emitDereference(AstNode* nodep, const string& pointer); + std::string dereferenceString(const std::string& pointer); void emitCvtPackStr(AstNode* nodep); void emitCvtWideArray(AstNode* nodep, AstNode* fromp); void emitConstant(AstConst* nodep); void emitConstantString(const AstConst* nodep); void emitSetVarConstant(const string& assignString, AstConst* constp); - void emitVarReset(AstVar* varp, bool constructing); + void emitVarReset(const string& prefix, AstVar* varp, bool constructing); string emitVarResetRecurse(const AstVar* varp, bool constructing, const string& varNameProtected, AstNodeDType* dtypep, int depth, - const string& suffix); + const string& suffix, const AstNode* valuep); void emitVarResetScopeHash(); void emitChangeDet(); void emitConstInit(AstNode* initp) { iterateConst(initp); } @@ -478,7 +481,7 @@ public: if (nodep->isCoroutine()) { // Sometimes coroutines don't have co_awaits, // so emit a co_return at the end to avoid compile errors. - puts("co_return;"); + puts("co_return;\n"); } puts("}\n"); @@ -523,6 +526,32 @@ public: } void visit(AstNodeAssign* nodep) override { + if (AstCReset* const resetp = VN_CAST(nodep->rhsp(), CReset)) { + // TODO get rid of emitVarReset and instead let AstNodeAssign understand how to init + // anything + AstNode* fromp = nodep->lhsp(); + // Fork needs to use a member select. Nothing else should be possible before VarRef. + if (AstMemberSel* const sfromp = VN_CAST(fromp, MemberSel)) { + // Fork-DynScope generated pointer to previously automatic variable + AstVar* const memberVarp = sfromp->varp(); + fromp = sfromp->fromp(); + if (AstNullCheck* const sfromp = VN_CAST(fromp, NullCheck)) fromp = sfromp->lhsp(); + AstNodeVarRef* const fromVarRefp = VN_AS(fromp, NodeVarRef); + emitVarReset( + ("VL_NULL_CHECK("s + + (fromVarRefp->selfPointer().isEmpty() + ? "" + : dereferenceString(fromVarRefp->selfPointerProtect(m_useSelfForThis))) + + fromVarRefp->varp()->nameProtect() + ", \"" + + V3OutFormatter::quoteNameControls(protect(nodep->fileline()->filename())) + + "\", " + std::to_string(nodep->fileline()->lineno()) + ")->"), + memberVarp, resetp->constructing()); + } else { + AstVar* const varp = VN_AS(fromp, NodeVarRef)->varp(); + emitVarReset("", varp, resetp->constructing()); + } + return; + } bool paren = true; bool decind = false; bool rhs = true; @@ -702,6 +731,7 @@ public: void visit(AstCAwait* nodep) override { putns(nodep, "co_await "); iterateConst(nodep->exprp()); + puts(";\n"); } void visit(AstCNew* nodep) override { if (VN_IS(nodep->dtypep(), VoidDType)) { @@ -720,15 +750,44 @@ public: putns(nodep, nodep->name()); puts("("); bool comma = false; + int argNum = 0; for (AstNode* subnodep = nodep->pinsp(); subnodep; subnodep = subnodep->nextp()) { if (comma) puts(", "); // handle wide arguments to the queues if (VN_IS(nodep->fromp()->dtypep(), QueueDType) && subnodep->dtypep()->isWide()) { emitCvtWideArray(subnodep, nodep->fromp()); + } else if (nodep->method() == VCMethod::RANDOMIZER_HARD && argNum == 1) { + // For RANDOMIZER_HARD's filename argument (2nd arg after constraint), + // apply protect() similar to VL_STOP to handle --protected flag + if (const AstCExpr* const cexprp = VN_CAST(subnodep, CExpr)) { + // Extract filename from the CExpr (which contains "filename") + std::string filename; + for (const AstNode* textnodep = cexprp->nodesp(); textnodep; + textnodep = textnodep->nextp()) { + if (const AstText* const textp = VN_CAST(textnodep, Text)) { + filename = textp->text(); + break; + } + } + // Remove surrounding quotes if present + if (filename.size() >= 2 && filename.front() == '"' + && filename.back() == '"') { + filename = filename.substr(1, filename.size() - 2); + } + // Emit with protect() + putsQuoted(protect(filename)); + } else { + iterateConst(subnodep); + } } else { iterateConst(subnodep); } comma = true; + argNum++; + } + if (nodep->withp()) { + if (comma) puts(", "); + iterateConst(nodep->withp()); } puts(")"); } @@ -962,7 +1021,7 @@ public: } void visit(AstFGetS* nodep) override { checkMaxWords(nodep); - emitOpName(nodep, nodep->emitC(), nodep->lhsp(), nodep->rhsp(), nullptr); + emitOpName(nodep, nodep->emitC(), nodep->strgp(), nodep->filep(), nullptr); } void checkMaxWords(AstNode* nodep) { @@ -1308,6 +1367,9 @@ public: / v3Global.rootp()->timeprecision().multiplier())); puts(")"); } + void visit(AstGetInitialRandomSeed* nodep) override { + putns(nodep, "vlSymsp->_vm_contextp__->randSeed()"); + } void visit(AstTimeFormat* nodep) override { putns(nodep, "VL_TIMEFORMAT_IINI("); if (nodep->unitsp()) { @@ -1500,10 +1562,22 @@ public: puts(")"); } void visit(AstNewCopy* nodep) override { - putns(nodep, "VL_NEW(" + EmitCUtil::prefixNameProtect(nodep->dtypep())); - puts(", *"); // i.e. make into a reference - iterateAndNextConstNull(nodep->rhsp()); - puts(")"); + // Polymorphic shallow clone: preserves runtime type via virtual clone() + // VL_NULL_CHECK enforces null check per IEEE 1800-2017 8.7 + putns(nodep, "VL_NULL_CHECK("); + if (VN_IS(nodep->rhsp(), Const) && VN_AS(nodep->rhsp(), Const)->isNull()) { + // V3Const folded rhs to null: emit a typed empty ref so VL_NULL_CHECK fires + const AstClassRefDType* const refDTypep + = VN_CAST(nodep->dtypep()->skipRefp(), ClassRefDType); + puts(refDTypep->cType("", false, false) + "{}"); + } else { + iterateAndNextConstNull(nodep->rhsp()); + } + puts(", "); + putsQuoted(protect(nodep->fileline()->filename())); + puts(", "); + puts(cvtToStr(nodep->fileline()->lineno())); + puts(").clone(vlSymsp->__Vm_deleter)"); } void visit(AstSel* nodep) override { // Note ASSIGN checks for this on a LHS @@ -1621,6 +1695,22 @@ public: puts(VSelfPointerText::replaceThis(m_useSelfForThis, "this")); puts("}"); } + void visit(AstNodeSel* nodep) override { + if (!VN_IS(nodep, ArraySel) && !VN_IS(nodep, WordSel)) { + visit(static_cast(nodep)); + return; + } + // ArraySel or WordSel + iterateAndNextConstNull(nodep->fromp()); + // Special case constant index for readability + if (AstConst* const idxp = VN_CAST(nodep->bitp(), Const)) { + puts("[" + std::to_string(idxp->toUInt()) + "U]"); + return; + } + putbs("["); + iterateAndNextConstNull(nodep->bitp()); + puts("]"); + } // void visit(AstConsAssoc* nodep) override { @@ -1711,10 +1801,6 @@ public: puts(")"); } } - void visit(AstCReset* nodep) override { - AstVar* const varp = nodep->varrefp()->varp(); - emitVarReset(varp, nodep->constructing()); - } void visit(AstExecGraph* nodep) override { // The location of the AstExecGraph within the containing AstCFunc is where we want to // invoke the graph and wait for it to complete. Emitting the children does just that. diff --git a/src/V3EmitCHeaders.cpp b/src/V3EmitCHeaders.cpp index d6d47405c..77124ad91 100644 --- a/src/V3EmitCHeaders.cpp +++ b/src/V3EmitCHeaders.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -169,8 +169,8 @@ class EmitCHeader final : public EmitCConstInit { putns(modp, name + "(" + ctorArgs + ");\n"); putns(modp, "~" + name + "();\n"); } else { - putns(modp, name + "() = default;\n"); - putns(modp, "~" + name + "() = default;\n"); + putns(modp, name + "();\n"); + putns(modp, "~" + name + "();\n"); putns(modp, "void ctor(" + ctorArgs + ");\n"); putns(modp, "void dtor();\n"); } @@ -183,6 +183,12 @@ class EmitCHeader final : public EmitCConstInit { if (!VN_IS(modp, Class)) { decorateFirst(first, section); puts("void " + protect("__Vconfigure") + "(bool first);\n"); + } else { + decorateFirst(first, section); + const std::string name = V3OutFormatter::quoteNameControls( + VIdProtect::protectWordsIf(modp->prettyName(), v3Global.opt.protectIds())); + // "override", but don't want clang to start checking them: + puts("virtual const char* typeName() const { return \""s + name + "\"; }\n"); } if (v3Global.opt.coverage() && !VN_IS(modp, Class)) { @@ -207,6 +213,15 @@ class EmitCHeader final : public EmitCConstInit { puts("void " + protect("__Vserialize") + "(VerilatedSerialize& os);\n"); puts("void " + protect("__Vdeserialize") + "(VerilatedDeserialize& os);\n"); } + + // Polymorphic clone for concrete (non-abstract, non-interface) classes + if (const AstClass* const classp = VN_CAST(modp, Class)) { + if (!classp->isInterfaceClass() && !classp->isVirtual()) { + decorateFirst(first, section); + putns(classp, "VlClass* clone() const { return new " + + EmitCUtil::prefixNameProtect(classp) + "(*this); }\n"); + } + } } void emitEnums(const AstNodeModule* modp) { bool first = true; diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp index c29f51013..8300a01d3 100644 --- a/src/V3EmitCImp.cpp +++ b/src/V3EmitCImp.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -135,6 +135,8 @@ class EmitCImp final : public EmitCFunc { ofp()->indentDec(); puts(" {\n"); } else { + putns(modp, modName + "::" + modName + "() = default;\n"); + putns(modp, modName + "::~" + modName + "() = default;\n\n"); putns(modp, "void " + modName + "::ctor(" + ctorArgs + ") {\n"); } diff --git a/src/V3EmitCInlines.cpp b/src/V3EmitCInlines.cpp index a10534849..303b28c5a 100644 --- a/src/V3EmitCInlines.cpp +++ b/src/V3EmitCInlines.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitCMain.cpp b/src/V3EmitCMain.cpp index 2cf5ab518..46734c540 100644 --- a/src/V3EmitCMain.cpp +++ b/src/V3EmitCMain.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitCMain.h b/src/V3EmitCMain.h index d2029ed98..1bee13b15 100644 --- a/src/V3EmitCMain.h +++ b/src/V3EmitCMain.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp deleted file mode 100644 index c1ebc8359..000000000 --- a/src/V3EmitCMake.cpp +++ /dev/null @@ -1,241 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -//************************************************************************* -// DESCRIPTION: Verilator: Emit CMake file list -// -// Code available from: https://verilator.org -// -//************************************************************************* -// -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -// -//************************************************************************* - -#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT - -#include "V3EmitCMake.h" - -#include "V3EmitCBase.h" -#include "V3HierBlock.h" -#include "V3Os.h" - -#include - -VL_DEFINE_DEBUG_FUNCTIONS; - -// TODO: this file is completely uncovered by tests - -// ###################################################################### -// Emit statements - -class CMakeEmitter final { - - // METHODS - - // STATIC FUNCTIONS - - // Concatenate all strings in 'strs' with ' ' between them. - template - static string cmake_list(const T_List& strs) { - string s; - for (const std::string& itr : strs) { - if (!s.empty()) s += ' '; - s += '"'; - s += V3OutFormatter::quoteNameControls(itr); - s += '"'; - } - return s; - } - static string cmake_list(const VFileLibList& strs) { - string s; - for (const VFileLibName& itr : strs) { - if (!s.empty()) s += ' '; - s += '"'; - s += V3OutFormatter::quoteNameControls(itr.filename()); - s += '"'; - } - return s; - } - - // Print CMake variable set command: output raw_value unmodified - // cache_type should be empty for a normal variable - // "BOOL", "FILEPATH", "PATH", "STRING" or "INTERNAL" for a CACHE variable - // See https://cmake.org/cmake/help/latest/command/set.html - static void cmake_set_raw(std::ofstream& of, const string& name, const string& raw_value, - const string& cache_type = "", const string& docstring = "") { - of << "set(" << name << " " << raw_value; - if (!cache_type.empty()) of << " CACHE " << cache_type << " \"" << docstring << '"'; - of << ")\n"; - } - - static void cmake_set(std::ofstream& of, const string& name, const string& value, - const string& cache_type = "", const string& docstring = "") { - const string raw_value = '"' + value + '"'; - cmake_set_raw(of, name, raw_value, cache_type, docstring); - } - - static void emitOverallCMake() { - const std::unique_ptr of{ - V3File::new_ofstream(v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + ".cmake")}; - const string name = v3Global.opt.prefix(); - - *of << "# Verilated -*- CMake -*-\n"; - *of << "# DESCR" - "IPTION: Verilator output: CMake include script with class lists\n"; - *of << "#\n"; - *of << "# This CMake script lists generated Verilated files, for " - "including in higher level CMake scripts.\n"; - *of << "# This file is meant to be consumed by the verilate() function,\n"; - *of << "# which becomes available after executing `find_package(verilator).\n"; - - *of << "\n### Constants...\n"; - cmake_set(*of, "PERL", V3OutFormatter::quoteNameControls(V3Options::getenvPERL()), - "FILEPATH", "Perl executable (from $PERL, defaults to 'perl' if not set)"); - cmake_set(*of, "PYTHON3", V3OutFormatter::quoteNameControls(V3Options::getenvPYTHON3()), - "FILEPATH", - "Python3 executable (from $PYTHON3, defaults to 'python3' if not set)"); - cmake_set(*of, "VERILATOR_ROOT", - V3OutFormatter::quoteNameControls(V3Options::getenvVERILATOR_ROOT()), "PATH", - "Path to Verilator kit (from $VERILATOR_ROOT)"); - cmake_set(*of, "VERILATOR_SOLVER", - V3OutFormatter::quoteNameControls(V3Options::getenvVERILATOR_SOLVER()), "STRING", - "Default SMT solver for constrained randomization (from $VERILATOR_SOLVER)"); - - *of << "\n### Compiler flags...\n"; - - *of << "# User CFLAGS (from -CFLAGS on Verilator command line)\n"; - cmake_set_raw(*of, name + "_USER_CFLAGS", cmake_list(v3Global.opt.cFlags())); - - *of << "# User LDLIBS (from -LDFLAGS on Verilator command line)\n"; - cmake_set_raw(*of, name + "_USER_LDLIBS", cmake_list(v3Global.opt.ldLibs())); - - *of << "\n### Switches...\n"; - - *of << "# SystemC output mode? 0/1 (from --sc)\n"; - cmake_set_raw(*of, name + "_SC", v3Global.opt.systemC() ? "1" : "0"); - *of << "# Coverage output mode? 0/1 (from --coverage)\n"; - cmake_set_raw(*of, name + "_COVERAGE", v3Global.opt.coverage() ? "1" : "0"); - *of << "# Timing mode? 0/1\n"; - cmake_set_raw(*of, name + "_TIMING", v3Global.usesTiming() ? "1" : "0"); - *of << "# Threaded output mode? 1/N threads (from --threads)\n"; - cmake_set_raw(*of, name + "_THREADS", cvtToStr(v3Global.opt.threads())); - *of << "# FST Tracing output mode? 0/1 (from --trace-fst)\n"; - cmake_set_raw(*of, name + "_TRACE_FST", (v3Global.opt.traceEnabledFst()) ? "1" : "0"); - *of << "# SAIF Tracing output mode? 0/1 (from --trace-saif)\n"; - cmake_set_raw(*of, name + "_TRACE_SAIF", (v3Global.opt.traceEnabledSaif()) ? "1" : "0"); - *of << "# VCD Tracing output mode? 0/1 (from --trace-vcd)\n"; - cmake_set_raw(*of, name + "_TRACE_VCD", (v3Global.opt.traceEnabledVcd()) ? "1" : "0"); - - *of << "\n### Sources...\n"; - std::vector classes_fast; - std::vector classes_slow; - std::vector support_fast; - std::vector support_slow; - std::vector global; - for (AstNodeFile* nodep = v3Global.rootp()->filesp(); nodep; - nodep = VN_AS(nodep->nextp(), NodeFile)) { - const AstCFile* const cfilep = VN_CAST(nodep, CFile); - if (cfilep && cfilep->source()) { - if (cfilep->support()) { - if (cfilep->slow()) { - support_slow.push_back(cfilep->name()); - } else { - support_fast.push_back(cfilep->name()); - } - } else { - if (cfilep->slow()) { - classes_slow.push_back(cfilep->name()); - } else { - classes_fast.push_back(cfilep->name()); - } - } - } - } - - for (const string& cpp : v3Global.verilatedCppFiles()) - global.emplace_back("${VERILATOR_ROOT}/include/"s + cpp); - - if (!v3Global.opt.libCreate().empty()) { - global.emplace_back(v3Global.opt.makeDir() + "/" + v3Global.opt.libCreate() + ".cpp"); - } - - *of << "# Global classes, need linked once per executable\n"; - cmake_set_raw(*of, name + "_GLOBAL", cmake_list(global)); - *of << "# Generated module classes, non-fast-path, compile with low/medium optimization\n"; - cmake_set_raw(*of, name + "_CLASSES_SLOW", cmake_list(classes_slow)); - *of << "# Generated module classes, fast-path, compile with highest optimization\n"; - cmake_set_raw(*of, name + "_CLASSES_FAST", cmake_list(classes_fast)); - *of << "# Generated support classes, non-fast-path, compile with " - "low/medium optimization\n"; - cmake_set_raw(*of, name + "_SUPPORT_SLOW", cmake_list(support_slow)); - *of << "# Generated support classes, fast-path, compile with highest optimization\n"; - cmake_set_raw(*of, name + "_SUPPORT_FAST", cmake_list(support_fast)); - - *of << "# All dependencies\n"; - cmake_set_raw(*of, name + "_DEPS", cmake_list(V3File::getAllDeps())); - - *of << "# User .cpp files (from .cpp's on Verilator command line)\n"; - cmake_set_raw(*of, name + "_USER_CLASSES", cmake_list(v3Global.opt.cppFiles())); - if (const V3HierGraph* const graphp = v3Global.hierGraphp()) { - *of << "# Verilate hierarchical blocks\n"; - // Sorted hierarchical blocks in order of leaf-first. - *of << "get_target_property(TOP_TARGET_NAME \"${TARGET}\" NAME)\n"; - for (const V3GraphVertex& vtx : vlstd::reverse_view(graphp->vertices())) { - const V3HierBlock* const hblockp = vtx.as(); - const string prefix = hblockp->hierPrefix(); - *of << "add_library(" << prefix << " STATIC)\n"; - *of << "target_link_libraries(${TOP_TARGET_NAME} PRIVATE " << prefix << ")\n"; - if (!hblockp->outEmpty()) { - *of << "target_link_libraries(" << prefix << " INTERFACE"; - for (const V3GraphEdge& edge : hblockp->outEdges()) { - const V3HierBlock* const dependencyp = edge.top()->as(); - *of << " " << dependencyp->hierPrefix(); - } - *of << ")\n"; - } - *of << "verilate(" << prefix << " PREFIX " << prefix << " TOP_MODULE " - << hblockp->modp()->name() << " DIRECTORY " - << v3Global.opt.makeDir() + "/" + prefix << " SOURCES "; - for (const V3GraphEdge& edge : hblockp->outEdges()) { - const V3HierBlock* const dependencyp = edge.top()->as(); - *of << " " - << v3Global.opt.makeDir() + "/" + dependencyp->hierWrapperFilename(true); - } - *of << " "; - const string vFile = hblockp->vFileIfNecessary(); - if (!vFile.empty()) *of << vFile << " "; - for (const auto& i : v3Global.opt.vFiles()) - *of << V3Os::filenameRealPath(i.filename()) << " "; - *of << " VERILATOR_ARGS "; - *of << "-f " << hblockp->commandArgsFilename(true) - << " -CFLAGS -fPIC" // hierarchical block will be static, but may be linked - // with .so - << ")\n"; - } - *of << "\n# Verilate the top module that refers to lib-create wrappers of above\n"; - *of << "verilate(${TOP_TARGET_NAME} PREFIX " << v3Global.opt.prefix() << " TOP_MODULE " - << v3Global.rootp()->topModulep()->name() << " DIRECTORY " - << v3Global.opt.makeDir() << " SOURCES "; - for (const V3GraphVertex& vtx : graphp->vertices()) { - const V3HierBlock* const hblockp = vtx.as(); - *of << " " << v3Global.opt.makeDir() + "/" + hblockp->hierWrapperFilename(true); - } - *of << " " << cmake_list(v3Global.opt.vFiles()); - *of << " VERILATOR_ARGS "; - *of << "-f " << graphp->topCommandArgsFilename(true); - *of << ")\n"; - } - } - -public: - explicit CMakeEmitter() { emitOverallCMake(); } - virtual ~CMakeEmitter() = default; -}; - -void V3EmitCMake::emit() { - UINFO(2, __FUNCTION__ << ":"); - const CMakeEmitter emitter; -} diff --git a/src/V3EmitCMake.h b/src/V3EmitCMake.h deleted file mode 100644 index 7d39784f2..000000000 --- a/src/V3EmitCMake.h +++ /dev/null @@ -1,30 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -//************************************************************************* -// DESCRIPTION: Verilator: Emit CMake file list -// -// Code available from: https://verilator.org -// -//************************************************************************* -// -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -// -//************************************************************************* - -#ifndef VERILATOR_V3EMITCMAKE_H_ -#define VERILATOR_V3EMITCMAKE_H_ - -#include "config_build.h" -#include "verilatedos.h" - -//============================================================================ - -class V3EmitCMake final { -public: - static void emit() VL_MT_DISABLED; -}; - -#endif // Guard diff --git a/src/V3EmitCModel.cpp b/src/V3EmitCModel.cpp index 37d829f90..029f01941 100644 --- a/src/V3EmitCModel.cpp +++ b/src/V3EmitCModel.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -414,11 +414,11 @@ class EmitCModel final : public EmitCFunc { if (v3Global.hasClasses()) puts("vlSymsp->__Vm_deleter.deleteAll();\n"); puts("if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {\n"); - puts("vlSymsp->__Vm_didInit = true;\n"); puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+ Initial\\n\"););\n"); puts(topModNameProtected + "__" + protect("_eval_static") + "(&(vlSymsp->TOP));\n"); puts(topModNameProtected + "__" + protect("_eval_initial") + "(&(vlSymsp->TOP));\n"); puts(topModNameProtected + "__" + protect("_eval_settle") + "(&(vlSymsp->TOP));\n"); + puts("vlSymsp->__Vm_didInit = true;\n"); puts("}\n"); if (v3Global.opt.profExec() && !v3Global.opt.hierChild() @@ -458,7 +458,7 @@ class EmitCModel final : public EmitCFunc { putns(modp, "bool " + EmitCUtil::topClassName() + "::eventsPending() { return !vlSymsp->TOP."); puts(delaySchedp->nameProtect()); - puts(".empty(); }\n\n"); + puts(".empty() && !contextp()->gotFinish(); }\n\n"); putns(modp, "uint64_t " + EmitCUtil::topClassName() + "::nextTimeSlot() { return vlSymsp->TOP."); @@ -544,15 +544,19 @@ class EmitCModel final : public EmitCFunc { puts(EmitCUtil::voidSelfAssign(modp)); puts(EmitCUtil::symClassAssign()); puts("if (!vlSymsp->_vm_contextp__->calcUnusedSigs()) {\n"); - puts("VL_FATAL_MT(__FILE__, __LINE__, __FILE__,\n"); + puts("VL_FATAL_MT(__FILE__, __LINE__, __FILE__,\n"); // LCOV_EXCL_LINE puts("\"Turning on wave traces requires Verilated::traceEverOn(true) call before time " "0.\");\n"); puts("}\n"); puts("vlSymsp->__Vm_baseCode = code;\n"); - puts("tracep->pushPrefix(vlSymsp->name(), VerilatedTracePrefixType::SCOPE_MODULE);\n"); + if (v3Global.opt.libCreate().empty()) { + puts("tracep->pushPrefix(vlSymsp->name(), VerilatedTracePrefixType::SCOPE_MODULE);\n"); + } puts(topModNameProtected + "__" + protect("trace_decl_types") + "(tracep);\n"); puts(topModNameProtected + "__" + protect("trace_init_top") + "(vlSelf, tracep);\n"); - puts("tracep->popPrefix();\n"); + if (v3Global.opt.libCreate().empty()) { // + puts("tracep->popPrefix();\n"); + } puts("}\n"); // Forward declaration @@ -583,8 +587,13 @@ class EmitCModel final : public EmitCFunc { + " and --trace-vcd with VerilatedVcd object\");\n"); puts(/**/ "}\n"); puts(/**/ "stfp->spTrace()->addModel(this);\n"); - puts(/**/ "stfp->spTrace()->addInitCb(&" + protect("trace_init") - + ", &(vlSymsp->TOP));\n"); + puts(/**/ "stfp->spTrace()->addInitCb("s // + + "&" + protect("trace_init") // + + ", &(vlSymsp->TOP)" // + + ", name()" // + + ", " + (v3Global.opt.libCreate().empty() ? "false" : "true") // + + ", " + std::to_string(v3Global.rootp()->nTraceCodes()) // + + ");\n"); puts(/**/ topModNameProtected + "__" + protect("trace_register") + "(&(vlSymsp->TOP), stfp->spTrace());\n"); puts("}\n"); diff --git a/src/V3EmitCPch.cpp b/src/V3EmitCPch.cpp index 8c404a4d6..9c26d22d9 100644 --- a/src/V3EmitCPch.cpp +++ b/src/V3EmitCPch.cpp @@ -2,10 +2,10 @@ //************************************************************************* // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 5b60d210e..5a9c6398f 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -828,6 +828,9 @@ std::vector EmitCSyms::getSymCtorStmts() { stmt += ", "; stmt += varp->vlEnumDir(); // VLVD_IN etc if (varp->dtypep()->skipRefp()->isSigned()) stmt += "|VLVF_SIGNED"; + if (AstBasicDType* const basicp = varp->dtypep()->skipRefp()->basicp()) { + if (basicp->keyword() == VBasicDTypeKwd::BIT) stmt += "|VLVF_BITVAR"; + } stmt += ", "; stmt += std::to_string(udim); stmt += ", "; diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index 393a84525..17caa16c2 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitMk.h b/src/V3EmitMk.h index 31fa35037..51c8308c7 100644 --- a/src/V3EmitMk.h +++ b/src/V3EmitMk.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitMkJson.cpp b/src/V3EmitMkJson.cpp index 740bf3acc..042787ea8 100644 --- a/src/V3EmitMkJson.cpp +++ b/src/V3EmitMkJson.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitMkJson.h b/src/V3EmitMkJson.h index 85136892d..bfb8bb01d 100644 --- a/src/V3EmitMkJson.h +++ b/src/V3EmitMkJson.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index d65dcc441..904da3186 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -182,6 +182,8 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst { } void visit(AstInitialAutomatic* nodep) override { iterateChildrenConst(nodep); } void visit(AstInitialStatic* nodep) override { iterateChildrenConst(nodep); } + void visit(AstInitialAutomaticStmt* nodep) override { iterateChildrenConst(nodep); } + void visit(AstInitialStaticStmt* nodep) override { iterateChildrenConst(nodep); } void visit(AstAlways* nodep) override { if (const AstAssignW* const ap = VN_CAST(nodep->stmtsp(), AssignW)) { if (!ap->nextp()) { @@ -225,12 +227,6 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst { iterateAndNextConstNull(nodep->rhsp()); if (!m_suppressSemi) puts(";\n"); } - void visit(AstAssignDly* nodep) override { - iterateAndNextConstNull(nodep->lhsp()); - putfs(nodep, " <= "); - iterateAndNextConstNull(nodep->rhsp()); - puts(";\n"); - } void visit(AstAlias* nodep) override { putbs("alias "); iterateConst(nodep->itemsp()); @@ -271,6 +267,7 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst { if (nodep->sensp()) puts(" "); iterateChildrenConst(nodep); } + void visit(AstCReset* nodep) override { puts("/*CRESET*/"); } void visit(AstCase* nodep) override { putfs(nodep, ""); if (nodep->priorityPragma()) puts("priority "); @@ -614,6 +611,7 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst { putfs(nodep, "$_EXPRSTMT(\n"); iterateAndNextConstNull(nodep->stmtsp()); putbs(", "); + iterateAndNextConstNull(nodep->resultp()); puts(");\n"); } @@ -622,6 +620,7 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst { puts("." + nodep->name() + "("); iterateAndCommaConstNull(nodep->pinsp()); puts(")"); + iterateConstNull(nodep->withp()); } void visit(AstCMethodCall* nodep) override { iterateConst(nodep->fromp()); @@ -1016,8 +1015,9 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst { } if (!VN_IS(nodep->taskp(), Property)) { puts("("); - iterateAndNextConstNull(nodep->pinsp()); + iterateAndNextConstNull(nodep->argsp()); puts(")"); + iterateConstNull(nodep->withp()); } } void visit(AstCCall* nodep) override { @@ -1027,6 +1027,12 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst { puts(")"); } void visit(AstArg* nodep) override { iterateAndNextConstNull(nodep->exprp()); } + void visit(AstWith* nodep) override { + putfs(nodep, " with ("); + iterateConstNull(nodep->exprp()); + puts(") "); + } + void visit(AstLambdaArgRef* nodep) override { putfs(nodep, nodep->name()); } void visit(AstPrintTimeScale* nodep) override { puts(nodep->verilogKwd()); puts(";\n"); @@ -1222,6 +1228,12 @@ void V3EmitV::debugVerilogForTree(const AstNode* nodep, std::ostream& os) { { EmitVStreamVisitor{nodep, os, /* tracking: */ true, true}; } } +std::string V3EmitV::debugVerilogForTree(const AstNode* nodep) { + std::stringstream ss; + debugVerilogForTree(nodep, ss); + return ss.str(); +} + void V3EmitV::emitvFiles() { UINFO(2, __FUNCTION__ << ":"); for (AstNodeFile* filep = v3Global.rootp()->filesp(); filep; diff --git a/src/V3EmitV.h b/src/V3EmitV.h index 527e4556e..5211d92b7 100644 --- a/src/V3EmitV.h +++ b/src/V3EmitV.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -29,6 +29,7 @@ class V3EmitV final { public: static void verilogForTree(const AstNode* nodep, std::ostream& os = std::cout); static void debugVerilogForTree(const AstNode* nodep, std::ostream& os); + static std::string debugVerilogForTree(const AstNode* nodep); static void emitvFiles(); static void debugEmitV(const string& filename); }; diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp deleted file mode 100644 index 1f4dd666f..000000000 --- a/src/V3EmitXml.cpp +++ /dev/null @@ -1,460 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -//************************************************************************* -// DESCRIPTION: Verilator: Emit Verilog from tree -// -// Code available from: https://verilator.org -// -//************************************************************************* -// -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -// -//************************************************************************* - -#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT - -#include "V3EmitXml.h" - -#include "V3EmitCBase.h" - -#include -#include - -VL_DEFINE_DEBUG_FUNCTIONS; - -// ###################################################################### -// Emit statements and expressions - -class EmitXmlFileVisitor final : public VNVisitorConst { - // NODE STATE - // Entire netlist: - // AstNode::user1 -> uint64_t, number to connect crossrefs - const VNUser1InUse m_user1InUse; - - // MEMBERS - V3OutFile* const m_ofp; - uint64_t m_id = 0; - - // METHODS - - // Outfile methods - V3OutFile* ofp() const { return m_ofp; } - virtual void puts(const string& str) { ofp()->puts(str); } - virtual void putsNoTracking(const string& str) { ofp()->putsNoTracking(str); } - virtual void putsQuoted(const string& str) { - // Quote \ and " for use inside C programs - // Don't use to quote a filename for #include - #include doesn't \ escape. - // Duplicate in V3File - here so we can print to string - putsNoTracking("\""); - putsNoTracking(V3OutFormatter::quoteNameControls(str, V3OutFormatter::LA_XML)); - putsNoTracking("\""); - } - - // XML methods - void outputId(AstNode* nodep) { - if (!nodep->user1()) nodep->user1(++m_id); - puts("\"" + cvtToStr(nodep->user1()) + "\""); - } - void outputTag(AstNode* nodep, const string& tagin) { - string tag = tagin; - if (tag == "") tag = VString::downcase(nodep->typeName()); - puts("<" + tag); - puts(" " + nodep->fileline()->xmlDetailedLocation()); - if (VN_IS(nodep, NodeDType)) { - puts(" id="); - outputId(nodep); - } - if (nodep->name() != "") { - puts(" name="); - putsQuoted(nodep->prettyName()); - } - if (nodep->tag() != "") { - puts(" tag="); - putsQuoted(nodep->tag()); - } - if (const AstNodeDType* const dtp = VN_CAST(nodep, NodeDType)) { - if (dtp->subDTypep()) { - puts(" sub_dtype_id="); - outputId(dtp->subDTypep()->skipRefp()); - } - } else { - if (nodep->dtypep()) { - puts(" dtype_id="); - outputId(nodep->dtypep()->skipRefp()); - } - } - } - void outputChildrenEnd(AstNode* nodep, const string& tagin) { - string tag = tagin; - if (tag == "") tag = VString::downcase(nodep->typeName()); - if (nodep->op1p() || nodep->op2p() || nodep->op3p() || nodep->op4p()) { - puts(">\n"); - iterateChildrenConst(nodep); - puts("\n"); - } else { - puts("/>\n"); - } - } - - // VISITORS - void visit(AstAssignW* nodep) override { - outputTag(nodep, "contassign"); // IEEE: vpiContAssign - outputChildrenEnd(nodep, "contassign"); - } - void visit(AstCell* nodep) override { - outputTag(nodep, "instance"); // IEEE: vpiInstance - puts(" defName="); - putsQuoted(nodep->modName()); // IEEE vpiDefName - puts(" origName="); - putsQuoted(nodep->origName()); - outputChildrenEnd(nodep, "instance"); - } - void visit(AstNodeIf* nodep) override { - outputTag(nodep, "if"); - puts(">\n"); - iterateAndNextConstNull(nodep->condp()); - puts("\n"); - iterateAndNextConstNull(nodep->thensp()); - puts("\n"); - if (nodep->elsesp()) { - puts("\n"); - iterateAndNextConstNull(nodep->elsesp()); - puts("\n"); - } - puts("\n"); - } - void visit(AstLoop* nodep) override { - outputTag(nodep, "loop"); - puts(">\n"); - if (nodep->stmtsp()) { - puts("\n"); - iterateAndNextConstNull(nodep->stmtsp()); - puts("\n"); - } - if (nodep->contsp()) { - puts("\n"); - iterateAndNextConstNull(nodep->contsp()); - puts("\n"); - } - puts("\n"); - } - void visit(AstLoopTest* nodep) override { - outputTag(nodep, "looptest"); - puts(">\n"); - iterateAndNextConstNull(nodep->condp()); - puts("\n"); - } - void visit(AstNetlist* nodep) override { - puts("\n"); - iterateChildrenConst(nodep); - puts("\n"); - } - void visit(AstConstPool* nodep) override { - if (!v3Global.opt.xmlOnly()) { - puts("\n"); - iterateChildrenConst(nodep); - puts("\n"); - } - } - void visit(AstInitArray* nodep) override { - puts("\n"); - const auto& mapr = nodep->map(); - for (const auto& itr : mapr) { - puts("\n"); - iterateChildrenConst(itr.second); - puts("\n"); - } - puts("\n"); - } - void visit(AstNodeModule* nodep) override { - outputTag(nodep, ""); - puts(" origName="); - putsQuoted(nodep->origName()); - if (nodep->isTop()) puts(" topModule=\"1\""); // IEEE vpiTopModule - if (nodep->modPublic()) puts(" public=\"true\""); - outputChildrenEnd(nodep, ""); - } - void visit(AstVar* nodep) override { - const VVarType typ = nodep->varType(); - const string kw = nodep->verilogKwd(); - const string vt = nodep->dtypep() ? nodep->dtypep()->name() : ""; - outputTag(nodep, ""); - if (nodep->isIO()) { - puts(" dir="); - putsQuoted(kw); - if (nodep->pinNum() != 0) puts(" pinIndex=\"" + cvtToStr(nodep->pinNum()) + "\""); - puts(" vartype="); - putsQuoted(!vt.empty() ? vt : typ == VVarType::PORT ? "port" : "unknown"); - } else { - puts(" vartype="); - putsQuoted(!vt.empty() ? vt : kw); - } - puts(" origName="); - putsQuoted(nodep->origName()); - // Attributes - if (nodep->attrIsolateAssign()) puts(" isolate_assignments=\"true\""); - if (nodep->isLatched()) puts(" latched=\"true\""); - if (nodep->isSigPublic()) puts(" public=\"true\""); - if (nodep->isSigUserRdPublic()) puts(" public_flat_rd=\"true\""); - if (nodep->isSigUserRWPublic()) puts(" public_flat_rw=\"true\""); - if (nodep->isGParam()) { - puts(" param=\"true\""); - } else if (nodep->isParam()) { - puts(" localparam=\"true\""); - } - if (nodep->attrScBv()) puts(" sc_bv=\"true\""); - if (nodep->attrSFormat()) puts(" sformat=\"true\""); - outputChildrenEnd(nodep, ""); - } - void visit(AstPin* nodep) override { - // What we call a pin in verilator is a port in the IEEE spec. - outputTag(nodep, "port"); // IEEE: vpiPort - if (nodep->modVarp() && nodep->modVarp()->isIO()) { - puts(" direction=\"" + nodep->modVarp()->direction().xmlKwd() + "\""); - } - puts(" portIndex=\"" + cvtToStr(nodep->pinNum()) + "\""); // IEEE: vpiPortIndex - // Children includes vpiHighConn and vpiLowConn; we don't support port bits (yet?) - outputChildrenEnd(nodep, "port"); - } - void visit(AstSenItem* nodep) override { - outputTag(nodep, ""); - puts(" edgeType=\"" + cvtToStr(nodep->edgeType().ascii()) + "\""); // IEEE vpiTopModule - outputChildrenEnd(nodep, ""); - } - void visit(AstModportVarRef* nodep) override { - // Dump direction for Modport references - const string kw = nodep->direction().xmlKwd(); - outputTag(nodep, ""); - puts(" direction="); - putsQuoted(kw); - outputChildrenEnd(nodep, ""); - } - void visit(AstVarXRef* nodep) override { - outputTag(nodep, ""); - puts(" dotted="); - putsQuoted(nodep->dotted()); - outputChildrenEnd(nodep, ""); - } - void visit(AstNodeCCall* nodep) override { - outputTag(nodep, ""); - puts(" func="); - putsQuoted(nodep->funcp() ? nodep->funcp()->name() : nodep->name()); - outputChildrenEnd(nodep, ""); - } - void visit(AstSel* nodep) override { - outputTag(nodep, ""); - puts(" widthConst=\"" + cvtToStr(nodep->widthConst()) + "\""); - outputChildrenEnd(nodep, ""); - } - - // Data types - void visit(AstBasicDType* nodep) override { - outputTag(nodep, "basicdtype"); - if (nodep->isRanged()) { - puts(" left=\"" + cvtToStr(nodep->left()) + "\""); - puts(" right=\"" + cvtToStr(nodep->right()) + "\""); - } - if (nodep->isSigned()) puts(" signed=\"true\""); - puts("/>\n"); - } - void visit(AstIfaceRefDType* nodep) override { - string mpn; - outputTag(nodep, ""); - if (nodep->isModport()) mpn = nodep->modportName(); - puts(" modportname="); - putsQuoted(mpn); - outputChildrenEnd(nodep, ""); - } - void visit(AstDisplay* nodep) override { - outputTag(nodep, ""); - puts(" displaytype="); - putsQuoted(nodep->verilogKwd()); - outputChildrenEnd(nodep, ""); - } - void visit(AstElabDisplay* nodep) override { - outputTag(nodep, ""); - puts(" displaytype="); - putsQuoted(nodep->verilogKwd()); - outputChildrenEnd(nodep, ""); - } - void visit(AstExtend* nodep) override { - outputTag(nodep, ""); - puts(" width="); - putsQuoted(cvtToStr(nodep->width())); - puts(" widthminv="); - putsQuoted(cvtToStr(nodep->lhsp()->widthMinV())); - outputChildrenEnd(nodep, ""); - } - void visit(AstExtendS* nodep) override { - outputTag(nodep, ""); - puts(" width="); - putsQuoted(cvtToStr(nodep->width())); - puts(" widthminv="); - putsQuoted(cvtToStr(nodep->lhsp()->widthMinV())); - outputChildrenEnd(nodep, ""); - } - - // Default - void visit(AstNode* nodep) override { - outputTag(nodep, ""); - outputChildrenEnd(nodep, ""); - } - -public: - EmitXmlFileVisitor(AstNode* nodep, V3OutFile* ofp) - : m_ofp{ofp} { - iterateConst(nodep); - } - ~EmitXmlFileVisitor() override = default; -}; - -//###################################################################### -// List of module files xml visitor - -class ModuleFilesXmlVisitor final : public VNVisitorConst { - // MEMBERS - std::ostream& m_os; - std::set m_modulesCovered; - std::deque m_nodeModules; - - // METHODS - - // VISITORS - void visit(AstNetlist* nodep) override { - // Children are iterated backwards to ensure correct compilation order - iterateChildrenBackwardsConst(nodep); - } - void visit(AstNodeModule* nodep) override { - // Only list modules and interfaces - // Assumes modules and interfaces list is already sorted level wise - if (!nodep->dead() && (VN_IS(nodep, Module) || VN_IS(nodep, Iface)) - && m_modulesCovered.insert(nodep->fileline()->filename()).second) { - m_nodeModules.push_front(nodep->fileline()); - } - } - //----- - void visit(AstNode*) override { - // All modules are present at root so no need to iterate on children - } - -public: - // CONSTRUCTORS - ModuleFilesXmlVisitor(AstNetlist* nodep, std::ostream& os) - : m_os(os) { // Need () or GCC 4.8 false warning - // Operate on whole netlist - iterateConst(nodep); - // Xml output - m_os << "\n"; - for (const FileLine* ifp : m_nodeModules) { - m_os << "filenameLetters() << "\" filename=\"" - << ifp->filenameEsc() << "\" language=\"" << ifp->language().ascii() << "\"/>\n"; - } - m_os << "\n"; - } - ~ModuleFilesXmlVisitor() override = default; -}; - -//###################################################################### -// Hierarchy of Cells visitor - -class HierCellsXmlVisitor final : public VNVisitorConst { - // MEMBERS - std::ostream& m_os; - std::string m_hier; - bool m_hasChildren = false; - - // METHODS - - // VISITORS - void visit(AstConstPool*) override {} - - void visit(AstNodeModule* nodep) override { - if (nodep->level() >= 0 && nodep->isTop()) { - m_os << "\n"; - m_os << "fileline()->xmlDetailedLocation() // - << " name=\"" << nodep->prettyName() << "\"" << " submodname=\"" - << nodep->prettyName() << "\"" << " hier=\"" << nodep->prettyName() << "\""; - m_hier = nodep->prettyName() + "."; - m_hasChildren = false; - iterateChildrenConst(nodep); - if (m_hasChildren) { - m_os << "\n"; - } else { - m_os << "/>\n"; - } - m_os << "\n"; - } - } - void visit(AstCell* nodep) override { - if (nodep->modp() && nodep->modp()->dead()) return; - if (!m_hasChildren) m_os << ">\n"; - m_os << "fileline()->xmlDetailedLocation() << " name=\"" << nodep->name() - << "\"" << " submodname=\"" << nodep->modName() << "\"" << " hier=\"" - << m_hier + nodep->name() << "\""; - const std::string hier = m_hier; - m_hier += nodep->name() + "."; - m_hasChildren = false; - iterateChildrenConst(nodep->modp()); - if (m_hasChildren) { - m_os << "\n"; - } else { - m_os << "/>\n"; - } - m_hier = hier; - m_hasChildren = true; - } - void visit(AstGenBlock* nodep) override { - VL_RESTORER(m_hier); - if (nodep->name() != "") m_hier += nodep->name() + "."; - iterateChildrenConst(nodep); - } - void visit(AstBegin* nodep) override { - VL_RESTORER(m_hier); - if (nodep->name() != "") m_hier += nodep->name() + "."; - iterateChildrenConst(nodep); - } - //----- - void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } - -public: - // CONSTRUCTORS - HierCellsXmlVisitor(AstNetlist* nodep, std::ostream& os) - : m_os(os) { // Need () or GCC 4.8 false warning - iterateConst(nodep); - } - ~HierCellsXmlVisitor() override = default; -}; - -//###################################################################### -// EmitXml class functions - -void V3EmitXml::emitxml() { - UINFO(2, __FUNCTION__ << ":"); - // All-in-one file - const string filename = (v3Global.opt.xmlOutput().empty() - ? v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + ".xml" - : v3Global.opt.xmlOutput()); - V3OutXmlFile of{filename}; - of.putsHeader(); - of.puts("\n"); - of.puts("\n"); - { - std::stringstream sstr; - FileLine::fileNameNumMapDumpXml(sstr); - of.puts(sstr.str()); - } - { - std::stringstream sstr; - const ModuleFilesXmlVisitor moduleFilesVisitor{v3Global.rootp(), sstr}; - const HierCellsXmlVisitor cellsVisitor{v3Global.rootp(), sstr}; - of.puts(sstr.str()); - } - const EmitXmlFileVisitor visitor{v3Global.rootp(), &of}; - of.puts("\n"); -} diff --git a/src/V3Error.cpp b/src/V3Error.cpp index 3c5787461..6dc1f1faa 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Error.h b/src/V3Error.h index 4be730016..b88c50545 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -122,6 +122,7 @@ public: INFINITELOOP, // Infinite loop INITIALDLY, // Initial delayed statement INSECURE, // Insecure options + INSIDETRUE, // Inside range is always true LATCH, // Latch detected outside of always_latch block LITENDIAN, // Little endian, renamed to ASCRANGE MINTYPMAXDLY, // Unsupported: min/typ/max delay expressions @@ -169,6 +170,7 @@ public: UNOPTFLAT, // Unoptimizable block after flattening UNOPTTHREADS, // Thread partitioner unable to fill all requested threads UNPACKED, // Unsupported unpacked + UNSATCONSTR, // Unsatisfied constraint UNSIGNED, // Comparison is constant due to unsigned arithmetic UNUSED, // Unused genvar, parameter or signal message (Backward Compatibility) UNUSEDGENVAR, // No receivers for genvar @@ -223,18 +225,18 @@ public: "ENCAPSULATED", "ENDLABEL", "ENUMITEMWIDTH", "ENUMVALUE", "EOFNEWLINE", "FUNCTIMECTL", "GENCLK", "GENUNNAMED", "HIERBLOCK", "HIERPARAM", "IFDEPTH", "IGNOREDRETURN", "IMPERFECTSCH", "IMPLICIT", "IMPLICITSTATIC", "IMPORTSTAR", "IMPURE", "INCABSPATH", - "INFINITELOOP", "INITIALDLY", "INSECURE", "LATCH", "LITENDIAN", "MINTYPMAXDLY", - "MISINDENT", "MODDUP", "MODMISSING", "MULTIDRIVEN", "MULTITOP", "NEWERSTD", "NOEFFECT", - "NOLATCH", "NONSTD", "NORETURN", "NULLPORT", "PARAMNODEFAULT", "PINCONNECTEMPTY", - "PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", "PREPROCZERO", "PROCASSINIT", - "PROCASSWIRE", "PROFOUTOFDATE", "PROTECTED", "PROTOTYPEMIS", "RANDC", "REALCVT", - "REDEFMACRO", "RISEFALLDLY", "SELRANGE", "SHORTREAL", "SIDEEFFECT", "SPECIFYIGN", - "SPLITVAR", "STATICVAR", "STMTDLY", "SUPERNFIRST", "SYMRSVDWORD", "SYNCASYNCNET", - "TICKCOUNT", "TIMESCALEMOD", "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNOPTTHREADS", - "UNPACKED", "UNSIGNED", "UNUSED", "UNUSEDGENVAR", "UNUSEDLOOP", "UNUSEDPARAM", - "UNUSEDSIGNAL", "USERERROR", "USERFATAL", "USERINFO", "USERWARN", "VARHIDDEN", - "WAITCONST", "WIDTH", "WIDTHCONCAT", "WIDTHEXPAND", "WIDTHTRUNC", "WIDTHXZEXPAND", - "ZERODLY", "ZEROREPL", " MAX"}; + "INFINITELOOP", "INITIALDLY", "INSECURE", "INSIDETRUE", "LATCH", "LITENDIAN", + "MINTYPMAXDLY", "MISINDENT", "MODDUP", "MODMISSING", "MULTIDRIVEN", "MULTITOP", + "NEWERSTD", "NOEFFECT", "NOLATCH", "NONSTD", "NORETURN", "NULLPORT", "PARAMNODEFAULT", + "PINCONNECTEMPTY", "PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", + "PREPROCZERO", "PROCASSINIT", "PROCASSWIRE", "PROFOUTOFDATE", "PROTECTED", + "PROTOTYPEMIS", "RANDC", "REALCVT", "REDEFMACRO", "RISEFALLDLY", "SELRANGE", + "SHORTREAL", "SIDEEFFECT", "SPECIFYIGN", "SPLITVAR", "STATICVAR", "STMTDLY", + "SUPERNFIRST", "SYMRSVDWORD", "SYNCASYNCNET", "TICKCOUNT", "TIMESCALEMOD", "UNDRIVEN", + "UNOPT", "UNOPTFLAT", "UNOPTTHREADS", "UNPACKED", "UNSATCONSTR", "UNSIGNED", "UNUSED", + "UNUSEDGENVAR", "UNUSEDLOOP", "UNUSEDPARAM", "UNUSEDSIGNAL", "USERERROR", "USERFATAL", + "USERINFO", "USERWARN", "VARHIDDEN", "WAITCONST", "WIDTH", "WIDTHCONCAT", + "WIDTHEXPAND", "WIDTHTRUNC", "WIDTHXZEXPAND", "ZERODLY", "ZEROREPL", " MAX"}; return names[m_e]; } // Warnings that default to off diff --git a/src/V3ExecGraph.cpp b/src/V3ExecGraph.cpp index d2a5ef922..f201cc6b5 100644 --- a/src/V3ExecGraph.cpp +++ b/src/V3ExecGraph.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -917,6 +917,7 @@ void addMTaskToFunction(const ThreadSchedule& schedule, const uint32_t threadId, AstBasicDType* const s_mtaskStateDtypep = v3Global.rootp()->typeTablep()->findBasicDType(fl, VBasicDTypeKwd::MTASKSTATE); AstVar* const varp = new AstVar{fl, VVarType::MODULETEMP, name, s_mtaskStateDtypep}; + varp->isConst(true); varp->valuep(new AstConst{fl, nDependencies}); varp->protect(false); // Do not protect as we have references in text modp->addStmtsp(varp); @@ -998,6 +999,7 @@ const std::vector createThreadFunctions(const ThreadSchedule& schedul AstVar* const varp = new AstVar{fl, VVarType::MODULETEMP, "__Vm_mtaskstate_final__" + cvtToStr(schedule.id()) + tag, s_mtaskStateDtypep}; + varp->isConst(true); varp->valuep(new AstConst(fl, funcps.size())); varp->protect(false); // Do not protect as we have references in text modp->addStmtsp(varp); diff --git a/src/V3ExecGraph.h b/src/V3ExecGraph.h index a81c8b6dd..906d744c0 100644 --- a/src/V3ExecGraph.h +++ b/src/V3ExecGraph.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp index fe0d02ea1..0eb724ea5 100644 --- a/src/V3Expand.cpp +++ b/src/V3Expand.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -71,7 +71,10 @@ public: class ExpandVisitor final : public VNVisitor { // NODE STATE // AstNode::user1() -> bool. Processed + // AstNode::user2() -> See ExpandOkVisitor + // AstVar::user3() -> bool. Is a constant pool variable const VNUser1InUse m_inuser1; + const VNUser3InUse m_inuser3; // STATE - for current visit position (use VL_RESTORER) AstNode* m_stmtp = nullptr; // Current statement @@ -313,6 +316,9 @@ class ExpandVisitor final : public VNVisitor { //-------- Uniops bool expandWide(AstNodeAssign* nodep, AstVarRef* rhsp) { UINFO(8, " Wordize ASSIGN(VARREF) " << nodep); + // Special case: do not expand assignment of constant pool variables. + // V3Subst undestands these directly. + if (rhsp->varp()->user3()) return false; if (!doExpandWide(nodep)) return false; for (int w = 0; w < nodep->widthWords(); ++w) { addWordAssign(nodep, w, newAstWordSelClone(rhsp, w)); @@ -373,6 +379,47 @@ class ExpandVisitor final : public VNVisitor { } return true; } + bool expandWideShift(AstNodeAssign* nodep, AstNodeBiop* rhsp, bool isLeftShift) { + if (!doExpandWide(nodep)) return false; + + // Simplify the shift amount, in case it becomes a constant + V3Const::constifyEditCpp(rhsp->rhsp()); + + // If it's a constant shift by whole words, expand it so V3Subst can substitute it + if (const AstConst* const rhsConstp = VN_CAST(rhsp->rhsp(), Const)) { + const uint32_t shiftBits = rhsConstp->toUInt(); + if (VL_BITBIT_E(shiftBits) == 0) { + const int widthWords = nodep->widthWords(); + const int shiftWords = std::min(VL_BITWORD_E(shiftBits), widthWords); + FileLine* const flp = rhsp->fileline(); + if (isLeftShift) { + UINFO(8, " Wordize ASSIGN(SHIFTL,words) " << nodep); + // Low words of the result are zero + for (int w = 0; w < shiftWords; ++w) { + addWordAssign(nodep, w, new AstConst{flp, AstConst::SizedEData{}, 0}); + } + // High words of the result are copied from higher words of the source + for (int w = shiftWords; w < widthWords; ++w) { + addWordAssign(nodep, w, newAstWordSelClone(rhsp->lhsp(), w - shiftWords)); + } + } else { + UINFO(8, " Wordize ASSIGN(SHIFTR,words) " << nodep); + // Low words of the result are copied from higher words of the source + for (int w = 0; w < widthWords - shiftWords; ++w) { + addWordAssign(nodep, w, newAstWordSelClone(rhsp->lhsp(), w + shiftWords)); + } + // High words of the result are zero + for (int w = widthWords - shiftWords; w < widthWords; ++w) { + addWordAssign(nodep, w, new AstConst{flp, AstConst::SizedEData{}, 0}); + } + } + return true; + } + } + + return false; + } + //-------- Triops bool expandWide(AstNodeAssign* nodep, AstCond* rhsp) { UINFO(8, " Wordize ASSIGN(COND) " << nodep); @@ -388,6 +435,15 @@ class ExpandVisitor final : public VNVisitor { } // VISITORS + void visit(AstNetlist* nodep) override { + // Mark constant pool variables + for (AstNode* np = nodep->constPoolp()->modp()->stmtsp(); np; np = np->nextp()) { + if (VN_IS(np, Var)) np->user3(true); + } + + iterateAndNextNull(nodep->modulesp()); + } + void visit(AstCFunc* nodep) override { VL_RESTORER(m_funcp); VL_RESTORER(m_nTmps); @@ -1026,7 +1082,7 @@ class ExpandVisitor final : public VNVisitor { m_stmtp = nodep; iterateChildren(nodep); bool did = false; - if (nodep->isWide() && ((VN_IS(nodep->lhsp(), VarRef) || VN_IS(nodep->lhsp(), ArraySel))) + if (nodep->isWide() // && ((VN_IS(nodep->lhsp(), VarRef) || VN_IS(nodep->lhsp(), ArraySel))) && !AstVar::scVarRecurse(nodep->lhsp()) // Need special function for SC && !AstVar::scVarRecurse(nodep->rhsp())) { @@ -1052,6 +1108,10 @@ class ExpandVisitor final : public VNVisitor { did = expandWide(nodep, rhsp); } else if (AstXor* const rhsp = VN_CAST(nodep->rhsp(), Xor)) { did = expandWide(nodep, rhsp); + } else if (AstShiftL* const rhsp = VN_CAST(nodep->rhsp(), ShiftL)) { + did = expandWideShift(nodep, rhsp, /* isLeftShift: */ true); + } else if (AstShiftR* const rhsp = VN_CAST(nodep->rhsp(), ShiftR)) { + did = expandWideShift(nodep, rhsp, /* isLeftShift: */ false); } else if (AstCond* const rhsp = VN_CAST(nodep->rhsp(), Cond)) { did = expandWide(nodep, rhsp); } diff --git a/src/V3Expand.h b/src/V3Expand.h index bf6838fd2..69ce46732 100644 --- a/src/V3Expand.h +++ b/src/V3Expand.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3File.cpp b/src/V3File.cpp index 75d0e472b..34f1e8597 100644 --- a/src/V3File.cpp +++ b/src/V3File.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3File.h b/src/V3File.h index 2fc9ca3c5..666736414 100644 --- a/src/V3File.h +++ b/src/V3File.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3FileLine.cpp b/src/V3FileLine.cpp index c202caf1a..4e82a497e 100644 --- a/src/V3FileLine.cpp +++ b/src/V3FileLine.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -77,18 +77,6 @@ FileLineSingleton::fileNameIdx_t FileLineSingleton::nameToNumber(const string& f return idx; } -//! Support XML output -//! Experimental. Updated to also put out the language. -void FileLineSingleton::fileNameNumMapDumpXml(std::ostream& os) { - os << "\n"; - for (const auto& itr : m_namemap) { - os << "\n"; - } - os << "\n"; -} - void FileLineSingleton::fileNameNumMapDumpJson(std::ostream& os) { std::string sep = "\n "; os << "\"files\": {"; @@ -241,12 +229,6 @@ void FileLine::newContent() { m_contentLineno = 1; } -string FileLine::xmlDetailedLocation() const { - return "loc=\"" + cvtToStr(filenameLetters()) + "," + cvtToStr(firstLineno()) + "," - + cvtToStr(firstColumn()) + "," + cvtToStr(lastLineno()) + "," + cvtToStr(lastColumn()) - + "\""; -} - string FileLine::lineDirectiveStrg(int enterExit) const { return "`line "s + cvtToStr(lastLineno()) + " \"" + V3OutFormatter::quoteNameControls(filename()) + "\" " + cvtToStr(enterExit) + '\n'; diff --git a/src/V3FileLine.h b/src/V3FileLine.h index 486588e23..40c28ec1d 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -135,7 +135,6 @@ class FileLineSingleton final { m_names.clear(); m_languages.clear(); } - void fileNameNumMapDumpXml(std::ostream& os); void fileNameNumMapDumpJson(std::ostream& os); static string filenameLetters(fileNameIdx_t fileno) VL_PURE; @@ -368,7 +367,6 @@ public: string filebasenameNoExt() const; string firstColumnLetters() const VL_MT_SAFE; string profileFuncname() const; - string xmlDetailedLocation() const; string lineDirectiveStrg(int enterExit) const; // Turn on/off warning messages on this line. @@ -410,7 +408,6 @@ public: static string globalWarnOffParse(const string& msgs, bool turnOff) { return defaultFileLine().warnOffParse(msgs, turnOff); } - static void fileNameNumMapDumpXml(std::ostream& os) { singleton().fileNameNumMapDumpXml(os); } static void fileNameNumMapDumpJson(std::ostream& os) { singleton().fileNameNumMapDumpJson(os); } diff --git a/src/V3Force.cpp b/src/V3Force.cpp index 02e0076dc..7f3a4f8b5 100644 --- a/src/V3Force.cpp +++ b/src/V3Force.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -47,6 +47,7 @@ #include "V3Force.h" #include "V3AstUserAllocator.h" +#include "V3UniqueNames.h" VL_DEFINE_DEBUG_FUNCTIONS; @@ -78,10 +79,12 @@ public: AstVarScope* const m_rdVscp; // New variable to replace read references with AstVarScope* const m_valVscp; // Forced value AstVarScope* const m_enVscp; // Force enabled signal + V3UniqueNames m_iterNames; // Names for loop iteration variables explicit ForceComponentsVarScope(AstVarScope* vscp, ForceComponentsVar& fcv) : m_rdVscp{new AstVarScope{vscp->fileline(), vscp->scopep(), fcv.m_rdVarp}} , m_valVscp{new AstVarScope{vscp->fileline(), vscp->scopep(), fcv.m_valVarp}} - , m_enVscp{new AstVarScope{vscp->fileline(), vscp->scopep(), fcv.m_enVarp}} { + , m_enVscp{new AstVarScope{vscp->fileline(), vscp->scopep(), fcv.m_enVarp}} + , m_iterNames{"__VForceIter"} { m_rdVscp->addNext(m_enVscp); m_rdVscp->addNext(m_valVscp); vscp->addNextHere(m_rdVscp); @@ -94,63 +97,30 @@ public: activeInitp->senTreeStorep(activeInitp->sentreep()); vscp->scopep()->addBlocksp(activeInitp); - AstVarRef* const enRefp = new AstVarRef{flp, m_enVscp, VAccess::WRITE}; + // Create statements that update __Rd variable. + // These nodes will be copied and used also for __En initialization + AstVarRef* const rdRefp = new AstVarRef{flp, m_rdVscp, VAccess::WRITE}; + std::vector assigns; + AstNodeStmt* const rdUpdateStmtsp + = getForcedUpdateStmtsRecursep(rdRefp, vscp, rdRefp, assigns); - AstNodeStmt* toInsertp = nullptr; - AstNodeStmt* outerStmtp = nullptr; - std::vector loopVarRefs; - if (VN_IS(enRefp->dtypep()->skipRefp(), UnpackArrayDType)) { - // Create a loop to set all elements of __VforceEn array to 0. - // That loop node is then copied and used for updating elements of __VforceRd array - if (AstUnpackArrayDType* const unpackedp - = VN_CAST(m_rdVscp->varp()->dtypep(), UnpackArrayDType)) { - std::vector dims = unpackedp->unpackDimensions(); - loopVarRefs.reserve(dims.size()); - for (size_t i = 0; i < dims.size(); i++) { - AstVar* const loopVarp = new AstVar{ - flp, VVarType::MODULETEMP, - m_rdVscp->varp()->name() + "__VwhileIter" + std::to_string(i), - VFlagBitPacked{}, 32}; - m_rdVscp->varp()->addNext(loopVarp); - AstVarScope* const loopVarScopep - = new AstVarScope{flp, m_rdVscp->scopep(), loopVarp}; - m_rdVscp->addNext(loopVarScopep); - AstVarRef* const readRefp - = new AstVarRef{flp, loopVarScopep, VAccess::READ}; - loopVarRefs.push_back(readRefp); - AstNodeStmt* const currInitp - = new AstAssign{flp, new AstVarRef{flp, loopVarScopep, VAccess::WRITE}, - new AstConst{flp, 0}}; - if (toInsertp) { - toInsertp->addNextHere(currInitp); - } else { - outerStmtp = currInitp; - } - AstLoop* const currWhilep = new AstLoop{flp}; - currInitp->addNextHere(currWhilep); - AstLoopTest* const loopTestp = new AstLoopTest{ - flp, currWhilep, - new AstNeq{flp, readRefp, - new AstConst{ - flp, static_cast(dims[i]->elementsConst())}}}; - currWhilep->addStmtsp(loopTestp); - toInsertp = loopTestp; - AstAssign* const currIncrp = new AstAssign{ - flp, new AstVarRef{flp, loopVarScopep, VAccess::WRITE}, - new AstAdd{flp, readRefp->cloneTree(false), new AstConst{flp, 1}}}; - currWhilep->addStmtsp(currIncrp); - } - } + // To use these statements for __En initialization, replace references to __Rd with + // ones to __En and replace assignments RHS with 0 + AstNodeStmt* const enInitStmtsp = rdUpdateStmtsp->cloneTree(true); + for (size_t i = 0; i < assigns.size(); i++) { + // Save copies, because clonep() works only after the last cloneTree + assigns[i] = assigns[i]->clonep(); } - V3Number zero{m_enVscp, m_enVscp->width()}; - AstNodeExpr* const enRhsp = new AstConst{flp, zero}; - AstNodeExpr* enLhsp = applySelects(enRefp, loopVarRefs); - AstNodeStmt* stmtp = new AstAssign{flp, enLhsp, enRhsp}; - if (toInsertp) { - toInsertp->addNextHere(stmtp); - stmtp = outerStmtp; + for (AstAssign* const assignp : assigns) { + AstVarRef* const lhsVarRefp + = VN_AS(AstNodeVarRef::varRefLValueRecurse(assignp->lhsp()), VarRef); + lhsVarRefp->replaceWith(new AstVarRef{flp, m_enVscp, VAccess::WRITE}); + lhsVarRefp->deleteTree(); + assignp->rhsp()->unlinkFrBack()->deleteTree(); + V3Number zero{m_enVscp, assignp->lhsp()->dtypep()->width()}; + assignp->rhsp(new AstConst{flp, zero}); } - activeInitp->addStmtsp(new AstInitial{flp, stmtp->cloneTree(true)}); + activeInitp->addStmtsp(new AstInitial{flp, enInitStmtsp}); { // Add the combinational override // Explicitly list dependencies for update. // Note: rdVscp is also needed to retrigger assignment for the first time. @@ -167,48 +137,105 @@ public: = new AstActive{flp, "force-update", new AstSenTree{flp, itemsp}}; activep->senTreeStorep(activep->sentreep()); - // Reuse the statements created for __VforceEn initialization - // and replace var ref on the LHS and the RHS - AstVarRef* const rdRefp = new AstVarRef{flp, m_rdVscp, VAccess::WRITE}; - AstNodeExpr* const rdRhsp = forcedUpdate(vscp, loopVarRefs); - enRefp->replaceWith(rdRefp); - VL_DO_DANGLING(enRefp->deleteTree(), enRefp); - enRhsp->replaceWith(rdRhsp); - VL_DO_DANGLING(enRhsp->deleteTree(), enRhsp); - - activep->addStmtsp(new AstAlways{flp, VAlwaysKwd::ALWAYS, nullptr, stmtp}); + activep->addStmtsp( + new AstAlways{flp, VAlwaysKwd::ALWAYS, nullptr, rdUpdateStmtsp}); vscp->scopep()->addBlocksp(activep); } } - static AstNodeExpr* applySelects(AstNodeExpr* exprp, - const std::vector& selectExprs) { - for (AstNodeExpr* const sp : selectExprs) { - exprp = new AstArraySel{exprp->fileline(), exprp, sp->cloneTreePure(false)}; + AstNodeStmt* getForcedUpdateStmtsRecursep(AstNodeExpr* const lhsp, AstVarScope* const vscp, + AstVarRef* const lhsVarRefp, + std::vector& assigns) { + // Create stataments that update values of __Rd variable. + // lhsp is either a reference to that variable or ArraySel or MemberSel on it. + // lhsVarRefp is a reference to that variable in lhsp subtree. + // assigns is a vector to which all assignments to __Rd are added. + FileLine* const flp = lhsp->fileline(); + const AstNodeDType* const lhsDtypep = lhsp->dtypep()->skipRefp(); + if (lhsDtypep->isIntegralOrPacked() || VN_IS(lhsDtypep, BasicDType)) { + AstAssign* const assignp + = new AstAssign{flp, lhsp, forcedUpdate(vscp, lhsp, lhsVarRefp)}; + assigns.push_back(assignp); + return assignp; + } else if (const AstStructDType* const structDtypep + = VN_CAST(lhsDtypep, StructDType)) { + AstNodeStmt* stmtsp = nullptr; + bool firstIter = true; + for (AstMemberDType* mdtp = structDtypep->membersp(); mdtp; + mdtp = VN_AS(mdtp->nextp(), MemberDType)) { + AstNodeExpr* const lhsCopyp = firstIter ? lhsp : lhsp->cloneTreePure(false); + AstVarRef* const lhsVarRefCopyp + = firstIter ? lhsVarRefp : lhsVarRefp->clonep(); + AstStructSel* const structSelp = new AstStructSel{flp, lhsCopyp, mdtp->name()}; + structSelp->dtypep(mdtp); + AstNodeStmt* const memberStmtp + = getForcedUpdateStmtsRecursep(structSelp, vscp, lhsVarRefCopyp, assigns); + stmtsp = firstIter ? memberStmtp : stmtsp->addNext(memberStmtp); + firstIter = false; + } + return stmtsp; + } else if (const AstUnpackArrayDType* const arrayDtypep + = VN_CAST(lhsDtypep, UnpackArrayDType)) { + AstVar* const loopVarp + = new AstVar{flp, VVarType::MODULETEMP, + m_iterNames.get(m_rdVscp->varp()->name()), VFlagBitPacked{}, 32}; + m_rdVscp->varp()->addNext(loopVarp); + AstVarScope* const loopVarScopep + = new AstVarScope{flp, m_rdVscp->scopep(), loopVarp}; + m_rdVscp->addNext(loopVarScopep); + AstVarRef* const readRefp = new AstVarRef{flp, loopVarScopep, VAccess::READ}; + AstNodeStmt* const currInitp = new AstAssign{ + flp, new AstVarRef{flp, loopVarScopep, VAccess::WRITE}, new AstConst{flp, 0}}; + AstLoop* const currWhilep = new AstLoop{flp}; + currInitp->addNextHere(currWhilep); + AstLoopTest* const loopTestp = new AstLoopTest{ + flp, currWhilep, + new AstNeq{ + flp, readRefp, + new AstConst{flp, static_cast(arrayDtypep->elementsConst())}}}; + currWhilep->addStmtsp(loopTestp); + AstArraySel* const lhsSelp + = new AstArraySel{flp, lhsp, readRefp->cloneTree(false)}; + AstNodeStmt* const loopBodyp + = getForcedUpdateStmtsRecursep(lhsSelp, vscp, lhsVarRefp, assigns); + currWhilep->addStmtsp(loopBodyp); + AstAssign* const currIncrp = new AstAssign{ + flp, new AstVarRef{flp, loopVarScopep, VAccess::WRITE}, + new AstAdd{flp, readRefp->cloneTree(false), new AstConst{flp, 1}}}; + currWhilep->addStmtsp(currIncrp); + return currInitp; + } else { + lhsDtypep->v3fatalSrc("Unhandled type"); } - return exprp; } - AstNodeExpr* forcedUpdate(AstVarScope* const vscp, - const std::vector& selectExprs) const { + static AstNodeExpr* wrapIntoExprp(AstVarRef* const refp, AstNodeExpr* const exprp, + AstVarRef* const varRefToReplacep) { + // Return a copy of exprp in which varRefToReplacep is replaced with refp + if (exprp == varRefToReplacep) { + return refp; + } else { + AstNodeExpr* const copiedExprp = exprp->cloneTreePure(false); + AstNode* const oldRefp = varRefToReplacep->clonep(); + varRefToReplacep->clonep()->replaceWith(refp); + oldRefp->deleteTree(); + return copiedExprp; + } + } + AstNodeExpr* forcedUpdate(AstVarScope* const vscp, AstNodeExpr* exprp = nullptr, + AstVarRef* const varRefToReplacep = nullptr) const { FileLine* const flp = vscp->fileline(); AstVarRef* origRefp = new AstVarRef{flp, vscp, VAccess::READ}; ForceState::markNonReplaceable(origRefp); - AstNodeExpr* const origp = applySelects(origRefp, selectExprs); + AstNodeExpr* const origExprp = wrapIntoExprp(origRefp, exprp, varRefToReplacep); + AstNodeExpr* const enExprp = wrapIntoExprp(new AstVarRef{flp, m_enVscp, VAccess::READ}, + exprp, varRefToReplacep); + AstNodeExpr* const valExprp = wrapIntoExprp( + new AstVarRef{flp, m_valVscp, VAccess::READ}, exprp, varRefToReplacep); if (ForceState::isRangedDType(vscp)) { return new AstOr{ - flp, - new AstAnd{ - flp, - applySelects(new AstVarRef{flp, m_enVscp, VAccess::READ}, selectExprs), - applySelects(new AstVarRef{flp, m_valVscp, VAccess::READ}, selectExprs)}, - new AstAnd{ - flp, - new AstNot{flp, applySelects(new AstVarRef{flp, m_enVscp, VAccess::READ}, - selectExprs)}, - origp}}; + flp, new AstAnd{flp, enExprp, valExprp}, + new AstAnd{flp, new AstNot{flp, enExprp->cloneTreePure(false)}, origExprp}}; } - return new AstCond{ - flp, applySelects(new AstVarRef{flp, m_enVscp, VAccess::READ}, selectExprs), - applySelects(new AstVarRef{flp, m_valVscp, VAccess::READ}, selectExprs), origp}; + return new AstCond{flp, enExprp, valExprp, origExprp}; } }; @@ -229,39 +256,52 @@ private: m_valVscps; // `valVscp` force components of a forced RHS - static AstNodeDType* getEnVarpDTypep(AstVar* const varp) { + static size_t checkIfDTypeSupportedRecurse(const AstNodeDType* const dtypep, + const AstVar* const varp) { + // Checks if force stmt is supported on all subtypes + // and returns number of unpacked elements + const AstNodeDType* const dtp = dtypep->skipRefp(); + if (const AstUnpackArrayDType* const udtp = VN_CAST(dtp, UnpackArrayDType)) { + const size_t elemsInSubDType = checkIfDTypeSupportedRecurse(udtp->subDTypep(), varp); + return udtp->elementsConst() * elemsInSubDType; + } else if (const AstNodeUOrStructDType* const sdtp = VN_CAST(dtp, NodeUOrStructDType)) { + size_t elemCount = 0; + for (const AstMemberDType* mdtp = sdtp->membersp(); mdtp; + mdtp = VN_AS(mdtp->nextp(), MemberDType)) { + elemCount += checkIfDTypeSupportedRecurse(mdtp->subDTypep(), varp); + } + return elemCount; + } else if (const AstBasicDType* const bdtp = VN_CAST(dtp, BasicDType)) { + if (bdtp->isString() || bdtp->isEvent() || bdtp->keyword() == VBasicDTypeKwd::CHANDLE + || bdtp->keyword() == VBasicDTypeKwd::TIME) { + varp->v3warn(E_UNSUPPORTED, "Forcing variable of unsupported type: " + << varp->dtypep()->prettyTypeName()); + } + return 1; + } else if (!dtp->isIntegralOrPacked()) { + varp->v3warn(E_UNSUPPORTED, "Forcing variable of unsupported type: " + << varp->dtypep()->prettyTypeName()); + return 1; + } else { + // All packed types are supported + return 1; + } + } + static AstNodeDType* getEnVarpDTypep(const AstVar* const varp) { AstNodeDType* const origDTypep = varp->dtypep()->skipRefp(); + const size_t unpackElemNum = checkIfDTypeSupportedRecurse(origDTypep, varp); + if (unpackElemNum > ELEMENTS_MAX) { + varp->v3warn(E_UNSUPPORTED, "Unsupported: Force of variable with " + ">= " + << ELEMENTS_MAX << " unpacked elements"); + } if (VN_IS(origDTypep, UnpackArrayDType)) { - size_t elemNum = 1; - AstNodeDType* dtp = origDTypep; - while (AstUnpackArrayDType* const uDtp = VN_CAST(dtp, UnpackArrayDType)) { - dtp = uDtp->subDTypep()->skipRefp(); - elemNum *= uDtp->elementsConst(); - } - if (elemNum > ELEMENTS_MAX) { - varp->v3warn(E_UNSUPPORTED, "Unsupported: Force of unpacked array variable with " - ">= " - << ELEMENTS_MAX << " elements"); - } - bool complexElem = true; - if (AstBasicDType* const basicp = VN_CAST(dtp, BasicDType)) { - complexElem = basicp->isOpaque(); - } - if (complexElem) { - varp->v3warn(E_UNSUPPORTED, "Unsupported: Force of unpacked array variable with " - "elements of complex data type"); - } return origDTypep; } else if (VN_IS(origDTypep, BasicDType)) { return isRangedDType(varp) ? origDTypep : varp->findBitDType(); } else if (VN_IS(origDTypep, PackArrayDType)) { return origDTypep; - } else if (const AstNodeUOrStructDType* const sdtp - = VN_CAST(origDTypep, NodeUOrStructDType)) { - if (!sdtp->packed()) { - varp->v3warn(E_UNSUPPORTED, - "Unsupported: Force of unpacked struct / union variable"); - } + } else if (VN_IS(origDTypep, NodeUOrStructDType)) { return origDTypep; } else { varp->v3fatalSrc("Unsupported: Force of variable of unhandled data type"); @@ -275,7 +315,7 @@ public: VL_UNCOPYABLE(ForceState); // STATIC METHODS - static bool isRangedDType(AstNode* nodep) { + static bool isRangedDType(const AstNode* const nodep) { // If ranged we need a multibit enable to support bit-by-bit part-select forces, // otherwise forcing a real or other opaque dtype and need a single bit enable. const AstBasicDType* const basicp = nodep->dtypep()->skipRefp()->basicp(); @@ -416,26 +456,14 @@ class ForceConvertVisitor final : public VNVisitor { } }); // Replace write refs on RHS - if (VN_IS(resetRdp->rhsp(), ArraySel)) { - std::vector selIndices; - AstNodeExpr* exprp = resetRdp->rhsp(); - while (AstArraySel* const selp = VN_CAST(exprp, ArraySel)) { - selIndices.push_back(selp->bitp()); - exprp = selp->fromp(); - } - if (AstVarRef* const refp = VN_CAST(exprp, VarRef)) { - AstVarScope* const vscp = refp->varScopep(); - std::vector reversedIndices(selIndices.size()); - std::reverse_copy(selIndices.begin(), selIndices.end(), reversedIndices.begin()); - AstNodeExpr* const origRhsp = resetRdp->rhsp(); - origRhsp->replaceWith( - m_state.getForceComponents(vscp).forcedUpdate(vscp, reversedIndices)); - VL_DO_DANGLING(origRhsp->deleteTree(), origRhsp); - } else { - exprp->v3warn( - E_UNSUPPORTED, - "Unsupported: Release statement argument is too complex array select"); - } + if (VN_IS(resetRdp->rhsp(), ArraySel) || VN_IS(resetRdp->rhsp(), StructSel)) { + AstVarRef* const refp + = VN_AS(AstNodeVarRef::varRefLValueRecurse(resetRdp->rhsp()), VarRef); + AstVarScope* const vscp = refp->varScopep(); + AstNodeExpr* const origRhsp = resetRdp->rhsp(); + origRhsp->replaceWith( + m_state.getForceComponents(vscp).forcedUpdate(vscp, origRhsp, refp)); + VL_DO_DANGLING(origRhsp->deleteTree(), origRhsp); } else { resetRdp->rhsp()->foreach([this](AstVarRef* refp) { if (refp->access() != VAccess::WRITE) return; @@ -444,7 +472,7 @@ class ForceConvertVisitor final : public VNVisitor { refp->access(VAccess::READ); ForceState::markNonReplaceable(refp); } else { - refp->replaceWith(m_state.getForceComponents(vscp).forcedUpdate(vscp, {})); + refp->replaceWith(m_state.getForceComponents(vscp).forcedUpdate(vscp)); VL_DO_DANGLING(refp->deleteTree(), refp); } }); @@ -457,6 +485,20 @@ class ForceConvertVisitor final : public VNVisitor { void visit(AstVarScope* nodep) override { // If this signal is marked externally forceable, create the public force signals if (nodep->varp()->isForceable()) { + if (VN_IS(nodep->varp()->dtypeSkipRefp(), UnpackArrayDType)) { + nodep->varp()->v3warn( + E_UNSUPPORTED, + "Unsupported: Forcing unpacked arrays: " << nodep->varp()->name()); // (#4735) + return; + } + + const AstBasicDType* const bdtypep = nodep->varp()->basicp(); + const bool strtype = bdtypep && bdtypep->keyword() == VBasicDTypeKwd::STRING; + if (strtype) { + nodep->varp()->v3error( + "Forcing strings is not permitted: " << nodep->varp()->name()); + } + const ForceState::ForceComponentsVarScope& fc = m_state.getForceComponents(nodep); fc.m_enVscp->varp()->sigUserRWPublic(true); fc.m_valVscp->varp()->sigUserRWPublic(true); @@ -479,7 +521,6 @@ class ForceReplaceVisitor final : public VNVisitor { AstNodeStmt* m_stmtp = nullptr; bool m_inLogic = false; bool m_releaseRhs = false; // Inside RHS of assignment created for release statement - std::vector m_selIndices; // Indices of array select expressions above // METHODS void iterateLogic(AstNode* logicp) { @@ -515,12 +556,6 @@ class ForceReplaceVisitor final : public VNVisitor { iterateLogic(nodep); } void visit(AstSenItem* nodep) override { iterateLogic(nodep); } - void visit(AstArraySel* nodep) override { - m_selIndices.push_back(nodep->bitp()); - iterateChildren(nodep); - UASSERT_OBJ(m_selIndices.size(), nodep, "Underflow"); - m_selIndices.pop_back(); - } void visit(AstVarRef* nodep) override { if (ForceState::isNotReplaceable(nodep)) return; @@ -540,12 +575,26 @@ class ForceReplaceVisitor final : public VNVisitor { if (ForceState::ForceComponentsVarScope* const fcp = m_state.tryGetForceComponents(nodep)) { FileLine* const flp = nodep->fileline(); - std::vector reversedIndices(m_selIndices.size()); - std::reverse_copy(m_selIndices.begin(), m_selIndices.end(), - reversedIndices.begin()); - AstNodeExpr* const lhsp = ForceState::ForceComponentsVarScope::applySelects( - new AstVarRef{flp, fcp->m_rdVscp, VAccess::WRITE}, reversedIndices); - AstNodeExpr* const rhsp = fcp->forcedUpdate(nodep->varScopep(), reversedIndices); + AstVarRef* const lhsRefp = new AstVarRef{flp, fcp->m_rdVscp, VAccess::WRITE}; + AstNodeExpr* lhsp; + AstNodeExpr* rhsp; + if (nodep->dtypep()->skipRefp()->isIntegralOrPacked()) { + rhsp = fcp->forcedUpdate(nodep->varScopep()); + lhsp = lhsRefp; + } else { + AstNodeExpr* wholeExprp = nodep; + while (VN_IS(wholeExprp->backp(), NodeExpr)) { + wholeExprp = VN_AS(wholeExprp->backp(), NodeExpr); + // wholeExprp should never be ExprStmt, because: + // * if nodep is inside stmtsp() of one, we should sooner get NodeStmt node + // * nodep should never be in resultp(), because it is a WRITE reference + // and resultp() should be an rvalue + UASSERT_OBJ(!VN_IS(wholeExprp, ExprStmt), nodep, "Unexpected AstExprStmt"); + } + lhsp = ForceState::ForceComponentsVarScope::wrapIntoExprp(lhsRefp, wholeExprp, + nodep); + rhsp = fcp->forcedUpdate(nodep->varScopep(), wholeExprp, nodep); + } m_stmtp->addNextHere(new AstAssign{flp, lhsp, rhsp}); } // Emit valVscp update after each write to any VarRef on forced RHS. diff --git a/src/V3Force.h b/src/V3Force.h index 5d736e1ed..26b50d9c9 100644 --- a/src/V3Force.h +++ b/src/V3Force.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // diff --git a/src/V3Fork.cpp b/src/V3Fork.cpp index 29c014a2f..e5f636338 100644 --- a/src/V3Fork.cpp +++ b/src/V3Fork.cpp @@ -7,10 +7,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -47,6 +47,7 @@ #include "V3AstNodeExpr.h" #include "V3MemberMap.h" +#include #include VL_DEFINE_DEBUG_FUNCTIONS; @@ -90,7 +91,7 @@ public: m_instance.m_handlep = new AstVar{m_procp->fileline(), VVarType::BLOCKTEMP, generateDynScopeHandleName(m_procp), m_instance.m_refDTypep}; - m_instance.m_handlep->funcLocal(true); + m_instance.m_handlep->funcLocal(false); m_instance.m_handlep->lifetime(VLifetime::AUTOMATIC_EXPLICIT); UINFO(9, "new dynscope var " << m_instance.m_handlep); @@ -153,7 +154,7 @@ public: UASSERT(stmtp, "Procedure lacks body"); UASSERT(initp, "Procedure lacks statements besides declarations"); - AstNew* const newp = new AstNew{m_procp->fileline(), nullptr}; + AstNew* const newp = new AstNew{m_procp->fileline()}; newp->taskp(VN_AS(memberMap.findMember(m_instance.m_classp, "new"), NodeFTask)); newp->dtypep(m_instance.m_refDTypep); newp->classOrPackagep(m_instance.m_classp); @@ -211,7 +212,7 @@ public: private: AstAssign* instantiateDynScope(VMemberMap& memberMap) { - AstNew* const newp = new AstNew{m_procp->fileline(), nullptr}; + AstNew* const newp = new AstNew{m_procp->fileline()}; newp->taskp(VN_AS(memberMap.findMember(m_instance.m_classp, "new"), NodeFTask)); newp->dtypep(m_instance.m_refDTypep); newp->classOrPackagep(m_instance.m_classp); @@ -334,14 +335,34 @@ class DynScopeVisitor final : public VNVisitor { auto r = m_frames.emplace(nodep, framep); if (r.second) m_frameOrder.push_back(nodep); } + void bindInitIterate(AstNode* stmtsp, ForkDynScopeFrame* framep) { + for (AstNode* stmtp = stmtsp; stmtp; stmtp = stmtp->nextp()) { + if (AstAssign* const asgnp = VN_CAST(stmtp, Assign)) { + bindNodeToDynScope(asgnp->lhsp(), framep); + iterate(asgnp->rhsp()); + } else if (AstInitialAutomaticStmt* astmtp + = VN_CAST(stmtp, InitialAutomaticStmt)) { // Moves in V3Begin + // Underlying assign RHS might use function argument, so can't just + // move whole thing into the new class's constructor/statements + bindInitIterate(astmtp->stmtsp(), framep); + } else if (AstInitialStaticStmt* astmtp + = VN_CAST(stmtp, InitialStaticStmt)) { // Moves in V3Begin + bindInitIterate(astmtp->stmtsp(), framep); + } else { + stmtp->v3fatalSrc("Invalid node under block item initialization part of fork"); + } + } + } bool needsDynScope(const AstVarRef* refp) const { + const AstVar* const varp = refp->varp(); return // Can this variable escape the scope - ((m_forkDepth > refp->varp()->user1()) && refp->varp()->isFuncLocal()) + ((m_forkDepth > varp->user1()) && varp->isFuncLocal()) + && varp->lifetime().isAutomatic() && ( // Is it mutated - (refp->varp()->isClassHandleValue() ? refp->user2() : refp->access().isWriteOrRW()) + (varp->isClassHandleValue() ? refp->user2() : refp->access().isWriteOrRW()) // Or is it after a timing-control event || m_afterTimingControl); } @@ -350,6 +371,7 @@ class DynScopeVisitor final : public VNVisitor { void visit(AstNodeModule* nodep) override { VL_RESTORER(m_modp); if (!VN_IS(nodep, Class)) m_modp = nodep; + VL_RESTORER(m_id); m_id = 0; iterateChildren(nodep); } @@ -380,16 +402,14 @@ class DynScopeVisitor final : public VNVisitor { for (AstNode* declp = nodep->declsp(); declp; declp = declp->nextp()) { AstVar* const varp = VN_CAST(declp, Var); UASSERT_OBJ(varp, declp, "Invalid node under block item initialization part of fork"); - if (!framep->instance().initialized()) framep->createInstancePrototype(); - framep->captureVarInsert(varp); - bindNodeToDynScope(varp, framep); - } - for (AstNode* stmtp = nodep->stmtsp(); stmtp; stmtp = stmtp->nextp()) { - AstAssign* const asgnp = VN_CAST(stmtp, Assign); - UASSERT_OBJ(asgnp, stmtp, "Invalid node under block item initialization part of fork"); - bindNodeToDynScope(asgnp->lhsp(), framep); - iterate(asgnp->rhsp()); + UASSERT_OBJ(!varp->lifetime().isNone(), nodep, "Variable's lifetime is unknown"); + if (varp->lifetime().isAutomatic()) { // else V3Begin will move later + if (!framep->instance().initialized()) framep->createInstancePrototype(); + framep->captureVarInsert(varp); + bindNodeToDynScope(varp, framep); + } } + bindInitIterate(nodep->stmtsp(), framep); for (AstNode* stmtp = nodep->forksp(); stmtp; stmtp = stmtp->nextp()) { m_afterTimingControl = false; @@ -520,15 +540,11 @@ class ForkVisitor final : public VNVisitor { // STATE - for current AstFork item bool m_inFork = false; // Traversal in an async fork + bool m_inInitStmt = false; // Traversal in InitialStaticStmt/InitialAutomaticStmt std::set m_forkLocalsp; // Variables local to a given fork AstVar* m_capturedVarsp = nullptr; // Local copies of captured variables AstArg* m_capturedArgsp = nullptr; // References to captured variables (as args) - // STATE - across all visitors - AstClass* m_processClassp = nullptr; - AstFunc* m_statusMethodp = nullptr; - VMemberMap m_memberMap; // for lookup of process class methods - // METHODS AstVar* capture(AstVarRef* refp) { AstVar* varp = nullptr; @@ -582,19 +598,6 @@ class ForkVisitor final : public VNVisitor { return true; } - AstClass* getProcessClassp() { - if (!m_processClassp) - m_processClassp - = VN_AS(m_memberMap.findMember(v3Global.rootp()->stdPackagep(), "process"), Class); - return m_processClassp; - } - - AstFunc* getStatusmethodp() { - if (m_statusMethodp == nullptr) - m_statusMethodp = VN_AS(m_memberMap.findMember(getProcessClassp(), "status"), Func); - return m_statusMethodp; - } - // VISITORS void visit(AstNodeModule* nodep) override { VL_RESTORER(m_modp); @@ -621,24 +624,16 @@ class ForkVisitor final : public VNVisitor { if (nodep->joinType().joinNone()) { UINFO(9, "Visiting fork..join_none " << nodep); FileLine* fl = nodep->fileline(); - AstVarRef* forkParentrefp = nodep->parentProcessp(); - - if (forkParentrefp) { // Forks created by V3Fork will not have this - for (AstBegin *itemp = nodep->forksp(), *nextp; itemp; itemp = nextp) { - nextp = VN_AS(itemp->nextp(), Begin); - if (!itemp->stmtsp()) continue; - AstMethodCall* const statusCallp = new AstMethodCall{ - fl, forkParentrefp->cloneTree(false), "status", nullptr}; - statusCallp->taskp(getStatusmethodp()); - statusCallp->classOrPackagep(getProcessClassp()); - statusCallp->dtypep(getStatusmethodp()->dtypep()); - AstNeq* const condp - = new AstNeq{fl, statusCallp, - new AstConst{fl, AstConst::WidthedValue{}, - getStatusmethodp()->dtypep()->width(), 1}}; - AstWait* const waitStmt = new AstWait{fl, condp, nullptr}; - itemp->stmtsp()->addHereThisAsNext(waitStmt); - } + // We use a sentinel value of UINT64_MAX to mark this delay so that it goes to the + // ACTIVE region with a delay value of 0. + for (AstBegin *itemp = nodep->forksp(), *nextp; itemp; itemp = nextp) { + nextp = VN_AS(itemp->nextp(), Begin); + if (!itemp->stmtsp()) continue; + AstDelay* const delayp = new AstDelay{ + fl, + new AstConst{fl, AstConst::Unsized64{}, std::numeric_limits::max()}, + false}; + itemp->stmtsp()->addHereThisAsNext(delayp); } } @@ -670,7 +665,8 @@ class ForkVisitor final : public VNVisitor { // If this ref is to a variable that will move into the task, then nothing to do if (m_forkLocalsp.count(varp)) return; - if (nodep->access().isWriteOrRW() && (!nodep->isClassHandleValue() || nodep->user2())) { + if (nodep->access().isWriteOrRW() && (!nodep->isClassHandleValue() || nodep->user2()) + && !m_inInitStmt) { nodep->v3warn( E_LIFETIME, "Invalid reference: Process might outlive variable " @@ -691,6 +687,17 @@ class ForkVisitor final : public VNVisitor { } iterateChildren(nodep); } + void visit(AstInitialAutomaticStmt* nodep) override { + VL_RESTORER(m_inInitStmt); + m_inInitStmt = true; + iterateChildren(nodep); + } + void visit(AstInitialStaticStmt* nodep) override { + VL_RESTORER(m_inInitStmt); + m_inInitStmt = true; + iterateChildren(nodep); + } + void visit(AstThisRef* nodep) override {} void visit(AstNode* nodep) override { iterateChildren(nodep); } diff --git a/src/V3Fork.h b/src/V3Fork.h index daac073b9..a00b01a8f 100644 --- a/src/V3Fork.h +++ b/src/V3Fork.h @@ -7,10 +7,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3FuncOpt.cpp b/src/V3FuncOpt.cpp index c07e9bbd7..002299db3 100644 --- a/src/V3FuncOpt.cpp +++ b/src/V3FuncOpt.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3FuncOpt.h b/src/V3FuncOpt.h index e727f3093..20bbea48c 100644 --- a/src/V3FuncOpt.h +++ b/src/V3FuncOpt.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3FunctionTraits.h b/src/V3FunctionTraits.h index fe64c31ec..804734a19 100644 --- a/src/V3FunctionTraits.h +++ b/src/V3FunctionTraits.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp index bafa03124..182a451c7 100644 --- a/src/V3Gate.cpp +++ b/src/V3Gate.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -456,6 +456,13 @@ class GateOkVisitor final : public VNVisitorConst { clearSimple("Not a buffer (goes to a clock)"); } } + void visit(AstCReset* nodep) override { + if (!m_isSimple) return; + // CReset is pure because we can optimize assignments, but if is + // the only assignment to a variable we still need to initial + // assign to get randomization etc + clearSimple("CReset"); + } //-------------------- void visit(AstNode* nodep) override { if (!m_isSimple) return; // Fastpath diff --git a/src/V3Gate.h b/src/V3Gate.h index d336c2a74..9d5c4313d 100644 --- a/src/V3Gate.h +++ b/src/V3Gate.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Global.cpp b/src/V3Global.cpp index 46df24135..eb96a3b70 100644 --- a/src/V3Global.cpp +++ b/src/V3Global.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Global.h b/src/V3Global.h index e46d05209..245cc05db 100644 --- a/src/V3Global.h +++ b/src/V3Global.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -125,6 +125,7 @@ class V3Global final { bool m_usesProbDist = false; // Uses $dist_* bool m_usesStdPackage = false; // Design uses the std package bool m_usesTiming = false; // Design uses timing constructs + bool m_usesZeroDelay = false; // Design uses #0 delay (or non-constant delay) bool m_hasForceableSignals = false; // Need to apply V3Force pass bool m_hasSystemCSections = false; // Has AstSystemCSection that need to be emitted bool m_useParallelBuild = false; // Use parallel build for model @@ -200,6 +201,8 @@ public: void setUsesStdPackage() { m_usesStdPackage = true; } bool usesTiming() const { return m_usesTiming; } void setUsesTiming() { m_usesTiming = true; } + bool usesZeroDelay() const { return m_usesZeroDelay; } + void setUsesZeroDelay() { m_usesZeroDelay = true; } bool hasForceableSignals() const { return m_hasForceableSignals; } void setHasForceableSignals() { m_hasForceableSignals = true; } bool hasSystemCSections() const VL_MT_SAFE { return m_hasSystemCSections; } diff --git a/src/V3Graph.cpp b/src/V3Graph.cpp index ee5944e51..69a04e5a8 100644 --- a/src/V3Graph.cpp +++ b/src/V3Graph.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Graph.h b/src/V3Graph.h index 505228133..c93b4115d 100644 --- a/src/V3Graph.h +++ b/src/V3Graph.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphAcyc.cpp b/src/V3GraphAcyc.cpp index cc7700a5b..f65a87cec 100644 --- a/src/V3GraphAcyc.cpp +++ b/src/V3GraphAcyc.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphAlg.cpp b/src/V3GraphAlg.cpp index 59131c887..9640f6272 100644 --- a/src/V3GraphAlg.cpp +++ b/src/V3GraphAlg.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphAlg.h b/src/V3GraphAlg.h index 0113fa342..a2ab590b8 100644 --- a/src/V3GraphAlg.h +++ b/src/V3GraphAlg.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphPathChecker.cpp b/src/V3GraphPathChecker.cpp index 18051c790..ceec04edc 100644 --- a/src/V3GraphPathChecker.cpp +++ b/src/V3GraphPathChecker.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphPathChecker.h b/src/V3GraphPathChecker.h index bcffaaa11..a8a0ab64f 100644 --- a/src/V3GraphPathChecker.h +++ b/src/V3GraphPathChecker.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphStream.h b/src/V3GraphStream.h index 9c216cdfe..62c9b8b21 100644 --- a/src/V3GraphStream.h +++ b/src/V3GraphStream.h @@ -7,10 +7,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphTest.cpp b/src/V3GraphTest.cpp index e1373e676..28c8c0d0f 100644 --- a/src/V3GraphTest.cpp +++ b/src/V3GraphTest.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Hash.cpp b/src/V3Hash.cpp index e3647d2e9..cfd38bc4e 100644 --- a/src/V3Hash.cpp +++ b/src/V3Hash.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Hash.h b/src/V3Hash.h index 0c4834390..a28d59618 100644 --- a/src/V3Hash.h +++ b/src/V3Hash.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Hasher.cpp b/src/V3Hasher.cpp index 987b871b6..4df1dbf63 100644 --- a/src/V3Hasher.cpp +++ b/src/V3Hasher.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -347,7 +347,7 @@ class HasherVisitor final : public VNVisitorConst { void visit(AstClassExtends* nodep) override { m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } - void visit(AstSelLoopVars* nodep) override { + void visit(AstForeachHeader* nodep) override { m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstDefParam* nodep) override { @@ -560,6 +560,9 @@ class HasherVisitor final : public VNVisitorConst { void visit(AstCExprUser* nodep) override { m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } + void visit(AstWith* nodep) override { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); + } public: // CONSTRUCTORS diff --git a/src/V3Hasher.h b/src/V3Hasher.h index 9fdd3957b..7e980565d 100644 --- a/src/V3Hasher.h +++ b/src/V3Hasher.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3HierBlock.cpp b/src/V3HierBlock.cpp index 3dff65f84..d8b5b5ace 100644 --- a/src/V3HierBlock.cpp +++ b/src/V3HierBlock.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -164,7 +164,8 @@ VStringList V3HierBlock::commandArgs(bool forMkJson) const { if (!forMkJson) { opts.push_back(" --prefix " + prefix); opts.push_back(" --mod-prefix " + prefix); - opts.push_back(" --top-module " + modp()->name()); + // Similar to --top-module but need to use encoded name(), not prettyName() + opts.push_back(" --top-module-encoded " + modp()->name()); } opts.push_back(" --lib-create " + modp()->name()); // possibly mangled name if (v3Global.opt.protectKeyProvided()) diff --git a/src/V3HierBlock.h b/src/V3HierBlock.h index b67158553..72877594c 100644 --- a/src/V3HierBlock.h +++ b/src/V3HierBlock.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index f9abf537d..05714a616 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -122,6 +122,12 @@ class InlineMarkVisitor final : public VNVisitor { if (m_modp->modPublic() && (m_modp->isTop() || !v3Global.opt.flatten())) { cantInline("modPublic", false); } + // If the instance is a --lib-create library stub instance, and need tracing, + // then don't inline as we need to know its a lib stub for sepecial handling + // in V3TraceDecl. See #7001. + if (m_modp->verilatorLib() && v3Global.opt.trace()) { + cantInline("verilatorLib with --trace", false); + } iterateChildren(nodep); } @@ -158,8 +164,8 @@ class InlineMarkVisitor final : public VNVisitor { } } void visit(AstVarXRef* nodep) override { - // Remove link. V3LinkDot will reestablish it after inlining. - nodep->varp(nullptr); + // Keep varp - V3Const::constifyEdit is called during pinReconnectSimple + // which needs varp to be set. V3LinkDot will re-resolve after inlining. } void visit(AstNodeFTaskRef* nodep) override { // Remove link. V3LinkDot will reestablish it after inlining. @@ -322,7 +328,7 @@ class InlineRelinkVisitor final : public VNVisitor { } void visit(AstVarRef* nodep) override { // If the target port is being inlined, replace reference with the - // connected expression (always a Const of a VarRef). + // connected expression (a Const, VarRef, or VarXRef). AstNode* const pinExpr = nodep->varp()->user2p(); if (!pinExpr) return; @@ -342,7 +348,8 @@ class InlineRelinkVisitor final : public VNVisitor { // variable that will later be pruned (it will otherwise be unreferenced). if (!nodep->access().isReadOnly()) { AstVar* const varp = nodep->varp(); - const std::string name = "__vInlPlaceholder_" + std::to_string(++m_nPlaceholders); + const std::string name + = m_cellp->name() + "__vInlPlaceholder_" + std::to_string(++m_nPlaceholders); AstVar* const holdep = new AstVar{varp->fileline(), VVarType::VAR, name, varp}; m_modp->addStmtsp(holdep); AstVarRef* const newp = new AstVarRef{nodep->fileline(), holdep, nodep->access()}; @@ -354,10 +361,25 @@ class InlineRelinkVisitor final : public VNVisitor { return; } - // Otherwise it must be a variable reference, retarget this ref - const AstVarRef* const vrefp = VN_AS(pinExpr, VarRef); - nodep->varp(vrefp->varp()); - nodep->classOrPackagep(vrefp->classOrPackagep()); + // Handle VarRef: simple retarget + if (const AstVarRef* const vrefp = VN_CAST(pinExpr, VarRef)) { + nodep->varp(vrefp->varp()); + nodep->classOrPackagep(vrefp->classOrPackagep()); + return; + } + + // Handle VarXRef: replace VarRef with VarXRef (e.g., nested interface port) + const AstVarXRef* const xrefp = VN_AS(pinExpr, VarXRef); + AstVarXRef* const newp + = new AstVarXRef{nodep->fileline(), xrefp->name(), xrefp->dotted(), nodep->access()}; + newp->varp(xrefp->varp()); + // Copy inlinedDots from pin expression - the normal visitor iteration will + // prepend the cell name when this VarXRef is visited later + newp->inlinedDots(xrefp->inlinedDots()); + nodep->replaceWith(newp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + // Note: Don't call iterate(newp) here - the node will be visited during + // normal tree iteration which will apply the inlining transformations } void visit(AstVarXRef* nodep) override { // Track what scope it was originally under so V3LinkDot can resolve it @@ -481,13 +503,28 @@ void connectPort(AstNodeModule* modp, AstVar* nodep, AstNodeExpr* pinExprp) { } // Otherwise it must be a variable reference due to having called pinReconnectSimple - const AstVarRef* const pinRefp = VN_AS(pinExprp, VarRef); + const AstNodeVarRef* const pinRefp = VN_AS(pinExprp, NodeVarRef); - // Helper to create an AstVarRef reference to the pin variable - const auto pinRef = [&](VAccess access) { - AstVarRef* const p = new AstVarRef{pinRefp->fileline(), pinRefp->varp(), access}; - p->classOrPackagep(pinRefp->classOrPackagep()); - return p; + const auto pinRefAsVarRef = [&](VAccess access) -> AstVarRef* { + const AstVarRef* const vrp = VN_AS(pinRefp, VarRef); + AstVarRef* const newp = new AstVarRef{vrp->fileline(), vrp->varp(), access}; + newp->classOrPackagep(vrp->classOrPackagep()); + return newp; + }; + + const auto pinRefAsExpr = [&](VAccess access) -> AstNodeExpr* { + if (const AstVarRef* const vrp = VN_CAST(pinRefp, VarRef)) { + AstVarRef* const newp = new AstVarRef{vrp->fileline(), vrp->varp(), access}; + newp->classOrPackagep(vrp->classOrPackagep()); + return newp; + } else { + const AstVarXRef* const xrp = VN_AS(pinRefp, VarXRef); + AstVarXRef* const newp + = new AstVarXRef{xrp->fileline(), xrp->name(), xrp->dotted(), access}; + newp->varp(xrp->varp()); + newp->inlinedDots(xrp->inlinedDots()); + return newp; + } }; // If it is being inlined, create the alias for it @@ -495,10 +532,10 @@ void connectPort(AstNodeModule* modp, AstVar* nodep, AstNodeExpr* pinExprp) { UINFO(6, "Inlining port variable: " << nodep); if (nodep->isIfaceRef()) { modp->addStmtsp( - new AstAliasScope{flp, portRef(VAccess::WRITE), pinRef(VAccess::READ)}); + new AstAliasScope{flp, portRef(VAccess::WRITE), pinRefAsExpr(VAccess::READ)}); } else { AstVarRef* const aliasArgsp = portRef(VAccess::WRITE); - aliasArgsp->addNext(pinRef(VAccess::READ)); + aliasArgsp->addNext(pinRefAsVarRef(VAccess::READ)); modp->addStmtsp(new AstAlias{flp, aliasArgsp}); } // They will become the same variable, so propagate file-line and variable attributes @@ -512,10 +549,12 @@ void connectPort(AstNodeModule* modp, AstVar* nodep, AstNodeExpr* pinExprp) { // Otherwise create the continuous assignment between the port var and the pin expression UINFO(6, "Not inlining port variable: " << nodep); if (nodep->direction() == VDirection::INPUT) { - AstAssignW* const ap = new AstAssignW{flp, portRef(VAccess::WRITE), pinRef(VAccess::READ)}; + AstAssignW* const ap + = new AstAssignW{flp, portRef(VAccess::WRITE), pinRefAsExpr(VAccess::READ)}; modp->addStmtsp(new AstAlways{ap}); } else if (nodep->direction() == VDirection::OUTPUT) { - AstAssignW* const ap = new AstAssignW{flp, pinRef(VAccess::WRITE), portRef(VAccess::READ)}; + AstAssignW* const ap + = new AstAssignW{flp, pinRefAsExpr(VAccess::WRITE), portRef(VAccess::READ)}; modp->addStmtsp(new AstAlways{ap}); } else { pinExprp->v3fatalSrc("V3Tristate left INOUT port"); diff --git a/src/V3Inline.h b/src/V3Inline.h index 3b6917d85..7c26496f5 100644 --- a/src/V3Inline.h +++ b/src/V3Inline.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3InlineCFuncs.cpp b/src/V3InlineCFuncs.cpp index 930e09740..922cc17f1 100644 --- a/src/V3InlineCFuncs.cpp +++ b/src/V3InlineCFuncs.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -112,7 +112,7 @@ class InlineCFuncsVisitor final : public VNVisitor { } // Check if a function is eligible for inlining into caller - bool isInlineable(AstCFunc* callerp, AstCFunc* cfuncp) { + bool isInlineable(const AstCFunc* callerp, AstCFunc* cfuncp) { // Must be in the same scope (same class) to access the same members if (callerp->scopep() != cfuncp->scopep()) return false; @@ -246,7 +246,7 @@ class InlineCFuncsVisitor final : public VNVisitor { public: // CONSTRUCTORS - explicit InlineCFuncsVisitor(AstNetlist* nodep) + explicit InlineCFuncsVisitor(const AstNetlist* nodep) : m_threshold1{v3Global.opt.inlineCFuncs()} , m_threshold2{v3Global.opt.inlineCFuncsProduct()} { // Don't inline when profiling or tracing diff --git a/src/V3InlineCFuncs.h b/src/V3InlineCFuncs.h index a75a6d69a..c365e61db 100644 --- a/src/V3InlineCFuncs.h +++ b/src/V3InlineCFuncs.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index 640d9b2a6..5122eafbf 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -566,7 +566,6 @@ private: void visit(AstNode* nodep) override { iterateChildren(nodep); } void visit(AstNew* nodep) override { iterateChildren(nodep); } void visit(AstMethodCall* nodep) override { iterateChildren(nodep); } - void visit(AstArg* nodep) override { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -662,6 +661,7 @@ public: if (pinVarp->isInout()) { pinVarp->v3fatalSrc("Unsupported: Inout connections to pins must be" " direct one-to-one connection (without any expression)"); + // V3Tristate should have cleared up before this point } else if (pinVarp->isWritable()) { // See also V3Inst AstNodeExpr* rhsp = new AstVarRef{pinp->fileline(), newvarp, VAccess::READ}; diff --git a/src/V3Inst.h b/src/V3Inst.h index d527fd81c..91bba478d 100644 --- a/src/V3Inst.h +++ b/src/V3Inst.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3InstrCount.cpp b/src/V3InstrCount.cpp index ec7333531..6b4b2676e 100644 --- a/src/V3InstrCount.cpp +++ b/src/V3InstrCount.cpp @@ -7,10 +7,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3InstrCount.h b/src/V3InstrCount.h index 3c1bcf327..c55ad432b 100644 --- a/src/V3InstrCount.h +++ b/src/V3InstrCount.h @@ -7,10 +7,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Interface.cpp b/src/V3Interface.cpp index 0bece6547..51cc2d11e 100644 --- a/src/V3Interface.cpp +++ b/src/V3Interface.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Interface.h b/src/V3Interface.h index a66d11daa..bfe702dd0 100644 --- a/src/V3Interface.h +++ b/src/V3Interface.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LangCode.h b/src/V3LangCode.h index 3b5bdf5fe..ad12809e5 100644 --- a/src/V3LangCode.h +++ b/src/V3LangCode.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LanguageWords.h b/src/V3LanguageWords.h index a849e91fd..f1a8fb527 100644 --- a/src/V3LanguageWords.h +++ b/src/V3LanguageWords.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LibMap.cpp b/src/V3LibMap.cpp index 5a91cf7eb..b7e3803fd 100644 --- a/src/V3LibMap.cpp +++ b/src/V3LibMap.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -59,7 +59,7 @@ class LibMapVisitor final : public VNVisitor { public: // CONSTRUCTORS - LibMapVisitor(AstNetlist* nodep) { iterate(nodep); } + explicit LibMapVisitor(AstNetlist* nodep) { iterate(nodep); } }; //###################################################################### diff --git a/src/V3LibMap.h b/src/V3LibMap.h index 9b23e8a4b..4de0f69e3 100644 --- a/src/V3LibMap.h +++ b/src/V3LibMap.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Life.cpp b/src/V3Life.cpp index 445a5a57a..46fc197e9 100644 --- a/src/V3Life.cpp +++ b/src/V3Life.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -46,13 +46,11 @@ class LifeState final { public: VDouble0 m_statAssnDel; // Statistic tracking VDouble0 m_statAssnCon; // Statistic tracking - VDouble0 m_statCResetDel; // Statistic tracking // CONSTRUCTORS LifeState() = default; ~LifeState() { V3Stats::addStatSum("Optimizations, Lifetime assign deletions", m_statAssnDel); - V3Stats::addStatSum("Optimizations, Lifetime creset deletions", m_statCResetDel); V3Stats::addStatSum("Optimizations, Lifetime constant prop", m_statAssnCon); } }; @@ -87,12 +85,6 @@ public: m_everSet = true; if (VN_IS(nodep->rhsp(), Const)) m_constp = VN_AS(nodep->rhsp(), Const); } - void resetStatement(AstCReset* nodep) { // New CReset(A) assignment - UASSERT_OBJ(!m_isNew, nodep, "Uninitialized new entry"); - m_assignp = nodep; - m_constp = nullptr; - m_everSet = true; - } void complexAssign() { // A[x]=... or some complicated assignment UASSERT(!m_isNew, "Uninitialized new entry"); m_assignp = nullptr; @@ -148,26 +140,9 @@ public: UINFOTREE(7, oldassp, "", "REMOVE/SAMEBLK"); entr.complexAssign(); oldassp->unlinkFrBack(); - if (VN_IS(oldassp, CReset)) { - ++m_statep->m_statCResetDel; - } else { - ++m_statep->m_statAssnDel; - } + ++m_statep->m_statAssnDel; VL_DO_DANGLING(m_deleter.pushDeletep(oldassp), oldassp); } - void resetStatement(AstVarScope* nodep, AstCReset* rstp) { - // Do we have a old assignment we can nuke? - UINFO(4, " CRESETof: " << nodep); - UINFO(7, " new: " << rstp); - LifeVarEntry& entr = m_map[nodep]; - if (entr.isNew()) { - entr.init(true); - } else { - checkRemoveAssign(nodep, entr); - } - entr.resetStatement(rstp); - // lifeDump(); - } void simpleAssign(AstVarScope* nodep, AstNodeAssign* assp) { // Do we have a old assignment we can nuke? UINFO(4, " ASSIGNof: " << nodep); @@ -196,7 +171,8 @@ public: entr.init(false); } else { if (AstConst* const constp = entr.constNodep()) { - if (!varrefp->varp()->isSigPublic() && !varrefp->varp()->sensIfacep()) { + if (!varrefp->varp()->isSigPublic() && !varrefp->varp()->isWrittenByDpi() + && !varrefp->varp()->isVirtIface()) { // Aha, variable is constant; substitute in. // We'll later constant propagate UINFO(4, " replaceconst: " << varrefp); @@ -333,15 +309,6 @@ class LifeVisitor final : public VNVisitor { iterateAndNextNull(nodep->lhsp()); } } - void visit(AstCReset* nodep) override { - if (!m_noopt) { - AstVarScope* const vscp = nodep->varrefp()->varScopep(); - UASSERT_OBJ(vscp, nodep, "Scope lost on variable"); - m_lifep->resetStatement(vscp, nodep); - } else { - iterateAndNextNull(nodep->varrefp()); - } - } void visit(AstAssignDly* nodep) override { // V3Life doesn't understand time sense if (nodep->isTimingControl()) { @@ -431,6 +398,7 @@ class LifeVisitor final : public VNVisitor { if (!m_tracingCall && !nodep->entryPoint()) return; m_tracingCall = false; if (nodep->recursive()) setNoopt(); + if (nodep->noLife()) setNoopt(); if (nodep->dpiImportPrototype() && !nodep->dpiPure()) { m_sideEffect = true; // If appears on assign RHS, don't ever delete the assignment } diff --git a/src/V3Life.h b/src/V3Life.h index a0a723196..7c1035ac5 100644 --- a/src/V3Life.h +++ b/src/V3Life.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LifePost.cpp b/src/V3LifePost.cpp index 8f67eaea9..e75ae3a7e 100644 --- a/src/V3LifePost.cpp +++ b/src/V3LifePost.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LifePost.h b/src/V3LifePost.h index 2c8b186cd..386d425fc 100644 --- a/src/V3LifePost.h +++ b/src/V3LifePost.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp index ec493696a..ccdbdc61a 100644 --- a/src/V3LinkCells.cpp +++ b/src/V3LinkCells.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -416,21 +416,32 @@ class LinkCellsVisitor final : public VNVisitor { m_graph.rank(); for (V3GraphVertex& vtx : m_graph.vertices()) { if (const LinkCellsVertex* const vvertexp = vtx.cast()) { - AstNodeModule* const modp = vvertexp->modp(); - modp->level(vvertexp->rank()); + AstNodeModule* const vmodp = vvertexp->modp(); + vmodp->level(vvertexp->rank()); } } m_graph.rankMin(); for (V3GraphVertex& vtx : m_graph.vertices()) { if (const LinkCellsVertex* const vvertexp = vtx.cast()) { // +1 so we leave level 1 for the new wrapper we'll make in a moment - AstNodeModule* const modp = vvertexp->modp(); - modp->depth(vvertexp->rank() + 1); + AstNodeModule* const vmodp = vvertexp->modp(); + vmodp->depth(vvertexp->rank() + 1); } } if (v3Global.opt.topModule() != "" && !m_topVertexp) { - v3error("Specified --top-module '" << v3Global.opt.topModule() - << "' was not found in design."); + VSpellCheck spell; + for (V3GraphVertex& vtx : m_graph.vertices()) { + if (const LinkCellsVertex* const vvertexp = vtx.cast()) { + AstNodeModule* const vmodp = vvertexp->modp(); + if (VN_IS(vmodp, Module)) spell.pushCandidate(vmodp->prettyName()); + } + } + const string suggest + = spell.bestCandidateMsg(AstNode::prettyName(v3Global.opt.topModule())); + v3error("Specified --top-module '" + << AstNode::prettyName(v3Global.opt.topModule()) + << "' was not found in design.\n" + << (suggest.empty() ? "" : V3Error::warnMore() + suggest)); } } void visit(AstConstPool* nodep) override {} @@ -473,8 +484,9 @@ class LinkCellsVisitor final : public VNVisitor { UINFO(2, "Link --top-module: " << nodep); nodep->inLibrary(false); // Safer to make sure it doesn't disappear } - if (v3Global.opt.topModule() == "" ? nodep->inLibrary() // Library cells are lower - : !topMatch) { // Any non-specified module is lower + if (v3Global.opt.topModule().empty() + ? nodep->inLibrary() // Library cells are lower + : !topMatch) { // Any non-specified module is lower // Put under a fake vertex so that the graph ranking won't indicate // this is a top level module if (!m_libVertexp) m_libVertexp = new LibraryVertex{&m_graph}; diff --git a/src/V3LinkCells.h b/src/V3LinkCells.h index 9d0a0e80c..e6cdfb877 100644 --- a/src/V3LinkCells.h +++ b/src/V3LinkCells.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 61f8ef4ac..8c3a05213 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -653,29 +653,6 @@ private: return findp; } - VSymEnt* findForkParentAlias(VSymEnt* symp, const string& ident) { - static const string suffix = "__VgetForkParent"; - VSymEnt* const wrapperp = symp->findIdFlat(ident + suffix); - if (!wrapperp) return nullptr; - if (!VN_IS(wrapperp->nodep(), Begin)) return nullptr; - if (VSymEnt* const forkSymp = wrapperp->findIdFlat(ident)) { - if (VN_IS(forkSymp->nodep(), Fork)) return forkSymp; - } - return nullptr; - } - - VSymEnt* unwrapForkParent(VSymEnt* symp, const string& ident) { - static const string suffix = "__VgetForkParent"; - if (AstBegin* const beginp = VN_CAST(symp->nodep(), Begin)) { - if (VString::endsWith(beginp->name(), suffix)) { - if (VSymEnt* const forkSymp = symp->findIdFlat(ident)) { - if (VN_IS(forkSymp->nodep(), Fork)) return forkSymp; - } - } - } - return symp; - } - VSymEnt* findWithAltFlat(VSymEnt* symp, const string& name, const string& altname) { VSymEnt* findp = symp->findIdFlat(name); if (findp) return findp; @@ -726,9 +703,9 @@ public: const AstCellInline* inlinep = lookupSymp ? VN_CAST(lookupSymp->nodep(), CellInline) : nullptr; // Replicated below - VSymEnt* findSymp = findWithAltFallback(lookupSymp, ident, altIdent); - if (!findSymp) findSymp = findForkParentAlias(lookupSymp, ident); - if (findSymp) lookupSymp = unwrapForkParent(findSymp, ident); + if (VSymEnt* const findSymp = findWithAltFallback(lookupSymp, ident, altIdent)) { + lookupSymp = findSymp; + } // Check this module - cur modname else if ((cellp && cellp->modp()->origName() == ident) @@ -758,9 +735,9 @@ public: if ((cellp && cellp->modp()->origName() == ident) || (inlinep && inlinep->origModName() == ident)) { break; - } else if (VSymEnt* const findSymp + } else if (VSymEnt* const findSym2p = findWithAltFallback(lookupSymp, ident, altIdent)) { - lookupSymp = findSymp; + lookupSymp = findSym2p; if (crossedCell && VN_IS(lookupSymp->nodep(), Var)) { UINFO(9, " Not found but matches var name in parent " << lookupSymp); @@ -774,13 +751,50 @@ public: } if (!lookupSymp) return nullptr; // Not found } - } else { // Searching for middle submodule, must be a cell name + } else { // Searching for middle path component, must be a cell or interface port VSymEnt* findSymp = findWithAltFlat(lookupSymp, ident, altIdent); - if (!findSymp) findSymp = findForkParentAlias(lookupSymp, ident); - if (findSymp) - lookupSymp = unwrapForkParent(findSymp, ident); - else { - return nullptr; // Not found + if (findSymp) { + lookupSymp = findSymp; + } else { + // Try prefixed lookup for interface ports accessed through hierarchy + // (e.g., slave_inst.bus.data where bus is an interface port) + // After inlining, interface ports have prefixed names like + // top__DOT__slave_inst__DOT__bus + UINFO(8, " middle-path: trying prefixed lookup for '" << ident << "'\n"); + string baddot; + findSymp = findSymPrefixed(lookupSymp, ident, baddot, /*fallback=*/true); + UINFO(8, " middle-path: prefixed lookup result: " + << (findSymp ? "found" : "not found") << "\n"); + if (findSymp) { + // Check if this is an interface reference variable + const AstVar* varp = VN_CAST(findSymp->nodep(), Var); + if (!varp) { + if (const AstVarScope* vscp = VN_CAST(findSymp->nodep(), VarScope)) { + varp = vscp->varp(); + } + } + if (varp && varp->isIfaceRef()) { + // Found an interface port - use findSymp directly + // computeScopeAliases has already imported interface members + // into this symbol entry, so we use it instead of redirecting + // to the shared modport definition (which would cause all + // instances to resolve to the same symbols - bug #2656) + lookupSymp = findSymp; + } else { + // Non-interface symbol in middle path must be a cell (module instance) + // to continue hierarchical resolution + if (VN_IS(findSymp->nodep(), Cell)) { + lookupSymp = findSymp; + } else { + // Reject non-cell, non-interface symbols found via fallback + // to prevent accidental resolution to unrelated symbols + UINFO(8, " middle-path: rejecting non-cell symbol\n"); + return nullptr; + } + } + } else { + return nullptr; // Not found + } } } if (lookupSymp) { @@ -795,6 +809,53 @@ public: } } } + // Follow scope alias for nested interface port access + if (!leftname.empty()) { + const auto aliasIt = m_scopeAliasMap[SAMN_IFTOP].find(lookupSymp); + if (aliasIt != m_scopeAliasMap[SAMN_IFTOP].end()) { + lookupSymp = aliasIt->second; + // Alias may point to __Viftop VarScope; find corresponding Cell + if (const AstVarScope* const vscp + = VN_CAST(lookupSymp->nodep(), VarScope)) { + const string varName = vscp->varp()->name(); + static constexpr const char* const VIFTOP_SUFFIX = "__Viftop"; + if (VString::endsWith(varName, VIFTOP_SUFFIX)) { + const string cellName + = varName.substr(0, varName.size() - strlen(VIFTOP_SUFFIX)); + VSymEnt* const parentSymp = lookupSymp->parentp(); + if (parentSymp) { + VSymEnt* const cellSymp = parentSymp->findIdFlat(cellName); + if (cellSymp && VN_IS(cellSymp->nodep(), Cell)) { + lookupSymp = cellSymp; // Use Cell for member lookup + } + } + } + } + } else { + // No alias; try following IfaceRefDType to interface cell + const AstVar* varp = VN_CAST(lookupSymp->nodep(), Var); + if (!varp) { + if (const AstVarScope* const vscp + = VN_CAST(lookupSymp->nodep(), VarScope)) { + varp = vscp->varp(); + } + } + if (varp && varp->isIfaceRef()) { + if (const AstIfaceRefDType* const ifaceRefp + = ifaceRefFromArray(varp->dtypep())) { + if (ifaceRefp->cellp() && existsNodeSym(ifaceRefp->cellp())) { + lookupSymp = getNodeSym(ifaceRefp->cellp()); + } else if (ifaceRefp->ifaceViaCellp() + && existsNodeSym(ifaceRefp->ifaceViaCellp())) { + lookupSymp = getNodeSym(ifaceRefp->ifaceViaCellp()); + } else if (ifaceRefp->ifacep() + && existsNodeSym(ifaceRefp->ifacep())) { + lookupSymp = getNodeSym(ifaceRefp->ifacep()); + } + } + } + } + } } firstId = false; } @@ -1076,8 +1137,8 @@ class LinkDotFindVisitor final : public VNVisitor { void visit(AstTypeTable*) override {} // FindVisitor:: void visit(AstConstPool*) override {} // FindVisitor:: void visit(AstIfaceRefDType* nodep) override { // FindVisitor:: - if (m_statep->forPrimary() && nodep->isVirtual() && nodep->ifacep() - && !nodep->ifacep()->user3()) { + if ((m_statep->forPrimary() || m_statep->forParamed()) && nodep->isVirtual() + && nodep->ifacep() && !nodep->ifacep()->user3()) { m_virtIfaces.push_back(nodep->ifacep()); nodep->ifacep()->user3(true); } @@ -1849,31 +1910,15 @@ class LinkDotFindVisitor final : public VNVisitor { m_curSymp = m_statep->insertBlock(m_curSymp, "__Vforeach" + cvtToStr(m_modWithNum), nodep, m_classOrPackagep); m_curSymp->fallbackp(VL_RESTORER_PREV(m_curSymp)); - // DOT(x, SELLOOPVARS(var, loops)) -> SELLOOPVARS(DOT(x, var), loops) - if (AstDot* const dotp = VN_CAST(nodep->arrayp(), Dot)) { - if (AstSelLoopVars* const loopvarsp = VN_CAST(dotp->rhsp(), SelLoopVars)) { - AstNodeExpr* const fromp = loopvarsp->fromp()->unlinkFrBack(); - loopvarsp->unlinkFrBack(); - dotp->replaceWith(loopvarsp); - dotp->rhsp(fromp); - loopvarsp->fromp(dotp); - } - } - const auto loopvarsp = VN_CAST(nodep->arrayp(), SelLoopVars); - if (!loopvarsp) { - AstNode* const warnp = nodep->arrayp() ? nodep->arrayp() : nodep; - warnp->v3warn(E_UNSUPPORTED, - "Unsupported (or syntax error): Foreach on this array's construct"); - VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - return; - } - for (AstNode *nextp, *argp = loopvarsp->elementsp(); argp; argp = nextp) { + for (AstNode *nextp, *argp = nodep->headerp()->elementsp(); argp; argp = nextp) { nextp = argp->nextp(); AstVar* argrefp = nullptr; if (AstParseRef* const parserefp = VN_CAST(argp, ParseRef)) { - // We use an int type, this might get changed in V3Width when types resolve + // IEEE 1800-2023 12.7.3: foreach loop variable type shall be int (2-state) + // This might get changed in V3Width when types resolve (e.g., for assoc + // arrays) argrefp = new AstVar{parserefp->fileline(), VVarType::BLOCKTEMP, - parserefp->name(), argp->findSigned32DType()}; + parserefp->name(), argp->findIntDType()}; argrefp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); parserefp->replaceWith(argrefp); VL_DO_DANGLING2(parserefp->deleteTree(), parserefp, argp); @@ -1917,18 +1962,21 @@ class LinkDotFindVisitor final : public VNVisitor { UASSERT_OBJ(funcrefp, nodep, "'with' only can operate on a function/task"); string name = "item"; FileLine* argFl = nodep->fileline(); - AstArg* argp = VN_CAST(funcrefp->pinsp(), Arg); - if (argp) argp->unlinkFrBackWithNext(); - if (argp && funcrefp->name() != "randomize") { - if (const auto parserefp = VN_CAST(argp->exprp(), ParseRef)) { - name = parserefp->name(); - argFl = parserefp->fileline(); - } else { - argp->v3error("'with' function expects simple variable name"); + AstArg* const argsp = funcrefp->argsp(); + if (argsp) { + argsp->unlinkFrBackWithNext(); + if (funcrefp->name() != "randomize") { + if (const auto parserefp = VN_CAST(argsp->exprp(), ParseRef)) { + name = parserefp->name(); + argFl = parserefp->fileline(); + } else { + argsp->v3error("'with' function expects simple variable name"); + } + if (argsp->nextp()) { + argsp->nextp()->v3error("'with' function expects only up to one argument"); + } + VL_DO_DANGLING(argsp->deleteTree(), argsp); } - if (argp->nextp()) - argp->nextp()->v3error("'with' function expects only up to one argument"); - VL_DO_DANGLING(argp->deleteTree(), argp); } // Type depends on the method used, let V3Width figure it out later if (nodep->exprsp() @@ -1949,9 +1997,9 @@ class LinkDotFindVisitor final : public VNVisitor { AstLambdaArgRef* const valueArgRefp = new AstLambdaArgRef{argFl, name, false}; AstWith* const newp = new AstWith{nodep->fileline(), indexArgRefp, valueArgRefp, exprOrConstraintsp}; - funcrefp->addPinsp(newp); + funcrefp->withp(newp); } - funcrefp->addPinsp(argp); + funcrefp->addArgsp(argsp); nodep->replaceWith(nodep->funcrefp()->unlinkFrBack()); VL_DO_DANGLING(nodep->deleteTree(), nodep); } @@ -2296,6 +2344,8 @@ class LinkDotScopeVisitor final : public VNVisitor { LinkDotState* const m_statep; // State to pass between visitors, including symbol table const AstScope* m_scopep = nullptr; // The current scope VSymEnt* m_modSymp = nullptr; // Symbol entry for current module + // Deferred AliasScope processing - must be done outer-to-inner for correct alias resolution + std::vector> m_deferredAliasScopes; // METHODS public: @@ -2339,37 +2389,39 @@ private: if (!nodep->varp()->isFuncLocal() && !nodep->varp()->isClassMember()) { VSymEnt* const varSymp = m_statep->insertSym(m_modSymp, nodep->varp()->name(), nodep, nullptr); - if (nodep->varp()->isIfaceRef() && nodep->varp()->isIfaceParent()) { - UINFO(9, "Iface parent ref var " << nodep->varp()->name() << " " << nodep); - // Find the interface cell the var references + if (nodep->varp()->isIfaceRef()) { AstIfaceRefDType* const dtypep = LinkDotState::ifaceRefFromArray(nodep->varp()->dtypep()); UASSERT_OBJ(dtypep, nodep, "Non AstIfaceRefDType on isIfaceRef() var"); - UINFO(9, "Iface parent dtype " << dtypep); - const string ifcellname = dtypep->cellName(); - string baddot; - VSymEnt* okSymp; - VSymEnt* cellSymp = m_statep->findDotted(nodep->fileline(), m_modSymp, ifcellname, - baddot, okSymp, false); - UASSERT_OBJ( - cellSymp, nodep, - "No symbol for interface instance: " << nodep->prettyNameQ(ifcellname)); - UINFO(5, " Found interface instance: se" << cvtToHex(cellSymp) << " " - << cellSymp->nodep()); - if (dtypep->modportName() != "") { - VSymEnt* const mpSymp = m_statep->findDotted( - nodep->fileline(), m_modSymp, ifcellname, baddot, okSymp, false); - UASSERT_OBJ(mpSymp, nodep, - "No symbol for interface modport: " - << nodep->prettyNameQ(dtypep->modportName())); - cellSymp = mpSymp; - UINFO(5, " Found modport cell: se" << cvtToHex(cellSymp) << " " - << mpSymp->nodep()); + if (nodep->varp()->isIfaceParent()) { + UINFO(9, "Iface parent ref var " << nodep->varp()->name() << " " << nodep); + // Find the interface cell the var references + UINFO(9, "Iface parent dtype " << dtypep); + const string ifcellname = dtypep->cellName(); + string baddot; + VSymEnt* okSymp; + VSymEnt* cellSymp = m_statep->findDotted(nodep->fileline(), m_modSymp, + ifcellname, baddot, okSymp, false); + UASSERT_OBJ( + cellSymp, nodep, + "No symbol for interface instance: " << nodep->prettyNameQ(ifcellname)); + UINFO(5, " Found interface instance: se" << cvtToHex(cellSymp) << " " + << cellSymp->nodep()); + if (dtypep->modportName() != "") { + // Look up the modport within the interface cell's symbol table + VSymEnt* const mpSymp = cellSymp->findIdFallback(dtypep->modportName()); + UASSERT_OBJ(mpSymp, nodep, + "No symbol for interface modport: " + << nodep->prettyNameQ(dtypep->modportName())); + cellSymp = mpSymp; + UINFO(5, " Found modport cell: se" << cvtToHex(cellSymp) << " " + << mpSymp->nodep()); + } + // Interface reference; need to put whole thing into + // symtable, but can't clone it now as we may have a later + // alias for it. + m_statep->insertScopeAlias(LinkDotState::SAMN_IFTOP, varSymp, cellSymp); } - // Interface reference; need to put whole thing into - // symtable, but can't clone it now as we may have a later - // alias for it. - m_statep->insertScopeAlias(LinkDotState::SAMN_IFTOP, varSymp, cellSymp); } } } @@ -2408,6 +2460,12 @@ private: pushDeletep(nodep->unlinkFrBack()); } void visit(AstAliasScope* nodep) override { // ScopeVisitor:: + // Defer AliasScope processing - must process outer scopes before inner ones + // so that nested interface port alias resolution works correctly + UINFO(5, "ALIASSCOPE (deferred) " << nodep); + m_deferredAliasScopes.emplace_back(nodep, m_modSymp); + } + void processAliasScope(AstAliasScope* nodep, VSymEnt* modSymp) { UINFO(5, "ALIASSCOPE " << nodep); UINFOTREE(9, nodep, "", "avs"); VSymEnt* rhsSymp; @@ -2419,22 +2477,21 @@ private: string inl = ((xrefp && xrefp->inlinedDots().size()) ? (xrefp->inlinedDots() + "__DOT__") : ""); + const string dottedPath + = (xrefp && !xrefp->dotted().empty()) ? (xrefp->dotted() + ".") : ""; VSymEnt* symp = nullptr; string scopename; while (!symp) { - scopename - = refp ? refp->name() : (inl.size() ? (inl + xrefp->name()) : xrefp->name()); + scopename = refp ? refp->name() + : (inl.size() ? (inl + dottedPath + xrefp->name()) + : (dottedPath + xrefp->name())); string baddot; VSymEnt* okSymp; - symp = m_statep->findDotted(nodep->rhsp()->fileline(), m_modSymp, scopename, - baddot, okSymp, false); + symp = m_statep->findDotted(nodep->rhsp()->fileline(), modSymp, scopename, baddot, + okSymp, true); if (inl == "") break; inl = LinkDotState::removeLastInlineScope(inl); } - if (!symp) { - UINFO(9, "No symbol for interface alias rhs (" - << std::string{refp ? "VARREF " : "VARXREF "} << scopename << ")"); - } UASSERT_OBJ(symp, nodep, "No symbol for interface alias rhs"); UINFO(5, " Found a linked scope RHS: " << scopename << " se" << cvtToHex(symp) << " " << symp->nodep()); @@ -2451,7 +2508,7 @@ private: = refp ? refp->varp()->name() : xrefp->dotted() + "." + xrefp->name(); string baddot; VSymEnt* okSymp; - VSymEnt* const symp = m_statep->findDotted(nodep->lhsp()->fileline(), m_modSymp, + VSymEnt* const symp = m_statep->findDotted(nodep->lhsp()->fileline(), modSymp, scopename, baddot, okSymp, false); UASSERT_OBJ(symp, nodep, "No symbol for interface alias lhs"); UINFO(5, " Found a linked scope LHS: " << scopename << " se" << cvtToHex(symp) @@ -2464,6 +2521,27 @@ private: // We have stored the link, we don't need these any more VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } + void processDeferredAliasScopes() { + // Sort by hierarchy depth (shallower first) so outer aliases are resolved before inner + // Pre-compute depth map to avoid O(N log N * D) complexity in sort comparisons + std::unordered_map depthMap; + for (const auto& pair : m_deferredAliasScopes) { + VSymEnt* const symp = pair.second; + if (depthMap.find(symp) == depthMap.end()) { + int depth = 0; + for (VSymEnt* p = symp; p; p = p->parentp()) ++depth; + depthMap[symp] = depth; + } + } + std::stable_sort(m_deferredAliasScopes.begin(), m_deferredAliasScopes.end(), + [&depthMap](const std::pair& a, + const std::pair& b) { + return depthMap.at(a.second) < depthMap.at(b.second); + }); + // Process in sorted order + for (auto& pair : m_deferredAliasScopes) { processAliasScope(pair.first, pair.second); } + m_deferredAliasScopes.clear(); + } void visit(AstNodeGen* nodep) override { // ScopeVisitor:: // LCOV_EXCL_LINE nodep->v3fatalSrc("Generate constructs should have been reduced out"); } @@ -2479,6 +2557,8 @@ public: : m_statep{statep} { UINFO(4, __FUNCTION__ << ": "); iterate(rootp); + // Process deferred AliasScopes in outer-to-inner order + processDeferredAliasScopes(); } ~LinkDotScopeVisitor() override = default; }; @@ -2526,13 +2606,168 @@ class LinkDotIfaceVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(nodep), nodep); } } + + // Helper to extract a dotted path string from an AstDot tree + // Returns empty string and sets hasPartSelect=true if part-select detected + string extractDottedPath(AstNode* nodep, bool& hasPartSelect) { + if (AstParseRef* const refp = VN_CAST(nodep, ParseRef)) { + return refp->name(); + } else if (AstVarRef* const refp = VN_CAST(nodep, VarRef)) { + return refp->name(); + } else if (AstDot* const dotp = VN_CAST(nodep, Dot)) { + const string lhs = extractDottedPath(dotp->lhsp(), hasPartSelect); + const string rhs = extractDottedPath(dotp->rhsp(), hasPartSelect); + if (lhs.empty()) return rhs; + if (rhs.empty()) return lhs; + return lhs + "." + rhs; + } else if (VN_IS(nodep, SelBit) || VN_IS(nodep, SelExtract)) { + hasPartSelect = true; + return ""; + } + return ""; + } + + // Helper to resolve remaining path through a nested interface + // When findDotted() partially matches (okSymp set, baddot non-empty), + // this follows the interface type to resolve the remaining path. + // Returns the resolved symbol, or nullptr if not found. + // On success, clears baddot; on partial match of multi-level path, updates baddot. + VSymEnt* resolveNestedInterfacePath(FileLine* fl, VSymEnt* okSymp, string& baddot) { + if (!okSymp || baddot.empty()) return nullptr; + + static constexpr int MAX_NESTING_DEPTH = 64; + VSymEnt* curOkSymp = okSymp; + + for (int depth = 0; depth < MAX_NESTING_DEPTH; ++depth) { + // Try to get interface from the partially-matched symbol + AstIface* ifacep = nullptr; + if (const AstCell* const cellp = VN_CAST(curOkSymp->nodep(), Cell)) { + ifacep = VN_CAST(cellp->modp(), Iface); + } else if (const AstVar* const varp = VN_CAST(curOkSymp->nodep(), Var)) { + if (varp->isIfaceRef()) { + if (const AstIfaceRefDType* const ifaceRefp + = LinkDotState::ifaceRefFromArray(varp->dtypep())) { + ifacep = ifaceRefp->ifaceViaCellp(); + } + } + } + + if (!ifacep || !m_statep->existsNodeSym(ifacep)) return nullptr; + + VSymEnt* const ifaceSymp = m_statep->getNodeSym(ifacep); + + if (baddot.find('.') == string::npos) { + // Simple identifier - direct lookup + VSymEnt* const symp = ifaceSymp->findIdFallback(baddot); + if (symp) baddot.clear(); + return symp; + } + + // Multi-level path - use findDotted for partial resolution + string remainingBaddot; + VSymEnt* remainingOkSymp = nullptr; + VSymEnt* const symp = m_statep->findDotted(fl, ifaceSymp, baddot, remainingBaddot, + remainingOkSymp, true); + if (symp) { + baddot = remainingBaddot; + return symp; + } + + // findDotted partially matched - check progress + if (remainingBaddot == baddot || !remainingOkSymp) return nullptr; + + // Continue resolving with updated state + baddot = remainingBaddot; + curOkSymp = remainingOkSymp; + } + + UINFO(1, "Nested interface resolution depth limit exceeded at " << fl << endl); + return nullptr; + } + + // Resolve a modport expression to find the referenced symbol + VSymEnt* resolveModportExpression(FileLine* fl, AstNodeExpr* exprp) { + UINFO(5, " resolveModportExpression: " << exprp << endl); + VSymEnt* symp = nullptr; + if (AstParseRef* const refp = VN_CAST(exprp, ParseRef)) { + // Simple variable reference: modport mp(input .a(sig_a)) + symp = m_curSymp->findIdFallback(refp->name()); + } else if (AstVarRef* const refp = VN_CAST(exprp, VarRef)) { + // Already resolved VarRef (can happen if iterateChildren resolved it) + if (refp->varScopep()) { + // During scope creation, VarRef may have VarScope already linked + symp = m_statep->getNodeSym(refp->varScopep()); + } else if (refp->varp()) { + symp = m_curSymp->findIdFallback(refp->varp()->name()); + } + } else if (AstVarXRef* const refp = VN_CAST(exprp, VarXRef)) { + // Resolved VarXRef (dotted reference resolved by earlier pass) + if (refp->varp()) { + // For nested interfaces, the var is in a different scope + // First try to find the symbol via the var itself + if (m_statep->existsNodeSym(refp->varp())) { + symp = m_statep->getNodeSym(refp->varp()); + } else { + // Fallback: look up in current scope + symp = m_curSymp->findIdFallback(refp->varp()->name()); + } + } else if (!refp->dotted().empty()) { + // varp not set yet - use dotted path to find the symbol + // The dotted part (e.g., "base") is the interface cell, and name is the member + const string fullPath = refp->dotted() + "." + refp->name(); + string baddot; + VSymEnt* okSymp = nullptr; + symp = m_statep->findDotted(fl, m_curSymp, fullPath, baddot, okSymp, true); + // Handle nested interface path when findDotted had partial match + if (okSymp && !baddot.empty()) { + VSymEnt* const resolved = resolveNestedInterfacePath(fl, okSymp, baddot); + if (resolved) symp = resolved; + } + } + } else if (AstDot* const dotp = VN_CAST(exprp, Dot)) { + // Dotted path: modport mp(input .a(inner.sig)) + bool hasPartSelect = false; + const string dottedPath = extractDottedPath(dotp, hasPartSelect); + if (hasPartSelect) { + fl->v3warn( + E_UNSUPPORTED, + "Unsupported: Modport expression with part select (IEEE 1800-2023 25.5.4)"); + } else { + string baddot; + VSymEnt* okSymp = nullptr; + symp = m_statep->findDotted(fl, m_curSymp, dottedPath, baddot, okSymp, true); + + // Handle nested interface path when findDotted had partial match + if (okSymp && !baddot.empty()) { + VSymEnt* const resolved = resolveNestedInterfacePath(fl, okSymp, baddot); + if (resolved) symp = resolved; + } + + if (!symp || !baddot.empty()) { + fl->v3error("Can't find modport expression target: " + << AstNode::prettyNameQ(dottedPath)); + symp = nullptr; + } + } + } else if (VN_IS(exprp, SelBit) || VN_IS(exprp, SelExtract)) { + // Part select expressions not yet supported + fl->v3warn(E_UNSUPPORTED, + "Unsupported: Modport expression with part select (IEEE 1800-2023 25.5.4)"); + } else { + // Other expression types not supported + fl->v3warn(E_UNSUPPORTED, + "Unsupported: Complex modport expression (IEEE 1800-2023 25.5.4)"); + } + return symp; + } + void visit(AstModportVarRef* nodep) override { // IfaceVisitor:: UINFO(5, " fiv: " << nodep); iterateChildren(nodep); VSymEnt* symp = nullptr; if (nodep->exprp()) { - nodep->v3warn(E_UNSUPPORTED, - "Unsupported: Modport expressions (IEEE 1800-2023 25.5.4)"); + // Modport expression syntax: modport mp(input .port_name(expression)) + symp = resolveModportExpression(nodep->fileline(), nodep->exprp()); } else { symp = m_curSymp->findIdFallback(nodep->name()); } @@ -2542,11 +2777,30 @@ class LinkDotIfaceVisitor final : public VNVisitor { // Make symbol under modport that points at the _interface_'s var via the modport. // (Need modport still to test input/output markings) nodep->varp(varp); - m_statep->insertSym(m_curSymp, nodep->name(), nodep, nullptr /*package*/); + if (nodep->exprp()) { + // For modport expressions, insert symbol pointing to the underlying var (not the + // ModportVarRef which will be deleted during scope creation). The virtual port + // name maps to the real signal's var. + VSymEnt* const subSymp + = m_statep->insertSym(m_curSymp, nodep->name(), varp, nullptr /*package*/); + m_statep->insertScopeAlias(LinkDotState::SAMN_MODPORT, subSymp, symp); + } else { + // For regular modport items, insert symbol pointing to ModportVarRef for + // input/output marking tests. + m_statep->insertSym(m_curSymp, nodep->name(), nodep, nullptr /*package*/); + } } else if (AstVarScope* const vscp = VN_CAST(symp->nodep(), VarScope)) { // Make symbol under modport that points at the _interface_'s var, not the modport. nodep->varp(vscp->varp()); - m_statep->insertSym(m_curSymp, nodep->name(), vscp, nullptr /*package*/); + // Only insert symbol for modport expression virtual ports (exprp set). + // For regular modport items, don't insert into the shared modport table because + // each instance would overwrite the previous one, causing wrong VarScope lookups. + // Regular items are found via the modport's fallback to the interface. + if (nodep->exprp()) { + VSymEnt* const subSymp + = m_statep->insertSym(m_curSymp, nodep->name(), vscp, nullptr /*package*/); + m_statep->insertScopeAlias(LinkDotState::SAMN_MODPORT, subSymp, symp); + } } else { nodep->v3error("Modport item is not a variable: " << nodep->prettyNameQ()); } @@ -2743,13 +2997,53 @@ class LinkDotResolveVisitor final : public VNVisitor { return nullptr; } } + + // Look up a virtual port through modport expression mapping. + // When a dotted reference uses a modport with expression syntax, the virtual port name + // maps to the real signal. This helper resolves that mapping during scope creation. + // Returns the VarScope for the real signal, or nullptr if not found. + AstVarScope* findVirtualPortVarScope(VSymEnt* dotSymp, const string& portName) { + const AstVarScope* const dotVscp = VN_CAST(dotSymp->nodep(), VarScope); + const AstVar* const dotVarp = dotVscp ? dotVscp->varp() : nullptr; + if (!dotVarp) return nullptr; + + AstNodeDType* dtypep = dotVarp->childDTypep(); + if (!dtypep) dtypep = dotVarp->subDTypep(); + if (!dtypep) return nullptr; + const AstIfaceRefDType* const ifaceRefp = VN_CAST(dtypep, IfaceRefDType); + if (!ifaceRefp || !ifaceRefp->modportp() || !ifaceRefp->ifaceViaCellp()) return nullptr; + + // Get the interface cell's symbol table + VSymEnt* const ifaceCellSymp = m_statep->getNodeSym(ifaceRefp->ifaceViaCellp()); + + // Look up modport by name in interface cell + VSymEnt* const modportSymp = ifaceCellSymp->findIdFallback(ifaceRefp->modportp()->name()); + if (!modportSymp) return nullptr; + + // Look up virtual port name in modport symbol table + string baddot; + VSymEnt* const virtPortp = m_statep->findSymPrefixed(modportSymp, portName, baddot, true); + if (!virtPortp) return nullptr; + + // Symbol may point to VarScope or Var + if (AstVarScope* vscp = VN_CAST(virtPortp->nodep(), VarScope)) return vscp; + + // Symbol points to Var - look up VarScope by name in interface cell + if (const AstVar* const realVarp = VN_CAST(virtPortp->nodep(), Var)) { + VSymEnt* const realFoundp + = m_statep->findSymPrefixed(ifaceCellSymp, realVarp->name(), baddot, true); + return realFoundp ? VN_CAST(realFoundp->nodep(), VarScope) : nullptr; + } + return nullptr; + } + AstNodeStmt* addImplicitSuperNewCall(AstFunc* const nodep, const AstClassExtends* const classExtendsp) { // Returns the added node FileLine* const fl = nodep->fileline(); - AstNodeExpr* pinsp = nullptr; - if (classExtendsp->argsp()) pinsp = classExtendsp->argsp()->cloneTree(true); - AstNew* const newExprp = new AstNew{fl, pinsp}; + AstArg* argsp = nullptr; + if (classExtendsp->argsp()) argsp = classExtendsp->argsp()->cloneTree(true); + AstNew* const newExprp = new AstNew{fl, argsp}; newExprp->isImplicit(true); AstDot* const superNewp = new AstDot{fl, false, new AstParseRef{fl, "super"}, newExprp}; AstNodeStmt* const superNewStmtp = superNewp->makeStmt(); @@ -3313,15 +3607,23 @@ class LinkDotResolveVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); return; } else { - const string suggest + const std::string suggest = (nodep->param() ? m_statep->suggestSymFlat(m_pinSymp, nodep->name(), LinkNodeMatcherVarParam{}) : m_statep->suggestSymFlat(m_pinSymp, nodep->name(), LinkNodeMatcherVarIO{})); + const std::string decl + = ((m_cellp && m_cellp->modp()) + ? "\n"s + nodep->warnMore() + "... Location of instance's " + + m_cellp->modp()->verilogKwd() + " declaration\n" + + m_cellp->modp()->warnContextSecondary() + : ""); nodep->v3warn(PINNOTFOUND, ucfirst(whatp) << " not found: " << nodep->prettyNameQ() << '\n' - << (suggest.empty() ? "" : nodep->warnMore() + suggest)); + << (suggest.empty() ? "" : nodep->warnMore() + suggest) + << '\n' + << nodep->warnContextPrimary() << decl); return; } } @@ -3384,6 +3686,9 @@ class LinkDotResolveVisitor final : public VNVisitor { if (VN_IS(nodep->lhsp(), ParseRef) && nodep->lhsp()->name() == "this") { VSymEnt* classSymp = getThisClassSymp(); + // In 'randomize() with { this.member }', 'this' refers to randomized + // object, not the calling class (IEEE 1800-2023 18.7) + if (m_randSymp && m_inWith) classSymp = m_randSymp; if (!classSymp) { nodep->v3error("'this' used outside class (IEEE 1800-2023 8.11)"); m_ds.m_dotErr = true; @@ -3427,7 +3732,7 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds = lastStates; // Resolve function args before bailing if (AstNodeFTaskRef* const ftaskrefp = VN_CAST(nodep->rhsp(), NodeFTaskRef)) { - iterateAndNextNull(ftaskrefp->pinsp()); + iterateAndNextNull(ftaskrefp->argsp()); } return; } @@ -3455,7 +3760,7 @@ class LinkDotResolveVisitor final : public VNVisitor { // Resolve function args before bailing if (AstNodeFTaskRef* const ftaskrefp = VN_CAST(nodep->rhsp(), NodeFTaskRef)) { - iterateAndNextNull(ftaskrefp->pinsp()); + iterateAndNextNull(ftaskrefp->argsp()); } return; } @@ -3465,7 +3770,7 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds = lastStates; // Resolve function args before bailing if (AstNodeFTaskRef* const ftaskrefp = VN_CAST(nodep->rhsp(), NodeFTaskRef)) { - iterateAndNextNull(ftaskrefp->pinsp()); + iterateAndNextNull(ftaskrefp->argsp()); } return; } @@ -3732,6 +4037,24 @@ class LinkDotResolveVisitor final : public VNVisitor { } else { foundp = m_ds.m_dotSymp->findIdFlat(nodep->name()); } + // If not found in modport, check interface fallback for parameters. + // Parameters are always visible through a modport (IEEE 1800-2023 25.5). + // This mirrors the VarXRef modport parameter fallback in visit(AstVarXRef). + if (!foundp && VN_IS(m_ds.m_dotSymp->nodep(), Modport) + && m_ds.m_dotSymp->fallbackp()) { + VSymEnt* const ifaceFoundp + = m_ds.m_dotSymp->fallbackp()->findIdFlat(nodep->name()); + if (ifaceFoundp) { + if (const AstVar* const varp = VN_CAST(ifaceFoundp->nodep(), Var)) { + if (varp->isParam()) foundp = ifaceFoundp; + } + } + } + // When flat lookup in modport fails, provide dotSymp for error diagnostics + // so the "Known scopes under..." hint appears (restores pre-routing behavior) + if (!foundp && !okSymp && VN_IS(m_ds.m_dotSymp->nodep(), Modport)) { + okSymp = m_ds.m_dotSymp; + } if (foundp) { UINFO(9, indent() << "found=se" << cvtToHex(foundp) << " exp=" << expectWhat << " n=" << foundp->nodep()); @@ -3808,9 +4131,9 @@ class LinkDotResolveVisitor final : public VNVisitor { } else if (allowFTask && VN_IS(foundp->nodep(), NodeFTask)) { AstNodeFTaskRef* taskrefp; if (VN_IS(foundp->nodep(), Task)) { - taskrefp = new AstTaskRef{nodep->fileline(), nodep->name(), nullptr}; + taskrefp = new AstTaskRef{nodep->fileline(), nodep->name()}; } else { - taskrefp = new AstFuncRef{nodep->fileline(), nodep->name(), nullptr}; + taskrefp = new AstFuncRef{nodep->fileline(), nodep->name()}; } nodep->replaceWith(taskrefp); VL_DO_DANGLING(pushDeletep(nodep), nodep); @@ -3828,7 +4151,12 @@ class LinkDotResolveVisitor final : public VNVisitor { // Really this is a scope reference into an interface UINFO(9, indent() << "varref-ifaceref " << m_ds.m_dotText << " " << nodep); m_ds.m_dotText = VString::dot(m_ds.m_dotText, ".", nodep->name()); - m_ds.m_dotSymp = m_statep->getNodeSym(ifacerefp->ifaceViaCellp()); + // If modport specified, use modport symbol table for lookup of virtual ports + if (ifacerefp->modportp() && m_statep->existsNodeSym(ifacerefp->modportp())) { + m_ds.m_dotSymp = m_statep->getNodeSym(ifacerefp->modportp()); + } else { + m_ds.m_dotSymp = m_statep->getNodeSym(ifacerefp->ifaceViaCellp()); + } m_ds.m_dotPos = DP_SCOPE; ok = true; AstNode* const newp = new AstVarRef{nodep->fileline(), varp, VAccess::READ}; @@ -3978,6 +4306,12 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotSymp = foundp; if (m_ds.m_dotText != "") m_ds.m_dotText += "." + nodep->name(); ok = m_ds.m_dotPos == DP_SCOPE || m_ds.m_dotPos == DP_FIRST; + } else if (const AstModportClockingRef* const clockingRefp + = VN_CAST(foundp->nodep(), ModportClockingRef)) { + // Clocking block accessed through a modport - redirect to actual clocking + m_ds.m_dotSymp = m_statep->getNodeSym(clockingRefp->clockingp()); + if (m_ds.m_dotText != "") m_ds.m_dotText += "." + nodep->name(); + ok = m_ds.m_dotPos == DP_SCOPE || m_ds.m_dotPos == DP_FIRST; } else if (const AstNodeFTask* const ftaskp = VN_CAST(foundp->nodep(), NodeFTask)) { if (!ftaskp->isFunction() || ftaskp->classMethod()) { ok = m_ds.m_dotPos == DP_NONE; @@ -3987,7 +4321,7 @@ class LinkDotResolveVisitor final : public VNVisitor { // In these cases, the parentheses may be skipped. // Also SV class methods can be called without parens AstFuncRef* const funcRefp - = new AstFuncRef{nodep->fileline(), nodep->name(), nullptr}; + = new AstFuncRef{nodep->fileline(), nodep->name()}; nodep->replaceWith(funcRefp); VL_DO_DANGLING(pushDeletep(nodep), nodep); } @@ -4039,8 +4373,12 @@ class LinkDotResolveVisitor final : public VNVisitor { [this](AstVar* v, AstRefDType* r) { return promoteVarToParamType(v, r); }, [this]() { return indent(); }); - replaceWithCheckBreak(nodep, refp); - VL_DO_DANGLING(pushDeletep(nodep), nodep); + if (VN_IS(nodep->backp(), SelExtract)) { + m_packedArrayDtp = refp; + } else { + replaceWithCheckBreak(nodep, refp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + } } } if (!ok) { @@ -4261,7 +4599,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } bool modport = false; - if (const AstVar* varp = VN_CAST(dotSymp->nodep(), Var)) { + if (const AstVar* const varp = VN_CAST(dotSymp->nodep(), Var)) { if (const AstIfaceRefDType* const ifaceRefp = VN_CAST(varp->childDTypep(), IfaceRefDType)) { if (ifaceRefp->modportp()) { @@ -4322,10 +4660,10 @@ class LinkDotResolveVisitor final : public VNVisitor { << okSymp->cellErrorScopes(nodep)); return; } - // V3Inst may have expanded arrays of interfaces to - // AstVarXRef's even though they are in the same module detect - // this and convert to normal VarRefs - if (!m_statep->forPrearray() && !m_statep->forScopeCreation()) { + // V3Inst may have expanded arrays of interfaces to AstVarXRef's even though + // they are in the same module; convert to normal VarRefs (but not if dotted) + if (!m_statep->forPrearray() && !m_statep->forScopeCreation() + && nodep->dotted().empty()) { if (const AstIfaceRefDType* const ifaceDtp = VN_CAST(nodep->dtypep(), IfaceRefDType)) { if (!ifaceDtp->isVirtual()) { @@ -4339,7 +4677,9 @@ class LinkDotResolveVisitor final : public VNVisitor { } else { VSymEnt* const foundp = m_statep->findSymPrefixed(dotSymp, nodep->name(), baddot, true); - AstVarScope* vscp = foundp ? VN_AS(foundp->nodep(), VarScope) : nullptr; + AstVarScope* vscp = foundp ? VN_CAST(foundp->nodep(), VarScope) : nullptr; + // Handle modport expression virtual ports + if (!vscp) vscp = findVirtualPortVarScope(dotSymp, nodep->name()); // If found, check if it's ok to access in case it's in a hier_block if (vscp && errorHierNonPort(nodep, vscp->varp(), dotSymp)) return; if (!vscp) { @@ -4406,7 +4746,7 @@ class LinkDotResolveVisitor final : public VNVisitor { VL_RESTORER(m_randMethodCallp); { m_ds.init(m_curSymp); - if (nodep->name() == "randomize" && nodep->pinsp()) { + if (nodep->name() == "randomize" && (nodep->argsp() || nodep->withp())) { m_randMethodCallp = nodep; const AstNodeDType* fromDtp = nodep->fromp()->dtypep(); if (!fromDtp) { @@ -4416,7 +4756,7 @@ class LinkDotResolveVisitor final : public VNVisitor { fromDtp = getExprDTypep(nodep->fromp()); } if (!fromDtp) { - if (VN_IS(nodep->pinsp(), With)) { + if (nodep->withp()) { nodep->v3warn( E_UNSUPPORTED, "Unsupported: 'randomize() with' on complex expressions"); @@ -4530,10 +4870,11 @@ class LinkDotResolveVisitor final : public VNVisitor { // Found a Var, everything following is method call. // {scope}.{var}.HERE {method} ( ARGS ) AstNodeExpr* const varEtcp = VN_AS(m_ds.m_dotp->lhsp()->unlinkFrBack(), NodeExpr); - AstNodeExpr* argsp = nullptr; - if (nodep->pinsp()) argsp = nodep->pinsp()->unlinkFrBackWithNext(); - AstNode* const newp = new AstMethodCall{nodep->fileline(), varEtcp, VFlagChildDType{}, - nodep->name(), argsp}; + AstArg* const argsp = nodep->argsp(); + if (argsp) argsp->unlinkFrBackWithNext(); + AstMethodCall* const newp = new AstMethodCall{nodep->fileline(), varEtcp, + VFlagChildDType{}, nodep->name(), argsp}; + if (AstWith* const withp = nodep->withp()) newp->withp(withp->unlinkFrBack()); nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); return; @@ -4581,10 +4922,10 @@ class LinkDotResolveVisitor final : public VNVisitor { VSymEnt* const foundp = m_randSymp->findIdFlat(nodep->name()); if (foundp && m_inWith) { UINFO(9, indent() << "randomize-with fromSym " << foundp->nodep()); - AstNodeExpr* argsp = nullptr; - if (nodep->pinsp()) { - iterateAndNextNull(nodep->pinsp()); - argsp = nodep->pinsp()->unlinkFrBackWithNext(); + AstArg* argsp = nullptr; + if (nodep->argsp()) { + iterateAndNextNull(nodep->argsp()); + argsp = nodep->argsp()->unlinkFrBackWithNext(); } if (m_ds.m_dotPos != DP_NONE) m_ds.m_dotPos = DP_MEMBER; AstNode* const newp = new AstMethodCall{ @@ -4685,15 +5026,10 @@ class LinkDotResolveVisitor final : public VNVisitor { if (VN_IS(nodep, FuncRef)) { newp = new AstConst{nodep->fileline(), AstConst::All0{}}; } else { - AstNode* outp = nullptr; - while (nodep->pinsp()) { - AstNode* const pinp = nodep->pinsp()->unlinkFrBack(); - AstNode* addp = pinp; - if (AstArg* const argp = VN_CAST(pinp, Arg)) { - addp = argp->exprp()->unlinkFrBack(); - VL_DO_DANGLING2(pushDeletep(pinp), pinp, argp); - } - outp = AstNode::addNext(outp, addp); + AstNodeExpr* outp = nullptr; + while (AstArg* const argp = nodep->argsp()) { + outp = AstNode::addNext(outp, argp->exprp()->unlinkFrBack()); + VL_DO_DANGLING(pushDeletep(argp->unlinkFrBack()), argp); } newp = new AstSysIgnore{nodep->fileline(), outp}; newp->dtypep(nodep->dtypep()); @@ -4983,7 +5319,10 @@ class LinkDotResolveVisitor final : public VNVisitor { cprp = dotp->rhsp(); VSymEnt* const foundp = m_statep->resolveClassOrPackage( lookSymp, lookNodep, true, false, nodep->verilogKwd()); - if (!foundp) return; + if (!foundp) { + VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); + return; + } UASSERT_OBJ(lookNodep->classOrPackageSkipp(), nodep, "Bad package link"); lookSymp = m_statep->getNodeSym(lookNodep->classOrPackageSkipp()); } else { @@ -4995,27 +5334,41 @@ class LinkDotResolveVisitor final : public VNVisitor { if (VL_UNCOVERABLE(!cpackagerefp)) { // Linking the extend gives an error before this is hit nodep->v3error("Attempting to extend using non-class"); // LCOV_EXCL_LINE + VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); return; } VSymEnt* const foundp = m_statep->resolveClassOrPackage(lookSymp, cpackagerefp, true, true, nodep->verilogKwd()); - if (foundp) { - if (AstClass* const classp = VN_CAST(foundp->nodep(), Class)) { + if (!foundp) { + VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); + return; + } + if (AstClass* const classp = VN_CAST(foundp->nodep(), Class)) { + AstPin* paramsp = cpackagerefp->paramsp(); + if (paramsp) { + paramsp = paramsp->cloneTree(true); + nodep->parameterized(true); + } + nodep->childDTypep(new AstClassRefDType{nodep->fileline(), classp, paramsp}); + // Link pins + iterate(nodep->childDTypep()); + } else if (AstParamTypeDType* const paramp + = VN_CAST(foundp->nodep(), ParamTypeDType)) { + AstRefDType* const refParamp = new AstRefDType{nodep->fileline(), paramp->name()}; + refParamp->refDTypep(paramp); + nodep->childDTypep(refParamp); + nodep->parameterized(true); + } else if (AstTypedef* const typedefp = VN_CAST(foundp->nodep(), Typedef)) { + AstNodeDType* const unwrappedp = typedefp->subDTypep()->skipRefp(); + if (AstClassRefDType* const classRefp = VN_CAST(unwrappedp, ClassRefDType)) { AstPin* paramsp = cpackagerefp->paramsp(); if (paramsp) { paramsp = paramsp->cloneTree(true); nodep->parameterized(true); } - nodep->childDTypep(new AstClassRefDType{nodep->fileline(), classp, paramsp}); - // Link pins + nodep->childDTypep( + new AstClassRefDType{nodep->fileline(), classRefp->classp(), paramsp}); iterate(nodep->childDTypep()); - } else if (AstParamTypeDType* const paramp - = VN_CAST(foundp->nodep(), ParamTypeDType)) { - AstRefDType* const refParamp - = new AstRefDType{nodep->fileline(), paramp->name()}; - refParamp->refDTypep(paramp); - nodep->childDTypep(refParamp); - nodep->parameterized(true); } else { nodep->v3warn(E_UNSUPPORTED, "Unsupported: " << foundp->nodep()->prettyTypeName() @@ -5023,6 +5376,8 @@ class LinkDotResolveVisitor final : public VNVisitor { return; } } else { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: " << foundp->nodep()->prettyTypeName() + << " in 'class extends'"); return; } if (!nodep->childDTypep()) nodep->v3error("Attempting to extend using non-class"); diff --git a/src/V3LinkDot.h b/src/V3LinkDot.h index 1169044e8..257d522c3 100644 --- a/src/V3LinkDot.h +++ b/src/V3LinkDot.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkDotIfaceCapture.cpp b/src/V3LinkDotIfaceCapture.cpp index 8f719bee5..9c6a6bad0 100644 --- a/src/V3LinkDotIfaceCapture.cpp +++ b/src/V3LinkDotIfaceCapture.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -47,16 +47,17 @@ bool V3LinkDotIfaceCapture::finalizeCapturedEntry(CapturedMap::iterator it, cons string V3LinkDotIfaceCapture::extractIfacePortName(const string& dotText) { string name = dotText; const size_t dotPos = name.find('.'); - if (dotPos != string::npos) name = name.substr(0, dotPos); + if (dotPos != string::npos) name.resize(dotPos); const size_t braPos = name.find("__BRA__"); - if (braPos != string::npos) name = name.substr(0, braPos); + if (braPos != string::npos) name.resize(braPos); return name; } void V3LinkDotIfaceCapture::add(AstRefDType* refp, AstCell* cellp, AstNodeModule* ownerModp, AstTypedef* typedefp, AstNodeModule* typedefOwnerModp, AstVar* ifacePortVarp) { - if (!refp) return; + // TODO -- probably classes too + if (!refp || cellp->modp() == ownerModp) return; if (!typedefp) typedefp = refp->typedefp(); if (!typedefOwnerModp && typedefp) typedefOwnerModp = findOwnerModule(typedefp); s_map[refp] = CapturedIfaceTypedef{ @@ -203,7 +204,7 @@ void V3LinkDotIfaceCapture::captureTypedefContext( AstVar* ifacePortVarp = nullptr; if (!dotText.empty() && curSymp) { const std::string portName = extractIfacePortName(dotText); - if (VSymEnt* const portSymp = curSymp->findIdFallback(portName)) { + if (const VSymEnt* const portSymp = curSymp->findIdFallback(portName)) { ifacePortVarp = VN_CAST(portSymp->nodep(), Var); UINFO(9, indentFn() << "iface capture found port var '" << portName << "' -> " << ifacePortVarp); diff --git a/src/V3LinkDotIfaceCapture.h b/src/V3LinkDotIfaceCapture.h index c0958b7b4..7c7f53cce 100644 --- a/src/V3LinkDotIfaceCapture.h +++ b/src/V3LinkDotIfaceCapture.h @@ -9,10 +9,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkInc.cpp b/src/V3LinkInc.cpp index e29bd7578..cf34778a9 100644 --- a/src/V3LinkInc.cpp +++ b/src/V3LinkInc.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -308,6 +308,7 @@ class LinkIncVisitor final : public VNVisitor { AstVar* const varp = new AstVar{ fl, VVarType::BLOCKTEMP, name, VFlagChildDType{}, new AstRefDType{fl, AstRefDType::FlagTypeOfExpr{}, readp->cloneTree(true)}}; + varp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); if (m_ftaskp) varp->funcLocal(true); // Declare the variable diff --git a/src/V3LinkInc.h b/src/V3LinkInc.h index 7a86e588d..2ff490c4a 100644 --- a/src/V3LinkInc.h +++ b/src/V3LinkInc.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp index a5e6b5ab1..0fd82701e 100644 --- a/src/V3LinkJump.cpp +++ b/src/V3LinkJump.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -89,7 +89,7 @@ class LinkJumpVisitor final : public VNVisitor { underp = fTaskp->stmtsp(); } else if (AstForeach* const foreachp = VN_CAST(nodep, Foreach)) { if (endOfIter) { - underp = foreachp->stmtsp(); + underp = foreachp->bodyp(); // Keep a LoopTest **at the front** outside the jump block if (VN_IS(underp, LoopTest)) underp = underp->nextp(); } else { @@ -172,7 +172,7 @@ class LinkJumpVisitor final : public VNVisitor { AstClass* const processClassp = VN_AS(getMemberp(v3Global.rootp()->stdPackagep(), "process"), Class); AstFunc* const selfMethodp = VN_AS(getMemberp(processClassp, "self"), Func); - AstFuncRef* const processSelfp = new AstFuncRef{fl, selfMethodp, nullptr}; + AstFuncRef* const processSelfp = new AstFuncRef{fl, selfMethodp}; processSelfp->classOrPackagep(processClassp); return new AstStmtExpr{ fl, new AstMethodCall{fl, queueRefp, "push_back", new AstArg{fl, "", processSelfp}}}; @@ -351,7 +351,7 @@ class LinkJumpVisitor final : public VNVisitor { void visit(AstNodeForeach* nodep) override { VL_RESTORER(m_loopp); m_loopp = nodep; - iterateAndNextNull(nodep->stmtsp()); + iterateAndNextNull(nodep->bodyp()); } void visit(AstReturn* nodep) override { iterateChildren(nodep); diff --git a/src/V3LinkJump.h b/src/V3LinkJump.h index a2523d2d3..8473020b8 100644 --- a/src/V3LinkJump.h +++ b/src/V3LinkJump.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkLValue.cpp b/src/V3LinkLValue.cpp index 8b14e2379..c8a701888 100644 --- a/src/V3LinkLValue.cpp +++ b/src/V3LinkLValue.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -39,6 +39,7 @@ class LinkLValueVisitor final : public VNVisitor { bool m_setStrengthSpecified = false; // Set that var has assignment with strength specified. bool m_inFunc = false; // Set if inside AstNodeFTask bool m_inInitialStatic = false; // Set if inside AstInitialStatic + bool m_inInitialStaticStmt = false; // Set if inside AstInitialStaticStmt VAccess m_setRefLvalue; // Set VarRefs to lvalues for pin assignments // VISITORS @@ -113,7 +114,7 @@ class LinkLValueVisitor final : public VNVisitor { iterateAndNextNull(nodep->rhsp()); } - if (m_inInitialStatic && m_inFunc) { + if ((m_inInitialStatic || m_inInitialStaticStmt) && m_inFunc) { const bool rhsHasIO = nodep->rhsp()->exists([](const AstNodeVarRef* const refp) { // Exclude module I/O referenced from a function/task. return refp->varp() && refp->varp()->isIO() @@ -147,6 +148,11 @@ class LinkLValueVisitor final : public VNVisitor { m_inInitialStatic = true; iterateChildren(nodep); } + void visit(AstInitialStaticStmt* nodep) override { + VL_RESTORER(m_inInitialStaticStmt); + m_inInitialStaticStmt = true; + iterateChildren(nodep); + } void visit(AstRelease* nodep) override { VL_RESTORER(m_setRefLvalue); VL_RESTORER(m_setContinuously); @@ -336,6 +342,7 @@ class LinkLValueVisitor final : public VNVisitor { iterate(pinp); } } + if (nodep->withp()) iterate(nodep->withp()); } void visit(AstConstraint* nodep) override { VL_RESTORER(m_setIfRand); diff --git a/src/V3LinkLValue.h b/src/V3LinkLValue.h index 52200b43f..008edc65c 100644 --- a/src/V3LinkLValue.h +++ b/src/V3LinkLValue.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp index 4c596f7e1..c6a5621d2 100644 --- a/src/V3LinkLevel.cpp +++ b/src/V3LinkLevel.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkLevel.h b/src/V3LinkLevel.h index c4f122bae..6ced1358b 100644 --- a/src/V3LinkLevel.h +++ b/src/V3LinkLevel.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index 3e569a3e1..4e238c75f 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -23,7 +23,6 @@ #include "V3LinkParse.h" #include "V3Control.h" -#include "V3MemberMap.h" #include "V3Stats.h" #include @@ -47,7 +46,6 @@ class LinkParseVisitor final : public VNVisitor { // STATE - across all visitors std::unordered_set m_filelines; // Filelines that have been seen - VMemberMap m_memberMap; // for lookup of process class methods // STATE - for current visit position (use VL_RESTORER) // If set, move AstVar->valuep() initial values to this module @@ -59,6 +57,8 @@ class LinkParseVisitor final : public VNVisitor { AstNodeProcedure* m_procedurep = nullptr; // Current procedure AstNodeFTask* m_ftaskp = nullptr; // Current task AstNodeBlock* m_blockp = nullptr; // Current AstNodeBlock + AstNodeStmt* m_blockAddAutomaticStmtp = nullptr; // Initial statements to add to block + AstNodeStmt* m_blockAddStaticStmtp = nullptr; // Initial statements to add to block AstNodeDType* m_dtypep = nullptr; // Current data type AstNodeExpr* m_defaultInSkewp = nullptr; // Current default input skew AstNodeExpr* m_defaultOutSkewp = nullptr; // Current default output skew @@ -68,16 +68,13 @@ class LinkParseVisitor final : public VNVisitor { int m_beginDepth = 0; // How many begin blocks above current node within current AstNodeModule int m_randSequenceNum = 0; // RandSequence uniqify number VLifetime m_lifetime = VLifetime::STATIC_IMPLICIT; // Propagating lifetime - bool m_insideLoop = false; // True if the node is inside a loop bool m_lifetimeAllowed = false; // True to allow lifetime settings bool m_moduleWithGenericIface = false; // If current module contains generic interface + std::set m_portDups; // Non-ANSI port datatype duplicating input/output decls // STATE - Statistic tracking VDouble0 m_statModules; // Number of modules seen - bool m_unprotectedStdProcess - = false; // Set when std::process internals were unprotected, we only need to do this once - // METHODS void cleanFileline(AstNode* nodep) { if (nodep->user2SetOnce()) return; // Process once @@ -111,21 +108,6 @@ class LinkParseVisitor final : public VNVisitor { return ""; } - void unprotectStdProcessHandle() { - if (m_unprotectedStdProcess) return; - m_unprotectedStdProcess = true; - if (!v3Global.opt.protectIds()) return; - if (AstPackage* const stdp = v3Global.rootp()->stdPackagep()) { - if (AstClass* const processp - = VN_CAST(m_memberMap.findMember(stdp, "process"), Class)) { - if (AstVar* const handlep - = VN_CAST(m_memberMap.findMember(processp, "m_process"), Var)) { - handlep->protect(false); - } - } - } - } - void visitIterateNodeDType(AstNodeDType* nodep) { if (nodep->user1SetOnce()) return; // Process only once. cleanFileline(nodep); @@ -201,36 +183,52 @@ class LinkParseVisitor final : public VNVisitor { << nodep->warnContextSecondary()); } - void addForkParentProcess(AstFork* forkp) { - FileLine* const fl = forkp->fileline(); + void collectPorts(AstNode* nodeListp) { + // V3LinkDot hasn't run yet, so have VAR for pre-IEEE 'input' and + // separate var for pre-IEEE 'integer'. + std::unordered_map portNames; + for (AstNode* nodep = nodeListp; nodep; nodep = nodep->nextp()) { + if (AstVar* const varp = VN_CAST(nodep, Var)) { + if (varp->isIO()) portNames.emplace(varp->name(), varp); + } + } + for (AstNode* nodep = nodeListp; nodep; nodep = nodep->nextp()) { + if (AstVar* const varp = VN_CAST(nodep, Var)) { + if (varp->isIO()) continue; + const auto it = portNames.find(varp->name()); + if (it == portNames.end()) continue; + AstVar* const iop = it->second; + UINFO(9, "Non-ANSI port dtype declaration " << varp); + if (!iop->valuep() && varp->valuep()) + iop->valuep(varp->valuep()->unlinkFrBackWithNext()); + m_portDups.emplace(varp); + } + } + } - const std::string parentName = "__VforkParent"; - AstRefDType* const dtypep = new AstRefDType{fl, "process"}; - AstVar* const parentVar - = new AstVar{fl, VVarType::BLOCKTEMP, parentName, VFlagChildDType{}, dtypep}; - parentVar->lifetime(VLifetime::AUTOMATIC_EXPLICIT); - - AstParseRef* const lhsp = new AstParseRef{fl, parentName, nullptr, nullptr}; - AstClassOrPackageRef* const processRefp - = new AstClassOrPackageRef{fl, "process", nullptr, nullptr}; - AstParseRef* const selfRefp = new AstParseRef{fl, "self", nullptr, nullptr}; - AstDot* const processSelfp = new AstDot{fl, true, processRefp, selfRefp}; - AstMethodCall* const callp = new AstMethodCall{fl, processSelfp, "self", nullptr}; - AstAssign* const initp = new AstAssign{fl, lhsp, callp}; - - AstVarRef* const parentRefp = new AstVarRef{fl, parentVar, VAccess::READ}; - forkp->parentProcessp(parentRefp); - - VNRelinker relinker; - forkp->unlinkFrBack(&relinker); - - parentVar->addNextHere(initp); - initp->addNextHere(forkp); - - AstBegin* const beginp = new AstBegin{ - fl, forkp->name() == "" ? "" : forkp->name() + "__VgetForkParent", parentVar, true}; - - relinker.relink(beginp); + AstNode* getVarsAndUnlink(AstNode* stmtsp) { + AstNode* varsp = nullptr; + for (AstNode *nextp, *itemp = stmtsp; itemp; itemp = nextp) { + nextp = itemp->nextp(); + if (VN_IS(itemp, Var)) varsp = AstNode::addNext(varsp, itemp->unlinkFrBack()); + } + return varsp; + } + AstNodeStmt* getBlockAdds() { + AstNodeStmt* addsp = nullptr; + // Add a single AstInitial...Stmt as the statements within may + // depend on each other, e.g. "var a=1; var b=a;" (but must be a constant expression) + if (m_blockAddStaticStmtp) + addsp = AstNode::addNext(addsp, + new AstInitialStaticStmt{m_blockAddStaticStmtp->fileline(), + m_blockAddStaticStmtp}); + if (m_blockAddAutomaticStmtp) + addsp = AstNode::addNext( + addsp, new AstInitialAutomaticStmt{m_blockAddAutomaticStmtp->fileline(), + m_blockAddAutomaticStmtp}); + m_blockAddStaticStmtp = nullptr; + m_blockAddAutomaticStmtp = nullptr; + return addsp; } // VISITORS @@ -243,6 +241,10 @@ class LinkParseVisitor final : public VNVisitor { cleanFileline(nodep); VL_RESTORER(m_ftaskp); m_ftaskp = nodep; + VL_RESTORER(m_blockAddAutomaticStmtp); + m_blockAddAutomaticStmtp = nullptr; + VL_RESTORER(m_blockAddStaticStmtp); + m_blockAddStaticStmtp = nullptr; VL_RESTORER(m_lifetime); VL_RESTORER(m_lifetimeAllowed); m_lifetimeAllowed = true; @@ -264,7 +266,26 @@ class LinkParseVisitor final : public VNVisitor { << nodep->warnMore() << "... May have intended 'static " << nodep->verilogKwd() << "'"); } + + VL_RESTORER(m_portDups); + collectPorts(nodep->stmtsp()); + iterateChildren(nodep); + + // If let, the statement must go first + AstNode* stmtsp = nullptr; + if (VN_IS(nodep, Let) && nodep->stmtsp()) stmtsp = nodep->stmtsp()->unlinkFrBack(); + // Move all Vars to front of function + stmtsp = AstNode::addNextNull(stmtsp, getVarsAndUnlink(nodep->stmtsp())); + // Follow vars by m_blockAddp's (if any) + stmtsp = AstNode::addNextNull(stmtsp, getBlockAdds()); + if (stmtsp) { + if (nodep->stmtsp()) { + nodep->stmtsp()->addHereThisAsNext(stmtsp); + } else { + nodep->addStmtsp(stmtsp); + } + } } void visit(AstNodeDType* nodep) override { visitIterateNodeDType(nodep); } void visit(AstConstraint* nodep) override { @@ -317,21 +338,20 @@ class LinkParseVisitor final : public VNVisitor { void visit(AstVar* nodep) override { cleanFileline(nodep); - if (nodep->lifetime().isStatic() && m_insideLoop && nodep->valuep()) { - nodep->lifetime(VLifetime::AUTOMATIC_IMPLICIT); - nodep->v3warn(STATICVAR, "Static variable with assignment declaration declared in a " - "loop converted to automatic"); - } else if (nodep->valuep() && nodep->lifetime().isNone() && m_lifetime.isStatic() - && !nodep->isIO() - && !nodep->isParam() - // In task, or a procedure but not Initial/Final as executed only once - && ((m_ftaskp && !m_ftaskp->lifetime().isStaticExplicit()) - || (m_procedurep && !VN_IS(m_procedurep, Initial) - && !VN_IS(m_procedurep, Final)))) { + UINFO(9, "VAR " << nodep); + if (nodep->valuep()) nodep->hasUserInit(true); + // IEEE 1800-2026 6.21: for loop variables are automatic. verilog.y is + // responsible for marking those. + if (nodep->valuep() && nodep->lifetime().isNone() && m_lifetime.isStatic() + && !nodep->isIO() + && !nodep->isParam() + // In task, or a procedure but not Initial/Final as executed only once + && ((m_ftaskp && !m_ftaskp->lifetime().isStaticExplicit()) || m_procedurep)) { if (VN_IS(m_modp, Module) && m_ftaskp) { m_ftaskp->v3warn( IMPLICITSTATIC, - "Function/task's lifetime implicitly set to static\n" + "Function/task's lifetime implicitly set to static;" + " variables made static (IEEE 1800-2023 6.21)\n" << m_ftaskp->warnMore() << "... Suggest use '" << m_ftaskp->verilogKwd() << " automatic' or '" << m_ftaskp->verilogKwd() << " static'\n" << m_ftaskp->warnContextPrimary() << '\n' @@ -339,12 +359,12 @@ class LinkParseVisitor final : public VNVisitor { << nodep->warnMore() << "... The initializer value will only be set once\n" << nodep->warnContextSecondary()); } else { - nodep->v3warn(IMPLICITSTATIC, - "Variable's lifetime implicitly set to static\n" - << nodep->warnMore() - << "... The initializer value will only be set once\n" - << nodep->warnMore() - << "... Suggest use 'static' before variable declaration'"); + nodep->v3warn( + IMPLICITSTATIC, + "Variable's lifetime implicitly set to static (IEEE 1800-2023 6.21)\n" + << nodep->warnMore() << "... The initializer value will only be set once\n" + << nodep->warnMore() + << "... Suggest use 'static' before variable declaration'"); } } if (!m_lifetimeAllowed && nodep->lifetime().isAutomatic()) { @@ -462,43 +482,75 @@ class LinkParseVisitor final : public VNVisitor { // temporaries under an always aren't expected to be blocking if (m_procedurep && VN_IS(m_procedurep, Always)) nodep->fileline()->modifyWarnOff(V3ErrorCode::BLKSEQ, true); - if (nodep->valuep()) { - FileLine* const fl = nodep->valuep()->fileline(); - // A variable with an = value can be 4 things: - if (nodep->isParam() || (m_ftaskp && nodep->isNonOutput())) { + // Compute initial value + if (nodep->valuep() || nodep->needsCReset()) { + FileLine* const fl = nodep->valuep() ? nodep->valuep()->fileline() : nodep->fileline(); + auto createValuep = [&]() -> AstNodeExpr* { + if (nodep->valuep()) { + return VN_AS(nodep->valuep()->unlinkFrBack(), NodeExpr); + } else { + return new AstCReset{fl, nodep, false}; + } + }; + // A variable can be in these positions related to having an initial value (or not): + if (m_portDups.find(nodep) != m_portDups.end()) { + // 0. Non-ANSI type declaration that is really a port, but we haven't resolved yet + // Earlier moved any valuep() under the duplicate to the IO declaration + UINFO(9, "VarInit case0 " << nodep); + } else if (nodep->isParam() || nodep->isGenVar() + || (m_ftaskp && (nodep->isNonOutput() || nodep->isFuncReturn()))) { // 1. Parameters and function inputs: It's a default to use if not overridden + UINFO(9, "VarInit case1 " << nodep); } else if (!m_ftaskp && !VN_IS(m_modp, Class) && nodep->isNonOutput() && !nodep->isInput()) { // 2. Module inout/ref/constref: const default to use - nodep->v3warn(E_UNSUPPORTED, - "Unsupported: Default value on module inout/ref/constref: " - << nodep->prettyNameQ()); - nodep->valuep()->unlinkFrBack()->deleteTree(); - } else if (m_blockp) { + UINFO(9, "VarInit case2 " << nodep); + if (nodep->valuep()) { + nodep->v3warn(E_UNSUPPORTED, + "Unsupported: Default value on module inout/ref/constref: " + << nodep->prettyNameQ()); + nodep->valuep()->unlinkFrBack()->deleteTree(); + } + } else if (m_blockp || m_ftaskp) { // 3. Under blocks, it's an initial value to be under an assign - // TODO: This is wrong if it's a static variable right? + UINFO(9, "VarInit case3 " << nodep); + nodep->noCReset(true); FileLine* const newfl = new FileLine{fl}; newfl->warnOff(V3ErrorCode::E_CONSTWRITTEN, true); - m_blockp->addStmtsp( - new AstAssign{newfl, new AstVarRef{newfl, nodep, VAccess::WRITE}, - VN_AS(nodep->valuep()->unlinkFrBack(), NodeExpr)}); + AstAssign* const assp + = new AstAssign{newfl, new AstParseRef{newfl, nodep->name()}, createValuep()}; + if (nodep->lifetime().isAutomatic()) { + // May later make: new AstInitialAutomaticStmt{newfl, assp}; + m_blockAddAutomaticStmtp = AstNode::addNext(m_blockAddAutomaticStmtp, assp); + } else { + // May later make: new AstInitialStaticStmt{newfl, assp}; + m_blockAddStaticStmtp = AstNode::addNext(m_blockAddStaticStmtp, assp); + } } else if (m_valueModp) { // 4. Under modules/class, it's the time 0 initialziation value // Making an AstAssign (vs AstAssignW) to a wire is an error, suppress it - FileLine* const newfl = new FileLine{fl}; - newfl->warnOff(V3ErrorCode::PROCASSWIRE, true); - newfl->warnOff(V3ErrorCode::E_CONSTWRITTEN, true); - // Create a ParseRef to the wire. We cannot use the var as it may be deleted if - // it's a port (see t_var_set_link.v) - AstAssign* const assp - = new AstAssign{newfl, new AstParseRef{newfl, nodep->name()}, - VN_AS(nodep->valuep()->unlinkFrBack(), NodeExpr)}; - if (nodep->lifetime().isAutomatic()) { - nodep->addNextHere(new AstInitialAutomatic{newfl, assp}); - } else { - nodep->addNextHere(new AstInitialStatic{newfl, assp}); + UINFO(9, "VarInit case4 " << nodep); + if (nodep->valuep()) { + nodep->noCReset(true); + FileLine* const newfl = new FileLine{fl}; + newfl->warnOff(V3ErrorCode::PROCASSWIRE, true); + newfl->warnOff(V3ErrorCode::E_CONSTWRITTEN, true); + // Create a ParseRef to the wire. We cannot use the var as it may be deleted if + // it's a port (see t_var_set_link.v) + AstAssign* const assp = new AstAssign{ + newfl, new AstParseRef{newfl, nodep->name()}, createValuep()}; + AstNode* newInitp; + // Must make a unique InitialAutomatic/Static for each + // variable or otherwise V3Gate will assume ordering + // within, and not properly optimize. + if (nodep->lifetime().isAutomatic()) { + newInitp = new AstInitialAutomatic{newfl, assp}; + } else { + newInitp = new AstInitialStatic{newfl, assp}; + } + nodep->addNextHere(newInitp); } - } else { + } else if (nodep->valuep()) { nodep->v3fatalSrc("Variable with initializer in unexpected position"); } } @@ -639,20 +691,8 @@ class LinkParseVisitor final : public VNVisitor { // 2. ASTSELBIT(first, var0)) // 3. ASTSELLOOPVARS(first, var0..var1)) // 4. DOT(DOT(first, second), ASTSELBIT(third, var0)) - VL_RESTORER(m_insideLoop); - m_insideLoop = true; - AstNode* bracketp = nodep->arrayp(); - while (AstDot* dotp = VN_CAST(bracketp, Dot)) bracketp = dotp->rhsp(); - if (AstSelBit* const selp = VN_CAST(bracketp, SelBit)) { - // Convert to AstSelLoopVars so V3LinkDot knows what's being defined - AstNode* const newp - = new AstSelLoopVars{selp->fileline(), selp->fromp()->unlinkFrBack(), - selp->bitp()->unlinkFrBackWithNext()}; - selp->replaceWith(newp); - VL_DO_DANGLING2(selp->deleteTree(), selp, bracketp); - } else if (VN_IS(bracketp, SelLoopVars)) { - // Ok - } else { + AstForeachHeader* const headerp = nodep->headerp(); + if (!headerp->elementsp()) { nodep->v3error("Foreach missing bracketed loop variable is no-operation" " (IEEE 1800-2023 12.7.3)"); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); @@ -662,15 +702,11 @@ class LinkParseVisitor final : public VNVisitor { } void visit(AstRepeat* nodep) override { cleanFileline(nodep); - VL_RESTORER(m_insideLoop); - m_insideLoop = true; checkIndent(nodep, nodep->stmtsp()); iterateChildren(nodep); } void visit(AstLoop* nodep) override { cleanFileline(nodep); - VL_RESTORER(m_insideLoop); - m_insideLoop = true; if (VN_IS(nodep->stmtsp(), LoopTest)) { checkIndent(nodep, nodep->stmtsp()->nextp()); } else { @@ -737,6 +773,10 @@ class LinkParseVisitor final : public VNVisitor { nodep->v3warn(E_UNSUPPORTED, "Module cannot be named 'TOP' as conflicts with " "Verilator top-level internals"); } + + VL_RESTORER(m_portDups); + collectPorts(nodep->stmtsp()); + iterateChildren(nodep); if (AstModule* const modp = VN_CAST(nodep, Module)) { modp->hasGenericIface(m_moduleWithGenericIface); @@ -838,14 +878,14 @@ class LinkParseVisitor final : public VNVisitor { iterateChildren(nodep); } void visit(AstNodeBlock* nodep) override { + VL_RESTORER(m_blockAddAutomaticStmtp); + m_blockAddAutomaticStmtp = nullptr; + VL_RESTORER(m_blockAddStaticStmtp); + m_blockAddStaticStmtp = nullptr; { VL_RESTORER(m_blockp); m_blockp = nodep; - // Temporarily unlink the statements so variable initializers can be inserted in order - AstNode* const stmtsp = nodep->stmtsp(); - if (stmtsp) stmtsp->unlinkFrBackWithNext(); iterateAndNextNull(nodep->declsp()); - nodep->addStmtsp(stmtsp); } if (AstBegin* const beginp = VN_CAST(nodep, Begin)) { @@ -853,14 +893,28 @@ class LinkParseVisitor final : public VNVisitor { } cleanFileline(nodep); iterateAndNextNull(nodep->stmtsp()); - if (AstFork* const forkp = VN_CAST(nodep, Fork)) { - iterateAndNextNull(forkp->forksp()); - if (!forkp->parentProcessp() && forkp->joinType().joinNone() && forkp->forksp()) - addForkParentProcess(forkp); + if (AstFork* const forkp = VN_CAST(nodep, Fork)) iterateAndNextNull(forkp->forksp()); + // Add statements created by AstVar vistor; can't do as-go because iteration + // would then get confused, additionally we did already iterate the contents + AstNode* stmtsp = nullptr; + // Move all Vars to front of function + stmtsp = AstNode::addNextNull(stmtsp, getVarsAndUnlink(nodep->stmtsp())); + // Follow vars by m_blockAddp's (if any) + stmtsp = AstNode::addNextNull(stmtsp, getBlockAdds()); + if (stmtsp) { + if (nodep->stmtsp()) { + nodep->stmtsp()->addHereThisAsNext(stmtsp); + } else { + nodep->addStmtsp(stmtsp); + } } } void visit(AstCase* nodep) override { V3Control::applyCase(nodep); + // Check for unsupported case matches (for tagged union) + if (nodep->caseMatches()) { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: case matches (for tagged union)"); + } cleanFileline(nodep); iterateChildren(nodep); } @@ -1018,6 +1072,41 @@ class LinkParseVisitor final : public VNVisitor { iterateChildren(nodep); } + // Tagged union features - flag as unsupported early + void visit(AstTaggedExpr* nodep) override { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: tagged union"); + cleanFileline(nodep); + iterateChildren(nodep); + } + void visit(AstTaggedPattern* nodep) override { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: tagged pattern"); + cleanFileline(nodep); + iterateChildren(nodep); + } + void visit(AstPatternVar* nodep) override { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: pattern variable"); + cleanFileline(nodep); + iterateChildren(nodep); + } + void visit(AstPatternStar* nodep) override { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: pattern wildcard"); + cleanFileline(nodep); + iterateChildren(nodep); + } + void visit(AstMatches* nodep) override { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: matches operator"); + cleanFileline(nodep); + iterateChildren(nodep); + } + void visit(AstBasicDType* nodep) override { + // Check for void type used in tagged unions + if (nodep->keyword() == VBasicDTypeKwd::CVOID) { + nodep->v3warn(E_UNSUPPORTED, "Unsupported: void (for tagged unions)"); + } + cleanFileline(nodep); + iterateChildren(nodep); + } + void visit(AstNode* nodep) override { // Default: Just iterate cleanFileline(nodep); @@ -1026,10 +1115,7 @@ class LinkParseVisitor final : public VNVisitor { public: // CONSTRUCTORS - explicit LinkParseVisitor(AstNetlist* rootp) { - unprotectStdProcessHandle(); - iterate(rootp); - } + explicit LinkParseVisitor(AstNetlist* rootp) { iterate(rootp); } ~LinkParseVisitor() override { V3Stats::addStatSum(V3Stats::STAT_SOURCE_MODULES, m_statModules); } diff --git a/src/V3LinkParse.h b/src/V3LinkParse.h index 9e797d7e8..328272002 100644 --- a/src/V3LinkParse.h +++ b/src/V3LinkParse.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index a3967ccb6..28cff46c6 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -73,6 +73,11 @@ class LinkResolveVisitor final : public VNVisitor { void visit(AstClass* nodep) override { VL_RESTORER(m_classp); m_classp = nodep; + for (AstNode* stmtp = nodep->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + if (AstVar* const varp = VN_CAST(stmtp, Var)) { + if (!varp->isParam()) varp->varType(VVarType::MEMBER); + } + } iterateChildren(nodep); } void visit(AstConstraint* nodep) override { @@ -120,7 +125,6 @@ class LinkResolveVisitor final : public VNVisitor { } void visit(AstVar* nodep) override { iterateChildren(nodep); - if (m_classp && !nodep->isParam()) nodep->varType(VVarType::MEMBER); if (m_ftaskp) nodep->funcLocal(true); if (nodep->isSigModPublic()) { nodep->sigModPublic(false); // We're done with this attribute @@ -174,6 +178,20 @@ class LinkResolveVisitor final : public VNVisitor { } VL_RESTORER(m_ftaskp); m_ftaskp = nodep; + + if (nodep->lifetime().isAutomatic() && nodep->fvarp()) { + // Must clear automatic function output variable on function invocation + AstVar* const fvarp = VN_AS(nodep->fvarp(), Var); + AstNode* const crstp = new AstAssign{ + fvarp->fileline(), new AstVarRef{fvarp->fileline(), fvarp, VAccess::WRITE}, + new AstCReset{fvarp->fileline(), fvarp, false}}; + fvarp->noCReset(true); + if (nodep->stmtsp()) { + nodep->stmtsp()->addHereThisAsNext(crstp); + } else { + nodep->addStmtsp(crstp); + } + } iterateChildren(nodep); if (nodep->dpiExport()) nodep->scopeNamep(new AstScopeName{nodep->fileline(), false}); } @@ -293,6 +311,11 @@ class LinkResolveVisitor final : public VNVisitor { m_modp->modPublic(true); // Need to get to the task... nodep->unlinkFrBack(); VL_DO_DANGLING(pushDeletep(nodep), nodep); + } else if (nodep->pragType() == VPragmaType::VERILATOR_LIB) { + UASSERT_OBJ(m_modp, nodep, "VERILATOR_LIB not under a module"); + m_modp->verilatorLib(true); + nodep->unlinkFrBack(); + VL_DO_DANGLING(pushDeletep(nodep), nodep); } else { iterateChildren(nodep); } diff --git a/src/V3LinkResolve.h b/src/V3LinkResolve.h index 27d628b3c..893aaf770 100644 --- a/src/V3LinkResolve.h +++ b/src/V3LinkResolve.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3List.h b/src/V3List.h index 7182fa93c..bb760693f 100644 --- a/src/V3List.h +++ b/src/V3List.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Localize.cpp b/src/V3Localize.cpp index ad3a96998..edafffdee 100644 --- a/src/V3Localize.cpp +++ b/src/V3Localize.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -69,6 +69,11 @@ class LocalizeVisitor final : public VNVisitor { bool isOptimizable(AstVarScope* nodep) { // Don't want to malloc/free the backing store all the time if (VN_IS(nodep->dtypep(), NBACommitQueueDType)) return false; + // Do not localize strings. They result in unnecessary initialization + // and bloated code size due to destructor calls when unused. + // TODO: Local variables should be pushed into the narrowest scope rather + // than emitted at the top of the function. See discussion in #6969. + if (nodep->dtypep()->skipRefp()->isString()) return false; // Variables used in super constructor call can't be localized, because // in C++ there is no way to declare them before base class constructor call if (nodep->user4()) return false; diff --git a/src/V3Localize.h b/src/V3Localize.h index 53e1a8f3e..4dda2faf1 100644 --- a/src/V3Localize.h +++ b/src/V3Localize.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3MemberMap.h b/src/V3MemberMap.h index 730c145b8..396f78a06 100644 --- a/src/V3MemberMap.h +++ b/src/V3MemberMap.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp index 804b9d8e2..d4d687c69 100644 --- a/src/V3MergeCond.cpp +++ b/src/V3MergeCond.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3MergeCond.h b/src/V3MergeCond.h index 232723646..218a2fbe3 100644 --- a/src/V3MergeCond.h +++ b/src/V3MergeCond.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Mutex.h b/src/V3Mutex.h index a69d9f748..7cab9caa3 100644 --- a/src/V3Mutex.h +++ b/src/V3Mutex.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Name.cpp b/src/V3Name.cpp index 909f5279d..8e763dc32 100644 --- a/src/V3Name.cpp +++ b/src/V3Name.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Name.h b/src/V3Name.h index e89239591..466ce6c4a 100644 --- a/src/V3Name.h +++ b/src/V3Name.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Number.cpp b/src/V3Number.cpp index 1117f1e74..61a8460af 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -116,12 +116,15 @@ V3Number::V3Number(AstNode* nodep, VerilogStringLiteral, const string& str) { } V3Number::V3Number(AstNode* nodep, const AstNodeDType* nodedtypep) { - if (nodedtypep->isString()) { + if (nodedtypep->isCHandle()) { init(nodep); - setString(""); + setNull(); } else if (nodedtypep->isDouble()) { init(nodep, 64); setDouble(0.0); + } else if (nodedtypep->isString()) { + init(nodep); + setString(""); } else { init(nodep, nodedtypep->width(), nodedtypep->widthSized()); } @@ -1529,8 +1532,9 @@ V3Number& V3Number::opRepl(const V3Number& lhs, // i op repl, L(i)*value(rhs) bit return NUM_ASSERT_OP_ARGS1(lhs); NUM_ASSERT_LOGIC_ARGS1(lhs); - if (rhsval > 8192) { - v3warn(WIDTHCONCAT, "More than a 8k bit replication is probably wrong: " << rhsval); + if (v3Global.opt.replicationLimit() && rhsval > (uint32_t)v3Global.opt.replicationLimit()) { + v3warn(WIDTHCONCAT, "Replication of more that --replication-limit " + << v3Global.opt.replicationLimit() << " is suspect: " << rhsval); } setZero(); int obit = 0; diff --git a/src/V3Number.h b/src/V3Number.h index bf3c17f1c..8c84252d1 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -340,6 +340,11 @@ class V3Number final { FileLine* m_fileline = nullptr; // Source location - if no parent node is reasonable // METHODS + void setNull() { + m_data.setLogic(); + m_data.m_isNull = true; + m_data.m_autoExtend = true; + } V3Number& setSingleBits(char value); V3Number& setString(const string& str) { m_data.setString(str); @@ -512,9 +517,7 @@ public: class Null {}; V3Number(AstNode* nodep, Null) { init(nodep); - m_data.setLogic(); - m_data.m_isNull = true; - m_data.m_autoExtend = true; + setNull(); } explicit V3Number(const V3Number* nump, int width = 1) { init(nullptr, width); diff --git a/src/V3OptionParser.cpp b/src/V3OptionParser.cpp index 1ea14e59e..eb9b73d5b 100644 --- a/src/V3OptionParser.cpp +++ b/src/V3OptionParser.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3OptionParser.h b/src/V3OptionParser.h index 85dfee2d9..01d20fdb5 100644 --- a/src/V3OptionParser.h +++ b/src/V3OptionParser.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Options.cpp b/src/V3Options.cpp index ac6a3b7d5..246aee89e 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -948,14 +948,14 @@ void V3Options::notify() VL_MT_DISABLED { if (!outFormatOk() && v3Global.opt.main()) ccSet(); // --main implies --cc if not provided if (!outFormatOk() && !dpiHdrOnly() && !lintOnly() && !preprocOnly() && !serializeOnly()) { v3fatal("verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, " - "--xml-only, --json-only or --E option"); + "--json-only or --E option"); } - if (m_build && (m_gmake || m_cmake || m_makeJson)) { + if (m_build && (m_gmake || m_makeJson)) { cmdfl->v3error("--make cannot be used together with --build. Suggest see manual"); } - // m_build, m_preprocOnly, m_dpiHdrOnly, m_lintOnly, m_jsonOnly and m_xmlOnly are mutually + // m_build, m_preprocOnly, m_dpiHdrOnly, m_lintOnly, and m_jsonOnly are mutually // exclusive std::vector backendFlags; if (m_build) { @@ -967,7 +967,6 @@ void V3Options::notify() VL_MT_DISABLED { if (m_preprocOnly) backendFlags.push_back("-E"); if (m_dpiHdrOnly) backendFlags.push_back("--dpi-hdr-only"); if (m_lintOnly) backendFlags.push_back("--lint-only"); - if (m_xmlOnly) backendFlags.push_back("--xml-only"); if (m_jsonOnly) backendFlags.push_back("--json-only"); if (backendFlags.size() > 1) { std::string backendFlagsString = backendFlags.front(); @@ -983,7 +982,7 @@ void V3Options::notify() VL_MT_DISABLED { } // Make sure at least one make system is enabled - if (!m_gmake && !m_cmake && !m_makeJson) m_gmake = true; + if (!m_gmake && !m_makeJson) m_gmake = true; if (m_hierarchical && (m_hierChild || !m_hierBlocks.empty())) { cmdfl->v3error( @@ -1039,8 +1038,7 @@ void V3Options::notify() VL_MT_DISABLED { && !v3Global.opt.serializeOnly()); } - if (m_timing.isDefault() - && (v3Global.opt.jsonOnly() || v3Global.opt.lintOnly() || v3Global.opt.xmlOnly())) + if (m_timing.isDefault() && (v3Global.opt.jsonOnly() || v3Global.opt.lintOnly())) v3Global.opt.m_timing.setTrueOrFalse(true); if (trace()) { @@ -1162,8 +1160,8 @@ void V3Options::parseOpts(FileLine* fl, int argc, char** argv) VL_MT_DISABLED { // Default certain options and error check // Detailed error, since this is what we often get when run with minimal arguments if (vFiles().empty()) { - v3fatal("verilator: No Input Verilog file specified on command line, " - "see verilator --help for more information\n"); + v3fatal("verilator: No input Verilog file specified on command line, " + "see 'verilator --help' for more information\n"); } // Default prefix to the filename @@ -1466,6 +1464,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, }); DECL_OPTION("-fdfg-pre-inline", FOnOff, &m_fDfgPreInline); DECL_OPTION("-fdfg-post-inline", FOnOff, &m_fDfgPostInline); + DECL_OPTION("-fdfg-push-down-sels", FOnOff, &m_fDfgPushDownSels); DECL_OPTION("-fdfg-scoped", FOnOff, &m_fDfgScoped); DECL_OPTION("-fdfg-synthesize-all", FOnOff, &m_fDfgSynthesizeAll); DECL_OPTION("-fexpand", FOnOff, &m_fExpand); @@ -1585,11 +1584,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, DECL_OPTION("-main", OnOff, &m_main); DECL_OPTION("-main-top-name", Set, &m_mainTopName); DECL_OPTION("-make", CbVal, [this, fl](const char* valp) { - if (!std::strcmp(valp, "cmake")) { - m_cmake = true; - fl->v3warn(DEPRECATED, - "Option '--make cmake' is deprecated, use '--make json' instead"); - } else if (!std::strcmp(valp, "gmake")) { + if (!std::strcmp(valp, "gmake")) { m_gmake = true; } else if (!std::strcmp(valp, "json")) { m_makeJson = true; @@ -1705,6 +1700,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, if (m_reloopLimit < 2) fl->v3error("--reloop-limit must be >= 2: " << valp); }); DECL_OPTION("-report-unoptflat", OnOff, &m_reportUnoptflat); + DECL_OPTION("-replication-limit", CbVal, [this, fl](const char* valp) { + m_replicationLimit = std::atoi(valp); + if (m_replicationLimit < 0) fl->v3error("--replication-limit must be >= 0: " << valp); + }); DECL_OPTION("-rr", CbCall, []() {}); // Processed only in bin/verilator shell DECL_OPTION("-runtime-debug", CbCall, [this, fl]() { decorations(fl, "node"); @@ -1721,6 +1720,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, m_outFormatOk = true; m_systemC = true; }); + DECL_OPTION("-sched-zero-delay", OnOff, &m_schedZeroDelay); DECL_OPTION("-skip-identical", OnOff, &m_skipIdentical); DECL_OPTION("-stats", OnOff, &m_stats); DECL_OPTION("-stats-vars", CbOnOff, [this](bool flag) { @@ -1795,8 +1795,11 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, } }); DECL_OPTION("-timing", OnOff, &m_timing); - DECL_OPTION("-top", Set, &m_topModule); - DECL_OPTION("-top-module", Set, &m_topModule); + DECL_OPTION("-top", CbVal, + [this](const std::string& flag) { m_topModule = AstNode::encodeName(flag); }); + DECL_OPTION("-top-module", CbVal, + [this](const std::string& flag) { m_topModule = AstNode::encodeName(flag); }); + DECL_OPTION("-top-module-encoded", Set, &m_topModule).undocumented(); DECL_OPTION("-trace", OnOff, &m_trace); DECL_OPTION("-trace-saif", CbCall, [this]() { m_traceEnabledSaif = true; }); DECL_OPTION("-trace-coverage", OnOff, &m_traceCoverage); @@ -1839,7 +1842,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, }); DECL_OPTION("-v", CbVal, [this, &optdir](const char* valp) { V3Options::addLibraryFile(parseFileArg(optdir, valp), work()); - }); + }).notForRerun(); DECL_OPTION("-valgrind", CbCall, []() {}); // Processed only in bin/verilator shell DECL_OPTION("-verilate", OnOff, &m_verilate); DECL_OPTION("-verilate-jobs", CbVal, [this, fl](const char* valp) { @@ -1944,17 +1947,6 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, } }); DECL_OPTION("-x-initial-edge", OnOff, &m_xInitialEdge); - DECL_OPTION("-xml-only", CbOnOff, [this, fl](bool flag) { - if (!m_xmlOnly && flag) - fl->v3warn(DEPRECATED, "Option --xml-only is deprecated, move to --json-only"); - m_xmlOnly = flag; - }); - DECL_OPTION("-xml-output", CbVal, [this, fl](const char* valp) { - if (!m_xmlOnly) - fl->v3warn(DEPRECATED, "Option --xml-only is deprecated, move to --json-only"); - m_xmlOutput = valp; - m_xmlOnly = true; - }); DECL_OPTION("-y", CbVal, [this, &optdir](const char* valp) { addIncDirUser(parseFileArg(optdir, string{valp})); diff --git a/src/V3Options.h b/src/V3Options.h index 6e75c373f..08df2599d 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -226,7 +226,6 @@ private: bool m_bboxUnsup = false; // main switch: --bbox-unsup bool m_binary = false; // main switch: --binary bool m_build = false; // main switch: --build - bool m_cmake = false; // main switch: --make cmake bool m_context = true; // main switch: --Wcontext bool m_coverageExpr = false; // main switch: --coverage-expr bool m_coverageLine = false; // main switch: --coverage-block @@ -286,6 +285,7 @@ private: bool m_relativeIncludes = false; // main switch: --relative-includes bool m_reportUnoptflat = false; // main switch: --report-unoptflat bool m_savable = false; // main switch: --savable + VOptionBool m_schedZeroDelay; // main switch: --sched-zero-delay bool m_stdPackage = true; // main switch: --std-package bool m_stdWaiver = true; // main switch: --std-waiver bool m_structsPacked = false; // main switch: --structs-packed @@ -310,7 +310,6 @@ private: bool m_vpi = false; // main switch: --vpi bool m_waiverMultiline = false; // main switch: --waiver-multiline bool m_xInitialEdge = false; // main switch: --x-initial-edge - bool m_xmlOnly = false; // main switch: --xml-only int m_buildJobs = -1; // main switch: --build-jobs, -j int m_coverageExprMax = 32; // main switch: --coverage-expr-max @@ -339,6 +338,7 @@ private: int m_preprocTokenLimit = 40000; // main switch: --preproc-token-limit int m_publicDepth = 0; // main switch: --public-depth int m_reloopLimit = 40; // main switch: --reloop-limit + int m_replicationLimit = 8192; // main switch: --replication-limit VOptionBool m_skipIdentical; // main switch: --skip-identical bool m_stopFail = true; // main switch: --stop-fail int m_threads = 1; // main switch: --threads @@ -380,7 +380,6 @@ private: string m_work = "work"; // main switch: --work {libname} string m_xAssign; // main switch: --x-assign string m_xInitial; // main switch: --x-initial - string m_xmlOutput; // main switch: --xml-output // Language is now held in FileLine, on a per-node basis. However we still // have a concept of the default language at a global level. @@ -400,6 +399,7 @@ private: bool m_fDfgPeephole = true; // main switch: -fno-dfg-peephole bool m_fDfgPreInline; // main switch: -fno-dfg-pre-inline and -fno-dfg bool m_fDfgPostInline; // main switch: -fno-dfg-post-inline and -fno-dfg + bool m_fDfgPushDownSels = true; // main switch: -fno-dfg-push-down-sels bool m_fDfgScoped; // main switch: -fno-dfg-scoped and -fno-dfg bool m_fDfgSynthesizeAll = false; // main switch: -fdfg-synthesize-all bool m_fDeadAssigns; // main switch: -fno-dead-assigns: remove dead assigns @@ -493,6 +493,7 @@ public: bool underlineZero() const { return m_underlineZero; } bool systemC() const VL_MT_SAFE { return m_systemC; } bool savable() const VL_MT_SAFE { return m_savable; } + VOptionBool schedZeroDelay() const { return m_schedZeroDelay; } bool stats() const { return m_stats; } bool statsVars() const { return m_statsVars; } bool stdPackage() const { return m_stdPackage; } @@ -506,7 +507,6 @@ public: bool build() const { return m_build; } string buildDepBin() const { return m_buildDepBin; } void buildDepBin(const string& flag) { m_buildDepBin = flag; } - bool cmake() const { return m_cmake; } bool context() const VL_MT_SAFE { return m_context; } bool coverage() const VL_MT_SAFE { return m_coverageLine || m_coverageToggle || m_coverageExpr || m_coverageUser; @@ -589,8 +589,7 @@ public: bool vpi() const { return m_vpi; } bool waiverMultiline() const { return m_waiverMultiline; } bool xInitialEdge() const { return m_xInitialEdge; } - bool xmlOnly() const { return m_xmlOnly; } - bool serializeOnly() const { return m_xmlOnly || m_jsonOnly; } + bool serializeOnly() const { return m_jsonOnly; } bool topIfacesSupported() const { return lintOnly() && !hierarchical(); } int buildJobs() const VL_MT_SAFE { return m_buildJobs; } @@ -617,6 +616,7 @@ public: int outputGroups() const { return m_outputGroups; } int pinsBv() const VL_MT_SAFE { return m_pinsBv; } int reloopLimit() const { return m_reloopLimit; } + int replicationLimit() const { return m_replicationLimit; } VOptionBool skipIdentical() const { return m_skipIdentical; } bool stopFail() const { return m_stopFail; } int threads() const VL_MT_SAFE { return m_threads; } @@ -673,7 +673,7 @@ public: // Not just called protectKey() to avoid bugs of not using protectKeyDefaulted() bool protectKeyProvided() const { return !m_protectKey.empty(); } string protectKeyDefaulted() VL_MT_SAFE; // Set default key if not set by user - string topModule() const { return m_topModule; } + string topModule() const { return m_topModule; } // As AstNode::encodeName() bool noTraceTop() const { return m_noTraceTop; } string unusedRegexp() const { return m_unusedRegexp; } string waiverOutput() const { return m_waiverOutput; } @@ -681,7 +681,6 @@ public: bool isWaiverOutput() const { return !m_waiverOutput.empty(); } string xAssign() const { return m_xAssign; } string xInitial() const { return m_xInitial; } - string xmlOutput() const { return m_xmlOutput; } const VStringSet& cppFiles() const { return m_cppFiles; } const VStringList& cFlags() const { return m_cFlags; } @@ -717,6 +716,7 @@ public: bool fDfgPeephole() const { return m_fDfgPeephole; } bool fDfgPreInline() const { return m_fDfgPreInline; } bool fDfgPostInline() const { return m_fDfgPostInline; } + bool fDfgPushDownSels() const { return m_fDfgPushDownSels; } bool fDfgScoped() const { return m_fDfgScoped; } bool fDfgSynthesizeAll() const { return m_fDfgSynthesizeAll; } bool fDfgPeepholeEnabled(const std::string& name) const { diff --git a/src/V3Order.cpp b/src/V3Order.cpp index d8c91eeae..54991d0c5 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Order.h b/src/V3Order.h index 2206b5913..7ff61a7b0 100644 --- a/src/V3Order.h +++ b/src/V3Order.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3OrderCFuncEmitter.h b/src/V3OrderCFuncEmitter.h index 103f556b2..e3727fdde 100644 --- a/src/V3OrderCFuncEmitter.h +++ b/src/V3OrderCFuncEmitter.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3OrderGraph.h b/src/V3OrderGraph.h index 0c3b68625..060bbf309 100644 --- a/src/V3OrderGraph.h +++ b/src/V3OrderGraph.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3OrderGraphBuilder.cpp b/src/V3OrderGraphBuilder.cpp index c86df1c0d..1f4936e87 100644 --- a/src/V3OrderGraphBuilder.cpp +++ b/src/V3OrderGraphBuilder.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -214,7 +214,7 @@ class OrderGraphBuilder final : public VNVisitor { // Variable is produced if (gen) { // Update VarUsage - varscp->user2(varscp->user2() | VU_GEN); + varscp->user2Or(VU_GEN); // Add edges for produced variables if (m_inPost) { if (!varscp->varp()->ignorePostWrite()) { @@ -253,7 +253,7 @@ class OrderGraphBuilder final : public VNVisitor { // Variable is consumed if (con) { // Update VarUsage - varscp->user2(varscp->user2() | VU_CON); + varscp->user2Or(VU_CON); // Add edges if (m_inPost) { // Combinational logic diff --git a/src/V3OrderInternal.h b/src/V3OrderInternal.h index 1caa4fc88..86a508204 100644 --- a/src/V3OrderInternal.h +++ b/src/V3OrderInternal.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3OrderMoveGraph.cpp b/src/V3OrderMoveGraph.cpp index 1e18a6a85..3c19c8382 100644 --- a/src/V3OrderMoveGraph.cpp +++ b/src/V3OrderMoveGraph.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3OrderMoveGraph.h b/src/V3OrderMoveGraph.h index 7560a669e..80432c55b 100644 --- a/src/V3OrderMoveGraph.h +++ b/src/V3OrderMoveGraph.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3OrderParallel.cpp b/src/V3OrderParallel.cpp index 0fb78b535..23e64a842 100644 --- a/src/V3OrderParallel.cpp +++ b/src/V3OrderParallel.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3OrderProcessDomains.cpp b/src/V3OrderProcessDomains.cpp index d59712afa..951f5214a 100644 --- a/src/V3OrderProcessDomains.cpp +++ b/src/V3OrderProcessDomains.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3OrderSerial.cpp b/src/V3OrderSerial.cpp index d262c0572..abdcd97be 100644 --- a/src/V3OrderSerial.cpp +++ b/src/V3OrderSerial.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Os.cpp b/src/V3Os.cpp index 96224384a..a34a7aec2 100644 --- a/src/V3Os.cpp +++ b/src/V3Os.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Os.h b/src/V3Os.h index 46b96523d..72d36b7d9 100644 --- a/src/V3Os.h +++ b/src/V3Os.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PairingHeap.h b/src/V3PairingHeap.h index d9f3a633e..4e8daf7a4 100644 --- a/src/V3PairingHeap.h +++ b/src/V3PairingHeap.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Param.cpp b/src/V3Param.cpp index dc48020e4..aeddbbeb4 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -616,6 +616,108 @@ class ParamProcessor final { if (nodep->op4p()) replaceRefsRecurse(nodep->op4p(), oldClassp, newClassp); if (nodep->nextp()) replaceRefsRecurse(nodep->nextp(), oldClassp, newClassp); } + + // Helper visitor to update VarXRefs to use variables from specialized interfaces. + // When a module with interface ports is cloned and the port's interface is remapped + // to a specialized version, VarXRefs that access members of the old interface need + // to be updated to reference the corresponding members in the new interface. + class VarXRefRelinkVisitor final : public VNVisitor { + AstNodeModule* m_modp; // The cloned module we're updating + std::unordered_map m_varModuleMap; // Cache var->module lookups + + public: + explicit VarXRefRelinkVisitor(AstNodeModule* newModp) + : m_modp{newModp} { + iterate(newModp); + } + + private: + // Find which module a variable belongs to, using cache to avoid repeated backp() walks + AstNodeModule* findVarModule(AstVar* varp) { + const auto it = m_varModuleMap.find(varp); + if (it != m_varModuleMap.end()) return it->second; + AstNodeModule* varModp = nullptr; + for (AstNode* np = varp; np; np = np->backp()) { + if (AstNodeModule* const modp = VN_CAST(np, NodeModule)) { + varModp = modp; + break; + } + } + m_varModuleMap[varp] = varModp; + return varModp; + } + + void visit(AstVarXRef* nodep) override { + AstVar* const varp = nodep->varp(); + if (!varp) { + iterateChildren(nodep); + return; + } + + // Get the dotted prefix (port name) from the VarXRef + // dotted() format: "portname" or "portname.subpath" or empty + const string& dotted = nodep->dotted(); + if (dotted.empty()) { + iterateChildren(nodep); + return; + } + + const size_t dotPos = dotted.find('.'); + const string portName = (dotPos == string::npos) ? dotted : dotted.substr(0, dotPos); + if (portName.empty()) { + iterateChildren(nodep); + return; + } + + // Find the interface port variable in the cloned module + AstVar* portVarp = nullptr; + for (AstNode* stmtp = m_modp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + if (AstVar* const varChkp = VN_CAST(stmtp, Var)) { + if (varChkp->name() == portName && varChkp->isIfaceRef()) { + portVarp = varChkp; + break; + } + } + } + if (!portVarp) { + iterateChildren(nodep); + return; + } + + // Get the interface module from the port's dtype + AstIfaceRefDType* const irefp = VN_CAST(portVarp->subDTypep(), IfaceRefDType); + if (!irefp) { + iterateChildren(nodep); + return; + } + + AstNodeModule* const newIfacep = irefp->ifaceViaCellp(); + if (!newIfacep) { + iterateChildren(nodep); + return; + } + + // Find which module the variable currently belongs to (cached) + AstNodeModule* const varModp = findVarModule(varp); + + // If variable is in a different module than the port's interface, remap it + if (varModp && varModp != newIfacep) { + for (AstNode* stmtp = newIfacep->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + if (AstVar* const newVarp = VN_CAST(stmtp, Var)) { + if (newVarp->name() == varp->name()) { + UINFO(9, "VarXRef relink " << varp->name() << " in " << varModp->name() + << " -> " << newIfacep->name() << endl); + nodep->varp(newVarp); + break; + } + } + } + } + iterateChildren(nodep); + } + void visit(AstNode* nodep) override { iterateChildren(nodep); } + }; + // Return true on success, false on error bool deepCloneModule(AstNodeModule* srcModp, AstNode* ifErrorp, AstPin* paramsp, const string& newname, const IfaceRefRefs& ifaceRefRefs) { @@ -737,7 +839,25 @@ class ParamProcessor final { // thus we need to stash this info. collectPins(clonemapp, newModp, srcModp->user3p()); // Relink parameter vars to the new module - relinkPins(clonemapp, paramsp); + // For interface ports (e.g., l3_if #(W, L0A_W) l3), the parameter pins may + // reference variables from the enclosing module rather than from the interface + // being cloned. In such cases, use relinkPinsByName to match by variable name. + // Check if any parameter pins reference variables outside the cloned interface. + // This is O(n) but acceptable since parameter pin lists are typically small (<10 pins). + bool needRelinkByName = false; + if (paramsp) { + for (AstPin* pinp = paramsp; pinp; pinp = VN_AS(pinp->nextp(), Pin)) { + if (pinp->modVarp() && clonemapp->find(pinp->modVarp()) == clonemapp->end()) { + needRelinkByName = true; + break; + } + } + } + if (needRelinkByName) { + relinkPinsByName(paramsp, newModp); + } else { + relinkPins(clonemapp, paramsp); + } // Fix any interface references for (auto it = ifaceRefRefs.cbegin(); it != ifaceRefRefs.cend(); ++it) { @@ -751,6 +871,12 @@ class ParamProcessor final { cloneIrefp->ifacep(pinIrefp->ifaceViaCellp()); UINFO(8, " IfaceNew " << cloneIrefp); } + + // Fix VarXRefs that reference variables in old interfaces. + // Now that interface port dtypes have been updated above, we can use them + // to find the correct interface for each VarXRef. + if (!ifaceRefRefs.empty()) { VarXRefRelinkVisitor{newModp}; } + // Assign parameters to the constants specified // DOES clone() so must be finished with module clonep() before here for (AstPin* pinp = paramsp; pinp; pinp = VN_AS(pinp->nextp(), Pin)) { @@ -810,17 +936,32 @@ class ParamProcessor final { } } - // Helper to resolve DOT to RefDType for class type references + // Helper to resolve DOT to RefDType for class type references. + // If the class is parameterized and not yet specialized, specialize it first. + // This handles cases like: iface #(param_class#(value)::typedef_name) void resolveDotToTypedef(AstNode* exprp) { AstDot* const dotp = VN_CAST(exprp, Dot); if (!dotp) return; - const AstClassOrPackageRef* const classRefp = VN_CAST(dotp->lhsp(), ClassOrPackageRef); + AstClassOrPackageRef* const classRefp = VN_CAST(dotp->lhsp(), ClassOrPackageRef); if (!classRefp) return; - const AstClass* const lhsClassp = VN_CAST(classRefp->classOrPackageSkipp(), Class); - if (!lhsClassp) return; AstParseRef* const parseRefp = VN_CAST(dotp->rhsp(), ParseRef); if (!parseRefp) return; + const AstClass* lhsClassp = VN_CAST(classRefp->classOrPackageSkipp(), Class); + if (classRefp->paramsp()) { + // ClassOrPackageRef has parameters - may need to specialize the class + AstClass* const srcClassp = VN_CAST(classRefp->classOrPackageNodep(), Class); + if (srcClassp && srcClassp->hasGParam()) { + // Specialize if the reference still points to the generic class + if (lhsClassp == srcClassp || !lhsClassp) { + UINFO(9, "resolveDotToTypedef: specializing " << srcClassp->name() << endl); + classRefDeparam(classRefp, srcClassp); + lhsClassp = VN_CAST(classRefp->classOrPackageSkipp(), Class); + } + } + } + if (!lhsClassp) return; + AstTypedef* const tdefp = VN_CAST(m_memberMap.findMember(lhsClassp, parseRefp->name()), Typedef); if (tdefp) { @@ -946,8 +1087,9 @@ class ParamProcessor final { } AstIfaceRefDType* pinIrefp = nullptr; const AstNode* const exprp = pinp->exprp(); - const AstVar* const varp - = (exprp && VN_IS(exprp, VarRef)) ? VN_AS(exprp, VarRef)->varp() : nullptr; + const AstVar* const varp = (exprp && VN_IS(exprp, NodeVarRef)) + ? VN_AS(exprp, NodeVarRef)->varp() + : nullptr; if (varp && varp->subDTypep() && VN_IS(varp->subDTypep(), IfaceRefDType)) { pinIrefp = VN_AS(varp->subDTypep(), IfaceRefDType); } else if (varp && varp->subDTypep() && arraySubDTypep(varp->subDTypep()) @@ -963,6 +1105,13 @@ class ParamProcessor final { pinIrefp = VN_AS(arraySubDTypep(VN_AS(exprp->op1p(), VarRef)->varp()->subDTypep()), IfaceRefDType); + } else if (VN_IS(exprp, CellArrayRef)) { + // Interface array element selection (e.g., l1(l2.l1[0]) for nested iface + // array) The CellArrayRef is not yet fully linked to an interface type. Skip + // interface cleanup for this pin - V3LinkDot will resolve this later. Just + // continue to the next pin without error. + UINFO(9, "Skipping interface cleanup for CellArrayRef pin: " << pinp << endl); + continue; } UINFO(9, " portIfaceRef " << portIrefp); @@ -1169,9 +1318,11 @@ class ParamProcessor final { cellInterfaceCleanup(pinsp, srcModp, longname /*ref*/, any_overrides /*ref*/, ifaceRefRefs /*ref*/); - // Default params are resolved as overrides + // Classes/modules with type parameters need specialization even when types match defaults. + // This is required for UVM parameterized classes. However, interfaces should NOT + // be specialized when type params match defaults (needed for nested interface ports). bool defaultsResolved = false; - if (!any_overrides) { + if (!any_overrides && !VN_IS(srcModp, Iface)) { for (AstPin* pinp = paramsp; pinp; pinp = VN_AS(pinp->nextp(), Pin)) { if (pinp->modPTypep()) { any_overrides = true; @@ -1223,6 +1374,7 @@ class ParamProcessor final { << " cellName=" << nodep->name() << " cloned=" << cloned); + // Link source class to its specialized version for later relinking of method references if (defaultsResolved) srcModp->user4p(newModp); for (auto* stmtp = newModp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { @@ -1318,13 +1470,13 @@ public: srcModp->someInstanceName(instanceName); AstNodeModule* newModp = nullptr; - if (AstCell* cellp = VN_CAST(nodep, Cell)) { + if (AstCell* const cellp = VN_CAST(nodep, Cell)) { newModp = cellDeparam(cellp, srcModp); - } else if (AstIfaceRefDType* ifaceRefDTypep = VN_CAST(nodep, IfaceRefDType)) { + } else if (AstIfaceRefDType* const ifaceRefDTypep = VN_CAST(nodep, IfaceRefDType)) { newModp = ifaceRefDeparam(ifaceRefDTypep, srcModp); - } else if (AstClassRefDType* classRefp = VN_CAST(nodep, ClassRefDType)) { + } else if (AstClassRefDType* const classRefp = VN_CAST(nodep, ClassRefDType)) { newModp = classRefDeparam(classRefp, srcModp); - } else if (AstClassOrPackageRef* classRefp = VN_CAST(nodep, ClassOrPackageRef)) { + } else if (AstClassOrPackageRef* const classRefp = VN_CAST(nodep, ClassOrPackageRef)) { newModp = classRefDeparam(classRefp, srcModp); } else { nodep->v3fatalSrc("Expected module parameterization"); @@ -1554,6 +1706,25 @@ class ParamVisitor final : public VNVisitor { return false; } + // Recursively specialize nested interface cells within a specialized interface. + // This handles parameter passthrough for nested interface hierarchies. + void specializeNestedIfaceCells(AstNodeModule* ifaceModp) { + for (AstNode* stmtp = ifaceModp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + AstCell* const nestedCellp = VN_CAST(stmtp, Cell); + if (!nestedCellp) continue; + if (!VN_IS(nestedCellp->modp(), Iface)) continue; + if (!nestedCellp->paramsp()) continue; + if (cellParamsReferenceIfacePorts(nestedCellp)) continue; + + AstNodeModule* const nestedSrcModp = nestedCellp->modp(); + if (AstNodeModule* const nestedNewModp = m_processor.nodeDeparam( + nestedCellp, nestedSrcModp, ifaceModp, ifaceModp->someInstanceName())) { + // Recursively process nested interfaces within this nested interface + if (nestedNewModp != nestedSrcModp) specializeNestedIfaceCells(nestedNewModp); + } + } + } + // A generic visitor for cells and class refs void visitCellOrClassRef(AstNode* nodep, bool isIface) { // Must do ifaces first, so push to list and do in proper order @@ -1566,7 +1737,13 @@ class ParamVisitor final : public VNVisitor { AstCell* const cellp = VN_CAST(nodep, Cell); if (!cellParamsReferenceIfacePorts(cellp)) { AstNodeModule* const srcModp = cellp->modp(); - m_processor.nodeDeparam(cellp, srcModp, m_modp, m_modp->someInstanceName()); + if (AstNodeModule* const newModp = m_processor.nodeDeparam( + cellp, srcModp, m_modp, m_modp->someInstanceName())) { + // For specialized interfaces, recursively process nested interface cells. + // This ensures nested interfaces are already specialized when modules + // using the interface are processed (parameter passthrough fix). + if (newModp != srcModp) specializeNestedIfaceCells(newModp); + } } } @@ -1793,13 +1970,25 @@ class ParamVisitor final : public VNVisitor { V3Const::constifyParamsEdit(nodep->selp()); if (const AstConst* const constp = VN_CAST(nodep->selp(), Const)) { const string index = AstNode::encodeNumber(constp->toSInt()); - const string replacestr = nodep->name() + "__BRA__??__KET__"; + // For nested interface array ports, the node name may have a __Viftop suffix + // that doesn't exist in the original unlinked text. Try without the suffix. + const string viftopSuffix = "__Viftop"; + const string baseName + = VString::endsWith(nodep->name(), viftopSuffix) + ? nodep->name().substr(0, nodep->name().size() - viftopSuffix.size()) + : nodep->name(); + const string replacestr = baseName + "__BRA__??__KET__"; const size_t pos = m_unlinkedTxt.find(replacestr); - UASSERT_OBJ(pos != string::npos, nodep, - "Could not find array index in unlinked text: '" - << m_unlinkedTxt << "' for node: " << nodep); + // For interface port array element selections (e.g., l1(l2.l1[0])), + // the AstCellArrayRef may be visited outside of an AstUnlinkedRef context. + // In such cases, m_unlinkedTxt won't contain the expected pattern. + // Simply skip the replacement - the cell array ref will be resolved later. + if (pos == string::npos) { + UINFO(9, "Skipping unlinked text replacement for " << nodep << endl); + return; + } m_unlinkedTxt.replace(pos, replacestr.length(), - nodep->name() + "__BRA__" + index + "__KET__"); + baseName + "__BRA__" + index + "__KET__"); } else { nodep->v3error("Could not expand constant selection inside dotted reference: " << nodep->selp()->prettyNameQ()); @@ -2025,7 +2214,7 @@ public: netlistp->foreach([](AstNodeFTaskRef* ftaskrefp) { AstNodeFTask* ftaskp = ftaskrefp->taskp(); if (!ftaskp || !ftaskp->classMethod()) return; - string funcName = ftaskp->name(); + const string funcName = ftaskp->name(); for (AstNode* backp = ftaskrefp->backp(); backp; backp = backp->backp()) { if (VN_IS(backp, Class)) { if (backp == ftaskrefp->classOrPackagep()) @@ -2042,7 +2231,7 @@ public: } UASSERT_OBJ(classp, ftaskrefp, "Class method has no class above it"); if (classp->user3p()) return; // will not get removed, no need to relink - AstClass* parametrizedClassp = VN_CAST(classp->user4p(), Class); + AstClass* const parametrizedClassp = VN_CAST(classp->user4p(), Class); if (!parametrizedClassp) return; AstNodeFTask* newFuncp = nullptr; parametrizedClassp->exists([&newFuncp, funcName](AstNodeFTask* ftaskp) { diff --git a/src/V3Param.h b/src/V3Param.h index d09c9e805..37db5d3e0 100644 --- a/src/V3Param.h +++ b/src/V3Param.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Parse.h b/src/V3Parse.h index cd3df5cdb..0ba12d6de 100644 --- a/src/V3Parse.h +++ b/src/V3Parse.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp index 040c920a5..fdc0e218b 100644 --- a/src/V3ParseGrammar.cpp +++ b/src/V3ParseGrammar.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ParseGrammar.h b/src/V3ParseGrammar.h index 640c70c69..373402133 100644 --- a/src/V3ParseGrammar.h +++ b/src/V3ParseGrammar.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -310,7 +310,7 @@ public: if (nextp) nextp->unlinkFrBackWithNext(); if (itemsp && skewp) skewp = skewp->cloneTree(false); AstClockingItem* itemp = new AstClockingItem{flp, direction, skewp, nodep}; - itemsp = itemsp ? itemsp->addNext(itemp) : itemp; + itemsp = AstNode::addNextNull(itemsp, itemp); } return itemsp; } @@ -364,12 +364,4 @@ public: } return resp; } - - // Wrap fork statements in AstBegin, ensure fork...join_none have process - static AstNodeStmt* wrapFork(V3ParseImp* parsep, AstFork* forkp, AstNodeStmt* stmtsp) { - if (forkp->joinType() == VJoinType::JOIN_NONE && stmtsp) - parsep->importIfInStd(forkp->fileline(), "process", true); - forkp->addForksp(wrapInBegin(stmtsp)); - return forkp; - } }; diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp index fde05d21c..603515c37 100644 --- a/src/V3ParseImp.cpp +++ b/src/V3ParseImp.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -610,6 +610,33 @@ size_t V3ParseImp::tokenPipeScanEqNew(size_t depth) { return depth; } +bool V3ParseImp::tokenPipeScanTaggedFollowsPrimary(size_t depth) { + // Check if token at depth is a primary-starting token + // Used to disambiguate tagged union expressions + // Returns true if the token starts a primary expression (IEEE A.8.4) + // Note: '.' and '.*' are pattern-specific, NOT primaries + const int tok = tokenPeekp(depth)->token; + if (tok == '(') return true; // Parenthesized expression + if (tok == '{') return true; // Concatenation + if (tok == yP_TICKBRA) return true; // Assignment pattern '{ + if (tok == yaINTNUM) return true; // Integer literal + if (tok == yaFLOATNUM) return true; // Float literal + if (tok == yaTIMENUM) return true; // Time literal + if (tok == yaSTRING) return true; // String literal + if (tok == yNULL) return true; // null + if (tok == yTHIS) return true; // this + if (tok == '$') return true; // $ + if (tok == yaID__LEX) return true; // Identifier (raw) + if (tok == yaID__ETC) return true; // Identifier + if (tok == yaID__CC) return true; // Identifier with :: + if (tok == yaID__aTYPE) return true; // Type identifier + if (tok == yaID__aINST) return true; // Instance identifier + if (tok == yTAGGED__LEX) return true; // Nested tagged (raw) + if (tok == yTAGGED) return true; // Nested tagged + if (tok == yTAGGED__NONPRIMARY) return true; // Nested tagged (no primary) + return false; +} + int V3ParseImp::tokenPipelineId(int token) { const V3ParseBisonYYSType* nexttokp = tokenPeekp(0); // First char after yaID const int nexttok = nexttokp->token; @@ -644,6 +671,7 @@ void V3ParseImp::tokenPipeline() { || token == yLOCAL__LEX // || token == yNEW__LEX // || token == ySTATIC__LEX // + || token == yTAGGED__LEX // || token == yTYPE__LEX // || token == yVIRTUAL__LEX // || token == yWITH__LEX // @@ -726,6 +754,22 @@ void V3ParseImp::tokenPipeline() { } else { token = yVIRTUAL__ETC; } + } else if (token == yTAGGED__LEX) { + // Look past 'tagged id' to see if primary follows + // Check for all ID token types (both raw and processed forms) + if (nexttok == yaID__LEX || nexttok == yaID__ETC || nexttok == yaID__aTYPE + || nexttok == yaID__aINST) { + VL_RESTORER(yylval); // Remember value, as about to read ahead + // Check token after the identifier + if (tokenPipeScanTaggedFollowsPrimary(1)) { + token = yTAGGED; // Has value expression following + } else { + token = yTAGGED__NONPRIMARY; // No primary follows + } + } else { + // No identifier follows, not a tagged expression (e.g., 'union tagged {') + token = yTAGGED; + } } else if (token == yWITH__LEX) { if (nexttok == '(') { VL_RESTORER(yylval); // Remember value, as about to read ahead diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h index 07e87fe25..636ea0ccf 100644 --- a/src/V3ParseImp.h +++ b/src/V3ParseImp.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2009-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -39,6 +39,8 @@ class V3Lexer; enum V3UniqState : uint8_t { uniq_NONE, uniq_UNIQUE, uniq_UNIQUE0, uniq_PRIORITY }; +enum V3TaggedState : uint8_t { tagged_NONE, tagged_SOFT, tagged_TAGGED }; + enum V3ImportProperty : uint8_t { iprop_NONE, iprop_CONTEXT, iprop_PURE }; //============================================================================ @@ -119,6 +121,7 @@ struct V3ParseBisonYYSType final { bool cbool; VMemberQualifiers qualifiers; V3UniqState uniqstate; + V3TaggedState taggedstate; V3ImportProperty iprop; VSigning::en signstate; V3ErrorCode::en errcodeen; @@ -322,6 +325,7 @@ private: size_t tokenPipeScanParam(size_t depth, bool forInst) VL_MT_DISABLED; size_t tokenPipeScanParens(size_t depth) VL_MT_DISABLED; size_t tokenPipeScanEqNew(size_t depth) VL_MT_DISABLED; + bool tokenPipeScanTaggedFollowsPrimary(size_t depth) VL_MT_DISABLED; const V3ParseBisonYYSType* tokenPeekp(size_t depth) VL_MT_DISABLED; void preprocDumps(std::ostream& os, bool forInputs) VL_MT_DISABLED; }; diff --git a/src/V3ParseLex.cpp b/src/V3ParseLex.cpp index 3b838a081..a655dd294 100644 --- a/src/V3ParseLex.cpp +++ b/src/V3ParseLex.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PchAstMT.h b/src/V3PchAstMT.h index 2dad5d679..34f862088 100644 --- a/src/V3PchAstMT.h +++ b/src/V3PchAstMT.h @@ -2,10 +2,10 @@ //************************************************************************* // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PchAstNoMT.h b/src/V3PchAstNoMT.h index 03307d9e0..e778dab5d 100644 --- a/src/V3PchAstNoMT.h +++ b/src/V3PchAstNoMT.h @@ -2,10 +2,10 @@ //************************************************************************* // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PreExpr.h b/src/V3PreExpr.h index e6210a88a..c7bb334d7 100644 --- a/src/V3PreExpr.h +++ b/src/V3PreExpr.h @@ -6,11 +6,11 @@ // //************************************************************************* // -// Copyright 2000-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only LOR Artistic-2.0 +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2000-2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PreLex.h b/src/V3PreLex.h index 04b75941c..e7fcaebcd 100644 --- a/src/V3PreLex.h +++ b/src/V3PreLex.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2000-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2000-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PreLex.l b/src/V3PreLex.l index bea1f9efd..db71ddb96 100644 --- a/src/V3PreLex.l +++ b/src/V3PreLex.l @@ -5,10 +5,10 @@ * ************************************************************************** * - * Copyright 2003-2026 by Wilson Snyder. This program is free software; you - * can redistribute it and/or modify it under the terms of either the - * GNU Lesser General Public License Version 3 or the Perl Artistic License - * Version 2.0. + * This program is free software; you can redistribute it and/or modify it + * under the terms of either the GNU Lesser General Public License Version 3 + * or the Perl Artistic License Version 2.0. + * SPDX-FileCopyrightText: 2003-2026 Wilson Snyder * SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 * ************************************************************************** diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index ade27aa84..85a9d7b83 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2000-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2000-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -481,17 +481,21 @@ void V3PreProcImp::comment(const string& text) { if ((cp[0] == 'v' || cp[0] == 'V') && VString::startsWith(cp + 1, "erilator")) { cp += std::strlen("verilator"); if (*cp == '_') { - fileline()->v3error("Extra underscore in meta-comment;" - " use /*verilator {...}*/ not /*verilator_{...}*/"); + V3Control::applyIgnores(fileline()); + fileline()->v3warn(BADVLTPRAGMA, "Extra underscore in meta-comment, ignoring comment;" + " use /*verilator {...}*/ not /*verilator_{...}*/"); + return; } vlcomment = true; } else if (VString::startsWith(cp, "synopsys")) { cp += std::strlen("synopsys"); - synth = true; if (*cp == '_') { - fileline()->v3error("Extra underscore in meta-comment;" - " use /*synopsys {...}*/ not /*synopsys_{...}*/"); + V3Control::applyIgnores(fileline()); + fileline()->v3warn(BADVLTPRAGMA, "Extra underscore in meta-comment, ignoring comment;" + " use /*synopsys {...}*/ not /*synopsys_{...}*/"); + return; } + synth = true; } else if (VString::startsWith(cp, "cadence")) { cp += std::strlen("cadence"); synth = true; @@ -505,8 +509,6 @@ void V3PreProcImp::comment(const string& text) { return; } - if (!vlcomment && !synth) return; // Short-circuit - while (std::isspace(*cp)) ++cp; string cmd = commentCleanup(string{cp}); // cmd now is comment without extra spaces and "verilator" prefix diff --git a/src/V3PreProc.h b/src/V3PreProc.h index 42b85c732..618bc1f58 100644 --- a/src/V3PreProc.h +++ b/src/V3PreProc.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2000-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2000-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PreShell.cpp b/src/V3PreShell.cpp index 12162f46a..b0698a21c 100644 --- a/src/V3PreShell.cpp +++ b/src/V3PreShell.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PreShell.h b/src/V3PreShell.h index 1fa489b6a..73c79b013 100644 --- a/src/V3PreShell.h +++ b/src/V3PreShell.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp index aed8ef36b..6aaf86c4f 100644 --- a/src/V3Premit.cpp +++ b/src/V3Premit.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Premit.h b/src/V3Premit.h index 7b4da0fb0..fa55117fc 100644 --- a/src/V3Premit.h +++ b/src/V3Premit.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp index 9af5f5fbe..e73b34bf2 100644 --- a/src/V3ProtectLib.cpp +++ b/src/V3ProtectLib.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -102,6 +102,8 @@ class ProtectVisitor final : public VNVisitor { txtp->add("\n`ifdef VERILATOR\n"); txtp->add("`verilator_config\n"); + txtp->add("verilator_lib -module \"" + m_libName + "\"\n"); + txtp->add("profile_data -hier-dpi \"" + m_libName + "_protectlib_combo_update\" -cost 64'd" + std::to_string(v3Global.currentHierBlockCost()) + "\n"); txtp->add("profile_data -hier-dpi \"" + m_libName + "_protectlib_seq_update\" -cost 64'd" diff --git a/src/V3ProtectLib.h b/src/V3ProtectLib.h index 24bc0b479..ce34dc160 100644 --- a/src/V3ProtectLib.h +++ b/src/V3ProtectLib.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3RandSequence.cpp b/src/V3RandSequence.cpp index f25554183..8ee8a2861 100644 --- a/src/V3RandSequence.cpp +++ b/src/V3RandSequence.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -91,7 +91,7 @@ class RandSequenceVisitor final : public VNVisitor { void findLocalizes(AstRandSequence* nodep) { std::set localVars; nodep->foreach([&](AstNode* const nodep) { - if (AstVarRef* const anodep = VN_CAST(nodep, VarRef)) { + if (const AstVarRef* const anodep = VN_CAST(nodep, VarRef)) { m_localizes.emplace(anodep->varp()); } else if (AstVar* const anodep = VN_CAST(nodep, Var)) { localVars.emplace(anodep); @@ -116,7 +116,7 @@ class RandSequenceVisitor final : public VNVisitor { new AstConst{fl, AstConst::BitFalse{}}}); // Also add arguments as next's - for (auto& itr : m_localizeNames) { + for (const auto& itr : m_localizeNames) { const AstVar* const lvarp = itr.second; AstVar* const iovarp = new AstVar{fl, VVarType::PORT, "__Vrsarg_" + lvarp->name(), lvarp}; @@ -154,7 +154,7 @@ class RandSequenceVisitor final : public VNVisitor { FileLine* const fl = nodep->fileline(); AstArg* const argsp = new AstArg{fl, breakVarp->name(), new AstVarRef{fl, breakVarp, VAccess::WRITE}}; - for (auto& itr : m_localizeNames) { + for (const auto& itr : m_localizeNames) { const AstVar* const lvarp = itr.second; AstVar* const iovarp = m_localizeRemaps[lvarp]; UASSERT_OBJ(iovarp, nodep, "No new port variable for local variable" << lvarp); @@ -188,7 +188,7 @@ class RandSequenceVisitor final : public VNVisitor { for (AstRSProdItem* proditemp = VN_AS(prodlistp->prodsp(), RSProdItem); proditemp; proditemp = VN_AS(proditemp->nextp(), RSProdItem)) { lists.push_back(proditemp); - AstRSProd* const subProdp = proditemp->prodp(); + const AstRSProd* const subProdp = proditemp->prodp(); if (!subProdp) continue; if (!subProdp->rulesp()) continue; if (!subProdp->rulesp()->prodlistsp()) continue; @@ -202,7 +202,8 @@ class RandSequenceVisitor final : public VNVisitor { UINFO(9, "RandJoin productions called:"); for (AstRSProdItem* proditemp : lists) { UINFO(9, " list " << proditemp); - for (AstNodeStmt* prodp : listStmts[proditemp]) UINFO(9, " calls " << prodp); + for (const AstNodeStmt* prodip : listStmts[proditemp]) + UINFO(9, " calls " << prodip); } // Need to clone all nodes used @@ -353,12 +354,12 @@ class RandSequenceVisitor final : public VNVisitor { // "case 2 / * N(a) * /: {statement}; break;" // "case 1 / * N(a) - 1 * /: {statement}; break;" uint32_t j = static_cast(listStmts[proditemp].size()); - for (AstNodeStmt* prodp : listStmts[proditemp]) { + for (AstNodeStmt* iprodp : listStmts[proditemp]) { jIfp->addThensp(new AstIf{ fl, new AstEq{fl, new AstConst{fl, AstConst::WidthedValue{}, 32, j}, new AstVarRef{fl, nleftVarps[i], VAccess::READ}}, - prodp->cloneTree(false)}); + iprodp->cloneTree(false)}); --j; } @@ -431,7 +432,7 @@ class RandSequenceVisitor final : public VNVisitor { UINFOTREE(9, nodep, "RS Tree pre-it", "-"); std::unordered_set prodHasRandJoin; for (AstRSProd* prodp = nodep->prodsp(); prodp; prodp = VN_AS(prodp->nextp(), RSProd)) { - prodp->foreach([&](AstRSProdList* const prodlistp) { + prodp->foreach([&](const AstRSProdList* const prodlistp) { if (prodlistp->randJoin()) prodHasRandJoin.emplace(prodp); }); } @@ -501,7 +502,7 @@ class RandSequenceVisitor final : public VNVisitor { iterateAndNextNull(itemsp); } else if (!nodep->rulesp()->nextp()) { // Single rule/list, can just do it // RSPROD(RSRULE(weight, stmt)) -> IF(weight != 0, stmt) - AstRSRule* const rulep = nodep->rulesp(); + const AstRSRule* const rulep = nodep->rulesp(); AstNode* itemsp = nullptr; if (rulep->weightStmtsp()) itemsp = rulep->weightStmtsp()->unlinkFrBackWithNext(); if (rulep->prodlistsp()) diff --git a/src/V3RandSequence.h b/src/V3RandSequence.h index 13c3f65f7..ab9bafcb6 100644 --- a/src/V3RandSequence.h +++ b/src/V3RandSequence.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index 24dd90822..76f359bf1 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -40,6 +40,7 @@ #include "V3FileLine.h" #include "V3Global.h" #include "V3MemberMap.h" +#include "V3Task.h" #include "V3UniqueNames.h" #include @@ -148,7 +149,6 @@ class RandomizeMarkVisitor final : public VNVisitor { bool m_inStdWith = false; // True when inside a 'with {}' clause std::set m_staticRefs; // References to static variables under `with` clauses AstWith* m_withp = nullptr; // Current 'with' constraint node - std::unordered_set m_processedVars; // Track by variable instance, not class // METHODS // Mark all rand variables in IS_RANDOMIZED_GLOBAL classes as globalConstrained @@ -166,17 +166,26 @@ class RandomizeMarkVisitor final : public VNVisitor { bool isVarInStdRandomizeArgs(const AstVar* varp) const { if (!m_inStdWith || !m_stdRandCallp) return false; - for (AstNode* pinp = m_stdRandCallp->pinsp(); pinp; pinp = pinp->nextp()) { - if (VN_IS(pinp, With)) continue; - const AstArg* const argp = VN_CAST(pinp, Arg); - if (!argp) continue; - const AstNodeExpr* const exprp = argp->exprp(); - if (const AstNodeVarRef* const varrefp = VN_CAST(exprp, NodeVarRef)) { - if (varrefp->varp() == varp) return true; - } else if (const AstMemberSel* const memberselp = VN_CAST(exprp, MemberSel)) { - if (memberselp->varp() == varp) return true; - } else if (const AstArraySel* const arrselp = VN_CAST(exprp, ArraySel)) { - if (VN_AS(arrselp->fromp(), VarRef)->varp() == varp) return true; + for (AstArg* argp = m_stdRandCallp->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { + const AstNodeExpr* exprp = argp->exprp(); + // Traverse through expression to find the base variable + while (exprp) { + if (const AstNodeVarRef* const varrefp = VN_CAST(exprp, NodeVarRef)) { + if (varrefp->varp() == varp) return true; + break; + } + if (const AstMemberSel* const memberselp = VN_CAST(exprp, MemberSel)) { + if (memberselp->varp() == varp) return true; + exprp = memberselp->fromp(); + } else if (const AstArraySel* const arrselp = VN_CAST(exprp, ArraySel)) { + exprp = arrselp->fromp(); + } else if (const AstStructSel* const strselp = VN_CAST(exprp, StructSel)) { + exprp = strselp->fromp(); + } else if (const AstCMethodHard* const methodp = VN_CAST(exprp, CMethodHard)) { + exprp = methodp->fromp(); + } else { + break; + } } } return false; @@ -280,8 +289,6 @@ class RandomizeMarkVisitor final : public VNVisitor { targetClassp->foreachMember([&](AstClass* const, AstConstraint* const existingConstrp) { if (existingConstrp->name() == newName) { // Multiple paths lead to same constraint - unsupported pattern - std::string fullPath = rootVarRefp->name(); - for (AstVar* pathVar : newPath) { fullPath += "." + pathVar->name(); } isDuplicate = true; } }); @@ -290,12 +297,14 @@ class RandomizeMarkVisitor final : public VNVisitor { AstConstraint* const cloneConstrp = constrp->cloneTree(false); cloneConstrp->name(newName); cloneConstrp->foreach([&](AstVarRef* varRefp) { - AstNodeExpr* const chainp = buildMemberSelChain(rootVarRefp, newPath); - AstMemberSel* const finalSelp - = new AstMemberSel{varRefp->fileline(), chainp, varRefp->varp()}; - finalSelp->user2p(m_classp); - varRefp->replaceWith(finalSelp); - VL_DO_DANGLING(varRefp->deleteTree(), varRefp); + if (varRefp->varp()->isClassMember()) { + AstNodeExpr* const chainp = buildMemberSelChain(rootVarRefp, newPath); + AstMemberSel* const finalSelp + = new AstMemberSel{varRefp->fileline(), chainp, varRefp->varp()}; + finalSelp->user2p(m_classp); + varRefp->replaceWith(finalSelp); + VL_DO_DANGLING(varRefp->deleteTree(), varRefp); + } }); // Add constraint directly to the target class @@ -331,6 +340,55 @@ class RandomizeMarkVisitor final : public VNVisitor { } } + // Get randomized variables from (std::)randomize() arguments + // and mark AstNodeModule nodes in which they are defined + void handleRandomizeArgument(AstNodeExpr* exprp, AstVar* const varp, const bool stdRandomize) { + // IEEE 1800-2023 18.11: "Arguments are limited to the names of properties + // of the calling object; expressions are not allowed." + // However, for compatibility with other simulators, we support complex + // expressions like obj.member[idx].field in inline randomize(). + while (exprp) { + AstVar* randVarp = nullptr; + if (AstMemberSel* const memberSelp = VN_CAST(exprp, MemberSel)) { + randVarp = memberSelp->varp(); + exprp = memberSelp->fromp(); + } else if (AstArraySel* const arraySelp = VN_CAST(exprp, ArraySel)) { + exprp = arraySelp->fromp(); + continue; // Skip ArraySel, continue traversing + } else if (AstStructSel* const structSelp = VN_CAST(exprp, StructSel)) { + exprp = structSelp->fromp(); + continue; // Skip StructSel, continue traversing + } else if (AstCMethodHard* const methodp = VN_CAST(exprp, CMethodHard)) { + exprp = methodp->fromp(); + continue; + } else if (AstVarRef* const varrefp = VN_CAST(exprp, VarRef)) { + randVarp = varrefp->varp(); + varrefp->user1(true); + varrefp->access(VAccess::READWRITE); + exprp = nullptr; + } else { + // All invalid and unsupported expressions should be caught in V3Width + exprp->v3fatalSrc("Unexpected expression type in randomize() argument"); + } + UASSERT_OBJ(randVarp, exprp, "No rand variable found"); + if (randVarp == varp) return; + AstNode* backp = randVarp; + while (backp && !VN_IS(backp, NodeModule)) backp = backp->backp(); + if (stdRandomize) { + UASSERT_OBJ(backp, randVarp, "No class or module found for rand variable"); + backp->user1(IS_STD_RANDOMIZED); + } else { + // Inline randomized then + UASSERT_OBJ(VN_IS(backp, Class), randVarp, + "No class found for inline randomized variable"); + RandomizeMode randMode = {}; + randMode.usesMode = true; + randVarp->user1(randMode.asInt); + backp->user1(IS_RANDOMIZED_INLINE); + } + } + } + // VISITORS void visit(AstClass* nodep) override { VL_RESTORER(m_classp); @@ -378,7 +436,7 @@ class RandomizeMarkVisitor final : public VNVisitor { methodHardp->v3fatalSrc("Unknown rand_mode() receiver"); } } - if (!nodep->pinsp() && VN_IS(nodep->backp(), StmtExpr) + if (!nodep->argsp() && VN_IS(nodep->backp(), StmtExpr) && !nodep->backp()->fileline()->warnIsOff(V3ErrorCode::IGNOREDRETURN)) { nodep->v3warn( IGNOREDRETURN, @@ -388,14 +446,14 @@ class RandomizeMarkVisitor final : public VNVisitor { if (valid) { const RandModeTarget randModeTarget = RandModeTarget::get(fromp, m_classp); if ((!randModeTarget.receiverp || !randModeTarget.receiverp->isRand()) - && !nodep->pinsp()) { + && !nodep->argsp()) { nodep->v3error( "Cannot call 'rand_mode()' as a function on non-random variable"); valid = false; } else if (!randModeTarget.classp) { nodep->v3error("Cannot call 'rand_mode()' on non-random, non-class variable"); valid = false; - } else if (nodep->pinsp() && !VN_IS(nodep->backp(), StmtExpr)) { + } else if (nodep->argsp() && !VN_IS(nodep->backp(), StmtExpr)) { nodep->v3error("'rand_mode()' with arguments cannot be called as a function"); valid = false; } else if (randModeTarget.receiverp @@ -424,7 +482,7 @@ class RandomizeMarkVisitor final : public VNVisitor { } } if (!valid) { - if (!nodep->pinsp() && !VN_IS(nodep->backp(), StmtExpr)) { + if (!nodep->argsp() && !VN_IS(nodep->backp(), StmtExpr)) { nodep->replaceWith(new AstConst{nodep->fileline(), 0}); VL_DO_DANGLING(nodep->deleteTree(), nodep); } else { @@ -436,11 +494,11 @@ class RandomizeMarkVisitor final : public VNVisitor { if (nodep->name() == "constraint_mode") { bool valid = true; - if (nodep->pinsp() && !VN_IS(nodep->backp(), StmtExpr)) { + if (nodep->argsp() && !VN_IS(nodep->backp(), StmtExpr)) { nodep->v3error( "'constraint_mode()' with arguments cannot be called as a function"); valid = false; - } else if (!nodep->pinsp() && VN_IS(nodep->backp(), StmtExpr) + } else if (!nodep->argsp() && VN_IS(nodep->backp(), StmtExpr) && !nodep->backp()->fileline()->warnIsOff(V3ErrorCode::IGNOREDRETURN)) { nodep->v3warn( IGNOREDRETURN, @@ -454,11 +512,6 @@ class RandomizeMarkVisitor final : public VNVisitor { = VN_CAST(methodCallp->fromp(), ConstraintRef)) { constrp = constrRefp->constrp(); if (constrRefp->fromp()) classp = VN_AS(constrRefp->classOrPackagep(), Class); - if (constrp->isStatic()) { - nodep->v3warn(E_UNSUPPORTED, - "Unsupported: 'constraint_mode()' on static constraint"); - valid = false; - } } else if (AstClassRefDType* classRefDtp = VN_CAST(methodCallp->fromp()->dtypep()->skipRefp(), ClassRefDType)) { classp = classRefDtp->classp(); @@ -467,7 +520,7 @@ class RandomizeMarkVisitor final : public VNVisitor { valid = false; } } - if (!nodep->pinsp() && !constrp) { + if (!nodep->argsp() && !constrp) { nodep->v3error("Cannot call 'constraint_mode()' as a function on a variable"); valid = false; } @@ -478,16 +531,11 @@ class RandomizeMarkVisitor final : public VNVisitor { constrp->user1(constraintMode.asInt); } else { classp->foreachMember([=](AstClass*, AstConstraint* constrp) { - if (constrp->isStatic()) { - nodep->v3warn(E_UNSUPPORTED, - "Unsupported: 'constraint_mode()' on static constraint: " - << constrp->prettyNameQ()); - } constrp->user1(constraintMode.asInt); }); } } else { - if (!nodep->pinsp() && !VN_IS(nodep->backp(), StmtExpr)) { + if (!nodep->argsp() && !VN_IS(nodep->backp(), StmtExpr)) { nodep->replaceWith(new AstConst{nodep->fileline(), 0}); VL_DO_DANGLING(nodep->deleteTree(), nodep); } else { @@ -497,7 +545,16 @@ class RandomizeMarkVisitor final : public VNVisitor { return; } - if (nodep->name() != "randomize") return; + if (nodep->name() != "randomize") { + // Propagate user1 from children (same pattern as visit(AstNodeExpr*)) + if (m_constraintExprGenp || m_inStdWith) { + nodep->user1((nodep->op1p() && nodep->op1p()->user1()) + || (nodep->op2p() && nodep->op2p()->user1()) + || (nodep->op3p() && nodep->op3p()->user1()) + || (nodep->op4p() && nodep->op4p()->user1())); + } + return; + } AstClass* classp = m_classp; if (const AstMethodCall* const methodCallp = VN_CAST(nodep, MethodCall)) { if (const AstClassRefDType* const classRefp @@ -531,44 +588,13 @@ class RandomizeMarkVisitor final : public VNVisitor { } if (nodep->classOrPackagep()->name() == "std") { m_stdRandCallp = nullptr; - for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { - AstArg* const argp = VN_CAST(pinp, Arg); - if (!argp) continue; - AstNodeExpr* exprp = argp->exprp(); - while (exprp) { - AstVar* randVarp = nullptr; - AstVarRef* varrefp = nullptr; - if (AstMemberSel* const memberSelp = VN_CAST(exprp, MemberSel)) { - randVarp = memberSelp->varp(); - exprp = memberSelp->fromp(); - } else if ((varrefp = VN_CAST(exprp, VarRef))) { - randVarp = varrefp->varp(); - varrefp->user1(true); - exprp = nullptr; - } else { - varrefp = VN_AS(VN_CAST(exprp, ArraySel)->fromp(), VarRef); - randVarp = varrefp->varp(); - varrefp->user1(true); - varrefp->access(VAccess::READWRITE); - exprp = nullptr; - } - UASSERT_OBJ(randVarp, nodep, "No rand variable found"); - AstNode* backp = randVarp; - while (backp && (!VN_IS(backp, Class) && !VN_IS(backp, NodeModule))) { - backp = backp->backp(); - } - UASSERT_OBJ(VN_IS(backp, NodeModule), randVarp, - "No class or module found for rand variable"); - backp->user1(IS_STD_RANDOMIZED); - } + for (AstArg* argp = nodep->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { + handleRandomizeArgument(argp->exprp(), nullptr, true); } return; } - for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { - AstArg* const argp = VN_CAST(pinp, Arg); - if (!argp) continue; + for (AstArg* argp = nodep->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { classp->user1(IS_RANDOMIZED_INLINE); - AstNodeExpr* exprp = argp->exprp(); AstVar* fromVarp = nullptr; // If nodep is a method call, this is its receiver if (AstMethodCall* methodCallp = VN_CAST(nodep, MethodCall)) { if (AstMemberSel* const memberSelp = VN_CAST(methodCallp->fromp(), MemberSel)) { @@ -578,27 +604,17 @@ class RandomizeMarkVisitor final : public VNVisitor { fromVarp = varrefp->varp(); } } - while (exprp) { - AstVar* randVarp = nullptr; - if (AstMemberSel* const memberSelp = VN_CAST(exprp, MemberSel)) { - randVarp = memberSelp->varp(); - exprp = memberSelp->fromp(); - } else { - AstVarRef* const varrefp = VN_AS(exprp, VarRef); - randVarp = varrefp->varp(); - exprp = nullptr; - } - if (randVarp == fromVarp) break; - UASSERT_OBJ(randVarp, nodep, "No rand variable found"); - AstNode* backp = randVarp; - while (backp && !VN_IS(backp, Class)) backp = backp->backp(); - RandomizeMode randMode = {}; - randMode.usesMode = true; - randVarp->user1(randMode.asInt); - VN_AS(backp, Class)->user1(IS_RANDOMIZED_INLINE); - } + handleRandomizeArgument(argp->exprp(), fromVarp, false); } } + void visit(AstConstraintUnique* nodep) override { + VL_RESTORER(m_stmtp); + VL_RESTORER(m_constraintExprGenp); + m_stmtp = nodep; + m_constraintExprGenp = nodep; + iterateChildren(nodep); + if (!nodep->backp()) VL_DO_DANGLING(nodep->deleteTree(), nodep); + } void visit(AstConstraintExpr* nodep) override { VL_RESTORER(m_constraintExprGenp); m_constraintExprGenp = nodep; @@ -670,11 +686,7 @@ class RandomizeMarkVisitor final : public VNVisitor { void visit(AstWith* nodep) override { VL_RESTORER(m_withp); m_withp = nodep; - for (AstNode* pinp = m_stdRandCallp ? m_stdRandCallp->pinsp() : nullptr; pinp; - pinp = pinp->nextp()) { - AstWith* const withp = VN_CAST(pinp, With); - if (withp == nodep) m_inStdWith = true; - } + if (m_stdRandCallp && nodep == m_stdRandCallp->withp()) m_inStdWith = true; iterateChildrenConst(nodep); m_inStdWith = false; } @@ -687,6 +699,12 @@ class RandomizeMarkVisitor final : public VNVisitor { || (nodep->op3p() && nodep->op3p()->user1()) || (nodep->op4p() && nodep->op4p()->user1())); } + void visit(AstArg* nodep) override { + iterateChildrenConst(nodep); + if (!m_constraintExprGenp && !m_inStdWith) return; + nodep->user1(nodep->exprp() && nodep->exprp()->user1()); + } + void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } public: @@ -709,6 +727,7 @@ class ConstraintExprVisitor final : public VNVisitor { // AstMemberSel::user2p() -> AstNodeModule*. Pointer to containing module // VNuser3InUse m_inuser3; (Allocated for use in RandomizeVisitor) + AstClass* const m_classp; AstNodeFTask* const m_inlineInitTaskp; // Method to add write_var calls to // (may be null, then new() is used) AstVar* const m_genp; // VlRandomizer variable of the class @@ -734,6 +753,17 @@ class ConstraintExprVisitor final : public VNVisitor { return ""; } + // Extract SMT variable name from a solve-before expression. + // Returns empty string if the expression is not a simple variable reference. + std::string extractSolveBeforeVarName(AstNodeExpr* exprp) { + if (const AstMemberSel* const memberSelp = VN_CAST(exprp, MemberSel)) { + return buildMemberPath(memberSelp); + } else if (const AstVarRef* const varrefp = VN_CAST(exprp, VarRef)) { + return varrefp->name(); + } + return ""; + } + AstSFormatF* getConstFormat(AstNodeExpr* nodep) { return new AstSFormatF{nodep->fileline(), (nodep->width() & 3) ? "#b%b" : "#x%x", false, nodep}; @@ -848,6 +878,55 @@ class ConstraintExprVisitor final : public VNVisitor { return selp; } + // Extract return expression from a simple function body, or nullptr if too complex. + // Uses foreach to walk all assigns regardless of body organization (JumpBlock nesting etc.). + // Takes the last assignment to the return variable -- the first is the initializer. + AstNodeExpr* extractReturnExpr(AstFunc* funcp) { + AstVar* const retVarp = VN_CAST(funcp->fvarp(), Var); + if (!retVarp) return nullptr; + AstNodeExpr* retExprp = nullptr; + int assignCount = 0; + funcp->foreach([&](AstAssign* assignp) { + AstVarRef* const lhsp = VN_CAST(assignp->lhsp(), VarRef); + if (!lhsp || lhsp->varp() != retVarp) return; + retExprp = assignp->rhsp(); + ++assignCount; + }); + // Simple function: initializer + return (2) or just return (1) + if (assignCount > 2 || !retExprp) return nullptr; + return retExprp; + } + + // Bottom-up user1 propagation on inlined expression tree + void propagateUser1InlineRecurse(AstNodeExpr* nodep) { + if (VN_IS(nodep, NodeVarRef)) { + nodep->user1(VN_AS(nodep, NodeVarRef)->varp()->rand().isRandomizable()); + return; + } + if (VN_IS(nodep, Const)) { + nodep->user1(false); + return; + } + bool anyChild = false; + if (AstNodeExpr* const cp = VN_CAST(nodep->op1p(), NodeExpr)) { + propagateUser1InlineRecurse(cp); + anyChild |= cp->user1(); + } + if (AstNodeExpr* const cp = VN_CAST(nodep->op2p(), NodeExpr)) { + propagateUser1InlineRecurse(cp); + anyChild |= cp->user1(); + } + if (AstNodeExpr* const cp = VN_CAST(nodep->op3p(), NodeExpr)) { + propagateUser1InlineRecurse(cp); + anyChild |= cp->user1(); + } + if (AstNodeExpr* const cp = VN_CAST(nodep->op4p(), NodeExpr)) { + propagateUser1InlineRecurse(cp); + anyChild |= cp->user1(); + } + nodep->user1(anyChild); + } + // VISITORS void visit(AstNodeVarRef* nodep) override { AstVar* varp = nodep->varp(); @@ -884,9 +963,9 @@ class ConstraintExprVisitor final : public VNVisitor { nodep->unlinkFrBack(&relinker); AstNodeExpr* exprp; if (randMode.usesMode) { - // Use string literal to avoid double formatting - exprp = new AstCExpr{nodep->fileline(), "std::string(\"" + smtName + "\")", 1}; - exprp->dtypeSetString(); + // Use AstSFormatF (not AstConst{String}) to prevent editFormat/V3Const + // from reformatting the SMT variable name into a hex literal + exprp = new AstSFormatF{nodep->fileline(), smtName, false, nullptr}; // Get const format, using membersel if available for correct width/value AstNodeExpr* constFormatp @@ -941,76 +1020,209 @@ class ConstraintExprVisitor final : public VNVisitor { if (isGlobalConstrained) m_writtenVars.insert(smtName); // For global constraints, delete nodep after processing if (isGlobalConstrained && !nodep->backp()) VL_DO_DANGLING(pushDeletep(nodep), nodep); - AstCMethodHard* const methodp = new AstCMethodHard{ - varp->fileline(), - new AstVarRef{varp->fileline(), VN_AS(m_genp->user2p(), NodeModule), m_genp, - VAccess::READWRITE}, - VCMethod::RANDOMIZER_WRITE_VAR}; - uint32_t dimension = 0; - if (VN_IS(varp->dtypep(), UnpackArrayDType) || VN_IS(varp->dtypep(), DynArrayDType) - || VN_IS(varp->dtypep(), QueueDType) || VN_IS(varp->dtypep(), AssocArrayDType)) { - const std::pair dims - = varp->dtypep()->dimensions(/*includeBasic=*/true); - const uint32_t unpackedDimensions = dims.second; - dimension = unpackedDimensions; - } - if (VN_IS(varp->dtypeSkipRefp(), StructDType) - && !VN_AS(varp->dtypeSkipRefp(), StructDType)->packed()) { - VN_AS(varp->dtypeSkipRefp(), StructDType)->markConstrainedRand(true); - dimension = 1; - } - methodp->dtypeSetVoid(); - AstNodeModule* classp; - if (membersel) { - // For membersel, find the root varref to get the class where randomize() is called - AstNode* rootNode = membersel->fromp(); - while (AstMemberSel* nestedMemberSel = VN_CAST(rootNode, MemberSel)) { - rootNode = nestedMemberSel->fromp(); + + // Detect if variable is an array of class references + bool isClassRefArray = false; + AstClassRefDType* elemClassRefDtp = nullptr; + { + AstNodeDType* varDtp = varp->dtypep()->skipRefp(); + if (VN_IS(varDtp, DynArrayDType) || VN_IS(varDtp, QueueDType) + || VN_IS(varDtp, UnpackArrayDType) || VN_IS(varDtp, AssocArrayDType)) { + AstNodeDType* const elemDtp = varDtp->subDTypep()->skipRefp(); + elemClassRefDtp = VN_CAST(elemDtp, ClassRefDType); + if (elemClassRefDtp) isClassRefArray = true; } - if (AstNodeVarRef* rootVarRef = VN_CAST(rootNode, NodeVarRef)) { - classp = VN_AS(rootVarRef->varp()->user2p(), NodeModule); - } else { - classp = VN_AS(membersel->user2p(), NodeModule); + } + + if (isClassRefArray && !membersel) { + // Per-member registration loop for class ref arrays + FileLine* const fl = varp->fileline(); + AstClass* const elemClassp = elemClassRefDtp->classp(); + AstNodeModule* const varClassp = VN_AS(varp->user2p(), NodeModule); + + AstVar* const iterVarp + = new AstVar{fl, VVarType::BLOCKTEMP, "__Vi", varp->findUInt32DType()}; + iterVarp->funcLocal(true); + iterVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); + + AstNode* const stmtsp = iterVarp; + stmtsp->addNext(new AstAssign{fl, new AstVarRef{fl, iterVarp, VAccess::WRITE}, + new AstConst{fl, 0}}); + + AstVarRef* const arraySizeRef = new AstVarRef{fl, varClassp, varp, VAccess::READ}; + arraySizeRef->classOrPackagep(classOrPackagep); + AstCMethodHard* const sizep + = new AstCMethodHard{fl, arraySizeRef, VCMethod::DYN_SIZE, nullptr}; + sizep->dtypeSetUInt32(); + + AstLoop* const loopp = new AstLoop{fl}; + stmtsp->addNext(loopp); + loopp->addStmtsp(new AstLoopTest{ + fl, loopp, new AstLt{fl, new AstVarRef{fl, iterVarp, VAccess::READ}, sizep}}); + + AstVarRef* const arrayAtRef = new AstVarRef{fl, varClassp, varp, VAccess::READ}; + arrayAtRef->classOrPackagep(classOrPackagep); + AstCMethodHard* const atReadp + = new AstCMethodHard{fl, arrayAtRef, VCMethod::ARRAY_AT, + new AstVarRef{fl, iterVarp, VAccess::READ}}; + atReadp->dtypep(elemClassRefDtp); + AstIf* const ifNonNullp = new AstIf{ + fl, new AstNeq{fl, atReadp, new AstConst{fl, AstConst::Null{}}}, nullptr}; + loopp->addStmtsp(ifNonNullp); + + AstCStmt* const bufDeclp = new AstCStmt{fl, "char __Vn[256];\n"}; + ifNonNullp->addThensp(bufDeclp); + + // 32-bit index hex chars for SMT name formatting + constexpr int idxWidth = 32; + const int fmtWidth = VL_WORDS_I(idxWidth) * 8; + + for (const AstClass* cp = elemClassp; cp; + cp = cp->extendsp() ? cp->extendsp()->classp() : nullptr) { + for (AstNode* mnodep = cp->stmtsp(); mnodep; mnodep = mnodep->nextp()) { + AstVar* const memberVarp = VN_CAST(mnodep, Var); + if (!memberVarp || !memberVarp->rand().isRandomizable()) continue; + AstNodeDType* const memberDtp = memberVarp->dtypep()->skipRefp(); + if (VN_IS(memberDtp, ClassRefDType) || VN_IS(memberDtp, DynArrayDType) + || VN_IS(memberDtp, QueueDType) || VN_IS(memberDtp, UnpackArrayDType) + || VN_IS(memberDtp, AssocArrayDType)) + continue; + const int memberWidth = memberDtp->width(); + + AstCStmt* const fmtp = new AstCStmt{fl}; + fmtp->add("VL_SNPRINTF(__Vn, sizeof(__Vn), \"" + smtName + ".%0" + + std::to_string(fmtWidth) + "x." + memberVarp->name() + + "\", (unsigned)"); + fmtp->add(new AstVarRef{fl, iterVarp, VAccess::READ}); + fmtp->add(");\n"); + ifNonNullp->addThensp(fmtp); + + AstVarRef* const arrayWrRef + = new AstVarRef{fl, varClassp, varp, VAccess::WRITE}; + arrayWrRef->classOrPackagep(classOrPackagep); + AstCMethodHard* const atWritep + = new AstCMethodHard{fl, arrayWrRef, VCMethod::ARRAY_AT_WRITE, + new AstVarRef{fl, iterVarp, VAccess::READ}}; + atWritep->dtypep(elemClassRefDtp); + AstMemberSel* const memberSelp + = new AstMemberSel{fl, atWritep, memberVarp}; + + AstCMethodHard* const writeVarp = new AstCMethodHard{ + fl, + new AstVarRef{fl, VN_AS(m_genp->user2p(), NodeModule), m_genp, + VAccess::READWRITE}, + VCMethod::RANDOMIZER_WRITE_VAR}; + writeVarp->dtypeSetVoid(); + writeVarp->addPinsp(memberSelp); + writeVarp->addPinsp(new AstConst{fl, AstConst::Unsized64{}, + static_cast(memberWidth)}); + AstCExpr* const nameRefp = new AstCExpr{fl, AstCExpr::Pure{}, "__Vn", 0}; + nameRefp->dtypep(varp->dtypep()); + writeVarp->addPinsp(nameRefp); + writeVarp->addPinsp(new AstConst{fl, AstConst::Unsized64{}, 0ULL}); + ifNonNullp->addThensp(writeVarp->makeStmt()); + } } - methodp->addPinsp(membersel); - } else { - classp = VN_AS(varp->user2p(), NodeModule); - AstVarRef* const varRefp - = new AstVarRef{varp->fileline(), classp, varp, VAccess::WRITE}; - varRefp->classOrPackagep(classOrPackagep); - methodp->addPinsp(varRefp); - } - AstNodeDType* tmpDtypep = varp->dtypep(); - while (VN_IS(tmpDtypep, UnpackArrayDType) || VN_IS(tmpDtypep, DynArrayDType) - || VN_IS(tmpDtypep, QueueDType) || VN_IS(tmpDtypep, AssocArrayDType)) - tmpDtypep = tmpDtypep->subDTypep(); - const size_t width = tmpDtypep->width(); - methodp->addPinsp( - new AstConst{varp->dtypep()->fileline(), AstConst::Unsized64{}, width}); - AstNodeExpr* const varnamep - = new AstCExpr{varp->fileline(), "\"" + smtName + "\"", varp->width()}; - varnamep->dtypep(varp->dtypep()); - methodp->addPinsp(varnamep); - methodp->addPinsp( - new AstConst{varp->dtypep()->fileline(), AstConst::Unsized64{}, dimension}); - // Don't pass randMode.index for global constraints with membersel - // because constraint object can't access nested object's randmode array - if (randMode.usesMode && !(isGlobalConstrained && membersel)) { - methodp->addPinsp( - new AstConst{varp->fileline(), AstConst::Unsized64{}, randMode.index}); - } - AstNodeFTask* initTaskp = m_inlineInitTaskp; - if (!initTaskp) { + + loopp->addStmtsp( + new AstAssign{fl, new AstVarRef{fl, iterVarp, VAccess::WRITE}, + new AstAdd{fl, new AstConst{fl, 1}, + new AstVarRef{fl, iterVarp, VAccess::READ}}}); + + AstBegin* const beginp = new AstBegin{fl, "", stmtsp, true}; varp->user3(true); + AstNodeFTask* initTaskp = m_inlineInitTaskp; + if (!initTaskp) { + initTaskp = VN_AS(m_memberMap.findMember(varClassp, "new"), NodeFTask); + UASSERT_OBJ(initTaskp, varClassp, "No new() in class"); + } + initTaskp->addStmtsp(beginp); + } else { + AstCMethodHard* const methodp = new AstCMethodHard{ + varp->fileline(), + new AstVarRef{varp->fileline(), VN_AS(m_genp->user2p(), NodeModule), m_genp, + VAccess::READWRITE}, + VCMethod::RANDOMIZER_WRITE_VAR}; + uint32_t dimension = 0; + if (VN_IS(varp->dtypep(), UnpackArrayDType) || VN_IS(varp->dtypep(), DynArrayDType) + || VN_IS(varp->dtypep(), QueueDType) + || VN_IS(varp->dtypep(), AssocArrayDType)) { + const std::pair dims + = varp->dtypep()->dimensions(/*includeBasic=*/true); + const uint32_t unpackedDimensions = dims.second; + dimension = unpackedDimensions; + } + if (VN_IS(varp->dtypeSkipRefp(), StructDType) + && !VN_AS(varp->dtypeSkipRefp(), StructDType)->packed()) { + VN_AS(varp->dtypeSkipRefp(), StructDType)->markConstrainedRand(true); + dimension = 1; + } + methodp->dtypeSetVoid(); + AstNodeModule* classp; if (membersel) { - initTaskp = VN_AS(m_memberMap.findMember(classp, "randomize"), NodeFTask); - UASSERT_OBJ(initTaskp, classp, "No randomize() in class"); + // For membersel, find the root varref to get the class + AstNode* rootNode = membersel->fromp(); + while (AstMemberSel* nestedMemberSel = VN_CAST(rootNode, MemberSel)) { + rootNode = nestedMemberSel->fromp(); + } + if (AstNodeVarRef* rootVarRef = VN_CAST(rootNode, NodeVarRef)) { + classp = VN_AS(rootVarRef->varp()->user2p(), NodeModule); + } else { + classp = VN_AS(membersel->user2p(), NodeModule); + } + methodp->addPinsp(membersel); } else { - initTaskp = VN_AS(m_memberMap.findMember(classp, "new"), NodeFTask); - UASSERT_OBJ(initTaskp, classp, "No new() in class"); + classp = VN_AS(varp->user2p(), NodeModule); + AstVarRef* const varRefp + = new AstVarRef{varp->fileline(), classp, varp, VAccess::WRITE}; + varRefp->classOrPackagep(classOrPackagep); + methodp->addPinsp(varRefp); + } + AstNodeDType* tmpDtypep = varp->dtypep(); + while (VN_IS(tmpDtypep, UnpackArrayDType) || VN_IS(tmpDtypep, DynArrayDType) + || VN_IS(tmpDtypep, QueueDType) || VN_IS(tmpDtypep, AssocArrayDType)) + tmpDtypep = tmpDtypep->subDTypep(); + const size_t width = tmpDtypep->width(); + methodp->addPinsp( + new AstConst{varp->dtypep()->fileline(), AstConst::Unsized64{}, width}); + AstNodeExpr* const varnamep = new AstCExpr{varp->fileline(), AstCExpr::Pure{}, + "\"" + smtName + "\"", varp->width()}; + varnamep->dtypep(varp->dtypep()); + methodp->addPinsp(varnamep); + methodp->addPinsp( + new AstConst{varp->dtypep()->fileline(), AstConst::Unsized64{}, dimension}); + // Don't pass randMode.index for global constraints with membersel + if (randMode.usesMode && !(isGlobalConstrained && membersel)) { + methodp->addPinsp( + new AstConst{varp->fileline(), AstConst::Unsized64{}, randMode.index}); + } + AstNodeFTask* initTaskp = m_inlineInitTaskp; + if (!initTaskp) { + varp->user3(true); + if (membersel) { + initTaskp = VN_AS(m_memberMap.findMember(classp, "randomize"), NodeFTask); + UASSERT_OBJ(initTaskp, classp, "No randomize() in class"); + } else { + initTaskp = VN_AS(m_memberMap.findMember(classp, "new"), NodeFTask); + UASSERT_OBJ(initTaskp, classp, "No new() in class"); + } + } + initTaskp->addStmtsp(methodp->makeStmt()); + // If randc, also emit markRandc() for cyclic tracking + if (varp->isRandC()) { + AstCMethodHard* const markp = new AstCMethodHard{ + varp->fileline(), + new AstVarRef{varp->fileline(), VN_AS(m_genp->user2p(), NodeModule), + m_genp, VAccess::READWRITE}, + VCMethod::RANDOMIZER_MARK_RANDC}; + markp->dtypeSetVoid(); + AstNodeExpr* const nameExprp = new AstCExpr{ + varp->fileline(), AstCExpr::Pure{}, "\"" + smtName + "\"", varp->width()}; + nameExprp->dtypep(varp->dtypep()); + markp->addPinsp(nameExprp); + initTaskp->addStmtsp(markp->makeStmt()); } } - initTaskp->addStmtsp(methodp->makeStmt()); } else { // Variable already written, clean up cloned membersel if any if (membersel) VL_DO_DANGLING(membersel->deleteTree(), membersel); @@ -1018,15 +1230,15 @@ class ConstraintExprVisitor final : public VNVisitor { if (isGlobalConstrained && !nodep->backp()) VL_DO_DANGLING(pushDeletep(nodep), nodep); } } - void visit(AstCountOnes* nodep) override { - // Convert it to (x & 1) + ((x & 2) >> 1) + ((x & 4) >> 2) + ... - FileLine* const fl = nodep->fileline(); - AstNodeExpr* const argp = nodep->lhsp()->unlinkFrBack(); - V3Number numOne{nodep, argp->width(), 1}; + // Build popcount expansion: (x & 1) + ((x & 2) >> 1) + ... + // argp is consumed; caller must clone if reusing. + AstNodeExpr* buildCountOnesExpansion(FileLine* fl, AstNodeExpr* argp, + AstNodeExpr* dtypeNodep) { + V3Number numOne{fl, argp->width(), 1}; AstNodeExpr* sump = new AstAnd{fl, argp, new AstConst{fl, numOne}}; sump->user1(true); for (int i = 1; i < argp->width(); i++) { - V3Number numBitMask{nodep, argp->width(), 0}; + V3Number numBitMask{fl, argp->width(), 0}; numBitMask.setBit(i, 1); AstAnd* const andp = new AstAnd{fl, argp->cloneTreePure(false), new AstConst{fl, numBitMask}}; @@ -1034,11 +1246,17 @@ class ConstraintExprVisitor final : public VNVisitor { AstShiftR* const shiftp = new AstShiftR{ fl, andp, new AstConst{fl, AstConst::WidthedValue{}, argp->width(), (uint32_t)i}}; shiftp->user1(true); - shiftp->dtypeFrom(nodep); - sump = new AstAdd{nodep->fileline(), sump, shiftp}; + shiftp->dtypeFrom(dtypeNodep); + sump = new AstAdd{fl, sump, shiftp}; sump->user1(true); } - // Restore the original width + return sump; + } + + void visit(AstCountOnes* nodep) override { + FileLine* const fl = nodep->fileline(); + AstNodeExpr* const argp = nodep->lhsp()->unlinkFrBack(); + AstNodeExpr* sump = buildCountOnesExpansion(fl, argp, nodep); if (nodep->width() > sump->width()) { sump = new AstExtend{fl, sump, nodep->width()}; sump->user1(true); @@ -1062,6 +1280,196 @@ class ConstraintExprVisitor final : public VNVisitor { VL_DO_DANGLING(nodep->deleteTree(), nodep); iterate(neqp); } + void visit(AstOneHot* nodep) override { + if (editFormat(nodep)) return; + // $onehot(x) = (x != 0) && ((x & (x-1)) == 0) + FileLine* const fl = nodep->fileline(); + AstNodeExpr* const argp = nodep->lhsp()->unlinkFrBack(); + const int w = argp->width(); + + V3Number numZero{fl, w, 0}; + AstNeq* const neZerop + = new AstNeq{fl, argp->cloneTreePure(false), new AstConst{fl, numZero}}; + neZerop->user1(true); + + V3Number numOne{fl, w, 1}; + AstSub* const subp = new AstSub{fl, argp->cloneTreePure(false), new AstConst{fl, numOne}}; + subp->dtypeFrom(argp); + subp->user1(true); + + AstAnd* const andp = new AstAnd{fl, argp, subp}; + andp->dtypeFrom(argp); + andp->user1(true); + + V3Number numZero2{fl, w, 0}; + AstEq* const eqZerop = new AstEq{fl, andp, new AstConst{fl, numZero2}}; + eqZerop->user1(true); + + AstLogAnd* const resultp = new AstLogAnd{fl, neZerop, eqZerop}; + resultp->user1(true); + + nodep->replaceWith(resultp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + iterate(resultp); + } + void visit(AstOneHot0* nodep) override { + if (editFormat(nodep)) return; + // $onehot0(x) = (x & (x-1)) == 0 + FileLine* const fl = nodep->fileline(); + AstNodeExpr* const argp = nodep->lhsp()->unlinkFrBack(); + const int w = argp->width(); + + V3Number numOne{fl, w, 1}; + AstSub* const subp = new AstSub{fl, argp->cloneTreePure(false), new AstConst{fl, numOne}}; + subp->dtypeFrom(argp); + subp->user1(true); + + AstAnd* const andp = new AstAnd{fl, argp, subp}; + andp->dtypeFrom(argp); + andp->user1(true); + + V3Number numZero{fl, w, 0}; + AstEq* const eqp = new AstEq{fl, andp, new AstConst{fl, numZero}}; + eqp->user1(true); + + nodep->replaceWith(eqp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + iterate(eqp); + } + void visit(AstCountBits* nodep) override { + if (editFormat(nodep)) return; + FileLine* const fl = nodep->fileline(); + + bool countOnes = false; + bool countZeros = false; + for (AstNodeExpr* ctrlp : {nodep->rhsp(), nodep->thsp(), nodep->fhsp()}) { + const AstConst* const cp = VN_CAST(ctrlp, Const); + if (!cp) { + nodep->v3warn(E_UNSUPPORTED, + "Unsupported: non-constant control in $countbits inside constraint"); + AstConst* const zerop + = new AstConst{fl, AstConst::WidthedValue{}, nodep->width(), 0u}; + nodep->replaceWith(zerop); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + return; + } + if (cp->num().bitIs1(0) && !countOnes) + countOnes = true; + else if (cp->num().bitIs0(0) && !countZeros) + countZeros = true; + } + + AstNodeExpr* const argp = nodep->lhsp()->unlinkFrBack(); + const int argWidth = argp->width(); + AstNodeExpr* sump = nullptr; + if (countOnes && countZeros) { + // ones + zeros = width for 2-state types + sump = new AstConst{fl, AstConst::WidthedValue{}, nodep->width(), (uint32_t)argWidth}; + VL_DO_DANGLING(argp->deleteTree(), argp); + } else if (countOnes) { + sump = buildCountOnesExpansion(fl, argp, nodep); + } else if (countZeros) { + // width - countones(x) + AstNodeExpr* const onesCountp = buildCountOnesExpansion(fl, argp, nodep); + V3Number widthVal{nodep, onesCountp->width(), (uint32_t)argWidth}; + sump = new AstSub{fl, new AstConst{fl, widthVal}, onesCountp}; + sump->dtypeFrom(onesCountp); + sump->user1(true); + } else { + sump = new AstConst{fl, AstConst::WidthedValue{}, nodep->width(), 0u}; + VL_DO_DANGLING(argp->deleteTree(), argp); + } + + if (nodep->width() > sump->width()) { + sump = new AstExtend{fl, sump, nodep->width()}; + sump->user1(true); + } else if (nodep->width() < sump->width()) { + sump = new AstSel{fl, sump, 0, nodep->width()}; + sump->user1(true); + } + + nodep->replaceWith(sump); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + iterate(sump); + } + void visit(AstCLog2* nodep) override { + if (editFormat(nodep)) return; + // $clog2(x): ITE chain (x<=1)?0 : (x<=2)?1 : ... : argWidth + FileLine* const fl = nodep->fileline(); + AstNodeExpr* const argp = nodep->lhsp()->unlinkFrBack(); + const int argWidth = argp->width(); + const int resultWidth = nodep->width(); + + AstNodeExpr* resultp + = new AstConst{fl, AstConst::WidthedValue{}, resultWidth, (uint32_t)argWidth}; + + for (int k = argWidth - 1; k >= 0; k--) { + V3Number threshold{fl, argWidth, 0}; + if (k < 32) + threshold.setLong(1ULL << k); + else + threshold.setBit(k, 1); + + AstLte* const ltep + = new AstLte{fl, argp->cloneTreePure(false), new AstConst{fl, threshold}}; + ltep->user1(true); + + AstConst* const valuep + = new AstConst{fl, AstConst::WidthedValue{}, resultWidth, (uint32_t)k}; + + resultp = new AstCond{fl, ltep, valuep, resultp}; + resultp->dtypeChgWidthSigned(resultWidth, resultWidth, VSigning::SIGNED); + resultp->user1(true); + } + + VL_DO_DANGLING(argp->deleteTree(), argp); + nodep->replaceWith(resultp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + iterate(resultp); + } + void handlePow(AstNodeBiop* nodep) { + if (AstConst* const exponentp = VN_CAST(nodep->rhsp(), Const)) { + FileLine* const fl = nodep->fileline(); + AstNodeExpr* const basep = nodep->lhsp(); + V3Number numOne{nodep, basep->width(), 1}; + AstNodeExpr* powerp = new AstConst{fl, numOne}; + const bool baseSigned = VN_IS(nodep, PowSS) || VN_IS(nodep, PowSU); + const int32_t exponent = baseSigned ? exponentp->toSInt() : exponentp->toUInt(); + if (exponent > 0) { + for (int32_t i = 0; i < exponent; i++) { + if (baseSigned) { + powerp = new AstMulS{fl, powerp, basep->cloneTreePure(false)}; + } else { + powerp = new AstMul{fl, powerp, basep->cloneTreePure(false)}; + } + powerp->user1(true); + } + } else if (exponent < 0) { + // Limit chain of divisions to max 2, because operations are on integers. + // Two divisions are needed to preserve the sign. + if (baseSigned) { + powerp = new AstDivS{fl, powerp, basep->cloneTreePure(false)}; + powerp->user1(true); + powerp = new AstDivS{fl, powerp, basep->cloneTreePure(false)}; + powerp->user1(true); + } else { + powerp = new AstDiv{fl, powerp, basep->cloneTreePure(false)}; + powerp->user1(true); + } + } + nodep->replaceWith(powerp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + iterate(powerp); + } else { + nodep->v3warn( + CONSTRAINTIGN, + "Unsupported: Power (**) expression with non-constant exponent in constraint"); + } + } + void visit(AstPow* nodep) override { handlePow(nodep); } + void visit(AstPowSS* nodep) override { handlePow(nodep); } + void visit(AstPowSU* nodep) override { handlePow(nodep); } + void visit(AstPowUS* nodep) override { handlePow(nodep); } void visit(AstNodeBiop* nodep) override { if (editFormat(nodep)) return; editSMT(nodep, nodep->lhsp(), nodep->rhsp()); @@ -1080,6 +1488,10 @@ class ConstraintExprVisitor final : public VNVisitor { // Do not burden the solver if cond computable: (cond ? "then" : "else") iterate(nodep->thenp()); iterate(nodep->elsep()); + UASSERT_OBJ( + nodep->thenp()->isString() && nodep->elsep()->isString(), nodep, + "Branches of conditional expression in constraint not converted to strings"); + nodep->dtypeSetString(); return; } // Fall back to "(ite cond then else)" @@ -1105,6 +1517,7 @@ class ConstraintExprVisitor final : public VNVisitor { editSMT(nodep, nodep->fromp(), lsbp, msbp); } void visit(AstStructSel* nodep) override { + if (editFormat(nodep)) return; m_structSel = true; if (VN_IS(nodep->fromp()->dtypep()->skipRefp(), StructDType)) { AstNodeExpr* const fromp = nodep->fromp(); @@ -1138,7 +1551,6 @@ class ConstraintExprVisitor final : public VNVisitor { } } iterateChildren(nodep); - if (editFormat(nodep)) return; FileLine* const fl = nodep->fileline(); AstSFormatF* newp = nullptr; if (VN_AS(nodep->fromp(), SFormatF)->name() == "%@.%@") { @@ -1253,6 +1665,38 @@ class ConstraintExprVisitor final : public VNVisitor { nodep->replaceWith(varRefp); VL_DO_DANGLING(pushDeletep(nodep), nodep); visit(varRefp); + } else if (nodep->user1() && VN_IS(nodep->fromp(), CMethodHard) + && VN_AS(nodep->fromp(), CMethodHard)->method() == VCMethod::ARRAY_AT) { + // Class ref array element member access (e.g., items[i].val) + AstCMethodHard* const cmethodp = VN_AS(nodep->fromp(), CMethodHard); + AstNodeDType* const arrayDtp = cmethodp->fromp()->dtypep()->skipRefp(); + AstNodeDType* const elemDtp = arrayDtp->subDTypep()->skipRefp(); + if (VN_IS(elemDtp, ClassRefDType)) { + VL_RESTORER(m_structSel); + m_structSel = true; + iterateChildren(nodep); + FileLine* const fl = nodep->fileline(); + AstSFormatF* newp = nullptr; + if (AstSFormatF* const fromp = VN_CAST(nodep->fromp(), SFormatF)) { + if (fromp->name() == "%@.%@") { + newp = new AstSFormatF{fl, "%@.%@." + nodep->name(), false, + fromp->exprsp()->cloneTreePure(true)}; + } else { + newp = new AstSFormatF{fl, fromp->name() + "." + nodep->name(), false, + nullptr}; + } + } else { + newp = new AstSFormatF{fl, nodep->name(), false, nullptr}; + } + nodep->replaceWith(newp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + return; + } + // Not a class ref element, fall through to normal handling + iterateChildren(nodep); + nodep->replaceWith(nodep->fromp()->unlinkFrBack()); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + return; } else if (nodep->user1()) { iterateChildren(nodep); nodep->replaceWith(nodep->fromp()->unlinkFrBack()); @@ -1264,6 +1708,7 @@ class ConstraintExprVisitor final : public VNVisitor { } void visit(AstSFormatF* nodep) override {} void visit(AstStmtExpr* nodep) override {} + void visit(AstCStmt* nodep) override {} void visit(AstConstraintIf* nodep) override { AstNodeExpr* newp = nullptr; FileLine* const fl = nodep->fileline(); @@ -1293,9 +1738,10 @@ class ConstraintExprVisitor final : public VNVisitor { // Convert to plain foreach FileLine* const fl = nodep->fileline(); - AstNode* const arrayp = nodep->arrayp()->unlinkFrBack(); - if (m_wantSingle) { - AstNodeExpr* const itemp = editSingle(fl, nodep->stmtsp()); + if (!nodep->bodyp()) { + nodep->unlinkFrBack(); + } else if (m_wantSingle) { + AstNodeExpr* const itemp = editSingle(fl, nodep->bodyp()); AstCStmt* const cstmtp = new AstCStmt{fl}; cstmtp->add("ret += \" \";\n"); cstmtp->add("ret += "); @@ -1304,25 +1750,155 @@ class ConstraintExprVisitor final : public VNVisitor { AstCExpr* const cexprp = new AstCExpr{fl}; cexprp->dtypeSetString(); cexprp->add("([&]{\nstd::string ret;\n"); - cexprp->add(new AstBegin{fl, "", new AstForeach{fl, arrayp, cstmtp}, true}); + cexprp->add(new AstBegin{ + fl, "", new AstForeach{fl, nodep->headerp()->unlinkFrBack(), cstmtp}, true}); cexprp->add("return ret.empty() ? \"#b1\" : \"(bvand\" + ret + \")\";\n})()"); nodep->replaceWith(new AstSFormatF{fl, "%@", false, cexprp}); } else { - iterateAndNextNull(nodep->stmtsp()); - nodep->replaceWith(new AstBegin{ - fl, "", new AstForeach{fl, arrayp, nodep->stmtsp()->unlinkFrBackWithNext()}, - true}); + iterateAndNextNull(nodep->bodyp()); + nodep->replaceWith(new AstBegin{fl, "", + new AstForeach{fl, nodep->headerp()->unlinkFrBack(), + nodep->bodyp()->unlinkFrBackWithNext()}, + true}); } VL_DO_DANGLING(nodep->deleteTree(), nodep); } void visit(AstConstraintBefore* nodep) override { - nodep->v3warn(CONSTRAINTIGN, "Constraint expression ignored (imperfect distribution)"); + // Generate solveBefore() calls for each (lhs, rhs) variable pair. + // Do NOT iterate children -- these are variable references, not constraint expressions. + FileLine* const fl = nodep->fileline(); + AstNodeModule* const genModp = VN_AS(m_genp->user2p(), NodeModule); + + for (AstNodeExpr* lhsp = nodep->lhssp(); lhsp; lhsp = VN_CAST(lhsp->nextp(), NodeExpr)) { + const std::string lhsName = extractSolveBeforeVarName(lhsp); + if (lhsName.empty()) { + lhsp->v3warn(CONSTRAINTIGN, + "Unsupported: non-variable expression in solve...before"); + continue; + } + for (AstNodeExpr* rhsp = nodep->rhssp(); rhsp; + rhsp = VN_CAST(rhsp->nextp(), NodeExpr)) { + const std::string rhsName = extractSolveBeforeVarName(rhsp); + if (rhsName.empty()) { + rhsp->v3warn(CONSTRAINTIGN, + "Unsupported: non-variable expression in solve...before"); + continue; + } + AstCMethodHard* const callp = new AstCMethodHard{ + fl, new AstVarRef{fl, genModp, m_genp, VAccess::READWRITE}, + VCMethod::RANDOMIZER_SOLVE_BEFORE}; + callp->dtypeSetVoid(); + AstNodeExpr* const beforeNamep + = new AstCExpr{fl, AstCExpr::Pure{}, "\"" + lhsName + "\""}; + beforeNamep->dtypeSetUInt32(); + AstNodeExpr* const afterNamep + = new AstCExpr{fl, AstCExpr::Pure{}, "\"" + rhsName + "\""}; + afterNamep->dtypeSetUInt32(); + callp->addPinsp(beforeNamep); + callp->addPinsp(afterNamep); + nodep->addHereThisAsNext(callp->makeStmt()); + } + } VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } void visit(AstConstraintUnique* nodep) override { - nodep->v3warn(CONSTRAINTIGN, "Constraint expression ignored (unsupported)"); - VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); + if (!m_classp) { + nodep->v3warn(CONSTRAINTIGN, + "Unsupported: Unique constraint in std::randomize() with {}"); + pushDeletep(nodep->unlinkFrBack()); + return; + } + UASSERT_OBJ(m_classp, nodep, "m_classp not set"); + + FileLine* const fl = nodep->fileline(); + + AstNodeFTask* const initTaskp = VN_AS(m_memberMap.findMember(m_classp, "new"), NodeFTask); + UASSERT_OBJ(initTaskp, nodep, "Class has no init Task"); + + AstVar* const genVarp = [](const AstClass* classp) { + while (classp->extendsp()) classp = classp->extendsp()->classp(); + return VN_AS(classp->user3p(), Var); + }(m_classp); + + // UASSERT_OBJ(genVarp, nodep, "No generator variable"); + if (!genVarp) { + // This shall be substituted with an assert when it will be supported + nodep->v3warn(CONSTRAINTIGN, "Unsupported: Unique constraint in randomize() with {}"); + pushDeletep(nodep->unlinkFrBack()); + return; + } + + AstNodeModule* const modp = VN_AS(genVarp->user2p(), NodeModule); + UASSERT_OBJ(modp, nodep, "genVarp has no NodeModule set"); + + for (AstNode* itemp = nodep->rangesp(); itemp; itemp = itemp->nextp()) { + if (AstVarRef* const varRefp = VN_CAST(itemp, VarRef)) { + AstVar* const varp = varRefp->varp(); + + AstNodeDType* const dtypep = varp->dtypep()->skipRefp(); + if (AstUnpackArrayDType* const up = VN_CAST(dtypep, UnpackArrayDType)) { + AstRange* const rangep = up->rangep(); + if (!rangep || !VN_IS(rangep->leftp(), Const) + || !VN_IS(rangep->rightp(), Const)) { + nodep->v3warn( + CONSTRAINTIGN, + "Unsupported: Unique constraint on other than static arrays"); + continue; + } + + // Ensure it is ONLY 1-D by checking that the sub-type is NOT an array/queue + // We skip refs (typedefs) to see the actual underlying type + AstNodeDType* const subp = up->subDTypep()->skipRefp(); + if (VN_IS(subp, NodeArrayDType) || VN_IS(subp, QueueDType) + || VN_IS(subp, DynArrayDType)) { + nodep->v3warn( + CONSTRAINTIGN, + "Unsupported: Unique constraint on other than static arrays"); + continue; + } + } else { + nodep->v3warn(CONSTRAINTIGN, + "Unsupported: Unique constraint on other than static arrays"); + continue; + } + + AstCMethodHard* const wCallp + = new AstCMethodHard{fl, new AstVarRef{fl, modp, genVarp, VAccess::READ}, + VCMethod::RANDOMIZER_WRITE_VAR}; + wCallp->addPinsp(new AstVarRef{fl, varp, VAccess::READ}); + wCallp->addPinsp(new AstConst{fl, AstConst::Unsized64{}, + static_cast(varp->dtypep()->width())}); + wCallp->addPinsp(new AstConst{fl, AstConst::String{}, varp->name()}); + wCallp->addPinsp(new AstConst{fl, 1}); // Dimension + + wCallp->dtypeSetVoid(); + initTaskp->addStmtsp(new AstStmtExpr{fl, wCallp}); + + uint32_t arraySize = 0; + if (AstUnpackArrayDType* const adtypep + = VN_CAST(varp->dtypep(), UnpackArrayDType)) { + arraySize = adtypep->elementsConst(); + } + if (arraySize > 100) { + nodep->v3warn(CONSTRAINTIGN, + "Unsupported: Unique constraint on static arrays of size > 100"); + continue; + } + + AstNodeExpr* const uPins = new AstConst{fl, AstConst::String{}, varp->name()}; + uPins->addNext(new AstConst{fl, arraySize}); + + AstCMethodHard* const uCallp + = new AstCMethodHard{fl, new AstVarRef{fl, modp, genVarp, VAccess::READ}, + VCMethod::RANDOMIZER_UNIQUE, uPins}; + uCallp->dtypep(nodep->findVoidDType()); + initTaskp->addStmtsp(new AstStmtExpr{fl, uCallp}); + } + } + nodep->unlinkFrBack(); + VL_DO_DANGLING(pushDeletep(nodep), nodep); } + void visit(AstConstraintExpr* nodep) override { iterateChildren(nodep); if (m_wantSingle) { @@ -1337,6 +1913,26 @@ class ConstraintExprVisitor final : public VNVisitor { VAccess::READWRITE}, VCMethod::RANDOMIZER_HARD, nodep->exprp()->unlinkFrBack()}; callp->dtypeSetVoid(); + // Pass filename, lineno, and source as separate arguments + // This allows EmitC to call protect() on filename, similar to VL_STOP + // Add filename parameter + callp->addPinsp(new AstCExpr{nodep->fileline(), AstCExpr::Pure{}, + "\"" + nodep->fileline()->filename() + "\""}); + // Add line number parameter + const uint32_t lineno = static_cast(nodep->fileline()->lineno()); + callp->addPinsp(new AstConst{nodep->fileline(), lineno}); + // Add source text parameter (empty if --protect-ids to avoid source leakage) + std::string prettyText; + if (!v3Global.opt.protectIds()) { + prettyText = nodep->fileline()->prettySource(); + size_t pos = 0; + while ((pos = prettyText.find('"', pos)) != std::string::npos) { + prettyText.insert(pos, "\\"); + pos += std::strlen("\\\""); + } + } + callp->addPinsp( + new AstCExpr{nodep->fileline(), AstCExpr::Pure{}, "\"" + prettyText + "\""}); nodep->replaceWith(callp->makeStmt()); VL_DO_DANGLING(nodep->deleteTree(), nodep); } @@ -1365,8 +1961,8 @@ class ConstraintExprVisitor final : public VNVisitor { AstVar* const newVarp = new AstVar{fl, VVarType::BLOCKTEMP, "__Vinside", nodep->findSigned32DType()}; AstNodeExpr* const idxRefp = new AstVarRef{nodep->fileline(), newVarp, VAccess::READ}; - AstSelLoopVars* const arrayp - = new AstSelLoopVars{fl, nodep->fromp()->cloneTreePure(false), newVarp}; + AstForeachHeader* const headerp + = new AstForeachHeader{fl, nodep->fromp()->cloneTreePure(false), newVarp}; AstNodeExpr* const selp = newSel(nodep->fileline(), nodep->fromp(), idxRefp); selp->user1(randArr); AstNode* const itemp = new AstEq{fl, selp, nodep->pinsp()->unlinkFrBack()}; @@ -1380,13 +1976,106 @@ class ConstraintExprVisitor final : public VNVisitor { AstCExpr* const cexprp = new AstCExpr{fl}; cexprp->dtypeSetString(); cexprp->add("([&]{\nstd::string ret;\n"); - cexprp->add(new AstBegin{fl, "", new AstForeach{fl, arrayp, cstmtp}, true}); + cexprp->add(new AstBegin{fl, "", new AstForeach{fl, headerp, cstmtp}, true}); cexprp->add("return ret.empty() ? \"#b0\" : \"(bvor\" + ret + \")\";\n})()"); nodep->replaceWith(new AstSFormatF{fl, "%@", false, cexprp}); VL_DO_DANGLING(nodep->deleteTree(), nodep); return; } + // Array reduction without 'with' clause (sum, product, and, or, xor) + // For dynamic arrays, V3Width keeps these as AstCMethodHard. + // Register each element as individual scalar solver variable at constraint + // setup time, then build SMT reduction expression over those variables. + if (nodep->fromp()->user1() + && (nodep->method() == VCMethod::ARRAY_R_SUM + || nodep->method() == VCMethod::ARRAY_R_PRODUCT + || nodep->method() == VCMethod::ARRAY_R_AND + || nodep->method() == VCMethod::ARRAY_R_OR + || nodep->method() == VCMethod::ARRAY_R_XOR)) { + + AstVarRef* const arrRefp = VN_CAST(nodep->fromp(), VarRef); + UASSERT_OBJ(arrRefp, nodep, "Array reduction in constraint has non-VarRef source"); + AstVar* const arrVarp = arrRefp->varp(); + const std::string smtArrayName = arrVarp->name(); + + // Get element width + AstNodeDType* elemDtp = arrVarp->dtypep()->skipRefp()->subDTypep(); + const int elemWidth = elemDtp->width(); + + // Compute correctly-sized identity value for empty array case + const int hexDigits = (elemWidth + 3) / 4; + std::string zeroIdentity = "#x" + std::string(hexDigits, '0'); + std::string oneIdentity = "#x" + std::string(hexDigits - 1, '0') + "1"; + std::string allOnesIdentity = "#x" + std::string(hexDigits, 'f'); + + // Class module for generating VarRefs + AstNodeModule* const classModulep = m_classp ? static_cast(m_classp) + : VN_AS(m_genp->user2p(), NodeModule); + + // Mark array as handled so BasicRand skips it. Solver controls + // element values via per-element write_var calls in the foreach below. + // Don't generate constructor write_var with dimension>0: dynamic arrays + // are empty at construction, so record_arr_table finds no elements. + arrVarp->user3(true); + + AstVar* const newVarp + = new AstVar{fl, VVarType::BLOCKTEMP, "__Vreduce", nodep->findSigned32DType()}; + AstForeachHeader* const headerp + = new AstForeachHeader{fl, nodep->fromp()->cloneTreePure(false), newVarp}; + + // Foreach body: register element as scalar solver var + append name + AstCStmt* const cstmtp = new AstCStmt{fl}; + // char __Vn[128]; VL_SNPRINTF(__Vn, ..., "arrayname_%x", idx); + cstmtp->add("{\nchar __Vn[128];\nVL_SNPRINTF(__Vn, sizeof(__Vn), \"" + smtArrayName + + "_%x\", (unsigned)"); + cstmtp->add(new AstVarRef{fl, newVarp, VAccess::READ}); + cstmtp->add(");\n"); + // constraint.write_var(array.atWrite(idx), width, __Vn, 0); + cstmtp->add(new AstVarRef{fl, classModulep, m_genp, VAccess::READWRITE}); + cstmtp->add(".write_var("); + cstmtp->add(new AstVarRef{fl, classModulep, arrVarp, VAccess::READWRITE}); + cstmtp->add(".atWrite("); + cstmtp->add(new AstVarRef{fl, newVarp, VAccess::READ}); + cstmtp->add("), " + std::to_string(elemWidth) + "ULL, __Vn, 0ULL);\n"); + // ret += " "; ret += __Vn; + cstmtp->add("ret += \" \";\nret += __Vn;\n}\n"); + + AstCExpr* const cexprp = new AstCExpr{fl}; + cexprp->dtypeSetString(); + cexprp->add("([&]{\nstd::string ret;\n"); + cexprp->add(new AstBegin{fl, "", new AstForeach{fl, headerp, cstmtp}, true}); + + const char* smtOp = nullptr; + std::string identity; + if (nodep->method() == VCMethod::ARRAY_R_SUM) { + smtOp = "bvadd"; + identity = zeroIdentity; + } else if (nodep->method() == VCMethod::ARRAY_R_PRODUCT) { + smtOp = "bvmul"; + identity = oneIdentity; + } else if (nodep->method() == VCMethod::ARRAY_R_AND) { + smtOp = "bvand"; + identity = allOnesIdentity; + } else if (nodep->method() == VCMethod::ARRAY_R_OR) { + smtOp = "bvor"; + identity = zeroIdentity; + } else if (nodep->method() == VCMethod::ARRAY_R_XOR) { + smtOp = "bvxor"; + identity = zeroIdentity; + } else { + nodep->v3fatalSrc("Unhandled reduction method"); + } + + cexprp->add(std::string("return ret.empty() ? \"") + identity + "\" : \"(" + smtOp + + "\" + ret + \")\";\n})()"); + // Unlink fromp before replacing (newSel already unlinked it in v1, + // but here we used cloneTreePure, so fromp is still linked) + nodep->replaceWith(new AstSFormatF{fl, "%@", false, cexprp}); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + return; + } + nodep->v3warn(CONSTRAINTIGN, "Unsupported: randomizing this expression, treating as state"); nodep->user1(false); @@ -1394,6 +2083,50 @@ class ConstraintExprVisitor final : public VNVisitor { if (editFormat(nodep)) return; nodep->v3fatalSrc("Method not handled in constraints? " << nodep); } + void visit(AstNodeFTaskRef* nodep) override { + if (editFormat(nodep)) return; + + AstFunc* const funcp = VN_CAST(nodep->taskp(), Func); + if (!funcp) { + // Tasks have no return value and can't appear in expressions. + // Parser rejects this, so reaching here indicates a compiler bug. + nodep->v3fatalSrc("Unexpected task call in constraint expression"); + return; + } + + AstNodeExpr* const retExprp = extractReturnExpr(funcp); + if (!retExprp) { + nodep->v3warn(CONSTRAINTIGN, + "Unsupported: complex function in constraint, treating as state"); + nodep->user1(false); + if (editFormat(nodep)) return; + return; + } + + // Map formal parameters to actual arguments using V3Task infrastructure + const V3TaskConnects tconnects + = V3Task::taskConnects(nodep, funcp->stmtsp(), nullptr, false); + + // Clone return expression, substitute params with args + AstNodeExpr* const inlinedp = retExprp->cloneTreePure(false); + for (const auto& tconnect : tconnects) { + const AstVar* const portp = tconnect.first; + AstArg* const argp = tconnect.second; + if (!argp || !argp->exprp()) continue; + inlinedp->foreach([&](AstVarRef* refp) { + if (refp->varp() == portp) { + refp->replaceWith(argp->exprp()->cloneTreePure(false)); + VL_DO_DANGLING(refp->deleteTree(), refp); + } + }); + } + + inlinedp->dtypep(nodep->dtypep()); + propagateUser1InlineRecurse(inlinedp); + nodep->replaceWith(inlinedp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + iterate(inlinedp); + } void visit(AstNodeExpr* nodep) override { if (editFormat(nodep)) return; nodep->v3fatalSrc( @@ -1406,10 +2139,11 @@ class ConstraintExprVisitor final : public VNVisitor { public: // CONSTRUCTORS - explicit ConstraintExprVisitor(VMemberMap& memberMap, AstNode* nodep, + explicit ConstraintExprVisitor(AstClass* classp, VMemberMap& memberMap, AstNode* nodep, AstNodeFTask* inlineInitTaskp, AstVar* genp, AstVar* randModeVarp, std::set& writtenVars) - : m_inlineInitTaskp{inlineInitTaskp} + : m_classp{classp} + , m_inlineInitTaskp{inlineInitTaskp} , m_genp{genp} , m_randModeVarp{randModeVarp} , m_memberMap{memberMap} @@ -1508,7 +2242,7 @@ class CaptureVisitor final : public VNVisitor { const bool varIsFieldOfCaller = AstClass::isClassExtendedFrom(callerClassp, varClassp); const bool varIsParam = varRefp->varp()->isParam(); const bool varIsConstraintIterator - = VN_IS(varRefp->varp()->firstAbovep(), SelLoopVars) + = VN_IS(varRefp->varp()->firstAbovep(), ForeachHeader) && VN_IS(varRefp->varp()->firstAbovep()->firstAbovep(), ConstraintForeach); if (refIsXref) return CaptureMode::CAP_VALUE | CaptureMode::CAP_F_XREF; if (varIsConstraintIterator) return CaptureMode::CAP_NO; @@ -1584,14 +2318,14 @@ class CaptureVisitor final : public VNVisitor { } AstClass* classp = VN_CAST(nodep->taskp()->user2p(), Class); if ((classp == m_callerp) && VN_IS(m_callerp, Class)) { - AstNodeExpr* const pinsp = nodep->pinsp(); - if (pinsp) pinsp->unlinkFrBack(); + AstArg* const argsp = nodep->argsp(); + if (argsp) argsp->unlinkFrBack(); // TODO: should this be unlinkFrBackWithNext? AstVar* const thisp = importThisp(nodep->fileline()); AstVarRef* const thisRefp = new AstVarRef{ nodep->fileline(), thisp, nodep->isPure() ? VAccess::READ : VAccess::READWRITE}; m_ignore.emplace(thisRefp); AstMethodCall* const methodCallp - = new AstMethodCall{nodep->fileline(), thisRefp, thisp->name(), pinsp}; + = new AstMethodCall{nodep->fileline(), thisRefp, thisp->name(), argsp}; methodCallp->taskp(nodep->taskp()); methodCallp->dtypep(nodep->dtypep()); nodep->replaceWith(methodCallp); @@ -1617,14 +2351,16 @@ class CaptureVisitor final : public VNVisitor { iterateChildren(nodep); return; } - AstNodeExpr* const pinsp - = nodep->pinsp() ? nodep->pinsp()->unlinkFrBackWithNext() : nullptr; + AstArg* const argsp = nodep->argsp(); + if (argsp) argsp->unlinkFrBackWithNext(); AstNodeFTaskRef* taskRefp = nullptr; - if (AstTask* const taskp = VN_CAST(nodep->taskp(), Task)) - taskRefp = new AstTaskRef{nodep->fileline(), taskp, pinsp}; - else if (AstFunc* const taskp = VN_CAST(nodep->taskp(), Func)) - taskRefp = new AstFuncRef{nodep->fileline(), taskp, pinsp}; - UASSERT_OBJ(taskRefp, nodep, "Node needs to point to regular method"); + if (AstTask* const taskp = VN_CAST(nodep->taskp(), Task)) { + taskRefp = new AstTaskRef{nodep->fileline(), taskp, argsp}; + } else if (AstFunc* const taskp = VN_CAST(nodep->taskp(), Func)) { + taskRefp = new AstFuncRef{nodep->fileline(), taskp, argsp}; + } else { + nodep->v3fatalSrc("Node needs to point to regular method"); + } fixupClassOrPackage(nodep->taskp(), taskRefp); taskRefp->user1(nodep->user1()); nodep->replaceWith(taskRefp); @@ -1700,6 +2436,8 @@ class RandomizeVisitor final : public VNVisitor { std::map m_randcDtypes; // RandC data type deduplication AstConstraint* m_constraintp = nullptr; // Current constraint std::set m_writtenVars; // Track write_var calls per class to avoid duplicates + std::map + m_staticConstraintModeVars; // Static constraint mode vars per class // METHODS // Check if two nodes are semantically equivalent (not pointer equality): @@ -1729,6 +2467,50 @@ class RandomizeVisitor final : public VNVisitor { } return false; } + // Expand unique{a,b,c} with explicit elements into pairwise != constraints. + // Whole-array unique{arr} is left for ConstraintExprVisitor's rand_unique handling. + static void expandUniqueElementList(AstNode* itemsp) { + AstNode* itemp = itemsp; + while (itemp) { + AstNode* const nextp = itemp->nextp(); + AstConstraintUnique* const uniquep = VN_CAST(itemp, ConstraintUnique); + if (!uniquep) { + itemp = nextp; + continue; + } + + std::vector exprItems; + bool hasArrayVarRef = false; + for (AstNode* rp = uniquep->rangesp(); rp; rp = rp->nextp()) { + if (AstVarRef* const vrp = VN_CAST(rp, VarRef)) { + if (VN_IS(vrp->varp()->dtypep()->skipRefp(), UnpackArrayDType)) { + hasArrayVarRef = true; + continue; + } + } + exprItems.push_back(VN_AS(rp, NodeExpr)); + } + + if (exprItems.size() >= 2) { + FileLine* const fl = uniquep->fileline(); + for (size_t i = 0; i < exprItems.size(); i++) { + for (size_t j = i + 1; j < exprItems.size(); j++) { + AstNodeExpr* const lhsp = exprItems[i]->cloneTree(false); + AstNodeExpr* const rhsp = exprItems[j]->cloneTree(false); + AstNeq* const neqp = new AstNeq{fl, lhsp, rhsp}; + neqp->user1(true); + AstConstraintExpr* const cexprp = new AstConstraintExpr{fl, neqp}; + uniquep->addNextHere(cexprp); + } + } + if (!hasArrayVarRef) { + uniquep->unlinkFrBack(); + VL_DO_DANGLING(uniquep->deleteTree(), uniquep); + } + } + itemp = nextp; + } + } void createRandomGenerator(AstClass* const classp) { if (classp->user3p()) return; if (classp->extendsp()) { @@ -1813,6 +2595,24 @@ class RandomizeVisitor final : public VNVisitor { } return nullptr; } + AstVar* getCreateStaticConstraintModeVar(AstClass* const classp) { + auto it = m_staticConstraintModeVars.find(classp); + if (it != m_staticConstraintModeVars.end()) return it->second; + if (AstClassExtends* const extendsp = classp->extendsp()) { + return getCreateStaticConstraintModeVar(extendsp->classp()); + } + AstVar* const staticModeVarp = createStaticModeVar(classp, "__Vstaticconstraintmode"); + m_staticConstraintModeVars[classp] = staticModeVarp; + return staticModeVarp; + } + AstVar* getStaticConstraintModeVar(AstClass* const classp) { + auto it = m_staticConstraintModeVars.find(classp); + if (it != m_staticConstraintModeVars.end()) return it->second; + if (AstClassExtends* const extendsp = classp->extendsp()) { + return getStaticConstraintModeVar(extendsp->classp()); + } + return nullptr; + } AstVar* createModeVar(AstClass* const classp, const char* const name) { FileLine* const fl = classp->fileline(); if (!m_dynarrayDtp) { @@ -1826,6 +2626,24 @@ class RandomizeVisitor final : public VNVisitor { classp->addStmtsp(modeVarp); return modeVarp; } + AstVar* createStaticModeVar(AstClass* const classp, const char* const name) { + // Create a static variable that will be shared across all instances. + // By setting lifetime to STATIC_EXPLICIT, V3Class will move this to the class package. + FileLine* const fl = classp->fileline(); + if (!m_dynarrayDtp) { + m_dynarrayDtp = new AstDynArrayDType{ + fl, v3Global.rootp()->typeTablep()->findBitDType()->dtypep()}; + m_dynarrayDtp->dtypep(m_dynarrayDtp); + v3Global.rootp()->typeTablep()->addTypesp(m_dynarrayDtp); + } + AstVar* const modeVarp = new AstVar{fl, VVarType::MODULETEMP, name, m_dynarrayDtp}; + modeVarp->lifetime(VLifetime::STATIC_EXPLICIT); + // Note: user2p is set to classp here. V3Scope will later update varScopep + // to point to the package scope when the variable is moved by V3Class. + modeVarp->user2p(classp); + classp->addStmtsp(modeVarp); + return modeVarp; + } static void addSetRandMode(AstNodeFTask* const ftaskp, AstVar* const genp, AstVar* const randModeVarp) { FileLine* const fl = ftaskp->fileline(); @@ -1842,18 +2660,28 @@ class RandomizeVisitor final : public VNVisitor { bool hasConstraints = false; uint32_t randModeCount = 0; uint32_t constraintModeCount = 0; + uint32_t staticConstraintModeCount = 0; classp->foreachMember([&](AstClass*, AstNode* memberp) { // SystemVerilog only allows single inheritance, so we don't need to worry about // index overlap. If the index > 0, it's already been set. - if (VN_IS(memberp, Constraint)) { + if (AstConstraint* const constrp = VN_CAST(memberp, Constraint)) { hasConstraints = true; RandomizeMode constraintMode = {.asInt = memberp->user1()}; if (!constraintMode.usesMode) return; if (constraintMode.index == 0) { - constraintMode.index = constraintModeCount++; + // Use separate index counters for static vs non-static constraints + if (constrp->isStatic()) { + constraintMode.index = staticConstraintModeCount++; + } else { + constraintMode.index = constraintModeCount++; + } memberp->user1(constraintMode.asInt); } else { - constraintModeCount = constraintMode.index + 1; + if (constrp->isStatic()) { + staticConstraintModeCount = constraintMode.index + 1; + } else { + constraintModeCount = constraintMode.index + 1; + } } } else if (VN_IS(memberp, Var)) { RandomizeMode randMode = {.asInt = memberp->user1()}; @@ -1875,6 +2703,10 @@ class RandomizeVisitor final : public VNVisitor { AstVar* const constraintModeVarp = getCreateConstraintModeVar(classp); makeModeInit(constraintModeVarp, classp, constraintModeCount); } + if (staticConstraintModeCount > 0) { + AstVar* const staticConstraintModeVarp = getCreateStaticConstraintModeVar(classp); + makeStaticModeInit(staticConstraintModeVarp, classp, staticConstraintModeCount); + } }); } void makeModeInit(AstVar* modeVarp, AstClass* classp, uint32_t modeCount) { @@ -1884,12 +2716,59 @@ class RandomizeVisitor final : public VNVisitor { = new AstCMethodHard{fl, new AstVarRef{fl, modeVarModp, modeVarp, VAccess::WRITE}, VCMethod::DYN_RESIZE, new AstConst{fl, modeCount}}; dynarrayNewp->dtypeSetVoid(); + AstNodeFTask* const ctorNewp = VN_AS(m_memberMap.findMember(classp, "new"), NodeFTask); + UASSERT_OBJ(ctorNewp, classp, "No new() in class"); + // Build init chain: resize -> set-all-to-1 loop + AstNode* const initFirstp = dynarrayNewp->makeStmt(); + initFirstp->addNext( + makeModeSetLoop(fl, new AstVarRef{fl, modeVarModp, modeVarp, VAccess::WRITE}, + new AstConst{fl, 1}, true)); + // Prepend init code before user statements in constructor body, but after + // var declarations and super.new(). This ensures that user's constraint_mode() + // or rand_mode() calls in the constructor execute after mode arrays are initialized. + // Pattern from V3LinkDot::addImplicitSuperNewCall. + for (AstNode* stmtp = ctorNewp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + if (!VN_IS(stmtp, NodeStmt)) continue; // Skip var declarations + if (const AstStmtExpr* const sep = VN_CAST(stmtp, StmtExpr)) { + if (VN_IS(sep->exprp(), New)) continue; // Skip super.new() + } + // Found first user statement - insert init code before it + stmtp->addHereThisAsNext(initFirstp); + return; + } + // No user statements (empty constructor or only var decls/super.new) + ctorNewp->addStmtsp(initFirstp); + } + void makeStaticModeInit(AstVar* modeVarp, AstClass* classp, uint32_t modeCount) { + // For static constraint mode, we need lazy initialization since it's shared across + // instances. Generate: if (size() == 0) { resize(N); set all to 1; } + AstNodeModule* const modeVarModp = VN_AS(modeVarp->user2p(), NodeModule); + FileLine* fl = modeVarp->fileline(); + + // Build the condition: size() == 0 + AstCMethodHard* const sizep + = new AstCMethodHard{fl, new AstVarRef{fl, modeVarModp, modeVarp, VAccess::READ}, + VCMethod::DYN_SIZE, nullptr}; + sizep->dtypeSetUInt32(); + AstEq* const condp = new AstEq{fl, sizep, new AstConst{fl, 0}}; + + // Build the then-block: resize and set all to 1 + AstCMethodHard* const dynarrayNewp + = new AstCMethodHard{fl, new AstVarRef{fl, modeVarModp, modeVarp, VAccess::WRITE}, + VCMethod::DYN_RESIZE, new AstConst{fl, modeCount}}; + dynarrayNewp->dtypeSetVoid(); + AstNode* const thenStmtsp = dynarrayNewp->makeStmt(); + thenStmtsp->addNext( + makeModeSetLoop(fl, new AstVarRef{fl, modeVarModp, modeVarp, VAccess::WRITE}, + new AstConst{fl, 1}, true)); + + // Build the if statement + AstIf* const ifp = new AstIf{fl, condp, thenStmtsp}; + + // Add to new() constructor AstNodeFTask* const newp = VN_AS(m_memberMap.findMember(classp, "new"), NodeFTask); UASSERT_OBJ(newp, classp, "No new() in class"); - newp->addStmtsp(dynarrayNewp->makeStmt()); - newp->addStmtsp(makeModeSetLoop(fl, - new AstVarRef{fl, modeVarModp, modeVarp, VAccess::WRITE}, - new AstConst{fl, 1}, true)); + newp->addStmtsp(ifp); } static AstNode* makeModeSetLoop(FileLine* const fl, AstNodeExpr* const lhsp, AstNodeExpr* const rhsp, bool inTask) { @@ -1920,17 +2799,20 @@ class RandomizeVisitor final : public VNVisitor { const RandomizeMode rmode = {.asInt = varp->user1()}; return VN_AS(wrapIfMode(rmode, getRandModeVar(classp), stmtp), NodeStmt); } - static AstNode* wrapIfConstraintMode(AstClass* classp, AstConstraint* const constrp, - AstNode* stmtp) { + AstNode* wrapIfConstraintMode(AstClass* classp, AstConstraint* const constrp, AstNode* stmtp) { const RandomizeMode rmode = {.asInt = constrp->user1()}; - return wrapIfMode(rmode, getConstraintModeVar(classp), stmtp); + AstVar* const modeVarp = constrp->isStatic() ? getStaticConstraintModeVar(classp) + : getConstraintModeVar(classp); + return wrapIfMode(rmode, modeVarp, stmtp); } static AstNode* wrapIfMode(const RandomizeMode mode, AstVar* modeVarp, AstNode* stmtp) { FileLine* const fl = stmtp->fileline(); if (mode.usesMode) { - AstCMethodHard* const atp = new AstCMethodHard{ - fl, new AstVarRef{fl, VN_AS(modeVarp->user2p(), Class), modeVarp, VAccess::READ}, - VCMethod::ARRAY_AT, new AstConst{fl, mode.index}}; + // user2p can be either AstClass or AstClassPackage (for static constraints) + AstNodeModule* const modp = VN_AS(modeVarp->user2p(), NodeModule); + AstCMethodHard* const atp + = new AstCMethodHard{fl, new AstVarRef{fl, modp, modeVarp, VAccess::READ}, + VCMethod::ARRAY_AT, new AstConst{fl, mode.index}}; atp->dtypeSetUInt32(); return new AstIf{fl, atp, stmtp}; } @@ -2056,12 +2938,12 @@ class RandomizeVisitor final : public VNVisitor { tempDTypep = tempDTypep->virtRefDTypep(); } - AstSelLoopVars* const randLoopVarp - = new AstSelLoopVars{fl, exprp->cloneTree(false), randLoopIndxp}; + AstForeachHeader* const headerp + = new AstForeachHeader{fl, exprp->cloneTree(false), randLoopIndxp}; AstNodeStmt* const randStmtsp = newRandStmtsp(fl, tempElementp, nullptr, outputVarp); // TODO: we should just not clone in 'newRandStmtsp' if not necessary if (!tempElementp->backp()) VL_DO_DANGLING(pushDeletep(tempElementp), tempElementp); - return new AstForeach{fl, randLoopVarp, randStmtsp}; + return new AstForeach{fl, headerp, randStmtsp}; } AstNodeStmt* newRandStmtsp(FileLine* fl, AstNodeExpr* exprp, AstVar* randcVarp, AstVar* const outputVarp, int offset = 0, @@ -2084,7 +2966,7 @@ class RandomizeVisitor final : public VNVisitor { if (!structSelp->dtypep()) structSelp->dtypep(smemberp->subDTypep()); randp = newRandStmtsp(fl, structSelp, nullptr, outputVarp); } - stmtsp = stmtsp ? stmtsp->addNext(randp) : randp; + stmtsp = AstNode::addNextNull(stmtsp, randp); } return stmtsp; } else if (const auto* const unionDtp = VN_CAST(memberDtp, UnionDType)) { @@ -2098,7 +2980,7 @@ class RandomizeVisitor final : public VNVisitor { } else if (const AstClassRefDType* const classRefDtp = VN_CAST(memberDtp, ClassRefDType)) { AstFunc* const memberFuncp = V3Randomize::newRandomizeFunc(m_memberMap, classRefDtp->classp()); - AstMethodCall* const callp = new AstMethodCall{fl, exprp, "randomize", nullptr}; + AstMethodCall* const callp = new AstMethodCall{fl, exprp, "randomize"}; callp->taskp(memberFuncp); callp->dtypeFrom(memberFuncp); AstAssign* const assignp = new AstAssign{ @@ -2159,12 +3041,94 @@ class RandomizeVisitor final : public VNVisitor { return new AstRandRNG{fl, dtypep}; } + // Find pre_randomize/post_randomize task in class hierarchy (walks extendsp chain) + AstTask* findPrePostTask(AstClass* classp, const string& name) { + for (AstClass* cp = classp; cp; cp = cp->extendsp() ? cp->extendsp()->classp() : nullptr) { + if (AstTask* const taskp = VN_CAST(m_memberMap.findMember(cp, name), Task)) { + return taskp; + } + } + return nullptr; + } void addPrePostCall(AstClass* const classp, AstFunc* const funcp, const string& name) { - if (AstTask* userFuncp = VN_CAST(m_memberMap.findMember(classp, name), Task)) { - AstTaskRef* const callp = new AstTaskRef{userFuncp->fileline(), userFuncp, nullptr}; + if (AstTask* const userFuncp = findPrePostTask(classp, name)) { + AstTaskRef* const callp = new AstTaskRef{userFuncp->fileline(), userFuncp}; funcp->addStmtsp(callp->makeStmt()); } } + // Check if a class (including inherited members) has any rand class-type members + bool classHasRandClassMembers(AstClass* classp) { + return classp->existsMember([](const AstClass*, const AstVar* varp) { + if (!varp->rand().isRandomizable()) return false; + const AstNodeDType* const dtypep = varp->dtypep()->skipRefp(); + return VN_IS(dtypep, ClassRefDType); + }); + } + // Get or create __VrandCb_pre/__VrandCb_post task for nested callbacks + AstTask* getCreateNestedCallbackTask(AstClass* classp, const string& suffix) { + const string name = "__VrandCb_" + suffix; + AstTask* taskp = VN_CAST(m_memberMap.findMember(classp, name), Task); + if (taskp) return taskp; + taskp = new AstTask{classp->fileline(), name, nullptr}; + taskp->classMethod(true); + classp->addMembersp(taskp); + m_memberMap.insert(classp, taskp); + return taskp; + } + // Populate nested callback task body: calls pre/post_randomize on nested rand class members + void populateNestedCallbackTask(AstTask* const callbackTaskp, AstClass* const classp, + const string& cbName) { + FileLine* const fl = classp->fileline(); + classp->foreachMember([&](AstClass* ownerClassp, AstVar* memberVarp) { + if (!memberVarp->rand().isRandomizable()) return; + const AstNodeDType* const dtypep = memberVarp->dtypep()->skipRefp(); + const AstClassRefDType* const classRefp = VN_CAST(dtypep, ClassRefDType); + if (!classRefp) return; + AstClass* const memberClassp = classRefp->classp(); + if (memberClassp == classp) return; // Avoid self-reference + + // Force-visit member class if not yet processed + if (memberClassp->user1()) { + iterate(memberClassp); + m_writtenVars.clear(); + } + + AstNode* stmtsp = nullptr; + + // 1. Call member.pre/post_randomize() if exists in hierarchy + if (AstTask* const userFuncp = findPrePostTask(memberClassp, cbName)) { + AstMethodCall* const callp = new AstMethodCall{ + fl, new AstVarRef{fl, ownerClassp, memberVarp, VAccess::WRITE}, cbName}; + callp->taskp(userFuncp); + callp->dtypeSetVoid(); + stmtsp = AstNode::addNext(stmtsp, callp->makeStmt()); + } + + // 2. Call member.__VrandCb_pre/post() for deeper recursion + if (classHasRandClassMembers(memberClassp)) { + const string suffix = (cbName == "pre_randomize") ? "pre" : "post"; + AstTask* const nestedTaskp = getCreateNestedCallbackTask(memberClassp, suffix); + AstMethodCall* const recurseCallp = new AstMethodCall{ + fl, new AstVarRef{fl, ownerClassp, memberVarp, VAccess::WRITE}, + nestedTaskp->name()}; + recurseCallp->taskp(nestedTaskp); + recurseCallp->dtypeSetVoid(); + stmtsp = AstNode::addNext(stmtsp, recurseCallp->makeStmt()); + } + + if (!stmtsp) return; + + // Wrap in null check + AstIf* const nullCheckp = new AstIf{ + fl, + new AstNeq{fl, new AstVarRef{fl, ownerClassp, memberVarp, VAccess::READ}, + new AstConst{fl, AstConst::Null{}}}, + stmtsp}; + + // Wrap in rand_mode check + callbackTaskp->addStmtsp(wrapIfRandMode(classp, memberVarp, nullCheckp)); + }); + } AstTask* newSetupConstraintTask(AstClass* const nodep, const std::string& name) { AstTask* const taskp = new AstTask{nodep->fileline(), name + "_setup_constraint", nullptr}; taskp->classMethod(true); @@ -2206,10 +3170,11 @@ class RandomizeVisitor final : public VNVisitor { AstNodeExpr* makeSiblingRefp(AstNodeExpr* const exprp, AstVar* const varp, const VAccess access) { if (AstMemberSel* const memberSelp = VN_CAST(exprp, MemberSel)) { - // TODO: this ignored 'access' and will create a read reference in - // t_randomize_inline_var_ctl, see issue #6756 - return new AstMemberSel{exprp->fileline(), memberSelp->fromp()->cloneTree(false), - varp}; + AstMemberSel* const newMemberSelp + = new AstMemberSel{exprp->fileline(), memberSelp->fromp()->cloneTree(false), varp}; + // Set access on all VarRef nodes in the cloned subtree + newMemberSelp->foreach([access](AstVarRef* varrefp) { varrefp->access(access); }); + return newMemberSelp; } UASSERT_OBJ(VN_IS(exprp, VarRef), exprp, "Should be a VarRef"); return new AstVarRef{exprp->fileline(), VN_AS(varp->user2p(), Class), varp, access}; @@ -2328,10 +3293,10 @@ class RandomizeVisitor final : public VNVisitor { ? new AstMethodCall{fl, new AstVarRef{fl, classp, memberVarp, VAccess::WRITE}, - BASIC_RANDOMIZE_FUNC_NAME, nullptr} + BASIC_RANDOMIZE_FUNC_NAME} : new AstMethodCall{ fl, new AstVarRef{fl, classp, memberVarp, VAccess::WRITE}, - "randomize", nullptr}; + "randomize"}; callp->taskp(memberFuncp); callp->dtypeFrom(memberFuncp); AstVarRef* const basicFvarRefReadp = basicFvarRefp->cloneTree(false); @@ -2357,7 +3322,15 @@ class RandomizeVisitor final : public VNVisitor { // Creates a lvalue reference to the randomize mode var. Called by visit(AstNodeFTaskRef*) AstNodeExpr* makeModeAssignLhs(FileLine* const fl, AstClass* const classp, AstNodeExpr* const fromp, AstVar* const modeVarp) { - if (classp == m_modp) { + // For static constraint mode vars, always use VarRef (not MemberSel). + // At this point V3Class hasn't run yet, so user2p may be nullptr. + // Generate VarRef with classp as module; V3Scope will update varScopep later + // when the variable is moved to the class package. + if (modeVarp->lifetime().isStatic()) { + // Static mode var - generate VarRef that will be resolved by V3Scope + if (fromp) VL_DO_DANGLING(fromp->unlinkFrBack()->deleteTree(), fromp); + return new AstVarRef{fl, classp, modeVarp, VAccess::WRITE}; + } else if (classp == m_modp) { // Called on 'this' or a member of 'this' return new AstVarRef{fl, VN_AS(modeVarp->user2p(), NodeModule), modeVarp, VAccess::WRITE}; @@ -2371,9 +3344,9 @@ class RandomizeVisitor final : public VNVisitor { void replaceWithModeAssign(AstNodeFTaskRef* const ftaskRefp, AstNode* const receiverp, AstNodeExpr* const lhsp) { FileLine* const fl = ftaskRefp->fileline(); - if (ftaskRefp->pinsp()) { + if (ftaskRefp->argsp()) { UASSERT_OBJ(VN_IS(ftaskRefp->backp(), StmtExpr), ftaskRefp, "Should be a statement"); - AstNodeExpr* const rhsp = VN_AS(ftaskRefp->pinsp(), Arg)->exprp()->unlinkFrBack(); + AstNodeExpr* const rhsp = ftaskRefp->argsp()->exprp()->unlinkFrBack(); if (receiverp) { // Called on a rand member variable/constraint. Set the variable/constraint's // mode @@ -2402,35 +3375,49 @@ class RandomizeVisitor final : public VNVisitor { } }; + // Wrap obj.randomize() with null guard: (obj != null) ? obj.randomize() : 0 + // IEEE 1800 requires randomize() on null handle to return 0. + // Uses user4() to prevent re-wrapping during iterateChildren. + void wrapRandomizeCallWithNullGuard(AstNodeFTaskRef* nodep) { + AstMethodCall* const callp = VN_CAST(nodep, MethodCall); + if (!callp) return; + if (callp->user4()) return; + callp->user4(true); + FileLine* const fl = callp->fileline(); + AstNodeExpr* const checkp + = new AstNeq{fl, callp->fromp()->cloneTree(false), new AstConst{fl, AstConst::Null{}}}; + VNRelinker relinker; + callp->unlinkFrBack(&relinker); + AstCond* const condp = new AstCond{fl, checkp, callp, new AstConst{fl, 0}}; + condp->dtypeFrom(callp); + relinker.relink(condp); + } + // Handle inline random variable control. After this, the randomize() call has no args void handleRandomizeArgs(AstNodeFTaskRef* const nodep) { - if (!nodep->pinsp()) return; + if (!nodep->argsp()) return; // This assumes arguments to always be a member sel from nodep->fromp(), if applicable // e.g. LinkDot transformed a.randomize(b, a.c) -> a.randomize(a.b, a.c) // Merge pins with common prefixes so that setting their rand mode doesn't interfere // with each other. // e.g. a.randomize(a.b, a.c, a.b.d) -> a.randomize(a.b, a.c) - for (AstNode *pinp = nodep->pinsp(), *nextp = nullptr; pinp; pinp = nextp) { - nextp = pinp->nextp(); - AstArg* const argp = VN_CAST(pinp, Arg); - if (!argp) continue; - AstNode* otherNextp = nullptr; - for (AstNode* otherPinp = nextp; otherPinp; otherPinp = otherNextp) { - otherNextp = otherPinp->nextp(); - AstArg* const otherArgp = VN_CAST(otherPinp, Arg); - if (!otherArgp) continue; + for (AstArg *argp = nodep->argsp(), *nextp = nullptr; argp; argp = nextp) { + nextp = VN_AS(argp->nextp(), Arg); + for (AstArg *otherArgp = nextp, *otherNextp = nullptr; otherArgp; + otherArgp = otherNextp) { + otherNextp = VN_AS(otherArgp->nextp(), Arg); if (AstNodeExpr* const prefixp = sliceToCommonPrefix(argp->exprp(), otherArgp->exprp())) { if (prefixp == argp->exprp()) { - if (nextp == otherPinp) nextp = nextp->nextp(); - VL_DO_DANGLING(otherPinp->unlinkFrBack()->deleteTree(), otherPinp); + if (nextp == otherArgp) nextp = VN_AS(nextp->nextp(), Arg); + VL_DO_DANGLING(otherArgp->unlinkFrBack()->deleteTree(), otherArgp); continue; } } if (AstNodeExpr* const prefixp = sliceToCommonPrefix(otherArgp->exprp(), argp->exprp())) { if (prefixp == otherArgp->exprp()) { - VL_DO_DANGLING(pinp->unlinkFrBack()->deleteTree(), pinp); + VL_DO_DANGLING(argp->unlinkFrBack()->deleteTree(), argp); break; } } @@ -2442,11 +3429,9 @@ class RandomizeVisitor final : public VNVisitor { AstNode* storeStmtsp = nullptr; AstNode* setStmtsp = nullptr; AstNodeStmt* restoreStmtsp = nullptr; - for (AstNode *pinp = nodep->pinsp(), *nextp = nullptr; pinp; pinp = nextp) { - nextp = pinp->nextp(); - AstArg* const argp = VN_CAST(pinp, Arg); - if (!argp) continue; - AstNodeExpr* exprp = VN_AS(pinp, Arg)->exprp(); + for (AstArg *argp = nodep->argsp(), *nextp = nullptr; argp; argp = nextp) { + nextp = VN_AS(argp->nextp(), Arg); + AstNodeExpr* exprp = argp->exprp(); AstNodeExpr* const commonPrefixp = sliceToCommonPrefix(exprp, nodep); UASSERT_OBJ(commonPrefixp != exprp, nodep, "Common prefix should be different than pin"); @@ -2471,7 +3456,7 @@ class RandomizeVisitor final : public VNVisitor { = AstNode::addNext(setStmtsp, new AstAssign{fl, setp, new AstConst{fl, 1}}); exprp = getFromp(exprp); } - pinp->unlinkFrBack()->deleteTree(); + argp->unlinkFrBack()->deleteTree(); } if (tmpVarps) { UASSERT_OBJ(storeStmtsp && setStmtsp && restoreStmtsp, nodep, "Should have stmts"); @@ -2517,6 +3502,13 @@ class RandomizeVisitor final : public VNVisitor { AstVar* const randModeVarp = getRandModeVar(nodep); addPrePostCall(nodep, randomizep, "pre_randomize"); + // Call nested pre_randomize on rand class-type members (IEEE 18.4.1) + if (classHasRandClassMembers(nodep)) { + AstTask* const preTaskp = getCreateNestedCallbackTask(nodep, "pre"); + populateNestedCallbackTask(preTaskp, nodep, "pre_randomize"); + randomizep->addStmtsp((new AstTaskRef{fl, preTaskp})->makeStmt()); + } + // Both IS_RANDOMIZED and IS_RANDOMIZED_GLOBAL classes need full constraint support // IS_RANDOMIZED_GLOBAL classes can be randomized independently AstNodeExpr* beginValp = nullptr; @@ -2528,8 +3520,7 @@ class RandomizeVisitor final : public VNVisitor { taskp = newSetupConstraintTask(classp, constrp->name()); constrp->user2p(taskp); } - AstTaskRef* const setupTaskRefp - = new AstTaskRef{constrp->fileline(), taskp, nullptr}; + AstTaskRef* const setupTaskRefp = new AstTaskRef{constrp->fileline(), taskp}; setupTaskRefp->classOrPackagep(classp); AstTask* const setupAllTaskp = getCreateConstraintSetupFunc(nodep); @@ -2539,13 +3530,14 @@ class RandomizeVisitor final : public VNVisitor { if (AstTask* const resizeTaskp = VN_CAST(constrp->user3p(), Task)) { AstTask* const resizeAllTaskp = getCreateAggrResizeTask(nodep); AstTaskRef* const resizeTaskRefp - = new AstTaskRef{constrp->fileline(), resizeTaskp, nullptr}; + = new AstTaskRef{constrp->fileline(), resizeTaskp}; resizeTaskRefp->classOrPackagep(classp); resizeAllTaskp->addStmtsp(resizeTaskRefp->makeStmt()); } - ConstraintExprVisitor{m_memberMap, constrp->itemsp(), nullptr, - genp, randModeVarp, m_writtenVars}; + if (constrp->itemsp()) expandUniqueElementList(constrp->itemsp()); + ConstraintExprVisitor{classp, m_memberMap, constrp->itemsp(), nullptr, + genp, randModeVarp, m_writtenVars}; if (constrp->itemsp()) { taskp->addStmtsp(wrapIfConstraintMode( nodep, constrp, constrp->itemsp()->unlinkFrBackWithNext())); @@ -2563,7 +3555,8 @@ class RandomizeVisitor final : public VNVisitor { stmtp = stmtp->nextp()) { bool foundClearConstraints = false; stmtp->foreach([&](AstCMethodHard* methodp) { - if (methodp->method() == VCMethod::RANDOMIZER_WRITE_VAR) { + if (methodp->method() == VCMethod::RANDOMIZER_WRITE_VAR + || methodp->method() == VCMethod::RANDOMIZER_MARK_RANDC) { randomizep->addStmtsp(stmtp->cloneTree(false)); } else if (methodp->method() == VCMethod::RANDOMIZER_CLEARCONSTRAINTS) { @@ -2578,8 +3571,36 @@ class RandomizeVisitor final : public VNVisitor { } } randomizep->addStmtsp(implementConstraintsClear(fl, genp)); + + // Restrict enum variables in solver to valid members only + { + AstNodeModule* const genModp = VN_AS(genp->user2p(), NodeModule); + nodep->foreachMember([&](AstClass*, AstVar* memberVarp) { + if (!memberVarp->user3()) return; + AstEnumDType* const enumDtp + = VN_CAST(memberVarp->dtypep()->skipRefToEnump(), EnumDType); + if (!enumDtp) return; + const int width = enumDtp->width(); + const std::string smtName = memberVarp->name(); + std::string constraint = "(__Vbv (or"; + for (AstEnumItem* itemp = enumDtp->itemsp(); itemp; + itemp = VN_AS(itemp->nextp(), EnumItem)) { + const AstConst* const vconstp = VN_AS(itemp->valuep(), Const); + constraint += " (= " + smtName + " (_ bv" + cvtToStr(vconstp->toUInt()) + + " " + cvtToStr(width) + "))"; + } + constraint += "))"; + AstCMethodHard* const callp = new AstCMethodHard{ + fl, new AstVarRef{fl, genModp, genp, VAccess::READWRITE}, + VCMethod::RANDOMIZER_HARD, + new AstCExpr{fl, AstCExpr::Pure{}, "\"" + constraint + "\""}}; + callp->dtypeSetVoid(); + randomizep->addStmtsp(callp->makeStmt()); + }); + } + AstTask* setupAllTaskp = getCreateConstraintSetupFunc(nodep); - AstTaskRef* const setupTaskRefp = new AstTaskRef{fl, setupAllTaskp, nullptr}; + AstTaskRef* const setupTaskRefp = new AstTaskRef{fl, setupAllTaskp}; randomizep->addStmtsp(setupTaskRefp->makeStmt()); AstNodeModule* const genModp = VN_AS(genp->user2p(), NodeModule); @@ -2605,7 +3626,7 @@ class RandomizeVisitor final : public VNVisitor { if (AstTask* const resizeAllTaskp = VN_AS(m_memberMap.findMember(nodep, "__Vresize_constrained_arrays"), Task)) { - AstTaskRef* const resizeTaskRefp = new AstTaskRef{fl, resizeAllTaskp, nullptr}; + AstTaskRef* const resizeTaskRefp = new AstTaskRef{fl, resizeAllTaskp}; randomizep->addStmtsp(resizeTaskRefp->makeStmt()); } @@ -2615,9 +3636,17 @@ class RandomizeVisitor final : public VNVisitor { AstFunc* const basicRandomizep = V3Randomize::newRandomizeFunc(m_memberMap, nodep, BASIC_RANDOMIZE_FUNC_NAME); addBasicRandomizeBody(basicRandomizep, nodep, randModeVarp); - AstFuncRef* const basicRandomizeCallp = new AstFuncRef{fl, basicRandomizep, nullptr}; + AstFuncRef* const basicRandomizeCallp = new AstFuncRef{fl, basicRandomizep}; randomizep->addStmtsp(new AstAssign{fl, fvarRefp->cloneTree(false), new AstAnd{fl, fvarRefReadp, basicRandomizeCallp}}); + + // Call nested post_randomize on rand class-type members (IEEE 18.4.1) + if (classHasRandClassMembers(nodep)) { + AstTask* const postTaskp = getCreateNestedCallbackTask(nodep, "post"); + populateNestedCallbackTask(postTaskp, nodep, "post_randomize"); + randomizep->addStmtsp((new AstTaskRef{fl, postTaskp})->makeStmt()); + } + addPrePostCall(nodep, randomizep, "post_randomize"); nodep->user1(false); } @@ -2713,14 +3742,22 @@ class RandomizeVisitor final : public VNVisitor { classp = VN_AS(fromp->dtypep()->skipRefp(), ClassRefDType)->classp(); } UASSERT_OBJ(classp, nodep, "Failed to find class"); - AstVar* const constraintModeVarp = getConstraintModeVar(classp); + // Use correct mode variable based on whether constraint is static + AstVar* const constraintModeVarp = (constrp && constrp->isStatic()) + ? getStaticConstraintModeVar(classp) + : getConstraintModeVar(classp); AstNodeExpr* const lhsp = makeModeAssignLhs(nodep->fileline(), classp, fromp, constraintModeVarp); replaceWithModeAssign(nodep, constrp, lhsp); return; } - if (nodep->name() != "randomize") return; + if (nodep->name() != "randomize") { + // Iterate children so nested rand_mode/constraint_mode/randomize calls + // inside function arguments are still visited and transformed + iterateChildren(nodep); + return; + } if (nodep->classOrPackagep() && nodep->classOrPackagep()->name() == "std") { // Handle std::randomize; create wrapper function that calls basicStdRandomization on @@ -2735,14 +3772,9 @@ class RandomizeVisitor final : public VNVisitor { new AstConst{nodep->fileline(), AstConst::WidthedValue{}, 32, 1}}); std::unique_ptr withCapturep; int argn = 0; - AstWith* withp = nullptr; - for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { - if ((withp = VN_CAST(pinp, With))) break; - } - for (const AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { - const AstArg* const argp = VN_CAST(pinp, Arg); - if (!argp) continue; - AstNodeExpr* exprp = argp->exprp(); + AstWith* const withp = nodep->withp(); + for (const AstArg* argp = nodep->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { + AstNodeExpr* const exprp = argp->exprp(); AstCMethodHard* const basicMethodp = new AstCMethodHard{ nodep->fileline(), new AstVarRef{nodep->fileline(), stdrand, VAccess::READWRITE}, @@ -2798,8 +3830,9 @@ class RandomizeVisitor final : public VNVisitor { AstNode* const capturedTreep = withp->exprp()->unlinkFrBackWithNext(); randomizeFuncp->addStmtsp(capturedTreep); { - ConstraintExprVisitor{m_memberMap, capturedTreep, randomizeFuncp, - stdrand, nullptr, m_writtenVars}; + expandUniqueElementList(capturedTreep); + ConstraintExprVisitor{nullptr, m_memberMap, capturedTreep, randomizeFuncp, + stdrand, nullptr, m_writtenVars}; } AstCExpr* const solverCallp = new AstCExpr{fl}; solverCallp->dtypeSetBit(); @@ -2810,30 +3843,25 @@ class RandomizeVisitor final : public VNVisitor { = new AstAnd{fl, new AstVarRef{fl, fvarp, VAccess::READ}, solverCallp}; randomizeFuncp->addStmtsp( new AstAssign{fl, new AstVarRef{fl, fvarp, VAccess::WRITE}, andExprp}); - } - // Remove With nodes from pins as they have been processed - for (AstNode* pinp = nodep->pinsp(); pinp;) { - AstNode* const nextp = pinp->nextp(); - if (VN_IS(pinp, With)) { - VL_DO_DANGLING(pinp->unlinkFrBack()->deleteTree(), pinp); - } - pinp = nextp; + // Remove With nodes as processed + VL_DO_DANGLING(withp->unlinkFrBack()->deleteTree(), withp); } // Replace the node with a call to that function nodep->name(randomizeFuncp->name()); nodep->taskp(randomizeFuncp); nodep->dtypeFrom(randomizeFuncp->dtypep()); if (VN_IS(m_modp, Class)) nodep->classOrPackagep(m_modp); - if (withCapturep) nodep->addPinsp(withCapturep->getArgs()); + if (withCapturep) nodep->addArgsp(withCapturep->getArgs()); UINFOTREE(9, nodep, "", "std::rnd-call"); UINFOTREE(9, randomizeFuncp, "", "std::rnd-func"); return; } handleRandomizeArgs(nodep); - AstWith* const withp = VN_CAST(nodep->pinsp(), With); + AstWith* const withp = nodep->withp(); if (!withp) { iterateChildren(nodep); + wrapRandomizeCallWithNullGuard(nodep); return; } withp->unlinkFrBack(); @@ -2873,6 +3901,15 @@ class RandomizeVisitor final : public VNVisitor { addPrePostCall(classp, randomizeFuncp, "pre_randomize"); + // Call nested pre_randomize on rand class-type members (IEEE 18.4.1) + if (classHasRandClassMembers(classp)) { + AstTask* const preTaskp = getCreateNestedCallbackTask(classp, "pre"); + if (!preTaskp->stmtsp()) { + populateNestedCallbackTask(preTaskp, classp, "pre_randomize"); + } + randomizeFuncp->addStmtsp((new AstTaskRef{nodep->fileline(), preTaskp})->makeStmt()); + } + // Detach the expression and prepare variable copies const CaptureVisitor captured{withp->exprp(), m_modp, classp}; // Add function arguments @@ -2887,7 +3924,8 @@ class RandomizeVisitor final : public VNVisitor { for (AstNode* stmtp = mainRandomizep->stmtsp(); stmtp; stmtp = stmtp->nextp()) { bool foundClearConstraints = false; stmtp->foreach([&](AstCMethodHard* methodp) { - if (methodp->method() == VCMethod::RANDOMIZER_WRITE_VAR) { + if (methodp->method() == VCMethod::RANDOMIZER_WRITE_VAR + || methodp->method() == VCMethod::RANDOMIZER_MARK_RANDC) { randomizeFuncp->addStmtsp(stmtp->cloneTree(false)); } else if (methodp->method() == VCMethod::RANDOMIZER_CLEARCONSTRAINTS) { foundClearConstraints = true; @@ -2905,12 +3943,12 @@ class RandomizeVisitor final : public VNVisitor { AstFunc* const basicRandomizeFuncp = V3Randomize::newRandomizeFunc(m_memberMap, classp, BASIC_RANDOMIZE_FUNC_NAME); AstFuncRef* const basicRandomizeFuncCallp - = new AstFuncRef{nodep->fileline(), basicRandomizeFuncp, nullptr}; + = new AstFuncRef{nodep->fileline(), basicRandomizeFuncp}; // Copy (derive) class constraints if present if (classGenp) { AstTask* const constrSetupFuncp = getCreateConstraintSetupFunc(classp); - AstTaskRef* const callp = new AstTaskRef{nodep->fileline(), constrSetupFuncp, nullptr}; + AstTaskRef* const callp = new AstTaskRef{nodep->fileline(), constrSetupFuncp}; randomizeFuncp->addStmtsp(callp->makeStmt()); randomizeFuncp->addStmtsp(new AstAssign{ nodep->fileline(), new AstVarRef{nodep->fileline(), localGenp, VAccess::WRITE}, @@ -2926,8 +3964,9 @@ class RandomizeVisitor final : public VNVisitor { AstNode* const capturedTreep = withp->exprp()->unlinkFrBackWithNext(); randomizeFuncp->addStmtsp(capturedTreep); { - ConstraintExprVisitor{m_memberMap, capturedTreep, randomizeFuncp, - localGenp, randModeVarp, m_writtenVars}; + expandUniqueElementList(capturedTreep); + ConstraintExprVisitor{classp, m_memberMap, capturedTreep, randomizeFuncp, + localGenp, randModeVarp, m_writtenVars}; } // Call the solver and set return value @@ -2940,15 +3979,25 @@ class RandomizeVisitor final : public VNVisitor { new AstVarRef{nodep->fileline(), VN_AS(randomizeFuncp->fvarp(), Var), VAccess::WRITE}, new AstAnd{nodep->fileline(), basicRandomizeFuncCallp, solverCallp}}); + // Call nested post_randomize on rand class-type members (IEEE 18.4.1) + if (classHasRandClassMembers(classp)) { + AstTask* const postTaskp = getCreateNestedCallbackTask(classp, "post"); + if (!postTaskp->stmtsp()) { + populateNestedCallbackTask(postTaskp, classp, "post_randomize"); + } + randomizeFuncp->addStmtsp((new AstTaskRef{nodep->fileline(), postTaskp})->makeStmt()); + } + addPrePostCall(classp, randomizeFuncp, "post_randomize"); // Replace the node with a call to that function nodep->name(randomizeFuncp->name()); - nodep->addPinsp(captured.getArgs()); + nodep->addArgsp(captured.getArgs()); nodep->taskp(randomizeFuncp); nodep->dtypeFrom(randomizeFuncp->dtypep()); nodep->classOrPackagep(classp); UINFO(9, "Added `%s` randomization procedure"); + wrapRandomizeCallWithNullGuard(nodep); VL_DO_DANGLING(withp->deleteTree(), withp); } void visit(AstConstraint* nodep) override { @@ -2979,16 +4028,21 @@ class RandomizeVisitor final : public VNVisitor { queueVarp->user4p(sizeVarp); - AstTask* resizerTaskp = VN_AS(m_constraintp->user3p(), Task); - if (!resizerTaskp) { - resizerTaskp = newResizeConstrainedArrayTask(classp, m_constraintp->name()); - m_constraintp->user3p(resizerTaskp); + // Associative arrays have no resize(); only generate resize + // for dynamic arrays and queues + if (!VN_IS(queueVarp->dtypep()->skipRefp(), AssocArrayDType)) { + AstTask* resizerTaskp = VN_AS(m_constraintp->user3p(), Task); + if (!resizerTaskp) { + resizerTaskp + = newResizeConstrainedArrayTask(classp, m_constraintp->name()); + m_constraintp->user3p(resizerTaskp); + } + AstCMethodHard* const resizep = new AstCMethodHard{ + fl, nodep->fromp()->unlinkFrBack(), VCMethod::DYN_RESIZE, + new AstVarRef{fl, sizeVarp, VAccess::READ}}; + resizep->dtypep(nodep->findVoidDType()); + resizerTaskp->addStmtsp(new AstStmtExpr{fl, resizep}); } - AstCMethodHard* const resizep - = new AstCMethodHard{fl, nodep->fromp()->unlinkFrBack(), VCMethod::DYN_RESIZE, - new AstVarRef{fl, sizeVarp, VAccess::READ}}; - resizep->dtypep(nodep->findVoidDType()); - resizerTaskp->addStmtsp(new AstStmtExpr{fl, resizep}); // Since size variable is signed int, we need additional constraint // to make sure it is always >= 0. diff --git a/src/V3Randomize.h b/src/V3Randomize.h index 2a2c0a4cf..f7e2589d4 100644 --- a/src/V3Randomize.h +++ b/src/V3Randomize.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Reloop.cpp b/src/V3Reloop.cpp index 800c8124a..8870e2ab6 100644 --- a/src/V3Reloop.cpp +++ b/src/V3Reloop.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -68,6 +68,7 @@ class ReloopVisitor final : public VNVisitor { const string newvarname{"__Vilp" + std::to_string(cfuncp->user1Inc() + 1)}; AstVar* const varp = new AstVar{fl, VVarType::STMTTEMP, newvarname, VFlagLogicPacked{}, 32}; + cfuncp->addVarsp(varp); return varp; } void mergeEnd() { @@ -105,8 +106,7 @@ class ReloopVisitor final : public VNVisitor { AstLoop* const loopp = new AstLoop{fl}; loopp->addStmtsp(new AstLoopTest{fl, loopp, condp}); initp->addNext(loopp); - itp->AstNode::addNext(initp); - bodyp->replaceWith(itp); + bodyp->replaceWith(initp); loopp->addStmtsp(bodyp); loopp->addStmtsp(incp); diff --git a/src/V3Reloop.h b/src/V3Reloop.h index 1423293aa..37bb1dd6c 100644 --- a/src/V3Reloop.h +++ b/src/V3Reloop.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Reorder.cpp b/src/V3Reorder.cpp new file mode 100644 index 000000000..7afa5d9d9 --- /dev/null +++ b/src/V3Reorder.cpp @@ -0,0 +1,534 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Reorder statements within always blocks +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* +// V3Reorder transformations: +// +// reorderAll() reorders statements within individual blocks to avoid +// shwdow variables use by non blocking assignments when possible. +// For exmaple, the left side needs a shadow variable for 'b', the +// right side does not: +// Bad: Good: +// b <= a; c <= b; +// c <= b; b <= a; +// +// The scoreboard tracks data deps as follows: +// +// ALWAYS +// ASSIGN ({var} <= {cons}) +// Record as generating var_DLY (independent of use of var), consumers +// ASSIGN ({var} = {cons} +// Record generator and consumer +// Any var that is only consumed can be ignored. +// Then we split into separate ALWAYS blocks. +// +// The scoreboard includes innards of if/else nodes also. Splitting is no +// longer limited to top-level statements, we can split within if-else +// blocks. We want to be able to split this: +// +// The optional reorder routine can optimize this: +// NODEASSIGN/NODEIF/WHILE +// S1: ASSIGN {v1} <= 0. // Duplicate of below +// S2: ASSIGN {v1} <= {v0} +// S3: IF (..., +// X1: ASSIGN {v2} <= {v1} +// X2: ASSIGN {v3} <= {v2} +// We'd like to swap S2 and S3, and X1 and X2. +// +// Create a graph in split assignment order. +// v3 -breakable-> v3Dly --> X2 --> v2 -brk-> v2Dly -> X1 -> v1 +// Likewise on each "upper" statement vertex +// v3Dly & v2Dly -> S3 -> v1 & v2 +// v1 -brk-> v1Dly -> S2 -> v0 +// v1Dly -> S1 -> {empty} +// +//************************************************************************* + +#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT + +#include "V3Reorder.h" + +#include "V3EmitV.h" +#include "V3Graph.h" +#include "V3Stats.h" + +#include +#include +#include + +VL_DEFINE_DEBUG_FUNCTIONS; + +namespace { + +//###################################################################### +// Support classes + +class ReorderNodeVertex VL_NOT_FINAL : public V3GraphVertex { + VL_RTTI_IMPL(ReorderNodeVertex, V3GraphVertex) + AstNode* const m_nodep; + +protected: + ReorderNodeVertex(V3Graph* graphp, AstNode* nodep) + : V3GraphVertex{graphp} + , m_nodep{nodep} {} + ~ReorderNodeVertex() override = default; + // ACCESSORS + // Do not make accessor for nodep(), It may change due to + // reordering a lower block, but we don't repair it + std::string name() const override { + std::string str = cvtToHex(m_nodep) + '\n'; + if (AstVarScope* const vscp = VN_CAST(m_nodep, VarScope)) { + str += vscp->prettyName(); + } else { + str += V3EmitV::debugVerilogForTree(m_nodep); + str = VString::quoteBackslash(str); + str = VString::quoteAny(str, '"', '\\'); + str = VString::replaceSubstr(str, "\n", "\\l"); + } + return str; + } + FileLine* fileline() const override { return nodep()->fileline(); } + std::string dotShape() const override { return VN_IS(m_nodep, VarScope) ? "ellipse" : "box"; } + +public: + virtual AstNode* nodep() const { return m_nodep; } +}; + +class ReorderImpureVertex final : public ReorderNodeVertex { + VL_RTTI_IMPL(ReorderImpureVertex, ReorderNodeVertex) +public: + explicit ReorderImpureVertex(V3Graph* graphp, AstNode* nodep) + : ReorderNodeVertex{graphp, nodep} {} + ~ReorderImpureVertex() override = default; + string name() const override VL_MT_STABLE { return "*IMPURE*"; } + string dotColor() const override { return "red"; } +}; + +class ReorderLogicVertex final : public ReorderNodeVertex { + VL_RTTI_IMPL(ReorderLogicVertex, ReorderNodeVertex) +public: + ReorderLogicVertex(V3Graph* graphp, AstNode* nodep) + : ReorderNodeVertex{graphp, nodep} {} + ~ReorderLogicVertex() override = default; + string dotColor() const override { return "black"; } +}; + +class ReorderVarStdVertex final : public ReorderNodeVertex { + VL_RTTI_IMPL(ReorderVarStdVertex, ReorderNodeVertex) +public: + ReorderVarStdVertex(V3Graph* graphp, AstVarScope* nodep) + : ReorderNodeVertex{graphp, nodep} {} + ~ReorderVarStdVertex() override = default; + string dotColor() const override { return "blue"; } +}; + +class ReorderVarPostVertex final : public ReorderNodeVertex { + VL_RTTI_IMPL(ReorderVarPostVertex, ReorderNodeVertex) +public: + ReorderVarPostVertex(V3Graph* graphp, AstVarScope* nodep) + : ReorderNodeVertex{graphp, nodep} {} + ~ReorderVarPostVertex() override = default; + string name() const override { return "POST "s + ReorderNodeVertex::name(); } + string dotColor() const override { return "green"; } +}; + +//###################################################################### +// Edge types + +class ReorderEdge VL_NOT_FINAL : public V3GraphEdge { + VL_RTTI_IMPL(ReorderEdge, V3GraphEdge) + uint32_t m_ignoreInStep = 0; // Step number that if set to, causes this edge to be ignored + static uint32_t s_stepNum; // Global step number +protected: + static constexpr int WEIGHT_NORMAL = 10; + ReorderEdge(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top, bool cutable) + : V3GraphEdge{graphp, fromp, top, WEIGHT_NORMAL, cutable} {} + ~ReorderEdge() override = default; + + virtual bool followScoreboard() const = 0; + + std::string dotStyle() const override { + return ignoreThisStep() ? "dotted" : V3GraphEdge::dotStyle(); + } + +public: + // Iterator for graph functions + static void incrementStep() { ++s_stepNum; } + bool ignoreThisStep() const { return m_ignoreInStep == s_stepNum; } + void setIgnoreThisStep() { m_ignoreInStep = s_stepNum; } + + static bool followScoreboard(const V3GraphEdge* edgep) { + const ReorderEdge& edge = *edgep->as(); + return !edge.ignoreThisStep() && edge.followScoreboard(); + } + static bool followCyclic(const V3GraphEdge* edgep) { + const ReorderEdge& edge = *edgep->as(); + return !edge.ignoreThisStep(); + } +}; +uint32_t ReorderEdge::s_stepNum = 0; + +class ReorderPostEdge final : public ReorderEdge { + VL_RTTI_IMPL(ReorderPostEdge, ReorderEdge) +public: + ReorderPostEdge(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top) + : ReorderEdge{graphp, fromp, top, CUTABLE} {} + ~ReorderPostEdge() override = default; + bool followScoreboard() const override { return false; } + string dotColor() const override { return "khaki"; } +}; + +class ReorderLVEdge final : public ReorderEdge { + VL_RTTI_IMPL(ReorderLVEdge, ReorderEdge) +public: + ReorderLVEdge(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top) + : ReorderEdge{graphp, fromp, top, CUTABLE} {} + ~ReorderLVEdge() override = default; + bool followScoreboard() const override { return true; } + string dotColor() const override { return "yellowGreen"; } +}; + +class ReorderRVEdge final : public ReorderEdge { + VL_RTTI_IMPL(ReorderRVEdge, ReorderEdge) +public: + ReorderRVEdge(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top) + : ReorderEdge{graphp, fromp, top, CUTABLE} {} + ~ReorderRVEdge() override = default; + bool followScoreboard() const override { return true; } + string dotColor() const override { return "green"; } +}; + +class ReorderScorebdEdge final : public ReorderEdge { + VL_RTTI_IMPL(ReorderScorebdEdge, ReorderEdge) +public: + ReorderScorebdEdge(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top) + : ReorderEdge{graphp, fromp, top, CUTABLE} {} + ~ReorderScorebdEdge() override = default; + bool followScoreboard() const override { return true; } + string dotColor() const override { return "blue"; } +}; + +class ReorderStrictEdge final : public ReorderEdge { + VL_RTTI_IMPL(ReorderStrictEdge, ReorderEdge) + // A strict order, based on the original statement order in the graph + // The only non-cutable edge type +public: + ReorderStrictEdge(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top) + : ReorderEdge{graphp, fromp, top, NOT_CUTABLE} {} + ~ReorderStrictEdge() override = default; + bool followScoreboard() const override { return true; } + string dotColor() const override { return "blue"; } +}; + +//###################################################################### +// Reorder class functions + +class ReorderVisitor final : public VNVisitor { + // NODE STATE - Only under AstAlways + // AstVarScope::user1p -> Var ReorderVarStdVertex* for usage var, 0=not set yet + // AstVarScope::user2p -> Var ReorderVarPostVertex* for delayed assignment var, 0=not set yet + // Ast*::user3p -> Statement ReorderLogicVertex* (temporary only) + // Ast*::user4 -> Current ordering number (reorderBlock usage) + + // STATE + V3Graph* m_graphp = nullptr; // Scoreboard of var usages/dependencies + ReorderImpureVertex* m_impureVtxp = nullptr; // Element specifying PLI ordering + bool m_inDly = false; // Inside ASSIGNDLY + const char* m_noReorderWhy = nullptr; // Reason we can't reorder + std::vector m_stmtStackps; // Current statements being tracked + + // METHODS + void cleanupBlockGraph(AstNode* nodep) { + // Transform the graph into what we need + UINFO(5, "ReorderBlock " << nodep); + + // Simplify graph by removing redundant edges + m_graphp->removeRedundantEdgesMax(&V3GraphEdge::followAlwaysTrue); + if (dumpGraphLevel() >= 9) m_graphp->dumpDotFilePrefixed("reorderg_nodup", false); + + // Mark all the logic for this step by setting Vertex::user() to true + m_graphp->userClearVertices(); + for (AstNode* nextp = nodep; nextp; nextp = nextp->nextp()) { + nextp->user3u().to()->user(true); + } + + // New step + ReorderEdge::incrementStep(); + + // If a var vertex has only inputs, it's a input-only node, + // and can be ignored for coloring **this block only** + for (V3GraphVertex& vtx : m_graphp->vertices()) { + if (!vtx.outEmpty()) continue; + if (!vtx.is()) continue; + for (V3GraphEdge& edge : vtx.inEdges()) edge.as()->setIgnoreThisStep(); + } + + // For reordering this single block only, mark all logic + // vertexes not involved with this step as unimportant + for (V3GraphVertex& vertex : m_graphp->vertices()) { + if (vertex.user()) continue; + if (!vertex.is()) continue; + for (V3GraphEdge& edge : vertex.inEdges()) edge.as()->setIgnoreThisStep(); + for (V3GraphEdge& edge : vertex.outEdges()) + edge.as()->setIgnoreThisStep(); + } + + // Weak coloring to determine what needs to remain in order + // This follows all step-relevant edges excluding PostEdges, which are done later + m_graphp->weaklyConnected(&ReorderEdge::followScoreboard); + + // Add hard orderings between all nodes of same color, in the order they appeared + std::unordered_map lastOfColor; + for (AstNode* currp = nodep; currp; currp = currp->nextp()) { + ReorderLogicVertex* const vtxp = currp->user3u().to(); + const uint32_t color = vtxp->color(); + UASSERT_OBJ(color, currp, "No node color assigned"); + if (lastOfColor[color]) new ReorderStrictEdge{m_graphp, lastOfColor[color], vtxp}; + lastOfColor[color] = vtxp; + } + + // And a real ordering to get the statements into something reasonable + // We don't care if there's cutable violations here... + // Non-cutable violations should be impossible; as those edges are program-order + if (dumpGraphLevel() >= 9) m_graphp->dumpDotFilePrefixed("reorderg_pre", false); + m_graphp->acyclic(&ReorderEdge::followCyclic); + m_graphp->rank(&ReorderEdge::followCyclic); // Or order(), but that's more expensive + if (dumpGraphLevel() >= 9) m_graphp->dumpDotFilePrefixed("reorderg_opt", false); + } + + void reorderBlock(AstNode* nodep) { + // Reorder statements in the completed graph + + // Map the rank numbers into nodes they associate with + std::multimap rankMap; + int currOrder = 0; // Existing sequence number of assignment + for (AstNode* currp = nodep; currp; currp = currp->nextp()) { + const ReorderLogicVertex* const vtxp = currp->user3u().to(); + rankMap.emplace(vtxp->rank(), currp); + currp->user4(++currOrder); // Record current ordering + } + + // Is the current ordering OK? + bool leaveAlone = true; + int newOrder = 0; // New sequence number of assignment + for (const auto& item : rankMap) { + const AstNode* const nextp = item.second; + if (++newOrder != nextp->user4()) leaveAlone = false; + } + if (leaveAlone) { + UINFO(6, " No changes"); + return; + } + + VNRelinker replaceHandle; // Where to add the list + AstNode* newListp = nullptr; + for (const auto& item : rankMap) { + AstNode* const nextp = item.second; + UINFO(6, " New order: " << nextp); + nextp->unlinkFrBack(nextp == nodep ? &replaceHandle : nullptr); + newListp = AstNode::addNext(newListp, nextp); + } + replaceHandle.relink(newListp); + } + + void processBlock(AstNode* nodep) { + if (m_noReorderWhy) return; + + // Empty lists are ignorable + if (!nodep) return; + UASSERT_OBJ(nodep->firstAbovep(), nodep, "Node passed is in not head of list"); + UASSERT_OBJ(!nodep->user3p(), nodep, "Should not have a logic vertex"); + + // It nothing to reorder with, just iterate + if (!nodep->nextp()) { + iterate(nodep); + return; + } + + // Process it + UINFO(9, " processBlock " << nodep); + + // Iterate across current block, making the scoreboard + for (AstNode* currp = nodep; currp; currp = currp->nextp()) { + // Create the logic vertex for this statement + UASSERT_OBJ(!currp->user3p(), currp, "user3p should not be set"); + ReorderLogicVertex* const vtxp = new ReorderLogicVertex{m_graphp, currp}; + currp->user3p(vtxp); + + // Visit the statement - this can recursively reorder sub statements + m_stmtStackps.push_back(vtxp); + iterate(currp); + m_stmtStackps.pop_back(); + } + + if (m_noReorderWhy) { // Jump or something nasty + UINFO(9, " NoReorderBlock because " << m_noReorderWhy); + return; + } + + // Reorder statements in this block + cleanupBlockGraph(nodep); + reorderBlock(nodep); + + // 'nodep' might no longer be the head of the list, rewind + while (nodep->backp()->nextp() == nodep) nodep = nodep->backp(); + + // Delete vertexes and edges only applying to this block + for (AstNode* currp = nodep; currp; currp = currp->nextp()) { + currp->user3u().to()->unlinkDelete(m_graphp); + currp->user3p(nullptr); + } + } + + // VISITORS + void visit(AstAlways* nodep) override { + UASSERT_OBJ(!m_graphp, nodep, "AstAlways should not nest"); + VL_RESTORER(m_graphp); + VL_RESTORER(m_impureVtxp); + VL_RESTORER(m_inDly); + VL_RESTORER(m_noReorderWhy); + + V3Graph graph; + m_graphp = &graph; + m_impureVtxp = nullptr; + m_inDly = false; + m_noReorderWhy = nullptr; + + const VNUser1InUse user1InUse; + const VNUser2InUse user2InUse; + const VNUser3InUse user3InUse; + const VNUser4InUse user4InUse; + + UINFOTREE(9, nodep, "", "alwIn:"); + processBlock(nodep->stmtsp()); + UINFOTREE(9, nodep, "", "alwOut"); + + m_stmtStackps.clear(); + } + + void visit(AstNodeIf* nodep) override { + if (!m_graphp || m_noReorderWhy) return; + iterateAndNextNull(nodep->condp()); + processBlock(nodep->thensp()); + processBlock(nodep->elsesp()); + } + + void visit(AstJumpGo* nodep) override { + if (!m_graphp || m_noReorderWhy) return; + m_noReorderWhy = "JumpGo"; + iterateChildren(nodep); + } + + void visit(AstExprStmt* nodep) override { + if (!m_graphp || m_noReorderWhy) return; + VL_RESTORER(m_inDly); + m_inDly = false; + iterateChildren(nodep); + } + + void visit(AstAssignDly* nodep) override { + if (!m_graphp || m_noReorderWhy) return; + iterate(nodep->rhsp()); + VL_RESTORER(m_inDly); + m_inDly = true; + iterate(nodep->lhsp()); + } + + void visit(AstVarRef* nodep) override { + if (!m_graphp || m_noReorderWhy) return; + if (m_stmtStackps.empty()) return; + + // Reads of constants can be ignored - TODO: This should be "constexpr", not run-time const + if (nodep->varp()->isConst()) return; + + // SPEEDUP: We add duplicate edges, that should be fixed + + AstVarScope* const vscp = nodep->varScopep(); + + // Create vertexes for variable + if (!vscp->user1p()) vscp->user1p(new ReorderVarStdVertex{m_graphp, vscp}); + ReorderVarStdVertex* const vstdp = vscp->user1u().to(); + + // Variable is read + if (nodep->access().isReadOnly()) { + for (ReorderLogicVertex* const vtxp : m_stmtStackps) { + new ReorderRVEdge{m_graphp, vtxp, vstdp}; + } + return; + } + + // Variable is written, not NBA + if (!m_inDly) { + for (ReorderLogicVertex* const vtxp : m_stmtStackps) { + new ReorderLVEdge{m_graphp, vstdp, vtxp}; + } + return; + } + + // Variable is written by NBA + if (!vscp->user2p()) { + ReorderVarPostVertex* const vpostp = new ReorderVarPostVertex{m_graphp, vscp}; + vscp->user2p(vpostp); + new ReorderPostEdge{m_graphp, vstdp, vpostp}; + } + ReorderVarPostVertex* const vpostp = vscp->user2u().to(); + for (ReorderLogicVertex* const vtxp : m_stmtStackps) { + new ReorderLVEdge{m_graphp, vpostp, vtxp}; + } + } + + void visit(AstNode* nodep) override { + // Outside AstAlways, just descend + if (!m_graphp) { + iterateChildren(nodep); + return; + } + + // Early exit if decided not to reorder + if (m_noReorderWhy) return; + + // Timing control prevents reordering + if (nodep->isTimingControl()) { + m_noReorderWhy = "TimingControl"; + return; + } + + // Order all impure statements with other impure statements + if (!nodep->isPure()) { + if (!m_impureVtxp) m_impureVtxp = new ReorderImpureVertex{m_graphp, nodep}; + // This edge is only used to find weakly connected components, so one edge is enough + for (ReorderLogicVertex* const vtxp : m_stmtStackps) { + new ReorderScorebdEdge{m_graphp, m_impureVtxp, vtxp}; + } + } + + iterateChildren(nodep); + } + + // CONSTRUCTORS +public: + explicit ReorderVisitor(AstNetlist* nodep) { iterate(nodep); } + ~ReorderVisitor() override = default; +}; + +} // namespace + +//###################################################################### +// V3Reorder class functions + +void V3Reorder::reorderAll(AstNetlist* nodep) { + UINFO(2, __FUNCTION__ << ":"); + { ReorderVisitor{nodep}; } // Destruct before checking + V3Global::dumpCheckGlobalTree("reorder", 0, dumpTreeEitherLevel() >= 3); +} diff --git a/src/V3EmitXml.h b/src/V3Reorder.h similarity index 53% rename from src/V3EmitXml.h rename to src/V3Reorder.h index c4caa9da0..8583fc6e6 100644 --- a/src/V3EmitXml.h +++ b/src/V3Reorder.h @@ -1,30 +1,32 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* -// DESCRIPTION: Verilator: Emit XML code +// DESCRIPTION: Verilator: Reorder statements within always blocks // // Code available from: https://verilator.org // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* -#ifndef VERILATOR_V3EMITXML_H_ -#define VERILATOR_V3EMITXML_H_ +#ifndef VERILATOR_V3REORDER_H_ +#define VERILATOR_V3REORDER_H_ #include "config_build.h" #include "verilatedos.h" +class AstNetlist; + //============================================================================ -class V3EmitXml final { +class V3Reorder final { public: - static void emitxml() VL_MT_DISABLED; + static void reorderAll(AstNetlist* nodep) VL_MT_DISABLED; }; #endif // Guard diff --git a/src/V3Rtti.h b/src/V3Rtti.h index 2bd98aaff..4f8e3391f 100644 --- a/src/V3Rtti.h +++ b/src/V3Rtti.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Sampled.cpp b/src/V3Sampled.cpp index a303043da..d978df73f 100644 --- a/src/V3Sampled.cpp +++ b/src/V3Sampled.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Sampled.h b/src/V3Sampled.h index 3560999ec..0affe682c 100644 --- a/src/V3Sampled.h +++ b/src/V3Sampled.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp index c3271d254..bef68595f 100644 --- a/src/V3Sched.cpp +++ b/src/V3Sched.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -86,18 +86,32 @@ void invertAndMergeSenTreeMap( } std::vector -findTriggeredIface(const AstVarScope* vscp, const VirtIfaceTriggers::IfaceSensMap& vifTrigged, +findTriggeredIface(const AstVarScope* vscp, const VirtIfaceTriggers::IfaceMemberSensMap& vifMemberTriggered) { - UASSERT_OBJ(vscp->varp()->sensIfacep(), vscp, "Not an virtual interface trigger"); - std::vector result; - const auto ifaceIt = vifTrigged.find(vscp->varp()->sensIfacep()); - if (ifaceIt != vifTrigged.end()) result.push_back(ifaceIt->second); - for (const auto& memberIt : vifMemberTriggered) { - if (vscp->varp()->sensIfacep() == memberIt.first.m_ifacep) { - result.push_back(memberIt.second); - } + const AstIface* ifacep; + if (vscp->varp()->isVirtIface()) { + // If `vscp->varp()->isVirtIface()` is true then the interface type that viface is pointing + // to is under `VN_AS(vscp->varp()->dtypep(), IfaceRefDType)->ifacep()` + + ifacep = VN_AS(vscp->varp()->dtypep(), IfaceRefDType)->ifacep(); + + // Virtual interface is sensitive to a different interface type than it is a virtual type + // of - this may be a valid behaviour but this function does not expects that + UASSERT_OBJ(vscp->varp()->sensIfacep() == nullptr, vscp, + "Virtual interface has an ambiguous type - " + << vscp->varp()->sensIfacep()->prettyTypeName() + << " != " << ifacep->prettyTypeName()); + } else { + // If `vscp->varp()` is of a non-virtual interface type it has `sensIfacep()` set to + // interface it is sensitive to + ifacep = vscp->varp()->sensIfacep(); } - if (result.empty()) vscp->v3fatalSrc("Did not find virtual interface trigger"); + UASSERT_OBJ(ifacep, vscp, "Variable is not sensitive for any interface"); + std::vector result; + for (const auto& memberIt : vifMemberTriggered) { + if (memberIt.first.m_ifacep == ifacep) result.push_back(memberIt.second); + } + UASSERT_OBJ(!result.empty(), vscp, "Did not find virtual interface trigger"); return result; } @@ -118,7 +132,8 @@ EvalLoop createEvalLoop( const string& name, // Name of current phase bool slow, // Should create slow functions const TriggerKit& trigKit, // The trigger kit - AstVarScope* trigp, // The trigger vector - may be nullptr if no triggers + AstVarScope* trigp, // The trigger vector - may be nullptr if no triggers or using 'condp' + AstNodeExpr* condp, // Explicit condition that must be true to run 'phaseWorkp' AstNodeStmt* innerp, // The inner loop, if any AstNodeStmt* phasePrepp, // Prep statements run before checking triggers AstNodeStmt* phaseWorkp, // The work to do if anything triggered @@ -127,9 +142,11 @@ EvalLoop createEvalLoop( // and must be unmodified otherwise. std::function phaseExtra = [](AstVarScope*) { return nullptr; } // ) { - // All work is under a trigger, so if there are no triggers, there is - // nothing to do besides executing the inner loop. - if (!trigp) return {nullptr, innerp}; + UASSERT(!trigp || !condp, "Cannot use both 'trigp' and 'condp' in 'createEvalLoop'"); + + // All work is under a trigger or condition, so if there are none, + // there is nothing to do besides executing the inner loop. + if (!trigp && !condp) return {nullptr, innerp}; const std::string varPrefix = "__V" + tag; AstScope* const scopeTopp = netlistp->topScopep()->scopep(); @@ -147,9 +164,10 @@ EvalLoop createEvalLoop( // If there is work in this phase, execute it if any triggers fired if (phaseWorkp) { - // Check if any triggers are fired, save the result AstNodeExpr* const lhsp = new AstVarRef{flp, executeFlagp, VAccess::WRITE}; - AstNodeExpr* const rhsp = trigKit.newAnySetCall(trigp); + // If using explicit condition, that directly determines whether to execute, + // otherwise check if any triggers are fired + AstNodeExpr* const rhsp = condp ? condp : trigKit.newAnySetCall(trigp); phaseFuncp->addStmtsp(new AstAssign{flp, lhsp, rhsp}); // Add the work @@ -179,26 +197,31 @@ EvalLoop createEvalLoop( stmtps = AstCStmt::profExecSectionPush(flp, "loop " + tag); } - const auto addVar = [&](const std::string& name, int width, uint32_t initVal) { - AstVarScope* const vscp = scopeTopp->createTemp("__V" + tag + name, width); + const auto addVar = [&](const std::string& name, int width, uint32_t initVal, bool init) { + const string tempName{"__V" + tag + name}; + AstVarScope* const vscp = tempName == "__VstlFirstIteration" + ? netlistp->stlFirstIterationp() + : scopeTopp->createTemp(tempName, width); vscp->varp()->noReset(true); vscp->varp()->isInternal(true); - stmtps = AstNode::addNext(stmtps, util::setVar(vscp, initVal)); + if (init) stmtps = AstNode::addNext(stmtps, util::setVar(vscp, initVal)); return vscp; }; // The iteration counter - AstVarScope* const counterp = addVar("IterCount", 32, 0); + AstVarScope* const counterp = addVar("IterCount", 32, 0, true); // The first iteration flag - cleared in 'phasePrepp' if used - AstVarScope* const firstIterFlagp = addVar("FirstIteration", 1, 1); + AstVarScope* const firstIterFlagp = addVar("FirstIteration", 1, 1, true); + // Phase function result + AstVarScope* const phaseResultp = addVar("PhaseResult", 1, 0, false); // The loop { AstLoop* const loopp = new AstLoop{flp}; stmtps->addNext(loopp); - // Check the iteration limit (aborts if exceeded) - AstNodeStmt* const dumpCallp = trigKit.newDumpCall(trigp, tag, false); + // Check the iteration limit (aborts if exceeded). Dump triggers if using triggers. + AstNodeStmt* dumpCallp = trigp ? trigKit.newDumpCall(trigp, tag, false) : nullptr; loopp->addStmtsp(util::checkIterationLimit(netlistp, name, counterp, dumpCallp)); // Increment the iteration counter loopp->addStmtsp(util::incrementVar(counterp)); @@ -212,8 +235,17 @@ EvalLoop createEvalLoop( // need to reset it AstCCall* const callp = new AstCCall{flp, phaseFuncp}; callp->dtypeSetBit(); + AstAssign* const resultAssignp + = new AstAssign{flp, new AstVarRef{flp, phaseResultp, VAccess::WRITE}, callp}; + loopp->addStmtsp(resultAssignp); + // Clear FirstIteration flag + AstAssign* const firstClearp + = new AstAssign{flp, new AstVarRef{flp, firstIterFlagp, VAccess::WRITE}, + new AstConst{flp, AstConst::BitFalse()}}; + loopp->addStmtsp(firstClearp); // Continues until the continuation flag is clear - loopp->addStmtsp(new AstLoopTest{flp, loopp, callp}); + loopp->addStmtsp( + new AstLoopTest{flp, loopp, new AstVarRef{flp, phaseResultp, VAccess::READ}}); } // Prof-exec section pop @@ -367,10 +399,6 @@ void createFinal(AstNetlist* netlistp, const LogicClasses& logicClasses) { void addVirtIfaceTriggerAssignments(const VirtIfaceTriggers& virtIfaceTriggers, uint32_t vifTriggerIndex, uint32_t vifMemberTriggerIndex, const TriggerKit& trigKit) { - for (const auto& p : virtIfaceTriggers.m_ifaceTriggers) { - trigKit.addExtraTriggerAssignment(p.second, vifTriggerIndex); - ++vifTriggerIndex; - } for (const auto& p : virtIfaceTriggers.m_memberTriggers) { trigKit.addExtraTriggerAssignment(p.second, vifMemberTriggerIndex); ++vifMemberTriggerIndex; @@ -397,7 +425,7 @@ void createSettle(AstNetlist* netlistp, AstCFunc* const initFuncp, SenExprBuilde // Gather the relevant sensitivity expressions and create the trigger kit const auto& senTreeps = getSenTreesUsedBy({&comb, &hybrid}); const TriggerKit trigKit = TriggerKit::create(netlistp, initFuncp, senExprBulider, {}, - senTreeps, "stl", extraTriggers, true); + senTreeps, "stl", extraTriggers, true, false); // Remap sensitivities (comb has none, so only do the hybrid) remapSensitivities(hybrid, trigKit.mapVec()); @@ -418,16 +446,23 @@ void createSettle(AstNetlist* netlistp, AstCFunc* const initFuncp, SenExprBuilde // Create the eval loop const EvalLoop stlLoop = createEvalLoop( // - netlistp, "stl", "Settle", /* slow: */ true, trigKit, trigKit.vscp(), + netlistp, "stl", "Settle", /* slow: */ true, trigKit, + // Use trigger + trigKit.vscp(), nullptr, + // Explicit condition // Inner loop statements nullptr, // Prep statements: Compute the current 'stl' triggers - trigKit.newCompCall(), + [&trigKit] { + AstNodeStmt* const stmtp = trigKit.newCompBaseCall(); + if (stmtp) stmtp->addNext(trigKit.newDumpCall(trigKit.vscp(), trigKit.name(), true)); + return stmtp; + }(), // Work statements: Invoke the 'stl' function util::callVoidFunc(stlFuncp)); // Add the first iteration trigger to the trigger computation function - trigKit.addExtraTriggerAssignment(stlLoop.firstIterp, firstIterationTrigger); + trigKit.addExtraTriggerAssignment(stlLoop.firstIterp, firstIterationTrigger, false); // Add the eval loop to the top function funcp->addStmtsp(stlLoop.stmtsp); @@ -465,9 +500,6 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp, ? extraTriggers.allocate("DPI export trigger") : std::numeric_limits::max(); const size_t firstVifTriggerIndex = extraTriggers.size(); - for (const auto& p : virtIfaceTriggers.m_ifaceTriggers) { - extraTriggers.allocate("virtual interface: " + p.first->name()); - } const size_t firstVifMemberTriggerIndex = extraTriggers.size(); for (const auto& p : virtIfaceTriggers.m_memberTriggers) { const auto& item = p.first; @@ -478,7 +510,8 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp, // Gather the relevant sensitivity expressions and create the trigger kit const auto& senTreeps = getSenTreesUsedBy({&logic}); const TriggerKit trigKit = TriggerKit::create(netlistp, initFuncp, senExprBuilder, {}, - senTreeps, "ico", extraTriggers, false); + senTreeps, "ico", extraTriggers, false, false); + std::ignore = senExprBuilder.getAndClearResults(); if (dpiExportTriggerVscp) { trigKit.addExtraTriggerAssignment(dpiExportTriggerVscp, dpiExportTriggerIndex); @@ -502,8 +535,6 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp, = dpiExportTriggerVscp ? trigKit.newExtraTriggerSenTree(trigKit.vscp(), dpiExportTriggerIndex) : nullptr; - const auto& vifTriggeredIco - = virtIfaceTriggers.makeIfaceToSensMap(trigKit, firstVifTriggerIndex, trigKit.vscp()); const auto& vifMemberTriggeredIco = virtIfaceTriggers.makeMemberToSensMap( trigKit, firstVifMemberTriggerIndex, trigKit.vscp()); @@ -516,9 +547,9 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp, out.push_back(inputChanged); } if (varp->isWrittenByDpi()) out.push_back(dpiExportTriggered); - if (vscp->varp()->sensIfacep()) { + if (vscp->varp()->isVirtIface()) { std::vector ifaceTriggered - = findTriggeredIface(vscp, vifTriggeredIco, vifMemberTriggeredIco); + = findTriggeredIface(vscp, vifMemberTriggeredIco); out.insert(out.end(), ifaceTriggered.begin(), ifaceTriggered.end()); } }); @@ -526,16 +557,22 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp, // Create the eval loop const EvalLoop icoLoop = createEvalLoop( // - netlistp, "ico", "Input combinational", /* slow: */ false, trigKit, trigKit.vscp(), + netlistp, "ico", "Input combinational", /* slow: */ false, trigKit, + // Use trigger + trigKit.vscp(), nullptr, // Inner loop statements nullptr, // Prep statements: Compute the current 'ico' triggers - trigKit.newCompCall(), + [&trigKit] { + AstNodeStmt* const stmtp = trigKit.newCompBaseCall(); + if (stmtp) stmtp->addNext(trigKit.newDumpCall(trigKit.vscp(), trigKit.name(), true)); + return stmtp; + }(), // Work statements: Invoke the 'ico' function util::callVoidFunc(icoFuncp)); // Add the first iteration trigger to the trigger computation function - trigKit.addExtraTriggerAssignment(icoLoop.firstIterp, firstIterationTrigger); + trigKit.addExtraTriggerAssignment(icoLoop.firstIterp, firstIterationTrigger, false); return icoLoop.stmtsp; } @@ -567,21 +604,33 @@ void createEval(AstNetlist* netlistp, // ) { FileLine* const flp = netlistp->fileline(); - // 'createResume' consumes the contents that 'createCommit' needs, so do the right order - AstCCall* const timingCommitp = timingKit.createCommit(netlistp); + // Grab the delay scheduler variable, if any + AstVarScope* const delaySchedVscp = timingKit.getDelayScheduler(netlistp); + + // 'createResume' consumes the contents that 'createReady' needs, so do the right order + AstCCall* const timingReadyp = timingKit.createReady(netlistp); AstCCall* const timingResumep = timingKit.createResume(netlistp); // Create the active eval loop EvalLoop topLoop = createEvalLoop( // - netlistp, "act", "Active", /* slow: */ false, trigKit, actKit.m_vscp, + netlistp, "act", "Active", /* slow: */ false, trigKit, + // Use trigger + actKit.m_vscp, nullptr, // Inner loop statements nullptr, // Prep statements [&]() { // Compute the current 'act' triggers - the NBA triggers are the latched value - AstNodeStmt* stmtsp = trigKit.newCompCall(nbaKit.m_vscp); - // Commit trigger awaits from the previous iteration - if (timingCommitp) stmtsp = AstNode::addNext(stmtsp, timingCommitp->makeStmt()); + AstNodeStmt* stmtsp = trigKit.newCompBaseCall(); + AstNodeStmt* const dumpp + = stmtsp ? trigKit.newDumpCall(trigKit.vscp(), trigKit.name(), true) : nullptr; + // Mark as ready for triggered awaits + if (timingReadyp) stmtsp = AstNode::addNext(stmtsp, timingReadyp->makeStmt()); + if (AstVarScope* const vscAccp = trigKit.vscAccp()) { + stmtsp = AstNode::addNext(stmtsp, trigKit.newOrIntoCall(actKit.m_vscp, vscAccp)); + } + stmtsp = AstNode::addNext(stmtsp, trigKit.newCompExtCall(nbaKit.m_vscp)); + stmtsp = AstNode::addNext(stmtsp, dumpp); // Latch the 'act' triggers under the 'nba' triggers stmtsp = AstNode::addNext(stmtsp, trigKit.newOrIntoCall(nbaKit.m_vscp, actKit.m_vscp)); // @@ -590,17 +639,69 @@ void createEval(AstNetlist* netlistp, // // Work statements [&]() { AstNodeStmt* workp = nullptr; + if (AstVarScope* const actAccp = trigKit.vscAccp()) { + AstCMethodHard* const cCallp = new AstCMethodHard{ + flp, new AstVarRef{flp, actAccp, VAccess::WRITE}, VCMethod::UNPACKED_FILL, + new AstConst{flp, AstConst::Unsized64{}, 0}}; + cCallp->dtypeSetVoid(); + workp = AstNode::addNext(workp, cCallp->makeStmt()); + } // Resume triggered timing schedulers - if (timingResumep) workp = timingResumep->makeStmt(); + if (timingResumep) workp = AstNode::addNext(workp, timingResumep->makeStmt()); // Invoke the 'act' function workp = AstNode::addNext(workp, util::callVoidFunc(actKit.m_funcp)); // return workp; }()); + // Create if there are any delays, so we can check at runtime if a #0 is unexpected + if (delaySchedVscp) { + topLoop = createEvalLoop( // + netlistp, "inact", "Inactive", /* slow: */ false, trigKit, + // Use explicit condition + nullptr, + [&]() { + // Run if any zero delays are pending + AstNodeExpr* const callp + = new AstCMethodHard{flp, new AstVarRef{flp, delaySchedVscp, VAccess::READ}, + VCMethod::SCHED_AWAITING_ZERO_DELAY}; + callp->dtypeSetBit(); + return callp; + }(), + // Inner loop statements + topLoop.stmtsp, + // Prep statements + nullptr, + // Work statements + [&]() -> AstNodeStmt* { + if (v3Global.usesZeroDelay()) { + // Resume processes watiting for #0 delay + AstCMethodHard* const callp = new AstCMethodHard{ + flp, new AstVarRef{flp, delaySchedVscp, VAccess::READWRITE}, + VCMethod::SCHED_RESUME_ZERO_DELAY}; + callp->dtypeSetVoid(); + return callp->makeStmt(); + } else { + // Assumption was that the design doesn't use #0 delays. + // Die at run-time if it does. + AstCStmt* const stmtp = new AstCStmt{flp}; + const FileLine* const locp = netlistp->topModulep()->fileline(); + const std::string& file = VIdProtect::protect(locp->filename()); + const std::string& line = std::to_string(locp->lineno()); + stmtp->add( + "VL_FATAL_MT(\"" + V3OutFormatter::quoteNameControls(file) + "\", " + line + + ", \"\", \"ZERODLY: Design Verilated with '--no-sched-zero-delay', " + + "but #0 delay executed at runtime\");"); + return stmtp; + } + }()); + } + // Create the NBA eval loop, which is the default top level loop. topLoop = createEvalLoop( // - netlistp, "nba", "NBA", /* slow: */ false, trigKit, nbaKit.m_vscp, + netlistp, "nba", "NBA", /* slow: */ false, trigKit, + // Use trigger + nbaKit.m_vscp, nullptr, // Inner loop statements topLoop.stmtsp, // Prep statements @@ -631,7 +732,7 @@ void createEval(AstNetlist* netlistp, // netlistp->nbaEventp(nullptr); netlistp->nbaEventTriggerp(nullptr); - // If a dynamic NBA is pending, clear the pending flag and fire the commit event + // If a dynamic NBA is pending, clear the pending flag and fire the ready event AstIf* const ifp = new AstIf{flp, new AstVarRef{flp, nbaEventTriggerp, VAccess::READ}}; ifp->addThensp(util::setVar(continuep, 1)); ifp->addThensp(util::setVar(nbaEventTriggerp, 0)); @@ -645,7 +746,9 @@ void createEval(AstNetlist* netlistp, // if (!obsKit.empty()) { // Create the Observed eval loop, which becomes the top level loop. topLoop = createEvalLoop( // - netlistp, "obs", "Observed", /* slow: */ false, trigKit, obsKit.m_vscp, + netlistp, "obs", "Observed", /* slow: */ false, trigKit, + // Use trigger + obsKit.m_vscp, nullptr, // Inner loop statements topLoop.stmtsp, // Prep statements @@ -669,7 +772,9 @@ void createEval(AstNetlist* netlistp, // if (!reactKit.empty()) { // Create the Reactive eval loop, which becomes the top level loop. topLoop = createEvalLoop( // - netlistp, "react", "Reactive", /* slow: */ false, trigKit, reactKit.m_vscp, + netlistp, "react", "Reactive", /* slow: */ false, trigKit, + // Use trigger + reactKit.m_vscp, nullptr, // Inner loop statements topLoop.stmtsp, // Prep statements @@ -707,17 +812,6 @@ void createEval(AstNetlist* netlistp, // //============================================================================ // Helper that builds virtual interface trigger sentrees -VirtIfaceTriggers::IfaceSensMap -VirtIfaceTriggers::makeIfaceToSensMap(const TriggerKit& trigKit, uint32_t vifTriggerIndex, - AstVarScope* trigVscp) const { - std::map map; - for (const auto& p : m_ifaceTriggers) { - map.emplace(p.first, trigKit.newExtraTriggerSenTree(trigVscp, vifTriggerIndex)); - ++vifTriggerIndex; - } - return map; -} - VirtIfaceTriggers::IfaceMemberSensMap VirtIfaceTriggers::makeMemberToSensMap(const TriggerKit& trigKit, uint32_t vifTriggerIndex, AstVarScope* trigVscp) const { @@ -846,9 +940,6 @@ void schedule(AstNetlist* netlistp) { ? extraTriggers.allocate("DPI export trigger") : std::numeric_limits::max(); const uint32_t firstVifTriggerIndex = extraTriggers.size(); - for (const auto& p : virtIfaceTriggers.m_ifaceTriggers) { - extraTriggers.allocate("virtual interface: " + p.first->name()); - } const uint32_t firstVifMemberTriggerIndex = extraTriggers.size(); for (const auto& p : virtIfaceTriggers.m_memberTriggers) { const auto& item = p.first; @@ -862,11 +953,12 @@ void schedule(AstNetlist* netlistp) { &logicRegions.m_obs, // &logicRegions.m_react, // &timingKit.m_lbs}); - const TriggerKit trigKit = TriggerKit::create(netlistp, staticp, senExprBuilder, preTreeps, - senTreeps, "act", extraTriggers, false); + const TriggerKit trigKit + = TriggerKit::create(netlistp, staticp, senExprBuilder, preTreeps, senTreeps, "act", + extraTriggers, false, v3Global.usesTiming()); // Add post updates from the timing kit - if (timingKit.m_postUpdates) trigKit.compp()->addStmtsp(timingKit.m_postUpdates); + if (timingKit.m_postUpdates) trigKit.compBasep()->addStmtsp(timingKit.m_postUpdates); if (dpiExportTriggerVscp) { trigKit.addExtraTriggerAssignment(dpiExportTriggerVscp, dpiExportTriggerIndex); @@ -901,8 +993,6 @@ void schedule(AstNetlist* netlistp) { ? trigKit.newExtraTriggerSenTree(trigKit.vscp(), dpiExportTriggerIndex) : nullptr; - const auto& vifTriggeredAct - = virtIfaceTriggers.makeIfaceToSensMap(trigKit, firstVifTriggerIndex, trigKit.vscp()); const auto& vifMemberTriggeredAct = virtIfaceTriggers.makeMemberToSensMap( trigKit, firstVifMemberTriggerIndex, trigKit.vscp()); @@ -912,9 +1002,9 @@ void schedule(AstNetlist* netlistp) { auto it = actTimingDomains.find(vscp); if (it != actTimingDomains.end()) out = it->second; if (vscp->varp()->isWrittenByDpi()) out.push_back(dpiExportTriggeredAct); - if (vscp->varp()->sensIfacep()) { + if (vscp->varp()->isVirtIface()) { std::vector ifaceTriggered - = findTriggeredIface(vscp, vifTriggeredAct, vifMemberTriggeredAct); + = findTriggeredIface(vscp, vifMemberTriggeredAct); out.insert(out.end(), ifaceTriggered.begin(), ifaceTriggered.end()); } }); @@ -940,8 +1030,6 @@ void schedule(AstNetlist* netlistp) { = dpiExportTriggerVscp ? trigKit.newExtraTriggerSenTree(trigVscp, dpiExportTriggerIndex) : nullptr; - const auto& vifTriggered - = virtIfaceTriggers.makeIfaceToSensMap(trigKit, firstVifTriggerIndex, trigVscp); const auto& vifMemberTriggered = virtIfaceTriggers.makeMemberToSensMap(trigKit, firstVifMemberTriggerIndex, trigVscp); @@ -952,9 +1040,11 @@ void schedule(AstNetlist* netlistp) { auto it = timingDomains.find(vscp); if (it != timingDomains.end()) out = it->second; if (vscp->varp()->isWrittenByDpi()) out.push_back(dpiExportTriggered); - if (vscp->varp()->sensIfacep()) { + // Sometimes virtual interfaces mix with non-virtual one so, here both have to be + // detected - look `t_virtual_interface_nba_assign` + if (vscp->varp()->sensIfacep() || vscp->varp()->isVirtIface()) { std::vector ifaceTriggered - = findTriggeredIface(vscp, vifTriggered, vifMemberTriggered); + = findTriggeredIface(vscp, vifMemberTriggered); out.insert(out.end(), ifaceTriggered.begin(), ifaceTriggered.end()); } }); @@ -993,6 +1083,46 @@ void schedule(AstNetlist* netlistp) { createEval(netlistp, icoLoopp, trigKit, actKit, nbaKit, obsKit, reactKit, postponedFuncp, timingKit); + // Step 15: Add neccessary evaluation before awaits + if (AstCCall* const readyp = timingKit.createReady(netlistp)) { + staticp->addStmtsp(readyp->makeStmt()); + beforeTrigVisitor(netlistp, senExprBuilder, trigKit); + } else { + // beforeTrigVisitor clears Sentree pointers in AstCAwaits (as these sentrees will get + // deleted later) if there was no need to call it, SenTrees have to be cleaned manually + netlistp->foreach([](AstCAwait* const cAwaitp) { cAwaitp->clearSentreep(); }); + } + if (AstVarScope* const trigAccp = trigKit.vscAccp()) { + // Copy trigger vector to accumulator at the end of static initialziation so, + // triggers fired during initialization persist to the first resume. + const AstUnpackArrayDType* const trigAccDTypep + = VN_AS(trigAccp->dtypep(), UnpackArrayDType); + UASSERT_OBJ( + trigAccDTypep->right() == 0, trigAccp, + "Expected that trigger vector and accumulator start elements enumeration from 0"); + UASSERT_OBJ(trigAccDTypep->left() >= 0, trigAccp, + "Expected that trigger vector and accumulator has no negative indexes"); + FileLine* const flp = trigAccp->fileline(); + AstVarScope* const vscp = netlistp->topScopep()->scopep()->createTemp("__Vi", 32); + AstLoop* const loopp = new AstLoop{flp}; + loopp->addStmtsp( + new AstAssign{flp, + new AstArraySel{flp, new AstVarRef{flp, trigAccp, VAccess::WRITE}, + new AstVarRef{flp, vscp, VAccess::READ}}, + new AstArraySel{flp, new AstVarRef{flp, actKit.m_vscp, VAccess::READ}, + new AstVarRef{flp, vscp, VAccess::READ}}}); + loopp->addStmtsp(util::incrementVar(vscp)); + loopp->addStmtsp(new AstLoopTest{ + flp, loopp, + new AstLte{flp, new AstVarRef{flp, vscp, VAccess::READ}, + new AstConst{flp, AstConst::WidthedValue{}, 32, + static_cast(trigAccDTypep->left())}}}); + staticp->addStmtsp(loopp); + } + + // Step 16: Clean up + netlistp->clearStlFirstIterationp(); + // Haven't split static initializer yet util::splitCheck(staticp); diff --git a/src/V3Sched.h b/src/V3Sched.h index d1a2ef4f7..870d6d4a9 100644 --- a/src/V3Sched.h +++ b/src/V3Sched.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -184,10 +184,12 @@ struct LogicReplicas final { // "Extra" triggers, with "Sense" triggers taking up the bulk of the bits. // class TriggerKit final { +public: // Triggers are storead as an UnpackedArray with a fixed word size static constexpr uint32_t WORD_SIZE_LOG2 = 6; // 64-bits / VL_QUADSIZE static constexpr uint32_t WORD_SIZE = 1 << WORD_SIZE_LOG2; +private: const std::string m_name; // TriggerKit name const bool m_slow; // TriggerKit is for schedulign 'slow' code const uint32_t m_nSenseWords; // Number of words for Sense triggers @@ -195,6 +197,8 @@ class TriggerKit final { const uint32_t m_nPreWords; // Number of words for 'pre' part const uint32_t m_nVecWords = m_nSenseWords + m_nExtraWords; // Number of words in 'vec' part + // SenItems to corresponding bit indexes + std::unordered_map, size_t> m_senItem2TrigIdx; // Data type of a single trigger word AstNodeDType* m_wordDTypep = nullptr; // Data type of a trigger vector holding one copy of all triggers @@ -204,8 +208,14 @@ class TriggerKit final { AstUnpackArrayDType* m_trigExtDTypep = nullptr; // The AstVarScope representing the extended trigger vector AstVarScope* m_vscp = nullptr; - // The AstCFunc that computes the current active triggers - AstCFunc* m_compp = nullptr; + // The AstVarScope representing the trigger accumulator vector + // It is used to accumulate triggers that were found fired and cleared in beforeTrigger's + // in current 'act' region iteration + AstVarScope* m_vscAccp = nullptr; + // The AstCFunc that computes the current active base triggers + AstCFunc* m_compVecp = nullptr; + // The AstCFunc that computes the current active extended triggers + AstCFunc* m_compExtp = nullptr; // The AstCFunc that dumps a trigger vector AstCFunc* m_dumpp = nullptr; // The AstCFunc that dumps an exended trigger vector - create lazily @@ -214,8 +224,7 @@ class TriggerKit final { mutable AstCFunc* m_anySetVecp = nullptr; mutable AstCFunc* m_anySetExtp = nullptr; // The AstCFunc setting bits in a trigger vector that are set in another - create lazily - mutable AstCFunc* m_orIntoVecp = nullptr; - mutable AstCFunc* m_orIntoExtp = nullptr; + mutable std::array m_orIntoVecps = {nullptr}; // The AstCFunc setting a trigger vector to all zeroes - create lazily mutable AstCFunc* m_clearp = nullptr; @@ -228,13 +237,15 @@ class TriggerKit final { AstCFunc* createDumpExtFunc() const; AstCFunc* createAnySetFunc(AstUnpackArrayDType* const dtypep) const; AstCFunc* createClearFunc() const; - AstCFunc* createOrIntoFunc(AstUnpackArrayDType* const iDtypep) const; + AstCFunc* createOrIntoFunc(AstUnpackArrayDType* const oDtypep, + AstUnpackArrayDType* const iDtypep) const; // Create an AstSenTree that is sensitive to the given trigger indices AstSenTree* newTriggerSenTree(AstVarScope* vscp, const std::vector& indices) const; TriggerKit(const std::string& name, bool slow, uint32_t nSenseWords, uint32_t nExtraWords, - uint32_t nPreWords); + uint32_t nPreWords, + std::unordered_map, size_t> senItem2TrigIdx, bool useAcc); VL_UNCOPYABLE(TriggerKit); TriggerKit& operator=(TriggerKit&&) = delete; @@ -258,6 +269,9 @@ public: } uint32_t size() const { return m_descriptions.size(); } }; + // Generates list of assignments that fills + static AstAssign* createSenTrigVecAssignment(AstVarScope* const target, + std::vector& trigps); // Create a TriggerKit for the given AstSenTree vector static TriggerKit create(AstNetlist* netlistp, // @@ -267,11 +281,17 @@ public: const std::vector& senTreeps, // const string& name, // const ExtraTriggers& extraTriggers, // - bool slow); + bool slow, // + bool useAcc); // ACCESSORS AstVarScope* vscp() const { return m_vscp; } - AstCFunc* compp() const { return m_compp; } + AstVarScope* vscAccp() const { return m_vscAccp; } + size_t senItem2TrigIdx(const AstSenItem* senItemp) const { + return m_senItem2TrigIdx.at(*senItemp); + } + AstCFunc* compBasep() const { return m_compVecp; } + const std::string& name() const { return m_name; } const std::unordered_map& mapPre() const { return m_mapPre; } const std::unordered_map& mapVec() const { return m_mapVec; } @@ -281,7 +301,8 @@ public: AstNodeStmt* newClearCall(AstVarScope* vscp) const; AstNodeStmt* newOrIntoCall(AstVarScope* op, AstVarScope* ip) const; // Helpers for code generation - AstNodeStmt* newCompCall(AstVarScope* vscp = nullptr) const; + AstNodeStmt* newCompBaseCall() const; + AstNodeStmt* newCompExtCall(AstVarScope* vscp) const; AstNodeStmt* newDumpCall(AstVarScope* vscp, const std::string& tag, bool debugOnly) const; // Create a new (non-extended) trigger vector - might return nullptr if there are no triggers AstVarScope* newTrigVec(const std::string& name) const; @@ -290,13 +311,13 @@ public: AstSenTree* newExtraTriggerSenTree(AstVarScope* vscp, uint32_t index) const; // Set then extra trigger bit at 'index' to the value of 'vscp', then set 'vscp' to 0 - void addExtraTriggerAssignment(AstVarScope* vscp, uint32_t index) const; + void addExtraTriggerAssignment(AstVarScope* vscp, uint32_t index, bool clear = true) const; }; // Everything needed for combining timing with static scheduling. class TimingKit final { AstCFunc* m_resumeFuncp = nullptr; // Global timing resume function - AstCFunc* m_commitFuncp = nullptr; // Global timing commit function + AstCFunc* m_readyFuncp = nullptr; // Global timing ready function // Additional var sensitivities for V3Order std::map> m_externalDomains; @@ -308,10 +329,12 @@ public: // Remaps external domains using the specified trigger map std::map> remapDomains( const std::unordered_map& trigMap) const VL_MT_DISABLED; + // Get the delay scheduler variable + AstVarScope* getDelayScheduler(AstNetlist* const netlistp) VL_MT_DISABLED; // Creates a timing resume call (if needed, else returns null) AstCCall* createResume(AstNetlist* const netlistp) VL_MT_DISABLED; - // Creates a timing commit call (if needed, else returns null) - AstCCall* createCommit(AstNetlist* const netlistp) VL_MT_DISABLED; + // Creates a timing ready call (if needed, else returns null) + AstCCall* createReady(AstNetlist* const netlistp) VL_MT_DISABLED; TimingKit() = default; TimingKit(LogicByScope&& lbs, AstNodeStmt* postUpdates, @@ -338,15 +361,10 @@ class VirtIfaceTriggers final { }; public: - using IfaceSensMap = std::map; using IfaceMemberSensMap = std::map; - std::vector> m_ifaceTriggers; std::vector> m_memberTriggers; - void addIfaceTrigger(const AstIface* ifacep, AstVarScope* vscp) { - m_ifaceTriggers.emplace_back(ifacep, vscp); - } void addMemberTrigger(const AstIface* ifacep, const AstVar* memberp, AstVarScope* vscp) { m_memberTriggers.emplace_back(IfaceMember{ifacep, memberp}, vscp); } @@ -362,9 +380,6 @@ public: IfaceMemberSensMap makeMemberToSensMap(const TriggerKit& trigKit, uint32_t vifTriggerIndex, AstVarScope* trigVscp) const; - IfaceSensMap makeIfaceToSensMap(const TriggerKit& trigKit, uint32_t vifTriggerIndex, - AstVarScope* trigVscp) const; - VL_UNCOPYABLE(VirtIfaceTriggers); VirtIfaceTriggers() = default; VirtIfaceTriggers(VirtIfaceTriggers&&) = default; @@ -411,6 +426,9 @@ void splitCheck(AstCFunc* ofuncp); AstIf* createIfFromSenTree(AstSenTree* senTreep); } // namespace util +void beforeTrigVisitor(AstNetlist* netlistp, SenExprBuilder& senExprBuilder, + const TriggerKit& trigKit); + } // namespace V3Sched #endif // Guard diff --git a/src/V3SchedAcyclic.cpp b/src/V3SchedAcyclic.cpp index c867fc872..c91f97b83 100644 --- a/src/V3SchedAcyclic.cpp +++ b/src/V3SchedAcyclic.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -35,14 +35,17 @@ #include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT +#include "V3EmitV.h" +#include "V3File.h" #include "V3Graph.h" #include "V3Sched.h" #include "V3SenTree.h" #include "V3SplitVar.h" #include "V3Stats.h" -#include +#include #include +#include #include #include @@ -222,13 +225,31 @@ bool isCut(const SchedAcyclicVarVertex* vtxp) { } std::vector findCutVertices(Graph* graphp) { + // List of cut vertices being computed here std::vector result; const VNUser1InUse user1InUse; // bool: already added to result + + // Statistics + size_t nCyclicVtxs = 0; // Number of vertices that are part of an SCC (cycle) + size_t nCyclicVars = 0; // Number of variables that are part of an SCC (cycle) + std::unordered_set sccs; // Unique SCC colors + for (V3GraphVertex& vtx : graphp->vertices()) { + if (!vtx.color()) continue; // Not part of an SCC (cycle), can ignore + ++nCyclicVtxs; if (SchedAcyclicVarVertex* const vvtxp = vtx.cast()) { + ++nCyclicVars; if (!vvtxp->vscp()->user1SetOnce() && isCut(vvtxp)) result.push_back(vvtxp); } + // Don't bother counting if not dumping statistics + if (v3Global.opt.stats()) sccs.insert(vtx.color()); } + + V3Stats::addStat("Scheduling, Cycles, cyclic variables", nCyclicVars); + V3Stats::addStat("Scheduling, Cycles, cyclic logic blocks", nCyclicVtxs - nCyclicVars); + V3Stats::addStat("Scheduling, Cycles, unique SCCs", sccs.size()); + V3Stats::addStat("Scheduling, Cycles, cut variables", result.size()); + return result; } @@ -367,6 +388,61 @@ void reportCycles(Graph* graphp, const std::vector& cutV } } +void dumpSccs(V3Graph* graphp) { + // Map from SCC color to vertices in that SCC + std::map> scc2Vtxps; + + // Gather all vertices in each SCC + for (V3GraphVertex& vtx : graphp->vertices()) { + if (!vtx.color()) continue; + scc2Vtxps[vtx.color()].push_back(&vtx); + } + + // Dump Verilog for each SCC into separate files + for (const auto& pair : scc2Vtxps) { + const uint32_t color = pair.first; + const std::vector& vtxps = pair.second; + + // Open dump file + const std::string fname + = v3Global.debugFilename("sched_scc_" + std::to_string(color) + ".v"); + const std::unique_ptr ofp{V3File::new_ofstream(fname)}; + if (ofp->fail()) v3fatal("Can't write file: " << fname); + + // Write header + *ofp << "// SCC " << color << ", size: " << vtxps.size() << "\n\n"; + + // Dump variables + *ofp << "//////////////////////////////////////////////////////////////////////\n"; + *ofp << "// Variables\n"; + *ofp << "//////////////////////////////////////////////////////////////////////\n"; + *ofp << "\n"; + for (V3GraphVertex* vtxp : vtxps) { + const SchedAcyclicVarVertex* const vvtxp = vtxp->cast(); + if (!vvtxp) continue; + AstVarScope* const vscp = vvtxp->vscp(); + *ofp << "// " << vscp->fileline()->ascii() << "\n"; + *ofp << "// " << vscp->prettyName() << "\n"; + V3EmitV::debugVerilogForTree(vscp->varp(), *ofp); + *ofp << "\n"; + } + + // Dump logic + *ofp << "\n"; + *ofp << "//////////////////////////////////////////////////////////////////////\n"; + *ofp << "// Logic\n"; + *ofp << "//////////////////////////////////////////////////////////////////////\n"; + *ofp << "\n"; + for (V3GraphVertex* vtxp : vtxps) { + const SchedAcyclicLogicVertex* const lvtxp = vtxp->cast(); + if (!lvtxp) continue; + *ofp << "// " << lvtxp->logicp()->fileline()->ascii() << "\n"; + V3EmitV::debugVerilogForTree(lvtxp->logicp(), *ofp); + *ofp << "\n"; + } + } +} + LogicByScope fixCuts(AstNetlist* netlistp, const std::vector& cutVertices) { // For all logic that reads a cut vertex, build a map from logic -> list of cut AstVarScope @@ -439,6 +515,9 @@ LogicByScope breakCycles(AstNetlist* netlistp, const LogicByScope& combinational // Report warnings/diagnostics reportCycles(graphp.get(), cutVertices); + // Debug dump + if (dumpLevel() >= 6) dumpSccs(graphp.get()); + // Fix cuts by converting dependent logic to use hybrid sensitivities return fixCuts(netlistp, cutVertices); } diff --git a/src/V3SchedPartition.cpp b/src/V3SchedPartition.cpp index d855af68a..1de20a5da 100644 --- a/src/V3SchedPartition.cpp +++ b/src/V3SchedPartition.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -354,7 +354,14 @@ LogicRegions partition(LogicByScope& clockedLogic, LogicByScope& combinationalLo for (V3GraphVertex& vtx : graphp->vertices()) { if (const auto lvtxp = vtx.cast()) { - LogicByScope& lbs = lvtxp->color() ? result.m_act : result.m_nba; + // Move to 'act'/'nba' based on coloring by default ... + bool toAct = lvtxp->color(); + // ... however, if a #0 delay is possible, then the 'inact' region is required, + // in which case **EVERYTHING** that is not a Post block needs to go to 'act'. + // This severely limits downstream optimizations (e.g. V3LifePost), and severely + // reduces available parallelism in 'nba' for multi-threaded execution. + if (v3Global.usesZeroDelay() && !VN_IS(lvtxp->logicp(), AlwaysPost)) toAct = true; + LogicByScope& lbs = toAct ? result.m_act : result.m_nba; AstNode* const logicp = lvtxp->logicp(); logicp->unlinkFrBack(); lbs.add(lvtxp->scopep(), lvtxp->senTreep(), logicp); diff --git a/src/V3SchedReplicate.cpp b/src/V3SchedReplicate.cpp index 959a28ab2..79596533e 100644 --- a/src/V3SchedReplicate.cpp +++ b/src/V3SchedReplicate.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -151,7 +151,7 @@ public: , m_vscp{vscp} { // Top level inputs are if (varp()->isPrimaryInish() || varp()->isSigUserRWPublic() || varp()->isWrittenByDpi() - || varp()->sensIfacep()) { + || varp()->sensIfacep() || varp()->isVirtIface()) { addDrivingRegions(INPUT); } // Currently we always execute suspendable processes at the beginning of diff --git a/src/V3SchedTiming.cpp b/src/V3SchedTiming.cpp index b18f4488b..e1c675579 100644 --- a/src/V3SchedTiming.cpp +++ b/src/V3SchedTiming.cpp @@ -6,17 +6,17 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // // Functions defined in this file are used by V3Sched.cpp to properly integrate // static scheduling with timing features. They create external domains for -// variables, remap them to trigger vectors, and create timing resume/commit +// variables, remap them to trigger vectors, and create timing resume/ready // calls for the global eval loop. There is also a function that transforms // forks into emittable constructs. // @@ -68,22 +68,39 @@ AstCCall* TimingKit::createResume(AstNetlist* const netlistp) { m_resumeFuncp->declPrivate(true); scopeTopp->addBlocksp(m_resumeFuncp); + for (const auto& p : m_lbs) { + AstActive* const activep = p.second; + activep->foreach([this](AstCMethodHard* const exprp) { + if (exprp->method() != VCMethod::SCHED_RESUME) return; + AstNodeExpr* const fromp = exprp->fromp(); + if (VN_AS(fromp->dtypep(), BasicDType)->keyword() + != VBasicDTypeKwd::TRIGGER_SCHEDULER) { + return; + } + AstCMethodHard* const moveToResumep = new AstCMethodHard{ + fromp->fileline(), fromp->cloneTree(false), + VCMethod::SCHED_MOVE_TO_RESUME_QUEUE, + exprp->pinsp() ? exprp->pinsp()->cloneTree(true) : nullptr}; + moveToResumep->dtypeSetVoid(); + m_resumeFuncp->addStmtsp(moveToResumep->makeStmt()); + }); + } + // Put all the timing actives in the resume function AstIf* dlyShedIfp = nullptr; for (auto& p : m_lbs) { AstActive* const activep = p.second; - // Hack to ensure that #0 delays will be executed after any other `act` events. - // Just handle delayed coroutines last. + // Resume time delays last. For no particular reason other than + // that's what we used to do prior to proper #0 support. AstVarRef* const schedrefp = VN_AS( VN_AS(VN_AS(activep->stmtsp(), StmtExpr)->exprp(), CMethodHard)->fromp(), VarRef); - AstIf* const ifp = V3Sched::util::createIfFromSenTree(activep->sentreep()); - ifp->addThensp(activep->stmtsp()->unlinkFrBackWithNext()); - + AstNode* const actionp = activep->stmtsp()->unlinkFrBackWithNext(); if (schedrefp->varScopep()->dtypep()->basicp()->isDelayScheduler()) { - dlyShedIfp = ifp; + dlyShedIfp = V3Sched::util::createIfFromSenTree(activep->sentreep()); + dlyShedIfp->addThensp(actionp); } else { - m_resumeFuncp->addStmtsp(ifp); + m_resumeFuncp->addStmtsp(actionp); } } if (dlyShedIfp) m_resumeFuncp->addStmtsp(dlyShedIfp); @@ -96,11 +113,24 @@ AstCCall* TimingKit::createResume(AstNetlist* const netlistp) { return callp; } -//============================================================================ -// Creates a timing commit call (if needed, else returns null) +AstVarScope* TimingKit::getDelayScheduler(AstNetlist* const netlistp) { + for (auto& p : m_lbs) { + AstActive* const ap = p.second; + // TODO: this triple VN_AS expression is ridiculous + AstVarRef* const schedrefp + = VN_AS(VN_AS(VN_AS(ap->stmtsp(), StmtExpr)->exprp(), CMethodHard)->fromp(), VarRef); + AstVarScope* const vscp = schedrefp->varScopep(); + if (vscp->dtypep()->basicp()->isDelayScheduler()) return vscp; + } + // None found. Design doesn't use any time delays + return nullptr; +} -AstCCall* TimingKit::createCommit(AstNetlist* const netlistp) { - if (!m_commitFuncp) { +//============================================================================ +// Creates a timing ready call (if needed, else returns null) + +AstCCall* TimingKit::createReady(AstNetlist* const netlistp) { + if (!m_readyFuncp) { for (auto& p : m_lbs) { AstActive* const activep = p.second; auto* const resumep = VN_AS(VN_AS(activep->stmtsp(), StmtExpr)->exprp(), CMethodHard); @@ -111,67 +141,35 @@ AstCCall* TimingKit::createCommit(AstNetlist* const netlistp) { || schedulerp->dtypep()->basicp()->isDynamicTriggerScheduler(), schedulerp, "Unexpected type"); if (!schedulerp->dtypep()->basicp()->isTriggerScheduler()) continue; - // Create the global commit function only if we have trigger schedulers - if (!m_commitFuncp) { + // Create the global ready function only if we have trigger schedulers + if (!m_readyFuncp) { AstScope* const scopeTopp = netlistp->topScopep()->scopep(); - m_commitFuncp - = new AstCFunc{netlistp->fileline(), "_timing_commit", scopeTopp, ""}; - m_commitFuncp->dontCombine(true); - m_commitFuncp->isLoose(true); - m_commitFuncp->isConst(false); - m_commitFuncp->declPrivate(true); - scopeTopp->addBlocksp(m_commitFuncp); + m_readyFuncp = new AstCFunc{netlistp->fileline(), "_timing_ready", scopeTopp, ""}; + m_readyFuncp->dontCombine(true); + m_readyFuncp->isLoose(true); + m_readyFuncp->isConst(false); + m_readyFuncp->declPrivate(true); + scopeTopp->addBlocksp(m_readyFuncp); } - // There is a somewhat complicate dance here. Given a suspendable - // process of the form: - // ->evntA; - // $display("Fired evntA"); - // @(evntA or evntB); - // The firing of the event cannot trigger the event control - // following it, as the process is not yet sensitive to the event - // when it fires (same applies for change detects). The way the - // scheduling works, the @evnt will suspend the process before - // the firing of the event is recognized on the next iteration of - // the 'act' loop, and hence could incorrectly resume the @evnt - // statement. To make this work, whenever a process suspends, it - // goes into an "uncommitted" state, so it cannot be resumed - // immediately on the next iteration of the 'act' loop, which is - // what we want. The question then is, when should the suspended - // process be "committed" and hence possible to be resumed. This is - // done when it is know for sure the suspending expression was not - // triggered on the current iteration of the 'act' loop. With - // multiple events in the suspending expression, all events need - // to be not triggered to safely commit the suspended process. - // - // This is is consistent with IEEE scheduling semantics, and - // behaves as if the above was executed as: - // ->evntA; - // $display("Fired evnt"); - // ... all other statements in the 'act' loop that might fire evntA or evntB ... - // @(evntA or evntB); - // which is a valid execution. Race conditions be fun to debug, - // but they are a responsibility of the user. - AstSenTree* const senTreep = activep->sentreep(); FileLine* const flp = senTreep->fileline(); // Create an 'AstIf' sensitive to the suspending triggers AstIf* const ifp = V3Sched::util::createIfFromSenTree(senTreep); - m_commitFuncp->addStmtsp(ifp); + m_readyFuncp->addStmtsp(ifp); - // Commit the processes suspended on this sensitivity expression - // in the **else** branch, when the event is known to be not fired. + // Mark as ready the processes resumed on this sensitivity expression AstVarRef* const refp = new AstVarRef{flp, schedulerp, VAccess::READWRITE}; - AstCMethodHard* const callp = new AstCMethodHard{flp, refp, VCMethod::SCHED_COMMIT}; + AstCMethodHard* const callp = new AstCMethodHard{flp, refp, VCMethod::SCHED_READY}; callp->dtypeSetVoid(); if (resumep->pinsp()) callp->addPinsp(resumep->pinsp()->cloneTree(false)); - ifp->addElsesp(callp->makeStmt()); + ifp->addThensp(callp->makeStmt()); } - // We still haven't created a commit function (no trigger schedulers), return null - if (!m_commitFuncp) return nullptr; + // We still haven't created a ready function (no trigger schedulers), return null + if (!m_readyFuncp) return nullptr; } - AstCCall* const callp = new AstCCall{m_commitFuncp->fileline(), m_commitFuncp}; + AstCCall* const callp = new AstCCall{m_readyFuncp->fileline(), m_readyFuncp}; callp->dtypeSetVoid(); return callp; } @@ -223,7 +221,7 @@ class AwaitVisitor final : public VNVisitor { if (schedulerp->dtypep()->basicp()->isTriggerScheduler()) { UASSERT_OBJ(methodp->pinsp(), methodp, "Trigger method should have pins from V3Timing"); - // The first pin is the commit boolean, the rest (if any) should be debug info + // The first pin is the ready boolean, the rest (if any) should be debug info // See V3Timing for details if (AstNode* const dbginfop = methodp->pinsp()->nextp()) { if (methodp->pinsp()) addResumePins(resumep, static_cast(dbginfop)); @@ -267,7 +265,6 @@ class AwaitVisitor final : public VNVisitor { void visit(AstCAwait* nodep) override { if (AstSenTree* const sentreep = nodep->sentreep()) { if (!sentreep->user1SetOnce()) createResumeActive(nodep); - nodep->clearSentreep(); // Clear as these sentrees will get deleted later if (m_inProcess) m_processDomains.insert(sentreep); } } diff --git a/src/V3SchedTrigger.cpp b/src/V3SchedTrigger.cpp index 829c5829f..428f77457 100644 --- a/src/V3SchedTrigger.cpp +++ b/src/V3SchedTrigger.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -225,19 +225,21 @@ AstCFunc* TriggerKit::createClearFunc() const { // Done return funcp; } -AstCFunc* TriggerKit::createOrIntoFunc(AstUnpackArrayDType* const iDtypep) const { +AstCFunc* TriggerKit::createOrIntoFunc(AstUnpackArrayDType* const oDtypep, + AstUnpackArrayDType* const iDtypep) const { AstNetlist* const netlistp = v3Global.rootp(); FileLine* const flp = netlistp->topScopep()->fileline(); AstNodeDType* const u32DTypep = netlistp->findUInt32DType(); // Create function std::string name = "_trigger_orInto__" + m_name; - name += iDtypep == m_trigVecDTypep ? "" : "_ext"; + name += iDtypep == m_trigVecDTypep ? "_vec" : "_ext"; + name += oDtypep == m_trigVecDTypep ? "_vec" : "_ext"; AstCFunc* const funcp = util::makeSubFunction(netlistp, name, m_slow); funcp->isStatic(true); // Add arguments - AstVarScope* const oVscp = newArgument(funcp, m_trigVecDTypep, "out", VDirection::INOUT); + AstVarScope* const oVscp = newArgument(funcp, oDtypep, "out", VDirection::INOUT); AstVarScope* const iVscp = newArgument(funcp, iDtypep, "in", VDirection::CONSTREF); // Add loop counter variable @@ -257,10 +259,14 @@ AstCFunc* TriggerKit::createOrIntoFunc(AstUnpackArrayDType* const iDtypep) const AstNodeExpr* const oWordp = new AstArraySel{flp, rd(oVscp), rd(nVscp)}; AstNodeExpr* const iWordp = new AstArraySel{flp, rd(iVscp), rd(nVscp)}; AstNodeExpr* const rhsp = new AstOr{flp, oWordp, iWordp}; - AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, m_nVecWords}; + AstConst* const outputRangeLeftp = VN_AS(oDtypep->rangep()->leftp(), Const); + AstConst* const inputRangeLeftp = VN_AS(iDtypep->rangep()->leftp(), Const); + AstNodeExpr* const limp = outputRangeLeftp->num().toSInt() < inputRangeLeftp->num().toSInt() + ? outputRangeLeftp->cloneTreePure(false) + : inputRangeLeftp->cloneTreePure(false); loopp->addStmtsp(new AstAssign{flp, lhsp, rhsp}); loopp->addStmtsp(util::incrementVar(nVscp)); - loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(nVscp), limp}}); + loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLte{flp, rd(nVscp), limp}}); // Done return funcp; @@ -297,16 +303,16 @@ AstNodeStmt* TriggerKit::newClearCall(AstVarScope* const vscp) const { } AstNodeStmt* TriggerKit::newOrIntoCall(AstVarScope* const oVscp, AstVarScope* const iVscp) const { if (!m_nVecWords) return nullptr; - UASSERT_OBJ(oVscp->dtypep() == m_trigVecDTypep, oVscp, "Bad trigger vector type"); - AstCFunc* funcp = nullptr; - if (iVscp->dtypep() == m_trigVecDTypep) { - if (!m_orIntoVecp) m_orIntoVecp = createOrIntoFunc(m_trigVecDTypep); - funcp = m_orIntoVecp; - } else if (iVscp->dtypep() == m_trigExtDTypep) { - if (!m_orIntoExtp) m_orIntoExtp = createOrIntoFunc(m_trigExtDTypep); - funcp = m_orIntoExtp; - } else { - iVscp->v3fatalSrc("Bad trigger vector type"); + UASSERT_OBJ(iVscp->dtypep() == m_trigVecDTypep || iVscp->dtypep() == m_trigExtDTypep, iVscp, + "Bad input trigger vector type"); + UASSERT_OBJ(oVscp->dtypep() == m_trigVecDTypep || oVscp->dtypep() == m_trigExtDTypep, oVscp, + "Bad output trigger vector type"); + const size_t mask + = ((oVscp->dtypep() == m_trigExtDTypep) << 1) | (iVscp->dtypep() == m_trigExtDTypep); + AstCFunc*& funcp = m_orIntoVecps[mask]; + if (!funcp) { + funcp = createOrIntoFunc(VN_AS(oVscp->dtypep(), UnpackArrayDType), + VN_AS(iVscp->dtypep(), UnpackArrayDType)); } FileLine* const flp = v3Global.rootp()->topScopep()->fileline(); AstCCall* const callp = new AstCCall{flp, funcp}; @@ -316,13 +322,19 @@ AstNodeStmt* TriggerKit::newOrIntoCall(AstVarScope* const oVscp, AstVarScope* co return callp->makeStmt(); } -AstNodeStmt* TriggerKit::newCompCall(AstVarScope* vscp) const { +AstNodeStmt* TriggerKit::newCompBaseCall() const { if (!m_nVecWords) return nullptr; - // If there are pre triggers, we need the argument - UASSERT(!m_nPreWords || vscp, "Need latched values for pre trigger compute"); FileLine* const flp = v3Global.rootp()->topScopep()->fileline(); - AstCCall* const callp = new AstCCall{flp, m_compp}; - if (m_nPreWords) callp->addArgsp(new AstVarRef{flp, vscp, VAccess::READ}); + AstCCall* const callp = new AstCCall{flp, m_compVecp}; + callp->dtypeSetVoid(); + return callp->makeStmt(); +} + +AstNodeStmt* TriggerKit::newCompExtCall(AstVarScope* vscp) const { + if (!m_nPreWords) return nullptr; + FileLine* const flp = v3Global.rootp()->topScopep()->fileline(); + AstCCall* const callp = new AstCCall{flp, m_compExtp}; + callp->addArgsp(new AstVarRef{flp, vscp, VAccess::READ}); callp->dtypeSetVoid(); return callp->makeStmt(); } @@ -392,7 +404,7 @@ AstSenTree* TriggerKit::newExtraTriggerSenTree(AstVarScope* vscp, uint32_t index return newTriggerSenTree(vscp, {index + m_nSenseWords * WORD_SIZE}); } -void TriggerKit::addExtraTriggerAssignment(AstVarScope* vscp, uint32_t index) const { +void TriggerKit::addExtraTriggerAssignment(AstVarScope* vscp, uint32_t index, bool clear) const { index += m_nSenseWords * WORD_SIZE; const uint32_t wordIndex = index / WORD_SIZE; const uint32_t bitIndex = index % WORD_SIZE; @@ -402,23 +414,28 @@ void TriggerKit::addExtraTriggerAssignment(AstVarScope* vscp, uint32_t index) co AstNodeExpr* const wordp = new AstArraySel{flp, refp, static_cast(wordIndex)}; AstNodeExpr* const trigLhsp = new AstSel{flp, wordp, static_cast(bitIndex), 1}; AstNodeExpr* const trigRhsp = new AstVarRef{flp, vscp, VAccess::READ}; - AstNodeStmt* const setp = new AstAssign{flp, trigLhsp, trigRhsp}; - // Clear the input variable - AstNodeExpr* const vscpLhsp = new AstVarRef{flp, vscp, VAccess::WRITE}; - AstNodeExpr* const vscpRhsp = new AstConst{flp, AstConst::BitFalse{}}; - AstNodeStmt* const clrp = new AstAssign{flp, vscpLhsp, vscpRhsp}; - // Note these are added in reverse order, so 'setp' executes before 'clrp' - m_compp->stmtsp()->addHereThisAsNext(clrp); - m_compp->stmtsp()->addHereThisAsNext(setp); + AstNode* const setp = new AstAssign{flp, trigLhsp, trigRhsp}; + if (clear) { + // Clear the input variable + setp->addNext(new AstAssign{flp, new AstVarRef{flp, vscp, VAccess::WRITE}, + new AstConst{flp, AstConst::BitFalse{}}}); + } + if (AstNode* const nodep = m_compVecp->stmtsp()) { + setp->addNext(setp, nodep->unlinkFrBackWithNext()); + } + m_compVecp->addStmtsp(setp); } TriggerKit::TriggerKit(const std::string& name, bool slow, uint32_t nSenseWords, - uint32_t nExtraWords, uint32_t nPreWords) + uint32_t nExtraWords, uint32_t nPreWords, + std::unordered_map, size_t> senItem2TrigIdx, + bool useAcc) : m_name{name} , m_slow{slow} , m_nSenseWords{nSenseWords} , m_nExtraWords{nExtraWords} - , m_nPreWords{nPreWords} { + , m_nPreWords{nPreWords} + , m_senItem2TrigIdx{std::move(senItem2TrigIdx)} { // If no triggers, we don't need to generate anything if (!m_nVecWords) return; // Othewise construc the parts of the kit @@ -436,6 +453,7 @@ TriggerKit::TriggerKit(const std::string& name, bool slow, uint32_t nSenseWords, AstRange* const ep = new AstRange{flp, static_cast(m_nVecWords + m_nPreWords - 1), 0}; m_trigExtDTypep = new AstUnpackArrayDType{flp, m_wordDTypep, ep}; netlistp->typeTablep()->addTypesp(m_trigExtDTypep); + m_compExtp = util::makeSubFunction(netlistp, "_eval_triggers_ext__" + m_name, m_slow); } else { m_trigExtDTypep = m_trigVecDTypep; } @@ -443,11 +461,40 @@ TriggerKit::TriggerKit(const std::string& name, bool slow, uint32_t nSenseWords, m_vscp = scopep->createTemp("__V" + m_name + "Triggered", m_trigExtDTypep); m_vscp->varp()->isInternal(true); // The trigger computation function - m_compp = util::makeSubFunction(netlistp, "_eval_triggers__" + m_name, m_slow); + m_compVecp = util::makeSubFunction(netlistp, "_eval_triggers_vec__" + m_name, m_slow); // The debug dump function, always 'slow' m_dumpp = util::makeSubFunction(netlistp, "_dump_triggers__" + m_name, true); m_dumpp->isStatic(true); m_dumpp->ifdef("VL_DEBUG"); + if (useAcc) { + m_vscAccp = scopep->createTemp("__V" + m_name + "TriggeredAcc", m_trigVecDTypep); + m_vscAccp->varp()->isInternal(true); + } +} + +AstAssign* TriggerKit::createSenTrigVecAssignment(AstVarScope* const target, + std::vector& trigps) { + FileLine* const flp = target->fileline(); + AstAssign* trigStmtsp = nullptr; + // Assign sense triggers vector one word at a time + for (size_t i = 0; i < trigps.size(); i += WORD_SIZE) { + // Concatenate all bits in this trigger word using a balanced + for (uint32_t level = 0; level < WORD_SIZE_LOG2; ++level) { + const uint32_t stride = 1 << level; + for (uint32_t j = 0; j < WORD_SIZE; j += 2 * stride) { + trigps[i + j] = new AstConcat{trigps[i + j]->fileline(), trigps[i + j + stride], + trigps[i + j]}; + trigps[i + j + stride] = nullptr; + } + } + + // Set the whole word in the trigger vector + const int wordIndex = static_cast(i / WORD_SIZE); + AstArraySel* const aselp + = new AstArraySel{flp, new AstVarRef{flp, target, VAccess::WRITE}, wordIndex}; + trigStmtsp = AstNode::addNext(trigStmtsp, new AstAssign{flp, aselp, trigps[i]}); + } + return trigStmtsp; } TriggerKit TriggerKit::create(AstNetlist* netlistp, // @@ -457,7 +504,8 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, // const std::vector& senTreeps, // const string& name, // const ExtraTriggers& extraTriggers, // - bool slow) { + bool slow, // + bool useAcc) { // Need to gather all the unique SenItems under the given SenTrees // List of unique SenItems used by all 'senTreeps' @@ -511,7 +559,7 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, // const uint32_t nExtraWords = nExtraTriggers / WORD_SIZE; // We can now construct the trigger kit - this constructs all items that will be kept - TriggerKit kit{name, slow, nSenseWords, nExtraWords, nPreWords}; + TriggerKit kit{name, slow, nSenseWords, nExtraWords, nPreWords, senItem2TrigIdx, useAcc}; // If there are no triggers we are done if (!kit.m_nVecWords) return kit; @@ -586,7 +634,11 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, // AstNodeExpr* const wordp = new AstArraySel{flp, wr(kit.m_vscp), wrdIndex}; AstNodeExpr* const lhsp = new AstSel{flp, wordp, bitIndex, 1}; AstNodeExpr* const rhsp = new AstConst{flp, AstConst::BitTrue{}}; - initialTrigsp = AstNode::addNext(initialTrigsp, new AstAssign{flp, lhsp, rhsp}); + if (useAcc) { + initFuncp->addStmtsp(new AstAssign{flp, lhsp, rhsp}); + } else { + initialTrigsp = AstNode::addNext(initialTrigsp, new AstAssign{flp, lhsp, rhsp}); + } } // Add a debug statement for this trigger @@ -600,25 +652,7 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, // } UASSERT(trigps.size() == nSenseTriggers, "Inconsistent number of trigger expressions"); - // Assign sense triggers vector one word at a time - AstNodeStmt* trigStmtsp = nullptr; - for (size_t i = 0; i < nSenseTriggers; i += WORD_SIZE) { - // Concatenate all bits in this trigger word using a balanced - for (uint32_t level = 0; level < WORD_SIZE_LOG2; ++level) { - const uint32_t stride = 1 << level; - for (uint32_t j = 0; j < WORD_SIZE; j += 2 * stride) { - trigps[i + j] = new AstConcat{trigps[i + j]->fileline(), trigps[i + j + stride], - trigps[i + j]}; - trigps[i + j + stride] = nullptr; - } - } - - // Set the whole word in the trigger vector - const int wordIndex = static_cast(i / WORD_SIZE); - AstArraySel* const aselp = new AstArraySel{flp, wr(kit.m_vscp), wordIndex}; - trigStmtsp = AstNode::addNext(trigStmtsp, new AstAssign{flp, aselp, trigps[i]}); - } - trigps.clear(); + AstAssign* const trigStmtsp = createSenTrigVecAssignment(kit.m_vscp, trigps); // Add a print for each of the extra triggers for (unsigned i = 0; i < extraTriggers.size(); ++i) { @@ -651,18 +685,18 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, // } // Get the SenExprBuilder results - const SenExprBuilder::Results senResults = senExprBuilder.getAndClearResults(); + const SenExprBuilder::Results senResults = senExprBuilder.getResultsAndClearUpdates(); // Add the SenExprBuilder init statements to the static initialization functino for (AstNodeStmt* const nodep : senResults.m_inits) initFuncp->addStmtsp(nodep); - // Assemble the trigger computation function + // Assemble the base trigger computation function + AstScope* const scopep = netlistp->topScopep()->scopep(); { - AstCFunc* const fp = kit.m_compp; - AstScope* const scopep = netlistp->topScopep()->scopep(); + AstCFunc* const fp = kit.m_compVecp; // Profiling push if (v3Global.opt.profExec()) { - fp->addStmtsp(AstCStmt::profExecSectionPush(flp, "trig " + name)); + fp->addStmtsp(AstCStmt::profExecSectionPush(flp, "trigBase " + name)); } // Trigger computation for (AstNodeStmt* const nodep : senResults.m_preUpdates) fp->addStmtsp(nodep); @@ -677,39 +711,39 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, // ifp->addThensp(util::setVar(initVscp, 1)); ifp->addThensp(initialTrigsp); } - // If there are 'pre' triggers, compute them - if (kit.m_nPreWords) { - // Add an argument to the function that takes the latched values - AstVarScope* const latchedp - = newArgument(fp, kit.m_trigVecDTypep, "latched", VDirection::CONSTREF); - // Add loop counter variable - this can't be local because we call util::splitCheck - AstVarScope* const nVscp = scopep->createTemp("__V" + name + "TrigPreLoopCounter", 32); - nVscp->varp()->noReset(true); - // Add a loop to compute the pre words - AstLoop* const loopp = new AstLoop{flp}; - fp->addStmtsp(util::setVar(nVscp, 0)); - fp->addStmtsp(loopp); - // Loop body - AstNodeExpr* const offsetp = new AstConst{flp, kit.m_nVecWords}; - AstNodeExpr* const lIdxp = new AstAdd{flp, rd(nVscp), offsetp}; - AstNodeExpr* const lhsp = new AstArraySel{flp, wr(kit.m_vscp), lIdxp}; - AstNodeExpr* const aWordp = new AstArraySel{flp, rd(kit.m_vscp), rd(nVscp)}; - AstNodeExpr* const bWordp = new AstArraySel{flp, rd(latchedp), rd(nVscp)}; - AstNodeExpr* const rhsp = new AstAnd{flp, aWordp, new AstNot{flp, bWordp}}; - AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, nPreWords}; - loopp->addStmtsp(new AstAssign{flp, lhsp, rhsp}); - loopp->addStmtsp(util::incrementVar(nVscp)); - loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(nVscp), limp}}); - } - // Add a call to the dumping function if debug is enabled - fp->addStmtsp(kit.newDumpCall(kit.m_vscp, name, true)); // Profiling pop if (v3Global.opt.profExec()) { - fp->addStmtsp(AstCStmt::profExecSectionPop(flp, "trig " + name)); + fp->addStmtsp(AstCStmt::profExecSectionPop(flp, "trigBase " + name)); } - // Done with the trigger computation function, split as might be large util::splitCheck(fp); }; + // If there are 'pre' triggers, compute them + if (kit.m_nPreWords) { + AstCFunc* const fp = kit.m_compExtp; + // Add an argument to the function that takes the latched values + AstVarScope* const latchedp + = newArgument(fp, kit.m_trigVecDTypep, "latched", VDirection::CONSTREF); + // Add loop counter variable - this can't be local because we call util::splitCheck + AstVarScope* const nVscp = scopep->createTemp("__V" + name + "TrigPreLoopCounter", 32); + nVscp->varp()->noReset(true); + // Add a loop to compute the pre words + AstLoop* const loopp = new AstLoop{flp}; + fp->addStmtsp(util::setVar(nVscp, 0)); + fp->addStmtsp(loopp); + // Loop body + AstNodeExpr* const offsetp = new AstConst{flp, kit.m_nVecWords}; + AstNodeExpr* const lIdxp = new AstAdd{flp, rd(nVscp), offsetp}; + AstNodeExpr* const lhsp = new AstArraySel{flp, wr(kit.m_vscp), lIdxp}; + AstNodeExpr* const aWordp = new AstArraySel{flp, rd(kit.m_vscp), rd(nVscp)}; + AstNodeExpr* const bWordp = new AstArraySel{flp, rd(latchedp), rd(nVscp)}; + AstNodeExpr* const rhsp = new AstAnd{flp, aWordp, new AstNot{flp, bWordp}}; + AstNodeExpr* const limp = new AstConst{flp, AstConst::WidthedValue{}, 32, nPreWords}; + loopp->addStmtsp(new AstAssign{flp, lhsp, rhsp}); + loopp->addStmtsp(util::incrementVar(nVscp)); + loopp->addStmtsp(new AstLoopTest{flp, loopp, new AstLt{flp, rd(nVscp), limp}}); + util::splitCheck(fp); + } + // Done with the trigger computation function, split as might be large // The debug code might leak signal names, so simply delete it when using --protect-ids if (v3Global.opt.protectIds()) kit.m_dumpp->stmtsp()->unlinkFrBackWithNext()->deleteTree(); @@ -719,4 +753,286 @@ TriggerKit TriggerKit::create(AstNetlist* netlistp, // return kit; } +// Find all CAwaits, clear SenTrees inside them, generate before-trigger functions (functions that +// shall be called before awaiting for a VCMethod::SCHED_TRIGGER) and add thier calls before +// proper CAwaits +class AwaitBeforeTrigVisitor final : public VNVisitor { + const VNUser1InUse m_user1InUse; + + /** + * AstCAwait::user1() -> bool. True if node has been visited + * AstSenTree::user1p() -> AstCFunc*. Function that has to be called before awaiting + * for CAwait pointing to this SenTree + * AstCFunc::user1p() -> AstVarScope* Function's local temporary extended trigger + * vector variable scope + */ + + // Netlist - needed for using util::makeSubFunction() + AstNetlist* const m_netlistp; + // Trigger kit - for accessing trigger vectors and mapping senItems to thier indexes + const TriggerKit& m_trigKit; + // Expression builder - for building expressions from SenItems + SenExprBuilder& m_senExprBuilder; + // Generator of unique names for before-trigger function + V3UniqueNames m_beforeTriggerFuncUniqueName; + + // Vector containing every generated CFuncs and related SenTree + std::vector> m_generatedFuncs; + // Vector containing SenTrees and coresponding scheduler + std::vector> m_senTreeToSched; + // Map containing vectors of SenItems that share the same prevValue variable + std::unordered_map, std::vector> m_senExprToSenItem; + + // Returns node which is used for grouping SenItems in `m_senExprToSenItem` + static AstNode* getSenHashNode(const AstSenItem* const nodep) { + if (AstVarRef* const varRefp = VN_CAST(nodep->sensp(), VarRef)) return varRefp; + return nodep->sensp(); + } + + // Populates `m_senExprToSenItem` with every group of SenItems that share the same prevValue + // variable. Groups that contain only one type of an edge are omitted. + void fillSenExprToSenItem() { + for (auto senTreeSched : m_senTreeToSched) { + AstSenTree* const senTreep = senTreeSched.first; + + for (AstSenItem* senItemp = senTreep->sensesp(); senItemp; + senItemp = VN_AS(senItemp->nextp(), SenItem)) { + const VEdgeType edge = senItemp->edgeType(); + if (edge.anEdge() || edge == VEdgeType::ET_CHANGED + || edge == VEdgeType::ET_HYBRID) { + m_senExprToSenItem[*getSenHashNode(senItemp)].push_back(senItemp); + } + } + } + + std::vector> toRemove; + for (const auto& senExprToSenTree : m_senExprToSenItem) { + std::vector senItemps = senExprToSenTree.second; + toRemove.push_back(senExprToSenTree.first); + for (size_t i = 1; i < senItemps.size(); ++i) { + if (senItemps[i]->edgeType() != senItemps[i - 1]->edgeType()) { + toRemove.pop_back(); + break; + } + } + } + for (VNRef it : toRemove) m_senExprToSenItem.erase(it); + } + + // For set of bits indexes (of sensitivity vector) return map from those indexes to set + // of schedulers sensitive to these indexes. Indices are split into word index and bit + // masking this index within given word + std::map>> + getUsedTriggersToTrees(const std::set& usedTriggers) { + std::map>> usedTrigsToUsingTrees; + for (auto senTreeSched : m_senTreeToSched) { + const AstSenTree* const senTreep = senTreeSched.first; + AstNodeExpr* const shedp = senTreeSched.second; + + // Find all common SenItem indexes for `senTreep` and `usedTriggers` + for (AstSenItem* senItemp = senTreep->sensesp(); senItemp; + senItemp = VN_AS(senItemp->nextp(), SenItem)) { + const size_t idx = m_trigKit.senItem2TrigIdx(senItemp); + if (usedTriggers.find(idx) != usedTriggers.end()) { + usedTrigsToUsingTrees[idx / TriggerKit::WORD_SIZE] + [1 << (idx % TriggerKit::WORD_SIZE)] + .push_back(shedp); + } + } + } + if (VL_UNLIKELY(v3Global.opt.debugCheck())) { + for (const auto& triggersToTrees : usedTrigsToUsingTrees) { + for (const auto& bitsToTrees : triggersToTrees.second) { + const std::set exprps{bitsToTrees.second.begin(), + bitsToTrees.second.end()}; + UASSERT(bitsToTrees.second.size() == exprps.size(), + "There is a SenTree with two SenItems indicating to the same bit"); + } + } + } + return usedTrigsToUsingTrees; + } + + // Returns a CCall to a before-trigger function for a given SenTree, + // Constructs such a function if it doesn't exist yet + AstCCall* getBeforeTriggerStmt(AstSenTree* const senTreep) { + FileLine* const flp = senTreep->fileline(); + if (!senTreep->user1p()) { + AstCFunc* const funcp = util::makeSubFunction( + m_netlistp, m_beforeTriggerFuncUniqueName.get(senTreep), false); + senTreep->user1p(funcp); + + // Create a local temporary extended vector + AstVarScope* const vscAccp = m_trigKit.vscAccp(); + AstVarScope* const tmpp = vscAccp->scopep()->createTempLike("__VTmp", vscAccp); + AstVar* const tmpVarp = tmpp->varp()->unlinkFrBack(); + funcp->user1p(tmpp); + funcp->addVarsp(tmpVarp); + // This function can be called multiple times, and accesses model state, which + // violates the assumption made in V3Life that there is no such function. + funcp->noLife(true); + tmpVarp->funcLocal(true); + tmpVarp->noReset(true); + + AstVar* const argp = new AstVar{flp, VVarType::BLOCKTEMP, "__VeventDescription", + senTreep->findBasicDType(VBasicDTypeKwd::CHARPTR)}; + argp->funcLocal(true); + argp->direction(VDirection::INPUT); + funcp->addArgsp(argp); + // Scope is created in the constructor after iterate finishes + + m_generatedFuncs.emplace_back(funcp, senTreep); + } + AstCCall* const callp = new AstCCall{flp, VN_AS(senTreep->user1p(), CFunc)}; + callp->dtypeSetVoid(); + return callp; + } + + void visit(AstCAwait* const nodep) override { + if (nodep->user1SetOnce()) return; + + // Check whether it is a CAwait for a VCMethod::SCHED_TRIGGER + if (const AstCMethodHard* const cMethodHardp = VN_CAST(nodep->exprp(), CMethodHard)) { + if (cMethodHardp->method() == VCMethod::SCHED_TRIGGER) { + AstCCall* const beforeTrigp = getBeforeTriggerStmt(nodep->sentreep()); + + // Add eventDescription argument value to a CCall - it is used for --runtime-debug + AstNode* const pinp = cMethodHardp->pinsp()->nextp()->nextp(); + UASSERT_OBJ(pinp, cMethodHardp, "No event description"); + beforeTrigp->addArgsp(VN_AS(pinp, NodeExpr)->cloneTree(false)); + + // Call the before-trigger function before the CAwait + nodep->addHereThisAsNext(beforeTrigp->makeStmt()); + m_senTreeToSched.emplace_back(nodep->sentreep(), cMethodHardp->fromp()); + } + } + nodep->clearSentreep(); // Clear as these sentrees will get deleted later + iterate(nodep); + } + + void visit(AstNode* const nodep) override { iterateChildren(nodep); } + +public: + AwaitBeforeTrigVisitor(AstNetlist* netlistp, SenExprBuilder& senExprBuilder, + const TriggerKit& trigKit) + : m_netlistp{netlistp} + , m_trigKit{trigKit} + , m_senExprBuilder{senExprBuilder} + , m_beforeTriggerFuncUniqueName{"__VbeforeTrig"} { + iterate(netlistp); + + fillSenExprToSenItem(); + + std::vector trigps; + std::set usedTriggers; + // In each of before-trigger functions check if anything was triggered and mark as ready + // triggered schedulers + for (const auto& funcToUsedTriggers : m_generatedFuncs) { + AstCFunc* const funcp = funcToUsedTriggers.first; + AstVarScope* const vscp = VN_AS(funcp->user1p(), VarScope); + FileLine* const flp = funcp->fileline(); + + // Generate trigger evaluation + { + AstSenTree* const senTreep = funcToUsedTriggers.second; + // Puts `exprp` at `pos` and makes sure that trigps.size() is multiple of + // TriggerKit::WORD_SIZE + const auto emplaceAt + = [flp, &trigps, &usedTriggers](AstNodeExpr* const exprp, const size_t pos) { + const size_t targetSize + = vlstd::roundUpToMultipleOf(pos + 1); + if (trigps.capacity() < targetSize) trigps.reserve(targetSize * 2); + while (trigps.size() < targetSize) { + trigps.push_back(new AstConst{flp, AstConst::BitFalse{}}); + } + trigps[pos]->deleteTree(); + trigps[pos] = exprp; + usedTriggers.insert(pos); + }; + + // Find all trigger indexes of SenItems inside `senTreep` + // and add them to `trigps` and `usedTriggers` + for (const AstSenItem* itemp = senTreep->sensesp(); itemp; + itemp = VN_AS(itemp->nextp(), SenItem)) { + const size_t idx = m_trigKit.senItem2TrigIdx(itemp); + emplaceAt(m_senExprBuilder.build(itemp).first, idx); + auto iter = m_senExprToSenItem.find(*getSenHashNode(itemp)); + if (iter != m_senExprToSenItem.end()) { + for (AstSenItem* const additionalItemp : iter->second) { + const size_t idx = m_trigKit.senItem2TrigIdx(additionalItemp); + emplaceAt(m_senExprBuilder.build(additionalItemp).first, idx); + } + } + } + + // Fill the function with neccessary statements + SenExprBuilder::Results results = m_senExprBuilder.getResultsAndClearUpdates(); + for (AstNodeStmt* const stmtsp : results.m_inits) funcp->addStmtsp(stmtsp); + for (AstNodeStmt* const stmtsp : results.m_preUpdates) funcp->addStmtsp(stmtsp); + funcp->addStmtsp(TriggerKit::createSenTrigVecAssignment(vscp, trigps)); + trigps.clear(); + for (AstNodeStmt* const stmtsp : results.m_postUpdates) funcp->addStmtsp(stmtsp); + } + + std::map>> usedTrigsToUsingTrees + = getUsedTriggersToTrees(usedTriggers); + usedTriggers.clear(); + + // Helper returning expression getting array index `idx` from `scocep` with access + // `access` + const auto getIdx = [flp](AstVarScope* const scocep, VAccess access, size_t idx) { + return new AstArraySel{flp, new AstVarRef{flp, scocep, access}, + new AstConst{flp, AstConst::Unsized64{}, idx}}; + }; + + // Get eventDescription argument + AstVarScope* const argpVscp = new AstVarScope{flp, funcp->scopep(), funcp->argsp()}; + funcp->scopep()->addVarsp(argpVscp); + + // Mark as ready triggered schedulers + for (const auto& triggersToTrees : usedTrigsToUsingTrees) { + const size_t word = triggersToTrees.first; + + for (const auto& bitsToTrees : triggersToTrees.second) { + const size_t bit = bitsToTrees.first; + const auto& schedulers = bitsToTrees.second; + + // Check if given bit is fired - single bits are checked since + // usually there is only a few of them (only one most of the times as we await + // only for one event) + AstConst* const maskConstp = new AstConst{flp, AstConst::Unsized64{}, bit}; + AstAnd* const condp + = new AstAnd{flp, getIdx(vscp, VAccess::READ, word), maskConstp}; + AstIf* const ifp = new AstIf{flp, condp}; + + // Call ready() on each scheduler sensitive to `condp` + for (AstNodeExpr* const schedp : schedulers) { + AstCMethodHard* const callp = new AstCMethodHard{ + flp, schedp->cloneTree(false), VCMethod::SCHED_READY}; + callp->dtypeSetVoid(); + callp->addPinsp(new AstVarRef{flp, argpVscp, VAccess::READ}); + ifp->addThensp(callp->makeStmt()); + } + funcp->addStmtsp(ifp); + } + } + + AstVarScope* const vscAccp = m_trigKit.vscAccp(); + // Add touched values to accumulator + for (const auto& triggersToTrees : usedTrigsToUsingTrees) { + const size_t word = triggersToTrees.first; + funcp->addStmtsp(new AstAssign{flp, getIdx(vscAccp, VAccess::WRITE, word), + new AstOr{flp, getIdx(vscAccp, VAccess::READ, word), + getIdx(vscp, VAccess::READ, word)}}); + } + } + } + ~AwaitBeforeTrigVisitor() override = default; +}; + +void beforeTrigVisitor(AstNetlist* netlistp, SenExprBuilder& senExprBuilder, + const TriggerKit& trigKit) { + AwaitBeforeTrigVisitor{netlistp, senExprBuilder, trigKit}; +} + } // namespace V3Sched diff --git a/src/V3SchedUtil.cpp b/src/V3SchedUtil.cpp index f773070ea..0f3fa30c2 100644 --- a/src/V3SchedUtil.cpp +++ b/src/V3SchedUtil.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -89,14 +89,15 @@ AstNodeStmt* checkIterationLimit(AstNetlist* netlistp, const string& name, AstVa AstNodeExpr* const condp = new AstGt{flp, counterRefp, constp}; AstIf* const ifp = new AstIf{flp, condp}; ifp->branchPred(VBranchPred::BP_UNLIKELY); - ifp->addThensp(dumpCallp); + if (dumpCallp) ifp->addThensp(dumpCallp); AstCStmt* const stmtp = new AstCStmt{flp}; ifp->addThensp(stmtp); const FileLine* const locp = netlistp->topModulep()->fileline(); const std::string& file = VIdProtect::protect(locp->filename()); const std::string& line = std::to_string(locp->lineno()); stmtp->add("VL_FATAL_MT(\"" + V3OutFormatter::quoteNameControls(file) + "\", " + line - + ", \"\", \"" + name + " region did not converge after " + std::to_string(limit) + + ", \"\", \"DIDNOTCONVERGE: " + name + + " region did not converge after '--converge-limit' of " + std::to_string(limit) + " tries\");"); return ifp; } @@ -136,11 +137,11 @@ void splitCheckFinishSubFunc(AstCFunc* ofuncp, AstCFunc* subFuncp, } bool containsAwait = false; - subFuncp->foreach([&](AstNodeExpr* exprp) { + subFuncp->foreach([&](AstNode* nodep) { // Record if it has a CAwait - if (VN_IS(exprp, CAwait)) containsAwait = true; + if (VN_IS(nodep, CAwait)) containsAwait = true; // Redirect references to arguments to the clone in the sub-function - if (AstVarRef* const refp = VN_CAST(exprp, VarRef)) { + if (AstVarRef* const refp = VN_CAST(nodep, VarRef)) { if (AstVarScope* const vscp = VN_AS(refp->varp()->user3p(), VarScope)) { refp->varp(vscp->varp()); refp->varScopep(vscp); @@ -150,9 +151,7 @@ void splitCheckFinishSubFunc(AstCFunc* ofuncp, AstCFunc* subFuncp, if (ofuncp->isCoroutine() && containsAwait) { // Wrap call with co_await subFuncp->rtnType("VlCoroutine"); - AstCAwait* const awaitp = new AstCAwait{flp, callp}; - awaitp->dtypeSetVoid(); - ofuncp->addStmtsp(awaitp->makeStmt()); + ofuncp->addStmtsp(new AstCAwait{flp, callp}); } else { ofuncp->addStmtsp(callp->makeStmt()); } diff --git a/src/V3SchedVirtIface.cpp b/src/V3SchedVirtIface.cpp index bea17d444..7d19d7c7a 100644 --- a/src/V3SchedVirtIface.cpp +++ b/src/V3SchedVirtIface.cpp @@ -7,10 +7,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -41,7 +41,8 @@ namespace { class VirtIfaceVisitor final : public VNVisitor { private: // NODE STATE - // AstIface::user1() -> AstVarScope*. Trigger var for this interface + // AstVarRef::user1() -> bool. Whether it has been visited + // AstMemberSel::user1() -> bool. Whether it has been visited const VNUser1InUse m_user1InUse; // TYPES @@ -51,47 +52,12 @@ private: // STATE AstNetlist* const m_netlistp; // Root node - AstAssign* m_trigAssignp = nullptr; // Previous/current trigger assignment - AstIface* m_trigAssignIfacep = nullptr; // Interface type whose trigger is assigned - // by m_trigAssignp - AstVar* m_trigAssignMemberVarp = nullptr; // Member pointer whose trigger is assigned V3UniqueNames m_vifTriggerNames{"__VvifTrigger"}; // Unique names for virt iface // triggers VirtIfaceTriggers m_triggers; // Interfaces and corresponding trigger vars // METHODS // For each write across a virtual interface boundary - static void foreachWrittenVirtIface(AstNode* const nodep, const OnWriteToVirtIface& onWrite) { - nodep->foreach([&](AstVarRef* const refp) { - if (refp->access().isReadOnly()) return; - if (AstIfaceRefDType* const dtypep = VN_CAST(refp->varp()->dtypep(), IfaceRefDType)) { - if (dtypep->isVirtual() && VN_IS(refp->firstAbovep(), MemberSel)) { - onWrite(refp, dtypep->ifacep()); - } - } else if (AstIface* const ifacep = refp->varp()->sensIfacep()) { - onWrite(refp, ifacep); - } - }); - } - // For each write across a virtual interface boundary (member-level tracking) - static void foreachWrittenVirtIfaceMember( - AstNode* const nodep, const std::function& onWrite) { - nodep->foreach([&](AstVarRef* const refp) { - if (refp->access().isReadOnly()) return; - if (AstIfaceRefDType* const dtypep = VN_CAST(refp->varp()->dtypep(), IfaceRefDType)) { - if (dtypep->isVirtual()) { - if (AstMemberSel* const memberSelp = VN_CAST(refp->firstAbovep(), MemberSel)) { - // Extract the member varp from the MemberSel node - AstVar* memberVarp = memberSelp->varp(); - onWrite(refp, dtypep->ifacep(), memberVarp); - } - } - } else if (AstIface* const ifacep = refp->varp()->sensIfacep()) { - AstVar* memberVarp = refp->varp(); - onWrite(refp, ifacep, memberVarp); - } - }); - } // Returns true if there is a write across a virtual interface boundary static bool writesToVirtIface(const AstNode* const nodep) { return nodep->exists([](const AstVarRef* const refp) { @@ -99,29 +65,10 @@ private: AstIfaceRefDType* const dtypep = VN_CAST(refp->varp()->dtypep(), IfaceRefDType); const bool writesToVirtIfaceMember = (dtypep && dtypep->isVirtual() && VN_IS(refp->firstAbovep(), MemberSel)); - const bool writesToIfaceSensVar = refp->varp()->sensIfacep(); + const bool writesToIfaceSensVar = refp->varp()->isVirtIface(); return writesToVirtIfaceMember || writesToIfaceSensVar; }); } - // Error on write across a virtual interface boundary - static void unsupportedWriteToVirtIfaceMember(AstNode* nodep, const char* locationp) { - if (!nodep) return; - foreachWrittenVirtIfaceMember( - nodep, [locationp](AstVarRef* const selp, AstIface*, AstVar* varp) { - selp->v3warn(E_UNSUPPORTED, - "Unsupported: Write to virtual interface in " << locationp); - }); - } - // Create trigger var for the given interface if it doesn't exist; return a write ref to it - AstVarRef* createVirtIfaceTriggerRefp(FileLine* const flp, AstIface* ifacep) { - if (!ifacep->user1()) { - AstScope* const scopeTopp = m_netlistp->topScopep()->scopep(); - AstVarScope* const vscp = scopeTopp->createTemp(m_vifTriggerNames.get(ifacep), 1); - ifacep->user1p(vscp); - m_triggers.addIfaceTrigger(ifacep, vscp); - } - return new AstVarRef{flp, VN_AS(ifacep->user1p(), VarScope), VAccess::WRITE}; - } // Create trigger reference for a specific interface member AstVarRef* createVirtIfaceMemberTriggerRefp(FileLine* const flp, AstIface* ifacep, @@ -140,14 +87,40 @@ private: return new AstVarRef{flp, existingTrigger, VAccess::WRITE}; } + template + void handleIface(T nodep) { + static_assert(std::is_same::type, + typename std::add_pointer::type>::value + || std::is_same::type, + typename std::add_pointer::type>::value, + "Node has to be of AstVarRef* or AstMemberSel* type"); + if (nodep->access().isReadOnly()) return; + if (nodep->user1SetOnce()) return; + AstIface* ifacep = nullptr; + AstVar* memberVarp = nullptr; + if (nodep->varp()->isVirtIface()) { + if (AstMemberSel* const memberSelp = VN_CAST(nodep->firstAbovep(), MemberSel)) { + ifacep = VN_AS(nodep->varp()->dtypep(), IfaceRefDType)->ifacep(); + memberVarp = memberSelp->varp(); + } + } else if ((ifacep = nodep->varp()->sensIfacep())) { + memberVarp = nodep->varp(); + } + + if (ifacep && memberVarp) { + FileLine* const flp = nodep->fileline(); + VNRelinker relinker; + nodep->unlinkFrBack(&relinker); + relinker.relink(new AstExprStmt{ + flp, + new AstAssign{flp, createVirtIfaceMemberTriggerRefp(flp, ifacep, memberVarp), + new AstConst{flp, AstConst::BitTrue{}}}, + nodep}); + } + } + // VISITORS void visit(AstNodeProcedure* nodep) override { - VL_RESTORER(m_trigAssignp); - m_trigAssignp = nullptr; - VL_RESTORER(m_trigAssignIfacep); - m_trigAssignIfacep = nullptr; - VL_RESTORER(m_trigAssignMemberVarp); - m_trigAssignMemberVarp = nullptr; // Not sure if needed, but be paranoid to match previous behavior as didn't optimize // before .. if (VN_IS(nodep, AlwaysPost) && writesToVirtIface(nodep)) { @@ -155,111 +128,8 @@ private: } iterateChildren(nodep); } - void visit(AstCFunc* nodep) override { - VL_RESTORER(m_trigAssignp); - m_trigAssignp = nullptr; - VL_RESTORER(m_trigAssignIfacep); - m_trigAssignIfacep = nullptr; - VL_RESTORER(m_trigAssignMemberVarp); - m_trigAssignMemberVarp = nullptr; - iterateChildren(nodep); - } - void visit(AstNodeIf* nodep) override { - unsupportedWriteToVirtIfaceMember(nodep->condp(), "if condition"); - { - VL_RESTORER(m_trigAssignp); - VL_RESTORER(m_trigAssignIfacep); - VL_RESTORER(m_trigAssignMemberVarp); - iterateAndNextNull(nodep->thensp()); - } - { - VL_RESTORER(m_trigAssignp); - VL_RESTORER(m_trigAssignIfacep); - VL_RESTORER(m_trigAssignMemberVarp); - iterateAndNextNull(nodep->elsesp()); - } - if (v3Global.usesTiming()) { - // Clear the trigger assignment, as there could have been timing controls in either - // branch - m_trigAssignp = nullptr; - m_trigAssignIfacep = nullptr; - m_trigAssignMemberVarp = nullptr; - } - } - void visit(AstLoop* nodep) override { - UASSERT_OBJ(!nodep->contsp(), nodep, "'contsp' only used before LinkJump"); - { - VL_RESTORER(m_trigAssignp); - VL_RESTORER(m_trigAssignIfacep); - VL_RESTORER(m_trigAssignMemberVarp); - iterateAndNextNull(nodep->stmtsp()); - } - if (v3Global.usesTiming()) { - // Clear the trigger assignment, as there could have been timing controls in the loop - m_trigAssignp = nullptr; - m_trigAssignIfacep = nullptr; - m_trigAssignMemberVarp = nullptr; - } - } - void visit(AstLoopTest* nodep) override { - unsupportedWriteToVirtIfaceMember(nodep->condp(), "loop condition"); - } - void visit(AstJumpBlock* nodep) override { - { - VL_RESTORER(m_trigAssignp); - VL_RESTORER(m_trigAssignIfacep); - VL_RESTORER(m_trigAssignMemberVarp); - iterateChildren(nodep); - } - if (v3Global.usesTiming()) { - // Clear the trigger assignment, as there could have been timing controls in the jump - // block - m_trigAssignp = nullptr; - m_trigAssignIfacep = nullptr; - m_trigAssignMemberVarp = nullptr; - } - } - void visit(AstNodeStmt* nodep) override { - if (v3Global.usesTiming() - && nodep->exists([](AstNode* nodep) { return nodep->isTimingControl(); })) { - m_trigAssignp = nullptr; - m_trigAssignIfacep = nullptr; - m_trigAssignMemberVarp = nullptr; - } - FileLine* const flp = nodep->fileline(); - - foreachWrittenVirtIfaceMember(nodep, [&](AstVarRef*, AstIface* ifacep, - AstVar* memberVarp) { - if (ifacep != m_trigAssignIfacep || memberVarp != m_trigAssignMemberVarp) { - // Write to different interface member than before - need new trigger assignment - m_trigAssignIfacep = ifacep; - m_trigAssignMemberVarp = memberVarp; - m_trigAssignp = nullptr; - } - if (!m_trigAssignp) { - m_trigAssignp - = new AstAssign{flp, createVirtIfaceMemberTriggerRefp(flp, ifacep, memberVarp), - new AstConst{flp, AstConst::BitTrue{}}}; - nodep->addNextHere(m_trigAssignp); - } - }); - // Fallback to whole-interface tracking if no member-specific assignments found - if (!m_trigAssignp) { - foreachWrittenVirtIface(nodep, [&](AstVarRef*, AstIface* ifacep) { - if (ifacep != m_trigAssignIfacep) { - m_trigAssignIfacep = ifacep; - m_trigAssignMemberVarp = nullptr; - m_trigAssignp = nullptr; - } - if (!m_trigAssignp) { - m_trigAssignp = new AstAssign{flp, createVirtIfaceTriggerRefp(flp, ifacep), - new AstConst{flp, AstConst::BitTrue{}}}; - nodep->addNextHere(m_trigAssignp); - } - }); - } - } - void visit(AstNodeExpr*) override {} // Accelerate + void visit(AstMemberSel* const nodep) override { handleIface(nodep); } + void visit(AstVarRef* const nodep) override { handleIface(nodep); } void visit(AstNode* nodep) override { iterateChildren(nodep); } public: diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp index a18a2f9a2..b10ac4999 100644 --- a/src/V3Scope.cpp +++ b/src/V3Scope.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -53,7 +53,8 @@ class ScopeVisitor final : public VNVisitor { AstCell* m_aboveCellp = nullptr; // Cell that instantiates this module AstScope* m_aboveScopep = nullptr; // Scope that instantiates this scope - std::unordered_map m_packageScopes; // Scopes for each package + std::unordered_map + m_classOrPackageScopes; // Scopes for each class or package VarScopeMap m_varScopes; // Varscopes created for each scope and var std::set> m_varRefScopes; // Varrefs-in-scopes needing fixup when done @@ -64,11 +65,15 @@ class ScopeVisitor final : public VNVisitor { for (const auto& itr : m_varRefScopes) { AstVarRef* const nodep = itr.first; AstScope* scopep = itr.second; - if (nodep->classOrPackagep()) { - const auto it2 = m_packageScopes.find(nodep->classOrPackagep()); - UASSERT_OBJ(it2 != m_packageScopes.end(), nodep, "Can't locate package scope"); + if (nodep->classOrPackagep() + && !VN_IS(nodep->classOrPackagep(), + Module)) { // Module scopes are not in m_classOrPackageScopes + const auto it2 = m_classOrPackageScopes.find(nodep->classOrPackagep()); + UASSERT_OBJ(it2 != m_classOrPackageScopes.end(), nodep, + "Can't locate class or package scope"); scopep = it2->second; } + nodep->classOrPackagep(nullptr); // No longer needed after V3Scope // Search up the scope hierarchy for the variable AstVarScope* varscp = nullptr; AstScope* searchScopep = scopep; @@ -114,7 +119,7 @@ class ScopeVisitor final : public VNVisitor { (m_aboveCellp ? static_cast(m_aboveCellp) : static_cast(nodep)) ->fileline(), nodep, scopename, m_aboveScopep, m_aboveCellp}; - if (VN_IS(nodep, Package)) m_packageScopes.emplace(nodep, m_scopep); + if (VN_IS(nodep, Package)) m_classOrPackageScopes.emplace(nodep, m_scopep); // Get list of cells before we edit, to avoid excess visits (issue #6059) std::deque cells; @@ -180,7 +185,7 @@ class ScopeVisitor final : public VNVisitor { = (m_aboveCellp ? static_cast(m_aboveCellp) : static_cast(nodep)); m_scopep = new AstScope{abovep->fileline(), m_modp, scopename, m_aboveScopep, m_aboveCellp}; - m_packageScopes.emplace(nodep, m_scopep); + m_classOrPackageScopes.emplace(nodep, m_scopep); // Create scope for the current usage of this cell AstNode::user1ClearTree(); diff --git a/src/V3Scope.h b/src/V3Scope.h index 3b07236ad..825edcfe8 100644 --- a/src/V3Scope.h +++ b/src/V3Scope.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Scoreboard.cpp b/src/V3Scoreboard.cpp index 5d1383b5a..a4ee5ae6c 100644 --- a/src/V3Scoreboard.cpp +++ b/src/V3Scoreboard.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Scoreboard.h b/src/V3Scoreboard.h index e99bd15e4..c9accfe54 100644 --- a/src/V3Scoreboard.h +++ b/src/V3Scoreboard.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h index 8ae70cb4a..4dd6634ff 100644 --- a/src/V3SenExprBuilder.h +++ b/src/V3SenExprBuilder.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -34,6 +34,7 @@ public: std::vector m_inits; // Initialization statements for previous values std::vector m_preUpdates; // Pre update assignments std::vector m_postUpdates; // Post update assignments + std::vector m_vars; // Created temporary variables }; private: @@ -71,6 +72,42 @@ private: }); } + // Check if expression contains a class member access that could be null + // (e.g., accessing an event through a class reference that may not be initialized) + static bool hasClassMemberAccess(const AstNode* const exprp) { + return exprp->exists([](const AstNode* const nodep) { + if (const AstMemberSel* const mselp = VN_CAST(nodep, MemberSel)) { + // Check if the base expression is a class reference + return mselp->fromp()->dtypep() + && VN_IS(mselp->fromp()->dtypep()->skipRefp(), ClassRefDType); + } + return false; + }); + } + + // Get the base class reference expression from a member selection chain + // Returns the outermost class reference that needs to be null-checked + // Note: Returns a pointer into the original tree - caller must clone if needed + static const AstNodeExpr* getBaseClassRef(const AstNodeExpr* exprp) { + while (exprp) { + if (const AstMemberSel* const mselp = VN_CAST(exprp, MemberSel)) { + const AstNodeExpr* const fromp = mselp->fromp(); + if (fromp->dtypep() && VN_IS(fromp->dtypep()->skipRefp(), ClassRefDType)) { + // Check if the base itself has class member access + if (hasClassMemberAccess(fromp)) { + exprp = fromp; + continue; + } + return fromp; + } + exprp = fromp; + } else { + return nullptr; + } + } + return nullptr; + } + // METHODS AstVarScope* crateTemp(AstNodeExpr* exprp) { // For readability, use the scoped signal name if the trigger is a simple AstVarRef @@ -84,9 +121,36 @@ private: } AstVarScope* const vscp = m_scopep->createTemp(name, exprp->dtypep()); vscp->varp()->isInternal(true); + m_results.m_vars.push_back(vscp->varp()); return vscp; } + // Helper to wrap a statement with a null check: if (baseRef != null) stmt + AstNodeStmt* wrapStmtWithNullCheck(FileLine* flp, AstNodeStmt* stmtp, + const AstNodeExpr* baseClassRefp) { + if (!baseClassRefp) return stmtp; + AstNodeExpr* const nullp = new AstConst{flp, AstConst::Null{}}; + // const_cast safe: cloneTree doesn't modify the source + AstNodeExpr* const checkp + = new AstNeq{flp, const_cast(baseClassRefp)->cloneTree(false), nullp}; + return new AstIf{flp, checkp, stmtp}; + } + + // Helper to wrap a trigger expression with a null check if needed + // Returns the expression wrapped in: (baseRef != null) ? expr : 0 + AstNodeExpr* wrapExprWithNullCheck(FileLine* flp, AstNodeExpr* exprp, + const AstNodeExpr* baseClassRefp) { + if (!baseClassRefp) return exprp; + AstNodeExpr* const nullp = new AstConst{flp, AstConst::Null{}}; + // const_cast safe: cloneTree doesn't modify the source + AstNodeExpr* const checkp + = new AstNeq{flp, const_cast(baseClassRefp)->cloneTree(false), nullp}; + AstNodeExpr* const falsep = new AstConst{flp, AstConst::BitFalse{}}; + AstNodeExpr* const condp = new AstCond{flp, checkp, exprp, falsep}; + condp->dtypeSetBit(); + return condp; + } + AstNodeExpr* getCurr(AstNodeExpr* exprp) { // For simple expressions like varrefs or selects, just use them directly if (isSimpleExpr(exprp)) return exprp->cloneTree(false); @@ -97,17 +161,29 @@ private: if (result.second) result.first->second = crateTemp(exprp); AstVarScope* const currp = result.first->second; + // Check if we need null guards for class member access + const AstNodeExpr* const baseClassRefp + = hasClassMemberAccess(exprp) ? getBaseClassRef(exprp) : nullptr; + // Add pre update if it does not exist yet in this round if (m_hasPreUpdate.emplace(*currp).second) { - m_results.m_preUpdates.push_back(new AstAssign{ - flp, new AstVarRef{flp, currp, VAccess::WRITE}, exprp->cloneTree(false)}); + m_results.m_preUpdates.push_back( + wrapStmtWithNullCheck(flp, + new AstAssign{flp, new AstVarRef{flp, currp, VAccess::WRITE}, + exprp->cloneTree(false)}, + baseClassRefp)); } return new AstVarRef{flp, currp, VAccess::READ}; } + AstVarScope* getPrev(AstNodeExpr* exprp) { FileLine* const flp = exprp->fileline(); const auto rdCurr = [this, exprp]() { return getCurr(exprp); }; + // Check if we need null guards for class member access + const AstNodeExpr* const baseClassRefp + = hasClassMemberAccess(exprp) ? getBaseClassRef(exprp) : nullptr; + AstNode* scopeExprp = exprp; if (AstVarRef* const refp = VN_CAST(exprp, VarRef)) scopeExprp = refp->varScopep(); // Create the 'previous value' variable @@ -115,10 +191,10 @@ private: if (pair.second) { AstVarScope* const prevp = crateTemp(exprp); pair.first->second = prevp; - // Add the initializer init + // Add the initializer init (guarded if class member access) AstAssign* const initp = new AstAssign{flp, new AstVarRef{flp, prevp, VAccess::WRITE}, exprp->cloneTree(false)}; - m_results.m_inits.push_back(initp); + m_results.m_inits.push_back(wrapStmtWithNullCheck(flp, initp, baseClassRefp)); } AstVarScope* const prevp = pair.first->second; @@ -141,9 +217,11 @@ private: AstCMethodHard* const cmhp = new AstCMethodHard{flp, wrPrev(), VCMethod::UNPACKED_ASSIGN, rdCurr()}; cmhp->dtypeSetVoid(); - m_results.m_postUpdates.push_back(cmhp->makeStmt()); + m_results.m_postUpdates.push_back( + wrapStmtWithNullCheck(flp, cmhp->makeStmt(), baseClassRefp)); } else { - m_results.m_postUpdates.push_back(new AstAssign{flp, wrPrev(), rdCurr()}); + m_results.m_postUpdates.push_back(wrapStmtWithNullCheck( + flp, new AstAssign{flp, wrPrev(), rdCurr()}, baseClassRefp)); } } @@ -154,6 +232,12 @@ private: FileLine* const flp = senItemp->fileline(); AstNodeExpr* const senp = senItemp->sensp(); + // Check if the sensitivity expression involves accessing through a class reference + // that may be null (e.g., DynScope handles created in fork blocks, or class member + // virtual interfaces). If so, we need to guard against null pointer dereference. + const AstNodeExpr* const baseClassRefp + = hasClassMemberAccess(senp) ? getBaseClassRef(senp) : nullptr; + const auto currp = [this, senp]() { return getCurr(senp); }; const auto prevp = [this, flp, senp]() { return new AstVarRef{flp, getPrev(senp), VAccess::READ}; }; @@ -169,31 +253,39 @@ private: AstCMethodHard* const resultp = new AstCMethodHard{flp, prevp(), VCMethod::UNPACKED_NEQ, currp()}; resultp->dtypeSetBit(); - return {resultp, true}; + return {wrapExprWithNullCheck(flp, resultp, baseClassRefp), true}; } - return {new AstNeq{flp, currp(), prevp()}, true}; + return {wrapExprWithNullCheck(flp, new AstNeq{flp, currp(), prevp()}, baseClassRefp), + true}; case VEdgeType::ET_BOTHEDGE: // - return {lsb(new AstXor{flp, currp(), prevp()}), false}; + return { + wrapExprWithNullCheck(flp, lsb(new AstXor{flp, currp(), prevp()}), baseClassRefp), + false}; case VEdgeType::ET_POSEDGE: // - return {lsb(new AstAnd{flp, currp(), new AstNot{flp, prevp()}}), false}; + return {wrapExprWithNullCheck(flp, + lsb(new AstAnd{flp, currp(), new AstNot{flp, prevp()}}), + baseClassRefp), + false}; case VEdgeType::ET_NEGEDGE: // - return {lsb(new AstAnd{flp, new AstNot{flp, currp()}, prevp()}), false}; + return {wrapExprWithNullCheck(flp, + lsb(new AstAnd{flp, new AstNot{flp, currp()}, prevp()}), + baseClassRefp), + false}; case VEdgeType::ET_EVENT: { UASSERT_OBJ(v3Global.hasEvents(), senItemp, "Inconsistent"); - { - // Clear 'fired' state when done - // No need to check if the event was fired, we need the flag clear regardless - AstCMethodHard* const clearp - = new AstCMethodHard{flp, currp(), VCMethod::EVENT_CLEAR_FIRED}; - clearp->dtypeSetVoid(); - m_results.m_postUpdates.push_back(clearp->makeStmt()); - } + + // Clear 'fired' state when done (guarded if class member access) + AstCMethodHard* const clearp + = new AstCMethodHard{flp, currp(), VCMethod::EVENT_CLEAR_FIRED}; + clearp->dtypeSetVoid(); + m_results.m_postUpdates.push_back( + wrapStmtWithNullCheck(flp, clearp->makeStmt(), baseClassRefp)); // Get 'fired' state AstCMethodHard* const callp = new AstCMethodHard{flp, currp(), VCMethod::EVENT_IS_FIRED}; callp->dtypeSetBit(); - return {callp, false}; + return {wrapExprWithNullCheck(flp, callp, baseClassRefp), false}; } case VEdgeType::ET_TRUE: // return {currp(), false}; @@ -230,6 +322,14 @@ public: return {resultp, firedAtInitialization}; } + Results getResultsAndClearUpdates() { + m_hasPreUpdate.clear(); + m_hasPostUpdate.clear(); + Results ans = std::move(m_results); + m_results = {}; + return ans; + } + Results getAndClearResults() { m_curr.clear(); m_prev.clear(); diff --git a/src/V3SenTree.h b/src/V3SenTree.h index 07a0d3c3a..6568a9385 100644 --- a/src/V3SenTree.h +++ b/src/V3SenTree.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Simulate.h b/src/V3Simulate.h index b751e2e65..7b16dec7f 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -458,7 +458,7 @@ private: if (const AstBasicDType* const basicp = nodep->dtypeSkipRefp()->basicp()) { AstConst cnst{nodep->fileline(), AstConst::WidthedValue{}, basicp->widthMin(), 0}; if (basicp->isZeroInit()) { - cnst.num().setAllBits0(); + cnst.num() = V3Number{nodep, basicp}; } else { cnst.num().setAllBitsX(); } @@ -574,6 +574,14 @@ private: checkNodeInfo(nodep); iterateChildrenConst(nodep); } + void visit(AstInitialAutomaticStmt* nodep) override { + checkNodeInfo(nodep); + iterateChildrenConst(nodep); + } + void visit(AstInitialStaticStmt* nodep) override { + checkNodeInfo(nodep); + iterateChildrenConst(nodep); + } void visit(AstInitialStatic* nodep) override { if (jumpingOver()) return; if (!m_params) { @@ -929,6 +937,11 @@ private: m_anyAssignComb = true; } + if (VN_IS(nodep->rhsp(), CReset)) { + initVar(VN_AS(nodep->lhsp(), VarRef)->varp()); + return; + } + iterateAndNextConstNull(nodep->rhsp()); // Value to assign handleAssignRecurse(nodep, nodep->lhsp(), nodep->rhsp()); // UINFO(9, "set " << fetchConst(nodep->rhsp())->num().ascii() << " for assign " @@ -1215,7 +1228,8 @@ private: initVar(VN_CAST(funcp->fvarp(), Var)); // Clear other automatic variables funcp->foreach([this](AstVar* varp) { - if (varp->lifetime().isAutomatic() && !varp->isIO()) initVar(varp); + if (varp->lifetime().isAutomatic() && (!varp->isIO() || varp->isFuncReturn())) + initVar(varp); }); } @@ -1362,6 +1376,7 @@ private: if (jumpingOver()) return; knownBadNodeType(nodep); } + void visit(AstGetInitialRandomSeed* nodep) override { badNodeType(nodep); } // ==== // default // These types are definitely not reducible diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp index ddc1b9be9..e203201a5 100644 --- a/src/V3Slice.cpp +++ b/src/V3Slice.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -125,6 +125,7 @@ class SliceVisitor final : public VNVisitor { nodep->v3error("Array initialization has too few elements, need element " << elemIdx); m_assignError = true; + break; } const AstNodeDType* itemRawDTypep = itemp->dtypep()->skipRefp(); const VCastable castable @@ -240,6 +241,7 @@ class SliceVisitor final : public VNVisitor { const AstUnpackArrayDType* const arrayp = VN_CAST(dtp, UnpackArrayDType); if (!arrayp) return false; if (VN_IS(stp, CvtPackedToArray)) return false; + if (VN_IS(stp, CReset)) return false; // Any isSc variables must be expanded regardless of --fno-slice const bool hasSc diff --git a/src/V3Slice.h b/src/V3Slice.h index f8ab01cb7..16f17f9aa 100644 --- a/src/V3Slice.h +++ b/src/V3Slice.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Split.cpp b/src/V3Split.cpp index 679f69f52..c3c835501 100644 --- a/src/V3Split.cpp +++ b/src/V3Split.cpp @@ -6,24 +6,19 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* -// V3Split implements two separate transformations: -// splitAlwaysAll() splits large always blocks into smaller always blocks +// V3Split transformation: +// +// splitAll() splits large always blocks into smaller always blocks // when possible (but does not change the order of statements relative // to one another.) // -// splitReorderAll() reorders statements within individual blocks -// to avoid delay vars when possible. It no longer splits always blocks. -// -// Both use a common base class, and common graph-building code to reflect -// data dependencies within an always block (the "scoreboard".) -// // The scoreboard tracks data deps as follows: // // ALWAYS @@ -56,25 +51,6 @@ // better. Later modules (V3Gate, V3Order) run faster if they aren't // handling enormous blocks with long lists of inputs and outputs. // -// Furthermore, the optional reorder routine can optimize this: -// NODEASSIGN/NODEIF/WHILE -// S1: ASSIGN {v1} <= 0. // Duplicate of below -// S2: ASSIGN {v1} <= {v0} -// S3: IF (..., -// X1: ASSIGN {v2} <= {v1} -// X2: ASSIGN {v3} <= {v2} -// We'd like to swap S2 and S3, and X1 and X2. -// -// Create a graph in split assignment order. -// v3 -breakable-> v3Dly --> X2 --> v2 -brk-> v2Dly -> X1 -> v1 -// Likewise on each "upper" statement vertex -// v3Dly & v2Dly -> S3 -> v1 & v2 -// v1 -brk-> v1Dly -> S2 -> v0 -// v1Dly -> S1 -> {empty} -// Multiple assignments to the same variable must remain in order -// -// Also vars must not be "public" and we also scoreboard nodep->isPure() -// //************************************************************************* #include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT @@ -90,6 +66,8 @@ VL_DEFINE_DEBUG_FUNCTIONS; +namespace { + //###################################################################### // Support classes @@ -444,182 +422,6 @@ private: VL_UNCOPYABLE(SplitReorderBaseVisitor); }; -class ReorderVisitor final : public SplitReorderBaseVisitor { - // CONSTRUCTORS -public: - explicit ReorderVisitor(AstNetlist* nodep) { iterate(nodep); } - ~ReorderVisitor() override = default; - - // METHODS -protected: - void makeRvalueEdges(SplitVarStdVertex* vstdp) override { - for (SplitLogicVertex* vxp : m_stmtStackps) new SplitRVEdge{&m_graph, vxp, vstdp}; - } - - void cleanupBlockGraph(AstNode* nodep) { - // Transform the graph into what we need - UINFO(5, "ReorderBlock " << nodep); - m_graph.removeRedundantEdgesMax(&V3GraphEdge::followAlwaysTrue); - - if (dumpGraphLevel() >= 9) m_graph.dumpDotFilePrefixed("reorderg_nodup", false); - - // Mark all the logic for this step - // Vertex::m_user begin: true indicates logic for this step - m_graph.userClearVertices(); - for (AstNode* nextp = nodep; nextp; nextp = nextp->nextp()) { - SplitLogicVertex* const vvertexp - = reinterpret_cast(nextp->user3p()); - vvertexp->user(true); - } - - // If a var vertex has only inputs, it's a input-only node, - // and can be ignored for coloring **this block only** - SplitEdge::incrementStep(); - pruneDepsOnInputs(); - - // For reordering this single block only, mark all logic - // vertexes not involved with this step as unimportant - for (V3GraphVertex& vertex : m_graph.vertices()) { - if (!vertex.user()) { - if (vertex.is()) { - for (V3GraphEdge& edge : vertex.inEdges()) { - SplitEdge& oedge = static_cast(edge); - oedge.setIgnoreThisStep(); - } - for (V3GraphEdge& edge : vertex.outEdges()) { - SplitEdge& oedge = static_cast(edge); - oedge.setIgnoreThisStep(); - } - } - } - } - - // Weak coloring to determine what needs to remain in order - // This follows all step-relevant edges excluding PostEdges, which are done later - m_graph.weaklyConnected(&SplitEdge::followScoreboard); - - // Add hard orderings between all nodes of same color, in the order they appeared - std::unordered_map lastOfColor; - for (AstNode* nextp = nodep; nextp; nextp = nextp->nextp()) { - SplitLogicVertex* const vvertexp - = reinterpret_cast(nextp->user3p()); - const uint32_t color = vvertexp->color(); - UASSERT_OBJ(color, nextp, "No node color assigned"); - if (lastOfColor[color]) { - new SplitStrictEdge{&m_graph, lastOfColor[color], vvertexp}; - } - lastOfColor[color] = vvertexp; - } - - // And a real ordering to get the statements into something reasonable - // We don't care if there's cutable violations here... - // Non-cutable violations should be impossible; as those edges are program-order - if (dumpGraphLevel() >= 9) m_graph.dumpDotFilePrefixed("splitg_preo", false); - m_graph.acyclic(&SplitEdge::followCyclic); - m_graph.rank(&SplitEdge::followCyclic); // Or order(), but that's more expensive - if (dumpGraphLevel() >= 9) m_graph.dumpDotFilePrefixed("splitg_opt", false); - } - - void reorderBlock(AstNode* nodep) { - // Reorder statements in the completed graph - - // Map the rank numbers into nodes they associate with - std::multimap rankMap; - int currOrder = 0; // Existing sequence number of assignment - for (AstNode* nextp = nodep; nextp; nextp = nextp->nextp()) { - const SplitLogicVertex* const vvertexp - = reinterpret_cast(nextp->user3p()); - rankMap.emplace(vvertexp->rank(), nextp); - nextp->user4(++currOrder); // Record current ordering - } - - // Is the current ordering OK? - bool leaveAlone = true; - int newOrder = 0; // New sequence number of assignment - for (auto it = rankMap.cbegin(); it != rankMap.cend(); ++it) { - const AstNode* const nextp = it->second; - if (++newOrder != nextp->user4()) leaveAlone = false; - } - if (leaveAlone) { - UINFO(6, " No changes"); - } else { - VNRelinker replaceHandle; // Where to add the list - AstNode* newListp = nullptr; - for (auto it = rankMap.cbegin(); it != rankMap.cend(); ++it) { - AstNode* const nextp = it->second; - UINFO(6, " New order: " << nextp); - if (nextp == nodep) { - nodep->unlinkFrBack(&replaceHandle); - } else { - nextp->unlinkFrBack(); - } - if (newListp) { - newListp = newListp->addNext(nextp); - } else { - newListp = nextp; - } - } - replaceHandle.relink(newListp); - } - } - - void processBlock(AstNode* nodep) { - if (!nodep) return; // Empty lists are ignorable - // Pass the first node in a list of block items, we'll process them - // Check there's >= 2 sub statements, else nothing to analyze - // Save recursion state - AstNode* firstp = nodep; // We may reorder, and nodep is no longer first. - void* const oldBlockUser3 = nodep->user3p(); // May be overloaded in below loop, save it - nodep->user3p(nullptr); - UASSERT_OBJ(nodep->firstAbovep(), nodep, - "Node passed is in next list; should have processed all list at once"); - // Process it - if (!nodep->nextp()) { - // Just one, so can't reorder. Just look for more blocks/statements. - iterate(nodep); - } else { - UINFO(9, " processBlock " << nodep); - // Process block and followers - scanBlock(nodep); - if (m_noReorderWhy != "") { // Jump or something nasty - UINFO(9, " NoReorderBlock because " << m_noReorderWhy); - } else { - // Reorder statements in this block - cleanupBlockGraph(nodep); - reorderBlock(nodep); - // Delete old vertexes and edges only applying to this block - // First, walk back to first in list - while (firstp->backp()->nextp() == firstp) firstp = firstp->backp(); - for (AstNode* nextp = firstp; nextp; nextp = nextp->nextp()) { - SplitLogicVertex* const vvertexp - = reinterpret_cast(nextp->user3p()); - vvertexp->unlinkDelete(&m_graph); - } - } - } - // Again, nodep may no longer be first. - firstp->user3p(oldBlockUser3); - } - - void visit(AstAlways* nodep) override { - UINFO(4, " ALW " << nodep); - UINFOTREE(9, nodep, "", "alwIn:"); - scoreboardClear(); - processBlock(nodep->stmtsp()); - UINFOTREE(9, nodep, "", "alwOut"); - } - - void visit(AstNodeIf* nodep) override { - UINFO(4, " IF " << nodep); - iterateAndNextNull(nodep->condp()); - processBlock(nodep->thensp()); - processBlock(nodep->elsesp()); - } - -private: - VL_UNCOPYABLE(ReorderVisitor); -}; - using ColorSet = std::unordered_set; using AlwaysVec = std::vector; @@ -1002,15 +804,12 @@ private: VL_UNCOPYABLE(SplitVisitor); }; +} //namespace + //###################################################################### // Split class functions -void V3Split::splitReorderAll(AstNetlist* nodep) { - UINFO(2, __FUNCTION__ << ":"); - { ReorderVisitor{nodep}; } // Destruct before checking - V3Global::dumpCheckGlobalTree("reorder", 0, dumpTreeEitherLevel() >= 3); -} -void V3Split::splitAlwaysAll(AstNetlist* nodep) { +void V3Split::splitAll(AstNetlist* nodep) { UINFO(2, __FUNCTION__ << ":"); { SplitVisitor{nodep}; } // Destruct before checking V3Global::dumpCheckGlobalTree("split", 0, dumpTreeEitherLevel() >= 3); diff --git a/src/V3Split.h b/src/V3Split.h index 54e422ab9..6212d8c55 100644 --- a/src/V3Split.h +++ b/src/V3Split.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -26,8 +26,7 @@ class AstNetlist; class V3Split final { public: - static void splitReorderAll(AstNetlist* nodep) VL_MT_DISABLED; - static void splitAlwaysAll(AstNetlist* nodep) VL_MT_DISABLED; + static void splitAll(AstNetlist* nodep) VL_MT_DISABLED; }; #endif // Guard diff --git a/src/V3SplitAs.cpp b/src/V3SplitAs.cpp index f40609862..74b72a4dd 100644 --- a/src/V3SplitAs.cpp +++ b/src/V3SplitAs.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3SplitAs.h b/src/V3SplitAs.h index 4fdfaf737..dc5c4cce6 100644 --- a/src/V3SplitAs.h +++ b/src/V3SplitAs.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp index df976bda2..62c386293 100644 --- a/src/V3SplitVar.cpp +++ b/src/V3SplitVar.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -479,7 +479,7 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl { const AstNodeFTask* const ftaskp = nodep->taskp(); UASSERT_OBJ(ftaskp, nodep, "Unlinked"); // Iterate arguments of a function/task. - for (AstNode *argp = nodep->pinsp(), *paramp = ftaskp->stmtsp(); argp; + for (AstNode *argp = nodep->argsp(), *paramp = ftaskp->stmtsp(); argp; argp = argp->nextp(), paramp = paramp ? paramp->nextp() : nullptr) { const char* reason = nullptr; const AstVar* vparamp = nullptr; @@ -505,6 +505,7 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl { } m_foundTargetVar.clear(); } + if (nodep->withp()) iterate(nodep->withp()); } void visit(AstPin* nodep) override { UINFO(5, nodep->modVarp()->prettyNameQ() << " pin "); @@ -835,10 +836,17 @@ public: // If this is AstVarRef and referred in the sensitivity list of always@, // return the sensitivity item AstSenItem* backSenItemp() const { - if (const AstVarRef* const refp = VN_CAST(m_nodep, VarRef)) { - return VN_CAST(refp->backp(), SenItem); - } - return nullptr; + const AstVarRef* const refp = VN_CAST(m_nodep, VarRef); + if (!refp) return nullptr; + return VN_CAST(refp->backp(), SenItem); + } + AstNodeAssign* backCResetp() const { + const AstVarRef* const refp = VN_CAST(m_nodep, VarRef); + if (!refp) return nullptr; + AstNodeAssign* const assp = VN_CAST(refp->backp(), NodeAssign); + if (!assp) return nullptr; + if (!VN_IS(assp->rhsp(), CReset)) return nullptr; + return assp; } }; @@ -1026,7 +1034,8 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl { UINFO(4, var.varp()->prettyNameQ() << "[" << msb << ":" << lsb << "] used for " << ref.nodep()->prettyNameQ() << '\n'); // LSB of varp is always 0. "lsb - var.lsb()" means this. see also SplitNewVar - return new AstSel{fl, refp, lsb - var.lsb(), bitwidth}; + AstNodeExpr* const newp = new AstSel{fl, refp, lsb - var.lsb(), bitwidth}; + return newp; } } static void connectPortAndVar(const std::vector& vars, AstVar* portp, @@ -1082,6 +1091,7 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl { dtypep->rangep(new AstRange{ varp->fileline(), VNumRange{newvar.msb(), newvar.lsb(), basicp->ascending()}}); newvar.varp(new AstVar{varp->fileline(), VVarType::VAR, name, dtypep}); + newvar.varp()->lifetime(varp->lifetime()); newvar.varp()->propagateAttrFrom(varp); newvar.varp()->funcLocal(varp->isFuncLocal() || varp->isFuncReturn()); // Enable this line to trace split variable directly: @@ -1091,6 +1101,15 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl { UINFO(4, newvar.varp()->prettyNameQ() << " is added for " << varp->prettyNameQ()); } } + static AstAssign* newAssignCReset(AstNodeAssign* cresetAssp, AstVar* attachVarp) { + AstCReset* const cresetp = VN_AS(cresetAssp->rhsp(), CReset); + AstCReset* const newCResetp = cresetp->cloneTree(false); + newCResetp->dtypeFrom(attachVarp); + AstAssign* const newp = new AstAssign{ + cresetAssp->fileline(), + new AstVarRef{cresetAssp->fileline(), attachVarp, VAccess::WRITE}, newCResetp}; + return newp; + } static void updateReferences(AstVar* varp, PackedVarRef& pref, const std::vector& vars) { for (const bool lvalue : {false, true}) { // Refer the new split variables @@ -1101,9 +1120,14 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl { UASSERT_OBJ(varit != vars.end(), ref.nodep(), "Not found"); UASSERT(!(varit->msb() < ref.lsb() || ref.msb() < varit->lsb()), "wrong search result"); - AstNode* prevp; + AstNode* prevp = nullptr; bool inSentitivityList = false; - if (AstSenItem* const senitemp = ref.backSenItemp()) { + AstNodeAssign* const cresetAssp = ref.backCResetp(); + if (cresetAssp) { + // ASSIGN(VARREF old, CRESET) convert to a creset of each new var + cresetAssp->addNextHere(newAssignCReset(cresetAssp, varit->varp())); + } else if (AstSenItem* const senitemp = ref.backSenItemp()) { + // SENITEM(VARREF old) convert to a list of separate SenItems for each new var AstNode* const oldsenrefp = senitemp->sensp(); oldsenrefp->replaceWith( new AstVarRef{senitemp->fileline(), varit->varp(), VAccess::READ}); @@ -1117,7 +1141,9 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl { residue -= varit->bitwidth()) { ++varit; UASSERT_OBJ(varit != vars.end(), ref.nodep(), "not enough split variables"); - if (AstSenItem* const senitemp = VN_CAST(prevp, SenItem)) { + if (cresetAssp) { + cresetAssp->addNextHere(newAssignCReset(cresetAssp, varit->varp())); + } else if (AstSenItem* const senitemp = VN_CAST(prevp, SenItem)) { prevp = new AstSenItem{ senitemp->fileline(), senitemp->edgeType(), new AstVarRef{senitemp->fileline(), varit->varp(), VAccess::READ}}; @@ -1134,7 +1160,9 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl { // split() if (varp->isIO() && (varp->isFuncLocal() || varp->isFuncReturn())) connectPortAndVar(vars, varp, ref.nodep()); - if (!inSentitivityList) ref.replaceNodeWith(prevp); + if (!inSentitivityList && !cresetAssp) ref.replaceNodeWith(prevp); + if (cresetAssp) + VL_DO_DANGLING(cresetAssp->unlinkFrBack()->deleteTree(), cresetAssp); UASSERT_OBJ(varit->msb() >= ref.msb(), varit->varp(), "Out of range"); } } diff --git a/src/V3SplitVar.h b/src/V3SplitVar.h index 297d79432..81b59f337 100644 --- a/src/V3SplitVar.h +++ b/src/V3SplitVar.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3StackCount.cpp b/src/V3StackCount.cpp index 49f24ca81..b0df50c50 100644 --- a/src/V3StackCount.cpp +++ b/src/V3StackCount.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3StackCount.h b/src/V3StackCount.h index 1dc88bff0..2c67ab9f4 100644 --- a/src/V3StackCount.h +++ b/src/V3StackCount.h @@ -7,10 +7,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Stats.cpp b/src/V3Stats.cpp index 409f5abed..e1cd949ae 100644 --- a/src/V3Stats.cpp +++ b/src/V3Stats.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Stats.h b/src/V3Stats.h index 4045d64ad..b84a7d9aa 100644 --- a/src/V3Stats.h +++ b/src/V3Stats.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3StatsReport.cpp b/src/V3StatsReport.cpp index d3f49855a..f5901c920 100644 --- a/src/V3StatsReport.cpp +++ b/src/V3StatsReport.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -271,6 +271,6 @@ void V3Stats::summaryReport() { uint64_t memPeak, memCurrent; VlOs::memUsageBytes(memPeak /*ref*/, memCurrent /*ref*/); const double memory = memPeak / 1024.0 / 1024.0; - if (VL_UNCOVERABLE(memory != 0.0)) std::cout << "; alloced " << memory << " MB"; + if (VL_UNCOVERABLE(memory != 0.0)) std::cout << "; allocated " << memory << " MB"; std::cout << "\n"; } diff --git a/src/V3StdFuture.h b/src/V3StdFuture.h index 61c2b39e3..6729d7131 100644 --- a/src/V3StdFuture.h +++ b/src/V3StdFuture.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3String.cpp b/src/V3String.cpp index 71e000511..8f425f8bf 100644 --- a/src/V3String.cpp +++ b/src/V3String.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3String.h b/src/V3String.h index c2fc1cb02..b04fb2c83 100644 --- a/src/V3String.h +++ b/src/V3String.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Subst.cpp b/src/V3Subst.cpp index 54ab8d6e9..a97d21d72 100644 --- a/src/V3Subst.cpp +++ b/src/V3Subst.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -29,380 +29,438 @@ #include "V3Const.h" #include "V3Stats.h" -#include #include VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### -// Class for each word of a multi-word variable - -class SubstVarWord final { -protected: - // MEMBERS - AstNodeAssign* m_assignp; // Last assignment to each word of this var - int m_step; // Step number of last assignment - bool m_use; // True if each word was consumed - bool m_complex; // True if each word is complex - friend class SubstVarEntry; - // METHODS - void clear() { - m_assignp = nullptr; - m_step = 0; - m_use = false; - m_complex = false; - } -}; - -//###################################################################### -// Class for every variable we may process +// Data strored for every variable that tracks assignments and usage class SubstVarEntry final { + friend class SubstValidVisitor; + + // SubstVarEntry contains a Record for each word, and one extra for the whole variable + struct Record final { + // MEMBERS + AstNodeAssign* m_assignp; // Last assignment to this part + uint32_t m_step; // Step number of last assignment. 0 means invalid entry. + bool m_used; // True if consumed. Can be set even if entry is invalid. + // CONSTRUCTOR + Record() { invalidate(); } + // METHODS + void invalidate() { + m_assignp = nullptr; + m_step = 0; + m_used = false; + } + }; + // MEMBERS - AstVar* const m_varp; // Variable this tracks - bool m_wordAssign = false; // True if any word assignments - bool m_wordUse = false; // True if any individual word usage - SubstVarWord m_whole; // Data for whole vector used at once - std::vector m_words; // Data for every word, if multi word variable + // Variable this SubstVarEntry tracks + AstVar* const m_varp; + // The recrod for whole variable tracking + Record m_wholeRecord{}; + // A record for each word in the variable + std::vector m_wordRecords{static_cast(m_varp->widthWords()), Record{}}; + + // METHDOS + void deleteAssignmentIfUnused(Record& record, size_t& nAssignDeleted) { + if (!record.m_assignp) return; + if (record.m_used) return; + ++nAssignDeleted; + VL_DO_DANGLING(record.m_assignp->unlinkFrBack()->deleteTree(), record.m_assignp); + } + + AstNodeExpr* substRecord(Record& record); public: // CONSTRUCTORS explicit SubstVarEntry(AstVar* varp) - : m_varp{varp} { // Construction for when a var is used - m_words.resize(varp->widthWords()); - m_whole.clear(); - for (int i = 0; i < varp->widthWords(); i++) m_words[i].clear(); - } + : m_varp{varp} {} ~SubstVarEntry() = default; -private: - // METHODS - bool wordNumOk(int word) const { return word < m_varp->widthWords(); } - AstNodeAssign* getWordAssignp(int word) const { - if (!wordNumOk(word)) { - return nullptr; - } else { - return m_words[word].m_assignp; - } + // Record assignment of whole variable. The given 'assp' can be null, which means + // the variable is known to be assigned, but to an unknown value. + void assignWhole(AstNodeAssign* assp, uint32_t step) { + // Invalidate all word records + for (Record& wordRecord : m_wordRecords) wordRecord.invalidate(); + // Set whole record + m_wholeRecord.m_assignp = assp; + m_wholeRecord.m_step = step; + m_wholeRecord.m_used = false; } -public: - void assignWhole(int step, AstNodeAssign* assp) { - if (m_whole.m_assignp) m_whole.m_complex = true; - m_whole.m_assignp = assp; - m_whole.m_step = step; + // Like assignWhole word, but records assignment to a specific word of the variable. + void assignWord(AstNodeAssign* assp, uint32_t step, uint32_t word) { + // Invalidate whole record + m_wholeRecord.invalidate(); + // Set word record + Record& wordRecord = m_wordRecords[word]; + wordRecord.m_assignp = assp; + wordRecord.m_step = step; + wordRecord.m_used = false; } - void assignWord(int step, int word, AstNodeAssign* assp) { - if (!wordNumOk(word) || getWordAssignp(word) || m_words[word].m_complex) { - m_whole.m_complex = true; - } - m_wordAssign = true; - if (wordNumOk(word)) { - m_words[word].m_assignp = assp; - m_words[word].m_step = step; - } - } - void assignWordComplex(int word) { - if (!wordNumOk(word) || getWordAssignp(word) || m_words[word].m_complex) { - m_whole.m_complex = true; - } - m_words[word].m_complex = true; - } - void assignComplex() { m_whole.m_complex = true; } - void consumeWhole() { // ==consumeComplex as we don't know the difference - m_whole.m_use = true; - } - void consumeWord(int word) { - m_words[word].m_use = true; - m_wordUse = true; - } - // ACCESSORS - AstNodeExpr* substWhole(AstNode* errp) { - if (m_varp->isWide()) return nullptr; - if (m_whole.m_complex) return nullptr; - if (!m_whole.m_assignp) return nullptr; - if (m_wordAssign) return nullptr; - const AstNodeAssign* const assp = m_whole.m_assignp; - UASSERT_OBJ(assp, errp, "Reading whole that was never assigned"); - AstNodeExpr* const rhsp = assp->rhsp(); + // Mark the whole variable as used (value consumed) + void usedWhole() { + m_wholeRecord.m_used = true; + for (Record& wordRecord : m_wordRecords) wordRecord.m_used = true; + } - // AstCvtPackedToArray can't be anywhere else than on the RHS of assignment - if (VN_IS(rhsp, CvtPackedToArray)) return nullptr; - // Check if only substitute if constant - if (m_varp->substConstOnly() && !VN_IS(rhsp, Const)) return nullptr; - // Substitute it - return rhsp; + // Mark the specific word as used (value consumed) + void usedWord(uint32_t word) { + m_wholeRecord.m_used = true; + m_wordRecords[word].m_used = true; } - // Return what to substitute given word number for - AstNodeExpr* substWord(AstNode* errp, int word) { - if (!m_whole.m_complex && !m_whole.m_assignp && !m_words[word].m_complex) { - const AstNodeAssign* const assp = getWordAssignp(word); - UASSERT_OBJ(assp, errp, "Reading a word that was never assigned, or bad word #"); - return assp->rhsp(); - } else { - return nullptr; - } - } - int getWholeStep() const { return m_whole.m_step; } - int getWordStep(int word) const { - if (!wordNumOk(word)) { - return 0; - } else { - return m_words[word].m_step; - } - } - void deleteAssign(AstNodeAssign* nodep) { - UINFO(5, "Delete " << nodep); - VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } - void deleteUnusedAssign() { - // If there are unused assignments in this var, kill them - if (!m_whole.m_use && !m_wordUse && m_whole.m_assignp) { - VL_DO_CLEAR(deleteAssign(m_whole.m_assignp), m_whole.m_assignp = nullptr); - } - for (unsigned i = 0; i < m_words.size(); i++) { - if (!m_whole.m_use && !m_words[i].m_use && m_words[i].m_assignp - && !m_words[i].m_complex) { - VL_DO_CLEAR(deleteAssign(m_words[i].m_assignp), m_words[i].m_assignp = nullptr); - } - } + + // Returns substitution of whole word, or nullptr if not known/stale + AstNodeExpr* substWhole() { return substRecord(m_wholeRecord); } + // Returns substitution of whole word, or nullptr if not known/stale + AstNodeExpr* substWord(uint32_t word) { return substRecord(m_wordRecords[word]); } + + void deleteUnusedAssignments(size_t& nWordAssignDeleted, size_t& nWholeAssignDeleted) { + // Delete assignments to temporaries if they are not used + if (!m_varp->isStatementTemp()) return; + for (Record& wordRecord : m_wordRecords) + deleteAssignmentIfUnused(wordRecord, nWordAssignDeleted); + deleteAssignmentIfUnused(m_wholeRecord, nWholeAssignDeleted); } }; //###################################################################### -// See if any variables have changed value since we determined subst value, -// as a visitor of each AstNode +// See if any variables in the expression we are considering to +// substitute have changed value since we recorded the assignment. -class SubstUseVisitor final : public VNVisitorConst { +class SubstValidVisitor final : public VNVisitorConst { // NODE STATE // See SubstVisitor - // STATE - across all visitors - const int m_origStep; // Step number where subst was recorded - bool m_ok = true; // No misassignments found + // STATE + const uint32_t m_step; // Step number where assignment was recorded + bool m_valid = true; // Is the expression we are considering to substitute valid // METHODS - SubstVarEntry* findEntryp(AstVarRef* nodep) { - return reinterpret_cast(nodep->varp()->user1p()); // Might be nullptr + SubstVarEntry& getEntry(AstVarRef* nodep) { + // This vistor is always invoked on the RHS of an assignment we are considering to + // substitute. Variable references must have all been recorded when visiting the + // assignments RHS, so the SubstVarEntry must exist for each referenced variable. + return *nodep->varp()->user1u().to(); } + // VISITORS - void visit(AstVarRef* nodep) override { - const SubstVarEntry* const entryp = findEntryp(nodep); - if (entryp) { - // Don't sweat it. We assign a new temp variable for every new assignment, - // so there's no way we'd ever replace a old value. - } else { - // A simple variable; needs checking. - if (m_origStep < nodep->varp()->user2()) { - if (m_ok) { UINFO(9, " RHS variable changed since subst recorded: " << nodep); } - m_ok = false; + void visit(AstWordSel* nodep) override { + if (!m_valid) return; + + if (AstVarRef* const refp = VN_CAST(nodep->fromp(), VarRef)) { + if (AstConst* const idxp = VN_CAST(nodep->bitp(), Const)) { + SubstVarEntry& entry = getEntry(refp); + // If either the whole variable, or the indexed word was written to + // after the original assignment was recorded, the value is invalid. + if (m_step < entry.m_wholeRecord.m_step) m_valid = false; + if (m_step < entry.m_wordRecords[idxp->toUInt()].m_step) m_valid = false; + return; } } - } - void visit(AstConst*) override {} // Accelerate - void visit(AstNode* nodep) override { - if (!nodep->isPure()) m_ok = false; iterateChildrenConst(nodep); } -public: - // CONSTRUCTORS - SubstUseVisitor(AstNode* nodep, int origStep) - : m_origStep{origStep} { - UINFO(9, " SubstUseVisitor " << origStep << " " << nodep); - iterateConst(nodep); + void visit(AstVarRef* nodep) override { + if (!m_valid) return; + + // If either the whole variable, or any of the words were written to + // after the original assignment was recorded, the value is invalid. + SubstVarEntry& entry = getEntry(nodep); + if (m_step < entry.m_wholeRecord.m_step) { + m_valid = false; + return; + } + for (SubstVarEntry::Record& wordRecord : entry.m_wordRecords) { + if (m_step < wordRecord.m_step) { + m_valid = false; + return; + } + } + } + + void visit(AstConst*) override {} // Accelerate + + void visit(AstNodeExpr* nodep) override { + if (!m_valid) return; + iterateChildrenConst(nodep); + } + + void visit(AstNode* nodep) override { nodep->v3fatalSrc("Non AstNodeExpr under AstNodeExpr"); } + + // CONSTRUCTORS + SubstValidVisitor(SubstVarEntry::Record& record) + : m_step{record.m_step} { + iterateConst(record.m_assignp->rhsp()); + } + ~SubstValidVisitor() override = default; + +public: + static bool valid(SubstVarEntry::Record& record) { + if (!record.m_assignp) return false; + return SubstValidVisitor{record}.m_valid; } - ~SubstUseVisitor() override = default; - // METHODS - bool ok() const { return m_ok; } }; +AstNodeExpr* SubstVarEntry::substRecord(SubstVarEntry::Record& record) { + if (!SubstValidVisitor::valid(record)) return nullptr; + AstNodeExpr* const rhsp = record.m_assignp->rhsp(); + UDEBUGONLY(UASSERT_OBJ(rhsp->isPure(), record.m_assignp, "Substituting impure expression");); + return rhsp; +} + //###################################################################### -// Subst state, as a visitor of each AstNode +// Substitution visitor class SubstVisitor final : public VNVisitor { - // NODE STATE - // Passed to SubstUseVisitor - // AstVar::user1p -> SubstVar* for usage var, 0=not set yet. Only under CFunc. - // AstVar::user2 -> int step number for last assignment, 0=not set yet - const VNUser2InUse m_inuser2; + // NODE STATE - only Under AstCFunc + // AstVar::user1p -> SubstVarEntry* for assignment tracking. Also used by SubstValidVisitor + // AstVar::user2 -> bool. Is a constant pool variable + const VNUser2InUse m_user2InUse; // STATE - std::deque m_entries; // Nodes to delete when we are finished - int m_ops = 0; // Number of operators on assign rhs - int m_assignStep = 0; // Assignment number to determine var lifetime + std::deque m_entries; // Storage for SubstVarEntry instances + uint32_t m_ops = 0; // Number of nodes on the RHS of an assignment + uint32_t m_assignStep = 0; // Assignment number to determine variable lifetimes const AstCFunc* m_funcp = nullptr; // Current function we are under - size_t m_nSubst = 0; // Number of substitutions performed + size_t m_nSubst = 0; // Number of substitutions performed - for avoiding constant folding + // Statistics + size_t m_nWordSubstituted = 0; // Number of words substituted + size_t m_nWholeSubstituted = 0; // Number of whole variables substituted + size_t m_nWordAssignDeleted = 0; // Number of word assignments deleted + size_t m_nWholeAssignDeleted = 0; // Number of whole variable assignments deleted + size_t m_nConstWordsReinlined = 0; // Number of constant words substituted - enum { - SUBST_MAX_OPS_SUBST = 30, // Maximum number of ops to substitute in - SUBST_MAX_OPS_NA = 9999 - }; // Not allowed to substitute + static constexpr uint32_t SUBST_MAX_OPS_SUBST = 30; // Maximum number of ops to substitute in + static constexpr uint32_t SUBST_MAX_OPS_NA = 9999; // Not allowed to substitute // METHODS - SubstVarEntry* getEntryp(AstVarRef* nodep) { + SubstVarEntry& getEntry(AstVarRef* nodep) { AstVar* const varp = nodep->varp(); if (!varp->user1p()) { m_entries.emplace_back(varp); varp->user1p(&m_entries.back()); } - return varp->user1u().to(); + return *varp->user1u().to(); } - bool isSubstVar(AstVar* nodep) { return nodep->isStatementTemp() && !nodep->noSubst(); } - // VISITORS - void visit(AstNodeAssign* nodep) override { - if (!m_funcp) return; - VL_RESTORER(m_ops); - m_ops = 0; - m_assignStep++; + void simplify(AstNodeExpr* exprp) { + // Often constant, so short circuit + if (VN_IS(exprp, Const)) return; + // Iterate expression, then constant fold it if anything changed const size_t nSubstBefore = m_nSubst; - iterateAndNextNull(nodep->rhsp()); - if (nSubstBefore != m_nSubst) V3Const::constifyEditCpp(nodep->rhsp()); - if (VN_IS(nodep->rhsp(), Const)) m_ops = 0; - bool hit = false; - if (AstVarRef* const varrefp = VN_CAST(nodep->lhsp(), VarRef)) { - if (isSubstVar(varrefp->varp())) { - SubstVarEntry* const entryp = getEntryp(varrefp); - hit = true; - if (m_ops > SUBST_MAX_OPS_SUBST) { - UINFO(8, " ASSIGNtooDeep " << varrefp); - entryp->assignComplex(); - } else { - UINFO(8, " ASSIGNwhole " << varrefp); - entryp->assignWhole(m_assignStep, nodep); - } - } - } else if (const AstWordSel* const wordp = VN_CAST(nodep->lhsp(), WordSel)) { - if (AstVarRef* const varrefp = VN_CAST(wordp->fromp(), VarRef)) { - if (VN_IS(wordp->bitp(), Const) && isSubstVar(varrefp->varp())) { - const int word = VN_AS(wordp->bitp(), Const)->toUInt(); - SubstVarEntry* const entryp = getEntryp(varrefp); - hit = true; - if (m_ops > SUBST_MAX_OPS_SUBST) { - UINFO(8, " ASSIGNtooDeep " << varrefp); - entryp->assignWordComplex(word); - } else { - UINFO(8, " ASSIGNword" << word << " " << varrefp); - entryp->assignWord(m_assignStep, word, nodep); - } - } - } - } - if (!hit) iterate(nodep->lhsp()); + exprp = VN_AS(iterateSubtreeReturnEdits(exprp), NodeExpr); + if (nSubstBefore != m_nSubst) V3Const::constifyEditCpp(exprp); } - void replaceSubstEtc(AstNode* nodep, AstNodeExpr* substp) { - UINFOTREE(6, nodep, "", "substw_old"); - AstNodeExpr* newp = substp->cloneTreePure(true); + + // The way the analysis algorithm works based on statement numbering only works + // for variables that are written in the same basic block (ignoring AstCond) as + // where they are consumed. The temporaries introduced in V3Premit are such, so + // only substitute those for now. + bool isSubstitutable(AstVar* nodep) { return nodep->isStatementTemp() && !nodep->noSubst(); } + + void substitute(AstNode* nodep, AstNodeExpr* substp) { + AstNodeExpr* newp = substp->backp() ? substp->cloneTreePure(true) : substp; if (!nodep->isQuad() && newp->isQuad()) { newp = new AstCCast{newp->fileline(), newp, nodep}; } - UINFOTREE(6, newp, "", "w_new"); nodep->replaceWith(newp); VL_DO_DANGLING(nodep->deleteTree(), nodep); ++m_nSubst; } - void visit(AstWordSel* nodep) override { - if (!m_funcp) return; - const size_t nSubstBefore = m_nSubst; - iterate(nodep->bitp()); - // Simplify in case it was substituted and became constant - if (nSubstBefore != m_nSubst) V3Const::constifyEditCpp(nodep->bitp()); - AstVarRef* const varrefp = VN_CAST(nodep->fromp(), VarRef); - const AstConst* const constp = VN_CAST(nodep->bitp(), Const); - if (varrefp && isSubstVar(varrefp->varp()) && varrefp->access().isReadOnly() && constp) { - // Nicely formed lvalues handled in NodeAssign - // Other lvalues handled as unknown mess in AstVarRef - const int word = constp->toUInt(); - UINFO(8, " USEword" << word << " " << varrefp); - SubstVarEntry* const entryp = getEntryp(varrefp); - if (AstNodeExpr* const substp = entryp->substWord(nodep, word)) { - // Check that the RHS hasn't changed value since we recorded it. - const SubstUseVisitor visitor{substp, entryp->getWordStep(word)}; - if (visitor.ok()) { - VL_DO_DANGLING(replaceSubstEtc(nodep, substp), nodep); - } else { - entryp->consumeWord(word); - } - } else { - entryp->consumeWord(word); - } - } else { - iterate(nodep->fromp()); + + // VISITORS + + void visit(AstNetlist* nodep) override { + // Mark constant pool variables + for (AstNode* np = nodep->constPoolp()->modp()->stmtsp(); np; np = np->nextp()) { + if (VN_IS(np, Var)) np->user2(true); } + + iterateAndNextNull(nodep->modulesp()); } - void visit(AstVarRef* nodep) override { - if (!m_funcp) return; - // Any variable - if (nodep->access().isWriteOrRW()) { - m_assignStep++; - nodep->varp()->user2(m_assignStep); - UINFO(9, " ASSIGNstep u2=" << nodep->varp()->user2() << " " << nodep); - } - if (isSubstVar(nodep->varp())) { - SubstVarEntry* const entryp = getEntryp(nodep); - if (nodep->access().isWriteOrRW()) { - UINFO(8, " ASSIGNcpx " << nodep); - entryp->assignComplex(); - } else if (AstNodeExpr* const substp = entryp->substWhole(nodep)) { - // Check that the RHS hasn't changed value since we recorded it. - const SubstUseVisitor visitor{substp, entryp->getWholeStep()}; - if (visitor.ok()) { - UINFO(8, " USEwhole " << nodep); - VL_DO_DANGLING(replaceSubstEtc(nodep, substp), nodep); - } else { - UINFO(8, " USEwholeButChg " << nodep); - entryp->consumeWhole(); - } - } else { // Consumed w/o substitute - UINFO(8, " USEwtf " << nodep); - entryp->consumeWhole(); - } - } - } - void visit(AstVar*) override {} - void visit(AstConst*) override {} void visit(AstCFunc* nodep) override { UASSERT_OBJ(!m_funcp, nodep, "Should not nest"); - UASSERT_OBJ(m_entries.empty(), nodep, "References outside functions"); - VL_RESTORER(m_funcp); - m_funcp = nodep; + UASSERT_OBJ(m_entries.empty(), nodep, "Should not visit outside functions"); - const VNUser1InUse m_inuser1; - iterateChildren(nodep); - for (SubstVarEntry& ip : m_entries) ip.deleteUnusedAssign(); - m_entries.clear(); + // Process the function body + { + VL_RESTORER(m_funcp); + m_funcp = nodep; + const VNUser1InUse m_inuser1; + iterateChildren(nodep); + // Deletes unused assignments and clear entries + for (SubstVarEntry& entry : m_entries) { + entry.deleteUnusedAssignments(m_nWordAssignDeleted, m_nWholeAssignDeleted); + } + m_entries.clear(); + } // Constant fold here, as Ast size can likely be reduced - if (v3Global.opt.fConstEager()) { - AstNode* const editedp = V3Const::constifyEditCpp(nodep); - UASSERT_OBJ(editedp == nodep, editedp, "Should not have replaced CFunc"); + if (v3Global.opt.fConstEager()) V3Const::constifyEditCpp(nodep); + } + + void visit(AstNodeAssign* nodep) override { + if (!m_funcp) return; + + const uint32_t ops = [&]() { + VL_RESTORER(m_ops); + m_ops = 0; + // Simplify the RHS + simplify(nodep->rhsp()); + // If the became constant, we can continue substituting it + return VN_IS(nodep->rhsp(), Const) ? 0 : m_ops; + }(); + + // Assignment that defines the value, which is either this 'nodep', + // or nullptr, if the value should not be substituted. + const auto getAssignp = [&](AstVarRef* refp) -> AstNodeAssign* { + // If too complex, don't substitute + if (ops > SUBST_MAX_OPS_SUBST) return nullptr; + // AstCvtPackedToArray can't be anywhere else than on the RHS of assignment + if (VN_IS(nodep->rhsp(), CvtPackedToArray)) return nullptr; + // If non const but want const subtitutions only + if (refp->varp()->substConstOnly() && !VN_IS(nodep->rhsp(), Const)) return nullptr; + // Otherwise can substitute based on the assignment + return nodep; + }; + + // If LHS is a whole variable reference, track the whole variable + if (AstVarRef* const refp = VN_CAST(nodep->lhsp(), VarRef)) { + getEntry(refp).assignWhole(getAssignp(refp), ++m_assignStep); + return; } + + // If LHS is a known word reference, track the word + if (const AstWordSel* const selp = VN_CAST(nodep->lhsp(), WordSel)) { + if (AstVarRef* const refp = VN_CAST(selp->fromp(), VarRef)) { + // Simplify the index + simplify(selp->bitp()); + if (const AstConst* const idxp = VN_CAST(selp->bitp(), Const)) { + getEntry(refp).assignWord(getAssignp(refp), ++m_assignStep, idxp->toUInt()); + return; + } + } + } + + // Not tracked, iterate LHS to simplify/reset tracking + iterate(nodep->lhsp()); } - // Do not optimzie across user $c input - void visit(AstCExprUser* nodep) override { - m_ops = SUBST_MAX_OPS_NA; - iterateChildren(nodep); - } - void visit(AstCStmtUser* nodep) override { - m_ops = SUBST_MAX_OPS_NA; - iterateChildren(nodep); + void visit(AstWordSel* nodep) override { + if (!m_funcp) return; + + // Simplify the index + simplify(nodep->bitp()); + + // If this is a known word reference, track/substitute it + if (AstVarRef* const refp = VN_CAST(nodep->fromp(), VarRef)) { + if (const AstConst* const idxp = VN_CAST(nodep->bitp(), Const)) { + SubstVarEntry& entry = getEntry(refp); + const uint32_t word = idxp->toUInt(); + + // If it's a write, reset tracking as we don't know the assigned value, + // otherwise we would have picked it up in visit(AstNodeAssign*) + if (refp->access().isWriteOrRW()) { + entry.assignWord(nullptr, ++m_assignStep, word); + return; + } + + // Otherwise it's a read, + UASSERT_OBJ(refp->access().isReadOnly(), nodep, "Invalid access"); + + // If it's a constant pool variable, substiute with the constant word + AstVar* const varp = refp->varp(); + if (varp->user2()) { + AstConst* const constp = VN_AS(varp->valuep(), Const); + const uint32_t value = constp->num().edataWord(word); + FileLine* const flp = nodep->fileline(); + ++m_nConstWordsReinlined; + substitute(nodep, new AstConst{flp, AstConst::SizedEData{}, value}); + return; + } + + // Substitute other variables if possible + if (isSubstitutable(refp->varp())) { + if (AstNodeExpr* const substp = entry.substWord(word)) { + ++m_nWordSubstituted; + substitute(nodep, substp); + return; + } + } + + // If not substituted, mark the assignment setting this word as used + entry.usedWord(word); + return; + } + } + + // If not a known word reference, iterate fromp to simplify/reset tracking + iterate(nodep->fromp()); } - void visit(AstNode* nodep) override { + void visit(AstVarRef* nodep) override { + if (!m_funcp) return; + + SubstVarEntry& entry = getEntry(nodep); + + // If it's a write, reset tracking as we don't know the assigned value, + // otherwise we would have picked it up in visit(AstNodeAssign*) + if (nodep->access().isWriteOrRW()) { + entry.assignWhole(nullptr, ++m_assignStep); + return; + } + + // Otherwise it's a read, substitute it if possible + UASSERT_OBJ(nodep->access().isReadOnly(), nodep, "Invalid access"); + if (isSubstitutable(nodep->varp())) { + if (AstNodeExpr* const substp = entry.substWhole()) { + // Do not substitute a compound wide expression. + // The whole point of adding temporaries is to eliminate them. + if (!nodep->isWide() || VN_IS(substp, VarRef)) { + ++m_nWholeSubstituted; + substitute(nodep, substp); + return; + } + } + } + + // If not substituted, mark the assignment setting this variable as used + entry.usedWhole(); + } + + void visit(AstNodeExpr* nodep) override { + if (!m_funcp) return; + + // Count nodes as we descend to track complexity ++m_ops; + // First iterate children, this can cache child purity iterateChildren(nodep); + // Do not substitute impure expressions + if (!nodep->isPure()) m_ops = SUBST_MAX_OPS_NA; } + void visit(AstVar*) override {} // Accelerate + void visit(AstConst*) override {} // Accelerate + + void visit(AstNode* nodep) override { iterateChildren(nodep); } + public: // CONSTRUCTORS - explicit SubstVisitor(AstNode* nodep) { iterate(nodep); } + explicit SubstVisitor(AstNetlist* nodep) { iterate(nodep); } ~SubstVisitor() override { - V3Stats::addStat("Optimizations, Substituted temps", m_nSubst); - UASSERT(m_entries.empty(), "References outside functions"); + V3Stats::addStat("Optimizations, Subst, Substituted temps", m_nSubst); + V3Stats::addStat("Optimizations, Subst, Constant words reinlined", m_nConstWordsReinlined); + V3Stats::addStat("Optimizations, Subst, Whole variable assignments deleted", + m_nWholeAssignDeleted); + V3Stats::addStat("Optimizations, Subst, Whole variables substituted", m_nWholeSubstituted); + V3Stats::addStat("Optimizations, Subst, Word assignments deleted", m_nWordAssignDeleted); + V3Stats::addStat("Optimizations, Subst, Words substituted", m_nWordSubstituted); + UASSERT(m_entries.empty(), "Should not visit outside functions"); } }; diff --git a/src/V3Subst.h b/src/V3Subst.h index 3f4f3226a..a58f929b8 100644 --- a/src/V3Subst.h +++ b/src/V3Subst.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3SymTable.h b/src/V3SymTable.h index 3e8bd4140..019bfbe19 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp index cb5007a88..4244a5676 100644 --- a/src/V3TSP.cpp +++ b/src/V3TSP.cpp @@ -11,10 +11,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3TSP.h b/src/V3TSP.h index 3b02499f2..840f5fa96 100644 --- a/src/V3TSP.h +++ b/src/V3TSP.h @@ -7,10 +7,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Table.cpp b/src/V3Table.cpp index aa1637370..d99f25e27 100644 --- a/src/V3Table.cpp +++ b/src/V3Table.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Table.h b/src/V3Table.h index 6cad38399..af2acd6ba 100644 --- a/src/V3Table.h +++ b/src/V3Table.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 75544d232..387ff5de1 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -32,6 +32,7 @@ #include "V3EmitCBase.h" #include "V3Graph.h" #include "V3Stats.h" +#include "V3UniqueNames.h" #include @@ -209,9 +210,11 @@ private: // Find all var->varscope mappings, for later cleanup for (AstNode* stmtp = nodep->varsp(); stmtp; stmtp = stmtp->nextp()) { if (AstVarScope* const vscp = VN_CAST(stmtp, VarScope)) { - if (vscp->varp()->isFuncLocal() || vscp->varp()->isUsedLoopIdx()) { + AstVar* const varp = vscp->varp(); + if (varp->isFuncLocal() || varp->isUsedLoopIdx() + || varp->lifetime().isAutomatic()) { UINFO(9, " funcvsc " << vscp); - m_varToScopeMap.emplace(std::make_pair(nodep, vscp->varp()), vscp); + m_varToScopeMap.emplace(std::make_pair(nodep, varp), vscp); } } } @@ -288,18 +291,23 @@ private: iterateChildren(nodep); } UASSERT_OBJ(m_ctorp, nodep, "class constructor missing"); // LinkDot always makes it + AstNode* insertp = nullptr; for (AstInitialAutomatic* initialp : m_initialps) { - if (AstNode* const newp = initialp->stmtsp()) { - newp->unlinkFrBackWithNext(); - if (!m_ctorp->stmtsp()) { - m_ctorp->addStmtsp(newp); - } else { - m_ctorp->stmtsp()->addHereThisAsNext(newp); - } + if (AstNode* const movep = initialp->stmtsp()) { + movep->unlinkFrBackWithNext(); + // Next InitialAutomatic must go in order after what we inserted + insertp = AstNode::addNextNull(insertp, movep); } VL_DO_DANGLING(pushDeletep(initialp->unlinkFrBack()), initialp); } m_initialps.clear(); + if (insertp) { + if (!m_ctorp->stmtsp()) { + m_ctorp->addStmtsp(insertp); + } else { + m_ctorp->stmtsp()->addHereThisAsNext(insertp); + } + } } void visit(AstInitialAutomatic* nodep) override { m_initialps.push_back(nodep); @@ -371,6 +379,7 @@ struct TaskDpiUtils final { : dtypep->width() <= 16 ? 'S' : *dtypep->charIQWN(); const std::string& size = std::to_string(dtypep->width()); + // cppcheck-suppress strPlusChar return {"VL_SET_"s + sizeChar + "_" + vecType + "(" + size + ", ", true}; } }; @@ -393,6 +402,8 @@ class TaskVisitor final : public VNVisitor { // STATE TaskStateVisitor* const m_statep; // Common state between visitors + V3UniqueNames m_initArrayTmpNames; // For generating unique temporary variable names for + // arguments being AstInitArray AstNodeModule* m_modp = nullptr; // Current module AstTopScope* const m_topScopep = v3Global.rootp()->topScopep(); // The AstTopScope AstScope* m_scopep = nullptr; // Current scope @@ -400,6 +411,7 @@ class TaskVisitor final : public VNVisitor { bool m_inSensesp = false; // Are we under a senitem? bool m_inNew = false; // Are we under a constructor? int m_modNCalls = 0; // Incrementing func # for making symbols + int m_unconVarNum = 0; // Unique bad connection variable // STATE - across all visitors DpiCFuncs m_dpiNames; // Map of all created DPI functions @@ -439,6 +451,7 @@ class TaskVisitor final : public VNVisitor { = new AstVar{invarp->fileline(), VVarType::BLOCKTEMP, name, invarp}; newvarp->funcLocal(false); newvarp->propagateAttrFrom(invarp); + newvarp->isInternal(true); m_modp->addStmtsp(newvarp); AstVarScope* const newvscp = new AstVarScope{newvarp->fileline(), m_scopep, newvarp}; m_scopep->addVarsp(newvscp); @@ -504,9 +517,19 @@ class TaskVisitor final : public VNVisitor { return assp; } + void changeAtWriteRecurse(AstNodeExpr* const exprp) { + // Change nested at methods to writable variant + if (AstCMethodHard* const cMethodp = VN_CAST(exprp, CMethodHard)) { + if (cMethodp->method() == VCMethod::ARRAY_AT) { + cMethodp->method(VCMethod::ARRAY_AT_WRITE); + } + changeAtWriteRecurse(cMethodp->fromp()); + } + } + void connectPort(AstVar* portp, AstArg* argp, const string& namePrefix, AstNode* beginp, bool inlineTask) { - AstNodeExpr* const pinp = argp->exprp(); + AstNodeExpr* pinp = argp->exprp(); if (inlineTask) { portp->unlinkFrBack(); pushDeletep(portp); // Remove it from the clone (not original) @@ -516,15 +539,28 @@ class TaskVisitor final : public VNVisitor { } else { UINFO(9, " Port " << portp); UINFO(9, " pin " << pinp); - if (inlineTask) { - pushDeletep(pinp->unlinkFrBack()); // Cloned in assignment below - VL_DO_DANGLING(argp->unlinkFrBack()->deleteTree(), argp); // Args no longer needed - } if (portp->isWritable() && VN_IS(pinp, Const)) { pinp->v3error("Function/task " + portp->direction().prettyName() // e.g. "output" + " connected to constant instead of variable: " + portp->prettyNameQ()); - } else if (portp->isRef() || portp->isConstRef()) { + // Make temp pin to tie it off + AstVar* const varp = new AstVar{pinp->fileline(), VVarType::STMTTEMP, + "__VfuncUnconn_" + portp->name() + "__" + + std::to_string(m_unconVarNum++), + portp->dtypep()}; + m_modp->addStmtsp(varp); + AstVarScope* const newvscp = new AstVarScope{pinp->fileline(), m_scopep, varp}; + m_scopep->addVarsp(newvscp); + AstVarRef* const repp = new AstVarRef{pinp->fileline(), newvscp, VAccess::WRITE}; + pinp->replaceWith(repp); + pushDeletep(pinp); + pinp = repp; + } + if (inlineTask) { + pushDeletep(pinp->unlinkFrBack()); // Cloned in assignment below + VL_DO_DANGLING(argp->unlinkFrBack()->deleteTree(), argp); // Args no longer needed + } + if (portp->isRef() || portp->isConstRef()) { bool refArgOk = false; if (VN_IS(pinp, VarRef) || VN_IS(pinp, MemberSel) || VN_IS(pinp, StructSel) || VN_IS(pinp, ArraySel)) { @@ -534,8 +570,8 @@ class TaskVisitor final : public VNVisitor { refArgOk = cMethodp->method() == VCMethod::DYN_AT_WRITE_APPEND || cMethodp->method() == VCMethod::DYN_AT_WRITE_APPEND_BACK; } else { - refArgOk = cMethodp->method() == VCMethod::ARRAY_AT - || cMethodp->method() == VCMethod::ARRAY_AT_BACK; + changeAtWriteRecurse(cMethodp); + refArgOk = cMethodp->method() == VCMethod::ARRAY_AT_WRITE; } } if (refArgOk) { @@ -627,7 +663,7 @@ class TaskVisitor final : public VNVisitor { connectPort(portp, argp, namePrefix, beginp, true); } } - UASSERT_OBJ(!refp->pinsp(), refp, "Pin wasn't removed by above loop"); + UASSERT_OBJ(!refp->argsp(), refp, "Arg wasn't removed by above loop"); { AstNode* nextstmtp; for (AstNode* stmtp = beginp; stmtp; stmtp = nextstmtp) { @@ -642,9 +678,11 @@ class TaskVisitor final : public VNVisitor { if (portp->needsCReset() && portp->lifetime().isAutomatic() && !portp->valuep()) { // Reset automatic var to its default, on each invocation of function - AstVarRef* const vrefp - = new AstVarRef{portp->fileline(), portp, VAccess::WRITE}; - portp->replaceWith(new AstCReset{portp->fileline(), vrefp, false}); + AstNode* const crstp = new AstAssign{ + portp->fileline(), + new AstVarRef{portp->fileline(), portp, VAccess::WRITE}, + new AstCReset{portp->fileline(), portp, false}}; + portp->replaceWith(crstp); } else { portp->unlinkFrBack(); } @@ -723,14 +761,10 @@ class TaskVisitor final : public VNVisitor { ccallp->addArgsp(new AstConst(flp, flp->lineno())); } - // Create connections - AstNode* nextpinp; - for (AstNode* pinp = refp->pinsp(); pinp; pinp = nextpinp) { - nextpinp = pinp->nextp(); - // Move pin to the CCall, removing all Arg's - AstNodeExpr* const exprp = VN_AS(pinp, Arg)->exprp(); - exprp->unlinkFrBack(); - ccallp->addArgsp(exprp); + // Move artument expression to the CCall, without AstArg + for (AstArg *argp = refp->argsp(), *nextp; argp; argp = nextp) { + nextp = VN_AS(argp->nextp(), Arg); + ccallp->addArgsp(argp->exprp()->unlinkFrBack()); } if (outvscp) ccallp->addArgsp(new AstVarRef{refp->fileline(), outvscp, VAccess::WRITE}); @@ -1222,6 +1256,7 @@ class TaskVisitor final : public VNVisitor { unlinkAndClone(nodep, portp, false); rtnvarp = portp; rtnvarp->funcLocal(true); + rtnvarp->noCReset(true); // As made for port in V3LinkResolve rtnvarp->name(rtnvarp->name() + "__Vfuncrtn"); // Avoid conflict with DPI function name if (nodep->dpiImport() || nodep->dpiExport()) rtnvarp->protect(false); @@ -1438,6 +1473,28 @@ class TaskVisitor final : public VNVisitor { UINFOTREE(9, newp, "", "newfunc"); m_insStmtp->addHereThisAsNext(newp); } + void processArgs(AstNodeFTaskRef* nodep) { + // Create a fresh variable for each concat array present in pins list + for (AstArg* argp = nodep->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { + AstInitArray* const arrayp = VN_CAST(argp->exprp(), InitArray); + if (!arrayp) continue; + + FileLine* const flp = arrayp->fileline(); + const std::string tempName = m_initArrayTmpNames.get(argp); + AstVar* const substp = new AstVar{flp, VVarType::VAR, tempName, arrayp->dtypep()}; + substp->funcLocal(true); + AstVarScope* const substvscp = createVarScope(substp, tempName); + + AstAssign* const assignp + = new AstAssign{flp, new AstVarRef{arrayp->fileline(), substvscp, VAccess::WRITE}, + arrayp->unlinkFrBack()}; + + AstExprStmt* const exprstmtp = new AstExprStmt{ + flp, substp, new AstVarRef{arrayp->fileline(), substvscp, VAccess::READ}}; + exprstmtp->stmtsp()->addNext(assignp); + argp->exprp(exprstmtp); + } + } // VISITORS void visit(AstNodeModule* nodep) override { @@ -1494,6 +1551,7 @@ class TaskVisitor final : public VNVisitor { AstNode* beginp; AstCNew* cnewp = nullptr; if (m_statep->ftaskNoInline(nodep->taskp())) { + processArgs(nodep); // This may share VarScope's with a public task, if any. Yuk. beginp = createNonInlinedFTask(nodep, namePrefix, outvscp, cnewp /*ref*/); } else { @@ -1669,7 +1727,8 @@ class TaskVisitor final : public VNVisitor { public: // CONSTRUCTORS TaskVisitor(AstNetlist* nodep, TaskStateVisitor* statep) - : m_statep{statep} { + : m_statep{statep} + , m_initArrayTmpNames{"__VInitArrayTemp"} { iterate(nodep); } ~TaskVisitor() { @@ -1717,25 +1776,22 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp, // Find pins int ppinnum = 0; bool reorganize = false; - for (AstNode *nextp, *pinp = nodep->pinsp(); pinp; pinp = nextp) { - nextp = pinp->nextp(); - if (VN_IS(pinp, With)) continue; - AstArg* const argp = VN_AS(pinp, Arg); - UASSERT_OBJ(argp, pinp, "Non-arg under ftask reference"); - if (argp->name() != "") { + for (AstArg *argp = nodep->argsp(), *nextp; argp; argp = nextp) { + nextp = VN_AS(argp->nextp(), Arg); + if (!argp->name().empty()) { // By name const auto it = nameToIndex.find(argp->name()); if (it == nameToIndex.end()) { if (makeChanges) { - pinp->v3error("No such argument " << argp->prettyNameQ() + argp->v3error("No such argument " << argp->prettyNameQ() << " in function call to " << nodep->taskp()->prettyTypeName()); // We'll just delete it; seems less error prone than making a false argument - VL_DO_DANGLING(pinp->unlinkFrBack()->deleteTree(), pinp); + VL_DO_DANGLING(argp->unlinkFrBack()->deleteTree(), argp); } } else { if (tconnects[it->second].second && makeChanges) { - pinp->v3error("Duplicate argument " << argp->prettyNameQ() + argp->v3error("Duplicate argument " << argp->prettyNameQ() << " in function call to " << nodep->taskp()->prettyTypeName()); tconnects[it->second].second->unlinkFrBack()->deleteTree(); @@ -1752,10 +1808,10 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp, tconnects[ppinnum].second = argp; ++tpinnum; } else if (makeChanges) { - pinp->v3error("Too many arguments in function call to " + argp->v3error("Too many arguments in function call to " << nodep->taskp()->prettyTypeName()); // We'll just delete it; seems less error prone than making a false argument - VL_DO_DANGLING(pinp->unlinkFrBack()->deleteTree(), pinp); + VL_DO_DANGLING(argp->unlinkFrBack()->deleteTree(), argp); } } else { tconnects[ppinnum].second = argp; @@ -1834,14 +1890,14 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp, if (reorganize) { // To simplify downstream, put argument list back into pure pinnumber ordering - while (nodep->pinsp()) { + while (nodep->argsp()) { // Must unlink each pin, not all pins linked together as one list - nodep->pinsp()->unlinkFrBack(); + nodep->argsp()->unlinkFrBack(); } for (int i = 0; i < tpinnum; ++i) { AstArg* const argp = tconnects[i].second; UASSERT_OBJ(argp, nodep, "Lost argument in func conversion"); - nodep->addPinsp(argp); + nodep->addArgsp(argp); } } @@ -1913,13 +1969,13 @@ AstNodeFTask* V3Task::taskConnectWrapNew(AstNodeFTask* taskp, const string& newn newFVarp->name(newTaskp->name()); newTaskp->fvarp(newFVarp); newTaskp->dtypeFrom(newFVarp); - newCallp = new AstFuncRef{taskp->fileline(), VN_AS(taskp, Func), nullptr}; + newCallp = new AstFuncRef{taskp->fileline(), VN_AS(taskp, Func)}; newCallInsertp = new AstAssign{taskp->fileline(), new AstVarRef{fvarp->fileline(), newFVarp, VAccess::WRITE}, newCallp}; newCallInsertp->dtypeFrom(newFVarp); } else if (VN_IS(taskp, Task)) { - newCallp = new AstTaskRef{taskp->fileline(), VN_AS(taskp, Task), nullptr}; + newCallp = new AstTaskRef{taskp->fileline(), VN_AS(taskp, Task)}; newCallInsertp = new AstStmtExpr{taskp->fileline(), newCallp}; } else { taskp->v3fatalSrc("Unsupported: Non-constant default value in missing argument in a " @@ -1957,7 +2013,7 @@ AstNodeFTask* V3Task::taskConnectWrapNew(AstNodeFTask* taskp, const string& newn const VAccess pinAccess = portp->isWritable() ? VAccess::WRITE : VAccess::READ; AstArg* const newArgp = new AstArg{portp->fileline(), portp->name(), new AstVarRef{portp->fileline(), newPortp, pinAccess}}; - newCallp->addPinsp(newArgp); + newCallp->addArgsp(newArgp); } // Create wrapper call to original, passing arguments, adding setting of return value newTaskp->addStmtsp(newCallInsertp); diff --git a/src/V3Task.h b/src/V3Task.h index a5107962d..378e87330 100644 --- a/src/V3Task.h +++ b/src/V3Task.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ThreadPool.cpp b/src/V3ThreadPool.cpp index 8715b8865..a823dabe6 100644 --- a/src/V3ThreadPool.cpp +++ b/src/V3ThreadPool.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ThreadPool.h b/src/V3ThreadPool.h index 45d182554..c22984a37 100644 --- a/src/V3ThreadPool.h +++ b/src/V3ThreadPool.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp index 322f23e88..b723cbcb9 100644 --- a/src/V3Timing.cpp +++ b/src/V3Timing.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // // TimingSuspendableVisitor does not perform any AST transformations. @@ -66,12 +66,15 @@ #include "V3Const.h" #include "V3EmitV.h" +#include "V3Global.h" #include "V3Graph.h" #include "V3MemberMap.h" #include "V3SenExprBuilder.h" #include "V3SenTree.h" +#include "V3Stats.h" #include "V3UniqueNames.h" +#include #include VL_DEFINE_DEBUG_FUNCTIONS; @@ -100,7 +103,7 @@ enum PropagationType : uint8_t { }; // Add timing flag to a node -static void addFlags(AstNode* const nodep, uint8_t flags) { nodep->user2(nodep->user2() | flags); } +static void addFlags(AstNode* const nodep, uint8_t flags) { nodep->user2Or(flags); } // Check if a node has ALL of the expected flags set static bool hasFlags(AstNode* const nodep, uint8_t flags) { return !(~nodep->user2() & flags); } @@ -277,6 +280,7 @@ class TimingSuspendableVisitor final : public VNVisitor { addFlags(m_procp, T_FORCES_PROC | T_NEEDS_PROC); } void visit(AstWait* nodep) override { + UINFO(9, "suspendable-visit " << nodep); AstNodeExpr* const condp = V3Const::constifyEdit(nodep->condp()); if (AstConst* const constp = VN_CAST(condp, Const)) { if (!nodep->fileline()->warnIsOff(V3ErrorCode::WAITCONST)) { @@ -365,6 +369,7 @@ class TimingSuspendableVisitor final : public VNVisitor { iterateChildren(nodep); } void visit(AstFork* nodep) override { + UINFO(9, "suspendable-visit " << nodep); VL_RESTORER(m_underFork); v3Global.setUsesTiming(); // Even if there are no event controls, we have to set this flag @@ -473,6 +478,8 @@ class TimingControlVisitor final : public VNVisitor { int m_forkCnt = 0; // Number of forks inside a module bool m_underJumpBlock = false; // True if we are inside of a jump-block bool m_underProcedure = false; // True if we are under an always or initial + bool m_hasStaticZeroDelay = false; // True if we have a static #0 delay + std::vector m_unknownDelayFlps; // Locations of AstDelay with non-constant value // Unique names V3UniqueNames m_dlyforkNames{"__Vdlyfork"}; // Names for temp AssignW vars @@ -499,6 +506,11 @@ class TimingControlVisitor final : public VNVisitor { SenTreeFinder m_finder{m_netlistp}; // Sentree finder and uniquifier SenExprBuilder* m_senExprBuilderp = nullptr; // Sens expression builder for current m_scope + // Stats + size_t m_statZeroDelays = 0; // Number of statically known #0 delays + size_t m_statConstDelays = 0; // Number of statically known #const (non-zero) delays + size_t m_statVariableDelays = 0; // Number of delays with value unknown at compile time + // METHODS // Transform an assignment with an intra timing control into a timing control with the // assignment under it @@ -616,9 +628,10 @@ class TimingControlVisitor final : public VNVisitor { // Returns true if the given trigger expression needs a destructive post update after trigger // evaluation. Currently this only applies to named events. bool destructivePostUpdate(AstNode* const exprp) const { - return exprp->exists([](const AstNodeVarRef* const refp) { - AstBasicDType* const dtypep = refp->dtypep()->basicp(); - return dtypep && dtypep->isEvent(); + return exprp->exists([](const AstNode* const nodep) { + const AstNodeDType* const dtypep = nodep->dtypep(); + const AstBasicDType* const basicp = dtypep ? dtypep->skipRefp()->basicp() : nullptr; + return basicp && basicp->isEvent(); }); } // Creates a trigger scheduler variable @@ -757,9 +770,40 @@ class TimingControlVisitor final : public VNVisitor { joinp->dtypeSetVoid(); addProcessInfo(joinp); addDebugInfo(joinp); - AstCAwait* const awaitp = new AstCAwait{flp, joinp}; - awaitp->dtypeSetVoid(); - forkp->addNextHere(awaitp->makeStmt()); + forkp->addNextHere(new AstCAwait{flp, joinp}); + } + + // `procp` shall be a NodeProcedure/CFunc/Begin and within it vars from `varsp` will be placed. + // `varsp` vector of vars which shall be localized. + static void localizeVars(AstNode* const procp, const std::vector& varsp) { + UASSERT(procp, "procp is nullptr"); + AstNode* firstStmtp; + if (AstNodeProcedure* const nodeProcp = VN_CAST(procp, NodeProcedure)) { + firstStmtp = nodeProcp->stmtsp(); + } else if (AstCFunc* const cfuncp = VN_CAST(procp, CFunc)) { + if (!cfuncp->varsp()) { + for (AstVar* const varp : varsp) { + varp->funcLocal(true); + cfuncp->addVarsp(varp->unlinkFrBack()); + } + return; + } + firstStmtp = cfuncp->varsp(); + } else if (AstBegin* const beginp = VN_CAST(procp, Begin)) { + firstStmtp = beginp->stmtsp(); + } else { + procp->v3fatalSrc( + procp->prettyNameQ() + << " is not of an expected type NodeProcedure/CFunc/Begin instead it is: " + << procp->prettyTypeName()); + } + UASSERT_OBJ(firstStmtp, procp, + procp->prettyNameQ() << " has no non-var statement. 'localizeVars()' is ment " + "to be called on non empty NodeProcedure/CFunc/Begin"); + for (AstVar* const varp : varsp) { + varp->funcLocal(true); + firstStmtp->addHereThisAsNext(varp->unlinkFrBack()); + } } // VISITORS @@ -872,11 +916,10 @@ class TimingControlVisitor final : public VNVisitor { void visit(AstNodeCCall* nodep) override { if (nodep->funcp()->needProcess()) m_hasProcess = true; if (hasFlags(nodep->funcp(), T_SUSPENDEE) && !nodep->user1SetOnce()) { // If suspendable - VNRelinker relinker; - nodep->unlinkFrBack(&relinker); - AstCAwait* const awaitp = new AstCAwait{nodep->fileline(), nodep}; - awaitp->dtypeSetVoid(); - relinker.relink(awaitp); + // Calls to suspendables are always void return type, hence parent must be StmtExpr + AstStmtExpr* const stmtp = VN_AS(nodep->backp(), StmtExpr); + stmtp->replaceWith(new AstCAwait{nodep->fileline(), nodep->unlinkFrBack()}); + VL_DO_DANGLING(pushDeletep(stmtp), stmtp); } iterateChildren(nodep); } @@ -884,27 +927,76 @@ class TimingControlVisitor final : public VNVisitor { UASSERT_OBJ(!nodep->isCycleDelay(), nodep, "Cycle delays should have been handled in V3AssertPre"); FileLine* const flp = nodep->fileline(); - AstNodeExpr* valuep = V3Const::constifyEdit(nodep->lhsp()->unlinkFrBack()); - AstConst* const constp = VN_CAST(valuep, Const); - if (!constp || !constp->isZero()) { - // Scale the delay - const double timescaleFactor = calculateTimescaleFactor(nodep, nodep->timeunit()); - if (valuep->dtypep()->skipRefp()->isDouble()) { - valuep = new AstRToIRoundS{ - flp, new AstMulD{flp, valuep, - new AstConst{flp, AstConst::RealDouble{}, timescaleFactor}}}; - valuep->dtypeSetBitSized(64, VSigning::UNSIGNED); - } else { - valuep->dtypeSetBitSized(64, VSigning::UNSIGNED); - valuep = new AstMul{flp, valuep, - new AstConst{flp, AstConst::Unsized64{}, - static_cast(timescaleFactor)}}; - } - } else if (constp->num().is1Step()) { + + AstNodeExpr* valuep = nodep->lhsp()->unlinkFrBack(); + if (VN_IS(valuep, Const) && VN_AS(valuep, Const)->num().is1Step()) { + // #1step special case VL_DO_DANGLING(valuep->deleteTree(), valuep); valuep = new AstConst{flp, AstConst::Unsized64{}, 1}; valuep->dtypeSetBitSized(64, VSigning::UNSIGNED); + } else { + AstConst* const constp = VN_CAST(valuep, Const); + const bool isForkSentinel + = constp && (constp->toUQuad() == std::numeric_limits::max()); + if (!isForkSentinel && (!constp || !constp->isZero())) { + // Scale the delay + const double timescaleFactorD = calculateTimescaleFactor(nodep, nodep->timeunit()); + if (valuep->dtypep()->skipRefp()->isDouble()) { + AstConst* const tsfp + = new AstConst{flp, AstConst::RealDouble{}, timescaleFactorD}; + valuep = new AstMulD{flp, valuep, tsfp}; + valuep = new AstRToIRoundS{flp, valuep}; + valuep->dtypeSetBitSized(64, VSigning::UNSIGNED); + } else { + valuep->dtypeSetBitSized(64, VSigning::UNSIGNED); + const uint64_t timescaleFactorU = static_cast(timescaleFactorD); + AstConst* const tsfp + = new AstConst{flp, AstConst::Unsized64{}, timescaleFactorU}; + valuep = new AstMul{flp, valuep, tsfp}; + } + // Simplify + valuep = V3Const::constifyEdit(valuep); + } } + + // Statistics + if (valuep->isZero()) { + ++m_statZeroDelays; + } else if (VN_IS(valuep, Const)) { + ++m_statConstDelays; + } else { + ++m_statVariableDelays; + } + + // Decide scheduling support for #0 + if (v3Global.opt.schedZeroDelay().isSetTrue()) { + // User said to schedule for #0 support, nothing else to do + v3Global.setUsesZeroDelay(); + } else if (v3Global.opt.schedZeroDelay().isSetFalse()) { + // User said to schedule without #0 support. Still warn if a static #0 delay exists + if (valuep->isZero()) { + nodep->v3warn( + ZERODLY, + "Static #0 delay exists, but '--no-sched-zero-delay' was given.\n" + << nodep->warnMore() // + << "... Can proceed, but this will fail at runtime if executed."); + } + } else { + // User did not express preference, decide based on presence of delays + if (valuep->isZero()) { + // Statically known #0 delay exists, schedule for #0 support + v3Global.setUsesZeroDelay(); + m_hasStaticZeroDelay = true; + // Don't warn on variable delays, as no point + m_unknownDelayFlps.clear(); + } else if (!VN_IS(valuep, Const)) { + // Delay is not known at compiile time. Conservatively schedule for #0 support, + // but warn if no static #0 delays used as performance might be improved + v3Global.setUsesZeroDelay(); + if (!m_hasStaticZeroDelay) m_unknownDelayFlps.push_back(nodep->fileline()); + } + } + // Replace self with a 'co_await dlySched.delay()' AstCMethodHard* const delayMethodp = new AstCMethodHard{ flp, new AstVarRef{flp, getCreateDelayScheduler(), VAccess::WRITE}, @@ -913,15 +1005,12 @@ class TimingControlVisitor final : public VNVisitor { addProcessInfo(delayMethodp); addDebugInfo(delayMethodp); // Create the co_await - AstCAwait* const awaitp = new AstCAwait{flp, delayMethodp, getCreateDelaySenTree()}; - awaitp->dtypeSetVoid(); - AstStmtExpr* const awaitStmtp = awaitp->makeStmt(); + AstNode* const awaitp = new AstCAwait{flp, delayMethodp, getCreateDelaySenTree()}; // Relink child statements after the co_await - if (nodep->stmtsp()) { - AstNode::addNext(awaitStmtp, - nodep->stmtsp()->unlinkFrBackWithNext()); + if (AstNode* const stmtsp = nodep->stmtsp()) { + awaitp->addNext(stmtsp->unlinkFrBackWithNext()); } - nodep->replaceWith(awaitStmtp); + nodep->replaceWith(awaitp); VL_DO_DANGLING(nodep->deleteTree(), nodep); } void visit(AstEventControl* nodep) override { @@ -954,13 +1043,13 @@ class TimingControlVisitor final : public VNVisitor { // Create the co_await AstCAwait* const awaitEvalp = new AstCAwait{flp, evalMethodp, getCreateDynamicTriggerSenTree()}; - awaitEvalp->dtypeSetVoid(); // Construct the sen expression for this sentree UASSERT_OBJ(m_senExprBuilderp, nodep, "No SenExprBuilder for this scope"); auto* const assignp = new AstAssign{flp, new AstVarRef{flp, trigvscp, VAccess::WRITE}, m_senExprBuilderp->build(sentreep).first}; // Get the SenExprBuilder results const SenExprBuilder::Results senResults = m_senExprBuilderp->getAndClearResults(); + localizeVars(m_procp, senResults.m_vars); // Put all and inits before the trigger eval loop for (AstNodeStmt* const stmtp : senResults.m_inits) { nodep->addHereThisAsNext(stmtp); @@ -971,7 +1060,7 @@ class TimingControlVisitor final : public VNVisitor { = new AstLogNot{flp, new AstVarRef{flp, trigvscp, VAccess::READ}}; AstLoop* const loopp = new AstLoop{flp}; loopp->addStmtsp(new AstLoopTest{flp, loopp, condp}); - loopp->addStmtsp(awaitEvalp->makeStmt()); + loopp->addStmtsp(awaitEvalp); // Put pre updates before the trigger check and assignment for (AstNodeStmt* const stmtp : senResults.m_preUpdates) loopp->addStmtsp(stmtp); // Then the trigger check and assignment @@ -988,14 +1077,14 @@ class TimingControlVisitor final : public VNVisitor { if (destructivePostUpdate(sentreep)) { AstCAwait* const awaitPostUpdatep = awaitEvalp->cloneTree(false); VN_AS(awaitPostUpdatep->exprp(), CMethodHard)->method(VCMethod::SCHED_POST_UPDATE); - loopp->addStmtsp(awaitPostUpdatep->makeStmt()); + loopp->addStmtsp(awaitPostUpdatep); } // Put the post updates at the end of the loop for (AstNodeStmt* const stmtp : senResults.m_postUpdates) loopp->addStmtsp(stmtp); // Finally, await the resumption step in 'act' AstCAwait* const awaitResumep = awaitEvalp->cloneTree(false); VN_AS(awaitResumep->exprp(), CMethodHard)->method(VCMethod::SCHED_RESUMPTION); - AstNode::addNext(loopp, awaitResumep->makeStmt()); + AstNode::addNext(loopp, awaitResumep); // Replace the event control with the loop nodep->replaceWith(loopp); } else { @@ -1014,14 +1103,14 @@ class TimingControlVisitor final : public VNVisitor { addEventDebugInfo(triggerMethodp, sentreep); // Create the co_await AstCAwait* const awaitp = new AstCAwait{flp, triggerMethodp, sentreep}; - awaitp->dtypeSetVoid(); - nodep->replaceWith(awaitp->makeStmt()); + nodep->replaceWith(awaitp); } VL_DO_DANGLING(nodep->deleteTree(), nodep); } void visit(AstNodeAssign* nodep) override { // Only process once to avoid infinite loops (due to the net delay) if (nodep->user1SetOnce()) return; + UINFO(9, "control-visit " << nodep); FileLine* const flp = nodep->fileline(); AstNode* controlp = factorOutTimingControl(nodep); const bool inAssignDly = VN_IS(nodep, AssignDly); @@ -1029,7 +1118,10 @@ class TimingControlVisitor final : public VNVisitor { // Transform if: // * there's a timing control in the assignment // * the assignment is an AssignDly and it's in a non-inlined function - if (!controlp && (!inAssignDly || m_underProcedure)) return; + if (!controlp && (!inAssignDly || m_underProcedure)) { + iterateChildren(nodep); + return; + } // Insert new vars before the timing control if we're in a function; in a process we can't // do that. These intra-assignment vars will later be passed to forked processes by value. AstNode* insertBeforep = m_underProcedure ? nullptr : controlp; @@ -1168,10 +1260,16 @@ class TimingControlVisitor final : public VNVisitor { new AstAssign{flp, new AstVarRef{flp, tmpVarp, VAccess::WRITE}, tmpAssignRhsp}); // If the RHS is different from the currently scheduled value, schedule the new assignment // The generation will increase, effectively 'descheduling' the previous assignment. - alwaysp->addStmtsp(new AstIf{flp, - new AstNeq{flp, preAssignp->rhsp()->cloneTree(false), - new AstVarRef{flp, tmpVarp, VAccess::READ}}, - forkp->unlinkFrBack()}); + AstNodeExpr* const didNotInitp + = new AstLogNot{flp, new AstCExpr{flp, "vlSymsp->__Vm_didInit", 1}}; + AstVarRef* const firstIterp + = new AstVarRef{flp, m_netlistp->stlFirstIterationp(), VAccess::READ}; + AstNodeExpr* const schedCondp + = new AstLogOr{flp, + new AstNeq{flp, preAssignp->rhsp()->cloneTree(false), + new AstVarRef{flp, tmpVarp, VAccess::READ}}, + new AstLogAnd{flp, didNotInitp, firstIterp}}; + alwaysp->addStmtsp(new AstIf{flp, schedCondp, forkp->unlinkFrBack()}); } void visit(AstDisableFork* nodep) override { if (m_hasProcess) return; @@ -1192,6 +1290,7 @@ class TimingControlVisitor final : public VNVisitor { } void visit(AstWait* nodep) override { // Wait on changed events related to the vars in the wait statement + UINFO(9, "control-visit " << nodep); FileLine* const flp = nodep->fileline(); AstNode* const stmtsp = nodep->stmtsp(); if (stmtsp) stmtsp->unlinkFrBackWithNext(); @@ -1203,8 +1302,7 @@ class TimingControlVisitor final : public VNVisitor { // callstack AstCExpr* const foreverp = new AstCExpr{flp, "VlForever{}"}; AstCAwait* const awaitp = new AstCAwait{flp, foreverp}; - awaitp->dtypeSetVoid(); - nodep->replaceWith(awaitp->makeStmt()); + nodep->replaceWith(awaitp); if (stmtsp) VL_DO_DANGLING(stmtsp->deleteTree(), stmtsp); VL_DO_DANGLING(condp->deleteTree(), condp); } else { @@ -1250,6 +1348,7 @@ class TimingControlVisitor final : public VNVisitor { } void visit(AstFork* nodep) override { if (nodep->user1SetOnce()) return; + UINFO(9, "control-visit " << nodep); v3Global.setUsesTiming(); // Create a unique name for this fork @@ -1281,8 +1380,28 @@ public: explicit TimingControlVisitor(AstNetlist* nodep) : m_netlistp{nodep} { iterate(nodep); + + // If there is no static #0 in the design, but an unknown delay was found, + // and the user did not specify preference, then warn on all unknown delays + // as we will be assuming they can be #0, which can cause performance degradation. + for (FileLine* const flp : m_unknownDelayFlps) { + flp->v3warn(ZERODLY, + "Value of # delay control statically unknown. Assuming it can be #0.\n" + << flp->warnMore() // + << "... If all # delays are non-zero at runtime,\n" + << flp->warnMore() // + << "... use '--no-sched-zero-delay' for improved performance.\n" + << flp->warnMore() // + << "... If a real #0 is expected at runtime,\n" + << flp->warnMore() // + << "... use '--sched-zero-delay' to suppress this warning."); + } + } + ~TimingControlVisitor() override { + V3Stats::addStat("Timing, known #0 delays", m_statZeroDelays); + V3Stats::addStat("Timing, known #const delays", m_statConstDelays); + V3Stats::addStat("Timing, unknown #variable delays", m_statVariableDelays); } - ~TimingControlVisitor() override = default; }; //###################################################################### diff --git a/src/V3Timing.h b/src/V3Timing.h index 1a44a1408..94ac15602 100644 --- a/src/V3Timing.h +++ b/src/V3Timing.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp index 37707fb68..4b532e76f 100644 --- a/src/V3Trace.cpp +++ b/src/V3Trace.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -190,7 +190,6 @@ class TraceVisitor final : public VNVisitor { VDouble0 m_statSetters; // Statistic tracking VDouble0 m_statSettersSlow; // Statistic tracking - VDouble0 m_statUniqCodes; // Statistic tracking VDouble0 m_statUniqSigs; // Statistic tracking // All activity numbers applying to a given trace @@ -595,19 +594,18 @@ class TraceVisitor final : public VNVisitor { // no need to create a TraceInc node. const AstTraceDecl* const canonDeclp = canonVtxp->nodep(); UASSERT_OBJ(!canonVtxp->duplicatep(), canonDeclp, "Canonical node is a duplicate"); - UASSERT_OBJ(canonDeclp->code() != 0, canonDeclp, + UASSERT_OBJ(canonDeclp->codeAssigned(), canonDeclp, "Canonical node should have code assigned already"); declp->code(canonDeclp->code()); continue; } // This is a canonical trace node. Assign trace code (signal number). - UASSERT_OBJ(declp->code() == 0, declp, + UASSERT_OBJ(!declp->codeAssigned(), declp, "Canonical node should not have code assigned yet"); declp->code(m_code); const uint32_t codeInc = declp->codeInc(); m_code += codeInc; - m_statUniqCodes += codeInc; ++m_statUniqSigs; // If this is a const signal, add the AstTraceInc @@ -839,9 +837,6 @@ class TraceVisitor final : public VNVisitor { // VISITORS void visit(AstNetlist* nodep) override { - m_code = 1; // Multiple TopScopes will require fixing how code#s - // are assigned as duplicate varscopes must result in the same tracing code#. - // Add vertexes for all TraceDecl, and edges from VARs each trace looks at m_finding = false; iterateChildren(nodep); @@ -852,6 +847,9 @@ class TraceVisitor final : public VNVisitor { // Create the trace functions and insert them into the tree createTraceFunctions(); + + // Save number of trace codes used + nodep->nTraceCodes(m_code); } void visit(AstNodeModule* nodep) override { if (nodep->isTop()) m_topModp = nodep; @@ -945,7 +943,7 @@ public: ~TraceVisitor() override { V3Stats::addStat("Tracing, Activity setters", m_statSetters); V3Stats::addStat("Tracing, Activity slow blocks", m_statSettersSlow); - V3Stats::addStat("Tracing, Unique trace codes", m_statUniqCodes); + V3Stats::addStat("Tracing, Unique trace codes", m_code); V3Stats::addStat("Tracing, Unique traced signals", m_statUniqSigs); } }; diff --git a/src/V3Trace.h b/src/V3Trace.h index 5204c5277..84d395f98 100644 --- a/src/V3Trace.h +++ b/src/V3Trace.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index 9a8ad49b2..940066dca 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -51,32 +51,37 @@ public: , m_emit{emit} {} // Emit Prefix adjustments until the current path is 'newPath' - void adjust(const string& newPath) { + void adjust(const string& newPath, AstCell* cellp, AstVarScope* vscp) { // Move up to enclosing path - unsigned toPop = 0; while (!VString::startsWith(newPath, m_stack.back())) { - ++toPop; + m_emit(new AstTracePopPrefix{m_flp}); m_stack.pop_back(); } - while (toPop--) m_emit(new AstTracePopPrefix{m_flp}); + + if (newPath == m_stack.back()) return; + + const VTracePrefixType lastScopeType = // + (cellp && VN_IS(cellp->modp(), Iface)) + || (vscp && VN_IS(vscp->dtypep(), IfaceRefDType)) + ? VTracePrefixType::SCOPE_INTERFACE + : VTracePrefixType::SCOPE_MODULE; + const std::string extraPrefix = newPath.substr(m_stack.back().size()); + size_t begin = 0; + size_t last = extraPrefix.rfind(SEPARATOR); // Move down, one path element at a time - if (newPath != m_stack.back()) { - const string& extraPrefix = newPath.substr(m_stack.back().size()); - size_t begin = 0; - while (true) { - const size_t end = extraPrefix.find(SEPARATOR, begin); - if (end == string::npos) break; - const string& extra = extraPrefix.substr(begin, end - begin); + while (true) { + const size_t end = extraPrefix.find(SEPARATOR, begin); + if (end == string::npos) break; + const string& extra = extraPrefix.substr(begin, end - begin); + if (end == last) { + m_emit(new AstTracePushPrefix{m_flp, extra, lastScopeType}); + } else { m_emit(new AstTracePushPrefix{m_flp, extra, VTracePrefixType::SCOPE_MODULE}); - m_stack.push_back(m_stack.back() + extra + SEPARATOR); - begin = end + 1; - } - const string& extra = extraPrefix.substr(begin); - if (!extra.empty()) { - m_emit(new AstTracePushPrefix{m_flp, extra, VTracePrefixType::SCOPE_MODULE}); - m_stack.push_back(m_stack.back() + extra); } + m_stack.push_back(m_stack.back() + extra + SEPARATOR); + begin = end + 1; } + UASSERT(begin == extraPrefix.size(), "Should have consumed all of extraPrefix"); } // Emit Prefix adjustments to unwind the path back to its original state @@ -89,8 +94,6 @@ public: // TraceDecl state, as a visitor of each AstNode class TraceDeclVisitor final : public VNVisitor { - // NODE STATE - // STATE AstTopScope* const m_topScopep; // The singleton AstTopScope const AstScope* m_currScopep = nullptr; // Current scope being visited @@ -124,29 +127,55 @@ class TraceDeclVisitor final : public VNVisitor { AstCell* m_cellp = nullptr; // Sub scope (as AstCell) under scope being traced std::string m_path; // Path to enclosing module in original hierarchy std::string m_name; // Name of signal/subscope - bool m_rootio = false; // Is part of $rootio, if model at runtime uses name()="" - void init(const std::string& name) { + void init(const std::string& name, AstNode* nodep, bool inTopScope) { // Compute path in hierarchy and item name const std::string& vcdName = AstNode::vcdName(name); - const size_t pos = vcdName.rfind(' '); - const size_t pathLen = pos == std::string::npos ? 0 : pos + 1; - m_path = vcdName.substr(0, pathLen); - m_name = vcdName.substr(pathLen); + AstVar* const varp = VN_CAST(nodep, Var); + if (VN_IS(nodep, Cell) || VN_IS(varp->dtypep(), IfaceRefDType)) { + // Cell or interface reference + m_path = vcdName + " "; + m_name.clear(); + } else if (varp->isPrimaryIO()) { + // Primary IO variable + m_path = "$rootio "; + m_name = vcdName; + } else { + // Other Variable + const size_t pos = vcdName.rfind(' '); + const size_t pathLen = pos == std::string::npos ? 0 : pos + 1; + m_path = vcdName.substr(0, pathLen); + m_name = vcdName.substr(pathLen); + } + + // When creating a --lib-create library, drop the name of the top module (l2 name). + // This will be replaced by the instance name in the model that uses the library. + // This would be a bit murky when there are other top level entities ($unit, + // packages, which have an instance in all libs - a problem on its own). If + // --top-module was explicitly specified, then we will drop the prefix only for the + // actual top level module, and wrap the rest in '$libroot'. This way at least we get a + // usable dump of everything, with library instances showing in a right place, without + // pollution from other top level entities. + if (inTopScope && !v3Global.opt.libCreate().empty()) { + const size_t start = m_path.find(' '); + // Must have a prefix in the top scope with lib, as top wrapper signals not traced + UASSERT_OBJ(start != std::string::npos, nodep, "No prefix with --lib-create"); + const std::string prefix = m_path.substr(0, start); + m_path = m_path.substr(start + 1); + if (v3Global.opt.topModule() != prefix) m_path = "$libroot " + m_path; + } } public: - explicit TraceEntry(AstVarScope* vscp) + explicit TraceEntry(const AstScope* scopep, AstVarScope* vscp) : m_vscp{vscp} { - init(vscp->varp()->name()); + init(vscp->varp()->name(), vscp->varp(), scopep->isTop()); } - explicit TraceEntry(AstCell* cellp) + explicit TraceEntry(const AstScope* scopep, AstCell* cellp) : m_cellp{cellp} { - init(cellp->name()); + init(cellp->name(), cellp, scopep->isTop()); } int operatorCompare(const TraceEntry& b) const { - if (rootio() && !b.rootio()) return true; - if (!rootio() && b.rootio()) return false; if (const int cmp = path().compare(b.path())) return cmp < 0; if (const int cmp = fileline().operatorCompare(b.fileline())) return cmp < 0; return name() < b.name(); @@ -157,8 +186,6 @@ class TraceDeclVisitor final : public VNVisitor { void path(const std::string& path) { m_path = path; } const std::string& name() const { return m_name; } FileLine& fileline() const { return m_vscp ? *m_vscp->fileline() : *m_cellp->fileline(); } - bool rootio() const { return m_rootio; } - void rootio(bool flag) { m_rootio = flag; } }; std::vector m_entries; // Trace entries under current scope AstVarScope* m_traVscp = nullptr; // Current AstVarScope we are constructing AstTraceDecls for @@ -176,6 +203,12 @@ class TraceDeclVisitor final : public VNVisitor { const AstVar* const varp = nodep->varp(); if (!varp->isTrace()) return "Verilator trace_off"; if (!nodep->isTrace()) return "Verilator instance trace_off"; + // Automatics (typically, excluding forks) have no persistance over + // time, and may optimize differently when multithreadeded or hierarchical. + // Class automatics refer to being in a class but might still be pointed + // to by a static, so are ok. + if (varp->lifetime().isAutomatic() && !varp->isClassMember() && !varp->isParam()) + return "Automatic variable"; const int width = recurseDTypeWidth(nodep->varp()->dtypep()); if (v3Global.opt.traceMaxWidth() && width > v3Global.opt.traceMaxWidth()) @@ -262,45 +295,43 @@ class TraceDeclVisitor final : public VNVisitor { // Find the scope for the path. As we are working based on cell names, // it is possible there is no corresponding scope (e.g.: for an empty // module). - const auto it = m_pathToScopep.find(path); + const auto it = m_pathToScopep.find(AstNode::prettyName(path)); if (it != m_pathToScopep.end()) { const AstScope* const scopep = it->second; FileLine* const flp = placeholderp->fileline(); - // Pick up the last path element. The prefixes have already been pushed - // when building the initialization functions - const size_t pos = path.rfind('.'); - const std::string name = path.substr(pos == string::npos ? 0 : pos + 1); - - // Compute the type of the scope being fixed up - const AstCell* const cellp = scopep->aboveCellp(); - const VTracePrefixType scopeType - = cellp ? (VN_IS((cellp->modp()), Iface) ? VTracePrefixType::SCOPE_INTERFACE - : VTracePrefixType::SCOPE_MODULE) - : VTracePrefixType::SCOPE_MODULE; - - // Push the scope prefix - AstNodeStmt* const pushp = new AstTracePushPrefix{flp, name, scopeType}; - // Call the initialization functions for the scope + AstNode* stmtp = nullptr; for (AstCFunc* const subFuncp : m_scopeInitFuncps.at(scopep)) { AstCCall* const callp = new AstCCall{flp, subFuncp}; callp->dtypeSetVoid(); callp->argTypes("tracep"); - pushp->addNext(callp->makeStmt()); + stmtp = AstNode::addNext(stmtp, callp->makeStmt()); } - // Pop the scope prefix - pushp->addNext(new AstTracePopPrefix{flp}); - // Add after the placeholder - placeholderp->addNextHere(pushp); + if (stmtp) placeholderp->addNextHere(stmtp); } // Delete the placeholder placeholderp->unlinkFrBack(); VL_DO_DANGLING(placeholderp->deleteTree(), placeholderp); } + void fixupLibStub(const std::string& path, AstNodeStmt* placeholderp) { + FileLine* const flp = placeholderp->fileline(); + + // Call the initialization function for the library instance + AstCStmt* const initp = new AstCStmt{flp}; + initp->add("tracep->initLib(vlSymsp->name() + "); + initp->add(new AstConst{flp, AstConst::String{}, "." + AstNode::prettyName(path)}); + initp->add(");\n"); + + placeholderp->addNextHere(initp); + // Delete the placeholder + VL_DO_DANGLING(placeholderp->unlinkFrBack()->deleteTree(), placeholderp); + return; + } + void fixupPlaceholders() { // Fix up cell initialization placehodlers UINFO(9, "fixupPlaceholders()"); @@ -308,15 +339,19 @@ class TraceDeclVisitor final : public VNVisitor { const AstScope* const parentp = std::get<0>(item); const AstCell* const cellp = std::get<1>(item); AstNodeStmt* const placeholderp = std::get<2>(item); - const std::string path = AstNode::prettyName(parentp->name() + "." + cellp->name()); - fixupPlaceholder(path, placeholderp); + const std::string path = parentp->name() + "__DOT__" + cellp->name(); + if (cellp->modp()->verilatorLib()) { + fixupLibStub(path, placeholderp); + } else { + fixupPlaceholder(path, placeholderp); + } } // Fix up interface reference initialization placeholders for (const auto& item : m_ifaceRefInitPlaceholders) { const AstVarScope* const vscp = std::get<0>(item); AstNodeStmt* const placeholderp = std::get<1>(item); - const std::string path = vscp->prettyName(); + const std::string path = vscp->scopep()->name() + "__DOT__" + vscp->varp()->name(); fixupPlaceholder(path, placeholderp); } } @@ -369,6 +404,9 @@ class TraceDeclVisitor final : public VNVisitor { UASSERT_OBJ(!m_traValuep, nodep, "Should not nest"); UASSERT_OBJ(m_traName.empty(), nodep, "Should not nest"); + // If this is a stub for a --lib-create library, skip. + if (nodep->modp()->verilatorLib()) return; + VL_RESTORER(m_currScopep); m_currScopep = nodep; @@ -377,20 +415,12 @@ class TraceDeclVisitor final : public VNVisitor { // Gather cells under this scope for (AstNode* stmtp = nodep->modp()->stmtsp(); stmtp; stmtp = stmtp->nextp()) { - if (AstCell* const cellp = VN_CAST(stmtp, Cell)) m_entries.emplace_back(cellp); + if (AstCell* const cellp = VN_CAST(stmtp, Cell)) m_entries.emplace_back(nodep, cellp); } if (!m_entries.empty()) { - if (nodep->name() == "TOP") { - UINFO(9, " Add $rootio " << nodep); - for (TraceEntry& entry : m_entries) { - if (entry.path() == "" && entry.vscp()) entry.rootio(true); - } - } - - // Sort trace entries, first by if a $root io, then by enclosing instance - // (necessary for single traversal of hierarchy during initialization), then - // by source location, then by name. + // Sort trace entries, by enclosing instance (necessary for single traversal of + // hierarchy during initialization), then by source location, then by name. std::stable_sort( m_entries.begin(), m_entries.end(), [](const TraceEntry& a, const TraceEntry& b) { return a.operatorCompare(b); }); @@ -403,7 +433,7 @@ class TraceDeclVisitor final : public VNVisitor { UINFO(9, "path='" << entry.path() << "' name='" << entry.name() << "' " << (entry.cellp() ? static_cast(entry.cellp()) : static_cast(entry.vscp()))); - pathAdjustor.adjust(entry.rootio() ? "$rootio" : entry.path()); + pathAdjustor.adjust(entry.path(), entry.cellp(), entry.vscp()); m_traName = entry.name(); @@ -496,8 +526,16 @@ class TraceDeclVisitor final : public VNVisitor { if (nodep->varp()->isClassMember()) return; if (nodep->varp()->isFuncLocal()) return; + // When creating a --lib-create library ... + if (!v3Global.opt.libCreate().empty()) { + // Ignore the wrapper created primary IO ports + if (nodep->varp()->isPrimaryIO()) return; + // Ignore parameters in packages. These will be traced at the top level. + if (nodep->varp()->isParam() && VN_IS(nodep->scopep()->modp(), Package)) return; + } + // Add to traced signal list - m_entries.emplace_back(nodep); + m_entries.emplace_back(m_currScopep, nodep); } // VISITORS - Data types when tracing diff --git a/src/V3TraceDecl.h b/src/V3TraceDecl.h index 7ff64620d..8a6189f07 100644 --- a/src/V3TraceDecl.h +++ b/src/V3TraceDecl.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp index 33d64df4d..667184be7 100644 --- a/src/V3Tristate.cpp +++ b/src/V3Tristate.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -44,7 +44,7 @@ // the module level, all the output enable signals from what can be // many tristate drivers are combined together to produce a single // driver and output enable. If the signal propagates up into higher -// modules, then new ports are created with for the signal with +// modules, then new ports are created for the signal with // suffixes __en and __out. The original port is turned from an inout // to an input and the __out port carries the output driver signal and // the __en port carried the output enable for that driver. @@ -55,8 +55,10 @@ // duplicating vars and logic that is common between each instance of a // module. // +//---------------------------------------------------------------------- // // Another thing done in this phase is signal strength handling. +// // Currently they are only supported in assignments and gates parsed as assignments (see verilog.y) // when any of the cases occurs: // - it is possible to statically resolve all drivers, @@ -190,8 +192,8 @@ private: public: // CONSTRUCTORS - TristateGraph() { clear(); } - virtual ~TristateGraph() { clear(); } + TristateGraph() { clearAndCheck(); } + virtual ~TristateGraph() { clearAndCheck(); } VL_UNCOPYABLE(TristateGraph); private: @@ -228,7 +230,7 @@ private: } } else { // A variable is tristated. Find all of the LHS VARREFs that - // drive this signal now need tristate drivers + // drive this signal; they now need tristate drivers for (V3GraphEdge& edge : vtxp->inEdges()) { TristateVertex* const vvertexp = static_cast(edge.fromp()); if (const AstVarRef* const refp = VN_CAST(vvertexp->nodep(), VarRef)) { @@ -269,7 +271,7 @@ private: public: // METHODS bool empty() const { return m_graph.empty(); } - void clear() { + void clearAndCheck() { for (V3GraphVertex& vtx : m_graph.vertices()) { const TristateVertex& vvertex = static_cast(vtx); if (vvertex.isTristate() && !vvertex.processed()) { @@ -316,17 +318,16 @@ public: const TristateVertex* const vertexp = reinterpret_cast(nodep->user4p()); return vertexp && vertexp->feedsTri(); } - void didProcess(AstNode* nodep) { - TristateVertex* const vertexp = reinterpret_cast(nodep->user4p()); - if (!vertexp) { + void didProcess(AstNode* nodep, bool quiet = false) { + if (TristateVertex* const vertexp = reinterpret_cast(nodep->user4p())) { + // We don't warn if no vertexp->isTristate() as the creation + // process makes midling nodes that don't have it set + vertexp->processed(true); + } else if (!quiet) { // Not v3errorSrc as no reason to stop the world nodep->v3warn(E_UNSUPPORTED, "Unsupported tristate construct (not in propagation graph): " << nodep->prettyTypeName()); - } else { - // We don't warn if no vertexp->isTristate() as the creation - // process makes midling nodes that don't have it set - vertexp->processed(true); } } // ITERATOR METHODS @@ -423,8 +424,8 @@ class TristateVisitor final : public TristateBaseVisitor { enum : uint8_t { U2_GRAPHING = 1, // bit[0] if did m_graphing visit U2_NONGRAPH = 2, // bit[1] if did !m_graphing visit - U2_BOTH = 3 - }; // Both bits set + U2_BOTH = 3 // Both bits set + }; // MEMBERS bool m_graphing = false; // Major mode - creating graph @@ -600,7 +601,7 @@ class TristateVisitor final : public TristateBaseVisitor { nodep->v3warn(E_UNSUPPORTED, "Unsupported LHS tristate construct: " << nodep->prettyTypeName()); } - // Ignore Var's because they end up adjacent to statements + // Ignore Var because they end up adjacent to statements if ((nodep->op1p() && nodep->op1p()->user1p() && !VN_IS(nodep->op1p(), Var)) || (nodep->op2p() && nodep->op2p()->user1p() && !VN_IS(nodep->op2p(), Var)) || (nodep->op3p() && nodep->op3p()->user1p() && !VN_IS(nodep->op3p(), Var)) @@ -616,23 +617,20 @@ class TristateVisitor final : public TristateBaseVisitor { // them to the lhs map so they get expanded correctly. const TristateGraph::VarVec vars = m_tgraph.tristateVars(); for (auto varp : vars) { - if (m_tgraph.isTristate(varp)) { - const auto it = m_lhsmap.find(varp); - if (it == m_lhsmap.end()) { - // This variable is floating, set output enable to - // always be off on this assign - UINFO(8, " Adding driver to var " << varp); - AstConst* const constp = newAllZerosOrOnes(varp, false); - AstVarRef* const varrefp - = new AstVarRef{varp->fileline(), varp, VAccess::WRITE}; - AstAssignW* const newp = new AstAssignW{varp->fileline(), varrefp, constp}; - UINFO(9, " newoev " << newp); - varrefp->user1p(newAllZerosOrOnes(varp, false)); - nodep->addStmtsp(new AstAlways{newp}); - mapInsertLhsVarRef(varrefp); // insertTristates will convert - // // to a varref to the __out# variable - } - } + if (!m_tgraph.isTristate(varp)) continue; + const auto it = m_lhsmap.find(varp); + if (it != m_lhsmap.end()) continue; + // This variable is floating, set output enable to + // always be off on this assign + UINFO(8, " Adding driver to var " << varp); + AstConst* const constp = newAllZerosOrOnes(varp, false); + AstVarRef* const varrefp = new AstVarRef{varp->fileline(), varp, VAccess::WRITE}; + AstAssignW* const newp = new AstAssignW{varp->fileline(), varrefp, constp}; + UINFO(9, " newoev " << newp); + varrefp->user1p(newAllZerosOrOnes(varp, false)); + nodep->addStmtsp(new AstAlways{newp}); + mapInsertLhsVarRef(varrefp); // insertTristates will convert + // // to a varref to the __out# variable } // Now go through the lhs driver map and generate the output @@ -729,7 +727,7 @@ class TristateVisitor final : public TristateBaseVisitor { bool isTopInout = (invarp->direction() == VDirection::INOUT) && invarp->isIO() && nodep->isTop(); if ((v3Global.opt.pinsInoutEnables() && isTopInout) - || ((!nodep->isTop()) && invarp->isIO())) { + || (!nodep->isTop() && invarp->isIO())) { // This var becomes an input invarp->varType2In(); // convert existing port to type input // Create an output port (__out) @@ -739,8 +737,7 @@ class TristateVisitor final : public TristateBaseVisitor { UINFO(9, " TRISTATE propagates up with " << lhsp); // Create an output enable port (__en) // May already be created if have foo === 1'bz somewhere - envarp - = getCreateEnVarp(invarp, isTopInout); // direction will be sen in visit(AstPin*) + envarp = getCreateEnVarp(invarp, isTopInout); // direction to be set in visit(AstPin*) // outvarp->user1p(envarp); m_varAux(outvarp).pullp = m_varAux(invarp).pullp; // AstPull* propagation @@ -766,14 +763,14 @@ class TristateVisitor final : public TristateBaseVisitor { const string strengthVarName = lhsp->name() + "__" + beginStrength->m_strength.ascii(); // var__strength variable - AstVar* varStrengthp = new AstVar{fl, VVarType::MODULETEMP, strengthVarName, - invarp}; // 2-state ok; sep enable; + AstVar* const varStrengthp = new AstVar{fl, VVarType::MODULETEMP, strengthVarName, + invarp}; // 2-state ok; sep enable; UINFO(9, " newstrength " << varStrengthp); nodep->addStmtsp(varStrengthp); // var__strength__en variable - AstVar* enVarStrengthp = new AstVar{fl, VVarType::MODULETEMP, strengthVarName + "__en", - invarp}; // 2-state ok; + AstVar* const enVarStrengthp = new AstVar{ + fl, VVarType::MODULETEMP, strengthVarName + "__en", invarp}; // 2-state ok; UINFO(9, " newenstrength " << enVarStrengthp); nodep->addStmtsp(enVarStrengthp); @@ -791,7 +788,8 @@ class TristateVisitor final : public TristateBaseVisitor { } orp = (!orp) ? exprCurrentStrengthp : new AstOr{fl, orp, exprCurrentStrengthp}; - AstNodeExpr* enVarStrengthRefp = new AstVarRef{fl, enVarStrengthp, VAccess::READ}; + AstNodeExpr* const enVarStrengthRefp + = new AstVarRef{fl, enVarStrengthp, VAccess::READ}; enp = (!enp) ? enVarStrengthRefp : new AstOr{fl, enp, enVarStrengthRefp}; @@ -831,7 +829,7 @@ class TristateVisitor final : public TristateBaseVisitor { // __out (child) or (parent) = drive-value expression AstAssignW* const assp = new AstAssignW{ lhsp->fileline(), new AstVarRef{lhsp->fileline(), lhsp, VAccess::WRITE}, orp}; - assp->user2(U2_BOTH); // Don't process further; already resolved + assp->user2Or(U2_BOTH); // Don't process further; already resolved UINFOTREE(9, assp, "", "lhsp-eqn"); nodep->addStmtsp(new AstAlways{assp}); @@ -928,33 +926,31 @@ class TristateVisitor final : public TristateBaseVisitor { // same Net (merge by or for WOR/TIOR and merge by and for WAND/TRIAND). for (auto& varpAssigns : m_assigns) { Assigns& assigns = varpAssigns.second; - if (assigns.size() > 1) { - AstVar* varp = varpAssigns.first; - if (varp->isWiredNet()) { - auto it = assigns.begin(); - AstAssignW* const assignWp0 = *it; - FileLine* const fl = assignWp0->fileline(); - AstNodeExpr* wExp = nullptr; - while (++it != assigns.end()) { - AstAssignW* assignWpi = *it; - if (!wExp) { - wExp = newMergeExpr(assignWp0->rhsp()->cloneTreePure(false), - assignWpi->rhsp()->cloneTreePure(false), fl, - varp->isWor()); - } else { - wExp = newMergeExpr(wExp, assignWpi->rhsp()->cloneTreePure(false), fl, - varp->isWor()); - } - VL_DO_DANGLING((assignWpi->unlinkFrBack()->deleteTree()), assignWpi); - } - AstVarRef* const wVarRef = new AstVarRef{fl, varp, VAccess::WRITE}; - AstAssignW* const wAssignp = new AstAssignW{fl, wVarRef, wExp}; - assignWp0->replaceWith(wAssignp); - VL_DO_DANGLING(pushDeletep(assignWp0), assignWp0); - assigns.clear(); - assigns.push_back(wAssignp); + if (assigns.size() <= 1) continue; + AstVar* const varp = varpAssigns.first; + if (!varp->isWiredNet()) continue; + auto it = assigns.begin(); + AstAssignW* const assignWp0 = *it; + FileLine* const fl = assignWp0->fileline(); + AstNodeExpr* wExp = nullptr; + while (++it != assigns.end()) { + AstAssignW* assignWpi = *it; + if (!wExp) { + wExp + = newMergeExpr(assignWp0->rhsp()->cloneTreePure(false), + assignWpi->rhsp()->cloneTreePure(false), fl, varp->isWor()); + } else { + wExp = newMergeExpr(wExp, assignWpi->rhsp()->cloneTreePure(false), fl, + varp->isWor()); } + VL_DO_DANGLING((assignWpi->unlinkFrBack()->deleteTree()), assignWpi); } + AstVarRef* const wVarRef = new AstVarRef{fl, varp, VAccess::WRITE}; + AstAssignW* const wAssignp = new AstAssignW{fl, wVarRef, wExp}; + assignWp0->replaceWith(wAssignp); + VL_DO_DANGLING(pushDeletep(assignWp0), assignWp0); + assigns.clear(); + assigns.push_back(wAssignp); } } @@ -984,26 +980,25 @@ class TristateVisitor final : public TristateBaseVisitor { // value (0 or 1), is found, all weaker assignments can be safely removed. for (auto& varpAssigns : m_assigns) { Assigns& assigns = varpAssigns.second; - if (assigns.size() > 1) { - const AstAssignW* const strongest0p = getStrongestAssignmentOfValue(assigns, 0); - const AstAssignW* const strongest1p = getStrongestAssignmentOfValue(assigns, 1); - const AstAssignW* strongestp = nullptr; - uint8_t greatestKnownStrength = 0; - const auto getIfStrongest - = [&](const AstAssignW* const strongestCandidatep, bool value) { - if (!strongestCandidatep) return; - uint8_t strength = getStrength(strongestCandidatep, value); - if (strength >= greatestKnownStrength) { - greatestKnownStrength = strength; - strongestp = strongestCandidatep; - } - }; - getIfStrongest(strongest0p, 0); - getIfStrongest(strongest1p, 1); + if (assigns.size() <= 1) continue; + const AstAssignW* const strongest0p = getStrongestAssignmentOfValue(assigns, 0); + const AstAssignW* const strongest1p = getStrongestAssignmentOfValue(assigns, 1); + const AstAssignW* strongestp = nullptr; + uint8_t greatestKnownStrength = 0; + const auto getIfStrongest + = [&](const AstAssignW* const strongestCandidatep, bool value) { + if (!strongestCandidatep) return; + uint8_t strength = getStrength(strongestCandidatep, value); + if (strength >= greatestKnownStrength) { + greatestKnownStrength = strength; + strongestp = strongestCandidatep; + } + }; + getIfStrongest(strongest0p, 0); + getIfStrongest(strongest1p, 1); - if (strongestp) { - removeNotStrongerAssignments(assigns, strongestp, greatestKnownStrength); - } + if (strongestp) { + removeNotStrongerAssignments(assigns, strongestp, greatestKnownStrength); } } } @@ -1016,28 +1011,22 @@ class TristateVisitor final : public TristateBaseVisitor { // constant are already removed.) for (auto& varpAssigns : m_assigns) { Assigns& assigns = varpAssigns.second; - if (assigns.size() > 1) { - auto maxIt - = std::max_element(assigns.begin(), assigns.end(), - [&](const AstAssignW* ap, const AstAssignW* bp) { - if (m_tgraph.isTristate(ap)) - return !m_tgraph.isTristate(bp); - if (m_tgraph.isTristate(bp)) return false; - const uint8_t minStrengthA - = std::min(getStrength(ap, 0), getStrength(ap, 1)); - const uint8_t minStrengthB - = std::min(getStrength(bp, 0), getStrength(bp, 1)); - return minStrengthA < minStrengthB; - }); - // If RHSs of all assignments are tristate, 1st element is returned, so it is - // needed to check if it is non-tristate. - const AstAssignW* const strongestp - = m_tgraph.isTristate(*maxIt) ? nullptr : *maxIt; - if (strongestp) { - uint8_t greatestKnownStrength - = std::min(getStrength(strongestp, 0), getStrength(strongestp, 1)); - removeNotStrongerAssignments(assigns, strongestp, greatestKnownStrength); - } + if (assigns.size() <= 1) continue; + auto maxIt = std::max_element( + assigns.begin(), assigns.end(), [&](const AstAssignW* ap, const AstAssignW* bp) { + if (m_tgraph.isTristate(ap)) return !m_tgraph.isTristate(bp); + if (m_tgraph.isTristate(bp)) return false; + const uint8_t minStrengthA = std::min(getStrength(ap, 0), getStrength(ap, 1)); + const uint8_t minStrengthB = std::min(getStrength(bp, 0), getStrength(bp, 1)); + return minStrengthA < minStrengthB; + }); + // If RHSs of all assignments are tristate, 1st element is returned, so it is + // needed to check if it is non-tristate. + const AstAssignW* const strongestp = m_tgraph.isTristate(*maxIt) ? nullptr : *maxIt; + if (strongestp) { + uint8_t greatestKnownStrength + = std::min(getStrength(strongestp, 0), getStrength(strongestp, 1)); + removeNotStrongerAssignments(assigns, strongestp, greatestKnownStrength); } } } @@ -1307,6 +1296,7 @@ class TristateVisitor final : public TristateBaseVisitor { void visitAssign(AstNodeAssign* nodep) { VL_RESTORER(m_alhs); VL_RESTORER(m_currentStrength); + if (VN_IS(nodep->rhsp(), CReset)) return; if (m_graphing) { if (AstAssignW* assignWp = VN_CAST(nodep, AssignW)) { if (assignWp->timingControlp() || assignWp->getLhsNetDelay()) return; @@ -1316,7 +1306,7 @@ class TristateVisitor final : public TristateBaseVisitor { if (nodep->user2() & U2_GRAPHING) return; VL_RESTORER(m_logicp); m_logicp = nodep; - nodep->user2(U2_GRAPHING); + nodep->user2Or(U2_GRAPHING); iterateAndNextNull(nodep->rhsp()); m_alhs = true; iterateAndNextNull(nodep->lhsp()); @@ -1327,7 +1317,7 @@ class TristateVisitor final : public TristateBaseVisitor { if (nodep->user2() & U2_NONGRAPH) { return; // Iterated here, or created assignment to ignore } - nodep->user2(U2_NONGRAPH); + nodep->user2Or(U2_NONGRAPH); iterateAndNextNull(nodep->rhsp()); UINFO(9, dbgState() << nodep); UINFOTREE(9, nodep, "", "assign"); @@ -1340,6 +1330,8 @@ class TristateVisitor final : public TristateBaseVisitor { nodep->rhsp()->user1p(nullptr); UINFO(9, " enp<-rhs " << nodep->lhsp()->user1p()); m_tgraph.didProcess(nodep); + } else { + m_tgraph.didProcess(nodep, true); } m_alhs = true; // And user1p() will indicate tristate equation, if any if (AstAssignW* const assignWp = VN_CAST(nodep, AssignW)) { @@ -1598,7 +1590,7 @@ class TristateVisitor final : public TristateBaseVisitor { void visit(AstPin* nodep) override { if (m_graphing) { if (nodep->user2() & U2_GRAPHING) return; // This pin is already expanded - nodep->user2(U2_GRAPHING); + nodep->user2Or(U2_GRAPHING); // Find child module's new variables. AstVar* const enModVarp = static_cast(nodep->modVarp()->user1p()); if (!enModVarp) { @@ -1654,10 +1646,11 @@ class TristateVisitor final : public TristateBaseVisitor { AstPin* const enpinp = new AstPin{nodep->fileline(), nodep->pinNum(), enModVarp->name(), // should be {var}"__en" - new AstVarRef{nodep->fileline(), enVarp, VAccess::WRITE}}; + new AstVarRef{nodep->fileline(), enVarp, + inDeclProcessing ? VAccess::READ : VAccess::WRITE}}; enpinp->modVarp(enModVarp); UINFO(9, " newpin " << enpinp); - enpinp->user2(U2_BOTH); // don't iterate the pin later + enpinp->user2Or(U2_BOTH); // don't iterate the pin later nodep->addNextHere(enpinp); m_modp->addStmtsp(enVarp); UINFOTREE(9, enpinp, "", "pin-ena"); @@ -1680,7 +1673,7 @@ class TristateVisitor final : public TristateBaseVisitor { outexprp}; outpinp->modVarp(outModVarp); UINFO(9, " newpin " << outpinp); - outpinp->user2(U2_BOTH); // don't iterate the pin later + outpinp->user2Or(U2_BOTH); // don't iterate the pin later nodep->addNextHere(outpinp); // Simplify if (inDeclProcessing) { // Not an input that was a converted tristate @@ -1754,7 +1747,7 @@ class TristateVisitor final : public TristateBaseVisitor { // Not graph building else { if (nodep->user2() & U2_NONGRAPH) return; // This pin is already expanded - nodep->user2(U2_NONGRAPH); + nodep->user2Or(U2_NONGRAPH); UINFO(9, " " << nodep); iteratePinGuts(nodep); } @@ -1767,7 +1760,7 @@ class TristateVisitor final : public TristateBaseVisitor { if (nodep->access().isReadOrRW()) associateLogic(nodep->varp(), nodep); } else { if (nodep->user2() & U2_NONGRAPH) return; // Processed - nodep->user2(U2_NONGRAPH); + nodep->user2Or(U2_NONGRAPH); // Detect all var lhs drivers and adds them to the // VarMap so that after the walk through the module we can expand // any tristate logic on the driver. @@ -1799,7 +1792,6 @@ class TristateVisitor final : public TristateBaseVisitor { AstVar* const enVarp = getCreateEnVarp(nodep->varp(), false); nodep->user1p(new AstVarRef{nodep->fileline(), enVarp, VAccess::READ}); } - (void)m_alhs; // NOP; user1() already passed down from assignment } } @@ -1809,7 +1801,8 @@ class TristateVisitor final : public TristateBaseVisitor { if (m_graphing) { // If tri0/1 force a pullup if (nodep->user2() & U2_GRAPHING) return; // Already processed - nodep->user2(U2_GRAPHING); + nodep->user2Or(U2_GRAPHING); + if (nodep->isPulldown() || nodep->isPullup()) { AstNode* const newp = new AstPull{ nodep->fileline(), new AstVarRef{nodep->fileline(), nodep, VAccess::WRITE}, @@ -1818,13 +1811,12 @@ class TristateVisitor final : public TristateBaseVisitor { nodep->addNextHere(newp); // We'll iterate on the new AstPull later } - if (nodep->isInout() + if (nodep->isInout()) { //|| varp->isOutput() // Note unconnected output only changes behavior vs. previous // versions and causes outputs that don't come from anywhere to // possibly create connection errors. // One example of problems is this: "output z; task t; z <= {something}; endtask" - ) { UINFO(9, " setTristate-inout " << nodep); m_tgraph.setTristate(nodep); } @@ -1837,7 +1829,7 @@ class TristateVisitor final : public TristateBaseVisitor { } void visit(AstNodeModule* nodep) override { - UINFO(8, nodep); + UINFO(8, dbgState() << nodep); VL_RESTORER(m_modp); VL_RESTORER(m_graphing); VL_RESTORER(m_unique); @@ -1845,37 +1837,38 @@ class TristateVisitor final : public TristateBaseVisitor { VL_RESTORER(m_assigns); // Not preserved, needs pointer instead: TristateGraph origTgraph = m_tgraph; UASSERT_OBJ(m_tgraph.empty(), nodep, "Unsupported: NodeModule under NodeModule"); - { - // Clear state - m_graphing = false; - m_tgraph.clear(); - m_unique = 0; - m_logicp = nullptr; - m_lhsmap.clear(); - m_assigns.clear(); - m_modp = nodep; - // Walk the graph, finding all variables and tristate constructs - { - m_graphing = true; - iterateChildren(nodep); - m_graphing = false; - } - // Merge the assignments for very Wired net LHS : wor, trior, wand and triand - mergeWiredNetsAssignments(); - // Remove all assignments not stronger than the strongest uniform constant - removeAssignmentsNotStrongerThanUniformConstant(); - // Use graph to find tristate signals - m_tgraph.graphWalk(nodep); - // Remove all assignments not stronger than the strongest non-tristate RHS - removeAssignmentsNotStrongerThanNonTristate(); + // Clear state + m_graphing = false; + m_tgraph.clearAndCheck(); + m_unique = 0; + m_logicp = nullptr; + m_lhsmap.clear(); + m_assigns.clear(); + m_modp = nodep; + // Walk the graph, finding all variables and tristate constructs + m_graphing = true; + UINFO(9, dbgState() << "graphing mod " << nodep); + iterateChildren(nodep); + m_graphing = false; + UINFO(9, dbgState() << "processing mod " << nodep); - // Build the LHS drivers map for this module - iterateChildren(nodep); - // Insert new logic for all tristates - insertTristates(nodep); - } - m_tgraph.clear(); // Recursion not supported + // Merge the assignments for very Wired net LHS : wor, trior, wand and triand + mergeWiredNetsAssignments(); + // Remove all assignments not stronger than the strongest uniform constant + removeAssignmentsNotStrongerThanUniformConstant(); + // Use graph to find tristate signals + m_tgraph.graphWalk(nodep); + + // Remove all assignments not stronger than the strongest non-tristate RHS + removeAssignmentsNotStrongerThanNonTristate(); + + // Build the LHS drivers map for this module + iterateChildren(nodep); + // Insert new logic for all tristates + insertTristates(nodep); + + m_tgraph.clearAndCheck(); // Recursion not supported } void visit(AstClass* nodep) override { @@ -1892,13 +1885,12 @@ class TristateVisitor final : public TristateBaseVisitor { void visit(AstCell* nodep) override { VL_RESTORER(m_cellp); + VL_RESTORER(m_alhs); m_cellp = nodep; m_alhs = false; iterateChildren(nodep); } - void visit(AstNetlist* nodep) override { iterateChildrenBackwardsConst(nodep); } - // Default: Just iterate void visit(AstNode* nodep) override { iterateChildren(nodep); @@ -1908,8 +1900,9 @@ class TristateVisitor final : public TristateBaseVisitor { public: // CONSTRUCTORS explicit TristateVisitor(AstNetlist* netlistp) { - m_tgraph.clear(); - iterate(netlistp); + m_tgraph.clearAndCheck(); + iterateChildrenBackwardsConst(netlistp); + #ifdef VL_LEAK_CHECKS // It's a bit chaotic up there std::vector unusedRootps; diff --git a/src/V3Tristate.h b/src/V3Tristate.h index 01cadef73..74b6b7ce7 100644 --- a/src/V3Tristate.h +++ b/src/V3Tristate.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Udp.cpp b/src/V3Udp.cpp index e724f8c59..291cfb72e 100644 --- a/src/V3Udp.cpp +++ b/src/V3Udp.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Udp.h b/src/V3Udp.h index 1d415302c..d379f9c08 100644 --- a/src/V3Udp.h +++ b/src/V3Udp.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp index 82b01ae5e..b108f40bb 100644 --- a/src/V3Undriven.cpp +++ b/src/V3Undriven.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2004-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2004-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -28,6 +28,7 @@ #include "V3Undriven.h" #include "V3Stats.h" +#include "V3UndrivenCapture.h" #include @@ -50,6 +51,9 @@ class UndrivenVarEntry final { const AstNode* m_procWritep = nullptr; // varref if written in process const FileLine* m_nodeFileLinep = nullptr; // File line of varref if driven, else nullptr bool m_underGen = false; // Under a generate + bool m_ftaskDriven = false; // Last driven by function or task + + const AstNodeFTaskRef* m_callNodep = nullptr; // Call node if driven via writeSummary enum : uint8_t { FLAG_USED = 0, FLAG_DRIVEN = 1, FLAG_DRIVEN_ALWCOMB = 2, FLAGS_PER_BIT = 3 }; @@ -113,16 +117,17 @@ private: } public: - void usedWhole() { - UINFO(9, "set u[*] " << m_varp->name()); + void usedWhole(const AstNode* nodep) { + UINFO(9, "set u[*] " << m_varp->name() << " " << nodep); m_wholeFlags[FLAG_USED] = true; } - void drivenWhole() { - UINFO(9, "set d[*] " << m_varp->name()); + void drivenWhole(const AstNode* nodep) { + UINFO(9, "set d[*] " << m_varp->name() << " " << nodep); m_wholeFlags[FLAG_DRIVEN] = true; } - void drivenWhole(const AstNodeVarRef* nodep, const FileLine* fileLinep) { - drivenWhole(); + void drivenWhole(const AstNodeVarRef* nodep, const FileLine* fileLinep, bool ftaskDef) { + m_ftaskDriven = ftaskDef && !isDrivenWhole(); + drivenWhole(nodep); m_nodep = nodep; m_nodeFileLinep = fileLinep; } @@ -140,6 +145,7 @@ public: bool isUnderGen() const { return m_underGen; } bool isDrivenWhole() const { return m_wholeFlags[FLAG_DRIVEN]; } bool isDrivenAlwaysCombWhole() const { return m_wholeFlags[FLAG_DRIVEN_ALWCOMB]; } + bool isFtaskDriven() const { return m_ftaskDriven; } const AstNodeVarRef* getNodep() const { return m_nodep; } const FileLine* getNodeFileLinep() const { return m_nodeFileLinep; } const AstAlways* getAlwCombp() const { return m_alwCombp; } @@ -179,7 +185,8 @@ public: // Combine bits into overall state AstVar* const nodep = m_varp; - if (initStaticp() && procWritep() && !nodep->isClassMember() && !nodep->isFuncLocal()) { + if (initStaticp() && procWritep() && nodep->hasUserInit() && !nodep->isClassMember() + && !nodep->isFuncLocal()) { initStaticp()->v3warn( PROCASSINIT, "Procedural assignment to declaration with initial value: " @@ -204,6 +211,8 @@ public: true); // Warn only once } } else { // Signal + const string varType{nodep->isFuncLocal() ? "Function variable" : "Signal"}; + bool funcInout = nodep->isFuncLocal() && nodep->isInout(); bool allU = true; bool allD = true; bool anyU = m_wholeFlags[FLAG_USED]; @@ -222,6 +231,10 @@ public: anyDnotU |= !used && driv; anynotDU |= !used && !driv; } + if (funcInout) { + if (anyD) allU = true; + allD = true; + } if (allU) m_wholeFlags[FLAG_USED] = true; if (allD) m_wholeFlags[FLAG_DRIVEN] = true; // Test results @@ -236,37 +249,45 @@ public: // thus undriven+unused bits get UNUSED warnings, as they're not as buggy. if (!unusedMatch(nodep)) { nodep->v3warn(UNUSEDSIGNAL, - "Signal is not driven, nor used: " << nodep->prettyNameQ()); + varType << " is not driven, nor used: " << nodep->prettyNameQ()); nodep->fileline()->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true); // Warn only once } } else if (allD && !anyU) { if (!unusedMatch(nodep)) { - nodep->v3warn(UNUSEDSIGNAL, "Signal is not used: " << nodep->prettyNameQ()); + nodep->v3warn(UNUSEDSIGNAL, + varType << " is not used: " << nodep->prettyNameQ()); nodep->fileline()->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true); // Warn only once } } else if (!anyD && allU) { - nodep->v3warn(UNDRIVEN, "Signal is not driven: " << nodep->prettyNameQ()); + nodep->v3warn(UNDRIVEN, varType << " is not driven: " << nodep->prettyNameQ()); nodep->fileline()->modifyWarnOff(V3ErrorCode::UNDRIVEN, true); // Warn only once - } else { + } else if (!funcInout) { // Bits have different dispositions + const std::string varTypeLower = [&varType]() { + std::string str = varType; + str[0] = std::tolower(static_cast(str[0])); + return str; + }(); bool setU = false; bool setD = false; if (anynotDU && !unusedMatch(nodep)) { - nodep->v3warn(UNUSEDSIGNAL, "Bits of signal are not driven, nor used: " - << nodep->prettyNameQ() << bitNames(BN_BOTH)); + nodep->v3warn(UNUSEDSIGNAL, + "Bits of " << varTypeLower << " are not driven, nor used: " + << nodep->prettyNameQ() << bitNames(BN_BOTH)); setU = true; } if (anyDnotU && !unusedMatch(nodep)) { - nodep->v3warn(UNUSEDSIGNAL, - "Bits of signal are not used: " << nodep->prettyNameQ() - << bitNames(BN_UNUSED)); + nodep->v3warn(UNUSEDSIGNAL, "Bits of " << varTypeLower << " are not used: " + << nodep->prettyNameQ() + << bitNames(BN_UNUSED)); setU = true; } if (anyUnotD) { - nodep->v3warn(UNDRIVEN, "Bits of signal are not driven: " - << nodep->prettyNameQ() << bitNames(BN_UNDRIVEN)); + nodep->v3warn(UNDRIVEN, "Bits of " << varTypeLower << " are not driven: " + << nodep->prettyNameQ() + << bitNames(BN_UNDRIVEN)); setD = true; } if (setU) { // Warn only once @@ -278,6 +299,12 @@ public: } } } + + void drivenViaCall(const AstNodeFTaskRef* nodep) { + drivenWhole(nodep); + if (!m_callNodep) m_callNodep = nodep; + } + const AstNodeFTaskRef* callNodep() const { return m_callNodep; } }; //###################################################################### @@ -296,6 +323,7 @@ class UndrivenVisitor final : public VNVisitorConst { std::array, 3> m_entryps = {}; // Nodes to delete when finished bool m_inBBox = false; // In black box; mark as driven+used bool m_inContAssign = false; // In continuous assignment + bool m_inInitialSetup = false; // In InitialAutomatic*/InitialStatic* assignment LHS bool m_inInitialStatic = false; // In InitialStatic bool m_inProcAssign = false; // In procedural assignment bool m_inFTaskRef = false; // In function or task call @@ -304,6 +332,8 @@ class UndrivenVisitor final : public VNVisitorConst { const AstAlways* m_alwaysp = nullptr; // Current always of either type const AstAlways* m_alwaysCombp = nullptr; // Current always if combo, otherwise nullptr + V3UndrivenCapture* const m_capturep = nullptr; // Capture object. 'nullptr' if disabled. + // METHODS UndrivenVarEntry* getEntryp(AstVar* nodep, int which_user) { @@ -343,22 +373,24 @@ class UndrivenVisitor final : public VNVisitorConst { // VISITORS void visit(AstVar* nodep) override { + const bool funcInout = nodep->isFuncLocal() && nodep->isInout(); for (int usr = 1; usr < (m_alwaysCombp ? 3 : 2); ++usr) { // For assigns and non-combo always, do just usr==1, to look // for module-wide undriven etc. // For combo always, run both usr==1 for above, and also // usr==2 for always-only checks. UndrivenVarEntry* const entryp = getEntryp(nodep, usr); - if (nodep->isNonOutput() || nodep->isSigPublic() || nodep->isSigUserRWPublic() + if ((nodep->isNonOutput() && !funcInout) || nodep->isSigPublic() + || nodep->hasUserInit() || nodep->isSigUserRWPublic() || (m_taskp && (m_taskp->dpiImport() || m_taskp->dpiExport()))) { - entryp->drivenWhole(); + entryp->drivenWhole(nodep); } - if (nodep->isWritable() || nodep->isSigPublic() || nodep->isSigUserRWPublic() - || nodep->isSigUserRdPublic() + if ((nodep->isWritable() && !funcInout) || nodep->isSigPublic() + || nodep->isSigUserRWPublic() || nodep->isSigUserRdPublic() || (m_taskp && (m_taskp->dpiImport() || m_taskp->dpiExport()))) { - entryp->usedWhole(); + entryp->usedWhole(nodep); } - if (nodep->valuep()) entryp->drivenWhole(); + if (nodep->valuep()) entryp->drivenWhole(nodep->valuep()); } // Discover variables used in bit definitions, etc iterateChildrenConst(nodep); @@ -420,6 +452,16 @@ class UndrivenVisitor final : public VNVisitorConst { << " (IEEE 1800-2023 13.5): " << nodep->prettyNameQ()); } } + + // If writeSummary is enabled, task/function definitions are treated as non-executed. + // Remember that anything driven here doesn't count toward MULTIDRIVEN. + bool ftaskDef = false; + if (m_taskp && !m_alwaysp && !m_inContAssign && !m_inInitialStatic && !m_inBBox + && !m_taskp->dpiExport()) { + AstVar* const retVarp = VN_CAST(m_taskp->fvarp(), Var); + if (!retVarp || nodep->varp() != retVarp) ftaskDef = true; + } + for (int usr = 1; usr < (m_alwaysCombp ? 3 : 2); ++usr) { UndrivenVarEntry* const entryp = getEntryp(nodep->varp(), usr); const bool fdrv = nodep->access().isWriteOrRW() @@ -432,7 +474,13 @@ class UndrivenVisitor final : public VNVisitorConst { if (entryp->isDrivenWhole() && !m_inBBox && !VN_IS(nodep, VarXRef) && !VN_IS(nodep->dtypep()->skipRefp(), UnpackArrayDType) && nodep->fileline() != entryp->getNodeFileLinep() && !entryp->isUnderGen() - && entryp->getNodep()) { + && (entryp->getNodep() || entryp->callNodep()) && !entryp->isFtaskDriven() + && !ftaskDef) { + + const AstNode* const otherWritep + = entryp->getNodep() ? static_cast(entryp->getNodep()) + : entryp->callNodep(); + if (m_alwaysCombp && (!entryp->isDrivenAlwaysCombWhole() || (m_alwaysCombp != entryp->getAlwCombp() @@ -443,23 +491,24 @@ class UndrivenVisitor final : public VNVisitorConst { << " (IEEE 1800-2023 9.2.2.2): " << nodep->prettyNameQ() << '\n' << nodep->warnOther() << '\n' << nodep->warnContextPrimary() << '\n' - << entryp->getNodep()->warnOther() - << "... Location of other write\n" - << entryp->getNodep()->warnContextSecondary()); + << otherWritep->warnOther() << "... Location of other write\n" + << otherWritep->warnContextSecondary()); } if (!m_alwaysCombp && entryp->isDrivenAlwaysCombWhole()) { - nodep->v3warn(MULTIDRIVEN, - "Variable also written to in always_comb" - << " (IEEE 1800-2023 9.2.2.2): " << nodep->prettyNameQ() - << '\n' - << nodep->warnOther() << '\n' - << nodep->warnContextPrimary() << '\n' - << entryp->getNodep()->warnOther() - << "... Location of always_comb write\n" - << entryp->getNodep()->warnContextSecondary()); + nodep->v3warn(MULTIDRIVEN, "Variable also written to in always_comb" + << " (IEEE 1800-2023 9.2.2.2): " + << nodep->prettyNameQ() << '\n' + << nodep->warnOther() << '\n' + << nodep->warnContextPrimary() << '\n' + << otherWritep->warnOther() + << "... Location of always_comb write\n" + << otherWritep->warnContextSecondary()); } } - entryp->drivenWhole(nodep, nodep->fileline()); + if (!m_inInitialSetup || nodep->varp()->hasUserInit()) { + // Else don't count default initialization as a driver to a net/variable + entryp->drivenWhole(nodep, nodep->fileline(), ftaskDef); + } if (m_alwaysCombp && entryp->isDrivenAlwaysCombWhole() && m_alwaysCombp != entryp->getAlwCombp() && m_alwaysCombp->fileline() == entryp->getAlwCombFileLinep()) @@ -472,13 +521,14 @@ class UndrivenVisitor final : public VNVisitorConst { if (m_alwaysp && m_inProcAssign && !entryp->procWritep()) entryp->procWritep(nodep); } - if (m_inBBox || nodep->access().isReadOrRW() - || fdrv - // Inouts have only isWrite set, as we don't have more - // information and operating on module boundary, treat as - // both read and writing - || m_inInoutOrRefPin) - entryp->usedWhole(); + if ((!m_inInitialSetup || nodep->varp()->hasUserInit()) + && (m_inBBox || nodep->access().isReadOrRW() + || fdrv + // Inouts have only isWrite set, as we don't have more + // information and operating on module boundary, treat as + // both read and writing + || m_inInoutOrRefPin)) + entryp->usedWhole(nodep); } } @@ -492,7 +542,12 @@ class UndrivenVisitor final : public VNVisitorConst { void visit(AstAssign* nodep) override { VL_RESTORER(m_inProcAssign); m_inProcAssign = true; - iterateChildrenConst(nodep); + { + VL_RESTORER(m_inInitialSetup); + m_inInitialSetup = false; + iterateConst(nodep->rhsp()); + } + iterateConst(nodep->lhsp()); } void visit(AstAssignDly* nodep) override { VL_RESTORER(m_inProcAssign); @@ -504,9 +559,26 @@ class UndrivenVisitor final : public VNVisitorConst { m_inContAssign = true; iterateChildrenConst(nodep); } + void visit(AstInitialAutomatic* nodep) override { + VL_RESTORER(m_inInitialSetup); + m_inInitialSetup = true; + iterateChildrenConst(nodep); + } + void visit(AstInitialAutomaticStmt* nodep) override { + VL_RESTORER(m_inInitialSetup); + m_inInitialSetup = true; + iterateChildrenConst(nodep); + } void visit(AstInitialStatic* nodep) override { VL_RESTORER(m_inInitialStatic); m_inInitialStatic = true; + VL_RESTORER(m_inInitialSetup); + m_inInitialSetup = true; + iterateChildrenConst(nodep); + } + void visit(AstInitialStaticStmt* nodep) override { + VL_RESTORER(m_inInitialSetup); + m_inInitialSetup = true; iterateChildrenConst(nodep); } void visit(AstAlways* nodep) override { @@ -523,10 +595,36 @@ class UndrivenVisitor final : public VNVisitorConst { iterateChildrenConst(nodep); if (nodep->keyword() == VAlwaysKwd::ALWAYS_COMB) UINFO(9, " Done " << nodep); } + void visit(AstNodeFTaskRef* nodep) override { VL_RESTORER(m_inFTaskRef); m_inFTaskRef = true; + iterateChildrenConst(nodep); + + if (!m_capturep) return; + + // If writeSummary is enabled, task/function definitions are treated as non-executed. + // Do not apply writeSummary at calls inside a task definition, or they will look like + // independent drivers (phantom MULTIDRIVEN). + const bool inExecutedContext + = !(m_taskp && !m_alwaysp && !m_inContAssign && !m_inInitialStatic && !m_inBBox + && !m_taskp->dpiExport()); + + if (!inExecutedContext) return; + + AstNodeFTask* const calleep = nodep->taskp(); + if (!calleep) return; + + const auto& vars = m_capturep->writeSummary(calleep); + for (AstVar* const varp : vars) { + for (int usr = 1; usr < (m_alwaysCombp ? 3 : 2); ++usr) { + UndrivenVarEntry* const entryp = getEntryp(varp, usr); + entryp->drivenViaCall(nodep); + if (m_alwaysCombp) + entryp->drivenAlwaysCombWhole(m_alwaysCombp, m_alwaysCombp->fileline()); + } + } } void visit(AstNodeFTask* nodep) override { @@ -556,7 +654,11 @@ class UndrivenVisitor final : public VNVisitorConst { public: // CONSTRUCTORS - explicit UndrivenVisitor(AstNetlist* nodep) { iterateConst(nodep); } + explicit UndrivenVisitor(AstNetlist* nodep, V3UndrivenCapture* capturep) + : m_capturep{capturep} { + iterateConst(nodep); + } + ~UndrivenVisitor() override { for (UndrivenVarEntry* ip : m_entryps[1]) ip->reportViolations(); for (int usr = 1; usr < 3; ++usr) { @@ -570,6 +672,9 @@ public: void V3Undriven::undrivenAll(AstNetlist* nodep) { UINFO(2, __FUNCTION__ << ":"); - { UndrivenVisitor{nodep}; } + + V3UndrivenCapture capture{nodep}; + UndrivenVisitor{nodep, &capture}; + if (v3Global.opt.stats()) V3Stats::statsStage("undriven"); } diff --git a/src/V3Undriven.h b/src/V3Undriven.h index 0b77cbb2a..8db29dc4d 100644 --- a/src/V3Undriven.h +++ b/src/V3Undriven.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3UndrivenCapture.cpp b/src/V3UndrivenCapture.cpp new file mode 100644 index 000000000..4d310cda2 --- /dev/null +++ b/src/V3UndrivenCapture.cpp @@ -0,0 +1,198 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Capture task/function write summaries for undriven checks +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2025 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#include "V3UndrivenCapture.h" + +#include "V3Error.h" +#include "V3Global.h" + +VL_DEFINE_DEBUG_FUNCTIONS; + +namespace { + +class CaptureUtil final { +public: + static std::string taskNameQ(const AstNodeFTask* taskp) { + if (!taskp) return ""; + return taskp->prettyNameQ(); + } +}; + +class CaptureVisitor final : public VNVisitorConst { + V3UndrivenCapture& m_cap; + const AstNodeFTask* m_curTaskp = nullptr; // Current task + bool m_inInitialSetup = false; // In InitialAutomatic*/InitialStatic* assignment LHS + +public: + explicit CaptureVisitor(V3UndrivenCapture& cap, AstNetlist* netlistp) + : m_cap{cap} { + iterateConst(netlistp); + } + +private: + // Visit a task/function definition and collect direct writes and direct callees. + void visit(AstNodeFTask* nodep) override { + VL_RESTORER(m_curTaskp); + m_curTaskp = nodep; + UINFO(9, "undriven capture enter ftask " << nodep << " " << nodep->prettyNameQ()); + m_cap.noteTask(nodep); + iterateAndNextConstNull(nodep->stmtsp()); + } + + void visit(AstInitialAutomaticStmt* nodep) override { + VL_RESTORER(m_inInitialSetup); + m_inInitialSetup = true; + iterateChildrenConst(nodep); + } + void visit(AstInitialStaticStmt* nodep) override { + VL_RESTORER(m_inInitialSetup); + m_inInitialSetup = true; + iterateChildrenConst(nodep); + } + void visit(AstAssign* nodep) override { + { + VL_RESTORER(m_inInitialSetup); + m_inInitialSetup = false; + iterateConst(nodep->rhsp()); + } + iterateConst(nodep->lhsp()); + } + + void visit(AstNodeVarRef* nodep) override { + if (m_curTaskp && nodep->access().isWriteOrRW() + && (nodep->varp()->hasUserInit() || !m_inInitialSetup)) { + UINFO(9, "undriven capture direct write in " << CaptureUtil::taskNameQ(m_curTaskp) + << " var=" << nodep->varp()->prettyNameQ() + << " at " << nodep->fileline()); + + m_cap.noteDirectWrite(m_curTaskp, nodep->varp()); + } + iterateChildrenConst(nodep); + } + + void visit(AstNodeFTaskRef* nodep) override { + // Record the call edge if resolved + if (m_curTaskp) { + if (const AstNodeFTask* const calleep = nodep->taskp()) { + UINFO(9, "undriven capture call edge " << CaptureUtil::taskNameQ( + m_curTaskp) << " -> " << CaptureUtil::taskNameQ(calleep)); + m_cap.noteCallEdge(m_curTaskp, calleep); + } + } + iterateChildrenConst(nodep); // still scan pins/args + } + + void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } +}; + +} // namespace + +V3UndrivenCapture::V3UndrivenCapture(AstNetlist* netlistp) { + gather(netlistp); + + // Compute summaries for all tasks + for (const auto& kv : m_info) (void)computeWriteSummary(kv.first); + + // Release the filter memory + for (auto& kv : m_info) { + kv.second.calleesSet.clear(); + kv.second.calleesSet.rehash(0); + kv.second.directWritesSet.clear(); + kv.second.directWritesSet.rehash(0); + } +} + +void V3UndrivenCapture::gather(AstNetlist* netlistp) { + // Walk netlist and populate m_info with direct writes + call edges + CaptureVisitor{*this, netlistp}; +} + +const std::vector& V3UndrivenCapture::writeSummary(const AstNodeFTask* taskp) { + // Ensure entry exists even if empty + (void)m_info[taskp]; + return computeWriteSummary(taskp); +} + +const std::vector& V3UndrivenCapture::computeWriteSummary(const AstNodeFTask* taskp) { + FTaskInfo& info = m_info[taskp]; + + if (info.state == State::DONE) { + UINFO(9, "undriven capture writeSummary cached size=" + << info.writeSummary.size() << " for " << CaptureUtil::taskNameQ(taskp)); + return info.writeSummary; + } + if (info.state == State::VISITING) { + UINFO(9, "undriven capture recursion detected at " + << CaptureUtil::taskNameQ(taskp) + << " returning directWrites size=" << info.directWrites.size()); + // Cycle detected. return directWrites only to guarantee termination. + if (info.writeSummary.empty()) info.writeSummary = info.directWrites; + return info.writeSummary; + } + + info.state = State::VISITING; + + info.writeSummary.clear(); + + // Prevent duplicates across all sources that can contribute to a write summary (direct writes + // and call chains) + std::unordered_set seen; + + // Simple lambda for filtering duplicates + auto addVar = [&](AstVar* v) { + if (seen.insert(v).second) info.writeSummary.push_back(v); + }; + + // Start with direct writes + for (AstVar* v : info.directWrites) addVar(v); + + // Add callee summaries + for (const AstNodeFTask* calleep : info.callees) { + if (m_info.find(calleep) == m_info.end()) continue; + const std::vector& sub = computeWriteSummary(calleep); + for (AstVar* v : sub) addVar(v); + } + + UINFO(9, "undriven capture writeSummary computed size=" << info.writeSummary.size() << " for " + << CaptureUtil::taskNameQ(taskp)); + + // We are done, so set the m_info state correctly and return the vector of variables + info.state = State::DONE; + return info.writeSummary; +} + +void V3UndrivenCapture::noteTask(const AstNodeFTask* taskp) { (void)m_info[taskp]; } + +void V3UndrivenCapture::noteDirectWrite(const AstNodeFTask* taskp, AstVar* varp) { + FTaskInfo& info = m_info[taskp]; + + // Exclude function return variable (not an externally visible side-effect) + AstVar* const retVarp = VN_CAST(taskp->fvarp(), Var); + if (retVarp && varp == retVarp) return; + + // Filter out duplicates. + if (info.directWritesSet.insert(varp).second) info.directWrites.push_back(varp); +} + +void V3UndrivenCapture::noteCallEdge(const AstNodeFTask* callerp, const AstNodeFTask* calleep) { + FTaskInfo& callerInfo = m_info[callerp]; + // Prevents duplicate entries from being appended, if calleep already exists then insert will + // return false, and then is not inserted into the callees vector. + if (callerInfo.calleesSet.insert(calleep).second) { callerInfo.callees.push_back(calleep); } + // Ensure callee entry exists, if already exists then this is a no-op. unordered_map<> so + // cheap. + (void)m_info[calleep]; +} diff --git a/src/V3UndrivenCapture.h b/src/V3UndrivenCapture.h new file mode 100644 index 000000000..2e6b4e07e --- /dev/null +++ b/src/V3UndrivenCapture.h @@ -0,0 +1,103 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Capture task/function write summaries for undriven checks +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2025 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +//************************************************************************* +// +// Capture task/function write summaries for multidriven checks. +// Per-task/function capture info keyed by resolved AstNodeFTask* +// identity (FTask = function or task). This is a 'graph' of +// tasks/functions. Each node has a list of direct callees and +// a list of variables written in the function body. There +// are methods to dedup after walking the tree. V3Undriven then uses +// the writeSummary for multidriven checks - i.e. it treats writes (side +// effects) inside subroutines as part of the caller's process. +//************************************************************************* + +#ifndef VERILATOR_V3UNDRIVENCAPTURE_H_ +#define VERILATOR_V3UNDRIVENCAPTURE_H_ + +#include "config_build.h" + +#include "V3Ast.h" + +#include +#include +#include + +class AstNetlist; + +class V3UndrivenCapture final { +public: + // DFS computation state for writeSummary propagation. + enum class State : uint8_t { + UNVISITED, // Write summary not computed yet + VISITING, // Currently computing on the call stack - used to detect cycles + DONE // Write summary computed + }; + + struct FTaskInfo final { + // Variables written directly in this task/function body (iteration order) + std::vector directWrites; + // Direct resolved callees from this task/function body (iteration order) + std::vector callees; + // 'Write through write' writeSummary for the given task/function. Meaning ultimately + // everything that this function/task writes to. + std::vector writeSummary; + // State for writeSummary computation. + State state = State::UNVISITED; + // Test if already recorded a callee. Used to 'filter' on insert + // versus sorting at the end. + std::unordered_set calleesSet; + // Test if already recorded a direct write. Used to 'filter' on + // insert versus sorting at the end. + std::unordered_set directWritesSet; + }; + +private: + // Per-task/function capture info keyed by resolved AstNodeFTask* identity (FTask = function or + // task). The 'graph' of tasks/functions. Each node has a list of direct callees and + // a list of variables written in the function body. There are methods to remove duplicates + // otherwise this could explode. + std::unordered_map m_info; + + // Collect direct writes and call edges for all tasks/functions. Run one time when + // UndrivenCapture is created. This runs the visitor over the tree. + void gather(AstNetlist* netlistp); + // Compute (and cache) 'write through write' writeSummary for the given task/function. + const std::vector& computeWriteSummary(const AstNodeFTask* taskp); + +public: + // Build capture database and precompute writeSummary for all discovered tasks/functions. + explicit V3UndrivenCapture(AstNetlist* netlistp); + + // Get write through write through write, etc (call chain) writeSummary for a task/function + // (creates empty entry if needed). This returns a vector of variables that a particular + // task/function writes to, including all variables written by functions called by this + // task/function, and so on. + const std::vector& writeSummary(const AstNodeFTask* taskp); + + // Used by the capture visitor to record information about tasks/functions and their statements + // and callees. noteTask() makes sure there is an entry for the given taskp. + void noteTask(const AstNodeFTask* taskp); + // Inside the body of taskp there is a write to variable varp + void noteDirectWrite(const AstNodeFTask* taskp, AstVar* varp); + // Inside the body of callerp there is a call to calleep, this is needed so we can create a + // summary that includes all variables written by functions called by this task/function, and + // so on. + void noteCallEdge(const AstNodeFTask* callerp, const AstNodeFTask* calleep); +}; + +#endif // VERILATOR_V3UNDRIVENCAPTURE_H_ diff --git a/src/V3UniqueNames.h b/src/V3UniqueNames.h index 55be682da..70226e846 100644 --- a/src/V3UniqueNames.h +++ b/src/V3UniqueNames.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2005-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2005-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index 24a9850b3..727e97840 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Unknown.h b/src/V3Unknown.h index bd1f1589d..5face0519 100644 --- a/src/V3Unknown.h +++ b/src/V3Unknown.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp index 5ccd40874..d8dd4221e 100644 --- a/src/V3Unroll.cpp +++ b/src/V3Unroll.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Unroll.h b/src/V3Unroll.h index bb09a3881..0b8e89c57 100644 --- a/src/V3Unroll.h +++ b/src/V3Unroll.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3UnrollGen.cpp b/src/V3UnrollGen.cpp index cc441c4cd..658eac07e 100644 --- a/src/V3UnrollGen.cpp +++ b/src/V3UnrollGen.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3VariableOrder.cpp b/src/V3VariableOrder.cpp index 2032c80bc..4b61b3f9b 100644 --- a/src/V3VariableOrder.cpp +++ b/src/V3VariableOrder.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3VariableOrder.h b/src/V3VariableOrder.h index 966b26f76..749377a33 100644 --- a/src/V3VariableOrder.h +++ b/src/V3VariableOrder.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Waiver.cpp b/src/V3Waiver.cpp index 86afadeb1..d81cf3194 100644 --- a/src/V3Waiver.cpp +++ b/src/V3Waiver.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2020-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Waiver.h b/src/V3Waiver.h index a3213fe12..93eba3036 100644 --- a/src/V3Waiver.h +++ b/src/V3Waiver.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 3343b5c70..de98e9de6 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -216,6 +216,8 @@ class WidthVisitor final : public VNVisitor { WidthVP* m_vup = nullptr; // Current node state bool m_underFork = false; // Visiting under a fork bool m_underSExpr = false; // Visiting under a sequence expression + bool m_underPackedArray = false; // Visiting under a AstPackArrayDType + bool m_hasNamedType = false; // Packed array is defined using named type AstNode* m_seqUnsupp = nullptr; // Property has unsupported node bool m_hasSExpr = false; // Property has a sequence expression const AstCell* m_cellp = nullptr; // Current cell for arrayed instantiations @@ -235,6 +237,8 @@ class WidthVisitor final : public VNVisitor { TableMap m_tableMap; // Created tables so can remove duplicates std::map m_queueDTypeIndexed; // Queues with given index type + std::map + m_containingClassp; // Containing class cache for containingClass() function std::unordered_set m_aliasedVars; // Variables referenced in alias static constexpr int ENUM_LOOKUP_BITS = 16; // Maximum # bits to make enum lookup table @@ -496,6 +500,7 @@ class WidthVisitor final : public VNVisitor { void visit(AstTime* nodep) override { nodep->dtypeSetUInt64(); } void visit(AstTimeD* nodep) override { nodep->dtypeSetDouble(); } void visit(AstTimePrecision* nodep) override { nodep->dtypeSetSigned32(); } + void visit(AstGetInitialRandomSeed* nodep) override { nodep->dtypeSetSigned32(); } void visit(AstTimeUnit* nodep) override { nodep->replaceWith( new AstConst{nodep->fileline(), AstConst::Signed32{}, nodep->timeunit().powerOfTen()}); @@ -1620,6 +1625,7 @@ class WidthVisitor final : public VNVisitor { nodep->dtypeSetSigned32(); // Used in int context if (VN_IS(nodep->backp(), IsUnbounded)) return; // Ok, leave if (VN_IS(nodep->backp(), BracketArrayDType)) return; // Ok, leave + if (VN_IS(nodep->backp(), InsideRange)) return; // Ok, leave if (const auto* const varp = VN_CAST(nodep->backp(), Var)) { if (varp->isParam()) return; // Ok, leave } @@ -2044,8 +2050,13 @@ class WidthVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(basicp), basicp); } } + if (!m_underPackedArray) m_hasNamedType = false; // Outermost dimension + VL_RESTORER(m_hasNamedType); + VL_RESTORER(m_underPackedArray); + if (VN_IS(nodep, PackArrayDType)) m_underPackedArray = true; // Iterate into subDTypep() to resolve that type and update pointer. nodep->refDTypep(iterateEditMoveDTypep(nodep, nodep->subDTypep())); + // Cleanup array size userIterateAndNext(nodep->rangep(), WidthVP{SELF, BOTH}.p()); nodep->dtypep(nodep); // The array itself, not subDtype @@ -2056,6 +2067,14 @@ class WidthVisitor final : public VNVisitor { } else { const int width = nodep->subDTypep()->width() * nodep->rangep()->elementsConst(); nodep->widthForce(width, width); + if (!VL_RESTORER_PREV(m_underPackedArray)) { // Outermost dimension + // IEEE 1800-2023 7.4.1 "Packed arrays" says + // If a packed array is declared as signed, + // then the array viewed as a single vector shall be signed. + if (!m_hasNamedType && nodep->basicp()->isSigned()) { + nodep->numeric(VSigning::fromBool(true)); + } + } } UINFO(4, "dtWidthed " << nodep); } @@ -2177,6 +2196,7 @@ class WidthVisitor final : public VNVisitor { UINFO(4, "dtWidthed " << nodep); } void visit(AstRefDType* nodep) override { + m_hasNamedType = m_underPackedArray; if (nodep->didWidthAndSet()) return; // This node is a dtype & not both PRELIMed+FINALed nodep->doingWidth(true); if (nodep->typeofp()) { // type(typeofp_expression) @@ -2497,10 +2517,8 @@ class WidthVisitor final : public VNVisitor { // So two steps, first do the calculation's width (max of the two widths) { const int calcWidth = std::max(width, underDtp->width()); - AstNodeDType* const calcDtp - = (underDtp->isFourstate() - ? nodep->findLogicDType(calcWidth, calcWidth, underDtp->numeric()) - : nodep->findBitDType(calcWidth, calcWidth, underDtp->numeric())); + AstNodeDType* const calcDtp = nodep->findBitOrLogicDType( + calcWidth, calcWidth, underDtp->numeric(), underDtp->isFourstate()); nodep->dtypep(calcDtp); // We ignore warnings as that is sort of the point of a cast iterateCheck(nodep, "Cast expr", underp, CONTEXT_DET, FINAL, calcDtp, EXTEND_EXP, @@ -2511,10 +2529,8 @@ class WidthVisitor final : public VNVisitor { // UINFOTREE(1, nodep, "", "CastSizeClc"); // Next step, make the proper output width { - AstNodeDType* const outDtp - = (underDtp->isFourstate() - ? nodep->findLogicDType(width, width, underDtp->numeric()) - : nodep->findBitDType(width, width, underDtp->numeric())); + AstNodeDType* const outDtp = nodep->findBitOrLogicDType( + width, width, underDtp->numeric(), underDtp->isFourstate()); nodep->dtypep(outDtp); // We ignore warnings as that is sort of the point of a cast widthCheckSized(nodep, "Cast expr", VN_AS(underp, NodeExpr), outDtp, EXTEND_EXP, @@ -2751,6 +2767,12 @@ class WidthVisitor final : public VNVisitor { << nodep->prettyNameQ() << " (IEEE 1800-2023 6.20.6)"); } + if (nodep->varp()->isClassMember() && !nodep->varp()->isFuncLocal() + && !nodep->varp()->lifetime().isStatic() && m_ftaskp && m_ftaskp->isStatic()) { + nodep->v3error("Cannot access non-static member variable " + << nodep->prettyNameQ() << " from a static method " + << m_ftaskp->prettyNameQ() << " without object (IEEE 1800-2023 8.10)"); + } nodep->didWidth(true); } @@ -3114,8 +3136,7 @@ class WidthVisitor final : public VNVisitor { } nodep->dtypeSetBit(); const VSigning numeric = nodep->exprp()->dtypep()->numeric(); - expDTypep = isFourstate ? nodep->findLogicDType(width, mwidth, numeric) - : nodep->findBitDType(width, mwidth, numeric); + expDTypep = nodep->findBitOrLogicDType(width, mwidth, numeric, isFourstate); } iterateCheck(nodep, "Inside expression", nodep->exprp(), CONTEXT_DET, FINAL, expDTypep, @@ -3134,8 +3155,15 @@ class WidthVisitor final : public VNVisitor { // executed so, there is no need for purification since they cannot generate sideeffects. if (!m_constraintp && !nodep->exprp()->isPure()) { FileLine* const fl = nodep->exprp()->fileline(); - AstVar* const varp = new AstVar{fl, VVarType::XTEMP, m_insideTempNames.get(nodep), - nodep->exprp()->dtypep()}; + // Ensure sized dtype for temp variable + AstNodeDType* const exprDtp = nodep->exprp()->dtypep(); + const int w = exprDtp->width(); + AstNodeDType* const tempDTypep + = exprDtp->widthSized() ? exprDtp + : nodep->findBitOrLogicDType(w, w, exprDtp->numeric(), + exprDtp->isFourstate()); + AstVar* const varp + = new AstVar{fl, VVarType::XTEMP, m_insideTempNames.get(nodep), tempDTypep}; exprp = new AstVarRef{fl, varp, VAccess::READ}; exprStmtp = new AstExprStmt{fl, new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, @@ -3221,6 +3249,10 @@ class WidthVisitor final : public VNVisitor { if (nodep->didWidthAndSet()) return; // This node is a dtype & not both PRELIMed+FINALed nodep->doingWidth(true); UINFO(5, " NODEUORS " << nodep); + // Check for tagged unions + if (const AstUnionDType* const unionp = VN_CAST(nodep, UnionDType)) { + if (unionp->isTagged()) { nodep->v3warn(E_UNSUPPORTED, "Unsupported: tagged union"); } + } // UINFOTREE(9, nodep, "", "class-in"); if (!nodep->packed() && v3Global.opt.structsPacked()) nodep->packed(true); userIterateChildren(nodep, nullptr); // First size all members @@ -3241,10 +3273,6 @@ class WidthVisitor final : public VNVisitor { itemp->v3error("Initial values not allowed in packed struct/union" " (IEEE 1800-2023 7.2.2)"); pushDeletep(itemp->valuep()->unlinkFrBack()); - } else if (itemp->valuep()) { - itemp->valuep()->v3warn(E_UNSUPPORTED, - "Unsupported: Initial values in struct/union members"); - pushDeletep(itemp->valuep()->unlinkFrBack()); } } const bool isHardPackedUnion @@ -3286,6 +3314,10 @@ class WidthVisitor final : public VNVisitor { void visit(AstThisRef* nodep) override { if (nodep->didWidthAndSet()) return; nodep->dtypep(iterateEditMoveDTypep(nodep, nodep->childDTypep())); + if (m_ftaskp && m_ftaskp->isStatic()) { + nodep->v3error("Cannot use 'this' in a static method " + << m_ftaskp->prettyNameQ() << " (IEEE 1800-2023 8.10-8.11)"); + } } void visit(AstClassRefDType* nodep) override { if (nodep->didWidthAndSet()) return; @@ -3390,8 +3422,8 @@ class WidthVisitor final : public VNVisitor { || VN_IS(fromDtp, BasicDType)) { // Method call on enum without following parenthesis, e.g. "ENUM.next" // Convert this into a method call, and let that visitor figure out what to do next - AstNode* const newp = new AstMethodCall{ - nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name(), nullptr}; + AstNode* const newp = new AstMethodCall{nodep->fileline(), + nodep->fromp()->unlinkFrBack(), nodep->name()}; nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); userIterate(newp, m_vup); @@ -3408,7 +3440,7 @@ class WidthVisitor final : public VNVisitor { bool memberSelClass(AstMemberSel* nodep, AstClassRefDType* adtypep) { if (nodep->name() == "rand_mode" || nodep->name() == "randomize") { AstMethodCall* const newp = new AstMethodCall{ - nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name(), nullptr}; + nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name()}; nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); visit(newp); @@ -3452,7 +3484,7 @@ class WidthVisitor final : public VNVisitor { } if (AstNodeFTask* ftaskp = VN_CAST(foundp, NodeFTask)) { AstMethodCall* newp = new AstMethodCall{ - nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name(), nullptr}; + nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name()}; newp->taskp(ftaskp); newp->dtypep(ftaskp->dtypep()); newp->classOrPackagep(classp); @@ -3579,7 +3611,7 @@ class WidthVisitor final : public VNVisitor { // Should check types the method requires, but at present we don't do much userIterate(nodep->fromp(), WidthVP{SELF, BOTH}.p()); // Args are checked within each particular method's decode - // Any AstWith is checked later when know types, in methodWithArgument + // Any AstWith is checked later when know types, in methodWithClause // Find the fromp dtype - should be a class UASSERT_OBJ(nodep->fromp() && nodep->fromp()->dtypep(), nodep, "Unsized expression"); AstNodeDType* const fromDtp = nodep->fromp()->dtypep()->skipRefToEnump(); @@ -3620,18 +3652,16 @@ class WidthVisitor final : public VNVisitor { nodep->dtypeSetVoid(); } } - AstWith* methodWithArgument(AstNodeFTaskRef* nodep, bool required, bool arbReturn, - AstNodeDType* returnDtp, AstNodeDType* indexDtp, - AstNodeDType* valueDtp) { + AstWith* methodWithClause(AstNodeFTaskRef* nodep, bool required, bool arbReturn, + AstNodeDType* returnDtp, AstNodeDType* indexDtp, + AstNodeDType* valueDtp) { UASSERT_OBJ(arbReturn || returnDtp, nodep, "Null return type"); - for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { - if (AstWith* const withp = VN_CAST(pinp, With)) { - withp->indexArgRefp()->dtypep(indexDtp); - withp->valueArgRefp()->dtypep(valueDtp); - userIterate(withp, WidthVP{returnDtp, BOTH}.p()); - withp->unlinkFrBack(); - return withp; - } + if (AstWith* const withp = nodep->withp()) { + withp->indexArgRefp()->dtypep(indexDtp); + withp->valueArgRefp()->dtypep(valueDtp); + userIterate(withp, WidthVP{returnDtp, BOTH}.p()); + withp->unlinkFrBack(); + return withp; } if (required) { nodep->v3error("'with' statement is required for ." << nodep->prettyName() @@ -3641,16 +3671,11 @@ class WidthVisitor final : public VNVisitor { } void methodOkArguments(AstNodeFTaskRef* nodep, int minArg, int maxArg) { int narg = 0; - for (AstNode* argp = nodep->pinsp(); argp; argp = argp->nextp()) { - if (VN_IS(argp, With)) { - argp->v3error("'with' not legal on this method"); - // Delete all arguments as nextp() otherwise dangling - VL_DO_DANGLING(pushDeletep(argp->unlinkFrBackWithNext()), argp); - break; - } - ++narg; - UASSERT_OBJ(VN_IS(argp, Arg), nodep, "Method arg without Arg type"); + if (AstWith* const withp = nodep->withp()) { + withp->v3error("'with' not legal on this method"); + VL_DO_DANGLING(pushDeletep(withp->unlinkFrBack()), withp); } + for (AstArg* argp = nodep->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) ++narg; const bool ok = (narg >= minArg) && (narg <= maxArg); if (!ok) { nodep->v3error("The " << narg << " arguments passed to ." << nodep->prettyName() @@ -3659,12 +3684,12 @@ class WidthVisitor final : public VNVisitor { << " arguments"); // Adjust to required argument counts, very bogus, but avoids core dump for (; narg < minArg; ++narg) { - nodep->addPinsp( + nodep->addArgsp( new AstArg{nodep->fileline(), "", new AstConst(nodep->fileline(), 0)}); } for (; narg > maxArg; --narg) { - AstNode* argp = nodep->pinsp(); - while (argp->nextp()) argp = argp->nextp(); + AstArg* argp = nodep->argsp(); + while (argp->nextp()) argp = VN_AS(argp->nextp(), Arg); argp->unlinkFrBack(); VL_DO_DANGLING(argp->deleteTree(), argp); } @@ -3672,10 +3697,10 @@ class WidthVisitor final : public VNVisitor { } AstNodeExpr* methodArg(AstMethodCall* nodep, int arg) { - AstNode* argp = nodep->pinsp(); - for (int narg = 0; narg < arg; ++narg) argp = argp->nextp(); + AstArg* argp = nodep->argsp(); + for (int narg = 0; narg < arg; ++narg) argp = VN_AS(argp->nextp(), Arg); UASSERT_OBJ(argp, nodep, "methodOkArguments() should have detected arg count error"); - return VN_AS(argp, Arg)->exprp(); + return argp->exprp(); } void methodCallEnum(AstMethodCall* nodep, AstEnumDType* adtypep) { @@ -3731,7 +3756,7 @@ class WidthVisitor final : public VNVisitor { nodep->v3fatalSrc("Bad case"); } - if (nodep->name() != "name" && nodep->pinsp()) { + if (nodep->name() != "name" && nodep->argsp()) { AstNodeExpr* stepp = methodArg(nodep, 0); VL_DO_DANGLING(V3Const::constifyParamsNoWarnEdit(stepp), stepp); stepp = methodArg(nodep, 0); @@ -3751,15 +3776,15 @@ class WidthVisitor final : public VNVisitor { AstMethodCall* const newp = new AstMethodCall{ nodep->fileline(), new AstMethodCall{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - "next", nullptr}, - "prev", nullptr}; + "next"}, + "prev"}; // No dtype assigned, we will recurse the new method and replace nodep->replaceWith(newp); VL_DO_DANGLING(nodep->deleteTree(), nodep); return; } else if (stepWidth != 1) { // Unroll of enumVar.next(k) to enumVar.next(1).next(k - 1) - pushDeletep(nodep->pinsp()->unlinkFrBack()); + pushDeletep(nodep->argsp()->unlinkFrBack()); AstMethodCall* const clonep = nodep->cloneTree(false); VN_AS(stepp, Const)->num().setLong(1); AstConst* const constp = new AstConst(nodep->fileline(), stepWidth - 1); @@ -3808,7 +3833,7 @@ class WidthVisitor final : public VNVisitor { } else if (nodep->name() == "delete") { // function void delete([input integer index]) methodOkArguments(nodep, 0, 1); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); - if (!nodep->pinsp()) { + if (!nodep->argsp()) { newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), VCMethod::ASSOC_CLEAR}; newp->dtypeSetVoid(); @@ -3827,12 +3852,13 @@ class WidthVisitor final : public VNVisitor { || nodep->name() == "sum" || nodep->name() == "product") { // All value return AstWith* const withp - = methodWithArgument(nodep, false, false, adtypep->subDTypep(), - adtypep->findStringDType(), adtypep->subDTypep()); + = methodWithClause(nodep, false, false, adtypep->subDTypep(), + adtypep->findStringDType(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod("r_" + nodep->name()), withp}; + VCMethod::arrayMethod("r_" + nodep->name())}; + newp->withp(withp); newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep()); if (!nodep->firstAbovep()) newp->dtypeSetVoid(); } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique") { @@ -3845,12 +3871,13 @@ class WidthVisitor final : public VNVisitor { } else if (nodep->name() == "find" || nodep->name() == "find_first" || nodep->name() == "find_last") { AstWith* const withp - = methodWithArgument(nodep, true, false, nodep->findBitDType(), - adtypep->findStringDType(), adtypep->subDTypep()); + = methodWithClause(nodep, true, false, nodep->findBitDType(), + adtypep->findStringDType(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod(nodep->name()), withp}; + VCMethod::arrayMethod(nodep->name())}; + newp->withp(withp); newp->dtypep(queueDTypeIndexedBy(adtypep->subDTypep())); if (!nodep->firstAbovep()) newp->dtypeSetVoid(); } else if (nodep->name() == "map") { @@ -3901,7 +3928,7 @@ class WidthVisitor final : public VNVisitor { } else if (nodep->name() == "delete") { // function void delete([input integer index]) methodOkArguments(nodep, 0, 1); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); - if (!nodep->pinsp()) { + if (!nodep->argsp()) { newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), VCMethod::ASSOC_CLEAR}; newp->dtypeSetVoid(); @@ -3920,22 +3947,24 @@ class WidthVisitor final : public VNVisitor { } else if (nodep->name() == "and" || nodep->name() == "or" || nodep->name() == "xor" || nodep->name() == "sum" || nodep->name() == "product") { // All value return - AstWith* const withp = methodWithArgument(nodep, false, false, adtypep->subDTypep(), - adtypep->keyDTypep(), adtypep->subDTypep()); + AstWith* const withp = methodWithClause(nodep, false, false, adtypep->subDTypep(), + adtypep->keyDTypep(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod("r_" + nodep->name()), withp}; + VCMethod::arrayMethod("r_" + nodep->name())}; + newp->withp(withp); newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep()); if (!nodep->firstAbovep()) newp->dtypeSetVoid(); } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique" || nodep->name() == "unique_index") { - AstWith* const withp = methodWithArgument( + AstWith* const withp = methodWithClause( nodep, false, true, nullptr, nodep->findUInt32DType(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod(nodep->name()), withp}; + VCMethod::arrayMethod(nodep->name())}; + newp->withp(withp); if (nodep->name() == "unique_index") { newp->dtypep(queueDTypeIndexedBy(adtypep->keyDTypep())); } else { @@ -3944,22 +3973,24 @@ class WidthVisitor final : public VNVisitor { if (!nodep->firstAbovep()) newp->dtypeSetVoid(); } else if (nodep->name() == "find" || nodep->name() == "find_first" || nodep->name() == "find_last") { - AstWith* const withp = methodWithArgument(nodep, true, false, nodep->findBitDType(), - adtypep->keyDTypep(), adtypep->subDTypep()); + AstWith* const withp = methodWithClause(nodep, true, false, nodep->findBitDType(), + adtypep->keyDTypep(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod(nodep->name()), withp}; + VCMethod::arrayMethod(nodep->name())}; + newp->withp(withp); newp->dtypep(queueDTypeIndexedBy(adtypep->subDTypep())); if (!nodep->firstAbovep()) newp->dtypeSetVoid(); } else if (nodep->name() == "find_index" || nodep->name() == "find_first_index" || nodep->name() == "find_last_index") { - AstWith* const withp = methodWithArgument(nodep, true, false, nodep->findBitDType(), - adtypep->keyDTypep(), adtypep->subDTypep()); + AstWith* const withp = methodWithClause(nodep, true, false, nodep->findBitDType(), + adtypep->keyDTypep(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod(nodep->name()), withp}; + VCMethod::arrayMethod(nodep->name())}; + newp->withp(withp); newp->dtypep(queueDTypeIndexedBy(adtypep->keyDTypep())); if (!nodep->firstAbovep()) newp->dtypeSetVoid(); } else if (nodep->name() == "map") { @@ -3978,19 +4009,19 @@ class WidthVisitor final : public VNVisitor { } } AstNodeExpr* methodCallAssocIndexExpr(AstMethodCall* nodep, AstAssocArrayDType* adtypep) { - AstNode* const index_exprp = VN_CAST(nodep->pinsp(), Arg)->exprp(); + AstNode* const index_exprp = nodep->argsp()->exprp(); iterateCheck(nodep, "index", index_exprp, CONTEXT_DET, FINAL, adtypep->keyDTypep(), EXTEND_EXP); VL_DANGLING(index_exprp); // May have been edited - return VN_AS(nodep->pinsp(), Arg)->exprp(); + return nodep->argsp()->exprp(); } AstNodeExpr* methodCallWildcardIndexExpr(AstMethodCall* nodep, AstWildcardArrayDType* adtypep) { - AstNode* const index_exprp = VN_CAST(nodep->pinsp(), Arg)->exprp(); + AstNode* const index_exprp = nodep->argsp()->exprp(); iterateCheck(nodep, "index", index_exprp, CONTEXT_DET, FINAL, adtypep->findStringDType(), EXTEND_EXP); VL_DANGLING(index_exprp); // May have been edited - return VN_AS(nodep->pinsp(), Arg)->exprp(); + return nodep->argsp()->exprp(); } void methodCallLValueRecurse(AstMethodCall* nodep, AstNode* childp, const VAccess& access) { if (AstCMethodHard* const ichildp = VN_CAST(childp, CMethodHard)) { @@ -4048,22 +4079,24 @@ class WidthVisitor final : public VNVisitor { || nodep->name() == "rsort") { AstWith* withp = nullptr; if (nodep->name() == "sort" || nodep->name() == "rsort") { - withp = methodWithArgument(nodep, false, true, nullptr, nodep->findUInt32DType(), - adtypep->subDTypep()); + withp = methodWithClause(nodep, false, true, nullptr, nodep->findUInt32DType(), + adtypep->subDTypep()); } methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod(nodep->name()), withp}; + VCMethod::arrayMethod(nodep->name())}; + newp->withp(withp); newp->dtypeSetVoid(); } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique" || nodep->name() == "unique_index") { - AstWith* const withp = methodWithArgument( + AstWith* const withp = methodWithClause( nodep, false, true, nullptr, nodep->findUInt32DType(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod(nodep->name()), withp}; + VCMethod::arrayMethod(nodep->name())}; + newp->withp(withp); if (nodep->name() == "unique_index") { newp->dtypep(newp->findQueueIndexDType()); } else { @@ -4073,23 +4106,25 @@ class WidthVisitor final : public VNVisitor { } else if (nodep->name() == "find" || nodep->name() == "find_first" || nodep->name() == "find_last" || nodep->name() == "find_index") { AstWith* const withp - = methodWithArgument(nodep, true, false, nodep->findBitDType(), - nodep->findUInt32DType(), adtypep->subDTypep()); + = methodWithClause(nodep, true, false, nodep->findBitDType(), + nodep->findUInt32DType(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod(nodep->name()), withp}; + VCMethod::arrayMethod(nodep->name())}; + newp->withp(withp); newp->dtypep(queueDTypeIndexedBy(adtypep->subDTypep())); if (!nodep->firstAbovep()) newp->dtypeSetVoid(); } else if (nodep->name() == "find_index" || nodep->name() == "find_first_index" || nodep->name() == "find_last_index") { AstWith* const withp - = methodWithArgument(nodep, true, false, nodep->findBitDType(), - nodep->findUInt32DType(), adtypep->subDTypep()); + = methodWithClause(nodep, true, false, nodep->findBitDType(), + nodep->findUInt32DType(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod(nodep->name()), withp}; + VCMethod::arrayMethod(nodep->name())}; + newp->withp(withp); newp->dtypep(newp->findQueueIndexDType()); if (!nodep->firstAbovep()) newp->dtypeSetVoid(); } else if (nodep->name() == "map") { @@ -4129,12 +4164,13 @@ class WidthVisitor final : public VNVisitor { || nodep->name() == "sum" || nodep->name() == "product") { // All value return AstWith* const withp - = methodWithArgument(nodep, false, false, adtypep->subDTypep(), - nodep->findUInt32DType(), adtypep->subDTypep()); + = methodWithClause(nodep, false, false, adtypep->subDTypep(), + nodep->findUInt32DType(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod("r_" + nodep->name()), withp}; + VCMethod::arrayMethod("r_" + nodep->name())}; + newp->withp(withp); newp->dtypeFrom(adtypep->subDTypep()); if (!nodep->firstAbovep()) newp->dtypeSetVoid(); } else if ((newp = methodCallArray(nodep, adtypep))) { @@ -4175,7 +4211,7 @@ class WidthVisitor final : public VNVisitor { } else if (nodep->name() == "delete") { // function void delete([input integer index]) methodOkArguments(nodep, 0, 1); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); - if (!nodep->pinsp()) { + if (!nodep->argsp()) { newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), VCMethod::DYN_CLEAR}; newp->dtypeSetVoid(); @@ -4198,7 +4234,7 @@ class WidthVisitor final : public VNVisitor { iterateCheckSigned32(nodep, "index", methodArg(nodep, 0), BOTH); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); AstNodeExpr* const index_exprp = methodCallQueueIndexExpr(nodep); - AstArg* const argp = VN_AS(nodep->pinsp()->nextp(), Arg); + AstArg* const argp = VN_AS(nodep->argsp()->nextp(), Arg); iterateCheckTyped(nodep, "insert value", argp->exprp(), adtypep->subDTypep(), BOTH); if (index_exprp->isZero()) { // insert(0, ...) is a push_front newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), @@ -4221,7 +4257,7 @@ class WidthVisitor final : public VNVisitor { methodOkArguments(nodep, 1, 1); iterateCheckTyped(nodep, "argument", methodArg(nodep, 0), adtypep->subDTypep(), BOTH); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); - AstArg* const argp = VN_AS(nodep->pinsp(), Arg); + AstArg* const argp = nodep->argsp(); iterateCheckTyped(nodep, "push value", argp->exprp(), adtypep->subDTypep(), BOTH); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), VCMethod::arrayMethod(nodep->name()), @@ -4230,12 +4266,13 @@ class WidthVisitor final : public VNVisitor { } else if (nodep->name() == "and" || nodep->name() == "or" || nodep->name() == "xor" || nodep->name() == "sum" || nodep->name() == "product") { AstWith* const withp - = methodWithArgument(nodep, false, false, adtypep->subDTypep(), - nodep->findUInt32DType(), adtypep->subDTypep()); + = methodWithClause(nodep, false, false, adtypep->subDTypep(), + nodep->findUInt32DType(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod("r_" + nodep->name()), withp}; + VCMethod::arrayMethod("r_" + nodep->name())}; + newp->withp(withp); newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep()); if (!nodep->firstAbovep()) newp->dtypeSetVoid(); } else if ((newp = methodCallArray(nodep, adtypep))) { @@ -4252,10 +4289,10 @@ class WidthVisitor final : public VNVisitor { } } AstNodeExpr* methodCallQueueIndexExpr(AstMethodCall* nodep) { - AstNode* const index_exprp = VN_AS(nodep->pinsp(), Arg)->exprp(); + AstNode* const index_exprp = nodep->argsp()->exprp(); iterateCheckSigned32(nodep, "index", index_exprp, BOTH); VL_DANGLING(index_exprp); // May have been edited - return VN_AS(nodep->pinsp(), Arg)->exprp(); + return nodep->argsp()->exprp(); } void methodCallWarnTiming(AstNodeFTaskRef* const nodep, const std::string& className) { if (v3Global.opt.timing().isSetFalse()) { @@ -4275,8 +4312,8 @@ class WidthVisitor final : public VNVisitor { UINFO(5, __FUNCTION__ << "AstNodeFTask" << nodep); userIterate(ftaskp, nullptr); if (ftaskp->isStatic()) { - AstNodeExpr* argsp = nullptr; - if (nodep->pinsp()) argsp = nodep->pinsp()->unlinkFrBackWithNext(); + AstArg* const argsp = nodep->argsp(); + if (argsp) argsp->unlinkFrBackWithNext(); AstNodeFTaskRef* newp = nullptr; if (VN_IS(ftaskp, Task)) { newp = new AstTaskRef{nodep->fileline(), VN_AS(ftaskp, Task), argsp}; @@ -4301,10 +4338,8 @@ class WidthVisitor final : public VNVisitor { void handleRandomizeArgs(AstNodeFTaskRef* const nodep, AstClass* const classp) { bool hasNonNullArgs = false; AstConst* nullp = nullptr; - for (AstNode *pinp = nodep->pinsp(), *nextp = nullptr; pinp; pinp = nextp) { - nextp = pinp->nextp(); - AstArg* const argp = VN_CAST(pinp, Arg); - if (!argp) continue; + for (AstArg *argp = nodep->argsp(), *nextp; argp; argp = nextp) { + nextp = VN_AS(argp->nextp(), Arg); AstVar* randVarp = nullptr; AstNodeExpr* exprp = argp->exprp(); if (AstConst* const constp = VN_CAST(exprp, Const)) { @@ -4378,20 +4413,18 @@ class WidthVisitor final : public VNVisitor { if (nodep->name() == "randomize") { VL_RESTORER(m_randomizeFromp); m_randomizeFromp = nodep->fromp(); - withp = methodWithArgument(nodep, false, false, adtypep->findVoidDType(), - adtypep->findBitDType(), adtypep); - for (AstNode* pinp = nodep->pinsp(); pinp; pinp = pinp->nextp()) { - if (AstArg* const argp = VN_CAST(pinp, Arg)) { - if (argp->exprp()) userIterate(argp->exprp(), WidthVP{SELF, BOTH}.p()); - } + withp = methodWithClause(nodep, false, false, adtypep->findVoidDType(), + adtypep->findBitDType(), adtypep); + for (AstArg* argp = nodep->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { + if (argp->exprp()) userIterate(argp->exprp(), WidthVP{SELF, BOTH}.p()); } - methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); + methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); V3Randomize::newRandomizeFunc(m_memberMap, first_classp); handleRandomizeArgs(nodep, first_classp); } else if (nodep->name() == "srandom") { methodOkArguments(nodep, 1, 1); iterateCheckSigned32(nodep, "argument", methodArg(nodep, 0), BOTH); - methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); + methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); V3Randomize::newSRandomFunc(m_memberMap, first_classp); } UASSERT_OBJ(first_classp, nodep, "Unlinked"); @@ -4418,8 +4451,8 @@ class WidthVisitor final : public VNVisitor { = VN_CAST(m_memberMap.findMember(classp, nodep->name()), NodeFTask)) { userIterate(ftaskp, nullptr); if (ftaskp->isStatic()) { - AstNodeExpr* argsp = nullptr; - if (nodep->pinsp()) argsp = nodep->pinsp()->unlinkFrBackWithNext(); + AstArg* const argsp = nodep->argsp(); + if (argsp) argsp->unlinkFrBackWithNext(); AstNodeFTaskRef* newp = nullptr; // We use m_vup to determine task or function, so that later error checks // for funcref->task and taskref->func will pick up properly @@ -4444,7 +4477,7 @@ class WidthVisitor final : public VNVisitor { } nodep->dtypeSetVoid(); } - if (withp) nodep->addPinsp(withp); + if (withp) nodep->withp(withp); processFTaskRefArgs(nodep); } return; @@ -4462,9 +4495,9 @@ class WidthVisitor final : public VNVisitor { return; } else if (nodep->name() == "set_randstate") { methodOkArguments(nodep, 1, 1); - AstNodeExpr* const expr1p = VN_AS(nodep->pinsp(), Arg)->exprp(); // May edit + AstNodeExpr* const expr1p = nodep->argsp()->exprp(); // May edit iterateCheckString(nodep, "LHS", expr1p, BOTH); - AstNodeExpr* const exprp = VN_AS(nodep->pinsp(), Arg)->exprp(); + AstNodeExpr* const exprp = nodep->argsp()->exprp(); first_classp->baseMostClassp()->needRNG(true); v3Global.useRandomizeMethods(true); AstCMethodHard* const newp @@ -4502,7 +4535,7 @@ class WidthVisitor final : public VNVisitor { if (nodep->name() == "constraint_mode") { // IEEE 1800-2023 18.9 methodOkArguments(nodep, 0, 1); - if (nodep->pinsp()) { + if (nodep->argsp()) { iterateCheckBool(nodep, "argument", methodArg(nodep, 0), BOTH); nodep->dtypep(nodep->findBasicDType(VBasicDTypeKwd::INT)); } else { @@ -4518,7 +4551,7 @@ class WidthVisitor final : public VNVisitor { void methodCallRandMode(AstMethodCall* nodep) { methodOkArguments(nodep, 0, 1); // IEEE 1800-2023 18.8 - if (nodep->pinsp()) { + if (nodep->argsp()) { iterateCheckBool(nodep, "argument", methodArg(nodep, 0), BOTH); nodep->dtypeSetVoid(); } else { @@ -4551,14 +4584,15 @@ class WidthVisitor final : public VNVisitor { if (methodId) { AstWith* const withp - = methodWithArgument(nodep, false, false, adtypep->subDTypep(), - nodep->findUInt32DType(), adtypep->subDTypep()); + = methodWithClause(nodep, false, false, adtypep->subDTypep(), + nodep->findUInt32DType(), adtypep->subDTypep()); methodOkArguments(nodep, 0, 0); if (withp) { methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); AstCMethodHard* const newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), - VCMethod::arrayMethod("r_" + nodep->name()), withp}; + VCMethod::arrayMethod("r_" + nodep->name())}; + newp->withp(withp); newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep()); if (!nodep->firstAbovep()) newp->dtypeSetVoid(); newp->protect(false); @@ -4657,7 +4691,7 @@ class WidthVisitor final : public VNVisitor { const bool ignoreCase = nodep->name()[0] == 'i'; methodOkArguments(nodep, 1, 1); iterateCheckString(nodep, "argument", methodArg(nodep, 0), BOTH); - AstArg* const argp = VN_AS(nodep->pinsp(), Arg); + AstArg* const argp = nodep->argsp(); AstNodeExpr* const lhs = nodep->fromp()->unlinkFrBack(); AstNodeExpr* const rhs = argp->exprp()->unlinkFrBack(); AstNode* const newp = new AstCompareNN{nodep->fileline(), lhs, rhs, ignoreCase}; @@ -4667,7 +4701,7 @@ class WidthVisitor final : public VNVisitor { methodOkArguments(nodep, 2, 2); iterateCheckSigned32(nodep, "argument 0", methodArg(nodep, 0), BOTH); iterateCheckSigned8(nodep, "argument 1", methodArg(nodep, 1), BOTH); - AstArg* const arg0p = VN_AS(nodep->pinsp(), Arg); + AstArg* const arg0p = nodep->argsp(); AstArg* const arg1p = VN_AS(arg0p->nextp(), Arg); AstNodeVarRef* const fromp = VN_AS(nodep->fromp()->unlinkFrBack(), VarRef); AstNodeExpr* const rhsp = arg0p->exprp()->unlinkFrBack(); @@ -4682,7 +4716,7 @@ class WidthVisitor final : public VNVisitor { } else if (nodep->name() == "getc") { methodOkArguments(nodep, 1, 1); iterateCheckSigned32(nodep, "argument", methodArg(nodep, 0), BOTH); - AstArg* const arg0p = VN_AS(nodep->pinsp(), Arg); + AstArg* const arg0p = nodep->argsp(); AstNodeExpr* const lhsp = nodep->fromp()->unlinkFrBack(); AstNodeExpr* const rhsp = arg0p->exprp()->unlinkFrBack(); AstNodeExpr* const newp = new AstGetcN{nodep->fileline(), lhsp, rhsp}; @@ -4692,7 +4726,7 @@ class WidthVisitor final : public VNVisitor { methodOkArguments(nodep, 2, 2); iterateCheckSigned32(nodep, "argument 0", methodArg(nodep, 0), BOTH); iterateCheckSigned32(nodep, "argument 1", methodArg(nodep, 1), BOTH); - AstArg* const arg0p = VN_AS(nodep->pinsp(), Arg); + AstArg* const arg0p = nodep->argsp(); AstArg* const arg1p = VN_AS(arg0p->nextp(), Arg); AstNodeExpr* const lhsp = nodep->fromp()->unlinkFrBack(); AstNodeExpr* const rhsp = arg0p->exprp()->unlinkFrBack(); @@ -4836,6 +4870,37 @@ class WidthVisitor final : public VNVisitor { } } + void visit(AstTaggedExpr* nodep) override { + // Tagged union expressions are currently unsupported + nodep->v3warn(E_UNSUPPORTED, "Unsupported: tagged union"); + // Set a placeholder type to allow further processing + nodep->dtypeSetBit(); + userIterateChildren(nodep, m_vup); + } + void visit(AstTaggedPattern* nodep) override { + // Tagged patterns are currently unsupported + nodep->v3warn(E_UNSUPPORTED, "Unsupported: tagged pattern"); + nodep->dtypeSetBit(); + userIterateChildren(nodep, m_vup); + } + void visit(AstPatternVar* nodep) override { + // Pattern variable bindings are currently unsupported + nodep->v3warn(E_UNSUPPORTED, "Unsupported: pattern variable"); + nodep->dtypeSetBit(); + } + void visit(AstPatternStar* nodep) override { + // Pattern wildcards are currently unsupported + nodep->v3warn(E_UNSUPPORTED, "Unsupported: pattern wildcard"); + nodep->dtypeSetBit(); + } + void visit(AstMatches* nodep) override { + // Matches operator is currently unsupported + nodep->v3warn(E_UNSUPPORTED, "Unsupported: matches operator"); + // Matches returns a boolean + nodep->dtypeSetBit(); + userIterateChildren(nodep, m_vup); + } + void visit(AstPattern* nodep) override { if (nodep->didWidthAndSet()) return; UINFO(9, "PATTERN " << nodep); @@ -4850,6 +4915,11 @@ class WidthVisitor final : public VNVisitor { nodep->v3warn(E_UNSUPPORTED, "Unsupported/Illegal: Assignment pattern" " member not underneath a supported construct: " << nodep->backp()->prettyTypeName()); + + if (nodep->backp() && (VN_IS(nodep->backp(), Eq) || VN_IS(nodep->backp(), Neq))) + return; + nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}}); + VL_DO_DANGLING(pushDeletep(nodep), nodep); return; } { @@ -5032,7 +5102,7 @@ class WidthVisitor final : public VNVisitor { AstNodeExpr* const valuep = patternMemberValueIterate(patp); AstConsPackMember* const cpmp = new AstConsPackMember{patp->fileline(), memp, valuep}; - membersp = membersp ? membersp->addNext(cpmp) : cpmp; + membersp = AstNode::addNextNull(membersp, cpmp); } newp = new AstConsPackUOrStruct{nodep->fileline(), vdtypep, membersp}; } @@ -5077,6 +5147,11 @@ class WidthVisitor final : public VNVisitor { // default_value for any unmatched member yet return defaultp->cloneTree(false); } + if (memp->valuep()) { + return new AstPatMember{nodep->fileline(), + VN_AS(memp->valuep()->cloneTree(false), NodeExpr), + new AstText{nodep->fileline(), memp->name()}, nullptr}; + } if (!VN_IS(memp_vdtypep, UnionDType)) { nodep->v3error("Assignment pattern missed initializing elements: " << memp->virtRefDTypep()->prettyDTypeNameQ() << " " @@ -5168,7 +5243,7 @@ class WidthVisitor final : public VNVisitor { // UINFOTREE(9, newp, "", "apat-out"); } void patternAssoc(AstPattern* nodep, AstAssocArrayDType* arrayDtp, AstPatMember* defaultp) { - AstNode* defaultValuep = nullptr; + AstNodeExpr* defaultValuep = nullptr; if (defaultp) { defaultp->dtypep(arrayDtp->subDTypep()); defaultValuep = patternMemberValueIterate(defaultp); @@ -5200,12 +5275,12 @@ class WidthVisitor final : public VNVisitor { } void patternWildcard(AstPattern* nodep, AstWildcardArrayDType* arrayDtp, AstPatMember* defaultp) { - AstNode* defaultValuep = nullptr; + AstNodeExpr* defaultValuep = nullptr; if (defaultp) { defaultp->dtypep(arrayDtp->subDTypep()); defaultValuep = patternMemberValueIterate(defaultp); } - AstNode* newp = new AstConsWildcard{nodep->fileline(), defaultValuep}; + AstNodeExpr* newp = new AstConsWildcard{nodep->fileline(), defaultValuep}; newp->dtypeFrom(arrayDtp); for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp; patp = VN_AS(patp->nextp(), PatMember)) { @@ -5221,7 +5296,7 @@ class WidthVisitor final : public VNVisitor { // UINFOTREE(9, newp, "", "apat-out"); } void patternDynArray(AstPattern* nodep, AstDynArrayDType* arrayp, AstPatMember* defaultp) { - AstNode* newp = new AstConsDynArray{nodep->fileline()}; + AstNodeExpr* newp = new AstConsDynArray{nodep->fileline()}; newp->dtypeFrom(arrayp); for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp; patp = VN_AS(patp->nextp(), PatMember)) { @@ -5239,7 +5314,7 @@ class WidthVisitor final : public VNVisitor { // UINFOTREE(9, newp, "", "apat-out"); } void patternQueue(AstPattern* nodep, AstQueueDType* arrayp, AstPatMember* defaultp) { - AstNode* newp = new AstConsQueue{nodep->fileline()}; + AstNodeExpr* newp = new AstConsQueue{nodep->fileline()}; newp->dtypeFrom(arrayp); for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp; patp = VN_AS(patp->nextp(), PatMember)) { @@ -5325,6 +5400,7 @@ class WidthVisitor final : public VNVisitor { static void checkEventAssignment(const AstNodeAssign* const asgnp) { string unsupEvtAsgn; if (!usesDynamicScheduler(asgnp->lhsp())) unsupEvtAsgn = "to"; + if (VN_IS(asgnp->rhsp(), CReset)) return; if (asgnp->rhsp()->dtypep()->isEvent() && !usesDynamicScheduler(asgnp->rhsp())) { unsupEvtAsgn += (unsupEvtAsgn.empty() ? "from" : " and from"); } @@ -5415,15 +5491,33 @@ class WidthVisitor final : public VNVisitor { newp->dtypeFrom(nodep); nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); - } else if (nodep->disablep()) { - nodep->disablep()->v3warn(E_UNSUPPORTED, - "Unsupported: Disable iff with sequence expression"); - VL_DO_DANGLING(pushDeletep(nodep->disablep()->unlinkFrBack()), nodep); } } } } + bool firstNewStatementOkRecurse(AstNode* nodep) { + if (AstVar* const varp = VN_CAST(nodep, Var)) { + if (!varp->valuep() || VN_CAST(varp->valuep(), Const) || varp->isIO()) return true; + } + if (AstAssign* const aitemp = VN_CAST(nodep, Assign)) { + if (VN_IS(aitemp->rhsp(), Const) || VN_IS(aitemp->rhsp(), CReset)) return true; + } + if (AstInitialStaticStmt* const aitemp = VN_CAST(nodep, InitialStaticStmt)) { + for (AstNode* stmtp = aitemp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + if (!firstNewStatementOkRecurse(stmtp)) return false; + } + return true; + } + if (AstInitialAutomaticStmt* const aitemp = VN_CAST(nodep, InitialAutomaticStmt)) { + for (AstNode* stmtp = aitemp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + if (!firstNewStatementOkRecurse(stmtp)) return false; + } + return true; + } + return false; + } + //-------------------- // Top levels @@ -5589,15 +5683,14 @@ class WidthVisitor final : public VNVisitor { void visit(AstNodeForeach* nodep) override { if (nodep->didWidth()) return; nodep->didWidth(true); - const AstSelLoopVars* const loopsp = VN_CAST(nodep->arrayp(), SelLoopVars); - UASSERT_OBJ(loopsp, nodep, "No loop variables under foreach"); + const AstForeachHeader* const headerp = nodep->headerp(); // UINFOTREE(1, nodep, "", "foreach-old"); - userIterateAndNext(loopsp->fromp(), WidthVP{SELF, BOTH}.p()); - AstNodeExpr* const fromp = loopsp->fromp(); + userIterateAndNext(headerp->fromp(), WidthVP{SELF, BOTH}.p()); + AstNodeExpr* const fromp = headerp->fromp(); UASSERT_OBJ(fromp->dtypep(), fromp, "Missing data type"); AstNodeDType* fromDtp = fromp->dtypep()->skipRefp(); // Major dimension first - for (AstNode *argsp = loopsp->elementsp(), *next_argsp; argsp; argsp = next_argsp) { + for (AstNode *argsp = headerp->elementsp(), *next_argsp; argsp; argsp = next_argsp) { next_argsp = argsp->nextp(); const bool empty = VN_IS(argsp, Empty); AstVar* const varp = VN_CAST(argsp, Var); @@ -5635,7 +5728,7 @@ class WidthVisitor final : public VNVisitor { fromDtp = fromDtp->subDTypep(); } // The parser validates we don't have "foreach (array[,,,])" - AstNode* const bodyp = nodep->stmtsp(); + AstNode* const bodyp = nodep->bodyp(); userIterateAndNext(bodyp, nullptr); if (AstForeach* const loopp = VN_CAST(nodep, Foreach)) { VL_DO_DANGLING2(V3Begin::convertToWhile(loopp), loopp, nodep); @@ -5702,6 +5795,34 @@ class WidthVisitor final : public VNVisitor { } } + // IEEE 1800-2023 7.6: For unpacked arrays to be assignment compatible, + // the element types shall be equivalent (IEEE 1800-2023 6.22.2). + // Check specifically for 2-state vs 4-state mismatch for unpacked array + // to unpacked array assignments, as this is a common IEEE compliance issue. + // Note: Streaming operators and string literals have implicit conversion rules. + if (nodep->rhsp()->dtypep()) { // May be null on earlier errors + const AstNodeDType* const lhsDtp = lhsDTypep->skipRefp(); + const AstNodeDType* const rhsDtp = nodep->rhsp()->dtypep()->skipRefp(); + // Only check unpacked array to unpacked array assignments + const bool lhsIsUnpackArray + = VN_IS(lhsDtp, UnpackArrayDType) || VN_IS(lhsDtp, DynArrayDType) + || VN_IS(lhsDtp, QueueDType) || VN_IS(lhsDtp, AssocArrayDType); + const bool rhsIsUnpackArray + = VN_IS(rhsDtp, UnpackArrayDType) || VN_IS(rhsDtp, DynArrayDType) + || VN_IS(rhsDtp, QueueDType) || VN_IS(rhsDtp, AssocArrayDType); + if (lhsIsUnpackArray && rhsIsUnpackArray) { + if (lhsDtp->isFourstate() != rhsDtp->isFourstate()) { + nodep->v3error( + "Assignment between 2-state and 4-state types requires " + "equivalent element types (IEEE 1800-2023 6.22.2, 7.6)\n" + << nodep->warnMore() << "... LHS type: " << lhsDtp->prettyDTypeNameQ() + << (lhsDtp->isFourstate() ? " (4-state)" : " (2-state)") << "\n" + << nodep->warnMore() << "... RHS type: " << rhsDtp->prettyDTypeNameQ() + << (rhsDtp->isFourstate() ? " (4-state)" : " (2-state)")); + } + } + } + iterateCheckAssign(nodep, "Assign RHS", nodep->rhsp(), FINAL, lhsDTypep); // UINFOTREE(1, nodep, "", "AssignOut"); } @@ -5736,8 +5857,8 @@ class WidthVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); return; } - AstMethodCall* const newp = new AstMethodCall{ - nodep->fileline(), nodep->lhsp()->unlinkFrBack(), "delete", nullptr}; + AstMethodCall* const newp + = new AstMethodCall{nodep->fileline(), nodep->lhsp()->unlinkFrBack(), "delete"}; newp->dtypeSetVoid(); nodep->replaceWith(newp->makeStmt()); VL_DO_DANGLING(pushDeletep(nodep), nodep); @@ -5949,6 +6070,10 @@ class WidthVisitor final : public VNVisitor { nodep->text(newFormat); UINFO(9, " Display out " << nodep->text()); } + void visit(AstCReset* nodep) override { + assertAtExpr(nodep); + nodep->dtypeFrom(m_vup->dtypep()); + } void visit(AstCReturn* nodep) override { nodep->v3fatalSrc("Should not exist yet"); } void visit(AstConstraintRef* nodep) override { userIterateChildren(nodep, nullptr); } void visit(AstDisplay* nodep) override { @@ -6407,13 +6532,7 @@ class WidthVisitor final : public VNVisitor { } continue; } - if (AstVar* const varp = VN_CAST(itemp, Var)) { - if (!varp->valuep() || VN_CAST(varp->valuep(), Const) || varp->isIO()) - continue; - } - if (AstAssign* const aitemp = VN_CAST(itemp, Assign)) { - if (VN_IS(aitemp->rhsp(), Const)) continue; - } + if (firstNewStatementOkRecurse(itemp)) continue; firstp = itemp; } } @@ -6566,6 +6685,22 @@ class WidthVisitor final : public VNVisitor { } return VN_CAST(pkgItemp->backp(), Package); } + const AstClass* containingClass(AstNode* nodep) { + // abovep is still needed, m_containingClassp is just a cache + if (const AstClass* const classp = VN_CAST(nodep, Class)) + return m_containingClassp[nodep] = classp; + if (const AstClassPackage* const packagep = VN_CAST(nodep, ClassPackage)) { + return m_containingClassp[nodep] = packagep->classp(); + } + if (m_containingClassp.find(nodep) != m_containingClassp.end()) { + return m_containingClassp[nodep]; + } + if (AstNode* const abovep = nodep->aboveLoopp()) { + return m_containingClassp[nodep] = containingClass(abovep); + } else { + return m_containingClassp[nodep] = nullptr; + } + } void visit(AstFuncRef* nodep) override { visit(static_cast(nodep)); if (nodep->taskp() && VN_IS(nodep->taskp(), Task)) { @@ -6765,10 +6900,8 @@ class WidthVisitor final : public VNVisitor { void handleStdRandomizeArgs(AstNodeFTaskRef* const nodep) { AstConst* nullp = nullptr; - for (AstNode *pinp = nodep->pinsp(), *nextp = nullptr; pinp; pinp = nextp) { - nextp = pinp->nextp(); - AstArg* const argp = VN_CAST(pinp, Arg); - if (!argp) continue; + for (AstArg *argp = nodep->argsp(), *nextp; argp; argp = nextp) { + nextp = VN_AS(argp->nextp(), Arg); AstNodeExpr* const exprp = argp->exprp(); if (AstConst* const constp = VN_CAST(exprp, Const)) { if (constp->num().isNull()) { @@ -6781,12 +6914,18 @@ class WidthVisitor final : public VNVisitor { // IEEE 1800-2023 (18.12) limits args to current scope variables. // Verilator accepts this for compatibility with other simulators. continue; - } else if (VN_IS(exprp, VarRef) || VN_IS(exprp, ArraySel)) { + } + if (VN_IS(exprp, VarRef) || VN_IS(exprp, ArraySel) || VN_IS(exprp, StructSel)) { // Valid usage continue; - } else { - argp->v3error("Non-variable arguments for 'std::randomize()'."); } + if (const AstCMethodHard* const methodp = VN_CAST(exprp, CMethodHard)) { + if (methodp->method() == VCMethod::ARRAY_AT + || methodp->method() == VCMethod::ARRAY_AT_WRITE) { + continue; + } + } + argp->v3error("Non-variable arguments for 'std::randomize()'."); } if (nullp) nullp->v3error("'std::randomize()' does not accept 'null' as arguments."); } @@ -6809,13 +6948,14 @@ class WidthVisitor final : public VNVisitor { if (nodep->classOrPackagep() && nodep->classOrPackagep()->name() == "std") { v3Global.useRandomizeMethods(true); AstNodeDType* const adtypep = nodep->findBitDType(); - withp = methodWithArgument(nodep, false, false, adtypep->findVoidDType(), - adtypep->findBitDType(), adtypep); - for (const AstNode* argp = nodep->pinsp(); argp; argp = argp->nextp()) - userIterateAndNext(VN_AS(argp, Arg)->exprp(), WidthVP{SELF, BOTH}.p()); + withp = methodWithClause(nodep, false, false, adtypep->findVoidDType(), + adtypep->findBitDType(), adtypep); + for (const AstArg* argp = nodep->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { + userIterateAndNext(argp->exprp(), WidthVP{SELF, BOTH}.p()); + } handleStdRandomizeArgs(nodep); // Provided args should be in current scope processFTaskRefArgs(nodep); - nodep->addPinsp(withp); + if (withp) nodep->withp(withp); nodep->didWidth(true); return; } @@ -6824,10 +6964,11 @@ class WidthVisitor final : public VNVisitor { AstClassRefDType* const adtypep = new AstClassRefDType{nodep->fileline(), classp, nullptr}; v3Global.rootp()->typeTablep()->addTypesp(adtypep); - withp = methodWithArgument(nodep, false, false, adtypep->findVoidDType(), - adtypep->findBitDType(), adtypep); - for (const AstNode* argp = nodep->pinsp(); argp; argp = argp->nextp()) - userIterateAndNext(VN_AS(argp, Arg)->exprp(), WidthVP{SELF, BOTH}.p()); + withp = methodWithClause(nodep, false, false, adtypep->findVoidDType(), + adtypep->findBitDType(), adtypep); + for (const AstArg* argp = nodep->argsp(); argp; argp = VN_AS(argp->nextp(), Arg)) { + userIterateAndNext(argp->exprp(), WidthVP{SELF, BOTH}.p()); + } handleRandomizeArgs(nodep, classp); } else if (nodep->name() == "srandom") { nodep->taskp(V3Randomize::newSRandomFunc(m_memberMap, classp)); @@ -6844,9 +6985,9 @@ class WidthVisitor final : public VNVisitor { return; } else if (nodep->name() == "set_randstate") { methodOkArguments(nodep, 1, 1); - AstNodeExpr* const expr1p = VN_AS(nodep->pinsp(), Arg)->exprp(); // May edit + AstNodeExpr* const expr1p = nodep->argsp()->exprp(); // May edit iterateCheckString(nodep, "LHS", expr1p, BOTH); - AstNodeExpr* const exprp = VN_AS(nodep->pinsp(), Arg)->exprp(); + AstNodeExpr* const exprp = nodep->argsp()->exprp(); classp->baseMostClassp()->needRNG(true); v3Global.useRandomizeMethods(true); AstCExpr* const newp @@ -6863,14 +7004,30 @@ class WidthVisitor final : public VNVisitor { } UASSERT_OBJ(nodep->taskp(), nodep, "Unlinked"); if (nodep->didWidth()) { - nodep->addPinsp(withp); + if (withp) nodep->withp(withp); return; } if ((nodep->taskp()->classMethod() && !nodep->taskp()->isStatic()) - && !VN_IS(m_procedurep, InitialAutomatic) - && (!m_ftaskp || !m_ftaskp->classMethod() || m_ftaskp->isStatic()) && !m_constraintp) { - nodep->v3error("Cannot call non-static member function " - << nodep->prettyNameQ() << " without object (IEEE 1800-2023 8.10)"); + && !VN_IS(m_procedurep, InitialAutomatic) && !m_constraintp) { + bool allow = false; + if (m_ftaskp && m_ftaskp->classMethod() && !m_ftaskp->isStatic()) { + if (const AstFuncRef* const funcRefp = VN_CAST(nodep, FuncRef)) { + allow = funcRefp->superReference(); + } else if (const AstTaskRef* const taskRefp = VN_CAST(nodep, TaskRef)) { + allow = taskRefp->superReference(); + } + if (!allow) { + const AstClass* callerClassp = containingClass(m_ftaskp); + if (!callerClassp) callerClassp = containingClass(m_ftaskp->classOrPackagep()); + const AstClass* calleeClassp = VN_CAST(nodep->classOrPackagep(), Class); + if (!calleeClassp) calleeClassp = containingClass(nodep->taskp()); + allow = AstClass::isClassExtendedFrom(callerClassp, calleeClassp); + } + } + if (!allow) { + nodep->v3error("Cannot call non-static member function " + << nodep->prettyNameQ() << " without object (IEEE 1800-2023 8.10)"); + } } if (nodep->taskp() && !nodep->scopeNamep() && (nodep->taskp()->dpiContext() || nodep->taskp()->dpiExport())) { @@ -6878,7 +7035,7 @@ class WidthVisitor final : public VNVisitor { } // And do the arguments to the task/function too processFTaskRefArgs(nodep); - nodep->addPinsp(withp); + if (withp) nodep->withp(withp); nodep->didWidth(true); // See steps that follow in visit(AstFuncRef*) } @@ -7688,6 +7845,11 @@ class WidthVisitor final : public VNVisitor { // Warn if user wants extra bit from carry if (subDTypep->widthMin() == (nodep->lhsp()->widthMin() + 1)) lhsWarn = false; if (subDTypep->widthMin() == (nodep->rhsp()->widthMin() + 1)) rhsWarn = false; + if (VN_IS(nodep, Add) && nodep->lhsp()->width() == 1 + && nodep->rhsp()->width() != 1) + lhsWarn = false; // do_increment + ... + if (nodep->rhsp()->width() == 1 && nodep->lhsp()->width() != 1) + rhsWarn = false; // ... + do_increment } else if (VN_IS(nodep, Mul) || VN_IS(nodep, MulS)) { if (subDTypep->widthMin() >= (nodep->lhsp()->widthMin())) lhsWarn = false; if (subDTypep->widthMin() >= (nodep->rhsp()->widthMin())) rhsWarn = false; @@ -8111,7 +8273,7 @@ class WidthVisitor final : public VNVisitor { linker.relink(newp); } else if (VN_IS(underVDTypep, ClassRefDType) || VN_IS(underVDTypep, IfaceRefDType) || (VN_IS(underVDTypep, BasicDType) - && VN_AS(underVDTypep, BasicDType)->keyword() == VBasicDTypeKwd::CHANDLE)) { + && VN_AS(underVDTypep, BasicDType)->isCHandle())) { // Allow warning-free "if (handle)" VL_DO_DANGLING(fixWidthReduce(VN_AS(underp, NodeExpr)), underp); // Changed } else if (!underVDTypep->basicp()) { @@ -8579,7 +8741,7 @@ class WidthVisitor final : public VNVisitor { void replaceWithSFormat(AstMethodCall* nodep, const string& format) { // For string.itoa and similar, replace with SFormatF - const AstArg* argp = VN_CAST(nodep->pinsp(), Arg); + AstArg* const argp = nodep->argsp(); UASSERT_OBJ(argp, nodep, "Argument needed for string method, call methodOkArguments before here"); AstNodeVarRef* const fromp = VN_AS(nodep->fromp()->unlinkFrBack(), VarRef); diff --git a/src/V3Width.h b/src/V3Width.h index 9a1e7ab79..7dd7471df 100644 --- a/src/V3Width.h +++ b/src/V3Width.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3WidthCommit.cpp b/src/V3WidthCommit.cpp index 11f765cd8..c5013ea6b 100644 --- a/src/V3WidthCommit.cpp +++ b/src/V3WidthCommit.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -48,8 +48,8 @@ class WidthCommitVisitor final : public VNVisitor { AstNodeFTask* m_ftaskp = nullptr; // Current function/task AstNodeModule* m_modp = nullptr; // Current module std::string m_contNba; // In continuous- or non-blocking assignment - bool m_dynsizedelem - = false; // Writing a dynamically-sized array element, not the array itself + bool m_contReads = false; // Check read continuous automatic variables + bool m_dynsizedelem = false; // Writing dynamically-sized array element, not the array itself VMemberMap m_memberMap; // Member names cached for fast lookup bool m_taskRefWarn = true; // Allow task reference warnings bool m_underSel = false; // Under AstMemberSel or AstSel @@ -390,7 +390,7 @@ private: iterateChildren(nodep); editDType(nodep); classEncapCheck(nodep, nodep->varp(), VN_CAST(nodep->classOrPackagep(), Class)); - if (nodep->access().isWriteOrRW()) varLifetimeCheck(nodep, nodep->varp()); + if (nodep->access().isWriteOrRW() || m_contReads) varLifetimeCheck(nodep, nodep->varp()); if (VN_IS(nodep, VarRef)) nodep->name(""); // Clear to save memory; nodep->name() will work via nodep->varp() } @@ -416,12 +416,31 @@ private: } } } + void visit(AstAssignCont* nodep) override { + iterateAndNextNull(nodep->timingControlp()); + { + VL_RESTORER(m_contNba); + VL_RESTORER(m_contReads); + m_contNba = "continuous"; + m_contReads = true; + iterateAndNextNull(nodep->lhsp()); + iterateAndNextNull(nodep->rhsp()); + } + editDType(nodep); + AstNode* const controlp + = nodep->timingControlp() ? nodep->timingControlp()->unlinkFrBack() : nullptr; + nodep->replaceWith(new AstAssign{nodep->fileline(), nodep->lhsp()->unlinkFrBack(), + nodep->rhsp()->unlinkFrBack(), controlp}); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + } void visit(AstAssignDly* nodep) override { iterateAndNextNull(nodep->timingControlp()); iterateAndNextNull(nodep->rhsp()); { VL_RESTORER(m_contNba); + VL_RESTORER(m_contReads); m_contNba = "nonblocking"; + m_contReads = false; iterateAndNextNull(nodep->lhsp()); } editDType(nodep); @@ -431,7 +450,9 @@ private: iterateAndNextNull(nodep->rhsp()); { VL_RESTORER(m_contNba); + VL_RESTORER(m_contReads); m_contNba = "continuous"; + m_contReads = false; iterateAndNextNull(nodep->lhsp()); } editDType(nodep); @@ -470,7 +491,7 @@ private: iterateChildren(nodep); } editDType(nodep); - if (auto* const classrefp = VN_CAST(nodep->fromp()->dtypep(), ClassRefDType)) { + if (AstClassRefDType* const classrefp = VN_CAST(nodep->fromp()->dtypep(), ClassRefDType)) { classEncapCheck(nodep, nodep->varp(), classrefp->classp()); } // else might be struct, etc varLifetimeCheck(nodep, nodep->varp()); @@ -510,6 +531,10 @@ private: } editDType(nodep); } + void visit(AstClassOrPackageRef* nodep) override { + // Reference must have been resolved, can delete these + VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); + } void visit(AstNode* nodep) override { iterateChildren(nodep); editDType(nodep); diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h index d57a64dbf..7715b1db7 100644 --- a/src/V3WidthCommit.h +++ b/src/V3WidthCommit.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3WidthRemove.h b/src/V3WidthRemove.h index d022333fc..0b553a5d9 100644 --- a/src/V3WidthRemove.h +++ b/src/V3WidthRemove.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp index e6abd704a..aa632a8c1 100644 --- a/src/V3WidthSel.cpp +++ b/src/V3WidthSel.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -266,6 +266,12 @@ class WidthSelVisitor final : public VNVisitor { newp->declRange(fromRange); newp->declElWidth(elwidth); newp->dtypeFrom(adtypep->subDTypep()); // Need to strip off array reference + if (VN_IS(adtypep->subDTypep(), BasicDType)) { + // IEEE 1800-2023 7.4.1 Packed arrays says: + // The individual elements of the array are unsigned + // unless they are of a named type declared as signed. + newp->dtypep()->numeric(VSigning::fromBool(false)); + } UINFOTREE(9, newp, "", "SELBTn"); nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 540f83d37..50a4dcf0f 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -47,11 +47,9 @@ #include "V3DiagSarif.h" #include "V3EmitC.h" #include "V3EmitCMain.h" -#include "V3EmitCMake.h" #include "V3EmitMk.h" #include "V3EmitMkJson.h" #include "V3EmitV.h" -#include "V3EmitXml.h" #include "V3ExecGraph.h" #include "V3Expand.h" #include "V3File.h" @@ -88,6 +86,7 @@ #include "V3RandSequence.h" #include "V3Randomize.h" #include "V3Reloop.h" +#include "V3Reorder.h" #include "V3Sampled.h" #include "V3Sched.h" #include "V3Scope.h" @@ -139,7 +138,6 @@ static void emitJson() VL_MT_DISABLED { } static void emitSerialized() VL_MT_DISABLED { - if (v3Global.opt.xmlOnly()) V3EmitXml::emitxml(); if (v3Global.opt.jsonOnly()) emitJson(); } @@ -404,7 +402,7 @@ static void process() { V3Active::activeAll(v3Global.rootp()); // Split single ALWAYS blocks into multiple blocks for better ordering chances - if (v3Global.opt.fSplit()) V3Split::splitAlwaysAll(v3Global.rootp()); + if (v3Global.opt.fSplit()) V3Split::splitAll(v3Global.rootp()); V3SplitAs::splitAsAll(v3Global.rootp()); // Create tracing sample points, before we start eliminating signals @@ -438,7 +436,7 @@ static void process() { V3Dead::deadifyAllScoped(v3Global.rootp()); // Reorder assignments in pipelined blocks - if (v3Global.opt.fReorder()) V3Split::splitReorderAll(v3Global.rootp()); + if (v3Global.opt.fReorder()) V3Reorder::reorderAll(v3Global.rootp()); if (v3Global.opt.timing().isSetTrue()) { // Convert AST for timing if requested @@ -637,8 +635,7 @@ static void process() { emitSerialized(); } else if (v3Global.opt.debugCheck() && !v3Global.opt.lintOnly() && !v3Global.opt.dpiHdrOnly()) { - // Check XML/JSON when debugging to make sure no missing node types - V3EmitXml::emitxml(); + // Check JSON when debugging to make sure no missing node types emitJson(); } @@ -655,7 +652,7 @@ static void process() { if (!v3Global.opt.lintOnly() && !v3Global.opt.serializeOnly() && !v3Global.opt.dpiHdrOnly()) { if (v3Global.opt.main()) V3EmitCMain::emit(); - // V3EmitMk/V3EmitCMake/V3EmitMkJson must be after all other emitters, + // V3EmitMk/V3EmitMkJson must be after all other emitters, // as they and below code visits AstCFiles added earlier size_t src_f_cnt = 0; for (AstNode* nodep = v3Global.rootp()->filesp(); nodep; nodep = nodep->nextp()) { @@ -663,7 +660,6 @@ static void process() { src_f_cnt += cfilep->source() ? 1 : 0; } if (src_f_cnt >= V3EmitMk::PARALLEL_FILE_CNT_THRESHOLD) v3Global.useParallelBuild(true); - if (v3Global.opt.cmake()) V3EmitCMake::emit(); if (v3Global.opt.makeJson()) V3EmitMkJson::emit(); if (v3Global.opt.gmake()) V3EmitMk::emitmk(); } @@ -765,10 +761,6 @@ static bool verilate(const string& argString) { hierGraphp->writeCommandArgsFiles(false); V3EmitMk::emitHierVerilation(hierGraphp); } - if (v3Global.opt.cmake()) { - hierGraphp->writeCommandArgsFiles(true); - V3EmitCMake::emit(); - } if (v3Global.opt.makeJson()) { hierGraphp->writeCommandArgsFiles(true); V3EmitMkJson::emit(); @@ -832,7 +824,6 @@ static string buildMakeCmd(const string& makefile, const string& target) { static void execBuildJob() { UASSERT(v3Global.opt.build(), "--build is not specified."); UASSERT(v3Global.opt.gmake(), "--build requires GNU Make."); - UASSERT(!v3Global.opt.cmake(), "--build cannot use CMake."); UASSERT(!v3Global.opt.makeJson(), "--build cannot use json build."); VlOs::DeltaWallTime buildWallTime{true}; UINFO(1, "Start Build"); diff --git a/src/VlcBucket.h b/src/VlcBucket.h index 05d2042ba..ff6f956d5 100644 --- a/src/VlcBucket.h +++ b/src/VlcBucket.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/VlcMain.cpp b/src/VlcMain.cpp index e8806b665..e5113a966 100644 --- a/src/VlcMain.cpp +++ b/src/VlcMain.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/VlcOptions.h b/src/VlcOptions.h index d03f3d8e8..7d957f722 100644 --- a/src/VlcOptions.h +++ b/src/VlcOptions.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/VlcPoint.h b/src/VlcPoint.h index 2cabf2d9f..7f667adce 100644 --- a/src/VlcPoint.h +++ b/src/VlcPoint.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -108,7 +108,7 @@ public: void dumpAnnotate(std::ostream& os, unsigned annotateMin) const { os << (ok(annotateMin) ? "+" : "-"); os << std::setw(6) << std::setfill('0') << count(); - os << " point: comment=" << comment() << " hier=" << hier(); + os << " point: type=" << type() << " comment=" << comment() << " hier=" << hier(); os << "\n"; } }; diff --git a/src/VlcSource.h b/src/VlcSource.h index 269fce83a..095e66cb5 100644 --- a/src/VlcSource.h +++ b/src/VlcSource.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/VlcTest.h b/src/VlcTest.h index 1e074287d..024d2b9b3 100644 --- a/src/VlcTest.h +++ b/src/VlcTest.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp index 1d5d2d86e..a4cc92ae7 100644 --- a/src/VlcTop.cpp +++ b/src/VlcTop.cpp @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/VlcTop.h b/src/VlcTop.h index 2b9fbca6c..13e0d93d6 100644 --- a/src/VlcTop.h +++ b/src/VlcTop.h @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/astgen b/src/astgen index f3b182e06..3d26c0474 100755 --- a/src/astgen +++ b/src/astgen @@ -1355,12 +1355,13 @@ parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Generate V3Ast headers to reduce C++ code duplication.""", - epilog="""Copyright 2002-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2002-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('-I', action='store', help='source code include directory') parser.add_argument('--astdef', action='append', help='add AST definition file (relative to -I)') diff --git a/src/bisonpre b/src/bisonpre index b4ab0e9d9..9be647f39 100755 --- a/src/bisonpre +++ b/src/bisonpre @@ -484,12 +484,13 @@ BISON GRAMMAR EXTENSIONS If the bison version is >= the specified version, include the given command. -Copyright 2002-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. +This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2002-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") # Local options parser.add_argument('--yacc', diff --git a/src/config_build.h b/src/config_build.h index cf7c47252..e2230f078 100644 --- a/src/config_build.h +++ b/src/config_build.h @@ -8,10 +8,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/config_package.h.in b/src/config_package.h.in index 97d0fc6e6..22909cbde 100644 --- a/src/config_package.h.in +++ b/src/config_package.h.in @@ -6,11 +6,10 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either -// the GNU Lesser General Public License Version 3 or -// the Perl Artistic License Version 2.0. -// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 diff --git a/src/config_rev b/src/config_rev index b45e8ca4b..432179abd 100755 --- a/src/config_rev +++ b/src/config_rev @@ -3,10 +3,10 @@ # pylint: disable=C0103,C0114,C0116 ###################################################################### # -# Copyright 2005-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2005-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/src/cppcheck-suppressions.txt b/src/cppcheck-suppressions.txt index 2c0c57770..754ef3c4b 100644 --- a/src/cppcheck-suppressions.txt +++ b/src/cppcheck-suppressions.txt @@ -1,7 +1,7 @@ -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ctunullpointer diff --git a/src/flexfix b/src/flexfix index a112cfb6b..3a4479bdd 100755 --- a/src/flexfix +++ b/src/flexfix @@ -3,10 +3,10 @@ # pylint: disable=C0114,C0301 ###################################################################### # -# Copyright 2002-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2002-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/src/mkinstalldirs b/src/mkinstalldirs index 3e2a294bd..9fe43ecf9 100644 --- a/src/mkinstalldirs +++ b/src/mkinstalldirs @@ -3,6 +3,8 @@ # Author: Noah Friedman # Created: 1993-05-16 # Public domain +# SPDX-FileCopyrightText: 1993 Noah Friedman +# SPDX-License-Identifier: CC0-1.0 errstatus=0 diff --git a/src/verilog.l b/src/verilog.l index 940903e69..7a47a7c43 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -6,10 +6,10 @@ * ************************************************************************** * - * Copyright 2003-2026 by Wilson Snyder. Verilator is free software; you - * can redistribute it and/or modify it under the terms of either the - * GNU Lesser General Public License Version 3 or the Perl Artistic License - * Version 2.0. + * This program is free software; you can redistribute it and/or modify it + * under the terms of either the GNU Lesser General Public License Version 3 + * or the Perl Artistic License Version 2.0. + * SPDX-FileCopyrightText: 2003-2026 Wilson Snyder * SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 * *************************************************************************/ @@ -161,6 +161,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "timing_on" { FL; return yVLT_TIMING_ON; } "tracing_off" { FL; return yVLT_TRACING_OFF; } "tracing_on" { FL; return yVLT_TRACING_ON; } + "verilator_lib" { FL; return yVLT_VERILATOR_LIB; } -?"-block" { FL; return yVLT_D_BLOCK; } -?"-contents" { FL; return yVLT_D_CONTENTS; } @@ -527,6 +528,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "$fell" { FL; return yD_FELL; } "$fell_gclk" { FL; return yD_FELL_GCLK; } "$future_gclk" { FL; return yD_FUTURE_GCLK; } + "$get_initial_random_seed" { FL; return yD_GET_INITIAL_RANDOM_SEED; } "$get_coverage" { FL; STR; ERROR_RSVD_WORD("IEEE 1800-2005"); return yaD_PLI; } "$high" { FL; return yD_HIGH; } "$increment" { FL; return yD_INCREMENT; } @@ -639,7 +641,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "string" { FL; return ySTRING; } "struct" { FL; return ySTRUCT; } "super" { FL; return ySUPER; } - "tagged" { FL; return yTAGGED; } + "tagged" { FL; return yTAGGED__LEX; } "this" { FL; return yTHIS; } "throughout" { FL; return yTHROUGHOUT; } "timeprecision" { FL; return yTIMEPRECISION; } diff --git a/src/verilog.y b/src/verilog.y index d4532db48..76ca9f54e 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -6,10 +6,10 @@ // //************************************************************************* // -// Copyright 2003-2026 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -136,6 +136,7 @@ const VBasicDTypeKwd LOGIC_IMPLICIT = VBasicDTypeKwd::LOGIC_IMPLICIT; #define DEL(...) \ { \ + /* cppcheck-suppress constVariable */ \ AstNode* const nodeps[] = {__VA_ARGS__}; \ for (AstNode* const nodep : nodeps) \ if (nodep) nodep->deleteTree(); \ @@ -170,8 +171,7 @@ void yyerror(const char* errmsg) { PARSEP->bisonLastFileline()->v3error(errmsg); template static T_Node* addNextNull(T_Node* nodep, T_Next* nextp) { - if (!nextp) return nodep; - return AstNode::addNext(nodep, nextp); + return AstNode::addNextNull(nodep, nextp); } //====================================================================== @@ -270,6 +270,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yVLT_TIMING_ON "timing_on" %token yVLT_TRACING_OFF "tracing_off" %token yVLT_TRACING_ON "tracing_on" +%token yVLT_VERILATOR_LIB "verilator_lib" %token yVLT_D_BLOCK "--block" %token yVLT_D_CONTENTS "--contents" @@ -539,6 +540,8 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yS_UNTIL_WITH "s_until_with" %token yTABLE "table" %token yTAGGED "tagged" +%token yTAGGED__LEX "tagged-in-lex" +%token yTAGGED__NONPRIMARY "tagged-nonprimary" %token yTASK "task" %token yTHIS "this" %token yTHROUGHOUT "throughout" @@ -686,6 +689,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yD_FWRITEB "$fwriteb" %token yD_FWRITEH "$fwriteh" %token yD_FWRITEO "$fwriteo" +%token yD_GET_INITIAL_RANDOM_SEED "$get_initial_random_seed" %token yD_GLOBAL_CLOCK "$global_clock" %token yD_HIGH "$high" %token yD_HYPOT "$hypot" @@ -1209,7 +1213,8 @@ module_declaration: // ==IEEE: module_declaration GRAMMARP->endLabel($6, $1, $6); } // | yEXTERN modFront parameter_port_listE portsStarE ';' - { BBUNSUP($1, "Unsupported: extern module"); } + { DEL($2->unlinkFrBack()); } + // We allow modules to be declared after instantiations, so harmless ; modFront: @@ -1393,9 +1398,9 @@ port: // ==IEEE: port // // IEEE: ansi_port_declaration, with [port_direction] removed // // IEEE: [ net_port_header | interface_port_header ] // // port_identifier { unpacked_dimension } [ '=' constant_expression ] - // // IEEE: [ net_port_header | variable_port_header ] '.' port_identifier '(' [ expression ] ')' // // IEEE: [ variable_port_header ] port_identifier // // { variable_dimension } [ '=' constant_expression ] + // // IEEE: '.' port_identifier '(' [ expression ] ')' // // Substitute net_port_header = [ port_direction ] net_port_type // // Substitute variable_port_header = [ port_direction ] variable_port_type // // Substitute net_port_type = [ net_type ] data_type_or_implicit @@ -1470,6 +1475,13 @@ port: // ==IEEE: port | portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE '=' constExpr { $$ = $2; /*VARDTYPE-same*/ if (AstVar* vp = VARDONEP($$, $3, $4)) { addNextNull($$, vp); vp->valuep($6); } } + // // IEEE: '.' port_identifier '(' [ expression ] ')' + | portDirNetE /*implicit*/ '.' portSig '(' expr ')' + { $$ = $3; DEL($5); + BBUNSUP($2, "Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2)"); } + // // IEEE: part of (non-ansi) port_reference + | '{' port_expressionList '}' + { $$ = $2; } ; portDirNetE: // IEEE: part of port, optional net type and/or direction @@ -1493,6 +1505,18 @@ portSig: { $$ = new AstPort{$1, PINNUMINC(), *$1}; } ; +port_expressionList: // IEEE: part of (non-ansi) port_reference + port_reference { $$ = $1; } + | port_expressionList ',' port_reference { $$ = addNextNull($1, $3); } + ; + +port_reference: // IEEE: (non-ansi) port-reference + // // IEEE: port_identifier constant_select + // // constant_select ::= [ '[' constant_part_select_range ']' ] + id/*port_identifier*/ { $$ = nullptr; } // UNSUP above here + | id/*port_identifier*/ part_select_range { $$ = nullptr; DEL($2); } // UNSUP above here + ; + //********************************************************************** // Interface headers @@ -1505,7 +1529,8 @@ interface_declaration: // IEEE: interface_declaration + interface_nonan if ($5) $1->addStmtsp($5); $1->hasParameterList($2); } | yEXTERN intFront parameter_port_listE portsStarE ';' - { BBUNSUP($1, "Unsupported: extern interface"); } + { DEL($2->unlinkFrBack()); } + // We allow interfaces to be declared after instantiations, so harmless ; intFront: @@ -1595,7 +1620,8 @@ program_declaration: // IEEE: program_declaration + program_nonansi_h if ($5) $1->addStmtsp($5); GRAMMARP->endLabel($7, $1, $7); } | yEXTERN pgmFront parameter_port_listE portsStarE ';' - { BBUNSUP($1, "Unsupported: extern program"); } + { DEL($2->unlinkFrBack()); } + // We allow programs to be declared after instantiations, so harmless ; pgmFront: @@ -2103,8 +2129,7 @@ data_typeVirtual: // ==IEEE: data_type after yVIRTUAL [ yI data_type_or_void: // ==IEEE: data_type_or_void data_typeAny { $$ = $1; } | yVOID - { $$ = new AstBasicDType{$1, LOGIC_IMPLICIT}; - BBUNSUP($1, "Unsupported: void (for tagged unions)"); } + { $$ = new AstBasicDType{$1, VBasicDTypeKwd::CVOID}; } ; var_data_type: // ==IEEE: var_data_type @@ -2135,7 +2160,7 @@ struct_unionDecl: // IEEE: part of data_type /*cont*/ struct_union_memberListEnd { $$ = $4; $$->addMembersp($5); } | yUNION taggedSoftE packedSigningE '{' - /*mid*/ { $$ = new AstUnionDType{$1, $2, $3}; } + /*mid*/ { $$ = new AstUnionDType{$1, $2 == tagged_SOFT, $2 == tagged_TAGGED, $3}; } /*cont*/ struct_union_memberListEnd { $$ = $5; $$->addMembersp($6); } ; @@ -2273,10 +2298,10 @@ random_qualifier: // ==IEEE: random_qualifier | yRANDC { $$ = VMemberQualifiers::none(); $$.m_randc = true; } ; -taggedSoftE: - /*empty*/ { $$ = false; } - | ySOFT { $$ = true; } - | yTAGGED { $$ = false; BBUNSUP($1, "Unsupported: tagged union"); } +taggedSoftE: + /*empty*/ { $$ = tagged_NONE; } + | ySOFT { $$ = tagged_SOFT; } + | yTAGGED { $$ = tagged_TAGGED; } ; packedSigningE: @@ -2902,48 +2927,48 @@ c_loop_generate_construct: // IEEE: loop_generate_construct (for checker ; genvar_initialization: // ==IEEE: genvar_initialization - varRefBase '=' expr { $$ = new AstAssign{$2, $1, $3}; } + parseRefBase '=' expr { $$ = new AstAssign{$2, $1, $3}; } | yGENVAR genvar_identifierDecl '=' constExpr { $$ = $2; AstNode::addNext($$, new AstAssign{$3, new AstVarRef{$2->fileline(), $2, VAccess::WRITE}, $4}); } ; genvar_iteration: // ==IEEE: genvar_iteration - varRefBase '=' expr + parseRefBase '=' expr { $$ = new AstAssign{$2, $1, $3}; } - | varRefBase yP_PLUSEQ expr + | parseRefBase yP_PLUSEQ expr { $$ = new AstAssign{$2, $1, new AstAdd{$2, $1->cloneTreePure(true), $3}}; } - | varRefBase yP_MINUSEQ expr + | parseRefBase yP_MINUSEQ expr { $$ = new AstAssign{$2, $1, new AstSub{$2, $1->cloneTreePure(true), $3}}; } - | varRefBase yP_TIMESEQ expr + | parseRefBase yP_TIMESEQ expr { $$ = new AstAssign{$2, $1, new AstMul{$2, $1->cloneTreePure(true), $3}}; } - | varRefBase yP_DIVEQ expr + | parseRefBase yP_DIVEQ expr { $$ = new AstAssign{$2, $1, new AstDiv{$2, $1->cloneTreePure(true), $3}}; } - | varRefBase yP_MODEQ expr + | parseRefBase yP_MODEQ expr { $$ = new AstAssign{$2, $1, new AstModDiv{$2, $1->cloneTreePure(true), $3}}; } - | varRefBase yP_ANDEQ expr + | parseRefBase yP_ANDEQ expr { $$ = new AstAssign{$2, $1, new AstAnd{$2, $1->cloneTreePure(true), $3}}; } - | varRefBase yP_OREQ expr + | parseRefBase yP_OREQ expr { $$ = new AstAssign{$2, $1, new AstOr{$2, $1->cloneTreePure(true), $3}}; } - | varRefBase yP_XOREQ expr + | parseRefBase yP_XOREQ expr { $$ = new AstAssign{$2, $1, new AstXor{$2, $1->cloneTreePure(true), $3}}; } - | varRefBase yP_SLEFTEQ expr + | parseRefBase yP_SLEFTEQ expr { $$ = new AstAssign{$2, $1, new AstShiftL{$2, $1->cloneTreePure(true), $3}}; } - | varRefBase yP_SRIGHTEQ expr + | parseRefBase yP_SRIGHTEQ expr { $$ = new AstAssign{$2, $1, new AstShiftR{$2, $1->cloneTreePure(true), $3}}; } - | varRefBase yP_SSRIGHTEQ expr + | parseRefBase yP_SSRIGHTEQ expr { $$ = new AstAssign{$2, $1, new AstShiftRS{$2, $1->cloneTreePure(true), $3}}; } // // inc_or_dec_operator - | yP_PLUSPLUS varRefBase + | yP_PLUSPLUS parseRefBase { $$ = new AstAssign{$1, $2, new AstAdd{$1, $2->cloneTreePure(true), new AstConst{$1, AstConst::StringToParse{}, "'b1"}}}; } - | yP_MINUSMINUS varRefBase + | yP_MINUSMINUS parseRefBase { $$ = new AstAssign{$1, $2, new AstSub{$1, $2->cloneTreePure(true), new AstConst{$1, AstConst::StringToParse{}, "'b1"}}}; } - | varRefBase yP_PLUSPLUS + | parseRefBase yP_PLUSPLUS { $$ = new AstAssign{$2, $1, new AstAdd{$2, $1->cloneTreePure(true), new AstConst{$2, AstConst::StringToParse{}, "'b1"}}}; } - | varRefBase yP_MINUSMINUS + | parseRefBase yP_MINUSMINUS { $$ = new AstAssign{$2, $1, new AstSub{$2, $1->cloneTreePure(true), new AstConst{$2, AstConst::StringToParse{}, "'b1"}}}; } ; @@ -3176,11 +3201,27 @@ list_of_defparam_assignments: //== IEEE: list_of_defparam_assignments ; defparam_assignment: // ==IEEE: defparam_assignment - idAny '.' idAny '=' expr { $$ = new AstDefParam{$4, *$1, *$3, $5}; } - | idAny '=' expr - { $$ = nullptr; BBUNSUP($2, "Unsupported: defparam with no dot"); DEL($3); } - | idAny '.' idAny '.' - { $$ = nullptr; BBUNSUP($4, "Unsupported: defparam with more than one dot"); } + defparamIdRange '.' defparamIdRange '=' expr + { $$ = new AstDefParam{$4, *$1, *$3, $5}; } + | defparamIdRange '=' expr + { $$ = nullptr; BBUNSUP($2, "Unsupported: defparam with no dot"); + DEL($3); } + | defparamIdRange '.' defparamIdRange '.' defparamIdRangeList '=' expr + { $$ = nullptr; BBUNSUP($4, "Unsupported: defparam with more than one dot"); + DEL($7); } + ; + +defparamIdRangeList: // IEEE: part of defparam_assignment + defparamIdRange { $$ = $1; } + | defparamIdRangeList '.' defparamIdRange { $$ = $3; } + ; + +defparamIdRange: // IEEE: part of defparam_assignment + idAny + { $$ = $1; } + | idAny part_select_rangeList + { $$ = $1; BBUNSUP($2, "Unsupported: defparam with arrayed instance"); + DEL($2); } ; //************************************************ @@ -3452,23 +3493,23 @@ par_blockJoin: | yJOIN_NONE { $$ = VJoinType::JOIN_NONE; } ; -par_block: // ==IEEE: par_block +par_block: // ==IEEE: par_block yFORK startLabelE blockDeclListE stmtListE par_blockJoin endLabelE { - AstFork* const forkp = new AstFork{$1, $5, $2 ? *$2 : ""}; - GRAMMARP->endLabel($6, forkp, $6); - forkp->addDeclsp($3); - $$ = V3ParseGrammar::wrapFork(PARSEP, forkp, $4); + $$ = new AstFork{$1, $5, $2 ? *$2 : ""}; + GRAMMARP->endLabel($6, $$, $6); + $$->addDeclsp($3); + $$->addForksp(V3ParseGrammar::wrapInBegin($4)); } ; -par_blockPreId: // ==IEEE: par_block but called with leading ID +par_blockPreId: // ==IEEE: par_block but called with leading ID id yP_COLON__FORK yFORK blockDeclListE stmtListE par_blockJoin endLabelE { - AstFork* const forkp = new AstFork{$3, $6, *$1}; - GRAMMARP->endLabel($7, forkp, $7); - forkp->addDeclsp($4); - $$ = V3ParseGrammar::wrapFork(PARSEP, forkp, $5); + $$ = new AstFork{$3, $6, *$1}; + GRAMMARP->endLabel($7, $$, $7); + $$->addDeclsp($4); + $$->addForksp(V3ParseGrammar::wrapInBegin($5)); } ; @@ -3496,7 +3537,7 @@ stmtList: | stmtList error ';' { $$ = $1; } // LCOV_EXCL_LINE ; -stmt: // IEEE: statement + seq_block + par_block +stmt: // IEEE: statement + statement_or_null + seq_block + par_block statement_item { $$ = $1; } // // S05 block creation rule | id/*block_identifier*/ ':' statement_item { $$ = new AstBegin{$1, *$1, $3, false}; } @@ -3527,7 +3568,7 @@ statement_item: // IEEE: statement_item { $$ = new AstAssignDly{$2, $1, $4, $3}; } //UNSUP cycle_delay fexprLvalue yP_LTE ';' { UNSUP } | yASSIGN idClassSel '=' delay_or_event_controlE expr ';' - { $$ = new AstAssign{$1, $2, $5, $4}; } + { $$ = new AstAssignCont{$1, $2, $5, $4}; } | yDEASSIGN variable_lvalue ';' { $$ = nullptr; BBUNSUP($1, "Unsupported: Verilog 1995 deassign"); DEL($2); } | yFORCE variable_lvalue '=' expr ';' @@ -3541,9 +3582,13 @@ statement_item: // IEEE: statement_item if ($1 == uniq_UNIQUE) $2->uniquePragma(true); if ($1 == uniq_UNIQUE0) $2->unique0Pragma(true); if ($1 == uniq_PRIORITY) $2->priorityPragma(true); } - // &&& is part of expr so case_patternList aliases to case_itemList - | unique_priorityE caseStart caseAttrE yMATCHES case_itemList yENDCASE - { $$ = nullptr; BBUNSUP($4, "Unsupported: matches (for tagged union)"); DEL($2, $5); } + // case matches uses patterns, not expressions + | unique_priorityE caseStart caseAttrE yMATCHES case_matches_itemList yENDCASE + { $$ = $2; if ($5) $2->addItemsp($5); + $2->caseMatchesSet(); + if ($1 == uniq_UNIQUE) $2->uniquePragma(true); + if ($1 == uniq_UNIQUE0) $2->unique0Pragma(true); + if ($1 == uniq_PRIORITY) $2->priorityPragma(true); } | unique_priorityE caseStart caseAttrE yINSIDE case_inside_itemList yENDCASE { $$ = $2; if ($5) $2->addItemsp($5); if (!$2->caseSimple()) $4->v3error("Illegal to have inside on a casex/casez"); @@ -3795,7 +3840,7 @@ class_new: // IEEE: class_new class_newNoScope: // IEEE: class_new but no packageClassScope // // Special precedence so (...) doesn't match expr - yNEW__ETC { $$ = new AstNew{$1, nullptr}; } + yNEW__ETC { $$ = new AstNew{$1}; } | yNEW__ETC expr { $$ = new AstNewCopy{$1, $2}; } | yNEW__PAREN '(' list_of_argumentsE ')' { $$ = new AstNew{$1, $3}; } ; @@ -3848,6 +3893,21 @@ case_inside_itemList: // IEEE: { case_inside_item + range_list | case_inside_itemList yDEFAULT colon stmt { $$ = $1->addNext(new AstCaseItem{$2, nullptr, $4}); } ; +case_matches_itemList: // IEEE: { case_pattern_item + ... } + // // IEEE: case_pattern_item ::= pattern [&&& expr] : stmt + // // pattern includes expr for tagged void members (tagged id) + patternNoExpr colon stmt { $$ = new AstCaseItem{$2, $1, $3}; } + | expr colon stmt { $$ = new AstCaseItem{$2, $1, $3}; } + | yDEFAULT colon stmt { $$ = new AstCaseItem{$1, nullptr, $3}; } + | yDEFAULT stmt { $$ = new AstCaseItem{$1, nullptr, $2}; } + | case_matches_itemList patternNoExpr colon stmt + { $$ = $1->addNext(new AstCaseItem{$3, $2, $4}); } + | case_matches_itemList expr colon stmt + { $$ = $1->addNext(new AstCaseItem{$3, $2, $4}); } + | case_matches_itemList yDEFAULT stmt { $$ = $1->addNext(new AstCaseItem{$2, nullptr, $3}); } + | case_matches_itemList yDEFAULT colon stmt { $$ = $1->addNext(new AstCaseItem{$2, nullptr, $4}); } + ; + rand_case_itemList: // IEEE: { rand_case_item + ... } // // Randcase syntax doesn't have default, or expression lists expr colon stmt { $$ = new AstCaseItem{$2, $1, $3}; } @@ -3893,15 +3953,19 @@ caseCondList: // IEEE: part of case_item | caseCondList ',' exprTypeCompare { $$ = $1->addNext($3); } ; -patternNoExpr: // IEEE: pattern **Excluding Expr* +patternNoExpr: // IEEE: pattern **Excluding Expr* '.' idAny/*variable*/ - { $$ = nullptr; BBUNSUP($1, "Unsupported: '{} tagged patterns"); } + { $$ = new AstPatternVar{$1, *$2}; } | yP_DOTSTAR - { $$ = nullptr; BBUNSUP($1, "Unsupported: '{} tagged patterns"); } + { $$ = new AstPatternStar{$1}; } // // IEEE: "expr" excluded; expand in callers - // // "yTAGGED idAny [expr]" Already part of expr + // // IEEE: tagged member_identifier [ pattern ] + // // Standalone "yTAGGED__NONPRIMARY idAny" is handled via expr in patternOne + // // Here, we need to treat yTAGGED and yTAGGED__NONPRIMARY identically. | yTAGGED idAny/*member_identifier*/ patternNoExpr - { $$ = nullptr; BBUNSUP($1, "Unsupported: '{} tagged patterns"); DEL($3); } + { $$ = new AstTaggedPattern{$1, *$2, $3}; } + | yTAGGED__NONPRIMARY idAny/*member_identifier*/ patternNoExpr + { $$ = new AstTaggedPattern{$1, *$2, $3}; } // // "yP_TICKBRA patternList '}'" part of expr under assignment_pattern ; @@ -3924,10 +3988,10 @@ patternMemberList: // IEEE: part of pattern and assignment_pattern patternMemberOne: // IEEE: part of pattern and assignment_pattern patternKey ':' expr { $$ = new AstPatMember{$1->fileline(), $3, $1, nullptr}; } - | patternKey ':' patternNoExpr { $$ = nullptr; BBUNSUP($2, "Unsupported: '{} .* patterns"); DEL($1, $3); } + | patternKey ':' patternNoExpr { $$ = new AstPatMember{$1->fileline(), $3, $1, nullptr}; } // // From assignment_pattern_key | yDEFAULT ':' expr { $$ = new AstPatMember{$1, $3, nullptr, nullptr}; $$->isDefault(true); } - | yDEFAULT ':' patternNoExpr { $$ = nullptr; BBUNSUP($2, "Unsupported: '{} .* patterns"); DEL($3); } + | yDEFAULT ':' patternNoExpr { AstPatMember* const patp = new AstPatMember{$1, $3, nullptr, nullptr}; patp->isDefault(true); $$ = patp; } ; patternKey: // IEEE: merge structure_pattern_key, array_pattern_key, assignment_pattern_key @@ -4037,17 +4101,20 @@ for_step_assignment: // ==IEEE: for_step_assignment ; loop_variables: // IEEE: loop_variables - parseRefBase { $$ = $1; } - | loop_variables ',' parseRefBase { $$ = $1->addNext($3); } - | ',' parseRefBase { $$ = new AstEmpty{$1}; $$->addNext($2); } - | ',' { $$ = new AstEmpty{$1}; } + loop_variableE { $$ = $1; } + | loop_variables ',' loop_variableE { $$ = $1->addNext($3); } + ; + +loop_variableE: // IEEE: part of loop_variables + /* empty */ { $$ = new AstEmpty{CRELINE()}; } + | parseRefBase { $$ = $1; } ; //************************************************ // Functions/tasks taskRef: // IEEE: part of tf_call - id { $$ = new AstTaskRef{$1, *$1, nullptr}; } + id { $$ = new AstTaskRef{$1, *$1}; } | id '(' list_of_argumentsE ')' { $$ = new AstTaskRef{$1, *$1, $3}; } | packageClassScope id '(' list_of_argumentsE ')' { $$ = AstDot::newIfPkg($2, $1, new AstTaskRef{$2, *$2, $4}); } @@ -4092,7 +4159,7 @@ task_subroutine_callNoMethod: // function_subroutine_callNoMethod // // funcref below not task ref to avoid conflict, must later handle either | funcRef yWITH__PAREN '(' expr ')' { $$ = new AstWithParse{$2, $1, $4}; } // // can call as method and yWITH without parenthesis - | id yWITH__PAREN '(' expr ')' { $$ = new AstWithParse{$2, new AstFuncRef{$1, *$1, nullptr}, $4}; } + | id yWITH__PAREN '(' expr ')' { $$ = new AstWithParse{$2, new AstFuncRef{$1, *$1}, $4}; } // // IEEE: method_call requires a "." so is in expr // // IEEE: ['std::'] not needed, as normal std package resolution will find it // // IEEE: randomize_call @@ -4107,7 +4174,7 @@ function_subroutine_callNoMethod: // IEEE: function_subroutine funcRef { $$ = $1; } | funcRef yWITH__PAREN '(' expr ')' { $$ = new AstWithParse{$2, $1, $4}; } // // can call as method and yWITH without parenthesis - | id yWITH__PAREN '(' expr ')' { $$ = new AstWithParse{$2, new AstFuncRef{$1, *$1, nullptr}, $4}; } + | id yWITH__PAREN '(' expr ')' { $$ = new AstWithParse{$2, new AstFuncRef{$1, *$1}, $4}; } | system_f_only_expr_call { $$ = $1; } | system_f_or_t_expr_call { $$ = $1; } // // IEEE: method_call requires a "." so is in expr @@ -4391,6 +4458,7 @@ system_f_or_t_expr_call: // IEEE: part of system_tf_call (can be tas | yD_FSCANF '(' expr ',' str commaVRDListE ')' { $$ = new AstFScanF{$1, *$5, $3, $6}; } | yD_FSEEK '(' expr ',' expr ',' expr ')' { $$ = new AstFSeek{$1, $3, $5, $7}; } | yD_FTELL '(' expr ')' { $$ = new AstFTell{$1, $3}; } + | yD_GET_INITIAL_RANDOM_SEED parenE { $$ = new AstGetInitialRandomSeed{$1}; } | yD_GLOBAL_CLOCK parenE { $$ = GRAMMARP->createGlobalClockParseRef($1); } | yD_HIGH '(' exprOrDataType ')' { $$ = new AstAttrOf{$1, VAttrType::DIM_HIGH, $3, nullptr}; } | yD_HIGH '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf{$1, VAttrType::DIM_HIGH, $3, $5}; } @@ -4533,10 +4601,10 @@ exprOrDataType: // expr | data_type: combined to prevent conflic //UNSUP | exprOrDataTypeList ',' exprOrDataType { $$ = addNextNull($1, $3); } //UNSUP ; -list_of_argumentsE: // IEEE: [list_of_arguments] +list_of_argumentsE: // IEEE: [list_of_arguments] argsDottedList { $$ = $1; } | argsExprListE - { if (VN_IS($1, Arg) && VN_CAST($1, Arg)->emptyConnectNoNext()) { + { if ($1->emptyConnectNoNext()) { $1->deleteTree(); $$ = nullptr; // Mis-created when have 'func()' } else { $$ = $1; } } | argsExprListE ',' argsDottedList { $$ = addNextNull($1, $3); } @@ -4808,10 +4876,10 @@ parenE: // // method_call_root not needed, part of expr resolution // // What's left is below array_methodNoRoot array_methodNoRoot: - yOR { $$ = new AstFuncRef{$1, "or", nullptr}; } - | yAND { $$ = new AstFuncRef{$1, "and", nullptr}; } - | yXOR { $$ = new AstFuncRef{$1, "xor", nullptr}; } - | yUNIQUE { $$ = new AstFuncRef{$1, "unique", nullptr}; } + yOR { $$ = new AstFuncRef{$1, "or"}; } + | yAND { $$ = new AstFuncRef{$1, "and"}; } + | yXOR { $$ = new AstFuncRef{$1, "xor"}; } + | yUNIQUE { $$ = new AstFuncRef{$1, "unique"}; } ; array_methodWith: @@ -4819,7 +4887,7 @@ array_methodWith: | array_methodNoRoot parenE yWITH__PAREN '(' expr ')' { $$ = new AstWithParse{$3, $1, $5}; } | array_methodNoRoot '(' expr ')' yWITH__PAREN '(' expr ')' - { $$ = new AstWithParse{$5, $1, $7}; $1->addPinsp(new AstArg{$3, "", $3}); } + { $$ = new AstWithParse{$5, $1, $7}; $1->addArgsp(new AstArg{$3, "", $3}); } ; dpi_import_export: // ==IEEE: dpi_import_export @@ -5001,9 +5069,34 @@ expr: // IEEE: part of expression/constant_expression/ | ~l~expr yINSIDE '{' range_list '}' { $$ = new AstInside{$2, $1, $4}; } // // // IEEE: tagged_union_expression - //UNSUP yTAGGED id/*member*/ %prec prTAGGED { $$ = $2; BBUNSUP("tagged reference"); } - // // Spec only allows primary - //UNSUP yTAGGED id/*member*/ %prec prTAGGED expr /*primary*/ { $$ = $2; BBUNSUP("tagged reference"); } + // // yTAGGED__NONPRIMARY = tokenPipeline determined no primary follows + | yTAGGED__NONPRIMARY idAny/*member*/ %prec prTAGGED + { $$ = new AstTaggedExpr{$1, *$2, nullptr}; } + // // yTAGGED = primary follows; handle specific primary types + // // Parenthesized expression + | yTAGGED idAny/*member*/ '(' expr ')' %prec prTAGGED + { $$ = new AstTaggedExpr{$1, *$2, $4}; } + // // Assignment patterns like tagged Add '{a, b, c} + | yTAGGED idAny/*member*/ assignment_pattern %prec prTAGGED + { $$ = new AstTaggedExpr{$1, *$2, $3}; } + // // Integer literal + | yTAGGED idAny/*member*/ yaINTNUM %prec prTAGGED + { $$ = new AstTaggedExpr{$1, *$2, new AstConst{$3, *$3}}; } + // // Float literal + | yTAGGED idAny/*member*/ yaFLOATNUM %prec prTAGGED + { $$ = new AstTaggedExpr{$1, *$2, new AstConst{$3, AstConst::RealDouble{}, $3}}; } + // // String literal + | yTAGGED idAny/*member*/ yaSTRING %prec prTAGGED + { $$ = new AstTaggedExpr{$1, *$2, new AstConst{$3, AstConst::VerilogStringLiteral{}, *$3}}; } + // // null literal + | yTAGGED idAny/*member*/ yNULL %prec prTAGGED + { $$ = new AstTaggedExpr{$1, *$2, new AstConst{$3, AstConst::Null{}}}; } + // // Identifier as value + | yTAGGED idAny/*member*/ idAny %prec prTAGGED + { $$ = new AstTaggedExpr{$1, *$2, new AstParseRef{$3, *$3, nullptr, nullptr}}; } + // // Concatenation + | yTAGGED idAny/*member*/ '{' cateList '}' %prec prTAGGED + { $$ = new AstTaggedExpr{$1, *$2, $4}; } // //======================// IEEE: primary/constant_primary // @@ -5109,10 +5202,8 @@ expr: // IEEE: part of expression/constant_expression/ // // IEEE: cond_pattern - here to avoid reduce problems // // "expr yMATCHES pattern" // // IEEE: pattern - expanded here to avoid conflicts - | ~l~expr yMATCHES patternNoExpr { $$ = new AstConst{$2, AstConst::BitFalse{}}; - BBUNSUP($2, "Unsupported: matches operator"); } - | ~l~expr yMATCHES ~r~expr { $$ = new AstConst{$2, AstConst::BitFalse{}}; - BBUNSUP($2, "Unsupported: matches operator"); } + | ~l~expr yMATCHES patternNoExpr { $$ = new AstMatches{$2, $1, $3}; } + | ~l~expr yMATCHES ~r~expr { $$ = new AstMatches{$2, $1, $3}; } // // // IEEE: expression_or_dist - here to avoid reduce problems // // "expr yDIST '{' dist_list '}'" @@ -5295,7 +5386,7 @@ exprDispList: // exprList for within $display { $$ = $1->addNext(new AstConst{$2, AstConst::VerilogStringLiteral{}, " "}); } ; -vrdList: +vrdList: idClassSel { $$ = $1; } | vrdList ',' idClassSel { $$ = $1->addNext($3); } ; @@ -5305,7 +5396,7 @@ commasE: | ',' commasE { } /* ignored */ ; -commaVRDListE: +commaVRDListE: /* empty */ { $$ = nullptr; } | ',' vrdList { $$ = $2; } ; @@ -5315,7 +5406,7 @@ argsExprList: // IEEE: part of list_of_arguments (used where , | argsExprList ',' expr { $$ = $1->addNext($3); } ; -argsExprListE: // IEEE: part of list_of_arguments +argsExprListE: // IEEE: part of list_of_arguments argsExprOneE { $$ = $1; } | argsExprListE ',' argsExprOneE { $$ = $1->addNext($3); } ; @@ -5325,7 +5416,7 @@ argsExprListE: // IEEE: part of list_of_arguments //UNSUP | pev_argsExprListE ',' pev_argsExprOneE { $$ = addNextNull($1, $3); } //UNSUP ; -argsExprOneE: // IEEE: part of list_of_arguments +argsExprOneE: // IEEE: part of list_of_arguments /*empty*/ { $$ = new AstArg{CRELINE(), "", nullptr}; } | expr { $$ = new AstArg{$1->fileline(), "", $1}; } ; @@ -5335,7 +5426,7 @@ argsExprOneE: // IEEE: part of list_of_arguments //UNSUP | pev_expr { $$ = $1; } //UNSUP ; -argsDottedList: // IEEE: part of list_of_arguments +argsDottedList: // IEEE: part of list_of_arguments argsDotted { $$ = $1; } | argsDottedList ',' argsDotted { $$ = addNextNull($1, $3); } ; @@ -5345,12 +5436,12 @@ argsDottedList: // IEEE: part of list_of_arguments //UNSUP | pev_argsDottedList ',' pev_argsDotted { $$ = addNextNull($1, $3); } //UNSUP ; -argsDotted: // IEEE: part of list_of_arguments +argsDotted: // IEEE: part of list_of_arguments '.' idAny '(' ')' { $$ = new AstArg{$2, *$2, nullptr}; } | '.' idAny '(' expr ')' { $$ = new AstArg{$2, *$2, $4}; } ; -//UNSUPpev_argsDotted: // IEEE: part of list_of_arguments - pev_expr at bottom +//UNSUPpev_argsDotted: // IEEE: part of list_of_arguments - pev_expr at bottom //UNSUP '.' idAny '(' ')' { $$ = new AstArg{$2, *$2, nullptr}; } //UNSUP | '.' idAny '(' pev_expr ')' { $$ = new AstArg{$2, *$2, $4}; } //UNSUP ; @@ -6034,17 +6125,18 @@ idClassSel: // Misc Ref to dotted, and/or arrayed, and/or bi | packageClassScope idDottedSel { $$ = new AstDot{$2, true, $1, $2}; } ; -idClassSelForeach: +idClassSelForeach: idDottedForeach { $$ = $1; } // // IEEE: [ implicit_class_handle . | package_scope ] hierarchical_variable_identifier select | yTHIS '.' idDottedForeach - { $$ = new AstDot{$2, false, new AstParseRef{$1, "this"}, $3}; } + { $3->fromp(new AstDot{$2, false, new AstParseRef{$1, "this"}, $3->fromp()->unlinkFrBack()}); $$ = $3; } | ySUPER '.' idDottedForeach - { $$ = new AstDot{$2, false, new AstParseRef{$1, "super"}, $3}; } + { $3->fromp(new AstDot{$2, false, new AstParseRef{$1, "super"}, $3->fromp()->unlinkFrBack()}); $$ = $3; } | yTHIS '.' ySUPER '.' idDottedForeach - { $$ = new AstDot{$4, false, new AstParseRef{$3, "super"}, $5}; } + { $5->fromp(new AstDot{$4, false, new AstParseRef{$3, "super"}, $5->fromp()->unlinkFrBack()}); $$ = $5; } // // Expanded: package_scope idForeach - | packageClassScope idDottedForeach { $$ = new AstDot{$2, true, $1, $2}; } + | packageClassScope idDottedForeach + { $2->fromp(new AstDot{$2, true, $1, $2->fromp()->unlinkFrBack()}); $$ = $2; } ; @@ -6069,15 +6161,15 @@ idDottedSel: | idDottedSelMore { $$ = $1; } ; -idDottedForeach: +idDottedForeach: yD_ROOT '.' idDottedMoreForeach - { $$ = new AstDot{$2, false, new AstParseRef{$1, "$root"}, $3}; } + { $3->fromp(new AstDot{$2, false, new AstParseRef{$1, "$root"}, $3->fromp()->unlinkFrBack()}); $$ = $3; } | idDottedMoreForeach { $$ = $1; } ; idDottedMore: - varRefBase { $$ = $1; } - | idDottedMore '.' varRefBase { $$ = new AstDot{$2, false, $1, $3}; } + parseRefBase { $$ = $1; } + | idDottedMore '.' parseRefBase { $$ = new AstDot{$2, false, $1, $3}; } ; idDottedSelMore: @@ -6085,9 +6177,10 @@ idDottedSelMore: | idDottedSelMore '.' idArrayed { $$ = new AstDot{$2, false, $1, $3}; } ; -idDottedMoreForeach: +idDottedMoreForeach: idArrayedForeach { $$ = $1; } - | idDottedMoreForeach '.' idArrayedForeach { $$ = new AstDot{$2, false, $1, $3}; } + | idDottedSelMore '.' idArrayedForeach + { $3->fromp(new AstDot{$2, false, $1, $3->fromp()->unlinkFrBack()}); $$ = $3; } ; // Single component of dotted path, maybe [#]. @@ -6106,36 +6199,24 @@ idArrayed: // IEEE: id + select | idArrayed '[' expr yP_MINUSCOLON constExpr ']' { $$ = new AstSelMinus{$2, $1, $3, $5}; } ; -idArrayedForeach: // IEEE: id + select (under foreach expression) - id - { $$ = new AstParseRef{$1, *$1, nullptr, nullptr}; } - // // IEEE: id + part_select_range/constant_part_select_range - | idArrayed '[' expr ']' { $$ = new AstSelBit{$2, $1, $3}; } // Or AstArraySel, don't know yet. - | idArrayed '[' constExpr ':' constExpr ']' { $$ = new AstSelExtract{$2, $1, $3, $5}; } - // // IEEE: id + indexed_range/constant_indexed_range - | idArrayed '[' expr yP_PLUSCOLON constExpr ']' { $$ = new AstSelPlus{$2, $1, $3, $5}; } - | idArrayed '[' expr yP_MINUSCOLON constExpr ']' { $$ = new AstSelMinus{$2, $1, $3, $5}; } - // // IEEE: loop_variables (under foreach expression) - // // To avoid conflicts we allow expr as first element, must post-check +idArrayedForeach: // IEEE: id + select (under foreach expression) + parseRefBase // Malformed, but accept for better error reporting + { $$ = new AstForeachHeader{$1, $1, nullptr}; } + | idArrayed '[' expr ']' + { $$ = new AstForeachHeader{$2, $1, $3}; } | idArrayed '[' ']' - { $$ = new AstSelLoopVars{$2, $1, new AstEmpty{$3}}; } - | idArrayed '[' expr ',' loop_variables ']' - { $$ = new AstSelLoopVars{$2, $1, addNextNull(static_cast($3), $5)}; } + { $$ = new AstForeachHeader{$2, $1, new AstEmpty{$3}}; } + | idArrayed '[' parseRefBase ',' loop_variables ']' + { $$ = new AstForeachHeader{$2, $1, addNextNull(static_cast($3), $5)}; } | idArrayed '[' ',' loop_variables ']' - { $$ = new AstSelLoopVars{$2, $1, addNextNull(static_cast(new AstEmpty{$3}), $4)}; } + { $$ = new AstForeachHeader{$2, $1, addNextNull(static_cast(new AstEmpty{$3}), $4)}; } ; -// VarRef without any dots or vectorizaion -varRefBase: +// ParseRef without any dots or vectorizaion +parseRefBase: id { $$ = new AstParseRef{$1, *$1}; } ; -// ParseRef -parseRefBase: - id - { $$ = new AstParseRef{$1, *$1, nullptr, nullptr}; } - ; - // yaSTRING shouldn't be used directly, instead via an abstraction below str: // yaSTRING but with \{escapes} need decoded yaSTRING { $$ = PARSEP->newString(GRAMMARP->unquoteString($1, *$1)); } @@ -6353,11 +6434,11 @@ concurrent_assertion_statement: // ==IEEE: concurrent_assertion_stat // // IEEE: assume_property_statement // // action_block expanded here assertOrAssume yPROPERTY '(' property_spec ')' stmt %prec prLOWER_THAN_ELSE - { $$ = new AstAssert{$1, new AstSampled{$1, $4}, $6, nullptr, VAssertType::CONCURRENT, $1}; } + { $$ = new AstAssert{$1, $4, $6, nullptr, VAssertType::CONCURRENT, $1}; } | assertOrAssume yPROPERTY '(' property_spec ')' stmt yELSE stmt - { $$ = new AstAssert{$1, new AstSampled{$1, $4}, $6, $8, VAssertType::CONCURRENT, $1}; } + { $$ = new AstAssert{$1, $4, $6, $8, VAssertType::CONCURRENT, $1}; } | assertOrAssume yPROPERTY '(' property_spec ')' yELSE stmt - { $$ = new AstAssert{$1, new AstSampled{$1, $4}, nullptr, $7, VAssertType::CONCURRENT, $1}; } + { $$ = new AstAssert{$1, $4, nullptr, $7, VAssertType::CONCURRENT, $1}; } // // IEEE: cover_property_statement | yCOVER yPROPERTY '(' property_spec ')' stmt { $$ = new AstCover{$1, $4, $6, VAssertType::CONCURRENT}; } @@ -6539,27 +6620,7 @@ property_spec: // IEEE: property_spec | pexpr { $$ = new AstPropSpec{$1->fileline(), nullptr, nullptr, $1}; } ; -//UNSUPproperty_statement_spec: // ==IEEE: property_statement_spec -//UNSUP // // IEEE: [ clocking_event ] [ yDISABLE yIFF '(' expression_or_dist ')' ] property_statement -//UNSUP property_statement { $$ = $1; } -//UNSUP | yDISABLE yIFF '(' expr/*expression_or_dist*/ ')' property_statement { } -//UNSUP // // IEEE: clocking_event property_statement -//UNSUP // // IEEE: clocking_event yDISABLE yIFF '(' expr/*expression_or_dist*/ ')' property_statement -//UNSUP // // Both overlap pexpr:"clocking_event pexpr" the difference is -//UNSUP // // property_statement:property_statementCaseIf so replicate it -//UNSUP | clocking_event property_statementCaseIf { } -//UNSUP | clocking_event yDISABLE yIFF '(' expr/*expression_or_dist*/ ')' property_statementCaseIf { } -//UNSUP ; - -//UNSUPproperty_statement: // ==IEEE: property_statement -//UNSUP // // Doesn't make sense to have "pexpr ;" in pexpr rule itself, so we split out case/if -//UNSUP pexpr ';' { $$ = $1; } -//UNSUP // // Note this term replicated in property_statement_spec -//UNSUP // // If committee adds terms, they may need to be there too. -//UNSUP | property_statementCaseIf { $$ = $1; } -//UNSUP ; - -property_statementCaseIf: // IEEE: property_statement - minus pexpr +property_exprCaseIf: // IEEE: part of property_expr for if/case yCASE '(' expr/*expression_or_dist*/ ')' property_case_itemList yENDCASE { $$ = new AstConst{$1, AstConst::BitFalse{}}; BBUNSUP($1, "Unsupported: property case expression"); @@ -6640,7 +6701,7 @@ pexpr: // IEEE: property_expr (The name pexpr is important as regex // // // IEEE-2009: property_statement // // IEEE-2012: yIF and yCASE - | property_statementCaseIf { $$ = $1; } + | property_exprCaseIf { $$ = $1; } // | ~o~pexpr/*sexpr*/ yP_POUNDMINUSPD pexpr { $$ = $1; BBUNSUP($2, "Unsupported: #-# (in property expression)"); DEL($3); } @@ -6695,7 +6756,8 @@ pexpr: // IEEE: property_expr (The name pexpr is important as regex // // property_statement_spec: clocking_event property_statement // // // Include property_specDisable to match property_spec rule - //UNSUP clocking_event yDISABLE yIFF '(' expr ')' pexpr %prec prSEQ_CLOCKING { } + //UNSUP clocking_event ~p~sexpr %prec prSEQ_CLOCKING + //UNSUP { $$ = $2; BBUNSUP($2, "Unsupported: clocking event (in sequence expression)"); DEL($1); } // //============= sexpr rules copied for property_expr | BISONPRE_COPY_ONCE(sexpr,{s/~p~s/p/g; }) // {copied} @@ -6963,6 +7025,8 @@ bins_or_options: // ==IEEE: bins_or_options { $$ = nullptr; BBCOVERIGN($4, "Ignoring unsupported: cover bin specification"); DEL($3, $6, $8); } | bins_keyword idAny/*bin_identifier*/ bins_orBraE '=' '{' range_list '}' yWITH__PAREN '(' cgexpr ')' iffE { $$ = nullptr; BBCOVERIGN($8, "Ignoring unsupported: cover bin 'with' specification"); DEL($3, $6, $10, $12); } + | bins_keyword idAny/*bin_identifier*/ bins_orBraE '=' id/*cover_point_id*/ yWITH__PAREN '(' cgexpr ')' iffE + { $$ = nullptr; BBCOVERIGN($6, "Ignoring unsupported: cover bin 'with' specification"); DEL($3, $8, $10); } | yWILDCARD bins_keyword idAny/*bin_identifier*/ bins_orBraE '=' '{' range_list '}' iffE { $$ = nullptr; BBCOVERIGN($5, "Ignoring unsupported: cover bin 'wildcard' specification"); DEL($4, $7, $9); } | yWILDCARD bins_keyword idAny/*bin_identifier*/ bins_orBraE '=' '{' range_list '}' yWITH__PAREN '(' cgexpr ')' iffE @@ -7779,7 +7843,13 @@ constraint_primary: // ==IEEE: constraint_primary constraint_expressionList: // ==IEEE: { constraint_expression } constraint_expression { $$ = $1; } + | ySOLVE solve_before_list yBEFORE solve_before_list ';' + { ($1)->v3warn(CONSTRAINTIGN, "Ignoring unsupported: solve-before only supported as top-level constraint statement"); + $$ = nullptr; DEL($2, $4); } | constraint_expressionList constraint_expression { $$ = addNextNull($1, $2); } + | constraint_expressionList ySOLVE solve_before_list yBEFORE solve_before_list ';' + { ($2)->v3warn(CONSTRAINTIGN, "Ignoring unsupported: solve-before only supported as top-level constraint statement"); + $$ = $1; DEL($3, $5); } ; constraint_expression: // ==IEEE: constraint_expression @@ -8121,6 +8191,8 @@ vltItem: { V3Control::addProfileData($1, *$2, $3->toUQuad()); } | yVLT_PROFILE_DATA vltDModel vltDMtask vltDCost { V3Control::addProfileData($1, *$2, *$3, $4->toUQuad()); } + | yVLT_VERILATOR_LIB vltDModule + { V3Control::addModulePragma(*$2, VPragmaType::VERILATOR_LIB); } ; vltOffFront: diff --git a/src/vlcovgen b/src/vlcovgen index b5133d1cf..3e156603d 100755 --- a/src/vlcovgen +++ b/src/vlcovgen @@ -79,12 +79,13 @@ parser = argparse.ArgumentParser( allow_abbrev=False, formatter_class=argparse.RawDescriptionHelpFormatter, description="""Generate verilated_cov headers to reduce C++ code duplication.""", - epilog="""Copyright 2002-2026 by Wilson Snyder. This program is free software; you -can redistribute it and/or modify it under the terms of either the GNU -Lesser General Public License Version 3 or the Perl Artistic License -Version 2.0. + epilog="""This program is free software; you can redistribute it and/or modify it +under the terms of either the GNU Lesser General Public License Version 3 +or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") +SPDX-FileCopyrightText: 2002-2026 Wilson Snyder +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--srcdir', action='store', help='directory containing Verilator sources') diff --git a/test_regress/CMakeLists.txt b/test_regress/CMakeLists.txt index 0c5540426..0d89bf2bd 100644 --- a/test_regress/CMakeLists.txt +++ b/test_regress/CMakeLists.txt @@ -4,10 +4,10 @@ # # This CMake file is meant to be consumed by regression tests. # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/test_regress/Makefile b/test_regress/Makefile index 713faa9b3..51f6be287 100644 --- a/test_regress/Makefile +++ b/test_regress/Makefile @@ -5,10 +5,10 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ @@ -99,8 +99,14 @@ distclean:: # Can be overridden for multiple snapshots TEST_SNAP_DIR ?= snapshot +define CMD_EXISTS +$(shell which $(1) > /dev/null 2>&1 && echo ok) +endef + +# GNU find +GNU_FIND := $(if $(call CMD_EXISTS, gfind), gfind, find) # Command to diff directories -TEST_DIFF_TOOL ?= $(if $(shell which icdiff), icdiff -N -r, diff -r) +TEST_DIFF_TOOL ?= $(if $(call CMD_EXISTS, icdiff), icdiff -N -r --cols=$(shell tput cols), diff -r) TEST_SNAP_IGNORE := \ *.status *.log *.dat *.d *.o *.a *.so *stats*.txt *.html *.includecache \ @@ -114,7 +120,7 @@ define TEST_SNAP_template mkdir -p $(TEST_SNAP_DIR) rm -rf $(TEST_SNAP_DIR)/obj_$(1) cp -r obj_$(1) $(TEST_SNAP_DIR)/ -find $(TEST_SNAP_DIR)/obj_$(1) \( $(TEST_SNAP_IGNORE:%=-name "%" -o) \ +$(GNU_FIND) $(TEST_SNAP_DIR)/obj_$(1) \( $(TEST_SNAP_IGNORE:%=-name "%" -o) \ -type f -executable \) -prune | xargs rm -r endef diff --git a/test_regress/Makefile_obj b/test_regress/Makefile_obj index e02c112b3..b7c6c5af1 100644 --- a/test_regress/Makefile_obj +++ b/test_regress/Makefile_obj @@ -5,10 +5,10 @@ # # This is executed in the object directory, and called by ../Makefile # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #***************************************************************************** diff --git a/test_regress/driver.py b/test_regress/driver.py index 025e3d263..dd76f244f 100755 --- a/test_regress/driver.py +++ b/test_regress/driver.py @@ -1416,7 +1416,8 @@ class VlTest: entering=self.obj_dir, cmd=[ os.environ['MAKE'], - (("-j " + str(Args.driver_build_jobs)) if Args.driver_build_jobs else ""), + (("-j " + + str(Args.driver_build_jobs_n)) if Args.driver_build_jobs_n else ""), "-C " + self.obj_dir, "-f " + os.path.abspath(os.path.dirname(__file__)) + "/Makefile_obj", ("" if self.verbose else "--no-print-directory"), @@ -1673,6 +1674,10 @@ class VlTest: VlTest._cached_aslr_off = "" return VlTest._cached_aslr_off + @property + def build_jobs(self) -> str: + return "--build-jobs " + str(Args.driver_build_jobs_n) + @property def driver_verilator_flags(self) -> list: return Args.passdown_verilator_flags @@ -2435,6 +2440,9 @@ class VlTest: if n: l1o.append(line) break # Trunc rest + if re.search(r'This fatal error may be caused', line): + l1o.append(line) + break # Trunc after "This fatal error" line l1o.append(line) # l1s = l1o @@ -2489,7 +2497,7 @@ class VlTest: print("%Warning: HARNESS_UPDATE_GOLDEN set: cp " + fn1 + " " + fn2, file=sys.stderr) shutil.copy(fn1, fn2) - def vcd_identical(self, fn1: str, fn2: str) -> None: + def vcd_identical(self, fn1: str, fn2: str, ignore_attr: bool = False) -> None: """Test if two VCD files have logically-identical contents""" # vcddiff to check transitions, if installed cmd = "vcddiff --help" @@ -2508,6 +2516,9 @@ class VlTest: # Also provides backup if vcddiff not installed h1 = self._vcd_read(fn1) h2 = self._vcd_read(fn2) + if ignore_attr: + h1 = {k: v for k, v in h1.items() if "$attr" not in v} + h2 = {k: v for k, v in h2.items() if "$attr" not in v} a = json.dumps(h1, sort_keys=True, indent=1) b = json.dumps(h2, sort_keys=True, indent=1) if a != b: @@ -2527,11 +2538,17 @@ class VlTest: out = VtOs.run_capture(cmd, check=False) print(out) - def fst_identical(self, fn1: str, fn2: str) -> None: + def fst_identical(self, fn1: str, fn2: str, ignore_attr: bool = False) -> None: """Test if two FST files have logically-identical contents""" - tmp = fn1 + ".vcd" - self.fst2vcd(fn1, tmp) - self.vcd_identical(tmp, fn2) + if fn1.endswith(".fst"): + tmp = fn1 + ".vcd" + self.fst2vcd(fn1, tmp) + fn1 = tmp + if fn2.endswith(".fst"): + tmp = fn2 + ".vcd" + self.fst2vcd(fn2, tmp) + fn2 = tmp + self.vcd_identical(fn1, fn2, ignore_attr) def saif_identical(self, fn1: str, fn2: str) -> None: """Test if two SAIF files have logically-identical contents""" @@ -2542,7 +2559,7 @@ class VlTest: if out != '': print(out) self.copy_if_golden(fn1, fn2) - self.error("SAIF files don't match!") + self.error("SAIF files miscompare") def _vcd_read(self, filename: str) -> dict: data = {} @@ -2945,12 +2962,13 @@ if __name__ == '__main__': epilog="""driver.py invokes Verilator or another simulator on each test file. See docs/internals.rst in the distribution for more information. - Copyright 2024-2026 by Wilson Snyder. This program is free software; you - can redistribute it and/or modify it under the terms of either the GNU - Lesser General Public License Version 3 or the Perl Artistic License - Version 2.0. + This program is free software; you can redistribute it and/or modify it + under the terms of either the GNU Lesser General Public License Version + 3 or the Perl Artistic License Version 2.0. - SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") + SPDX-FileCopyrightText: 2024-2026 Wilson Snyder + SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +""") parser.add_argument('--benchmark', action='store', help='enable benchmarking') parser.add_argument('--debug', action='store_const', const=9, help='enable debug') @@ -3062,8 +3080,8 @@ if __name__ == '__main__': forker = Forker(Args.jobs) - Args.driver_build_jobs = None if len(Arg_Tests) >= 2 and Args.jobs >= 2: + Args.driver_build_jobs_n = 2 # Read supported into master process, so don't call every subprocess Capabilities.warmup_cache() # Without this tests such as t_debug_sigsegv_bt_bad.py will occasionally @@ -3073,6 +3091,6 @@ if __name__ == '__main__': sys.stdin = open("/dev/null", 'r', encoding="utf8") # pylint: disable=consider-using-with else: # Speed up single-test makes - Args.driver_build_jobs = calc_jobs() + Args.driver_build_jobs_n = calc_jobs() run_them() diff --git a/test_regress/t/TestCheck.h b/test_regress/t/TestCheck.h index 6538e6ef8..f4c0f424b 100644 --- a/test_regress/t/TestCheck.h +++ b/test_regress/t/TestCheck.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2013-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2013-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/TestSimulator.h b/test_regress/t/TestSimulator.h index 7cd774629..ea999e2c3 100644 --- a/test_regress/t/TestSimulator.h +++ b/test_regress/t/TestSimulator.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2013-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2013-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/TestVpi.h b/test_regress/t/TestVpi.h index 88587a622..8627bccf0 100644 --- a/test_regress/t/TestVpi.h +++ b/test_regress/t/TestVpi.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2013-2026 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2013-2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/TestVpiMain.cpp b/test_regress/t/TestVpiMain.cpp index b72127d15..8f25ce24e 100644 --- a/test_regress/t/TestVpiMain.cpp +++ b/test_regress/t/TestVpiMain.cpp @@ -1,18 +1,11 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2024-2025 by Andrew Nolte. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// SPDX-FileCopyrightText: 2024-2025 cocotb contributors +// SPDX-License-Identifier: BSD-3-Clause // //************************************************************************* -// Copyright cocotb contributors -// Licensed under the Revised BSD License, see LICENSE for details. -// SPDX-License-Identifier: BSD-3-Clause - #include "verilated.h" #include "verilated_vpi.h" diff --git a/test_regress/t/t_EXAMPLE.py b/test_regress/t/t_EXAMPLE.py index e41ab0cdd..8a938befd 100755 --- a/test_regress/t/t_EXAMPLE.py +++ b/test_regress/t/t_EXAMPLE.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v index abcaa336a..b470624b4 100644 --- a/test_regress/t/t_EXAMPLE.v +++ b/test_regress/t/t_EXAMPLE.v @@ -12,8 +12,8 @@ // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2026 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_a1_first_cc.py b/test_regress/t/t_a1_first_cc.py index db89b3543..d13223772 100755 --- a/test_regress/t/t_a1_first_cc.py +++ b/test_regress/t/t_a1_first_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # show-config: This test runs the very first time we've executed Verilator diff --git a/test_regress/t/t_a1_first_cc.v b/test_regress/t/t_a1_first_cc.v index e541f39d9..03a9a497f 100644 --- a/test_regress/t/t_a1_first_cc.v +++ b/test_regress/t/t_a1_first_cc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_a2_first_sc.py b/test_regress/t/t_a2_first_sc.py index b72c58858..16ed8d0c0 100755 --- a/test_regress/t/t_a2_first_sc.py +++ b/test_regress/t/t_a2_first_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This test runs the very first time we've executed Verilator --sc diff --git a/test_regress/t/t_a3_selftest.py b/test_regress/t/t_a3_selftest.py index ff241c671..01049fc36 100755 --- a/test_regress/t/t_a3_selftest.py +++ b/test_regress/t/t_a3_selftest.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_a3_selftest_thread.py b/test_regress/t/t_a3_selftest_thread.py index a20a9e981..aa47a0366 100755 --- a/test_regress/t/t_a3_selftest_thread.py +++ b/test_regress/t/t_a3_selftest_thread.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_a6_examples.py b/test_regress/t/t_a6_examples.py index c0c1dae26..fecd52453 100755 --- a/test_regress/t/t_a6_examples.py +++ b/test_regress/t/t_a6_examples.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_cyclic_bad.py b/test_regress/t/t_alias_cyclic_bad.py index f093111b2..f3bbcad9d 100755 --- a/test_regress/t/t_alias_cyclic_bad.py +++ b/test_regress/t/t_alias_cyclic_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_cyclic_bad.v b/test_regress/t/t_alias_cyclic_bad.v index b1232d24c..b22d8edc0 100644 --- a/test_regress/t/t_alias_cyclic_bad.v +++ b/test_regress/t/t_alias_cyclic_bad.v @@ -2,8 +2,8 @@ // // Simple bi-directional transitive alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_alias_force.py b/test_regress/t/t_alias_force.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_alias_force.py +++ b/test_regress/t/t_alias_force.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_force.v b/test_regress/t/t_alias_force.v index 92e782e59..e4c95c3ca 100644 --- a/test_regress/t/t_alias_force.v +++ b/test_regress/t/t_alias_force.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_alias_hier_ref_bad.py b/test_regress/t/t_alias_hier_ref_bad.py index f093111b2..f3bbcad9d 100755 --- a/test_regress/t/t_alias_hier_ref_bad.py +++ b/test_regress/t/t_alias_hier_ref_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_hier_ref_bad.v b/test_regress/t/t_alias_hier_ref_bad.v index f17a9cdcf..842dcc39a 100644 --- a/test_regress/t/t_alias_hier_ref_bad.v +++ b/test_regress/t/t_alias_hier_ref_bad.v @@ -2,8 +2,8 @@ // // Alias type check error test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_alias_ports_unsup.py b/test_regress/t/t_alias_ports_unsup.py index 272fc1280..1952b53a1 100755 --- a/test_regress/t/t_alias_ports_unsup.py +++ b/test_regress/t/t_alias_ports_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_ports_unsup.v b/test_regress/t/t_alias_ports_unsup.v index a8807dbc1..91ab6490a 100644 --- a/test_regress/t/t_alias_ports_unsup.v +++ b/test_regress/t/t_alias_ports_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_alias_simple.py b/test_regress/t/t_alias_simple.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_alias_simple.py +++ b/test_regress/t/t_alias_simple.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_simple.v b/test_regress/t/t_alias_simple.v index a68e63130..5cda4508c 100644 --- a/test_regress/t/t_alias_simple.v +++ b/test_regress/t/t_alias_simple.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_alias_sub_select.py b/test_regress/t/t_alias_sub_select.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_alias_sub_select.py +++ b/test_regress/t/t_alias_sub_select.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_sub_select.v b/test_regress/t/t_alias_sub_select.v index 1e9ee9f29..78fbfea60 100644 --- a/test_regress/t/t_alias_sub_select.v +++ b/test_regress/t/t_alias_sub_select.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_alias_transitive.py b/test_regress/t/t_alias_transitive.py index 4f09ae982..84b274f68 100755 --- a/test_regress/t/t_alias_transitive.py +++ b/test_regress/t/t_alias_transitive.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_transitive.v b/test_regress/t/t_alias_transitive.v index a38298417..9faea7a60 100644 --- a/test_regress/t/t_alias_transitive.v +++ b/test_regress/t/t_alias_transitive.v @@ -2,8 +2,8 @@ // // Simple bi-directional transitive alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_alias_tristate_unsup.py b/test_regress/t/t_alias_tristate_unsup.py index 272fc1280..1952b53a1 100755 --- a/test_regress/t/t_alias_tristate_unsup.py +++ b/test_regress/t/t_alias_tristate_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_tristate_unsup.v b/test_regress/t/t_alias_tristate_unsup.v index 37c98a384..dbb2c6417 100644 --- a/test_regress/t/t_alias_tristate_unsup.v +++ b/test_regress/t/t_alias_tristate_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_alias_unsup.py b/test_regress/t/t_alias_unsup.py index 272fc1280..1952b53a1 100755 --- a/test_regress/t/t_alias_unsup.py +++ b/test_regress/t/t_alias_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_unsup.v b/test_regress/t/t_alias_unsup.v index ba96a9bb3..3fc958d2e 100644 --- a/test_regress/t/t_alias_unsup.v +++ b/test_regress/t/t_alias_unsup.v @@ -2,8 +2,8 @@ // // Simple bi-directional alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_alias_var_bad.py b/test_regress/t/t_alias_var_bad.py index f093111b2..f3bbcad9d 100755 --- a/test_regress/t/t_alias_var_bad.py +++ b/test_regress/t/t_alias_var_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_var_bad.v b/test_regress/t/t_alias_var_bad.v index 70f7c75bc..22801f289 100644 --- a/test_regress/t/t_alias_var_bad.v +++ b/test_regress/t/t_alias_var_bad.v @@ -2,8 +2,8 @@ // // Alias width check error test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_alias_width_bad.py b/test_regress/t/t_alias_width_bad.py index f093111b2..f3bbcad9d 100755 --- a/test_regress/t/t_alias_width_bad.py +++ b/test_regress/t/t_alias_width_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alias_width_bad.v b/test_regress/t/t_alias_width_bad.v index e2b33c27b..e5378cc59 100644 --- a/test_regress/t/t_alias_width_bad.v +++ b/test_regress/t/t_alias_width_bad.v @@ -2,8 +2,8 @@ // // Alias width check error test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_altera_lpm.v b/test_regress/t/t_altera_lpm.v index d1f3537fc..3b48d349c 100644 --- a/test_regress/t/t_altera_lpm.v +++ b/test_regress/t/t_altera_lpm.v @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: LicenseRef-Altera-No-Warranty +// SPDX-FileCopyrightText: 2016 Altera Corporation //------------------------------------------------------------------------- // This Verilog file was developed by Altera Corporation. It may be // freely copied and/or distributed at no cost. Any persons using this diff --git a/test_regress/t/t_altera_lpm_abs.py b/test_regress/t/t_altera_lpm_abs.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_abs.py +++ b/test_regress/t/t_altera_lpm_abs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_add_sub.py b/test_regress/t/t_altera_lpm_add_sub.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_add_sub.py +++ b/test_regress/t/t_altera_lpm_add_sub.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_and.py b/test_regress/t/t_altera_lpm_and.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_and.py +++ b/test_regress/t/t_altera_lpm_and.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_bustri.py b/test_regress/t/t_altera_lpm_bustri.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_bustri.py +++ b/test_regress/t/t_altera_lpm_bustri.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_bustri_noinl.py b/test_regress/t/t_altera_lpm_bustri_noinl.py new file mode 100755 index 000000000..ff6f6e705 --- /dev/null +++ b/test_regress/t/t_altera_lpm_bustri_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') +test.top_filename = "t/t_altera_lpm.v" +module = re.sub(r'.*t_altera_', '', test.name) +module = re.sub(r'_noinl', '', module) + +test.compile(verilator_flags2=["--top-module", module, "-fno-inline"]) + +test.passes() diff --git a/test_regress/t/t_altera_lpm_clshift.py b/test_regress/t/t_altera_lpm_clshift.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_clshift.py +++ b/test_regress/t/t_altera_lpm_clshift.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_compare.py b/test_regress/t/t_altera_lpm_compare.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_compare.py +++ b/test_regress/t/t_altera_lpm_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_constant.py b/test_regress/t/t_altera_lpm_constant.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_constant.py +++ b/test_regress/t/t_altera_lpm_constant.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_counter.py b/test_regress/t/t_altera_lpm_counter.py index 8863b8607..971d7ce7b 100755 --- a/test_regress/t/t_altera_lpm_counter.py +++ b/test_regress/t/t_altera_lpm_counter.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_decode.py b/test_regress/t/t_altera_lpm_decode.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_decode.py +++ b/test_regress/t/t_altera_lpm_decode.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_divide.py b/test_regress/t/t_altera_lpm_divide.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_divide.py +++ b/test_regress/t/t_altera_lpm_divide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_ff.py b/test_regress/t/t_altera_lpm_ff.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_ff.py +++ b/test_regress/t/t_altera_lpm_ff.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_fifo.py b/test_regress/t/t_altera_lpm_fifo.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_fifo.py +++ b/test_regress/t/t_altera_lpm_fifo.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_fifo_dc.py b/test_regress/t/t_altera_lpm_fifo_dc.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_fifo_dc.py +++ b/test_regress/t/t_altera_lpm_fifo_dc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_inv.py b/test_regress/t/t_altera_lpm_inv.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_inv.py +++ b/test_regress/t/t_altera_lpm_inv.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_latch.py b/test_regress/t/t_altera_lpm_latch.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_latch.py +++ b/test_regress/t/t_altera_lpm_latch.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_mult.py b/test_regress/t/t_altera_lpm_mult.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_mult.py +++ b/test_regress/t/t_altera_lpm_mult.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_mult_noinl.py b/test_regress/t/t_altera_lpm_mult_noinl.py index 82c1fef6a..ed460d248 100755 --- a/test_regress/t/t_altera_lpm_mult_noinl.py +++ b/test_regress/t/t_altera_lpm_mult_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_mux.py b/test_regress/t/t_altera_lpm_mux.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_mux.py +++ b/test_regress/t/t_altera_lpm_mux.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_or.py b/test_regress/t/t_altera_lpm_or.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_or.py +++ b/test_regress/t/t_altera_lpm_or.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_ram_dp.py b/test_regress/t/t_altera_lpm_ram_dp.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_ram_dp.py +++ b/test_regress/t/t_altera_lpm_ram_dp.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_ram_dq.py b/test_regress/t/t_altera_lpm_ram_dq.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_ram_dq.py +++ b/test_regress/t/t_altera_lpm_ram_dq.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_ram_io.py b/test_regress/t/t_altera_lpm_ram_io.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_ram_io.py +++ b/test_regress/t/t_altera_lpm_ram_io.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_rom.py b/test_regress/t/t_altera_lpm_rom.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_rom.py +++ b/test_regress/t/t_altera_lpm_rom.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_shiftreg.py b/test_regress/t/t_altera_lpm_shiftreg.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_shiftreg.py +++ b/test_regress/t/t_altera_lpm_shiftreg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_altera_lpm_xor.py b/test_regress/t/t_altera_lpm_xor.py index 72661f8d6..f26c3d861 100755 --- a/test_regress/t/t_altera_lpm_xor.py +++ b/test_regress/t/t_altera_lpm_xor.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alw_combdly.v b/test_regress/t/t_alw_combdly.v deleted file mode 100644 index 88e554a1b..000000000 --- a/test_regress/t/t_alw_combdly.v +++ /dev/null @@ -1,61 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - - reg [31:0] a, b, c, d, e, f, g, h; - - always @ (*) begin // Test Verilog 2001 (*) - // verilator lint_off COMBDLY - c <= a | b; - // verilator lint_on COMBDLY - end - - always @ (posedge (clk)) begin // always bug 2008/4/18 - d <= a | b; - end - always @ ((d)) begin // always bug 2008/4/18 - e = d; - end - - parameter CONSTANT = 1; - always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412 - f = e; - end - always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412 - g = f; - end - always @ ({CONSTANT, g}) begin // bug745 - h = g; - end - //always @ ((posedge b) or (a or b)) begin // note both illegal - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - a <= 32'hfeed0000; - b <= 32'h0000face; - end - if (cyc==2) begin - if (c != 32'hfeedface) $stop; - end - if (cyc==3) begin - if (h != 32'hfeedface) $stop; - end - if (cyc==7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end -endmodule diff --git a/test_regress/t/t_alw_dly.v b/test_regress/t/t_alw_dly.v deleted file mode 100644 index e43a8012f..000000000 --- a/test_regress/t/t_alw_dly.v +++ /dev/null @@ -1,64 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - - reg posedge_wr_clocks; - reg prev_wr_clocks; - reg [31:0] m_din; - reg [31:0] m_dout; - - always @(negedge clk) begin - prev_wr_clocks = 0; - end - - reg comb_pos_1; - reg comb_prev_1; - always @ (/*AS*/clk or posedge_wr_clocks or prev_wr_clocks) begin - comb_pos_1 = (clk &~ prev_wr_clocks); - comb_prev_1 = comb_pos_1 | posedge_wr_clocks; - comb_pos_1 = 1'b1; - end - - always @ (posedge clk) begin - posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS - prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS - if (posedge_wr_clocks) begin - //$write("[%0t] Wrclk\n", $time); - m_dout <= m_din; - end - end - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - $write(" %x\n",comb_pos_1); - m_din <= 32'hfeed; - end - if (cyc==2) begin - $write(" %x\n",comb_pos_1); - m_din <= 32'he11e; - end - if (cyc==3) begin - m_din <= 32'he22e; - $write(" %x\n",comb_pos_1); - if (m_dout!=32'hfeed) $stop; - end - if (cyc==4) begin - if (m_dout!=32'he11e) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - end -endmodule diff --git a/test_regress/t/t_alw_nosplit.v b/test_regress/t/t_alw_nosplit.v deleted file mode 100644 index 2bfb37b6e..000000000 --- a/test_regress/t/t_alw_nosplit.v +++ /dev/null @@ -1,145 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - - reg [15:0] m_din; - - // We expect none of these blocks to split. - // Blocks that can split should go in t_alw_split.v instead. - - reg [15:0] b_split_1, b_split_2; - always @ (/*AS*/m_din) begin - b_split_1 = m_din; - b_split_2 = b_split_1; - end - - reg [15:0] c_split_1, c_split_2; - always @ (/*AS*/m_din) begin - c_split_1 = m_din; - c_split_2 = c_split_1; - c_split_1 = ~m_din; - end - - always @ (posedge clk) begin - $write(" foo %x", m_din); - $write(" bar %x\n", m_din); - end - - reg [15:0] e_split_1, e_split_2; - always @ (posedge clk) begin - e_split_1 = m_din; - e_split_2 = e_split_1; - end - - reg [15:0] f_split_1, f_split_2; - always @ (posedge clk) begin - f_split_2 = f_split_1; - f_split_1 = m_din; - end - - function logic[15:0] sideeffect_func(logic [15:0] v); - /*verilator no_inline_task */ - $display(" sideeffect_func() is called %t", $time); - return ~v; - endfunction - reg [15:0] m_split_1 = 0; - reg [15:0] m_split_2 = 0; - always @(posedge clk) begin - if (sideeffect_func(m_split_1) != 16'b0) begin - m_split_1 <= m_din; - end else begin - m_split_2 <= m_din; - end - end - - - reg [15:0] z_split_1, z_split_2; - always @ (posedge clk) begin - z_split_1 <= 0; - z_split_1 <= ~m_din; - end - always @ (posedge clk) begin - z_split_2 <= 0; - z_split_2 <= z_split_1; - end - - reg [15:0] h_split_1; - reg [15:0] h_split_2; - reg [15:0] h_foo; - always @ (posedge clk) begin -// $write(" cyc = %x m_din = %x\n", cyc, m_din); - h_foo = m_din; - if (cyc > 2) begin - // This conditional depends on non-primary-input foo. - // Its dependency on foo should not be pruned. As a result, - // the dependencies of h_split_1 and h_split_2 on this - // conditional will also not be pruned, making them all - // weakly connected such that they'll end up in the same graph - // and we can't split. - if (h_foo == 16'h0) begin - h_split_1 <= 16'h0; - h_split_2 <= 16'h0; - end - else begin - h_split_1 <= m_din; - h_split_2 <= ~m_din; - end - end - else begin - h_split_1 <= 16'h0; - h_split_2 <= 16'h0; - end - end // always @ (posedge clk) - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - end - if (cyc==1) begin - m_din <= 16'hfeed; - end - if (cyc==4) begin - m_din <= 16'he11e; - if (!(b_split_1==16'hfeed && b_split_2==16'hfeed)) $stop; - if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop; - if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; - if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; - if (!(m_split_1==16'hfeed && m_split_2==16'h0000)) $stop; - if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; - end - if (cyc==5) begin - m_din <= 16'he22e; - if (!(b_split_1==16'he11e && b_split_2==16'he11e)) $stop; - if (!(c_split_1==16'h1ee1 && c_split_2==16'he11e)) $stop; - // Two valid orderings, as we don't know which posedge clk gets evaled first - if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; - if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; - if (!(m_split_1==16'hfeed && m_split_2==16'h0000)) $stop; - if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop; - end - if (cyc==6) begin - m_din <= 16'he33e; - if (!(b_split_1==16'he22e && b_split_2==16'he22e)) $stop; - if (!(c_split_1==16'h1dd1 && c_split_2==16'he22e)) $stop; - // Two valid orderings, as we don't know which posedge clk gets evaled first - if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; - if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; - if (!(m_split_1==16'he11e && m_split_2==16'h0000)) $stop; - if (!(z_split_1==16'h1ee1 && z_split_2==16'h0112)) $stop; - end - if (cyc==7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule diff --git a/test_regress/t/t_alw_reorder.v b/test_regress/t/t_alw_reorder.v deleted file mode 100644 index 2501945fe..000000000 --- a/test_regress/t/t_alw_reorder.v +++ /dev/null @@ -1,56 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - - reg [15:0] m_din; - - reg [15:0] v1; - reg [15:0] v2; - reg [15:0] v3; - integer nosplit; - - always @ (posedge clk) begin - // write needed so that V3Dead doesn't kill v0..v3 - $write(" values %x %x %x\n", v1, v2, v3); - - // Locally-set 'nosplit' will prevent the if from splitting - // in splitAlwaysAll(). This whole always block should still be - // intact when we call splitReorderAll() which is the subject - // of this test. - nosplit = cyc; - if (nosplit > 2) begin - /* S1 */ v1 <= 16'h0; - /* S2 */ v1 <= m_din; - /* S3 */ if (m_din == 16'h0) begin - /* X1 */ v2 <= v1; - /* X2 */ v3 <= v2; - end - end - - // We expect to swap S2 and S3, and to swap X1 and X2. - // We can check that this worked by the absense of dly vars - // in the generated output; if the reorder fails (or is disabled) - // we should see dly vars for v1 and v2. - end - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end - -endmodule diff --git a/test_regress/t/t_alw_split.v b/test_regress/t/t_alw_split.v deleted file mode 100644 index 52f52daa6..000000000 --- a/test_regress/t/t_alw_split.v +++ /dev/null @@ -1,94 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - - reg [15:0] m_din; - - // We expect all these blocks should split; - // blocks that don't split should go in t_alw_nosplit.v - - reg [15:0] a_split_1, a_split_2; - always @ (/*AS*/m_din) begin - a_split_1 = m_din; - a_split_2 = m_din; - end - - reg [15:0] d_split_1, d_split_2; - always @ (posedge clk) begin - d_split_1 <= m_din; - d_split_2 <= d_split_1; - d_split_1 <= ~m_din; - end - - reg [15:0] h_split_1; - reg [15:0] h_split_2; - always @ (posedge clk) begin -// $write(" cyc = %x m_din = %x\n", cyc, m_din); - if (cyc > 2) begin - if (m_din == 16'h0) begin - h_split_1 <= 16'h0; - h_split_2 <= 16'h0; - end - else begin - h_split_1 <= m_din; - h_split_2 <= ~m_din; - end - end - else begin - h_split_1 <= 16'h0; - h_split_2 <= 16'h0; - end - end - - reg [15:0] l_split_1, l_split_2; - always @ (posedge clk) begin - l_split_2 <= l_split_1; - l_split_1 <= l_split_2 | m_din; - end - - // (The checker block is an exception, it won't split.) - always @ (posedge clk) begin - if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - m_din <= 16'hfeed; - end - if (cyc==3) begin - end - if (cyc==4) begin - m_din <= 16'he11e; - //$write(" A %x %x\n", a_split_1, a_split_2); - if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; - if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; - end - if (cyc==5) begin - m_din <= 16'he22e; - if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; - if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; - end - if (cyc==6) begin - m_din <= 16'he33e; - if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop; - if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; - if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop; - end - if (cyc==7) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end // always @ (posedge clk) - -endmodule diff --git a/test_regress/t/t_alw_split_cond.py b/test_regress/t/t_alw_split_cond.py deleted file mode 100755 index c3bd7274f..000000000 --- a/test_regress/t/t_alw_split_cond.py +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile() - -test.passes() diff --git a/test_regress/t/t_alw_split_cond.v b/test_regress/t/t_alw_split_cond.v deleted file mode 100644 index e1af8f173..000000000 --- a/test_regress/t/t_alw_split_cond.v +++ /dev/null @@ -1,64 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -//bug1604 -module t (/*AUTOARG*/ - // Outputs - two, - // Inputs - clk, aresetn, ten - ); - - input wire clk; - input wire aresetn; - - input reg [9:0] ten; - output reg [1:0] two; - - // Passes with this - //output reg [1:0] rx; - //output reg [1:0] ry; - - function [1:0] func - ( - input [1:0] p0_x, - input [1:0] p0_y, - input [1:0] p1_x, - input [1:0] p1_y, - input [1:0] sel); - - reg [1:0] rx; - reg [1:0] ry; - -`ifdef NOT_DEF - // This way works - rx = sel == 2'b10 ? p1_x : p0_x; - ry = sel == 2'b10 ? p1_y : p0_y; -`else - // This way fails to compile - if (sel == 2'b10) begin - rx = p1_x; - ry = p1_y; - end - else begin - rx = p0_x; - ry = p0_y; - end -`endif - // Note rx and ry are unused - //func = rx | ry; // Also passes - func = 0; - endfunction - - always @(*) begin - two = func( - ten[8 +: 2], - ten[6 +: 2], - ten[4 +: 2], - ten[2 +: 2], - ten[0 +: 2]); - end -endmodule diff --git a/test_regress/t/t_alw_split_rst.v b/test_regress/t/t_alw_split_rst.v deleted file mode 100644 index b72d32c93..000000000 --- a/test_regress/t/t_alw_split_rst.v +++ /dev/null @@ -1,159 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - - -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; - - // Take CRC data and apply to testblock inputs - wire [3:0] in = crc[3:0]; - wire clken = crc[4]; - wire rstn = !(cyc < 20 || (crc[11:8]==0)); - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [3:0] ff_out; // From test of Test.v - wire [3:0] fg_out; // From test of Test.v - wire [3:0] fh_out; // From test of Test.v - // End of automatics - - Test test (/*AUTOINST*/ - // Outputs - .ff_out (ff_out[3:0]), - .fg_out (fg_out[3:0]), - .fh_out (fh_out[3:0]), - // Inputs - .clk (clk), - .clken (clken), - .rstn (rstn), - .in (in[3:0])); - - // Aggregate outputs into a single result vector - wire [63:0] result = {52'h0, ff_out, fg_out, fh_out}; - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x rstn=%x\n", $time, cyc, crc, result, rstn); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h77979747fd86e9fd - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - - -module Test - (/*AUTOARG*/ - // Outputs - ff_out, fg_out, fh_out, - // Inputs - clk, clken, rstn, in - ); - - input clk; - input clken; - input rstn; - - input [3:0] in; - - output reg [3:0] ff_out; - reg [3:0] ff_10; - reg [3:0] ff_11; - reg [3:0] ff_12; - reg [3:0] ff_13; - always @(posedge clk) begin - if ((rstn == 0)) begin - ff_10 <= 0; - ff_11 <= 0; - ff_12 <= 0; - ff_13 <= 0; - ff_out <= 0; - end - else begin - ff_10 <= in; - ff_11 <= ff_10; - ff_12 <= ff_11; - ff_13 <= ff_12; - ff_out <= ff_13; - end - end - - output reg [3:0] fg_out; - reg [3:0] fg_10; - reg [3:0] fg_11; - reg [3:0] fg_12; - reg [3:0] fg_13; - always @(posedge clk) begin - if (clken) begin - if ((rstn == 0)) begin - fg_10 <= 0; - fg_11 <= 0; - fg_12 <= 0; - fg_13 <= 0; - fg_out <= 0; - end - else begin - fg_10 <= in; - fg_11 <= fg_10; - fg_12 <= fg_11; - fg_13 <= fg_12; - fg_out <= fg_13; - end - end - end - - output reg [3:0] fh_out; - reg [3:0] fh_10; - reg [3:0] fh_11; - reg [3:0] fh_12; - reg [3:0] fh_13; - always @(posedge clk) begin - if ((rstn == 0)) begin - fh_10 <= 0; - fh_11 <= 0; - fh_12 <= 0; - fh_13 <= 0; - fh_out <= 0; - end - else begin - if (clken) begin - fh_10 <= in; - fh_11 <= fh_10; - fh_12 <= fh_11; - fh_13[3:1] <= fh_12[3:1]; - fh_13[0] <= fh_12[0]; - fh_out <= fh_13; - end - end - end - - -endmodule diff --git a/test_regress/t/t_alw_splitord.v b/test_regress/t/t_alw_splitord.v deleted file mode 100644 index 98f15f2b8..000000000 --- a/test_regress/t/t_alw_splitord.v +++ /dev/null @@ -1,152 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - - reg [15:0] m_din; - - // OK - reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5; - always @ (posedge clk) begin - if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - c_split_1 <= 16'h0; - c_split_2 <= 16'h0; - c_split_3 <= 16'h0; - c_split_4 <= 0; - c_split_5 <= 0; - // End of automatics - end - else begin - c_split_1 <= m_din; - c_split_2 <= c_split_1; - c_split_3 <= c_split_2 & {16{(cyc!=0)}}; - if (cyc==1) begin - c_split_4 <= 16'h4; - c_split_5 <= 16'h5; - end - else begin - c_split_4 <= c_split_3; - c_split_5 <= c_split_4; - end - end - end - - // OK - reg [15:0] d_split_1, d_split_2; - always @ (posedge clk) begin - if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - d_split_1 <= 16'h0; - d_split_2 <= 16'h0; - // End of automatics - end - else begin - d_split_1 <= m_din; - d_split_2 <= d_split_1; - d_split_1 <= ~m_din; - end - end - - // Not OK - always @ (posedge clk) begin - if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - // End of automatics - end - else begin - $write(" foo %x", m_din); - $write(" bar %x\n", m_din); - end - end - - // Not OK - reg [15:0] e_split_1, e_split_2; - always @ (posedge clk) begin - if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - e_split_1 = 16'h0; - e_split_2 = 16'h0; - // End of automatics - end - else begin - e_split_1 = m_din; - e_split_2 = e_split_1; - end - end - - // Not OK - reg [15:0] f_split_1, f_split_2; - always @ (posedge clk) begin - if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - f_split_1 = 16'h0; - f_split_2 = 16'h0; - // End of automatics - end - else begin - f_split_2 = f_split_1; - f_split_1 = m_din; - end - end - - always @ (posedge clk) begin - if (cyc!=0) begin - //$write(" C %d %x %x\n", cyc, c_split_1, c_split_2); - cyc<=cyc+1; - if (cyc==1) begin - m_din <= 16'hfeed; - end - if (cyc==3) begin - end - if (cyc==4) begin - m_din <= 16'he11e; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; - if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; - if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; - end - if (cyc==5) begin - m_din <= 16'he22e; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; - // Two valid orderings, as we don't know which posedge clk gets evaled first - if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; - if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; - end - if (cyc==6) begin - m_din <= 16'he33e; - if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop; - if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; - // Two valid orderings, as we don't know which posedge clk gets evaled first - if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; - if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; - end - if (cyc==7) begin - m_din <= 16'he44e; - if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop; - end - if (cyc==8) begin - m_din <= 16'he55e; - if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e - && c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end -endmodule diff --git a/test_regress/t/t_always_chg_first.py b/test_regress/t/t_always_chg_first.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_always_chg_first.py +++ b/test_regress/t/t_always_chg_first.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_always_chg_first.v b/test_regress/t/t_always_chg_first.v index 4b43f5761..017b516d0 100644 --- a/test_regress/t/t_always_chg_first.v +++ b/test_regress/t/t_always_chg_first.v @@ -1,72 +1,77 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk, fastclk - ); +module t ( + input clk, + input fastclk +); - input clk; - input fastclk; // surefire lint_off_line UDDIXN + integer _mode; + initial _mode = 0; - integer _mode; initial _mode=0; + reg [31:0] ord1; + initial ord1 = 32'h1111; + wire [31:0] ord2; + reg [31:0] ord3; + wire [31:0] ord4; + wire [31:0] ord5; + wire [31:0] ord6; + wire [31:0] ord7; - reg [31:0] ord1; initial ord1 = 32'h1111; - wire [31:0] ord2; - reg [31:0] ord3; - wire [31:0] ord4; - wire [31:0] ord5; - wire [31:0] ord6; - wire [31:0] ord7; + // verilator lint_off UNOPT + t_chg_a a ( + .a(ord1), + .a_p1(ord2), + .b(ord4), + .b_p1(ord5), + .c(ord3), + .c_p1(ord4), + .d(ord6), + .d_p1(ord7) + ); - // verilator lint_off UNOPT - t_chg_a a ( - .a(ord1), .a_p1(ord2), - .b(ord4), .b_p1(ord5), - .c(ord3), .c_p1(ord4), - .d(ord6), .d_p1(ord7) - ); + // surefire lint_off ASWEMB + assign ord6 = ord5 + 1; + // verilator lint_on UNOPT - // surefire lint_off ASWEMB - assign ord6 = ord5 + 1; - // verilator lint_on UNOPT + always @( /*AS*/ord2) ord3 = ord2 + 1; - always @ (/*AS*/ord2) ord3 = ord2 + 1; + always @(fastclk) begin // surefire lint_off_line ALWLTR ALWMTR + if (_mode == 1) begin + //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); + //if (ord2 == 2 && ord7 != 7) $stop; + end + end - always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR - if (_mode==1) begin - //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); - //if (ord2 == 2 && ord7 != 7) $stop; - end - end - - always @ (posedge clk) begin - if (_mode==0) begin - $write("[%0t] t_chg: Running\n", $time); - _mode<=1; - ord1 <= 1; - end - else if (_mode==1) begin - _mode<=2; - if (ord7 !== 7) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (_mode == 0) begin + $write("[%0t] t_chg: Running\n", $time); + _mode <= 1; + ord1 <= 1; + end + else if (_mode == 1) begin + _mode <= 2; + if (ord7 !== 7) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module t_chg_a (/*AUTOARG*/ - // Outputs - a_p1, b_p1, c_p1, d_p1, - // Inputs - a, b, c, d - ); - input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1; - input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1; - input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1; - input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1; +module t_chg_a ( /*AUTOARG*/ + // Outputs + a_p1, b_p1, c_p1, d_p1, + // Inputs + a, b, c, d + ); + // verilog_format: off + input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1; + input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1; + input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1; + input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1; + // verilog_format: on endmodule diff --git a/test_regress/t/t_class_param_extends_static_member_function_access.py b/test_regress/t/t_always_combdly.py similarity index 50% rename from test_regress/t/t_class_param_extends_static_member_function_access.py rename to test_regress/t/t_always_combdly.py index f989a35fb..3cc73805c 100755 --- a/test_regress/t/t_class_param_extends_static_member_function_access.py +++ b/test_regress/t/t_always_combdly.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_always_combdly.v b/test_regress/t/t_always_combdly.v new file mode 100644 index 000000000..8e8cfb4cb --- /dev/null +++ b/test_regress/t/t_always_combdly.v @@ -0,0 +1,63 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk +); + + integer cyc; + initial cyc = 1; + + reg [31:0] a, b, c, d, e, f, g, h; + + always @(*) begin // Test Verilog 2001 (*) + // verilator lint_off COMBDLY + c <= a | b; + // verilator lint_on COMBDLY + end + + always @(posedge (clk)) begin // always bug 2008/4/18 + d <= a | b; + end + always @((d)) begin // always bug 2008/4/18 + e = d; + end + + parameter CONSTANT = 1; + always @(e, 1'b0, CONSTANT) begin // not technically legal, see bug412 + f = e; + end + always @(1'b0, CONSTANT, f) begin // not technically legal, see bug412 + g = f; + end + always @({CONSTANT, + g + }) + begin // bug745 + h = g; + end + //always @ ((posedge b) or (a or b)) begin // note both illegal + + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + a <= 32'hfeed0000; + b <= 32'h0000face; + end + if (cyc == 2) begin + if (c != 32'hfeedface) $stop; + end + if (cyc == 3) begin + if (h != 32'hfeedface) $stop; + end + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test_regress/t/t_alw_combdly.py b/test_regress/t/t_always_dly.py similarity index 50% rename from test_regress/t/t_alw_combdly.py rename to test_regress/t/t_always_dly.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_alw_combdly.py +++ b/test_regress/t/t_always_dly.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_always_dly.v b/test_regress/t/t_always_dly.v new file mode 100644 index 000000000..a63120bc5 --- /dev/null +++ b/test_regress/t/t_always_dly.v @@ -0,0 +1,63 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk +); + + integer cyc; + initial cyc = 1; + + reg posedge_wr_clocks; + reg prev_wr_clocks; + reg [31:0] m_din; + reg [31:0] m_dout; + + always @(negedge clk) begin + prev_wr_clocks = 0; + end + + reg comb_pos_1; + reg comb_prev_1; + always @( /*AS*/ clk or posedge_wr_clocks or prev_wr_clocks) begin + comb_pos_1 = (clk & ~prev_wr_clocks); + comb_prev_1 = comb_pos_1 | posedge_wr_clocks; + comb_pos_1 = 1'b1; + end + + always @(posedge clk) begin + posedge_wr_clocks = (clk & ~prev_wr_clocks); //surefire lint_off_line SEQASS + prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS + if (posedge_wr_clocks) begin + //$write("[%0t] Wrclk\n", $time); + m_dout <= m_din; + end + end + + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + $write(" %x\n", comb_pos_1); + m_din <= 32'hfeed; + end + if (cyc == 2) begin + $write(" %x\n", comb_pos_1); + m_din <= 32'he11e; + end + if (cyc == 3) begin + m_din <= 32'he22e; + $write(" %x\n", comb_pos_1); + if (m_dout != 32'hfeed) $stop; + end + if (cyc == 4) begin + if (m_dout != 32'he11e) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test_regress/t/t_always_ff_never.py b/test_regress/t/t_always_ff_never.py index dbdaf4551..1a93d5310 100755 --- a/test_regress/t/t_always_ff_never.py +++ b/test_regress/t/t_always_ff_never.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_always_ff_never.v b/test_regress/t/t_always_ff_never.v index a00f0f576..1acf09d06 100644 --- a/test_regress/t/t_always_ff_never.v +++ b/test_regress/t/t_always_ff_never.v @@ -1,40 +1,42 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -interface intf - (input wire clk /*verilator public*/ ); +interface intf ( + input wire clk /*verilator public*/ +); endinterface module sub ( input wire clk, input wire dat ); - intf the_intf (.clk); + intf the_intf (.clk); - logic [63:0] last_transition = 123; - always_ff @(edge dat) begin - last_transition <= $time; - end + logic [63:0] last_transition = 123; + always_ff @(edge dat) begin + last_transition <= $time; + end - int cyc = 0; - always_ff @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 2) begin - if (last_transition != 123) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + int cyc = 0; + always_ff @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 2) begin + if (last_transition != 123) $stop; + $write("*-* All Finished *-*\n"); + $finish; end + end endmodule -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - sub the_sub (.clk, .dat ('0)); + sub the_sub ( + .clk, + .dat('0) + ); endmodule diff --git a/test_regress/t/t_alw_noreorder.py b/test_regress/t/t_always_noreorder.py similarity index 71% rename from test_regress/t/t_alw_noreorder.py rename to test_regress/t/t_always_noreorder.py index a64bbc380..4d5095754 100755 --- a/test_regress/t/t_alw_noreorder.py +++ b/test_regress/t/t_always_noreorder.py @@ -1,16 +1,16 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') -test.top_filename = "t/t_alw_reorder.v" +test.top_filename = "t/t_always_reorder.v" test.compile(verilator_flags2=["--stats -fno-reorder"]) test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0) diff --git a/test_regress/t/t_alw_nosplit.py b/test_regress/t/t_always_nosplit.py similarity index 60% rename from test_regress/t/t_alw_nosplit.py rename to test_regress/t/t_always_nosplit.py index e719df544..d33d40f72 100755 --- a/test_regress/t/t_alw_nosplit.py +++ b/test_regress/t/t_always_nosplit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_always_nosplit.v b/test_regress/t/t_always_nosplit.v new file mode 100644 index 000000000..467fad89e --- /dev/null +++ b/test_regress/t/t_always_nosplit.v @@ -0,0 +1,149 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk +); + + integer cyc; + initial cyc = 1; + + reg [15:0] m_din; + + // We expect none of these blocks to split. + // Blocks that can split should go in t_alw_split.v instead. + + reg [15:0] b_split_1, b_split_2; + always @( /*AS*/ m_din) begin + b_split_1 = m_din; + b_split_2 = b_split_1; + end + + reg [15:0] c_split_1, c_split_2; + always @( /*AS*/ m_din) begin + c_split_1 = m_din; + c_split_2 = c_split_1; + c_split_1 = ~m_din; + end + + always @(posedge clk) begin + $write(" foo %x", m_din); + $write(" bar %x\n", m_din); + end + + reg [15:0] e_split_1, e_split_2; + always @(posedge clk) begin + e_split_1 = m_din; + e_split_2 = e_split_1; + end + + reg [15:0] f_split_1, f_split_2; + always @(posedge clk) begin + f_split_2 = f_split_1; + f_split_1 = m_din; + end + + function logic [15:0] sideeffect_func(logic [15:0] v); + /*verilator no_inline_task */ + $display(" sideeffect_func() is called %t", $time); + return ~v; + endfunction + reg [15:0] m_split_1 = 0; + reg [15:0] m_split_2 = 0; + always @(posedge clk) begin + if (sideeffect_func(m_split_1) != 16'b0) begin + m_split_1 <= m_din; + end + else begin + m_split_2 <= m_din; + end + end + + + reg [15:0] z_split_1, z_split_2; + always @(posedge clk) begin + z_split_1 <= 0; + z_split_1 <= ~m_din; + end + always @(posedge clk) begin + z_split_2 <= 0; + z_split_2 <= z_split_1; + end + + reg [15:0] h_split_1; + reg [15:0] h_split_2; + reg [15:0] h_foo; + always @(posedge clk) begin + // $write(" cyc = %x m_din = %x\n", cyc, m_din); + h_foo = m_din; + if (cyc > 2) begin + // This conditional depends on non-primary-input foo. + // Its dependency on foo should not be pruned. As a result, + // the dependencies of h_split_1 and h_split_2 on this + // conditional will also not be pruned, making them all + // weakly connected such that they'll end up in the same graph + // and we can't split. + if (h_foo == 16'h0) begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + else begin + h_split_1 <= m_din; + h_split_2 <= ~m_din; + end + end + else begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + end // always @ (posedge clk) + + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + end + if (cyc == 1) begin + m_din <= 16'hfeed; + end + if (cyc == 4) begin + m_din <= 16'he11e; + if (!(b_split_1 == 16'hfeed && b_split_2 == 16'hfeed)) $stop; + if (!(c_split_1 == 16'h0112 && c_split_2 == 16'hfeed)) $stop; + if (!(e_split_1 == 16'hfeed && e_split_2 == 16'hfeed)) $stop; + if (!(f_split_1 == 16'hfeed && f_split_2 == 16'hfeed)) $stop; + if (!(m_split_1 == 16'hfeed && m_split_2 == 16'h0000)) $stop; + if (!(z_split_1 == 16'h0112 && z_split_2 == 16'h0112)) $stop; + end + if (cyc == 5) begin + m_din <= 16'he22e; + if (!(b_split_1 == 16'he11e && b_split_2 == 16'he11e)) $stop; + if (!(c_split_1 == 16'h1ee1 && c_split_2 == 16'he11e)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) + $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) + $stop; + if (!(m_split_1 == 16'hfeed && m_split_2 == 16'h0000)) $stop; + if (!(z_split_1 == 16'h0112 && z_split_2 == 16'h0112)) $stop; + end + if (cyc == 6) begin + m_din <= 16'he33e; + if (!(b_split_1 == 16'he22e && b_split_2 == 16'he22e)) $stop; + if (!(c_split_1 == 16'h1dd1 && c_split_2 == 16'he22e)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) + $stop; + if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) + $stop; + if (!(m_split_1 == 16'he11e && m_split_2 == 16'h0000)) $stop; + if (!(z_split_1 == 16'h1ee1 && z_split_2 == 16'h0112)) $stop; + end + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_alw_reorder.py b/test_regress/t/t_always_reorder.py similarity index 78% rename from test_regress/t/t_alw_reorder.py rename to test_regress/t/t_always_reorder.py index d61a33150..c995999c0 100755 --- a/test_regress/t/t_alw_reorder.py +++ b/test_regress/t/t_always_reorder.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_always_reorder.v b/test_regress/t/t_always_reorder.v new file mode 100644 index 000000000..f5ca037b8 --- /dev/null +++ b/test_regress/t/t_always_reorder.v @@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk +); + + integer cyc; + initial cyc = 1; + + reg [15:0] m_din; + + reg [15:0] v1; + reg [15:0] v2; + reg [15:0] v3; + integer nosplit; + + always @(posedge clk) begin + // write needed so that V3Dead doesn't kill v0..v3 + $write(" values %x %x %x\n", v1, v2, v3); + + // Locally-set 'nosplit' will prevent the if from splitting + // in splitAlwaysAll(). This whole always block should still be + // intact when we call splitReorderAll() which is the subject + // of this test. + nosplit = cyc; + if (nosplit > 2) begin + /* S1 */ v1 <= 16'h0; + /* S2 */ v1 <= m_din; + /* S3 */ if (m_din == 16'h0) begin + /* X1 */ v2 <= v1; + /* X2 */ v3 <= v2; + end + end + + // We expect to swap S2 and S3, and to swap X1 and X2. + // We can check that this worked by the absense of dly vars + // in the generated output; if the reorder fails (or is disabled) + // we should see dly vars for v1 and v2. + end + + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/test_regress/t/t_alw_reorder_inlined_func.py b/test_regress/t/t_always_reorder_inlined_func.py similarity index 53% rename from test_regress/t/t_alw_reorder_inlined_func.py rename to test_regress/t/t_always_reorder_inlined_func.py index f67fb32be..692e056be 100755 --- a/test_regress/t/t_alw_reorder_inlined_func.py +++ b/test_regress/t/t_always_reorder_inlined_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alw_reorder_inlined_func.v b/test_regress/t/t_always_reorder_inlined_func.v similarity index 95% rename from test_regress/t/t_alw_reorder_inlined_func.v rename to test_regress/t/t_always_reorder_inlined_func.v index 512fb2ebf..8040a4282 100644 --- a/test_regress/t/t_alw_reorder_inlined_func.v +++ b/test_regress/t/t_always_reorder_inlined_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_alw_reorder_no_acycsimp.py b/test_regress/t/t_always_reorder_no_acycsimp.py similarity index 50% rename from test_regress/t/t_alw_reorder_no_acycsimp.py rename to test_regress/t/t_always_reorder_no_acycsimp.py index 2b1eb20e1..50df28735 100755 --- a/test_regress/t/t_alw_reorder_no_acycsimp.py +++ b/test_regress/t/t_always_reorder_no_acycsimp.py @@ -1,16 +1,16 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt_all') -test.top_filename = 't/t_alw_reorder.v' +test.top_filename = 't/t_always_reorder.v' test.compile(verilator_flags2=["--stats", "-fno-acyc-simp"]) diff --git a/test_regress/t/t_alw_sen_compare.py b/test_regress/t/t_always_sen_compare.py similarity index 52% rename from test_regress/t/t_alw_sen_compare.py rename to test_regress/t/t_always_sen_compare.py index 2e9528d96..4f63b3a84 100755 --- a/test_regress/t/t_alw_sen_compare.py +++ b/test_regress/t/t_always_sen_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_alw_sen_compare.v b/test_regress/t/t_always_sen_compare.v similarity index 85% rename from test_regress/t/t_alw_sen_compare.v rename to test_regress/t/t_always_sen_compare.v index 16f121f2d..0de72b771 100644 --- a/test_regress/t/t_alw_sen_compare.v +++ b/test_regress/t/t_always_sen_compare.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module top; diff --git a/test_regress/t/t_alw_split.py b/test_regress/t/t_always_split.py similarity index 60% rename from test_regress/t/t_alw_split.py rename to test_regress/t/t_always_split.py index 08fff24cc..f5ececdbb 100755 --- a/test_regress/t/t_alw_split.py +++ b/test_regress/t/t_always_split.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_always_split.v b/test_regress/t/t_always_split.v new file mode 100644 index 000000000..057538c52 --- /dev/null +++ b/test_regress/t/t_always_split.v @@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk +); + + integer cyc; + initial cyc = 1; + + reg [15:0] m_din; + + // We expect all these blocks should split; + // blocks that don't split should go in t_alw_nosplit.v + + reg [15:0] a_split_1, a_split_2; + always @( /*AS*/ m_din) begin + a_split_1 = m_din; + a_split_2 = m_din; + end + + reg [15:0] d_split_1, d_split_2; + always @(posedge clk) begin + d_split_1 <= m_din; + d_split_2 <= d_split_1; + d_split_1 <= ~m_din; + end + + reg [15:0] h_split_1; + reg [15:0] h_split_2; + always @(posedge clk) begin + // $write(" cyc = %x m_din = %x\n", cyc, m_din); + if (cyc > 2) begin + if (m_din == 16'h0) begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + else begin + h_split_1 <= m_din; + h_split_2 <= ~m_din; + end + end + else begin + h_split_1 <= 16'h0; + h_split_2 <= 16'h0; + end + end + + reg [15:0] l_split_1, l_split_2; + always @(posedge clk) begin + l_split_2 <= l_split_1; + l_split_1 <= l_split_2 | m_din; + end + + // (The checker block is an exception, it won't split.) + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 1) begin + m_din <= 16'hfeed; + end + if (cyc == 3) begin + end + if (cyc == 4) begin + m_din <= 16'he11e; + //$write(" A %x %x\n", a_split_1, a_split_2); + if (!(a_split_1 == 16'hfeed && a_split_2 == 16'hfeed)) $stop; + if (!(d_split_1 == 16'h0112 && d_split_2 == 16'h0112)) $stop; + if (!(h_split_1 == 16'hfeed && h_split_2 == 16'h0112)) $stop; + end + if (cyc == 5) begin + m_din <= 16'he22e; + if (!(a_split_1 == 16'he11e && a_split_2 == 16'he11e)) $stop; + if (!(d_split_1 == 16'h0112 && d_split_2 == 16'h0112)) $stop; + if (!(h_split_1 == 16'hfeed && h_split_2 == 16'h0112)) $stop; + end + if (cyc == 6) begin + m_din <= 16'he33e; + if (!(a_split_1 == 16'he22e && a_split_2 == 16'he22e)) $stop; + if (!(d_split_1 == 16'h1ee1 && d_split_2 == 16'h0112)) $stop; + if (!(h_split_1 == 16'he11e && h_split_2 == 16'h1ee1)) $stop; + end + if (cyc == 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end // always @ (posedge clk) + +endmodule diff --git a/test_regress/t/t_always_split_cond.py b/test_regress/t/t_always_split_cond.py new file mode 100755 index 000000000..66009b455 --- /dev/null +++ b/test_regress/t/t_always_split_cond.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.passes() diff --git a/test_regress/t/t_always_split_cond.v b/test_regress/t/t_always_split_cond.v new file mode 100644 index 000000000..fd714026b --- /dev/null +++ b/test_regress/t/t_always_split_cond.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +//bug1604 +module t ( /*AUTOARG*/ + // Outputs + two, + // Inputs + clk, + aresetn, + ten +); + + input wire clk; + input wire aresetn; + + input reg [9:0] ten; + output reg [1:0] two; + + // Passes with this + //output reg [1:0] rx; + //output reg [1:0] ry; + + function [1:0] func(input [1:0] p0_x, input [1:0] p0_y, input [1:0] p1_x, input [1:0] p1_y, + input [1:0] sel); + + reg [1:0] rx; + reg [1:0] ry; + +`ifdef NOT_DEF + // This way works + rx = sel == 2'b10 ? p1_x : p0_x; + ry = sel == 2'b10 ? p1_y : p0_y; +`else + // This way fails to compile + if (sel == 2'b10) begin + rx = p1_x; + ry = p1_y; + end + else begin + rx = p0_x; + ry = p0_y; + end +`endif + // Note rx and ry are unused + //func = rx | ry; // Also passes + func = 0; + endfunction + + always @(*) begin + two = func(ten[8+:2], ten[6+:2], ten[4+:2], ten[2+:2], ten[0+:2]); + end +endmodule diff --git a/test_regress/t/t_alw_split_rst.py b/test_regress/t/t_always_split_rst.py similarity index 62% rename from test_regress/t/t_alw_split_rst.py rename to test_regress/t/t_always_split_rst.py index f801e0883..5afd83272 100755 --- a/test_regress/t/t_alw_split_rst.py +++ b/test_regress/t/t_always_split_rst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_always_split_rst.v b/test_regress/t/t_always_split_rst.v new file mode 100644 index 000000000..76af52866 --- /dev/null +++ b/test_regress/t/t_always_split_rst.v @@ -0,0 +1,156 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + + +module t ( + input clk +); + + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [3:0] in = crc[3:0]; + wire clken = crc[4]; + wire rstn = !(cyc < 20 || (crc[11:8] == 0)); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] ff_out; // From test of Test.v + wire [3:0] fg_out; // From test of Test.v + wire [3:0] fh_out; // From test of Test.v + // End of automatics + + Test test ( /*AUTOINST*/ + // Outputs + .ff_out (ff_out[3:0]), + .fg_out (fg_out[3:0]), + .fh_out (fh_out[3:0]), + // Inputs + .clk (clk), + .clken (clken), + .rstn (rstn), + .in (in[3:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {52'h0, ff_out, fg_out, fh_out}; + + // Test loop + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x rstn=%x\n", $time, cyc, crc, result, rstn); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h77979747fd86e9fd + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module Test ( /*AUTOARG*/ + // Outputs + ff_out, fg_out, fh_out, + // Inputs + clk, clken, rstn, in + ); + + input clk; + input clken; + input rstn; + + input [3:0] in; + + output reg [3:0] ff_out; + reg [3:0] ff_10; + reg [3:0] ff_11; + reg [3:0] ff_12; + reg [3:0] ff_13; + always @(posedge clk) begin + if ((rstn == 0)) begin + ff_10 <= 0; + ff_11 <= 0; + ff_12 <= 0; + ff_13 <= 0; + ff_out <= 0; + end + else begin + ff_10 <= in; + ff_11 <= ff_10; + ff_12 <= ff_11; + ff_13 <= ff_12; + ff_out <= ff_13; + end + end + + output reg [3:0] fg_out; + reg [3:0] fg_10; + reg [3:0] fg_11; + reg [3:0] fg_12; + reg [3:0] fg_13; + always @(posedge clk) begin + if (clken) begin + if ((rstn == 0)) begin + fg_10 <= 0; + fg_11 <= 0; + fg_12 <= 0; + fg_13 <= 0; + fg_out <= 0; + end + else begin + fg_10 <= in; + fg_11 <= fg_10; + fg_12 <= fg_11; + fg_13 <= fg_12; + fg_out <= fg_13; + end + end + end + + output reg [3:0] fh_out; + reg [3:0] fh_10; + reg [3:0] fh_11; + reg [3:0] fh_12; + reg [3:0] fh_13; + always @(posedge clk) begin + if ((rstn == 0)) begin + fh_10 <= 0; + fh_11 <= 0; + fh_12 <= 0; + fh_13 <= 0; + fh_out <= 0; + end + else begin + if (clken) begin + fh_10 <= in; + fh_11 <= fh_10; + fh_12 <= fh_11; + fh_13[3:1] <= fh_12[3:1]; + fh_13[0] <= fh_12[0]; + fh_out <= fh_13; + end + end + end + + +endmodule diff --git a/test_regress/t/t_alw_splitord.py b/test_regress/t/t_always_splitord.py similarity index 60% rename from test_regress/t/t_alw_splitord.py rename to test_regress/t/t_always_splitord.py index 0324c5dd2..d133a773e 100755 --- a/test_regress/t/t_alw_splitord.py +++ b/test_regress/t/t_always_splitord.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_always_splitord.v b/test_regress/t/t_always_splitord.v new file mode 100644 index 000000000..6730cb4c6 --- /dev/null +++ b/test_regress/t/t_always_splitord.v @@ -0,0 +1,156 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk +); + + integer cyc; + initial cyc = 1; + + reg [15:0] m_din; + + // OK + reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5; + always @(posedge clk) begin + if (cyc == 0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + c_split_1 <= 16'h0; + c_split_2 <= 16'h0; + c_split_3 <= 16'h0; + c_split_4 <= 0; + c_split_5 <= 0; + // End of automatics + end + else begin + c_split_1 <= m_din; + c_split_2 <= c_split_1; + c_split_3 <= c_split_2 & {16{(cyc != 0)}}; + if (cyc == 1) begin + c_split_4 <= 16'h4; + c_split_5 <= 16'h5; + end + else begin + c_split_4 <= c_split_3; + c_split_5 <= c_split_4; + end + end + end + + // OK + reg [15:0] d_split_1, d_split_2; + always @(posedge clk) begin + if (cyc == 0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + d_split_1 <= 16'h0; + d_split_2 <= 16'h0; + // End of automatics + end + else begin + d_split_1 <= m_din; + d_split_2 <= d_split_1; + d_split_1 <= ~m_din; + end + end + + // Not OK + always @(posedge clk) begin + if (cyc == 0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + // End of automatics + end + else begin + $write(" foo %x", m_din); + $write(" bar %x\n", m_din); + end + end + + // Not OK + reg [15:0] e_split_1, e_split_2; + always @(posedge clk) begin + if (cyc == 0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + e_split_1 = 16'h0; + e_split_2 = 16'h0; + // End of automatics + end + else begin + e_split_1 = m_din; + e_split_2 = e_split_1; + end + end + + // Not OK + reg [15:0] f_split_1, f_split_2; + always @(posedge clk) begin + if (cyc == 0) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + f_split_1 = 16'h0; + f_split_2 = 16'h0; + // End of automatics + end + else begin + f_split_2 = f_split_1; + f_split_1 = m_din; + end + end + + always @(posedge clk) begin + if (cyc != 0) begin + //$write(" C %d %x %x\n", cyc, c_split_1, c_split_2); + cyc <= cyc + 1; + if (cyc == 1) begin + m_din <= 16'hfeed; + end + if (cyc == 3) begin + end + if (cyc == 4) begin + m_din <= 16'he11e; + if (!(d_split_1 == 16'h0112 && d_split_2 == 16'h0112)) $stop; + if (!(e_split_1 == 16'hfeed && e_split_2 == 16'hfeed)) $stop; + if (!(f_split_1 == 16'hfeed && f_split_2 == 16'hfeed)) $stop; + end + if (cyc == 5) begin + m_din <= 16'he22e; + if (!(d_split_1 == 16'h0112 && d_split_2 == 16'h0112)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) + $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) + $stop; + end + if (cyc == 6) begin + m_din <= 16'he33e; + if (!(c_split_1 == 16'he11e && c_split_2 == 16'hfeed && c_split_3 == 16'hfeed)) $stop; + if (!(d_split_1 == 16'h1ee1 && d_split_2 == 16'h0112)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) + $stop; + if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) + $stop; + end + if (cyc == 7) begin + m_din <= 16'he44e; + if (!(c_split_1 == 16'he22e && c_split_2 == 16'he11e && c_split_3 == 16'hfeed)) $stop; + end + if (cyc == 8) begin + m_din <= 16'he55e; + if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e + && c_split_4==16'hfeed && c_split_5==16'hfeed)) + $stop; + end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule diff --git a/test_regress/t/t_array_backw_index_bad.py b/test_regress/t/t_array_backw_index_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_array_backw_index_bad.py +++ b/test_regress/t/t_array_backw_index_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_backw_index_bad.v b/test_regress/t/t_array_backw_index_bad.v index 266b45820..fddcfa3a0 100644 --- a/test_regress/t/t_array_backw_index_bad.v +++ b/test_regress/t/t_array_backw_index_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_array_compare.py b/test_regress/t/t_array_compare.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_compare.py +++ b/test_regress/t/t_array_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_compare.v b/test_regress/t/t_array_compare.v index fd893167b..e27d03a0f 100644 --- a/test_regress/t/t_array_compare.v +++ b/test_regress/t/t_array_compare.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Andrew Bardsley. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Andrew Bardsley // SPDX-License-Identifier: CC0-1.0 // bug1071 diff --git a/test_regress/t/t_array_event.py b/test_regress/t/t_array_event.py new file mode 100755 index 000000000..46d1fe4c0 --- /dev/null +++ b/test_regress/t/t_array_event.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_event.v b/test_regress/t/t_array_event.v new file mode 100644 index 000000000..c3bb7aa3e --- /dev/null +++ b/test_regress/t/t_array_event.v @@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +class Foo; + event write_events[int]; + + function void add_event(int index, event in); + write_events[index] = in; + endfunction + + task trigger_event(int index); + ->write_events[index]; + endtask + + function void delete_event(int index); + write_events.delete(index); + endfunction +endclass + +class Bar; + Foo foo; + event baz; + + function new(Foo foo); + this.foo = foo; + endfunction + + task go(); + foo.add_event(3, baz); + @baz; + $display("got here"); + foo.delete_event(3); + endtask +endclass + +module top; + Bar bar; + Foo foo; + + initial begin + foo = new(); + bar = new(foo); + bar.go(); + end + + initial begin + #10; + foo.trigger_event(3); + $finish; + end + +endmodule diff --git a/test_regress/t/t_array_in_struct.py b/test_regress/t/t_array_in_struct.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_in_struct.py +++ b/test_regress/t/t_array_in_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_in_struct.v b/test_regress/t/t_array_in_struct.v index 244ec4c4c..9c331c894 100644 --- a/test_regress/t/t_array_in_struct.v +++ b/test_regress/t/t_array_in_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug991 diff --git a/test_regress/t/t_array_index_increment.py b/test_regress/t/t_array_index_increment.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_index_increment.py +++ b/test_regress/t/t_array_index_increment.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_index_increment.v b/test_regress/t/t_array_index_increment.v index 4e9e24c88..b7588d035 100644 --- a/test_regress/t/t_array_index_increment.v +++ b/test_regress/t/t_array_index_increment.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_array_index_side.py b/test_regress/t/t_array_index_side.py index dbdaf4551..1a93d5310 100755 --- a/test_regress/t/t_array_index_side.py +++ b/test_regress/t/t_array_index_side.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_index_side.v b/test_regress/t/t_array_index_side.v index 1e2e1c151..5992f9898 100644 --- a/test_regress/t/t_array_index_side.v +++ b/test_regress/t/t_array_index_side.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_array_list_bad.py b/test_regress/t/t_array_list_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_array_list_bad.py +++ b/test_regress/t/t_array_list_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_list_bad.v b/test_regress/t/t_array_list_bad.v index b50e8531b..8841a602e 100644 --- a/test_regress/t/t_array_list_bad.v +++ b/test_regress/t/t_array_list_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_array_mda.py b/test_regress/t/t_array_mda.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_mda.py +++ b/test_regress/t/t_array_mda.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_mda.v b/test_regress/t/t_array_mda.v index c6105c7b4..bfa7116e9 100644 --- a/test_regress/t/t_array_mda.v +++ b/test_regress/t/t_array_mda.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_array_method.py b/test_regress/t/t_array_method.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_method.py +++ b/test_regress/t/t_array_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_method.v b/test_regress/t/t_array_method.v index 4f5021dad..186046820 100644 --- a/test_regress/t/t_array_method.v +++ b/test_regress/t/t_array_method.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_array_method_bad.py b/test_regress/t/t_array_method_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_array_method_bad.py +++ b/test_regress/t/t_array_method_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_method_bad.v b/test_regress/t/t_array_method_bad.v index ed8a07cde..5f8250831 100644 --- a/test_regress/t/t_array_method_bad.v +++ b/test_regress/t/t_array_method_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_array_method_map.py b/test_regress/t/t_array_method_map.py index 966dc53da..20b96a7d7 100755 --- a/test_regress/t/t_array_method_map.py +++ b/test_regress/t/t_array_method_map.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_method_map.v b/test_regress/t/t_array_method_map.v index 7fda8036d..8025971f7 100644 --- a/test_regress/t/t_array_method_map.v +++ b/test_regress/t/t_array_method_map.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off @@ -12,8 +12,8 @@ module t; initial begin - int res[]; - int a[3] = '{100, 200, 300}; + automatic int res[]; + automatic int a[3] = '{100, 200, 300}; // TODO results not known to be correct res = a.map(el) with (el == 200); diff --git a/test_regress/t/t_array_non_blocking_loop.py b/test_regress/t/t_array_non_blocking_loop.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_non_blocking_loop.py +++ b/test_regress/t/t_array_non_blocking_loop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_non_blocking_loop.v b/test_regress/t/t_array_non_blocking_loop.v index 5c1f488df..f7bab41db 100644 --- a/test_regress/t/t_array_non_blocking_loop.v +++ b/test_regress/t/t_array_non_blocking_loop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_array_packed_endian.py b/test_regress/t/t_array_packed_endian.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_packed_endian.py +++ b/test_regress/t/t_array_packed_endian.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_packed_endian.v b/test_regress/t/t_array_packed_endian.v index a0f3300ff..43787bd2a 100644 --- a/test_regress/t/t_array_packed_endian.v +++ b/test_regress/t/t_array_packed_endian.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Wilson Snyder. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_alw_dly.py b/test_regress/t/t_array_packed_sign.py similarity index 50% rename from test_regress/t/t_alw_dly.py rename to test_regress/t/t_array_packed_sign.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_alw_dly.py +++ b/test_regress/t/t_array_packed_sign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_packed_sign.v b/test_regress/t/t_array_packed_sign.v new file mode 100644 index 000000000..0f39b5505 --- /dev/null +++ b/test_regress/t/t_array_packed_sign.v @@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Yutetsu TAKATSUKASA +// SPDX-License-Identifier: CC0-1.0 + +// Test to check whether the following spec is properly implemented. +// In IEEE 1800-2023 7.4.1 Packed arrays: +// If a packed array is declared as signed, then the array viewed as a single +// vector shall be signed. The individual elements of the array are unsigned +// unless they are of a named type declared as signed. + +module t; + typedef logic signed [2:0] named_t; + typedef named_t [1:0] named_named_t; + typedef logic signed [1:0][2:0] named_unnamed_t; + + named_named_t [1:0] named_named; + named_unnamed_t [1:0] named_unnamed; + logic signed [1:0][1:0][2:0] unnamed; + + initial begin + // Set 1 to MSB(=sign bit) + named_named = 12'b100000_000000; + named_unnamed = 12'b100000_000000; + unnamed = 12'b100000_000000; + + if ($signed((named_named >>> 1) >> 11) != 0) begin + $stop; + end + if ($signed((named_named[1] >>> 1) >> 5) != 0) begin + $stop; + end + if ($signed((named_named[1][1] >>> 1) >> 2) != 1) begin + $stop; + end + + if ($signed((named_unnamed >>> 1) >> 11) != 0) begin + $stop; + end + if ($signed((named_unnamed[1] >>> 1) >> 5) != 1) begin + $stop; + end + if ($signed((named_unnamed[1][1] >>> 1) >> 2) != 0) begin + $stop; + end + + if ($signed((unnamed >>> 1) >> 11) != 1) begin + $stop;// + end + if ($signed((unnamed[1] >>> 1) >> 5) != 0) begin + $stop; + end + if ($signed((unnamed[1][1] >>> 1) >> 2) != 0) begin + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_array_packed_sysfunct.py b/test_regress/t/t_array_packed_sysfunct.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_packed_sysfunct.py +++ b/test_regress/t/t_array_packed_sysfunct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_packed_sysfunct.v b/test_regress/t/t_array_packed_sysfunct.v index b6f8877f6..fa081a1c3 100644 --- a/test_regress/t/t_array_packed_sysfunct.v +++ b/test_regress/t/t_array_packed_sysfunct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_array_packed_write_read.py b/test_regress/t/t_array_packed_write_read.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_packed_write_read.py +++ b/test_regress/t/t_array_packed_write_read.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_packed_write_read.v b/test_regress/t/t_array_packed_write_read.v index 1e2bf3d15..9fca1c2cc 100644 --- a/test_regress/t/t_array_packed_write_read.v +++ b/test_regress/t/t_array_packed_write_read.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_array_pattern_2d.py b/test_regress/t/t_array_pattern_2d.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_pattern_2d.py +++ b/test_regress/t/t_array_pattern_2d.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_pattern_2d.v b/test_regress/t/t_array_pattern_2d.v index 27e26b5cc..8df3b6fed 100644 --- a/test_regress/t/t_array_pattern_2d.v +++ b/test_regress/t/t_array_pattern_2d.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 //bug991 diff --git a/test_regress/t/t_array_pattern_bad.py b/test_regress/t/t_array_pattern_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_array_pattern_bad.py +++ b/test_regress/t/t_array_pattern_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_pattern_bad.v b/test_regress/t/t_array_pattern_bad.v index 6e00d149b..c35f191b1 100644 --- a/test_regress/t/t_array_pattern_bad.v +++ b/test_regress/t/t_array_pattern_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug1364 diff --git a/test_regress/t/t_array_pattern_bad2.py b/test_regress/t/t_array_pattern_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_array_pattern_bad2.py +++ b/test_regress/t/t_array_pattern_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_pattern_bad2.v b/test_regress/t/t_array_pattern_bad2.v index 5401630bc..4aa91b236 100644 --- a/test_regress/t/t_array_pattern_bad2.v +++ b/test_regress/t/t_array_pattern_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug1364 diff --git a/test_regress/t/t_array_pattern_bad3.py b/test_regress/t/t_array_pattern_bad3.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_array_pattern_bad3.py +++ b/test_regress/t/t_array_pattern_bad3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_pattern_bad3.v b/test_regress/t/t_array_pattern_bad3.v index a646ecca9..2e487c1e8 100644 --- a/test_regress/t/t_array_pattern_bad3.v +++ b/test_regress/t/t_array_pattern_bad3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug1364 diff --git a/test_regress/t/t_array_pattern_enum.py b/test_regress/t/t_array_pattern_enum.py index 4ac3b843d..b685d6345 100755 --- a/test_regress/t/t_array_pattern_enum.py +++ b/test_regress/t/t_array_pattern_enum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_pattern_enum.v b/test_regress/t/t_array_pattern_enum.v index 8581a1cee..eeae8c36e 100644 --- a/test_regress/t/t_array_pattern_enum.v +++ b/test_regress/t/t_array_pattern_enum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg; diff --git a/test_regress/t/t_array_pattern_packed.py b/test_regress/t/t_array_pattern_packed.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_pattern_packed.py +++ b/test_regress/t/t_array_pattern_packed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_pattern_packed.v b/test_regress/t/t_array_pattern_packed.v index 0c3eff320..45afbad31 100644 --- a/test_regress/t/t_array_pattern_packed.v +++ b/test_regress/t/t_array_pattern_packed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_array_pattern_scalar_bad.py b/test_regress/t/t_array_pattern_scalar_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_array_pattern_scalar_bad.py +++ b/test_regress/t/t_array_pattern_scalar_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_pattern_scalar_bad.v b/test_regress/t/t_array_pattern_scalar_bad.v index 03415c521..741538da6 100644 --- a/test_regress/t/t_array_pattern_scalar_bad.v +++ b/test_regress/t/t_array_pattern_scalar_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_array_pattern_unpacked.py b/test_regress/t/t_array_pattern_unpacked.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_pattern_unpacked.py +++ b/test_regress/t/t_array_pattern_unpacked.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_pattern_unpacked.v b/test_regress/t/t_array_pattern_unpacked.v index fd9a99d01..601d85db2 100644 --- a/test_regress/t/t_array_pattern_unpacked.v +++ b/test_regress/t/t_array_pattern_unpacked.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_array_query.py b/test_regress/t/t_array_query.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_query.py +++ b/test_regress/t/t_array_query.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_query.v b/test_regress/t/t_array_query.v index 963495080..0585a59ff 100644 --- a/test_regress/t/t_array_query.v +++ b/test_regress/t/t_array_query.v @@ -3,12 +3,10 @@ // This code instantiates a module that calls the various array querying // functions. // -// This file ONLY is placed into the Public Domain, for any use, without -// warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett, Embecosm // SPDX-License-Identifier: CC0-1.0 -// Contributed 2012 by Jeremy Bennett, Embecosm. - module t (/*AUTOARG*/ // Inputs clk diff --git a/test_regress/t/t_array_query_with.py b/test_regress/t/t_array_query_with.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_array_query_with.py +++ b/test_regress/t/t_array_query_with.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_query_with.v b/test_regress/t/t_array_query_with.v index d69ddfa42..eec4685b0 100644 --- a/test_regress/t/t_array_query_with.v +++ b/test_regress/t/t_array_query_with.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_array_rev.py b/test_regress/t/t_array_rev.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_rev.py +++ b/test_regress/t/t_array_rev.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_rev.v b/test_regress/t/t_array_rev.v index 6d06bbd9d..c8c63c58f 100644 --- a/test_regress/t/t_array_rev.v +++ b/test_regress/t/t_array_rev.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Geoff Barrett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Geoff Barrett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_array_sel_wide.py b/test_regress/t/t_array_sel_wide.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_array_sel_wide.py +++ b/test_regress/t/t_array_sel_wide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_sel_wide.v b/test_regress/t/t_array_sel_wide.v index 9f15a890b..24601b694 100644 --- a/test_regress/t/t_array_sel_wide.v +++ b/test_regress/t/t_array_sel_wide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_array_type_methods.py b/test_regress/t/t_array_type_methods.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_array_type_methods.py +++ b/test_regress/t/t_array_type_methods.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_type_methods.v b/test_regress/t/t_array_type_methods.v index d76ebd01e..7b3c71110 100644 --- a/test_regress/t/t_array_type_methods.v +++ b/test_regress/t/t_array_type_methods.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_array_unpacked_public.py b/test_regress/t/t_array_unpacked_public.py index 31843bd7b..96cc687b0 100755 --- a/test_regress/t/t_array_unpacked_public.py +++ b/test_regress/t/t_array_unpacked_public.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_array_unpacked_public.v b/test_regress/t/t_array_unpacked_public.v index fecfba51e..b74d6de54 100644 --- a/test_regress/t/t_array_unpacked_public.v +++ b/test_regress/t/t_array_unpacked_public.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 module t(); diff --git a/test_regress/t/t_assert_always_unsup.py b/test_regress/t/t_assert_always_unsup.py index acfc9858c..0ae6c2cf1 100755 --- a/test_regress/t/t_assert_always_unsup.py +++ b/test_regress/t/t_assert_always_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_always_unsup.v b/test_regress/t/t_assert_always_unsup.v index 5e46e676c..3165d4420 100644 --- a/test_regress/t/t_assert_always_unsup.v +++ b/test_regress/t/t_assert_always_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022-2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2022-2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_assert.py b/test_regress/t/t_assert_assert.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_assert_assert.py +++ b/test_regress/t/t_assert_assert.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_assert.v b/test_regress/t/t_assert_assert.v index ed0c9ef34..8065336c7 100644 --- a/test_regress/t/t_assert_assert.v +++ b/test_regress/t/t_assert_assert.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_assert_basic.py b/test_regress/t/t_assert_basic.py index d97aaff01..cae36a498 100755 --- a/test_regress/t/t_assert_basic.py +++ b/test_regress/t/t_assert_basic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_basic.v b/test_regress/t/t_assert_basic.v index 52ab6ed42..768a9f823 100644 --- a/test_regress/t/t_assert_basic.v +++ b/test_regress/t/t_assert_basic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_basic_cover.py b/test_regress/t/t_assert_basic_cover.py index 045f31a9c..48c7114a7 100755 --- a/test_regress/t/t_assert_basic_cover.py +++ b/test_regress/t/t_assert_basic_cover.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_basic_fail.py b/test_regress/t/t_assert_basic_fail.py index 08961e17e..b967c0080 100755 --- a/test_regress/t/t_assert_basic_fail.py +++ b/test_regress/t/t_assert_basic_fail.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_basic_off.py b/test_regress/t/t_assert_basic_off.py index cd9e8e0c5..ece9748ce 100755 --- a/test_regress/t/t_assert_basic_off.py +++ b/test_regress/t/t_assert_basic_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_casez.py b/test_regress/t/t_assert_casez.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_assert_casez.py +++ b/test_regress/t/t_assert_casez.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_casez.v b/test_regress/t/t_assert_casez.v index 359fc4ef2..a906454de 100644 --- a/test_regress/t/t_assert_casez.v +++ b/test_regress/t/t_assert_casez.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_assert_clock_event_unsup.py b/test_regress/t/t_assert_clock_event_unsup.py index 7e5bcdfe5..b5718946c 100755 --- a/test_regress/t/t_assert_clock_event_unsup.py +++ b/test_regress/t/t_assert_clock_event_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_clock_event_unsup.v b/test_regress/t/t_assert_clock_event_unsup.v index 6737ff316..eaac7d402 100644 --- a/test_regress/t/t_assert_clock_event_unsup.v +++ b/test_regress/t/t_assert_clock_event_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_comp.py b/test_regress/t/t_assert_comp.py index 85bad5b9a..2ed260e6f 100755 --- a/test_regress/t/t_assert_comp.py +++ b/test_regress/t/t_assert_comp.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_comp.v b/test_regress/t/t_assert_comp.v index ab85c8e58..970ac4b1a 100644 --- a/test_regress/t/t_assert_comp.v +++ b/test_regress/t/t_assert_comp.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_assert_comp_bad.py b/test_regress/t/t_assert_comp_bad.py index d90cee6ad..33f92081e 100755 --- a/test_regress/t/t_assert_comp_bad.py +++ b/test_regress/t/t_assert_comp_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_comp_bad.v b/test_regress/t/t_assert_comp_bad.v index f8a4fac4e..f1779f0d0 100644 --- a/test_regress/t/t_assert_comp_bad.v +++ b/test_regress/t/t_assert_comp_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_assert_cover.py b/test_regress/t/t_assert_cover.py index 4c62fcc22..175cad18a 100755 --- a/test_regress/t/t_assert_cover.py +++ b/test_regress/t/t_assert_cover.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_cover.v b/test_regress/t/t_assert_cover.v index fe4b6d93d..1fc90b039 100644 --- a/test_regress/t/t_assert_cover.v +++ b/test_regress/t/t_assert_cover.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_cover_off.py b/test_regress/t/t_assert_cover_off.py index 356558121..0df7ec649 100755 --- a/test_regress/t/t_assert_cover_off.py +++ b/test_regress/t/t_assert_cover_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_ctl_arg.cpp b/test_regress/t/t_assert_ctl_arg.cpp index 050d30833..7e386b5b0 100644 --- a/test_regress/t/t_assert_ctl_arg.cpp +++ b/test_regress/t/t_assert_ctl_arg.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include "verilated_cov.h" diff --git a/test_regress/t/t_assert_ctl_arg.py b/test_regress/t/t_assert_ctl_arg.py index d376b9136..573f5c1b5 100755 --- a/test_regress/t/t_assert_ctl_arg.py +++ b/test_regress/t/t_assert_ctl_arg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_ctl_arg.v b/test_regress/t/t_assert_ctl_arg.v index 94f2b3a41..5f11b2889 100644 --- a/test_regress/t/t_assert_ctl_arg.v +++ b/test_regress/t/t_assert_ctl_arg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 `define DISPLAY_PASS(file, line) \ diff --git a/test_regress/t/t_assert_ctl_arg_noinl.py b/test_regress/t/t_assert_ctl_arg_noinl.py index 205ed60f4..1ea437d1f 100755 --- a/test_regress/t/t_assert_ctl_arg_noinl.py +++ b/test_regress/t/t_assert_ctl_arg_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_ctl_arg_unsup.py b/test_regress/t/t_assert_ctl_arg_unsup.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_assert_ctl_arg_unsup.py +++ b/test_regress/t/t_assert_ctl_arg_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_ctl_arg_unsup.v b/test_regress/t/t_assert_ctl_arg_unsup.v index 74df63e66..e998de28e 100644 --- a/test_regress/t/t_assert_ctl_arg_unsup.v +++ b/test_regress/t/t_assert_ctl_arg_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_assert_ctl_concurrent.py b/test_regress/t/t_assert_ctl_concurrent.py index dddff8e39..5f3b89cca 100755 --- a/test_regress/t/t_assert_ctl_concurrent.py +++ b/test_regress/t/t_assert_ctl_concurrent.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_ctl_concurrent.v b/test_regress/t/t_assert_ctl_concurrent.v index a327b541a..3cc919d92 100644 --- a/test_regress/t/t_assert_ctl_concurrent.v +++ b/test_regress/t/t_assert_ctl_concurrent.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_assert_ctl_concurrent_noinl.py b/test_regress/t/t_assert_ctl_concurrent_noinl.py index 92c1105ac..1e71be98c 100755 --- a/test_regress/t/t_assert_ctl_concurrent_noinl.py +++ b/test_regress/t/t_assert_ctl_concurrent_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_ctl_immediate.py b/test_regress/t/t_assert_ctl_immediate.py index cbd7dd9cc..9691aba35 100755 --- a/test_regress/t/t_assert_ctl_immediate.py +++ b/test_regress/t/t_assert_ctl_immediate.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_ctl_immediate.v b/test_regress/t/t_assert_ctl_immediate.v index 05925fdc0..26d5a1e92 100644 --- a/test_regress/t/t_assert_ctl_immediate.v +++ b/test_regress/t/t_assert_ctl_immediate.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_ctl_immediate_noinl.py b/test_regress/t/t_assert_ctl_immediate_noinl.py index be07788c3..1a57006dc 100755 --- a/test_regress/t/t_assert_ctl_immediate_noinl.py +++ b/test_regress/t/t_assert_ctl_immediate_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_ctl_type_bad.py b/test_regress/t/t_assert_ctl_type_bad.py index 0275f2df9..da00b062f 100755 --- a/test_regress/t/t_assert_ctl_type_bad.py +++ b/test_regress/t/t_assert_ctl_type_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_ctl_type_bad.v b/test_regress/t/t_assert_ctl_type_bad.v old mode 100755 new mode 100644 index 7d25822ce..c482e152e --- a/test_regress/t/t_assert_ctl_type_bad.v +++ b/test_regress/t/t_assert_ctl_type_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_assert_ctl_unsup.py b/test_regress/t/t_assert_ctl_unsup.py index 0275f2df9..da00b062f 100755 --- a/test_regress/t/t_assert_ctl_unsup.py +++ b/test_regress/t/t_assert_ctl_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_ctl_unsup.v b/test_regress/t/t_assert_ctl_unsup.v old mode 100755 new mode 100644 index b0ec25707..7ff4eb013 --- a/test_regress/t/t_assert_ctl_unsup.v +++ b/test_regress/t/t_assert_ctl_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t(input logic clk); diff --git a/test_regress/t/t_assert_disable_bad.py b/test_regress/t/t_assert_disable_bad.py index 7e5bcdfe5..b5718946c 100755 --- a/test_regress/t/t_assert_disable_bad.py +++ b/test_regress/t/t_assert_disable_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_disable_bad.v b/test_regress/t/t_assert_disable_bad.v index 7bb6c04ad..4103e7b54 100644 --- a/test_regress/t/t_assert_disable_bad.v +++ b/test_regress/t/t_assert_disable_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_disable_count.py b/test_regress/t/t_assert_disable_count.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_assert_disable_count.py +++ b/test_regress/t/t_assert_disable_count.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_disable_count.v b/test_regress/t/t_assert_disable_count.v index 3a424467c..54451f211 100644 --- a/test_regress/t/t_assert_disable_count.v +++ b/test_regress/t/t_assert_disable_count.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_assert_disable_iff.py b/test_regress/t/t_assert_disable_iff.py index b17623e03..6832b1356 100755 --- a/test_regress/t/t_assert_disable_iff.py +++ b/test_regress/t/t_assert_disable_iff.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_disable_iff.v b/test_regress/t/t_assert_disable_iff.v index 764a406bc..86774145a 100644 --- a/test_regress/t/t_assert_disable_iff.v +++ b/test_regress/t/t_assert_disable_iff.v @@ -1,58 +1,64 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Peter Monsson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Peter Monsson // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; - int cyc; + input clk; + int cyc; - Test test (/*AUTOINST*/ - // Inputs - .clk (clk)); + Test test ( /*AUTOINST*/ + // Inputs + .clk(clk), + .cyc(cyc) + ); - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Test ( - input clk + input clk, + input int cyc ); `ifdef FAIL_ASSERT_1 - assert property (@(posedge clk) disable iff (0) 0) - else $display("wrong disable"); + assert property (@(posedge clk) disable iff (0) 0) + else $display("wrong disable"); `endif - assert property (@(posedge clk) disable iff (1) 0) $stop; - else $stop; + assert property (@(posedge clk) disable iff (1) 0) $stop; + else $stop; - assert property (@(posedge clk) disable iff (1) 1) $stop; - else $stop; + assert property (@(posedge clk) disable iff (1) 1) $stop; + else $stop; - assert property (@(posedge clk) disable iff (0) 1); + assert property (@(posedge clk) disable iff (0) 1); - // - // Cover properties behave differently - // + // Pass 1st cycle + assert property (@(cyc) disable iff (cyc != $sampled(cyc)) cyc == 0); - cover property (@(posedge clk) disable iff (1) 1) $stop; + // + // Cover properties behave differently + // - cover property (@(posedge clk) disable iff (1) 0) $stop; + cover property (@(posedge clk) disable iff (1) 1) $stop; - cover property (@(posedge clk) disable iff (0) 1) $display("*COVER: ok"); + cover property (@(posedge clk) disable iff (1) 0) $stop; - cover property (@(posedge clk) disable iff (0) 0) $stop; + cover property (@(posedge clk) disable iff (0) 1) $display("*COVER: ok"); + + cover property (@(posedge clk) disable iff (0) 0) $stop; endmodule diff --git a/test_regress/t/t_assert_disabled.py b/test_regress/t/t_assert_disabled.py index e6adf4fde..3a4d31c50 100755 --- a/test_regress/t/t_assert_disabled.py +++ b/test_regress/t/t_assert_disabled.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_dup_bad.py b/test_regress/t/t_assert_dup_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_assert_dup_bad.py +++ b/test_regress/t/t_assert_dup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_dup_bad.v b/test_regress/t/t_assert_dup_bad.v index aef62c7f4..250f7da9e 100644 --- a/test_regress/t/t_assert_dup_bad.v +++ b/test_regress/t/t_assert_dup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_elab.py b/test_regress/t/t_assert_elab.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_assert_elab.py +++ b/test_regress/t/t_assert_elab.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_elab.v b/test_regress/t/t_assert_elab.v index 9a23b1f5a..516cbd220 100644 --- a/test_regress/t/t_assert_elab.v +++ b/test_regress/t/t_assert_elab.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Johan Bjork. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Johan Bjork // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_assert_elab_bad.py b/test_regress/t/t_assert_elab_bad.py index 29cd2bc62..153dcddc8 100755 --- a/test_regress/t/t_assert_elab_bad.py +++ b/test_regress/t/t_assert_elab_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_elab_p.py b/test_regress/t/t_assert_elab_p.py index 099333258..8443b98f6 100755 --- a/test_regress/t/t_assert_elab_p.py +++ b/test_regress/t/t_assert_elab_p.py @@ -1,16 +1,16 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('simulator_st') -test.compile(expect_filename=test.golden_filename) +test.compile(verilator_flags2=['--no-skip-identical'], expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_assert_elab_p.v b/test_regress/t/t_assert_elab_p.v index 92a95bcc1..64ee3d0c7 100644 --- a/test_regress/t/t_assert_elab_p.v +++ b/test_regress/t/t_assert_elab_p.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH diff --git a/test_regress/t/t_assert_enabled_bad.py b/test_regress/t/t_assert_enabled_bad.py index aa290b7d0..211659953 100755 --- a/test_regress/t/t_assert_enabled_bad.py +++ b/test_regress/t/t_assert_enabled_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_enabled_off.py b/test_regress/t/t_assert_enabled_off.py index f2cce0678..da4df0583 100755 --- a/test_regress/t/t_assert_enabled_off.py +++ b/test_regress/t/t_assert_enabled_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_enabled_on_bad.py b/test_regress/t/t_assert_enabled_on_bad.py index 5789d18b7..97b64dfe7 100755 --- a/test_regress/t/t_assert_enabled_on_bad.py +++ b/test_regress/t/t_assert_enabled_on_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_future.py b/test_regress/t/t_assert_future.py index a34dd7c7a..a9ba85b06 100755 --- a/test_regress/t/t_assert_future.py +++ b/test_regress/t/t_assert_future.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_future.v b/test_regress/t/t_assert_future.v index 29ce13888..e95428d7d 100644 --- a/test_regress/t/t_assert_future.v +++ b/test_regress/t/t_assert_future.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_assert_future_bad.py b/test_regress/t/t_assert_future_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_assert_future_bad.py +++ b/test_regress/t/t_assert_future_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_future_bad.v b/test_regress/t/t_assert_future_bad.v index f8e28a4bf..b7a5121f3 100644 --- a/test_regress/t/t_assert_future_bad.v +++ b/test_regress/t/t_assert_future_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_assert_future_unsup.py b/test_regress/t/t_assert_future_unsup.py index 1bf1426f9..f3bbcad9d 100755 --- a/test_regress/t/t_assert_future_unsup.py +++ b/test_regress/t/t_assert_future_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_future_unsup.v b/test_regress/t/t_assert_future_unsup.v index 542ea17af..9349e7242 100644 --- a/test_regress/t/t_assert_future_unsup.v +++ b/test_regress/t/t_assert_future_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_assert_iff.py b/test_regress/t/t_assert_iff.py index b17623e03..6832b1356 100755 --- a/test_regress/t/t_assert_iff.py +++ b/test_regress/t/t_assert_iff.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_iff.v b/test_regress/t/t_assert_iff.v index 380f8831d..b56e72993 100644 --- a/test_regress/t/t_assert_iff.v +++ b/test_regress/t/t_assert_iff.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_iff_bad1.py b/test_regress/t/t_assert_iff_bad1.py index 0855ac24f..1eded5b63 100755 --- a/test_regress/t/t_assert_iff_bad1.py +++ b/test_regress/t/t_assert_iff_bad1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_iff_bad2.py b/test_regress/t/t_assert_iff_bad2.py index 6d25b802f..528ac5a33 100755 --- a/test_regress/t/t_assert_iff_bad2.py +++ b/test_regress/t/t_assert_iff_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_iff_clk_unsup.py b/test_regress/t/t_assert_iff_clk_unsup.py index 7e5bcdfe5..b5718946c 100755 --- a/test_regress/t/t_assert_iff_clk_unsup.py +++ b/test_regress/t/t_assert_iff_clk_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_iff_clk_unsup.v b/test_regress/t/t_assert_iff_clk_unsup.v index d1d3bd072..8890d5878 100644 --- a/test_regress/t/t_assert_iff_clk_unsup.v +++ b/test_regress/t/t_assert_iff_clk_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_imm_nz_bad.py b/test_regress/t/t_assert_imm_nz_bad.py index 7e5bcdfe5..b5718946c 100755 --- a/test_regress/t/t_assert_imm_nz_bad.py +++ b/test_regress/t/t_assert_imm_nz_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_imm_nz_bad.v b/test_regress/t/t_assert_imm_nz_bad.v index ce0867766..eaee647fe 100644 --- a/test_regress/t/t_assert_imm_nz_bad.v +++ b/test_regress/t/t_assert_imm_nz_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_implication.py b/test_regress/t/t_assert_implication.py index 724621ce6..3c390daaf 100755 --- a/test_regress/t/t_assert_implication.py +++ b/test_regress/t/t_assert_implication.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_implication.v b/test_regress/t/t_assert_implication.v index 1ff747a6b..4eb169f87 100644 --- a/test_regress/t/t_assert_implication.v +++ b/test_regress/t/t_assert_implication.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Peter Monsson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Peter Monsson // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_implication_bad.py b/test_regress/t/t_assert_implication_bad.py index 873345737..c6162d8aa 100755 --- a/test_regress/t/t_assert_implication_bad.py +++ b/test_regress/t/t_assert_implication_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_implication_coverage.py b/test_regress/t/t_assert_implication_coverage.py index 4674cc9c1..b375cb363 100755 --- a/test_regress/t/t_assert_implication_coverage.py +++ b/test_regress/t/t_assert_implication_coverage.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_implication_coverage.v b/test_regress/t/t_assert_implication_coverage.v index 8b4e5539c..6d58ec6cb 100644 --- a/test_regress/t/t_assert_implication_coverage.v +++ b/test_regress/t/t_assert_implication_coverage.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_assert_inside_cond.py b/test_regress/t/t_assert_inside_cond.py index 1a2dfabae..5ae697d72 100755 --- a/test_regress/t/t_assert_inside_cond.py +++ b/test_regress/t/t_assert_inside_cond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_inside_cond.v b/test_regress/t/t_assert_inside_cond.v index 6f12ec6d7..1a70b7a14 100644 --- a/test_regress/t/t_assert_inside_cond.v +++ b/test_regress/t/t_assert_inside_cond.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_inside_cond_bad.py b/test_regress/t/t_assert_inside_cond_bad.py index 8f955b403..382f607ed 100755 --- a/test_regress/t/t_assert_inside_cond_bad.py +++ b/test_regress/t/t_assert_inside_cond_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_on.v b/test_regress/t/t_assert_on.v index a1b28e48b..5ee299316 100644 --- a/test_regress/t/t_assert_on.v +++ b/test_regress/t/t_assert_on.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_past.py b/test_regress/t/t_assert_past.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_assert_past.py +++ b/test_regress/t/t_assert_past.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_past.v b/test_regress/t/t_assert_past.v index df6c6a920..40708babf 100644 --- a/test_regress/t/t_assert_past.v +++ b/test_regress/t/t_assert_past.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_pre.py b/test_regress/t/t_assert_pre.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_assert_pre.py +++ b/test_regress/t/t_assert_pre.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_pre.v b/test_regress/t/t_assert_pre.v index c8ce196ab..e0d812a62 100644 --- a/test_regress/t/t_assert_pre.v +++ b/test_regress/t/t_assert_pre.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_assert_procedural_clk_bad.py b/test_regress/t/t_assert_procedural_clk_bad.py index af14b700f..695572bb1 100755 --- a/test_regress/t/t_assert_procedural_clk_bad.py +++ b/test_regress/t/t_assert_procedural_clk_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_procedural_clk_bad.v b/test_regress/t/t_assert_procedural_clk_bad.v index ef2220d7f..e0615046f 100644 --- a/test_regress/t/t_assert_procedural_clk_bad.v +++ b/test_regress/t/t_assert_procedural_clk_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_question.py b/test_regress/t/t_assert_question.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_assert_question.py +++ b/test_regress/t/t_assert_question.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_question.v b/test_regress/t/t_assert_question.v index 8c6f4fe81..8d756a8e3 100644 --- a/test_regress/t/t_assert_question.v +++ b/test_regress/t/t_assert_question.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_sampled.py b/test_regress/t/t_assert_sampled.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_assert_sampled.py +++ b/test_regress/t/t_assert_sampled.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_sampled.v b/test_regress/t/t_assert_sampled.v index 3803e3634..5344592d6 100644 --- a/test_regress/t/t_assert_sampled.v +++ b/test_regress/t/t_assert_sampled.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_assert_synth.py b/test_regress/t/t_assert_synth.py index d97aaff01..cae36a498 100755 --- a/test_regress/t/t_assert_synth.py +++ b/test_regress/t/t_assert_synth.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_synth.v b/test_regress/t/t_assert_synth.v index 9eeda9ac7..fa9cff4f6 100644 --- a/test_regress/t/t_assert_synth.v +++ b/test_regress/t/t_assert_synth.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assert_synth_full.py b/test_regress/t/t_assert_synth_full.py index 5d213121c..51a4b04ab 100755 --- a/test_regress/t/t_assert_synth_full.py +++ b/test_regress/t/t_assert_synth_full.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_synth_full.vlt b/test_regress/t/t_assert_synth_full.vlt index ab46a1251..cadb835da 100644 --- a/test_regress/t/t_assert_synth_full.vlt +++ b/test_regress/t/t_assert_synth_full.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_assert_synth_full_vlt.py b/test_regress/t/t_assert_synth_full_vlt.py index 39ceee722..ddb365b89 100755 --- a/test_regress/t/t_assert_synth_full_vlt.py +++ b/test_regress/t/t_assert_synth_full_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_synth_off.py b/test_regress/t/t_assert_synth_off.py index 13a912951..a3749ba4e 100755 --- a/test_regress/t/t_assert_synth_off.py +++ b/test_regress/t/t_assert_synth_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_synth_parallel.py b/test_regress/t/t_assert_synth_parallel.py index 1218cfb79..ebc736037 100755 --- a/test_regress/t/t_assert_synth_parallel.py +++ b/test_regress/t/t_assert_synth_parallel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_synth_parallel.vlt b/test_regress/t/t_assert_synth_parallel.vlt index c2ddfb908..566a0b9f7 100644 --- a/test_regress/t/t_assert_synth_parallel.vlt +++ b/test_regress/t/t_assert_synth_parallel.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_assert_synth_parallel_vlt.py b/test_regress/t/t_assert_synth_parallel_vlt.py index 72f8e67fc..583578775 100755 --- a/test_regress/t/t_assert_synth_parallel_vlt.py +++ b/test_regress/t/t_assert_synth_parallel_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_unique_case.py b/test_regress/t/t_assert_unique_case.py index a76d4eb50..d51be7bb2 100755 --- a/test_regress/t/t_assert_unique_case.py +++ b/test_regress/t/t_assert_unique_case.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_unique_case_bad.py b/test_regress/t/t_assert_unique_case_bad.py index 3924fa02d..4286be915 100755 --- a/test_regress/t/t_assert_unique_case_bad.py +++ b/test_regress/t/t_assert_unique_case_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assert_unique_case_bad.v b/test_regress/t/t_assert_unique_case_bad.v index c5a3f1dab..949ccd9c5 100644 --- a/test_regress/t/t_assert_unique_case_bad.v +++ b/test_regress/t/t_assert_unique_case_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Yutetsu TAKATSUKASA. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assign_automatic_bad.py b/test_regress/t/t_assign_automatic_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_assign_automatic_bad.py +++ b/test_regress/t/t_assign_automatic_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assign_automatic_bad.v b/test_regress/t/t_assign_automatic_bad.v index dca14c9ba..83cf794d2 100644 --- a/test_regress/t/t_assign_automatic_bad.v +++ b/test_regress/t/t_assign_automatic_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // 6.21 Scope and lifetime diff --git a/test_regress/t/t_assign_cont_automatic_bad.out b/test_regress/t/t_assign_cont_automatic_bad.out new file mode 100644 index 000000000..0d32e5fca --- /dev/null +++ b/test_regress/t/t_assign_cont_automatic_bad.out @@ -0,0 +1,6 @@ +%Error: t/t_assign_cont_automatic_bad.v:14:26: Automatic lifetime variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'l' + : ... note: In instance 't' + 14 | assign g = signed'(l); + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_assign_cont_automatic_bad.py b/test_regress/t/t_assign_cont_automatic_bad.py new file mode 100755 index 000000000..1d5ccb8f4 --- /dev/null +++ b/test_regress/t/t_assign_cont_automatic_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assign_cont_automatic_bad.v b/test_regress/t/t_assign_cont_automatic_bad.v new file mode 100644 index 000000000..a603b8ceb --- /dev/null +++ b/test_regress/t/t_assign_cont_automatic_bad.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + + reg g; + + task automatic tsk; + reg l; + begin : cont_block + assign g = signed'(l); // <--- BAD: using automatic in cont assignment + end + endtask + + initial $stop; + +endmodule diff --git a/test_regress/t/t_assign_expr.py b/test_regress/t/t_assign_expr.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_assign_expr.py +++ b/test_regress/t/t_assign_expr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assign_expr.v b/test_regress/t/t_assign_expr.v index 7eb4b6f28..ff551bc81 100644 --- a/test_regress/t/t_assign_expr.v +++ b/test_regress/t/t_assign_expr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_static_function_in_class_call_without_parentheses.py b/test_regress/t/t_assign_func.py similarity index 50% rename from test_regress/t/t_static_function_in_class_call_without_parentheses.py rename to test_regress/t/t_assign_func.py index d4f986441..8a938befd 100755 --- a/test_regress/t/t_static_function_in_class_call_without_parentheses.py +++ b/test_regress/t/t_assign_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assign_func.v b/test_regress/t/t_assign_func.v new file mode 100644 index 000000000..0664d3745 --- /dev/null +++ b/test_regress/t/t_assign_func.v @@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk +); + + int cyc; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [9:0] a0 = crc[9:0]; + wire [9:0] a1 = crc[19:10]; + wire [9:0] b1 = crc[39:30]; + wire asel = crc[62]; + wire bsel = crc[63]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [9:0] aq; // From test of Test.v + wire [9:0] bq; // From test of Test.v + // End of automatics + + Test test ( /*AUTOINST*/ + // Outputs + .aq(aq[9:0]), + .bq(bq[9:0]), + // Inputs + .a0(a0[9:0]), + .a1(a1[9:0]), + .b1(b1[9:0]), + .asel(asel), + .bsel(bsel) + ); + + // Aggregate outputs into a single result vector + wire [63:0] result = {44'h0, aq, bq}; + + // Test loop + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h2c5e6c5e285efafa + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test ( + input [9:0] a0, + input [9:0] a1, + input [9:0] b1, + input asel, + input bsel, + output wire [9:0] aq, + output wire [9:0] bq +); + + assign aq = MUX10_2(a0, a1, asel); + assign bq = MUX10_2(aq, b1, bsel); + + function [9:0] MUX10_2; // Legacy code - not function automatic + input [9:0] i0; + input [9:0] i1; + input [0:0] sel; + /*static*/ logic [9:0] result; // Note this is not automatic + case (sel) + 1'b0: result = i0; + default: result = i1; + endcase + MUX10_2 = result; + endfunction + +endmodule diff --git a/test_regress/t/t_assign_inline.py b/test_regress/t/t_assign_inline.py index 6a30330fc..54903fd3d 100755 --- a/test_regress/t/t_assign_inline.py +++ b/test_regress/t/t_assign_inline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assign_inline.v b/test_regress/t/t_assign_inline.v index 1b7033e80..f378db28e 100644 --- a/test_regress/t/t_assign_inline.v +++ b/test_regress/t/t_assign_inline.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Mike Thyer. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Mike Thyer // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_assign_slice_overflow.py b/test_regress/t/t_assign_slice_overflow.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_assign_slice_overflow.py +++ b/test_regress/t/t_assign_slice_overflow.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assign_slice_overflow.v b/test_regress/t/t_assign_slice_overflow.v index 816aa6b98..64b6fca2c 100644 --- a/test_regress/t/t_assign_slice_overflow.v +++ b/test_regress/t/t_assign_slice_overflow.v @@ -19,8 +19,8 @@ // - Select offset is non-constant, destination is wide, bit-select width != 1 // - Select offset is non-constant, destination is narrow // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by David Turner. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 David Turner // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_assign_slice_overflow_ox.py b/test_regress/t/t_assign_slice_overflow_ox.py index b1371a321..d28c9d7e7 100755 --- a/test_regress/t/t_assign_slice_overflow_ox.py +++ b/test_regress/t/t_assign_slice_overflow_ox.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assigndly_deep_ref.py b/test_regress/t/t_assigndly_deep_ref.py index fda93f1f5..05f4c1c48 100755 --- a/test_regress/t/t_assigndly_deep_ref.py +++ b/test_regress/t/t_assigndly_deep_ref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assigndly_deep_ref.v b/test_regress/t/t_assigndly_deep_ref.v index 9393c161d..56fd8e0d3 100644 --- a/test_regress/t/t_assigndly_deep_ref.v +++ b/test_regress/t/t_assigndly_deep_ref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface Iface; @@ -51,9 +51,9 @@ module t; endtask initial begin - Foo foo = new(iface); - Foo foo2 = new(iface2); - Bar bar = new(foo); + automatic Foo foo = new(iface); + automatic Foo foo2 = new(iface2); + automatic Bar bar = new(foo); clockSome(); if (iface.x != 0) $stop; if (iface2.x != 0) $stop; diff --git a/test_regress/t/t_assigndly_deep_ref_array.py b/test_regress/t/t_assigndly_deep_ref_array.py index fda93f1f5..05f4c1c48 100755 --- a/test_regress/t/t_assigndly_deep_ref_array.py +++ b/test_regress/t/t_assigndly_deep_ref_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assigndly_deep_ref_array.v b/test_regress/t/t_assigndly_deep_ref_array.v index 4b9b12459..8ac1a84b6 100644 --- a/test_regress/t/t_assigndly_deep_ref_array.v +++ b/test_regress/t/t_assigndly_deep_ref_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface Iface; @@ -55,9 +55,9 @@ module t; endtask initial begin - Foo foo = new(iface); - Foo foo2 = new(iface2); - Bar bar = new(foo); + automatic Foo foo = new(iface); + automatic Foo foo2 = new(iface2); + automatic Bar bar = new(foo); clockSome(); if (iface.x[0] != 0) $stop; if (iface.x[1] != 0) $stop; diff --git a/test_regress/t/t_assigndly_dynamic.py b/test_regress/t/t_assigndly_dynamic.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_assigndly_dynamic.py +++ b/test_regress/t/t_assigndly_dynamic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assigndly_dynamic.v b/test_regress/t/t_assigndly_dynamic.v index 391174165..f1fac2ecf 100644 --- a/test_regress/t/t_assigndly_dynamic.v +++ b/test_regress/t/t_assigndly_dynamic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `ifdef WITH_DELAY @@ -15,56 +15,56 @@ `endif class nba_waiter; - // Task taken from UVM - task wait_for_nba_region; - static int nba; - int next_nba; - next_nba++; - nba <= `DELAY next_nba; - @(nba); - endtask + // Task taken from UVM + task wait_for_nba_region; + static int nba; + int next_nba; + next_nba++; + nba <= `DELAY next_nba; + @(nba); + endtask endclass class Foo; - task bar(logic a, logic b); - static int x; - static int y; - // bar's local vars and intravals could be overwritten by other locals - if (a) x <= `DELAY 'hDEAD; - if (b) y <= `DELAY 'hBEEF; - #2 - if (x != 'hDEAD) $stop; - endtask + task bar(logic a, logic b); + static int x; + static int y; + // bar's local vars and intravals could be overwritten by other locals + if (a) x <= `DELAY 'hDEAD; + if (b) y <= `DELAY 'hBEEF; + #2; + if (x != 'hDEAD) $stop; + endtask endclass module t; - nba_waiter waiter = new; - Foo foo = new; - event e; - int cnt = 0; + nba_waiter waiter = new; + Foo foo = new; + event e; + int cnt = 0; - initial begin - #1 ->e; - if (cnt != 0) $stop; - cnt++; - waiter.wait_for_nba_region; - ->e; - if (cnt != 2) $stop; - if ($time != `TIME_AFTER_FIRST_WAIT) $stop; - cnt++; - waiter.wait_for_nba_region; - if (cnt != 4) $stop; - if ($time != `TIME_AFTER_SECOND_WAIT) $stop; - foo.bar(1, 1); - #2 - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #1 ->e; + if (cnt != 0) $stop; + cnt++; + waiter.wait_for_nba_region; + ->e; + if (cnt != 2) $stop; + if ($time != `TIME_AFTER_FIRST_WAIT) $stop; + cnt++; + waiter.wait_for_nba_region; + if (cnt != 4) $stop; + if ($time != `TIME_AFTER_SECOND_WAIT) $stop; + foo.bar(1, 1); + #2; + $write("*-* All Finished *-*\n"); + $finish; + end - initial begin - @e if (cnt != 1) $stop; - cnt++; - @e if (cnt != 3) $stop; - cnt++; - end + initial begin + @e if (cnt != 1) $stop; + cnt++; + @e if (cnt != 3) $stop; + cnt++; + end endmodule diff --git a/test_regress/t/t_assigndly_dynamic_delay.py b/test_regress/t/t_assigndly_dynamic_delay.py index a3df69d2b..fc53ed6a8 100755 --- a/test_regress/t/t_assigndly_dynamic_delay.py +++ b/test_regress/t/t_assigndly_dynamic_delay.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assigndly_dynamic_nofork.py b/test_regress/t/t_assigndly_dynamic_nofork.py index 999869c5c..12f9972d3 100755 --- a/test_regress/t/t_assigndly_dynamic_nofork.py +++ b/test_regress/t/t_assigndly_dynamic_nofork.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.py b/test_regress/t/t_assigndly_dynamic_notiming_bad.py index 6f71603b5..d1bad5e3a 100755 --- a/test_regress/t/t_assigndly_dynamic_notiming_bad.py +++ b/test_regress/t/t_assigndly_dynamic_notiming_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.v b/test_regress/t/t_assigndly_dynamic_notiming_bad.v index b439348c8..818f9378f 100644 --- a/test_regress/t/t_assigndly_dynamic_notiming_bad.v +++ b/test_regress/t/t_assigndly_dynamic_notiming_bad.v @@ -1,13 +1,15 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; task bar; static int qux; qux <= '1; + // Use qux to prevent V3Dead optimizations + $display("qux = %d\n", qux); endtask endclass diff --git a/test_regress/t/t_assigndly_task.py b/test_regress/t/t_assigndly_task.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_assigndly_task.py +++ b/test_regress/t/t_assigndly_task.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assigndly_task.v b/test_regress/t/t_assigndly_task.v index 3d51a7ad6..6a7f4f63b 100644 --- a/test_regress/t/t_assigndly_task.v +++ b/test_regress/t/t_assigndly_task.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_assoc.py b/test_regress/t/t_assoc.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_assoc.py +++ b/test_regress/t/t_assoc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc.v b/test_regress/t/t_assoc.v index c8cae1b37..1f9d9b5a9 100644 --- a/test_regress/t/t_assoc.v +++ b/test_regress/t/t_assoc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_assoc2.py b/test_regress/t/t_assoc2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_assoc2.py +++ b/test_regress/t/t_assoc2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc2.v b/test_regress/t/t_assoc2.v index f3d03dcc2..42deb93c1 100644 --- a/test_regress/t/t_assoc2.v +++ b/test_regress/t/t_assoc2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_assoc_compare.py b/test_regress/t/t_assoc_compare.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_assoc_compare.py +++ b/test_regress/t/t_assoc_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_compare.v b/test_regress/t/t_assoc_compare.v index 1311b7cab..ce4923359 100644 --- a/test_regress/t/t_assoc_compare.v +++ b/test_regress/t/t_assoc_compare.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Check == and != operations performed on associative arrays // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Ilya Barkov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Ilya Barkov // SPDX-License-Identifier: CC0-1.0 `define stop $stop @@ -39,8 +39,8 @@ module t; begin // check that a class as key is fine int assoc1[Cls]; int assoc2[Cls]; - Cls a = new; - Cls b = new; + automatic Cls a = new; + automatic Cls b = new; int t; assoc1[a] = 0; `check_ne(assoc1, assoc2) @@ -53,8 +53,8 @@ module t; begin // check that a class as value is fine Cls assoc1[int]; Cls assoc2[int]; - Cls a = new; - Cls b = new; + automatic Cls a = new; + automatic Cls b = new; assoc1[1] = a; assoc2[1] = b; `check_ne(assoc1, assoc2) diff --git a/test_regress/t/t_assoc_default_func.py b/test_regress/t/t_assoc_default_func.py index cca4c9e73..d6d35e7fd 100755 --- a/test_regress/t/t_assoc_default_func.py +++ b/test_regress/t/t_assoc_default_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_default_func.v b/test_regress/t/t_assoc_default_func.v index e6f73bfad..50e1a8395 100644 --- a/test_regress/t/t_assoc_default_func.v +++ b/test_regress/t/t_assoc_default_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_assoc_enum.py b/test_regress/t/t_assoc_enum.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_assoc_enum.py +++ b/test_regress/t/t_assoc_enum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_enum.v b/test_regress/t/t_assoc_enum.v index 24e756851..79de64a4d 100644 --- a/test_regress/t/t_assoc_enum.v +++ b/test_regress/t/t_assoc_enum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off @@ -36,7 +36,7 @@ endclass module t; initial begin - X x = new; + automatic X x = new; $finish; end diff --git a/test_regress/t/t_assoc_method.py b/test_regress/t/t_assoc_method.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_assoc_method.py +++ b/test_regress/t/t_assoc_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_method.v b/test_regress/t/t_assoc_method.v index df7a0d556..cadc9809b 100644 --- a/test_regress/t/t_assoc_method.v +++ b/test_regress/t/t_assoc_method.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_assoc_method_bad.py b/test_regress/t/t_assoc_method_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_assoc_method_bad.py +++ b/test_regress/t/t_assoc_method_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_method_bad.v b/test_regress/t/t_assoc_method_bad.v index db44272b9..a2dabc4ea 100644 --- a/test_regress/t/t_assoc_method_bad.v +++ b/test_regress/t/t_assoc_method_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_assoc_method_map.py b/test_regress/t/t_assoc_method_map.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_assoc_method_map.py +++ b/test_regress/t/t_assoc_method_map.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_method_map.v b/test_regress/t/t_assoc_method_map.v index 1003f7742..c01a19a30 100644 --- a/test_regress/t/t_assoc_method_map.v +++ b/test_regress/t/t_assoc_method_map.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop @@ -10,8 +10,8 @@ module t; initial begin - int res[]; - int a[int] = '{1: 100, 2: 200, 3: 300}; + automatic int res[]; + automatic int a[int] = '{1: 100, 2: 200, 3: 300}; // TODO results not known to be correct res = a.map(el) with (el == 2); diff --git a/test_regress/t/t_assoc_nokey_bad.out b/test_regress/t/t_assoc_nokey_bad.out index 3ad1b3790..02de8ff85 100644 --- a/test_regress/t/t_assoc_nokey_bad.out +++ b/test_regress/t/t_assoc_nokey_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_assoc_nokey_bad.v:12:28: Missing pattern key (need an expression then a ':') +%Error: t/t_assoc_nokey_bad.v:12:36: Missing pattern key (need an expression then a ':') : ... note: In instance 't' - 12 | int dict[string] = '{1, 2}; - | ^ + 12 | automatic int dict[string] = '{1, 2}; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_assoc_nokey_bad.v:12:31: Missing pattern key (need an expression then a ':') +%Error: t/t_assoc_nokey_bad.v:12:39: Missing pattern key (need an expression then a ':') : ... note: In instance 't' - 12 | int dict[string] = '{1, 2}; - | ^ + 12 | automatic int dict[string] = '{1, 2}; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_assoc_nokey_bad.py b/test_regress/t/t_assoc_nokey_bad.py index dece38f4e..c7d9b21a5 100755 --- a/test_regress/t/t_assoc_nokey_bad.py +++ b/test_regress/t/t_assoc_nokey_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_nokey_bad.v b/test_regress/t/t_assoc_nokey_bad.v index 124f9ea60..afc76fe71 100644 --- a/test_regress/t/t_assoc_nokey_bad.v +++ b/test_regress/t/t_assoc_nokey_bad.v @@ -2,19 +2,19 @@ // // Simple bi-directional alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - int dict[string] = '{1, 2}; - int dict2[string] = '{3: 4}; // Legal due to value-to-string conversion - $display("dict=%p", dict); - $display("dict2=%p", dict2); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic int dict[string] = '{1, 2}; + automatic int dict2[string] = '{3: 4}; // Legal due to value-to-string conversion + $display("dict=%p", dict); + $display("dict2=%p", dict2); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assoc_ref_type.py b/test_regress/t/t_assoc_ref_type.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_assoc_ref_type.py +++ b/test_regress/t/t_assoc_ref_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_ref_type.v b/test_regress/t/t_assoc_ref_type.v index 173daf87f..276f98893 100644 --- a/test_regress/t/t_assoc_ref_type.v +++ b/test_regress/t/t_assoc_ref_type.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo1; @@ -66,13 +66,13 @@ module t; localparam string str_key = "the_key"; initial begin - Bar bar_i = new; - Baz baz_1_i = new; - Baz #(Foo2) baz_2_i = new; - Bum bum_i; + automatic Bar bar_i = new; + automatic Baz baz_1_i = new; + automatic Baz #(Foo2) baz_2_i = new; + automatic Bum bum_i; - Wrapper#(wrap_map_t) wrap_map = new(); - Wrapper#(wrap_queue_t) wrap_queue = new(); + automatic Wrapper#(wrap_map_t) wrap_map = new(); + automatic Wrapper#(wrap_queue_t) wrap_queue = new(); bar_i.set(1); baz_1_i.set(2); diff --git a/test_regress/t/t_assoc_wildcard.py b/test_regress/t/t_assoc_wildcard.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_assoc_wildcard.py +++ b/test_regress/t/t_assoc_wildcard.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_wildcard.v b/test_regress/t/t_assoc_wildcard.v index fd7ea4a03..002ae3549 100644 --- a/test_regress/t/t_assoc_wildcard.v +++ b/test_regress/t/t_assoc_wildcard.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_assoc_wildcard_bad.py b/test_regress/t/t_assoc_wildcard_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_assoc_wildcard_bad.py +++ b/test_regress/t/t_assoc_wildcard_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_wildcard_bad.v b/test_regress/t/t_assoc_wildcard_bad.v index 3246eb72e..f8e7c6f01 100644 --- a/test_regress/t/t_assoc_wildcard_bad.v +++ b/test_regress/t/t_assoc_wildcard_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef class Cls; diff --git a/test_regress/t/t_assoc_wildcard_map.py b/test_regress/t/t_assoc_wildcard_map.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_assoc_wildcard_map.py +++ b/test_regress/t/t_assoc_wildcard_map.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_wildcard_map.v b/test_regress/t/t_assoc_wildcard_map.v index a5e2f012a..befe2d958 100644 --- a/test_regress/t/t_assoc_wildcard_map.v +++ b/test_regress/t/t_assoc_wildcard_map.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off @@ -12,8 +12,8 @@ module t; initial begin - int res[]; - int a [*] = '{1: 100, 2: 200, 3: 300}; + automatic int res[]; + automatic int a [*] = '{1: 100, 2: 200, 3: 300}; // TODO results not known to be correct res = a.map(el) with (el == 2); diff --git a/test_regress/t/t_assoc_wildcard_method.py b/test_regress/t/t_assoc_wildcard_method.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_assoc_wildcard_method.py +++ b/test_regress/t/t_assoc_wildcard_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_assoc_wildcard_method.v b/test_regress/t/t_assoc_wildcard_method.v index 34d399015..d9b784d2d 100644 --- a/test_regress/t/t_assoc_wildcard_method.v +++ b/test_regress/t/t_assoc_wildcard_method.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop @@ -18,7 +18,7 @@ module t; initial begin int q[*]; int qe [ * ]; // Empty - Note spaces around [*] for parsing coverage - point points_q[*] = '{"a": point'{1, 2}, "b": point'{2, 4}, "c": point'{1, 4}}; + automatic point points_q[*] = '{"a": point'{1, 2}, "b": point'{2, 4}, "c": point'{1, 4}}; int qv[$]; // Value returns int qi[$]; // Index returns int i; diff --git a/test_regress/t/t_attr.py b/test_regress/t/t_attr.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_attr.py +++ b/test_regress/t/t_attr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_attr.v b/test_regress/t/t_attr.v index b24939114..655ff3058 100644 --- a/test_regress/t/t_attr.v +++ b/test_regress/t/t_attr.v @@ -1,14 +1,17 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; + localparam LP = 1; + (* attr_name1 *) - (* attr_name1 = val1 *) - (* attr_name1 = val1, attr_name2 *) + (* attr_name1 = 1 *) + (* attr_name1 = LP *) + (* attr_name1 = LP + 2, attr_name2 *) (* attr_name1 = val1, attr_name2=1 *) initial $finish; diff --git a/test_regress/t/t_attr_parenstar.py b/test_regress/t/t_attr_parenstar.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_attr_parenstar.py +++ b/test_regress/t/t_attr_parenstar.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_attr_parenstar.v b/test_regress/t/t_attr_parenstar.v index 6aef83e9d..580a42da7 100644 --- a/test_regress/t/t_attr_parenstar.v +++ b/test_regress/t/t_attr_parenstar.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_benchmark_mux4k.py b/test_regress/t/t_benchmark_mux4k.py index 1141bf9d2..61180d55a 100755 --- a/test_regress/t/t_benchmark_mux4k.py +++ b/test_regress/t/t_benchmark_mux4k.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_benchmark_mux4k.v b/test_regress/t/t_benchmark_mux4k.v index b2936a7b8..0e0fe4ee9 100644 --- a/test_regress/t/t_benchmark_mux4k.v +++ b/test_regress/t/t_benchmark_mux4k.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 // // This implements a 4096:1 mux via two stages of 64:1 muxing. diff --git a/test_regress/t/t_benchmark_mux4k_onecpu.py b/test_regress/t/t_benchmark_mux4k_onecpu.py index cf7690988..fc138f8da 100755 --- a/test_regress/t/t_benchmark_mux4k_onecpu.py +++ b/test_regress/t/t_benchmark_mux4k_onecpu.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_benchmark_sim.py b/test_regress/t/t_benchmark_sim.py index 4b23385b0..559d15b40 100755 --- a/test_regress/t/t_benchmark_sim.py +++ b/test_regress/t/t_benchmark_sim.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bind.py b/test_regress/t/t_bind.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_bind.py +++ b/test_regress/t/t_bind.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bind.v b/test_regress/t/t_bind.v index 27d98879b..a8ec4fe9e 100644 --- a/test_regress/t/t_bind.v +++ b/test_regress/t/t_bind.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 bit a_finished; diff --git a/test_regress/t/t_bind2.py b/test_regress/t/t_bind2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_bind2.py +++ b/test_regress/t/t_bind2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bind2.v b/test_regress/t/t_bind2.v index c1a7ef5bf..ebf19478c 100644 --- a/test_regress/t/t_bind2.v +++ b/test_regress/t/t_bind2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Ed Lander. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Ed Lander // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH diff --git a/test_regress/t/t_bind_nfound.py b/test_regress/t/t_bind_nfound.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_bind_nfound.py +++ b/test_regress/t/t_bind_nfound.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bind_nfound.v b/test_regress/t/t_bind_nfound.v index 505944b62..ba0e49bb5 100644 --- a/test_regress/t/t_bind_nfound.v +++ b/test_regress/t/t_bind_nfound.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface bound_if; diff --git a/test_regress/t/t_bitsel_2d_slice.py b/test_regress/t/t_bitsel_2d_slice.py index c39e83d77..903201f15 100755 --- a/test_regress/t/t_bitsel_2d_slice.py +++ b/test_regress/t/t_bitsel_2d_slice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_2d_slice.v b/test_regress/t/t_bitsel_2d_slice.v index 7aa39c50f..25ffbf47e 100644 --- a/test_regress/t/t_bitsel_2d_slice.v +++ b/test_regress/t/t_bitsel_2d_slice.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_bitsel_concat.py b/test_regress/t/t_bitsel_concat.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_bitsel_concat.py +++ b/test_regress/t/t_bitsel_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_concat.v b/test_regress/t/t_bitsel_concat.v index c0d687e00..daff0b45e 100644 --- a/test_regress/t/t_bitsel_concat.v +++ b/test_regress/t/t_bitsel_concat.v @@ -5,8 +5,8 @@ // This test is to check that bit selection of multi-dimensional signal inside // of a packed struct works. Currently +: and -: blow up with packed structs. // -// This file ONLY is placed into the Public Domain, for any use, without -// warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_bitsel_const_bad.py b/test_regress/t/t_bitsel_const_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_bitsel_const_bad.py +++ b/test_regress/t/t_bitsel_const_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_const_bad.v b/test_regress/t/t_bitsel_const_bad.v index cee4e86ea..27316736f 100644 --- a/test_regress/t/t_bitsel_const_bad.v +++ b/test_regress/t/t_bitsel_const_bad.v @@ -2,8 +2,8 @@ // // This tests issue #508, bit select of constant fails // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_bitsel_enum.py b/test_regress/t/t_bitsel_enum.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_bitsel_enum.py +++ b/test_regress/t/t_bitsel_enum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_enum.v b/test_regress/t/t_bitsel_enum.v index b23b72142..edb81040e 100644 --- a/test_regress/t/t_bitsel_enum.v +++ b/test_regress/t/t_bitsel_enum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Jonathon Donaldson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Jonathon Donaldson // SPDX-License-Identifier: CC0-1.0 module t_bitsel_enum diff --git a/test_regress/t/t_bitsel_lvalue.py b/test_regress/t/t_bitsel_lvalue.py index 147fe6faf..0379f0dd0 100755 --- a/test_regress/t/t_bitsel_lvalue.py +++ b/test_regress/t/t_bitsel_lvalue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_lvalue.v b/test_regress/t/t_bitsel_lvalue.v index da48ee063..fc5f9eeeb 100644 --- a/test_regress/t/t_bitsel_lvalue.v +++ b/test_regress/t/t_bitsel_lvalue.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_bitsel_over32.py b/test_regress/t/t_bitsel_over32.py index 46a3e3c1e..b24c8b500 100755 --- a/test_regress/t/t_bitsel_over32.py +++ b/test_regress/t/t_bitsel_over32.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_over32.v b/test_regress/t/t_bitsel_over32.v index 0940bc915..c4311ca0b 100644 --- a/test_regress/t/t_bitsel_over32.v +++ b/test_regress/t/t_bitsel_over32.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(aw_addr, orig_aw_size); diff --git a/test_regress/t/t_bitsel_slice.py b/test_regress/t/t_bitsel_slice.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_bitsel_slice.py +++ b/test_regress/t/t_bitsel_slice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_slice.v b/test_regress/t/t_bitsel_slice.v index e644592ba..bf26d8a10 100644 --- a/test_regress/t/t_bitsel_slice.v +++ b/test_regress/t/t_bitsel_slice.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_bitsel_struct.py b/test_regress/t/t_bitsel_struct.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_bitsel_struct.py +++ b/test_regress/t/t_bitsel_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_struct.v b/test_regress/t/t_bitsel_struct.v index 986b1bdf0..03e271b77 100644 --- a/test_regress/t/t_bitsel_struct.v +++ b/test_regress/t/t_bitsel_struct.v @@ -5,8 +5,8 @@ // This test is to check that bit selection of multi-dimensional signal inside // of a struct works. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jie Xu // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_bitsel_struct2.py b/test_regress/t/t_bitsel_struct2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_bitsel_struct2.py +++ b/test_regress/t/t_bitsel_struct2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_struct2.v b/test_regress/t/t_bitsel_struct2.v index 89dac5789..41b02b1ea 100644 --- a/test_regress/t/t_bitsel_struct2.v +++ b/test_regress/t/t_bitsel_struct2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_bitsel_struct3.py b/test_regress/t/t_bitsel_struct3.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_bitsel_struct3.py +++ b/test_regress/t/t_bitsel_struct3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_struct3.v b/test_regress/t/t_bitsel_struct3.v index b44b5f1ea..3a63eb106 100644 --- a/test_regress/t/t_bitsel_struct3.v +++ b/test_regress/t/t_bitsel_struct3.v @@ -5,8 +5,8 @@ // This test is to check that bit selection of multi-dimensional signal inside // of a packed struct works. Currently +: and -: blow up with packed structs. // -// This file ONLY is placed into the Public Domain, for any use, without -// warranty, 2013 by Jie Xu. +// This file ONLY is placed into the Public Domain. +// SPDX-FileCopyrightText: 2013 Jie Xu // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_bitsel_wire_array_bad.py b/test_regress/t/t_bitsel_wire_array_bad.py index d0fba6a98..3c74ad70b 100755 --- a/test_regress/t/t_bitsel_wire_array_bad.py +++ b/test_regress/t/t_bitsel_wire_array_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_bitsel_wire_array_bad.v b/test_regress/t/t_bitsel_wire_array_bad.v index cf3eca2d2..f14a20c61 100644 --- a/test_regress/t/t_bitsel_wire_array_bad.v +++ b/test_regress/t/t_bitsel_wire_array_bad.v @@ -2,8 +2,8 @@ // // This tests issue #509, bit select of constant fails // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_blocking.py b/test_regress/t/t_blocking.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_blocking.py +++ b/test_regress/t/t_blocking.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_blocking.v b/test_regress/t/t_blocking.v index 1f8013fbc..9978352cd 100644 --- a/test_regress/t/t_blocking.v +++ b/test_regress/t/t_blocking.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_c_this.py b/test_regress/t/t_c_this.py index be55d1566..4bb997e44 100755 --- a/test_regress/t/t_c_this.py +++ b/test_regress/t/t_c_this.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_c_this.v b/test_regress/t/t_c_this.v index 95cd63eac..50bd459f7 100644 --- a/test_regress/t/t_c_this.v +++ b/test_regress/t/t_c_this.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_c_width_bad.py b/test_regress/t/t_c_width_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_c_width_bad.py +++ b/test_regress/t/t_c_width_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_c_width_bad.v b/test_regress/t/t_c_width_bad.v index 18bfe5d84..f3e95433c 100644 --- a/test_regress/t/t_c_width_bad.v +++ b/test_regress/t/t_c_width_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_66bits.py b/test_regress/t/t_case_66bits.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_66bits.py +++ b/test_regress/t/t_case_66bits.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_66bits.v b/test_regress/t/t_case_66bits.v index b461f237a..47adab54b 100644 --- a/test_regress/t/t_case_66bits.v +++ b/test_regress/t/t_case_66bits.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_66bits_no_const_eager.py b/test_regress/t/t_case_66bits_no_const_eager.py index 2ce516e24..6809ac70f 100755 --- a/test_regress/t/t_case_66bits_no_const_eager.py +++ b/test_regress/t/t_case_66bits_no_const_eager.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_66bits_noexpand.py b/test_regress/t/t_case_66bits_noexpand.py index 2316143be..8674d7ee6 100755 --- a/test_regress/t/t_case_66bits_noexpand.py +++ b/test_regress/t/t_case_66bits_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_auto1.py b/test_regress/t/t_case_auto1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_auto1.py +++ b/test_regress/t/t_case_auto1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_auto1.v b/test_regress/t/t_case_auto1.v index a7cba372a..4c3350259 100644 --- a/test_regress/t/t_case_auto1.v +++ b/test_regress/t/t_case_auto1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_call_count.py b/test_regress/t/t_case_call_count.py index bd4e69b4b..4116217e8 100755 --- a/test_regress/t/t_case_call_count.py +++ b/test_regress/t/t_case_call_count.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_call_count.v b/test_regress/t/t_case_call_count.v index b7e7fdb8c..529596992 100644 --- a/test_regress/t/t_case_call_count.v +++ b/test_regress/t/t_case_call_count.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Cls; @@ -25,7 +25,7 @@ endclass module t; Cls c; initial begin - bit called = 0; + bit called; c = new; case (c.get()) 4: $stop; diff --git a/test_regress/t/t_case_deep.py b/test_regress/t/t_case_deep.py index 95c3e8bca..bfd4b3039 100755 --- a/test_regress/t/t_case_deep.py +++ b/test_regress/t/t_case_deep.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_deep.v b/test_regress/t/t_case_deep.v index ced8ee44d..b844e1d14 100644 --- a/test_regress/t/t_case_deep.v +++ b/test_regress/t/t_case_deep.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_default_bad.py b/test_regress/t/t_case_default_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_case_default_bad.py +++ b/test_regress/t/t_case_default_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_default_bad.v b/test_regress/t/t_case_default_bad.v index 4099e2d6b..fabed01c3 100644 --- a/test_regress/t/t_case_default_bad.v +++ b/test_regress/t/t_case_default_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_dupitems.py b/test_regress/t/t_case_dupitems.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_dupitems.py +++ b/test_regress/t/t_case_dupitems.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_dupitems.v b/test_regress/t/t_case_dupitems.v index 4c8911985..c608fb470 100644 --- a/test_regress/t/t_case_dupitems.v +++ b/test_regress/t/t_case_dupitems.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_enum_complete.py b/test_regress/t/t_case_enum_complete.py index 07d93ccf0..0930535c5 100755 --- a/test_regress/t/t_case_enum_complete.py +++ b/test_regress/t/t_case_enum_complete.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_enum_complete.v b/test_regress/t/t_case_enum_complete.v index cd0d02f92..2eb4e94f3 100644 --- a/test_regress/t/t_case_enum_complete.v +++ b/test_regress/t/t_case_enum_complete.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_enum_complete_wildcard.py b/test_regress/t/t_case_enum_complete_wildcard.py index 07d93ccf0..0930535c5 100755 --- a/test_regress/t/t_case_enum_complete_wildcard.py +++ b/test_regress/t/t_case_enum_complete_wildcard.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_enum_complete_wildcard.v b/test_regress/t/t_case_enum_complete_wildcard.v index 0beb75014..3cadee7bf 100644 --- a/test_regress/t/t_case_enum_complete_wildcard.v +++ b/test_regress/t/t_case_enum_complete_wildcard.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 // Fix bug4464 diff --git a/test_regress/t/t_case_enum_emptyish.py b/test_regress/t/t_case_enum_emptyish.py index 539f320b1..84c09a3bb 100755 --- a/test_regress/t/t_case_enum_emptyish.py +++ b/test_regress/t/t_case_enum_emptyish.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_enum_emptyish.v b/test_regress/t/t_case_enum_emptyish.v index 98b42103c..f637a6b33 100644 --- a/test_regress/t/t_case_enum_emptyish.v +++ b/test_regress/t/t_case_enum_emptyish.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_enum_incomplete_bad.py b/test_regress/t/t_case_enum_incomplete_bad.py index 0275f2df9..da00b062f 100755 --- a/test_regress/t/t_case_enum_incomplete_bad.py +++ b/test_regress/t/t_case_enum_incomplete_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_enum_incomplete_bad.v b/test_regress/t/t_case_enum_incomplete_bad.v index b6f6bc740..9c8e8395f 100644 --- a/test_regress/t/t_case_enum_incomplete_bad.v +++ b/test_regress/t/t_case_enum_incomplete_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_enum_incomplete_wildcard_bad.py b/test_regress/t/t_case_enum_incomplete_wildcard_bad.py index 0275f2df9..da00b062f 100755 --- a/test_regress/t/t_case_enum_incomplete_wildcard_bad.py +++ b/test_regress/t/t_case_enum_incomplete_wildcard_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_enum_incomplete_wildcard_bad.v b/test_regress/t/t_case_enum_incomplete_wildcard_bad.v index e0e6965ba..874eb2fa8 100644 --- a/test_regress/t/t_case_enum_incomplete_wildcard_bad.v +++ b/test_regress/t/t_case_enum_incomplete_wildcard_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_genx_bad.py b/test_regress/t/t_case_genx_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_case_genx_bad.py +++ b/test_regress/t/t_case_genx_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_genx_bad.v b/test_regress/t/t_case_genx_bad.v index c5d045979..7c5da4003 100644 --- a/test_regress/t/t_case_genx_bad.v +++ b/test_regress/t/t_case_genx_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_group.py b/test_regress/t/t_case_group.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_group.py +++ b/test_regress/t/t_case_group.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_group.v b/test_regress/t/t_case_group.v index 34525c73e..e69495511 100644 --- a/test_regress/t/t_case_group.v +++ b/test_regress/t/t_case_group.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Jonathon Donaldson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Jonathon Donaldson // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_case_huge.py b/test_regress/t/t_case_huge.py index f255824ab..81fcffbad 100755 --- a/test_regress/t/t_case_huge.py +++ b/test_regress/t/t_case_huge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_huge.v b/test_regress/t/t_case_huge.v index 655ff379a..cbdc93964 100644 --- a/test_regress/t/t_case_huge.v +++ b/test_regress/t/t_case_huge.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_huge_nocase.py b/test_regress/t/t_case_huge_nocase.py index 27639ae10..2b3aad742 100755 --- a/test_regress/t/t_case_huge_nocase.py +++ b/test_regress/t/t_case_huge_nocase.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_huge_noopt.py b/test_regress/t/t_case_huge_noopt.py index df4fd6835..5835918b6 100755 --- a/test_regress/t/t_case_huge_noopt.py +++ b/test_regress/t/t_case_huge_noopt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_huge_sub.v b/test_regress/t/t_case_huge_sub.v index 34d8514d5..2d95aeb1a 100644 --- a/test_regress/t/t_case_huge_sub.v +++ b/test_regress/t/t_case_huge_sub.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub (/*AUTOARG*/ diff --git a/test_regress/t/t_case_huge_sub2.v b/test_regress/t/t_case_huge_sub2.v index 5e5c4720f..7a71cb9e2 100644 --- a/test_regress/t/t_case_huge_sub2.v +++ b/test_regress/t/t_case_huge_sub2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub2 (/*AUTOARG*/ diff --git a/test_regress/t/t_case_huge_sub3.v b/test_regress/t/t_case_huge_sub3.v index 956324dc0..7d3d2df8f 100644 --- a/test_regress/t/t_case_huge_sub3.v +++ b/test_regress/t/t_case_huge_sub3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub3 (/*AUTOARG*/ diff --git a/test_regress/t/t_case_huge_sub4.v b/test_regress/t/t_case_huge_sub4.v index 5bc42fd3f..3b878d9d7 100644 --- a/test_regress/t/t_case_huge_sub4.v +++ b/test_regress/t/t_case_huge_sub4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off LATCH diff --git a/test_regress/t/t_case_incrdecr.py b/test_regress/t/t_case_incrdecr.py index ca7e7f331..7a37c1259 100755 --- a/test_regress/t/t_case_incrdecr.py +++ b/test_regress/t/t_case_incrdecr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_incrdecr.v b/test_regress/t/t_case_incrdecr.v index fe415616e..5fd5a4c4a 100644 --- a/test_regress/t/t_case_incrdecr.v +++ b/test_regress/t/t_case_incrdecr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_case_inside.py b/test_regress/t/t_case_inside.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_inside.py +++ b/test_regress/t/t_case_inside.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_inside.v b/test_regress/t/t_case_inside.v index 2db42cd2b..bb6305ce3 100644 --- a/test_regress/t/t_case_inside.v +++ b/test_regress/t/t_case_inside.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_inside_bad.py b/test_regress/t/t_case_inside_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_case_inside_bad.py +++ b/test_regress/t/t_case_inside_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_inside_bad.v b/test_regress/t/t_case_inside_bad.v index aa4e967c1..f653c84e1 100644 --- a/test_regress/t/t_case_inside_bad.v +++ b/test_regress/t/t_case_inside_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_inside_call_count.py b/test_regress/t/t_case_inside_call_count.py index bd4e69b4b..4116217e8 100755 --- a/test_regress/t/t_case_inside_call_count.py +++ b/test_regress/t/t_case_inside_call_count.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_inside_call_count.v b/test_regress/t/t_case_inside_call_count.v index 22e47039c..227de3f05 100644 --- a/test_regress/t/t_case_inside_call_count.v +++ b/test_regress/t/t_case_inside_call_count.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Cls; @@ -25,7 +25,7 @@ endclass module t; Cls c; initial begin - bit called = 0; + bit called; c = new; case (c.get()) inside [0:5]: $stop; diff --git a/test_regress/t/t_case_itemwidth.py b/test_regress/t/t_case_itemwidth.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_itemwidth.py +++ b/test_regress/t/t_case_itemwidth.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_itemwidth.v b/test_regress/t/t_case_itemwidth.v index 921a7bb51..0c0f16451 100644 --- a/test_regress/t/t_case_itemwidth.v +++ b/test_regress/t/t_case_itemwidth.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_nest.py b/test_regress/t/t_case_nest.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_nest.py +++ b/test_regress/t/t_case_nest.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_nest.v b/test_regress/t/t_case_nest.v index 55be130de..55d6d2171 100644 --- a/test_regress/t/t_case_nest.v +++ b/test_regress/t/t_case_nest.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_onehot.py b/test_regress/t/t_case_onehot.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_onehot.py +++ b/test_regress/t/t_case_onehot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_onehot.v b/test_regress/t/t_case_onehot.v index f555945d4..817e1eb8f 100644 --- a/test_regress/t/t_case_onehot.v +++ b/test_regress/t/t_case_onehot.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_orig.py b/test_regress/t/t_case_orig.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_orig.py +++ b/test_regress/t/t_case_orig.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_orig.v b/test_regress/t/t_case_orig.v index 823a97225..bbf1c84f5 100644 --- a/test_regress/t/t_case_orig.v +++ b/test_regress/t/t_case_orig.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_overlap_bad.out b/test_regress/t/t_case_overlap_bad.out index 3362705db..f53a2e97d 100644 --- a/test_regress/t/t_case_overlap_bad.out +++ b/test_regress/t/t_case_overlap_bad.out @@ -1,17 +1,11 @@ -%Warning-CASEOVERLAP: t/t_case_overlap_bad.v:20:21: Case conditions overlap (example pattern 0x6) - 20 | 3'b11?, 3'b???: v++; - | ^~~~~~ - t/t_case_overlap_bad.v:20:13: ... Location of overlapping condition - 20 | 3'b11?, 3'b???: v++; - | ^~~~~~ - ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=latest - ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Warning-CASEOVERLAP: t/t_case_overlap_bad.v:25:13: Case conditions overlap 25 | 3'b001, 3'b000: $stop; | ^~~~~~ t/t_case_overlap_bad.v:24:13: ... Location of overlapping condition 24 | 3'b00?: $stop; | ^~~~~~ + ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=latest + ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Warning-CASEOVERLAP: t/t_case_overlap_bad.v:30:13: Case conditions overlap (example pattern 0x7) 30 | 3'b11?: $stop; | ^~~~~~ diff --git a/test_regress/t/t_case_overlap_bad.py b/test_regress/t/t_case_overlap_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_case_overlap_bad.py +++ b/test_regress/t/t_case_overlap_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_overlap_bad.v b/test_regress/t/t_case_overlap_bad.v index 39cf8d4c6..1b30da2fe 100644 --- a/test_regress/t/t_case_overlap_bad.v +++ b/test_regress/t/t_case_overlap_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_reducer.py b/test_regress/t/t_case_reducer.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_reducer.py +++ b/test_regress/t/t_case_reducer.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_reducer.v b/test_regress/t/t_case_reducer.v index bf55f5d2f..02e398d01 100644 --- a/test_regress/t/t_case_reducer.v +++ b/test_regress/t/t_case_reducer.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_string.py b/test_regress/t/t_case_string.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_string.py +++ b/test_regress/t/t_case_string.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_string.v b/test_regress/t/t_case_string.v index a91a9a09d..46de15a86 100644 --- a/test_regress/t/t_case_string.v +++ b/test_regress/t/t_case_string.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_string2.py b/test_regress/t/t_case_string2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_string2.py +++ b/test_regress/t/t_case_string2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_string2.v b/test_regress/t/t_case_string2.v index f2722639b..01a5cb0f1 100644 --- a/test_regress/t/t_case_string2.v +++ b/test_regress/t/t_case_string2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_unique_many.py b/test_regress/t/t_case_unique_many.py index 4df7b8036..d4a6141c1 100755 --- a/test_regress/t/t_case_unique_many.py +++ b/test_regress/t/t_case_unique_many.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_unique_many.v b/test_regress/t/t_case_unique_many.v index 8c82086d2..394d39547 100644 --- a/test_regress/t/t_case_unique_many.v +++ b/test_regress/t/t_case_unique_many.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Varun Koyyalagunta, Tenstorrent. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Varun Koyyalagunta, Tenstorrent // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_unique_overlap.py b/test_regress/t/t_case_unique_overlap.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_case_unique_overlap.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_case_unique_overlap.v b/test_regress/t/t_case_unique_overlap.v new file mode 100644 index 000000000..9e77c0b6b --- /dev/null +++ b/test_regress/t/t_case_unique_overlap.v @@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Luca Colagrande +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk +); + + localparam logic [1:0] INST1 = 2'b0?; + localparam logic [1:0] INST2 = 2'b0?; + localparam logic [1:0] INST3 = 2'b1?; + + logic [1:0] in, out; + + always_comb begin + unique casez (in) + INST1, INST2: begin + if (in == 2'b00) out = 2'b01; + else out = 2'b00; + end + INST3: begin + out = 2'b10; + end + default: begin + out = 2'b11; + end + endcase + end + + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] in=%x out=%x\n", $time, in, out); +`endif + if (in == 0) begin + if (out != 2'b01) $stop; + end + else if (in == 1) begin + if (out != 2'b00) $stop; + end + else if (in == 2) begin + if (out != 2'b10) $stop; + end + else if (in == 3) begin + if (out != 2'b10) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + in <= in + 1; + end + +endmodule diff --git a/test_regress/t/t_case_wild.py b/test_regress/t/t_case_wild.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_case_wild.py +++ b/test_regress/t/t_case_wild.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_wild.v b/test_regress/t/t_case_wild.v index ef2002a14..80f08b488 100644 --- a/test_regress/t/t_case_wild.v +++ b/test_regress/t/t_case_wild.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_write1.py b/test_regress/t/t_case_write1.py index 68242656b..99c78dafa 100755 --- a/test_regress/t/t_case_write1.py +++ b/test_regress/t/t_case_write1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_write1.v b/test_regress/t/t_case_write1.v index cc790511d..901f8e5e8 100644 --- a/test_regress/t/t_case_write1.v +++ b/test_regress/t/t_case_write1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_case_write1_noexpand.py b/test_regress/t/t_case_write1_noexpand.py index 3ed6fde1c..1375ace89 100755 --- a/test_regress/t/t_case_write1_noexpand.py +++ b/test_regress/t/t_case_write1_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_write1_tasks.v b/test_regress/t/t_case_write1_tasks.v index 2ed073d58..5b4998938 100644 --- a/test_regress/t/t_case_write1_tasks.v +++ b/test_regress/t/t_case_write1_tasks.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_case_write1_tasks (); diff --git a/test_regress/t/t_case_write2.py b/test_regress/t/t_case_write2.py index 68242656b..99c78dafa 100755 --- a/test_regress/t/t_case_write2.py +++ b/test_regress/t/t_case_write2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_write2.v b/test_regress/t/t_case_write2.v index 1be020f0e..4123415ee 100644 --- a/test_regress/t/t_case_write2.v +++ b/test_regress/t/t_case_write2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_case_write2_tasks.v b/test_regress/t/t_case_write2_tasks.v index 840288eb4..6298dbadf 100644 --- a/test_regress/t/t_case_write2_tasks.v +++ b/test_regress/t/t_case_write2_tasks.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_case_write2_tasks (); diff --git a/test_regress/t/t_case_x.py b/test_regress/t/t_case_x.py index 8aee590f3..793e4f0a3 100755 --- a/test_regress/t/t_case_x.py +++ b/test_regress/t/t_case_x.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_x.v b/test_regress/t/t_case_x.v index c11a57f49..58d3a16f7 100644 --- a/test_regress/t/t_case_x.v +++ b/test_regress/t/t_case_x.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_case_x_bad.py b/test_regress/t/t_case_x_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_case_x_bad.py +++ b/test_regress/t/t_case_x_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_x_bad.v b/test_regress/t/t_case_x_bad.v index f42265cc7..761842c49 100644 --- a/test_regress/t/t_case_x_bad.v +++ b/test_regress/t/t_case_x_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_zx_bad.py b/test_regress/t/t_case_zx_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_case_zx_bad.py +++ b/test_regress/t/t_case_zx_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_case_zx_bad.v b/test_regress/t/t_case_zx_bad.v index a99363d78..58bab2d14 100644 --- a/test_regress/t/t_case_zx_bad.v +++ b/test_regress/t/t_case_zx_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_cast.py b/test_regress/t/t_cast.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_cast.py +++ b/test_regress/t/t_cast.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v index 98fba7f4e..3bf1c5124 100644 --- a/test_regress/t/t_cast.v +++ b/test_regress/t/t_cast.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface intf; diff --git a/test_regress/t/t_cast_class.py b/test_regress/t/t_cast_class.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_cast_class.py +++ b/test_regress/t/t_cast_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cast_class.v b/test_regress/t/t_cast_class.v index 41112a868..28c31716b 100644 --- a/test_regress/t/t_cast_class.v +++ b/test_regress/t/t_cast_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base; diff --git a/test_regress/t/t_cast_class_incompat_bad.py b/test_regress/t/t_cast_class_incompat_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_cast_class_incompat_bad.py +++ b/test_regress/t/t_cast_class_incompat_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cast_class_incompat_bad.v b/test_regress/t/t_cast_class_incompat_bad.v index d730af005..ca46da69c 100644 --- a/test_regress/t/t_cast_class_incompat_bad.v +++ b/test_regress/t/t_cast_class_incompat_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base; diff --git a/test_regress/t/t_cast_param_logic.py b/test_regress/t/t_cast_param_logic.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_cast_param_logic.py +++ b/test_regress/t/t_cast_param_logic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cast_param_logic.v b/test_regress/t/t_cast_param_logic.v index d452b0eb5..aeb6b494e 100644 --- a/test_regress/t/t_cast_param_logic.v +++ b/test_regress/t/t_cast_param_logic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_cast_param_type.py b/test_regress/t/t_cast_param_type.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_cast_param_type.py +++ b/test_regress/t/t_cast_param_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cast_param_type.v b/test_regress/t/t_cast_param_type.v index 18a50fe0d..f68e63a4e 100644 --- a/test_regress/t/t_cast_param_type.v +++ b/test_regress/t/t_cast_param_type.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef enum logic [1:0] {A, B, C } letters_t; diff --git a/test_regress/t/t_cast_signed.py b/test_regress/t/t_cast_signed.py index c39e83d77..903201f15 100755 --- a/test_regress/t/t_cast_signed.py +++ b/test_regress/t/t_cast_signed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cast_signed.v b/test_regress/t/t_cast_signed.v index d9cc53979..9a3832675 100644 --- a/test_regress/t/t_cast_signed.v +++ b/test_regress/t/t_cast_signed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_cast_size_bad.py b/test_regress/t/t_cast_size_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_cast_size_bad.py +++ b/test_regress/t/t_cast_size_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cast_size_bad.v b/test_regress/t/t_cast_size_bad.v index 3cf88e1da..c0dc36b4f 100644 --- a/test_regress/t/t_cast_size_bad.v +++ b/test_regress/t/t_cast_size_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_cast_stream.py b/test_regress/t/t_cast_stream.py index 147fe6faf..0379f0dd0 100755 --- a/test_regress/t/t_cast_stream.py +++ b/test_regress/t/t_cast_stream.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cast_stream.v b/test_regress/t/t_cast_stream.v index 05c75c6d8..703ced890 100644 --- a/test_regress/t/t_cast_stream.v +++ b/test_regress/t/t_cast_stream.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off @@ -18,9 +18,9 @@ typedef enum { module t; initial begin - bit array[] = new [8]; - int unsigned m_length; - uvm_tlm_command_e m_command; + automatic bit array[] = new [8]; + automatic int unsigned m_length; + automatic uvm_tlm_command_e m_command; m_length = 2; array = '{0, 0, 0, 0, 0, 0, 1, 0}; diff --git a/test_regress/t/t_cast_types.py b/test_regress/t/t_cast_types.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_cast_types.py +++ b/test_regress/t/t_cast_types.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cast_types.v b/test_regress/t/t_cast_types.v index 955e8bc42..c1d2fe71e 100644 --- a/test_regress/t/t_cast_types.v +++ b/test_regress/t/t_cast_types.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define TRY_ASSIGN(a,b) a = b diff --git a/test_regress/t/t_castdyn.py b/test_regress/t/t_castdyn.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_castdyn.py +++ b/test_regress/t/t_castdyn.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_castdyn.v b/test_regress/t/t_castdyn.v index 3437d3c15..f6afea886 100644 --- a/test_regress/t/t_castdyn.v +++ b/test_regress/t/t_castdyn.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base; diff --git a/test_regress/t/t_castdyn_bbox.py b/test_regress/t/t_castdyn_bbox.py index 3bc0aac7a..9f9743e9e 100755 --- a/test_regress/t/t_castdyn_bbox.py +++ b/test_regress/t/t_castdyn_bbox.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_castdyn_castconst_bad.py b/test_regress/t/t_castdyn_castconst_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_castdyn_castconst_bad.py +++ b/test_regress/t/t_castdyn_castconst_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_castdyn_castconst_bad.v b/test_regress/t/t_castdyn_castconst_bad.v index 48c8d171d..76ec5e7f5 100644 --- a/test_regress/t/t_castdyn_castconst_bad.v +++ b/test_regress/t/t_castdyn_castconst_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base; diff --git a/test_regress/t/t_castdyn_enum.py b/test_regress/t/t_castdyn_enum.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_castdyn_enum.py +++ b/test_regress/t/t_castdyn_enum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_castdyn_enum.v b/test_regress/t/t_castdyn_enum.v index 2a68c93bf..44b6bba5b 100644 --- a/test_regress/t/t_castdyn_enum.v +++ b/test_regress/t/t_castdyn_enum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef enum {TEN=10, diff --git a/test_regress/t/t_castdyn_run_bad.py b/test_regress/t/t_castdyn_run_bad.py index 2fdd6e92d..0dbd253f9 100755 --- a/test_regress/t/t_castdyn_run_bad.py +++ b/test_regress/t/t_castdyn_run_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_castdyn_run_bad.v b/test_regress/t/t_castdyn_run_bad.v index 168369505..999d45dd7 100644 --- a/test_regress/t/t_castdyn_run_bad.v +++ b/test_regress/t/t_castdyn_run_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base; diff --git a/test_regress/t/t_castdyn_unsup_bad.py b/test_regress/t/t_castdyn_unsup_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_castdyn_unsup_bad.py +++ b/test_regress/t/t_castdyn_unsup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_castdyn_unsup_bad.v b/test_regress/t/t_castdyn_unsup_bad.v index e9aa03530..d36ae6406 100644 --- a/test_regress/t/t_castdyn_unsup_bad.v +++ b/test_regress/t/t_castdyn_unsup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_ccache_report.py b/test_regress/t/t_ccache_report.py index c165d1442..1b78eeb5a 100755 --- a/test_regress/t/t_ccache_report.py +++ b/test_regress/t/t_ccache_report.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_checker.py b/test_regress/t/t_checker.py index 4df7b8036..d4a6141c1 100755 --- a/test_regress/t/t_checker.py +++ b/test_regress/t/t_checker.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_checker.v b/test_regress/t/t_checker.v index 61d8671d4..099423cea 100644 --- a/test_regress/t/t_checker.v +++ b/test_regress/t/t_checker.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_checker_top.py b/test_regress/t/t_checker_top.py index 06f5a0953..fedddbcdd 100755 --- a/test_regress/t/t_checker_top.py +++ b/test_regress/t/t_checker_top.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_checker_top.v b/test_regress/t/t_checker_top.v index 2c127e82c..fa575a315 100644 --- a/test_regress/t/t_checker_top.v +++ b/test_regress/t/t_checker_top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Not super-sensical to have checker without module, but useful for --lint-only diff --git a/test_regress/t/t_checker_unsup.py b/test_regress/t/t_checker_unsup.py index c735f5265..09ecd3de7 100755 --- a/test_regress/t/t_checker_unsup.py +++ b/test_regress/t/t_checker_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_checker_unsup.v b/test_regress/t/t_checker_unsup.v index 7d755b94d..4926cd4ab 100644 --- a/test_regress/t/t_checker_unsup.v +++ b/test_regress/t/t_checker_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_class1.py b/test_regress/t/t_class1.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_class1.py +++ b/test_regress/t/t_class1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class1.v b/test_regress/t/t_class1.v index 22510ac0d..1c4dc3736 100644 --- a/test_regress/t/t_class1.v +++ b/test_regress/t/t_class1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef class Cls; diff --git a/test_regress/t/t_class2.py b/test_regress/t/t_class2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class2.py +++ b/test_regress/t/t_class2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class2.v b/test_regress/t/t_class2.v index 412443a0e..d3bfc7962 100644 --- a/test_regress/t/t_class2.v +++ b/test_regress/t/t_class2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg; diff --git a/test_regress/t/t_class_assign_bad.py b/test_regress/t/t_class_assign_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_assign_bad.py +++ b/test_regress/t/t_class_assign_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_assign_bad.v b/test_regress/t/t_class_assign_bad.v index bf79a2b17..afa52f3aa 100644 --- a/test_regress/t/t_class_assign_bad.v +++ b/test_regress/t/t_class_assign_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_assign_cond.py b/test_regress/t/t_class_assign_cond.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_assign_cond.py +++ b/test_regress/t/t_class_assign_cond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_assign_cond.v b/test_regress/t/t_class_assign_cond.v index 4b60f537c..c1a040e2b 100644 --- a/test_regress/t/t_class_assign_cond.v +++ b/test_regress/t/t_class_assign_cond.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; @@ -33,10 +33,11 @@ module t; typedef ExtendCls ExtendCls_t; initial begin - Cls cls1 = null, cls2 = null; - ExtendCls_t ext_cls = null; - AnotherExtendCls an_ext_cls = null; - ExtendExtendCls ext_ext_cls = null; + automatic Cls cls1 = null; + automatic Cls cls2 = null; + automatic ExtendCls_t ext_cls = null; + automatic AnotherExtendCls an_ext_cls = null; + automatic ExtendExtendCls ext_ext_cls = null; int r; cls1 = (cls1 == null) ? cls2 : cls1; diff --git a/test_regress/t/t_class_assign_cond_bad.py b/test_regress/t/t_class_assign_cond_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_assign_cond_bad.py +++ b/test_regress/t/t_class_assign_cond_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_assign_cond_bad.v b/test_regress/t/t_class_assign_cond_bad.v index 304d6e0ca..8e51728e8 100644 --- a/test_regress/t/t_class_assign_cond_bad.v +++ b/test_regress/t/t_class_assign_cond_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls1; diff --git a/test_regress/t/t_class_builtin_bad.py b/test_regress/t/t_class_builtin_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_builtin_bad.py +++ b/test_regress/t/t_class_builtin_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_builtin_bad.v b/test_regress/t/t_class_builtin_bad.v index 343d4a179..5f3c42ade 100644 --- a/test_regress/t/t_class_builtin_bad.v +++ b/test_regress/t/t_class_builtin_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_capitalization.py b/test_regress/t/t_class_capitalization.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_capitalization.py +++ b/test_regress/t/t_class_capitalization.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_capitalization.v b/test_regress/t/t_class_capitalization.v index c8ca4e699..5bbcf882e 100644 --- a/test_regress/t/t_class_capitalization.v +++ b/test_regress/t/t_class_capitalization.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Test different uppercase/lowercase capitalization cases diff --git a/test_regress/t/t_class_class.py b/test_regress/t/t_class_class.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_class.py +++ b/test_regress/t/t_class_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_class.v b/test_regress/t/t_class_class.v index a5fe60faa..d04c31774 100644 --- a/test_regress/t/t_class_class.v +++ b/test_regress/t/t_class_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Note UVM internals do not require classes-in-classes diff --git a/test_regress/t/t_class_class_extends.py b/test_regress/t/t_class_class_extends.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_class_class_extends.py +++ b/test_regress/t/t_class_class_extends.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_class_extends.v b/test_regress/t/t_class_class_extends.v index 4baae7ce4..6f40138c2 100644 --- a/test_regress/t/t_class_class_extends.v +++ b/test_regress/t/t_class_class_extends.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; @@ -107,7 +107,7 @@ module t; endclass initial begin - Cls c = new(); + automatic Cls c = new(); $finish; end endmodule diff --git a/test_regress/t/t_class_compare.py b/test_regress/t/t_class_compare.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_compare.py +++ b/test_regress/t/t_class_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_compare.v b/test_regress/t/t_class_compare.v index b20d435cd..22521ee02 100644 --- a/test_regress/t/t_class_compare.v +++ b/test_regress/t/t_class_compare.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Check == and != operations performed on class objects // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Ilya Barkov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Ilya Barkov // SPDX-License-Identifier: CC0-1.0 `define stop $stop @@ -22,12 +22,12 @@ endclass module t; initial begin - Cls a = new; - Cls b = new; - ExtendCls ext = new; - Cls::InnerCls ia = new; - Cls::InnerCls ib = new; - ExtendCls::InnerCls iext = new; + automatic Cls a = new; + automatic Cls b = new; + automatic ExtendCls ext = new; + automatic Cls::InnerCls ia = new; + automatic Cls::InnerCls ib = new; + automatic ExtendCls::InnerCls iext = new; `check_ne(a, b) `check_ne(a, ext) `check_ne(ext, a) diff --git a/test_regress/t/t_class_const.py b/test_regress/t/t_class_const.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_const.py +++ b/test_regress/t/t_class_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_const.v b/test_regress/t/t_class_const.v index 5c30fa001..e0ab5aaac 100644 --- a/test_regress/t/t_class_const.v +++ b/test_regress/t/t_class_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; @@ -11,7 +11,7 @@ endclass module t; initial begin - Cls c = new; + automatic Cls c = new; if (c.aconst !== 10) $stop; if (Cls::astatic !== 20) $stop; $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_class_copy.py b/test_regress/t/t_class_copy.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_copy.py +++ b/test_regress/t/t_class_copy.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_copy.v b/test_regress/t/t_class_copy.v index c540b004b..b2cd08082 100644 --- a/test_regress/t/t_class_copy.v +++ b/test_regress/t/t_class_copy.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_copy2.py b/test_regress/t/t_class_copy2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_copy2.py +++ b/test_regress/t/t_class_copy2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_copy2.v b/test_regress/t/t_class_copy2.v index bd5e6408f..a296497c6 100644 --- a/test_regress/t/t_class_copy2.v +++ b/test_regress/t/t_class_copy2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_class_copy_bad.py b/test_regress/t/t_class_copy_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_copy_bad.py +++ b/test_regress/t/t_class_copy_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_copy_bad.v b/test_regress/t/t_class_copy_bad.v index 66a8f0266..d69b81f9d 100644 --- a/test_regress/t/t_class_copy_bad.v +++ b/test_regress/t/t_class_copy_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Other; diff --git a/test_regress/t/t_class_dead_varscope_uaf.py b/test_regress/t/t_class_dead_varscope_uaf.py new file mode 100755 index 000000000..ba6f14e4c --- /dev/null +++ b/test_regress/t/t_class_dead_varscope_uaf.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Regression test for scope/var lifetime issue +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_class_dead_varscope_uaf.v" + +test.compile(verilator_flags2=['--binary', '--timing', '--debug']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_dead_varscope_uaf.v b/test_regress/t/t_class_dead_varscope_uaf.v new file mode 100644 index 000000000..e573079a7 --- /dev/null +++ b/test_regress/t/t_class_dead_varscope_uaf.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Regression test for scope/var lifetime issue +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + + +package p; + typedef chandle PyObject; + + class uvm_object; + endclass + + class py_object; + function new(PyObject o); + endfunction + endclass + + class pyhdl_uvm_object_rgy; + static pyhdl_uvm_object_rgy m_inst; + + static function pyhdl_uvm_object_rgy inst(); + if (m_inst == null) m_inst = new; + return m_inst; + endfunction + + function PyObject wrap(uvm_object obj); + if (obj == null) return null; + return null; + endfunction + endclass + + class comp_proxy; + virtual function PyObject get_config_object(string name, bit clone = 0); + uvm_object obj; + py_object py_obj; + bit has = 0; + + if (has && obj != null) begin + py_obj = new(pyhdl_uvm_object_rgy::inst().wrap(obj)); + end + + return null; + endfunction + endclass +endpackage + +module t; + import p::*; + + initial begin + automatic comp_proxy cp = new; + void'(cp.get_config_object("x")); + $finish; + end +endmodule diff --git a/test_regress/t/t_class_defaultparam_import.py b/test_regress/t/t_class_defaultparam_import.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_class_defaultparam_import.py +++ b/test_regress/t/t_class_defaultparam_import.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_defaultparam_import.v b/test_regress/t/t_class_defaultparam_import.v index 9788346f5..f5b2347e9 100644 --- a/test_regress/t/t_class_defaultparam_import.v +++ b/test_regress/t/t_class_defaultparam_import.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 package foo; diff --git a/test_regress/t/t_class_defaultparams.py b/test_regress/t/t_class_defaultparams.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_class_defaultparams.py +++ b/test_regress/t/t_class_defaultparams.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_defaultparams.v b/test_regress/t/t_class_defaultparams.v index 0d95a5aa5..f5c955929 100644 --- a/test_regress/t/t_class_defaultparams.v +++ b/test_regress/t/t_class_defaultparams.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilator lint_off NORETURN diff --git a/test_regress/t/t_class_diamond.py b/test_regress/t/t_class_diamond.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_diamond.py +++ b/test_regress/t/t_class_diamond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_diamond.v b/test_regress/t/t_class_diamond.v index b4af229af..a75bb27e9 100644 --- a/test_regress/t/t_class_diamond.v +++ b/test_regress/t/t_class_diamond.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module class_tb (); diff --git a/test_regress/t/t_class_dict.py b/test_regress/t/t_class_dict.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_dict.py +++ b/test_regress/t/t_class_dict.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_dict.v b/test_regress/t/t_class_dict.v index cddb21f8c..bef95456d 100644 --- a/test_regress/t/t_class_dict.v +++ b/test_regress/t/t_class_dict.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop @@ -16,9 +16,9 @@ endclass module t; initial begin - int dict[Cls]; - Cls c1 = new(1); - Cls c2 = new(2); + automatic int dict[Cls]; + automatic Cls c1 = new(1); + automatic Cls c2 = new(2); dict[c1] = 1; dict[c2] = 2; `checkh(dict[c1], 1); diff --git a/test_regress/t/t_class_dyn_cast_empty_if.py b/test_regress/t/t_class_dyn_cast_empty_if.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_class_dyn_cast_empty_if.py +++ b/test_regress/t/t_class_dyn_cast_empty_if.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_dyn_cast_empty_if.v b/test_regress/t/t_class_dyn_cast_empty_if.v index 42a02fc02..2d2435018 100644 --- a/test_regress/t/t_class_dyn_cast_empty_if.v +++ b/test_regress/t/t_class_dyn_cast_empty_if.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 typedef class Derived; @@ -23,9 +23,9 @@ endclass module t; initial begin - Derived d = new("Hello"); - Base b = d; - Derived c = b.cast(); + automatic Derived d = new("Hello"); + automatic Base b = d; + automatic Derived c = b.cast(); if (d.get() != c.get()) $stop; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_class_enum.py b/test_regress/t/t_class_enum.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_enum.py +++ b/test_regress/t/t_class_enum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_enum.v b/test_regress/t/t_class_enum.v index 8b3b6b47f..f4147a18a 100644 --- a/test_regress/t/t_class_enum.v +++ b/test_regress/t/t_class_enum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_class_eq.py b/test_regress/t/t_class_eq.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_class_eq.py +++ b/test_regress/t/t_class_eq.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_eq.v b/test_regress/t/t_class_eq.v index d6738ae57..be9814153 100644 --- a/test_regress/t/t_class_eq.v +++ b/test_regress/t/t_class_eq.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(); diff --git a/test_regress/t/t_class_extends.py b/test_regress/t/t_class_extends.py index 952d410ef..8bbd29157 100755 --- a/test_regress/t/t_class_extends.py +++ b/test_regress/t/t_class_extends.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends.v b/test_regress/t/t_class_extends.v index 387fd50a9..85de6e686 100644 --- a/test_regress/t/t_class_extends.v +++ b/test_regress/t/t_class_extends.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef class Cls; diff --git a/test_regress/t/t_class_extends1.py b/test_regress/t/t_class_extends1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_extends1.py +++ b/test_regress/t/t_class_extends1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends1.v b/test_regress/t/t_class_extends1.v index 35574e614..021bacfb2 100644 --- a/test_regress/t/t_class_extends1.v +++ b/test_regress/t/t_class_extends1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base0; diff --git a/test_regress/t/t_class_extends2.py b/test_regress/t/t_class_extends2.py index 952d410ef..8bbd29157 100755 --- a/test_regress/t/t_class_extends2.py +++ b/test_regress/t/t_class_extends2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends2.v b/test_regress/t/t_class_extends2.v index 6031da919..3595601ae 100644 --- a/test_regress/t/t_class_extends2.v +++ b/test_regress/t/t_class_extends2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg; diff --git a/test_regress/t/t_class_extends_alias.out b/test_regress/t/t_class_extends_alias.out deleted file mode 100644 index f668ed890..000000000 --- a/test_regress/t/t_class_extends_alias.out +++ /dev/null @@ -1,5 +0,0 @@ -%Error-UNSUPPORTED: t/t_class_extends_alias.v:24:21: Unsupported: TYPEDEF 'foo_t' in 'class extends' - 24 | class bar extends foo_t; - | ^~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: Exiting due to diff --git a/test_regress/t/t_class_extends_alias.py b/test_regress/t/t_class_extends_alias.py index 31228c9a7..3cc73805c 100755 --- a/test_regress/t/t_class_extends_alias.py +++ b/test_regress/t/t_class_extends_alias.py @@ -1,16 +1,18 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap -test.scenarios('linter') +test.scenarios('simulator') -test.lint(fails=True, expect_filename=test.golden_filename) +test.compile() + +test.execute() test.passes() diff --git a/test_regress/t/t_class_extends_alias.v b/test_regress/t/t_class_extends_alias.v index 2e0ec59fe..e63b84f7c 100644 --- a/test_regress/t/t_class_extends_alias.v +++ b/test_regress/t/t_class_extends_alias.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_class_extends_aliased_real_bad.py b/test_regress/t/t_class_extends_aliased_real_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_extends_aliased_real_bad.py +++ b/test_regress/t/t_class_extends_aliased_real_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_aliased_real_bad.v b/test_regress/t/t_class_extends_aliased_real_bad.v index 5e992719e..a60a9b8e8 100644 --- a/test_regress/t/t_class_extends_aliased_real_bad.v +++ b/test_regress/t/t_class_extends_aliased_real_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_class_extends_arg.py b/test_regress/t/t_class_extends_arg.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_class_extends_arg.py +++ b/test_regress/t/t_class_extends_arg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_arg.v b/test_regress/t/t_class_extends_arg.v index cca83f85a..08f6323d2 100644 --- a/test_regress/t/t_class_extends_arg.v +++ b/test_regress/t/t_class_extends_arg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_class_extends_arg_super_bad.py b/test_regress/t/t_class_extends_arg_super_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_class_extends_arg_super_bad.py +++ b/test_regress/t/t_class_extends_arg_super_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_arg_super_bad.v b/test_regress/t/t_class_extends_arg_super_bad.v index b96cf5264..6dfd94fcb 100644 --- a/test_regress/t/t_class_extends_arg_super_bad.v +++ b/test_regress/t/t_class_extends_arg_super_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base; diff --git a/test_regress/t/t_class_extends_bad.py b/test_regress/t/t_class_extends_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_extends_bad.py +++ b/test_regress/t/t_class_extends_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_bad.v b/test_regress/t/t_class_extends_bad.v index 45f4de459..029b06535 100644 --- a/test_regress/t/t_class_extends_bad.v +++ b/test_regress/t/t_class_extends_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base1; diff --git a/test_regress/t/t_class_extends_colon.py b/test_regress/t/t_class_extends_colon.py index 952d410ef..8bbd29157 100755 --- a/test_regress/t/t_class_extends_colon.py +++ b/test_regress/t/t_class_extends_colon.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_colon.v b/test_regress/t/t_class_extends_colon.v index 01186db32..b1cd70a17 100644 --- a/test_regress/t/t_class_extends_colon.v +++ b/test_regress/t/t_class_extends_colon.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface class Icempty; diff --git a/test_regress/t/t_class_extends_default.py b/test_regress/t/t_class_extends_default.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_class_extends_default.py +++ b/test_regress/t/t_class_extends_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_default.v b/test_regress/t/t_class_extends_default.v index fc84c903b..2960054dd 100644 --- a/test_regress/t/t_class_extends_default.v +++ b/test_regress/t/t_class_extends_default.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base1; diff --git a/test_regress/t/t_class_extends_dot.py b/test_regress/t/t_class_extends_dot.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_class_extends_dot.py +++ b/test_regress/t/t_class_extends_dot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_dot.v b/test_regress/t/t_class_extends_dot.v index 70f89a925..c5f3fa1f6 100644 --- a/test_regress/t/t_class_extends_dot.v +++ b/test_regress/t/t_class_extends_dot.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_class_extends_int_param_bad.py b/test_regress/t/t_class_extends_int_param_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_extends_int_param_bad.py +++ b/test_regress/t/t_class_extends_int_param_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_int_param_bad.v b/test_regress/t/t_class_extends_int_param_bad.v index c28ddb417..abaad9b40 100644 --- a/test_regress/t/t_class_extends_int_param_bad.v +++ b/test_regress/t/t_class_extends_int_param_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_class_extends_nf_bad.out b/test_regress/t/t_class_extends_nf_bad.out index aa7a6cc54..d3a6993b3 100644 --- a/test_regress/t/t_class_extends_nf_bad.out +++ b/test_regress/t/t_class_extends_nf_bad.out @@ -7,4 +7,7 @@ : ... Suggested alternative: 'otFound2' 18 | class Cls2 extends Pkg::NotFound2; | ^~~~~~~~~ +%Error: t/t_class_extends_nf_bad.v:20:10: 'super' used on non-extended class (IEEE 1800-2023 8.15) + 20 | super.new(); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_extends_nf_bad.py b/test_regress/t/t_class_extends_nf_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_extends_nf_bad.py +++ b/test_regress/t/t_class_extends_nf_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_nf_bad.v b/test_regress/t/t_class_extends_nf_bad.v index bd62fa917..d2e274373 100644 --- a/test_regress/t/t_class_extends_nf_bad.v +++ b/test_regress/t/t_class_extends_nf_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg; @@ -16,6 +16,9 @@ class Cls extends IsNotFound; // BAD: not found endclass class Cls2 extends Pkg::NotFound2; // BAD: not found + function new; + super.new(); + endfunction endclass module t; diff --git a/test_regress/t/t_class_extends_param.py b/test_regress/t/t_class_extends_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_extends_param.py +++ b/test_regress/t/t_class_extends_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_param.v b/test_regress/t/t_class_extends_param.v index f8544aa80..60f879286 100644 --- a/test_regress/t/t_class_extends_param.v +++ b/test_regress/t/t_class_extends_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_class_extends_param_unused.py b/test_regress/t/t_class_extends_param_unused.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_extends_param_unused.py +++ b/test_regress/t/t_class_extends_param_unused.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_param_unused.v b/test_regress/t/t_class_extends_param_unused.v index b96569e77..6545002a0 100644 --- a/test_regress/t/t_class_extends_param_unused.v +++ b/test_regress/t/t_class_extends_param_unused.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo#(type T = logic) extends T; diff --git a/test_regress/t/t_class_extends_pkg_bad.py b/test_regress/t/t_class_extends_pkg_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_extends_pkg_bad.py +++ b/test_regress/t/t_class_extends_pkg_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_pkg_bad.v b/test_regress/t/t_class_extends_pkg_bad.v index 8939067b3..4aa06c039 100644 --- a/test_regress/t/t_class_extends_pkg_bad.v +++ b/test_regress/t/t_class_extends_pkg_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_class_extends_protect_ids.py b/test_regress/t/t_class_extends_protect_ids.py index f6fa53979..ac98e125a 100755 --- a/test_regress/t/t_class_extends_protect_ids.py +++ b/test_regress/t/t_class_extends_protect_ids.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_rec_bad.py b/test_regress/t/t_class_extends_rec_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_extends_rec_bad.py +++ b/test_regress/t/t_class_extends_rec_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_rec_bad.v b/test_regress/t/t_class_extends_rec_bad.v index 87a708c32..10d916b50 100644 --- a/test_regress/t/t_class_extends_rec_bad.v +++ b/test_regress/t/t_class_extends_rec_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class RecursiveExtCls extends RecursiveExtCls; diff --git a/test_regress/t/t_class_extends_this.py b/test_regress/t/t_class_extends_this.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_extends_this.py +++ b/test_regress/t/t_class_extends_this.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_this.v b/test_regress/t/t_class_extends_this.v index 8e3506f34..e36fe398a 100644 --- a/test_regress/t/t_class_extends_this.v +++ b/test_regress/t/t_class_extends_this.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef class Cls; diff --git a/test_regress/t/t_class_extends_this3.py b/test_regress/t/t_class_extends_this3.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_extends_this3.py +++ b/test_regress/t/t_class_extends_this3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_this3.v b/test_regress/t/t_class_extends_this3.v index 29e5303c2..e00f279a1 100644 --- a/test_regress/t/t_class_extends_this3.v +++ b/test_regress/t/t_class_extends_this3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef class Cls; diff --git a/test_regress/t/t_class_extends_this_protect_ids.py b/test_regress/t/t_class_extends_this_protect_ids.py index 8ed657472..aeae3a747 100755 --- a/test_regress/t/t_class_extends_this_protect_ids.py +++ b/test_regress/t/t_class_extends_this_protect_ids.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_vsyment.py b/test_regress/t/t_class_extends_vsyment.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_class_extends_vsyment.py +++ b/test_regress/t/t_class_extends_vsyment.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extends_vsyment.v b/test_regress/t/t_class_extends_vsyment.v index ac17ba1cf..343780d2e 100644 --- a/test_regress/t/t_class_extends_vsyment.v +++ b/test_regress/t/t_class_extends_vsyment.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_class_extern.py b/test_regress/t/t_class_extern.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_extern.py +++ b/test_regress/t/t_class_extern.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extern.v b/test_regress/t/t_class_extern.v index da50973d9..15ac405ac 100644 --- a/test_regress/t/t_class_extern.v +++ b/test_regress/t/t_class_extern.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; @@ -87,8 +87,8 @@ endtask module t; initial begin - Cls c = new; - Cls::SubCls subc = new; + automatic Cls c = new; + automatic Cls::SubCls subc = new; c.ext_t_i(2); if (c.ext_f_np() != 1) $stop; if (c.ext_f_p() != 2) $stop; diff --git a/test_regress/t/t_class_extern2.py b/test_regress/t/t_class_extern2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_extern2.py +++ b/test_regress/t/t_class_extern2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extern2.v b/test_regress/t/t_class_extern2.v index 10f46a997..857e43346 100644 --- a/test_regress/t/t_class_extern2.v +++ b/test_regress/t/t_class_extern2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class One #( diff --git a/test_regress/t/t_class_extern_args.py b/test_regress/t/t_class_extern_args.py index 3d49093ba..1bd86cd48 100755 --- a/test_regress/t/t_class_extern_args.py +++ b/test_regress/t/t_class_extern_args.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extern_args_bad.py b/test_regress/t/t_class_extern_args_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_extern_args_bad.py +++ b/test_regress/t/t_class_extern_args_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extern_args_bad.v b/test_regress/t/t_class_extern_args_bad.v index 16e04d7ae..68631efcd 100644 --- a/test_regress/t/t_class_extern_args_bad.v +++ b/test_regress/t/t_class_extern_args_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_extern_bad.py b/test_regress/t/t_class_extern_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_extern_bad.py +++ b/test_regress/t/t_class_extern_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extern_bad.v b/test_regress/t/t_class_extern_bad.v index 58d6dbbdb..8f1a426e2 100644 --- a/test_regress/t/t_class_extern_bad.v +++ b/test_regress/t/t_class_extern_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base1; diff --git a/test_regress/t/t_class_extern_typeref.py b/test_regress/t/t_class_extern_typeref.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_class_extern_typeref.py +++ b/test_regress/t/t_class_extern_typeref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_extern_typeref.v b/test_regress/t/t_class_extern_typeref.v index cabfb23ea..0fa46ba6d 100644 --- a/test_regress/t/t_class_extern_typeref.v +++ b/test_regress/t/t_class_extern_typeref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class uvm_process_guard #( diff --git a/test_regress/t/t_class_field_name.py b/test_regress/t/t_class_field_name.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_field_name.py +++ b/test_regress/t/t_class_field_name.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_field_name.v b/test_regress/t/t_class_field_name.v index 54eb1b5d3..96e575836 100644 --- a/test_regress/t/t_class_field_name.v +++ b/test_regress/t/t_class_field_name.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; @@ -11,7 +11,7 @@ endclass module t; initial begin - Cls cls = new; + automatic Cls cls = new; cls.queue = 1; if (cls.queue == 1) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_class_format.out b/test_regress/t/t_class_format.out index 219ddc86b..8a3a7a480 100644 --- a/test_regress/t/t_class_format.out +++ b/test_regress/t/t_class_format.out @@ -1,4 +1,7 @@ ''{b:'h1, i:'h2a, carray4:'{'h11, 'h22, 'h33, 'h44}, cwide:'{'h0, 'h0}, name:"object_name", r:2.2}' ''{b:'h1, i:'h2a, carray4:'{'h911, 'h922, 'h933, 'h944}, cwide:'{'h0, 'h0}, name:"object_name", r:2.2}' DEBUG: object_name (@0) message +''{m_in_a:'h0, m_b:null, m_in_base:'h0}' +''{m_in_a:'h0, m_b:$unit::ClsB, m_in_base:'h0}' +''{m_in_a:'h0, m_b:$unit::ClsB, m_in_base:'h0}' *-* All Finished *-* diff --git a/test_regress/t/t_class_format.py b/test_regress/t/t_class_format.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_class_format.py +++ b/test_regress/t/t_class_format.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_format.v b/test_regress/t/t_class_format.v index ab49286cb..76e14b879 100644 --- a/test_regress/t/t_class_format.v +++ b/test_regress/t/t_class_format.v @@ -1,49 +1,78 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -`ifdef verilator - `define stop $stop -`else - `define stop -`endif -`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); - class Cls; - bit b; - int i; - bit [15:0] carray4 [4]; - bit [64:0] cwide[2]; - string name; - real r; - task debug(); - $display("DEBUG: %s (@%0t) %s", this.name, $realtime, "message"); - endtask + bit b; + int i; + bit [15:0] carray4[4]; + bit [64:0] cwide[2]; + string name; + real r; + task debug(); + $display("DEBUG: %s (@%0t) %s", this.name, $realtime, "message"); + endtask +endclass + +class Base; + int m_in_base; + virtual function string fs(input string add = "default"); + static string s_f = "foo"; + fs = {s_f, add}; + endfunction + virtual function string other(input string add = "default"); + string other = "other"; + other = {other, fs(add)}; + endfunction +endclass + +class ClsA extends Base; + int m_in_a; + Base m_b; +endclass + +class ClsB extends Base; + int m_in_b; + Base m_a; endclass module t; - initial begin - Cls c; - c = new; - c.b = '1; - c.i = 42; - c.r = 2.2; - c.name = "object_name"; + initial begin + Cls c; + ClsA ca; + ClsB cb; - c.carray4[0] = 16'h11; - c.carray4[1] = 16'h22; - c.carray4[2] = 16'h33; - c.carray4[3] = 16'h44; - $display("'%p'", c); + c = new; + c.b = '1; + c.i = 42; + c.r = 2.2; + c.name = "object_name"; - c.carray4 = '{16'h911, 16'h922, 16'h933, 16'h944}; - $display("'%p'", c); + c.carray4[0] = 16'h11; + c.carray4[1] = 16'h22; + c.carray4[2] = 16'h33; + c.carray4[3] = 16'h44; + $display("'%p'", c); - c.debug(); + c.carray4 = '{16'h911, 16'h922, 16'h933, 16'h944}; + $display("'%p'", c); - $write("*-* All Finished *-*\n"); - $finish; - end + c.debug(); + + ca = new; + if (ca.fs("-s") !== "foo-s") $stop; // So not optimized away + if (ca.other("-o") !== "otherfoo-o") $stop; // So not optimized away + + cb = new; + $display("'%p'", ca); + ca.m_b = cb; + $display("'%p'", ca); + cb.m_a = ca; // Circular + $display("'%p'", ca); + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_forward.py b/test_regress/t/t_class_forward.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_forward.py +++ b/test_regress/t/t_class_forward.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_forward.v b/test_regress/t/t_class_forward.v index 9abd6ce39..590187350 100644 --- a/test_regress/t/t_class_forward.v +++ b/test_regress/t/t_class_forward.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package P; diff --git a/test_regress/t/t_class_func_arg_unused.py b/test_regress/t/t_class_func_arg_unused.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_func_arg_unused.py +++ b/test_regress/t/t_class_func_arg_unused.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_func_arg_unused.v b/test_regress/t/t_class_func_arg_unused.v index df6a1c9ac..5a31df2d7 100644 --- a/test_regress/t/t_class_func_arg_unused.v +++ b/test_regress/t/t_class_func_arg_unused.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; @@ -19,7 +19,7 @@ endpackage module t; initial begin - uvm_pkg::uvm_reg_field c = new; + automatic uvm_pkg::uvm_reg_field c = new; c.configure(1, 0); c.configure(0, 0); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_class_func_dot.py b/test_regress/t/t_class_func_dot.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_func_dot.py +++ b/test_regress/t/t_class_func_dot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_func_dot.v b/test_regress/t/t_class_func_dot.v index e35b5dbd4..8594b8d43 100644 --- a/test_regress/t/t_class_func_dot.v +++ b/test_regress/t/t_class_func_dot.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls_report_object; diff --git a/test_regress/t/t_class_func_nvoid_bad.py b/test_regress/t/t_class_func_nvoid_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_func_nvoid_bad.py +++ b/test_regress/t/t_class_func_nvoid_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_func_nvoid_bad.v b/test_regress/t/t_class_func_nvoid_bad.v index f78dcb08e..b693c29b6 100644 --- a/test_regress/t/t_class_func_nvoid_bad.v +++ b/test_regress/t/t_class_func_nvoid_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_class_func_static_bad.py b/test_regress/t/t_class_func_static_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_class_func_static_bad.py +++ b/test_regress/t/t_class_func_static_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_func_static_bad.v b/test_regress/t/t_class_func_static_bad.v index b5c675fab..f8253c8f8 100644 --- a/test_regress/t/t_class_func_static_bad.v +++ b/test_regress/t/t_class_func_static_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_class_fwd_cc.py b/test_regress/t/t_class_fwd_cc.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_class_fwd_cc.py +++ b/test_regress/t/t_class_fwd_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_fwd_cc.v b/test_regress/t/t_class_fwd_cc.v index cfb6c3696..c5ed2db27 100644 --- a/test_regress/t/t_class_fwd_cc.v +++ b/test_regress/t/t_class_fwd_cc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg; diff --git a/test_regress/t/t_class_hier_construction.py b/test_regress/t/t_class_hier_construction.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_class_hier_construction.py +++ b/test_regress/t/t_class_hier_construction.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_hier_construction.v b/test_regress/t/t_class_hier_construction.v index 116f4815c..6c7edda44 100644 --- a/test_regress/t/t_class_hier_construction.v +++ b/test_regress/t/t_class_hier_construction.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Petr Nohavica +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Petr Nohavica // SPDX-License-Identifier: CC0-1.0 // verilog_format: off @@ -72,10 +72,10 @@ endclass module t; initial begin - sky_class s = new("ahoj"); - bottom_class b = s; - top_class t = s; - IMid im; + automatic sky_class s = new("ahoj"); + automatic bottom_class b = s; + automatic top_class t = s; + automatic IMid im; `checks(b.name, "middle ahoj 42"); `checks(s.name, "middle ahoj 42"); diff --git a/test_regress/t/t_class_if_assign.py b/test_regress/t/t_class_if_assign.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_if_assign.py +++ b/test_regress/t/t_class_if_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_if_assign.v b/test_regress/t/t_class_if_assign.v index fda7ce354..cfa9226d4 100644 --- a/test_regress/t/t_class_if_assign.v +++ b/test_regress/t/t_class_if_assign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; @@ -25,9 +25,9 @@ endclass module t; initial begin - Cls cls = new; - ExtendCls ext_cls = new; - AnotherExtendCls an_ext_cls = new; + automatic Cls cls = new; + automatic ExtendCls ext_cls = new; + automatic AnotherExtendCls an_ext_cls = new; if (cls.x == 1) cls = ext_cls; else cls = an_ext_cls; diff --git a/test_regress/t/t_class_imp2.py b/test_regress/t/t_class_imp2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_imp2.py +++ b/test_regress/t/t_class_imp2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_imp2.v b/test_regress/t/t_class_imp2.v index 416b8e86d..92be1b878 100644 --- a/test_regress/t/t_class_imp2.v +++ b/test_regress/t/t_class_imp2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_class_inc.py b/test_regress/t/t_class_inc.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_inc.py +++ b/test_regress/t/t_class_inc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_inc.v b/test_regress/t/t_class_inc.v index 446df0c3f..3c5a59c58 100644 --- a/test_regress/t/t_class_inc.v +++ b/test_regress/t/t_class_inc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base #(type T = integer); diff --git a/test_regress/t/t_class_init_order.py b/test_regress/t/t_class_init_order.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_class_init_order.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_init_order.v b/test_regress/t/t_class_init_order.v new file mode 100644 index 000000000..13a7b6fad --- /dev/null +++ b/test_regress/t/t_class_init_order.v @@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t; + + class uvm_coreservice; + static uvm_coreservice inst; + + function new(string name); + endfunction + + static function uvm_coreservice get(); + if (inst == null) begin + inst = new("cs-base"); + end + return inst; + endfunction + + virtual function string get_factory(); + return "factory"; + endfunction + endclass + + class uvm_test; + string m_name; + string s0 = {m_name, "0"}; // Before new(); this must get "0" not "name0" + function new(string name); + m_name = name; + endfunction + endclass + + class test extends uvm_test; + + string s1 = {s0, "1"}; + string s2 = {s1, "2"}; + + uvm_coreservice cs = uvm_coreservice::get(); + // Below assumes that the above 'cs' executes first. + // Most simulators require this ordering, but some allow arbitrary order + // This would require dataflow analysis, so for now Verilator requires user ordering + string factory = cs.get_factory(); + + function new(string name); + super.new(name); + endfunction + endclass + initial begin + test t; + string s; + + t = new("test"); + `checks(t.s0, "0"); + `checks(t.s1, "01"); + `checks(t.s2, "012"); + s = t.factory; + `checks(s, "factory"); + + $finish; + end +endmodule diff --git a/test_regress/t/t_class_link_delay.py b/test_regress/t/t_class_link_delay.py index eb6589504..2182ebf7f 100755 --- a/test_regress/t/t_class_link_delay.py +++ b/test_regress/t/t_class_link_delay.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_link_delay.v b/test_regress/t/t_class_link_delay.v index 85651289b..834031c92 100644 --- a/test_regress/t/t_class_link_delay.v +++ b/test_regress/t/t_class_link_delay.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_class_link_delay2.py b/test_regress/t/t_class_link_delay2.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_class_link_delay2.py +++ b/test_regress/t/t_class_link_delay2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_link_delay2.v b/test_regress/t/t_class_link_delay2.v index 70ed0e502..657854af0 100644 --- a/test_regress/t/t_class_link_delay2.v +++ b/test_regress/t/t_class_link_delay2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pk1; diff --git a/test_regress/t/t_class_local.py b/test_regress/t/t_class_local.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_local.py +++ b/test_regress/t/t_class_local.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_local.v b/test_regress/t/t_class_local.v index d04455c68..e9cb4ae9a 100644 --- a/test_regress/t/t_class_local.v +++ b/test_regress/t/t_class_local.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_local_bad.py b/test_regress/t/t_class_local_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_local_bad.py +++ b/test_regress/t/t_class_local_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_local_bad.v b/test_regress/t/t_class_local_bad.v index 1852577cd..6af613062 100644 --- a/test_regress/t/t_class_local_bad.v +++ b/test_regress/t/t_class_local_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Let context messages easily know if given line is expected ok or bad diff --git a/test_regress/t/t_class_local_nested_bad.py b/test_regress/t/t_class_local_nested_bad.py index 710a094ab..4ea94519e 100755 --- a/test_regress/t/t_class_local_nested_bad.py +++ b/test_regress/t/t_class_local_nested_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_local_nested_bad.v b/test_regress/t/t_class_local_nested_bad.v index 3403683b5..5adcc9b2c 100644 --- a/test_regress/t/t_class_local_nested_bad.v +++ b/test_regress/t/t_class_local_nested_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class NodeList; @@ -17,7 +17,7 @@ endclass module t; initial begin - NodeList n = new; + automatic NodeList n = new; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_class_local_protect_ids.py b/test_regress/t/t_class_local_protect_ids.py index 81b18d6cc..0f072e745 100755 --- a/test_regress/t/t_class_local_protect_ids.py +++ b/test_regress/t/t_class_local_protect_ids.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_local_typedef_bad.py b/test_regress/t/t_class_local_typedef_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_local_typedef_bad.py +++ b/test_regress/t/t_class_local_typedef_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_local_typedef_bad.v b/test_regress/t/t_class_local_typedef_bad.v old mode 100755 new mode 100644 index 1688e7266..c7b05fccf --- a/test_regress/t/t_class_local_typedef_bad.v +++ b/test_regress/t/t_class_local_typedef_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_class_member_bad.py b/test_regress/t/t_class_member_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_member_bad.py +++ b/test_regress/t/t_class_member_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_member_bad.v b/test_regress/t/t_class_member_bad.v index cffa194c5..c6e904ba8 100644 --- a/test_regress/t/t_class_member_bad.v +++ b/test_regress/t/t_class_member_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base1; diff --git a/test_regress/t/t_class_member_bad2.py b/test_regress/t/t_class_member_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_member_bad2.py +++ b/test_regress/t/t_class_member_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_member_bad2.v b/test_regress/t/t_class_member_bad2.v index 70fc483ad..2d1814d5d 100644 --- a/test_regress/t/t_class_member_bad2.v +++ b/test_regress/t/t_class_member_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class ClsDup; diff --git a/test_regress/t/t_class_member_sens.py b/test_regress/t/t_class_member_sens.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_class_member_sens.py +++ b/test_regress/t/t_class_member_sens.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_member_sens.v b/test_regress/t/t_class_member_sens.v index f178f995b..869967f99 100644 --- a/test_regress/t/t_class_member_sens.v +++ b/test_regress/t/t_class_member_sens.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_class_member_var_virt_bad.py b/test_regress/t/t_class_member_var_virt_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_member_var_virt_bad.py +++ b/test_regress/t/t_class_member_var_virt_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_member_var_virt_bad.v b/test_regress/t/t_class_member_var_virt_bad.v index 492a70785..8a7673452 100644 --- a/test_regress/t/t_class_member_var_virt_bad.v +++ b/test_regress/t/t_class_member_var_virt_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_class_membersel_int.py b/test_regress/t/t_class_membersel_int.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_membersel_int.py +++ b/test_regress/t/t_class_membersel_int.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_membersel_int.v b/test_regress/t/t_class_membersel_int.v index 68e70f22b..f321cd0ee 100644 --- a/test_regress/t/t_class_membersel_int.v +++ b/test_regress/t/t_class_membersel_int.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_method.py b/test_regress/t/t_class_method.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_method.py +++ b/test_regress/t/t_class_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_method.v b/test_regress/t/t_class_method.v index 8e49c5fa5..53a35c1ec 100644 --- a/test_regress/t/t_class_method.v +++ b/test_regress/t/t_class_method.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef class Cls; diff --git a/test_regress/t/t_class_method_bad.py b/test_regress/t/t_class_method_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_method_bad.py +++ b/test_regress/t/t_class_method_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_method_bad.v b/test_regress/t/t_class_method_bad.v index f81efaba6..f8600d6c6 100644 --- a/test_regress/t/t_class_method_bad.v +++ b/test_regress/t/t_class_method_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base1; diff --git a/test_regress/t/t_class_method_str_literal.py b/test_regress/t/t_class_method_str_literal.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_method_str_literal.py +++ b/test_regress/t/t_class_method_str_literal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_method_str_literal.v b/test_regress/t/t_class_method_str_literal.v index 54dec5ca5..688e6ff76 100644 --- a/test_regress/t/t_class_method_str_literal.v +++ b/test_regress/t/t_class_method_str_literal.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; @@ -36,8 +36,8 @@ endclass initial begin - T t_c = new; - uvm_reg u_r = new; + automatic T t_c = new; + automatic uvm_reg u_r = new; if (u_r.get_string() != "user backdoor") $stop; if (t_c.return_str("A") != "A") $stop; if (t_c.static_return_str("B") != "B") $stop; diff --git a/test_regress/t/t_class_method_struct.py b/test_regress/t/t_class_method_struct.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_method_struct.py +++ b/test_regress/t/t_class_method_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_method_struct.v b/test_regress/t/t_class_method_struct.v index b8c220727..70c6a68b8 100644 --- a/test_regress/t/t_class_method_struct.v +++ b/test_regress/t/t_class_method_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef struct packed { @@ -22,8 +22,8 @@ endclass : Cls module t; initial begin - Cls c = new; - my_struct s = c.get_struct; + automatic Cls c = new; + automatic my_struct s = c.get_struct; if (s.x != 1) $stop; if (s.y != 2) $stop; if (s.z != 3) $stop; diff --git a/test_regress/t/t_class_mispure_bad.py b/test_regress/t/t_class_mispure_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_mispure_bad.py +++ b/test_regress/t/t_class_mispure_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_mispure_bad.v b/test_regress/t/t_class_mispure_bad.v index 438361a93..453b457f3 100644 --- a/test_regress/t/t_class_mispure_bad.v +++ b/test_regress/t/t_class_mispure_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 virtual class Base; @@ -14,7 +14,7 @@ endclass module t; initial begin - Bar obj = new(); + automatic Bar obj = new(); obj.pvfunc(); $stop; end diff --git a/test_regress/t/t_class_misstatic_bad.out b/test_regress/t/t_class_misstatic_bad.out index 368cfffae..171d60fed 100644 --- a/test_regress/t/t_class_misstatic_bad.out +++ b/test_regress/t/t_class_misstatic_bad.out @@ -1,14 +1,22 @@ -%Error: t/t_class_misstatic_bad.v:31:5: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) - : ... note: In instance 't' - 31 | nonstatic(); - | ^~~~~~~~~ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_misstatic_bad.v:38:10: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) +%Error: t/t_class_misstatic_bad.v:23:10: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) : ... note: In instance 't' - 38 | Cls::nonstatic(); + 23 | Cls::nonstatic(); | ^~~~~~~~~ -%Error: t/t_class_misstatic_bad.v:44:10: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_class_misstatic_bad.v:24:10: Cannot call non-static member function 'nonstatic_retcls' without object (IEEE 1800-2023 8.10) : ... note: In instance 't' - 44 | Cls::nonstatic(); + 24 | Cls::nonstatic_retcls(); + | ^~~~~~~~~~~~~~~~ +%Error: t/t_class_misstatic_bad.v:35:5: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) + : ... note: In instance 't' + 35 | nonstatic(); + | ^~~~~~~~~ +%Error: t/t_class_misstatic_bad.v:45:10: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) + : ... note: In instance 't' + 45 | Cls::nonstatic(); + | ^~~~~~~~~ +%Error: t/t_class_misstatic_bad.v:51:10: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) + : ... note: In instance 't' + 51 | Cls::nonstatic(); | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_misstatic_bad.py b/test_regress/t/t_class_misstatic_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_misstatic_bad.py +++ b/test_regress/t/t_class_misstatic_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_misstatic_bad.v b/test_regress/t/t_class_misstatic_bad.v index 3f0cbca1c..c5a56bef3 100644 --- a/test_regress/t/t_class_misstatic_bad.v +++ b/test_regress/t/t_class_misstatic_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; @@ -11,6 +11,9 @@ class Cls; endfunction function void nonstatic(); endfunction + function Cls nonstatic_retcls(); + return null; + endfunction static function void isst(); endfunction endclass @@ -18,6 +21,7 @@ endclass class Bar; function void bar(); Cls::nonstatic(); // <--- bad static ref + Cls::nonstatic_retcls(); // <--- bad static ref Cls::isst(); endfunction endclass @@ -31,6 +35,9 @@ class Extends extends Cls; nonstatic(); // <--- bad static ref isst(); endfunction + function new(); + Cls c = super.nonstatic_retcls(); + endfunction endclass module t; @@ -39,7 +46,7 @@ module t; Cls::isst(); endfunction initial begin - Bar obj = new(); + automatic Bar obj = new(); obj.bar(); Cls::nonstatic(); // <--- bad static ref Cls::isst(); diff --git a/test_regress/t/t_class_mod_bad.py b/test_regress/t/t_class_mod_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_mod_bad.py +++ b/test_regress/t/t_class_mod_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_mod_bad.v b/test_regress/t/t_class_mod_bad.v index 26c262031..5ca4ebe28 100644 --- a/test_regress/t/t_class_mod_bad.v +++ b/test_regress/t/t_class_mod_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTITOP diff --git a/test_regress/t/t_class_modscope.py b/test_regress/t/t_class_modscope.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_class_modscope.py +++ b/test_regress/t/t_class_modscope.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_modscope.v b/test_regress/t/t_class_modscope.v index 8caa24dbf..83a14cb9f 100644 --- a/test_regress/t/t_class_modscope.v +++ b/test_regress/t/t_class_modscope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_class_module.py b/test_regress/t/t_class_module.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_module.py +++ b/test_regress/t/t_class_module.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_module.v b/test_regress/t/t_class_module.v index cda33725b..31bc9b284 100644 --- a/test_regress/t/t_class_module.v +++ b/test_regress/t/t_class_module.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_class_name.py b/test_regress/t/t_class_name.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_name.py +++ b/test_regress/t/t_class_name.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_name.v b/test_regress/t/t_class_name.v index 578092fb2..cc38300df 100644 --- a/test_regress/t/t_class_name.v +++ b/test_regress/t/t_class_name.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef verilator diff --git a/test_regress/t/t_class_nested.py b/test_regress/t/t_class_nested.py index 49d728ea8..7b9547ce2 100755 --- a/test_regress/t/t_class_nested.py +++ b/test_regress/t/t_class_nested.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_nested.v b/test_regress/t/t_class_nested.v index 93a48d154..10c2f547d 100644 --- a/test_regress/t/t_class_nested.v +++ b/test_regress/t/t_class_nested.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class NodeList; @@ -46,14 +46,14 @@ endclass module t; initial begin - NodeList n = new; - NodeList::Node n1 = new; - NodeList::Node n2 = new; - NodeTree tr = new; - NodeTree::Node t1 = new; - NodeTree::Node t2 = new; - Outer o = new; - Outer::Inner i = new; + automatic NodeList n = new; + automatic NodeList::Node n1 = new; + automatic NodeList::Node n2 = new; + automatic NodeTree tr = new; + automatic NodeTree::Node t1 = new; + automatic NodeTree::Node t2 = new; + automatic Outer o = new; + automatic Outer::Inner i = new; i.innerMethod(o); diff --git a/test_regress/t/t_class_nested_link.py b/test_regress/t/t_class_nested_link.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_nested_link.py +++ b/test_regress/t/t_class_nested_link.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_nested_link.v b/test_regress/t/t_class_nested_link.v index def276cc9..f7bcc730a 100644 --- a/test_regress/t/t_class_nested_link.v +++ b/test_regress/t/t_class_nested_link.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 /// Test for bug4553 diff --git a/test_regress/t/t_class_new.py b/test_regress/t/t_class_new.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_new.py +++ b/test_regress/t/t_class_new.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new.v b/test_regress/t/t_class_new.v index 7dc2540c6..981033ecf 100644 --- a/test_regress/t/t_class_new.v +++ b/test_regress/t/t_class_new.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class ClsNoArg; @@ -63,7 +63,7 @@ module t; ClsArg c2; Cls2Arg c3; Cls2Arg c4; - ClsNoArg::InnerNoArg c5 = new; + automatic ClsNoArg::InnerNoArg c5 = new; c1 = new; if (c1.imembera != 5) $stop; diff --git a/test_regress/t/t_class_new_bad.py b/test_regress/t/t_class_new_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_new_bad.py +++ b/test_regress/t/t_class_new_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new_bad.v b/test_regress/t/t_class_new_bad.v index 245290bf8..1e9a3fb03 100644 --- a/test_regress/t/t_class_new_bad.v +++ b/test_regress/t/t_class_new_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_class_new_copy_null_bad.out b/test_regress/t/t_class_new_copy_null_bad.out new file mode 100644 index 000000000..72d6f9298 --- /dev/null +++ b/test_regress/t/t_class_new_copy_null_bad.out @@ -0,0 +1,2 @@ +%Error: t/t_class_new_copy_null_bad.v:16: Null pointer dereferenced +Aborting... diff --git a/test_regress/t/t_class_new_copy_null_bad.py b/test_regress/t/t_class_new_copy_null_bad.py new file mode 100755 index 000000000..346dfe57a --- /dev/null +++ b/test_regress/t/t_class_new_copy_null_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_new_copy_null_bad.v b/test_regress/t/t_class_new_copy_null_bad.v new file mode 100644 index 000000000..c89a703e0 --- /dev/null +++ b/test_regress/t/t_class_new_copy_null_bad.v @@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +class Base; + int value; +endclass + +module t; + Base b; + Base a; + initial begin + b = null; + a = new b; // BAD: null handle dereference (IEEE 8.7) + if (a != null) $write("unexpected clone\n"); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_class_new_copy_polymorphism.py b/test_regress/t/t_class_new_copy_polymorphism.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_class_new_copy_polymorphism.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_new_copy_polymorphism.v b/test_regress/t/t_class_new_copy_polymorphism.v new file mode 100644 index 000000000..ba0a530e1 --- /dev/null +++ b/test_regress/t/t_class_new_copy_polymorphism.v @@ -0,0 +1,101 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// Test that `new ` (shallow copy) preserves the runtime type +// of the source object, per IEEE 1800-2017 8.7. + +// verilog_format: off +`define stop $stop +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +class Base; + int value; + function new(); + value = 10; + endfunction + virtual function string get_type(); + return "BASE"; + endfunction + virtual function int get_id(); + return 1; + endfunction +endclass + +class Derived extends Base; + int extra; + function new(); + super.new(); + value = 20; + extra = 99; + endfunction + virtual function string get_type(); + return "DERIVED"; + endfunction + virtual function int get_id(); + return 2; + endfunction +endclass + +class GrandChild extends Derived; + function new(); + super.new(); + value = 30; + extra = 88; + endfunction + virtual function string get_type(); + return "GRANDCHILD"; + endfunction + virtual function int get_id(); + return 3; + endfunction +endclass + +module t; + initial begin + Base b; + Derived d; + Base copy; + + // Test 1: Copy via base handle pointing to Derived + d = new(); + b = d; + copy = new b; + `checks(copy.get_type(), "DERIVED"); + `checkd(copy.get_id(), 2); + `checkd(copy.value, 20); + + // Test 2: Verify it's a true copy (not alias) + copy.value = 999; + `checkd(d.value, 20); + + // Test 3: Copy via base handle pointing to GrandChild + begin + GrandChild gc; + gc = new(); + b = gc; + copy = new b; + `checks(copy.get_type(), "GRANDCHILD"); + `checkd(copy.get_id(), 3); + `checkd(copy.value, 30); + end + + // Test 4: Copy of base-type object (no polymorphism, still works) + begin + Base b2; + Base copy2; + b2 = new(); + copy2 = new b2; + `checks(copy2.get_type(), "BASE"); + `checkd(copy2.get_id(), 1); + `checkd(copy2.value, 10); + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_class_new_default.py b/test_regress/t/t_class_new_default.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_class_new_default.py +++ b/test_regress/t/t_class_new_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new_default.v b/test_regress/t/t_class_new_default.v index 627f3d261..213874f14 100644 --- a/test_regress/t/t_class_new_default.v +++ b/test_regress/t/t_class_new_default.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_class_new_noparen.py b/test_regress/t/t_class_new_noparen.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_new_noparen.py +++ b/test_regress/t/t_class_new_noparen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new_noparen.v b/test_regress/t/t_class_new_noparen.v index 520fa9060..299faf90a 100644 --- a/test_regress/t/t_class_new_noparen.v +++ b/test_regress/t/t_class_new_noparen.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class u_object; diff --git a/test_regress/t/t_class_new_ref_bad.out b/test_regress/t/t_class_new_ref_bad.out index bd21bae13..b949f859e 100644 --- a/test_regress/t/t_class_new_ref_bad.out +++ b/test_regress/t/t_class_new_ref_bad.out @@ -7,8 +7,8 @@ : ... note: In instance 't' 17 | txn_type_t copy = new txn; | ^~~ -%Error: t/t_class_new_ref_bad.v:26:21: Assign RHS expects a CLASSREFDTYPE 'Base', got BASICDTYPE 'int' +%Error: t/t_class_new_ref_bad.v:26:31: Assign RHS expects a CLASSREFDTYPE 'Base', got BASICDTYPE 'int' : ... note: In instance 't' - 26 | Base b = Cls::generate_txn(); - | ^~~~~~~~~~~~ + 26 | automatic Base b = Cls::generate_txn(); + | ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_new_ref_bad.py b/test_regress/t/t_class_new_ref_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_new_ref_bad.py +++ b/test_regress/t/t_class_new_ref_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new_ref_bad.v b/test_regress/t/t_class_new_ref_bad.v index ef02724c6..fbab68617 100644 --- a/test_regress/t/t_class_new_ref_bad.v +++ b/test_regress/t/t_class_new_ref_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base; @@ -23,7 +23,7 @@ endclass module t; initial begin - Base b = Cls::generate_txn(); + automatic Base b = Cls::generate_txn(); $display("%p", b); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_class_new_return.py b/test_regress/t/t_class_new_return.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_new_return.py +++ b/test_regress/t/t_class_new_return.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new_return.v b/test_regress/t/t_class_new_return.v index 2ee65b978..db38a2bfc 100644 --- a/test_regress/t/t_class_new_return.v +++ b/test_regress/t/t_class_new_return.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_class_new_scoped.py b/test_regress/t/t_class_new_scoped.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_class_new_scoped.py +++ b/test_regress/t/t_class_new_scoped.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new_scoped.v b/test_regress/t/t_class_new_scoped.v index 79bcef06c..620e2c524 100644 --- a/test_regress/t/t_class_new_scoped.v +++ b/test_regress/t/t_class_new_scoped.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_class_new_scoped_bad.py b/test_regress/t/t_class_new_scoped_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_new_scoped_bad.py +++ b/test_regress/t/t_class_new_scoped_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new_scoped_bad.v b/test_regress/t/t_class_new_scoped_bad.v index bf9c78f59..19f20889a 100644 --- a/test_regress/t/t_class_new_scoped_bad.v +++ b/test_regress/t/t_class_new_scoped_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_class_new_supernfirst_bad.py b/test_regress/t/t_class_new_supernfirst_bad.py index ebbd9c2d6..4ead528bc 100755 --- a/test_regress/t/t_class_new_supernfirst_bad.py +++ b/test_regress/t/t_class_new_supernfirst_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new_supernfirst_bad.v b/test_regress/t/t_class_new_supernfirst_bad.v index 1728b4776..5abf35cff 100644 --- a/test_regress/t/t_class_new_supernfirst_bad.v +++ b/test_regress/t/t_class_new_supernfirst_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class base_reg_block; @@ -23,7 +23,7 @@ endclass module t; initial begin - spi_reg_block test = new; + automatic spi_reg_block test = new; $finish; end endmodule diff --git a/test_regress/t/t_class_new_this.py b/test_regress/t/t_class_new_this.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_new_this.py +++ b/test_regress/t/t_class_new_this.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new_this.v b/test_regress/t/t_class_new_this.v index 01e230494..70211bb83 100644 --- a/test_regress/t/t_class_new_this.v +++ b/test_regress/t/t_class_new_this.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface class ICls; diff --git a/test_regress/t/t_class_new_typed.py b/test_regress/t/t_class_new_typed.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_new_typed.py +++ b/test_regress/t/t_class_new_typed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_new_typed.v b/test_regress/t/t_class_new_typed.v index e2a8c5bdf..b870a8b59 100644 --- a/test_regress/t/t_class_new_typed.v +++ b/test_regress/t/t_class_new_typed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_class_null_bad.py b/test_regress/t/t_class_null_bad.py index 2fdd6e92d..0dbd253f9 100755 --- a/test_regress/t/t_class_null_bad.py +++ b/test_regress/t/t_class_null_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_null_bad.v b/test_regress/t/t_class_null_bad.v index cd0d60c0c..75f06abe6 100644 --- a/test_regress/t/t_class_null_bad.v +++ b/test_regress/t/t_class_null_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_null_struct.py b/test_regress/t/t_class_null_struct.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_null_struct.py +++ b/test_regress/t/t_class_null_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_null_struct.v b/test_regress/t/t_class_null_struct.v index e5fcc585b..172a3ad78 100644 --- a/test_regress/t/t_class_null_struct.v +++ b/test_regress/t/t_class_null_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_override.py b/test_regress/t/t_class_override.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_override.py +++ b/test_regress/t/t_class_override.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_override.v b/test_regress/t/t_class_override.v index a331e5e1e..e2d7186f9 100644 --- a/test_regress/t/t_class_override.v +++ b/test_regress/t/t_class_override.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Function names correspond to how the function is declared in the base class, diff --git a/test_regress/t/t_class_override_bad.py b/test_regress/t/t_class_override_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_override_bad.py +++ b/test_regress/t/t_class_override_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_override_bad.v b/test_regress/t/t_class_override_bad.v index 0228cda6c..b4e9f251a 100644 --- a/test_regress/t/t_class_override_bad.v +++ b/test_regress/t/t_class_override_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Function names correspond to how the function is declared in the base class, diff --git a/test_regress/t/t_class_package.py b/test_regress/t/t_class_package.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_package.py +++ b/test_regress/t/t_class_package.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_package.v b/test_regress/t/t_class_package.v index 90fbc1029..20765e149 100644 --- a/test_regress/t/t_class_package.v +++ b/test_regress/t/t_class_package.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkga; diff --git a/test_regress/t/t_class_packed.py b/test_regress/t/t_class_packed.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_packed.py +++ b/test_regress/t/t_class_packed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_packed.v b/test_regress/t/t_class_packed.v index daef3ec55..3c603879e 100644 --- a/test_regress/t/t_class_packed.v +++ b/test_regress/t/t_class_packed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_class_param.py b/test_regress/t/t_class_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param.py +++ b/test_regress/t/t_class_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param.v b/test_regress/t/t_class_param.v index a8c1a7db8..8b00ad6d1 100644 --- a/test_regress/t/t_class_param.v +++ b/test_regress/t/t_class_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_class_param_bad1.py b/test_regress/t/t_class_param_bad1.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_param_bad1.py +++ b/test_regress/t/t_class_param_bad1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_bad1.v b/test_regress/t/t_class_param_bad1.v index f3b889366..239c1bf8c 100644 --- a/test_regress/t/t_class_param_bad1.v +++ b/test_regress/t/t_class_param_bad1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls #(parameter PARAMB = 12); diff --git a/test_regress/t/t_class_param_bad2.py b/test_regress/t/t_class_param_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_param_bad2.py +++ b/test_regress/t/t_class_param_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_bad2.v b/test_regress/t/t_class_param_bad2.v index d3f481bed..b46548e94 100644 --- a/test_regress/t/t_class_param_bad2.v +++ b/test_regress/t/t_class_param_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls #(type PARAMB); diff --git a/test_regress/t/t_class_param_bad_paren.py b/test_regress/t/t_class_param_bad_paren.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_param_bad_paren.py +++ b/test_regress/t/t_class_param_bad_paren.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_bad_paren.v b/test_regress/t/t_class_param_bad_paren.v index 0ba6ff7c2..8f943d2a8 100644 --- a/test_regress/t/t_class_param_bad_paren.v +++ b/test_regress/t/t_class_param_bad_paren.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls #(int PARAM = 1); diff --git a/test_regress/t/t_class_param_circ_bad.py b/test_regress/t/t_class_param_circ_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_param_circ_bad.py +++ b/test_regress/t/t_class_param_circ_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_circ_bad.v b/test_regress/t/t_class_param_circ_bad.v index 2a8ffd9ee..7f7622c1a 100644 --- a/test_regress/t/t_class_param_circ_bad.v +++ b/test_regress/t/t_class_param_circ_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef class ClsB; diff --git a/test_regress/t/t_class_param_comma_bad.py b/test_regress/t/t_class_param_comma_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_param_comma_bad.py +++ b/test_regress/t/t_class_param_comma_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_comma_bad.v b/test_regress/t/t_class_param_comma_bad.v index 77fd71e9c..1c4c0a7e0 100644 --- a/test_regress/t/t_class_param_comma_bad.v +++ b/test_regress/t/t_class_param_comma_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls #(parameter PARAMB = 12); diff --git a/test_regress/t/t_class_param_enum.py b/test_regress/t/t_class_param_enum.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_enum.py +++ b/test_regress/t/t_class_param_enum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_enum.v b/test_regress/t/t_class_param_enum.v index a8d499f47..8a7821bc2 100644 --- a/test_regress/t/t_class_param_enum.v +++ b/test_regress/t/t_class_param_enum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef enum bit {A = 0, B = 1} enum_t; @@ -14,8 +14,9 @@ endclass module t; initial begin - Converter#(enum_t) conv1 = new; - Converter#(bit) conv2 = new; + automatic Converter#(enum_t) conv1 = new; + automatic Converter#(bit) conv2 = new; + if (conv1.toInt(A) != 0) $stop; if (conv2.toInt(1) != 1) $stop; diff --git a/test_regress/t/t_class_param_enum_bad.out b/test_regress/t/t_class_param_enum_bad.out index afd1047ca..1367e3acb 100644 --- a/test_regress/t/t_class_param_enum_bad.out +++ b/test_regress/t/t_class_param_enum_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_class_param_enum_bad.v:20:31: Assign RHS expects a CLASSREFDTYPE 'Converter__Tz2', got CLASSREFDTYPE 'Converter__Tz1' +%Error: t/t_class_param_enum_bad.v:20:41: Assign RHS expects a CLASSREFDTYPE 'Converter__Tz2', got CLASSREFDTYPE 'Converter__Tz1' : ... note: In instance 't' - 20 | Converter#(bit) conv2 = conv1; - | ^~~~~ + 20 | automatic Converter#(bit) conv2 = conv1; + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error-ENUMVALUE: t/t_class_param_enum_bad.v:21:19: Implicit conversion to enum 'enum{}$unit::enum_t' from 'logic[31:0]' (IEEE 1800-2023 6.19.3) : ... note: In instance 't' diff --git a/test_regress/t/t_class_param_enum_bad.py b/test_regress/t/t_class_param_enum_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_param_enum_bad.py +++ b/test_regress/t/t_class_param_enum_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_enum_bad.v b/test_regress/t/t_class_param_enum_bad.v index 61342616d..b7215093e 100644 --- a/test_regress/t/t_class_param_enum_bad.v +++ b/test_regress/t/t_class_param_enum_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef enum bit {A = 0, B = 1} enum_t; @@ -14,10 +14,10 @@ endclass module t; initial begin - Converter#(enum_t) conv1 = new; + automatic Converter#(enum_t) conv1 = new; // enum types does not match with other types (IEEE 1800-2023 6.22.1 and 6.22.4) // The assignment and the function call should throw an error. - Converter#(bit) conv2 = conv1; + automatic Converter#(bit) conv2 = conv1; conv1.toInt(0); $stop; end diff --git a/test_regress/t/t_class_param_extends.py b/test_regress/t/t_class_param_extends.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_extends.py +++ b/test_regress/t/t_class_param_extends.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_extends.v b/test_regress/t/t_class_param_extends.v index 76cc416fe..fce412cfa 100644 --- a/test_regress/t/t_class_param_extends.v +++ b/test_regress/t/t_class_param_extends.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Code your testbench here diff --git a/test_regress/t/t_class_param_extends2.py b/test_regress/t/t_class_param_extends2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_extends2.py +++ b/test_regress/t/t_class_param_extends2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_extends2.v b/test_regress/t/t_class_param_extends2.v index f4420d0d0..1158d689a 100644 --- a/test_regress/t/t_class_param_extends2.v +++ b/test_regress/t/t_class_param_extends2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo #(type T=bit); @@ -26,8 +26,8 @@ typedef Baz baz_t; module t; initial begin - bar_default_t bar_default = new; - baz_t baz = new; + automatic bar_default_t bar_default = new; + automatic baz_t baz = new; if (bar_default.x != 32) $stop; if (baz.bar_x != 8) $stop; diff --git a/test_regress/t/t_class_param_extends3.py b/test_regress/t/t_class_param_extends3.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_extends3.py +++ b/test_regress/t/t_class_param_extends3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_extends3.v b/test_regress/t/t_class_param_extends3.v index 9fcf788ab..f728316e7 100644 --- a/test_regress/t/t_class_param_extends3.v +++ b/test_regress/t/t_class_param_extends3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package u_pkg; diff --git a/test_regress/t/t_class_param_extends_static_func.py b/test_regress/t/t_class_param_extends_static_func.py new file mode 100755 index 000000000..84b274f68 --- /dev/null +++ b/test_regress/t/t_class_param_extends_static_func.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_extends_static_member_function_access.v b/test_regress/t/t_class_param_extends_static_func.v similarity index 90% rename from test_regress/t/t_class_param_extends_static_member_function_access.v rename to test_regress/t/t_class_param_extends_static_func.v index 60ca13c37..863ab6ebd 100644 --- a/test_regress/t/t_class_param_extends_static_member_function_access.v +++ b/test_regress/t/t_class_param_extends_static_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Class1 #( diff --git a/test_regress/t/t_class_param_extra_bad.py b/test_regress/t/t_class_param_extra_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_param_extra_bad.py +++ b/test_regress/t/t_class_param_extra_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_extra_bad.v b/test_regress/t/t_class_param_extra_bad.v index 378c39ebe..6548e5f74 100644 --- a/test_regress/t/t_class_param_extra_bad.v +++ b/test_regress/t/t_class_param_extra_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_class_param_func_return.py b/test_regress/t/t_class_param_func_return.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_func_return.py +++ b/test_regress/t/t_class_param_func_return.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_func_return.v b/test_regress/t/t_class_param_func_return.v index 3cdcfd910..23f15377e 100644 --- a/test_regress/t/t_class_param_func_return.v +++ b/test_regress/t/t_class_param_func_return.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo #(type T=int); diff --git a/test_regress/t/t_class_param_lvalue.py b/test_regress/t/t_class_param_lvalue.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_class_param_lvalue.py +++ b/test_regress/t/t_class_param_lvalue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_lvalue.v b/test_regress/t/t_class_param_lvalue.v index 879693876..b9af1b40f 100644 --- a/test_regress/t/t_class_param_lvalue.v +++ b/test_regress/t/t_class_param_lvalue.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_class_param_mailbox.py b/test_regress/t/t_class_param_mailbox.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_mailbox.py +++ b/test_regress/t/t_class_param_mailbox.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_mailbox.v b/test_regress/t/t_class_param_mailbox.v index 58bd33700..4d19a370d 100644 --- a/test_regress/t/t_class_param_mailbox.v +++ b/test_regress/t/t_class_param_mailbox.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub #( diff --git a/test_regress/t/t_class_param_mod.py b/test_regress/t/t_class_param_mod.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_mod.py +++ b/test_regress/t/t_class_param_mod.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_mod.v b/test_regress/t/t_class_param_mod.v index cb89a3ff7..dbd6a0620 100644 --- a/test_regress/t/t_class_param_mod.v +++ b/test_regress/t/t_class_param_mod.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_class_param_nconst_bad.py b/test_regress/t/t_class_param_nconst_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_param_nconst_bad.py +++ b/test_regress/t/t_class_param_nconst_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_nconst_bad.v b/test_regress/t/t_class_param_nconst_bad.v index 64ac0fd70..ded86f95a 100644 --- a/test_regress/t/t_class_param_nconst_bad.v +++ b/test_regress/t/t_class_param_nconst_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls #(parameter PARAM = 12); diff --git a/test_regress/t/t_class_param_nested_bad.py b/test_regress/t/t_class_param_nested_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_param_nested_bad.py +++ b/test_regress/t/t_class_param_nested_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_nested_bad.v b/test_regress/t/t_class_param_nested_bad.v index 265ff794b..e6d75cf4b 100644 --- a/test_regress/t/t_class_param_nested_bad.v +++ b/test_regress/t/t_class_param_nested_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Arkadiusz Kozdra. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Arkadiusz Kozdra // SPDX-License-Identifier: CC0-1.0 typedef class Cls; diff --git a/test_regress/t/t_class_param_noinit.py b/test_regress/t/t_class_param_noinit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_noinit.py +++ b/test_regress/t/t_class_param_noinit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_noinit.v b/test_regress/t/t_class_param_noinit.v index 6baf9c4de..f17d5e9fb 100644 --- a/test_regress/t/t_class_param_noinit.v +++ b/test_regress/t/t_class_param_noinit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // No init value is legal with classes, as long as not used without the parameter diff --git a/test_regress/t/t_class_param_noinit_bad.py b/test_regress/t/t_class_param_noinit_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_param_noinit_bad.py +++ b/test_regress/t/t_class_param_noinit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_noinit_bad.v b/test_regress/t/t_class_param_noinit_bad.v index 180b6935c..1cf3b86c9 100644 --- a/test_regress/t/t_class_param_noinit_bad.v +++ b/test_regress/t/t_class_param_noinit_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // No init value is legal with classes, as long as not used without the parameter diff --git a/test_regress/t/t_class_param_override_local_bad.py b/test_regress/t/t_class_param_override_local_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_class_param_override_local_bad.py +++ b/test_regress/t/t_class_param_override_local_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_override_local_bad.v b/test_regress/t/t_class_param_override_local_bad.v index 39c89ea99..4ea6d1e62 100644 --- a/test_regress/t/t_class_param_override_local_bad.v +++ b/test_regress/t/t_class_param_override_local_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls1; diff --git a/test_regress/t/t_class_param_pkg.py b/test_regress/t/t_class_param_pkg.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_pkg.py +++ b/test_regress/t/t_class_param_pkg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_pkg.v b/test_regress/t/t_class_param_pkg.v index 5fe599280..e0615df98 100644 --- a/test_regress/t/t_class_param_pkg.v +++ b/test_regress/t/t_class_param_pkg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_class_param_rewrite.py b/test_regress/t/t_class_param_rewrite.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_rewrite.py +++ b/test_regress/t/t_class_param_rewrite.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_rewrite.v b/test_regress/t/t_class_param_rewrite.v index b88019127..1303af3db 100644 --- a/test_regress/t/t_class_param_rewrite.v +++ b/test_regress/t/t_class_param_rewrite.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module test; diff --git a/test_regress/t/t_class_param_static.py b/test_regress/t/t_class_param_static.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_class_param_static.py +++ b/test_regress/t/t_class_param_static.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_static.v b/test_regress/t/t_class_param_static.v index 9b92e9ac6..261a4e824 100644 --- a/test_regress/t/t_class_param_static.v +++ b/test_regress/t/t_class_param_static.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_class_param_subtype.v b/test_regress/t/t_class_param_subtype.v index 6799c43e6..b3158eab7 100644 --- a/test_regress/t/t_class_param_subtype.v +++ b/test_regress/t/t_class_param_subtype.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 // Test for bug4281 diff --git a/test_regress/t/t_class_param_subtype2.py b/test_regress/t/t_class_param_subtype2.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_class_param_subtype2.py +++ b/test_regress/t/t_class_param_subtype2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_subtype2.v b/test_regress/t/t_class_param_subtype2.v index 5bb85b6e3..3d7b22591 100644 --- a/test_regress/t/t_class_param_subtype2.v +++ b/test_regress/t/t_class_param_subtype2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Class1 #(type T); diff --git a/test_regress/t/t_class_param_subtype_bad_paren.py b/test_regress/t/t_class_param_subtype_bad_paren.py index 6b8a1cf07..d57d33a34 100755 --- a/test_regress/t/t_class_param_subtype_bad_paren.py +++ b/test_regress/t/t_class_param_subtype_bad_paren.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_subtype_constsim.py b/test_regress/t/t_class_param_subtype_constsim.py index cc356de23..498146b7b 100755 --- a/test_regress/t/t_class_param_subtype_constsim.py +++ b/test_regress/t/t_class_param_subtype_constsim.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_super.py b/test_regress/t/t_class_param_super.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_class_param_super.py +++ b/test_regress/t/t_class_param_super.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_super.v b/test_regress/t/t_class_param_super.v index 1b26f8812..b61616535 100644 --- a/test_regress/t/t_class_param_super.v +++ b/test_regress/t/t_class_param_super.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class base #( diff --git a/test_regress/t/t_class_param_type.py b/test_regress/t/t_class_param_type.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_type.py +++ b/test_regress/t/t_class_param_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_type.v b/test_regress/t/t_class_param_type.v index d00d1ece4..038abcc6f 100644 --- a/test_regress/t/t_class_param_type.v +++ b/test_regress/t/t_class_param_type.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 // See also t_class_param.v @@ -125,9 +125,9 @@ module t; automatic GetStaticXVal#(StaticX) get_statix_x_val = new; typedef bit my_bit_t; - Bar#(.A(my_bit_t)) bar_a_bit = new; - Bar#(.B(my_bit_t)) bar_b_bit = new; - Bar#() bar_default = new; + automatic Bar#(.A(my_bit_t)) bar_a_bit = new; + automatic Bar#(.B(my_bit_t)) bar_b_bit = new; + automatic Bar#() bar_default = new; if (bar_a_bit.get_size_A != 1) $stop; if (bar_a_bit.get_size_B != 1) $stop; diff --git a/test_regress/t/t_class_param_typedef.py b/test_regress/t/t_class_param_typedef.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_typedef.py +++ b/test_regress/t/t_class_param_typedef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_typedef.v b/test_regress/t/t_class_param_typedef.v index d9f9f73ce..3d1862b69 100644 --- a/test_regress/t/t_class_param_typedef.v +++ b/test_regress/t/t_class_param_typedef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo #(type T=int); @@ -46,14 +46,14 @@ endclass module t; initial begin - Cls1::type_id bar1 = new; - Cls2::type_id bar2 = new; + automatic Cls1::type_id bar1 = new; + automatic Cls2::type_id bar2 = new; - ClsTypedefParam #(int) cls_int = new; - ClsTypedefParam#() cls_def; + automatic ClsTypedefParam #(int) cls_int = new; + automatic ClsTypedefParam#() cls_def; - uvm_sequencer #(int, int) uvm_seq1 = new; - uvm_sequencer #(int, int)::this_type uvm_seq2; + automatic uvm_sequencer #(int, int) uvm_seq1 = new; + automatic uvm_sequencer #(int, int)::this_type uvm_seq2; if (bar1.get_x() != 1) $stop; if (bar2.get_x() != 2) $stop; diff --git a/test_regress/t/t_class_param_typedef2.py b/test_regress/t/t_class_param_typedef2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_typedef2.py +++ b/test_regress/t/t_class_param_typedef2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_typedef2.v b/test_regress/t/t_class_param_typedef2.v index ea2e74a1a..6d1b48dfc 100644 --- a/test_regress/t/t_class_param_typedef2.v +++ b/test_regress/t/t_class_param_typedef2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 virtual class Virt; @@ -25,7 +25,7 @@ typedef uvm_object_registry#(MyInt) type_id; module t; initial begin - MyInt mi = type_id::create_object(); + automatic MyInt mi = type_id::create_object(); if (mi.x != 1) $stop; $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_class_param_typedef3.py b/test_regress/t/t_class_param_typedef3.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_class_param_typedef3.py +++ b/test_regress/t/t_class_param_typedef3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_typedef3.v b/test_regress/t/t_class_param_typedef3.v index 9c1557ce0..717ff40e1 100644 --- a/test_regress/t/t_class_param_typedef3.v +++ b/test_regress/t/t_class_param_typedef3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class func_c #( diff --git a/test_regress/t/t_class_param_typedef4.py b/test_regress/t/t_class_param_typedef4.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_class_param_typedef4.py +++ b/test_regress/t/t_class_param_typedef4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_typedef4.v b/test_regress/t/t_class_param_typedef4.v index 9af53474f..3fef00d98 100644 --- a/test_regress/t/t_class_param_typedef4.v +++ b/test_regress/t/t_class_param_typedef4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class func_c #( diff --git a/test_regress/t/t_class_param_typedef5.py b/test_regress/t/t_class_param_typedef5.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_class_param_typedef5.py +++ b/test_regress/t/t_class_param_typedef5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_typedef5.v b/test_regress/t/t_class_param_typedef5.v index 201778abb..17915c9eb 100644 --- a/test_regress/t/t_class_param_typedef5.v +++ b/test_regress/t/t_class_param_typedef5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class func_c #( diff --git a/test_regress/t/t_class_param_typedef6.py b/test_regress/t/t_class_param_typedef6.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_class_param_typedef6.py +++ b/test_regress/t/t_class_param_typedef6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_typedef6.v b/test_regress/t/t_class_param_typedef6.v index acad6af63..f6d42dbcf 100644 --- a/test_regress/t/t_class_param_typedef6.v +++ b/test_regress/t/t_class_param_typedef6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_class_param_unused_default.py b/test_regress/t/t_class_param_unused_default.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_param_unused_default.py +++ b/test_regress/t/t_class_param_unused_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_unused_default.v b/test_regress/t/t_class_param_unused_default.v index 3ce45727b..e1563c077 100644 --- a/test_regress/t/t_class_param_unused_default.v +++ b/test_regress/t/t_class_param_unused_default.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Bar#(type T = int); @@ -17,7 +17,7 @@ endclass module t; initial begin - Bar#(Baz) bar_baz = new; + automatic Bar#(Baz) bar_baz = new; if (bar_baz.t.x != 1) $stop; $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_class_param_upcast.py b/test_regress/t/t_class_param_upcast.py index 147fe6faf..0379f0dd0 100755 --- a/test_regress/t/t_class_param_upcast.py +++ b/test_regress/t/t_class_param_upcast.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_upcast.v b/test_regress/t/t_class_param_upcast.v index 356780af1..7ed459bbf 100644 --- a/test_regress/t/t_class_param_upcast.v +++ b/test_regress/t/t_class_param_upcast.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class factory #( diff --git a/test_regress/t/t_class_param_virtual_bad.out b/test_regress/t/t_class_param_virtual_bad.out index 22322b74a..c53f4d7b3 100644 --- a/test_regress/t/t_class_param_virtual_bad.out +++ b/test_regress/t/t_class_param_virtual_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_class_param_virtual_bad.v:23:28: Illegal to call 'new' using an abstract virtual class 'ClsVirt' (IEEE 1800-2023 8.21) +%Error: t/t_class_param_virtual_bad.v:23:38: Illegal to call 'new' using an abstract virtual class 'ClsVirt' (IEEE 1800-2023 8.21) : ... note: In instance 't' - 23 | ClsVirt#(VBase) cv = new; - | ^~~ + 23 | automatic ClsVirt#(VBase) cv = new; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: t/t_class_param_virtual_bad.v:13:11: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2023 8.21) : ... note: In instance 't' diff --git a/test_regress/t/t_class_param_virtual_bad.py b/test_regress/t/t_class_param_virtual_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_class_param_virtual_bad.py +++ b/test_regress/t/t_class_param_virtual_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_param_virtual_bad.v b/test_regress/t/t_class_param_virtual_bad.v index e9f3c9c85..d53651d88 100644 --- a/test_regress/t/t_class_param_virtual_bad.v +++ b/test_regress/t/t_class_param_virtual_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 virtual class VBase; @@ -19,8 +19,8 @@ endclass module t; initial begin - Cls c = new; // Error - ClsVirt#(VBase) cv = new; // Error + automatic Cls c = new; // Error + automatic ClsVirt#(VBase) cv = new; // Error $stop; end endmodule diff --git a/test_regress/t/t_class_ref_as_arg_cast.py b/test_regress/t/t_class_ref_as_arg_cast.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_class_ref_as_arg_cast.py +++ b/test_regress/t/t_class_ref_as_arg_cast.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_ref_as_arg_cast.v b/test_regress/t/t_class_ref_as_arg_cast.v index d1d5f25d0..458437e35 100644 --- a/test_regress/t/t_class_ref_as_arg_cast.v +++ b/test_regress/t/t_class_ref_as_arg_cast.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -14,7 +14,8 @@ endclass module t; initial begin - Qux qux = new; + Qux qux; + qux = new; Foo::bar(qux); Foo::bar(null); end diff --git a/test_regress/t/t_class_ref_bad.py b/test_regress/t/t_class_ref_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_ref_bad.py +++ b/test_regress/t/t_class_ref_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_ref_bad.v b/test_regress/t/t_class_ref_bad.v index c0af601a8..d1242cb1c 100644 --- a/test_regress/t/t_class_ref_bad.v +++ b/test_regress/t/t_class_ref_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class ClsRight; diff --git a/test_regress/t/t_class_ref_ref.py b/test_regress/t/t_class_ref_ref.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_class_ref_ref.py +++ b/test_regress/t/t_class_ref_ref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_ref_ref.v b/test_regress/t/t_class_ref_ref.v index 7678dedbe..948ba2b22 100644 --- a/test_regress/t/t_class_ref_ref.v +++ b/test_regress/t/t_class_ref_ref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls#(type T = bit); diff --git a/test_regress/t/t_class_reference_name_colision.py b/test_regress/t/t_class_reference_name_colision.py index 147fe6faf..0379f0dd0 100755 --- a/test_regress/t/t_class_reference_name_colision.py +++ b/test_regress/t/t_class_reference_name_colision.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_reference_name_colision.v b/test_regress/t/t_class_reference_name_colision.v index 6ddd27f78..96d64f245 100644 --- a/test_regress/t/t_class_reference_name_colision.v +++ b/test_regress/t/t_class_reference_name_colision.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class setup_coefficients; diff --git a/test_regress/t/t_class_scope_import_bad.py b/test_regress/t/t_class_scope_import_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_class_scope_import_bad.py +++ b/test_regress/t/t_class_scope_import_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_scope_import_bad.v b/test_regress/t/t_class_scope_import_bad.v index 8bf6cee96..6d03848f2 100644 --- a/test_regress/t/t_class_scope_import_bad.v +++ b/test_regress/t/t_class_scope_import_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_class_short_circuit.py b/test_regress/t/t_class_short_circuit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_short_circuit.py +++ b/test_regress/t/t_class_short_circuit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_short_circuit.v b/test_regress/t/t_class_short_circuit.v index b34f863cb..02318d569 100644 --- a/test_regress/t/t_class_short_circuit.v +++ b/test_regress/t/t_class_short_circuit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_split.py b/test_regress/t/t_class_split.py index 628bb8901..8cde02d8c 100755 --- a/test_regress/t/t_class_split.py +++ b/test_regress/t/t_class_split.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_split.v b/test_regress/t/t_class_split.v index 7c6a6b8e8..decfb1ebf 100644 --- a/test_regress/t/t_class_split.v +++ b/test_regress/t/t_class_split.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Iru Cai. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Iru Cai // SPDX-License-Identifier: CC0-1.0 class Cls1; diff --git a/test_regress/t/t_class_static.py b/test_regress/t/t_class_static.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_static.py +++ b/test_regress/t/t_class_static.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_static.v b/test_regress/t/t_class_static.v index 9dae39e98..002034221 100644 --- a/test_regress/t/t_class_static.v +++ b/test_regress/t/t_class_static.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_class_static_after_cg.py b/test_regress/t/t_class_static_after_cg.py new file mode 100755 index 000000000..26440f70f --- /dev/null +++ b/test_regress/t/t_class_static_after_cg.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint() + +test.passes() diff --git a/test_regress/t/t_class_static_after_cg.v b/test_regress/t/t_class_static_after_cg.v new file mode 100644 index 000000000..293dd5528 --- /dev/null +++ b/test_regress/t/t_class_static_after_cg.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + class Cls; + // verilator lint_off COVERIGN + covergroup cov_trans; + option.per_instance = 1; + endgroup + + virtual function void perform_transfer_checks(); + check_transfer_size(); + endfunction + virtual function void check_transfer_size(); + endfunction + endclass + + initial begin + Cls c; + c = new; + c.perform_transfer_checks(); + $finish; + end +endmodule diff --git a/test_regress/t/t_class_static_default_arg.py b/test_regress/t/t_class_static_default_arg.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_static_default_arg.py +++ b/test_regress/t/t_class_static_default_arg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_static_default_arg.v b/test_regress/t/t_class_static_default_arg.v index b0572a40c..bd6a4d7d2 100644 --- a/test_regress/t/t_class_static_default_arg.v +++ b/test_regress/t/t_class_static_default_arg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -14,7 +14,7 @@ module t; initial begin bit first; - bit arg[$] = {1'b0, 1'b1}; + automatic bit arg[$] = {1'b0, 1'b1}; first = Foo::get_first(); if (first != 1) $stop; first = Foo::get_first(arg); diff --git a/test_regress/t/t_class_static_member.py b/test_regress/t/t_class_static_member.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_static_member.py +++ b/test_regress/t/t_class_static_member.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_static_member.v b/test_regress/t/t_class_static_member.v index d4eef9eb2..9f1cb99ad 100644 --- a/test_regress/t/t_class_static_member.v +++ b/test_regress/t/t_class_static_member.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_class_static_member_bad.out b/test_regress/t/t_class_static_member_bad.out new file mode 100644 index 000000000..2733cd82d --- /dev/null +++ b/test_regress/t/t_class_static_member_bad.out @@ -0,0 +1,8 @@ +%Error: t/t_class_static_member_bad.v:10:11: Cannot access non-static member variable 'mb' from a static method 'foo' without object (IEEE 1800-2023 8.10) + 10 | void'(mb.try_put(this)); + | ^~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_class_static_member_bad.v:10:22: Cannot use 'this' in a static method 'foo' (IEEE 1800-2023 8.10-8.11) + 10 | void'(mb.try_put(this)); + | ^~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_class_static_member_bad.py b/test_regress/t/t_class_static_member_bad.py new file mode 100755 index 000000000..38cf36b43 --- /dev/null +++ b/test_regress/t/t_class_static_member_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_static_member_bad.v b/test_regress/t/t_class_static_member_bad.v new file mode 100644 index 000000000..eb6cb4c69 --- /dev/null +++ b/test_regress/t/t_class_static_member_bad.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +class Cls; + mailbox #(Cls) mb = new(); + static task foo(); + void'(mb.try_put(this)); + endtask +endclass diff --git a/test_regress/t/t_class_static_member_pkg.py b/test_regress/t/t_class_static_member_pkg.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_static_member_pkg.py +++ b/test_regress/t/t_class_static_member_pkg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_static_member_pkg.v b/test_regress/t/t_class_static_member_pkg.v index a351b183c..b51eb6333 100644 --- a/test_regress/t/t_class_static_member_pkg.v +++ b/test_regress/t/t_class_static_member_pkg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_class_static_member_sel.py b/test_regress/t/t_class_static_member_sel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_static_member_sel.py +++ b/test_regress/t/t_class_static_member_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_static_member_sel.v b/test_regress/t/t_class_static_member_sel.v index 3071bf50f..e83659fb2 100644 --- a/test_regress/t/t_class_static_member_sel.v +++ b/test_regress/t/t_class_static_member_sel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -57,11 +57,11 @@ endclass module t; initial begin - Foo foo = new; - Bar bar = new; - Baz baz = new; - ExtendCls ec = new; - Getter1 getter1 = new; + automatic Foo foo = new; + automatic Bar bar = new; + automatic Baz baz = new; + automatic ExtendCls ec = new; + automatic Getter1 getter1 = new; if (foo.x != 1) $stop; diff --git a/test_regress/t/t_class_static_method.py b/test_regress/t/t_class_static_method.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_static_method.py +++ b/test_regress/t/t_class_static_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_static_method.v b/test_regress/t/t_class_static_method.v index 85ac94d0a..a7ba8a4a3 100644 --- a/test_regress/t/t_class_static_method.v +++ b/test_regress/t/t_class_static_method.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_static_method_protect_ids.py b/test_regress/t/t_class_static_method_protect_ids.py index 955f1a347..ff416ebdf 100755 --- a/test_regress/t/t_class_static_method_protect_ids.py +++ b/test_regress/t/t_class_static_method_protect_ids.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_static_order.py b/test_regress/t/t_class_static_order.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_static_order.py +++ b/test_regress/t/t_class_static_order.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_static_order.v b/test_regress/t/t_class_static_order.v index f361a8e74..bf639f50c 100644 --- a/test_regress/t/t_class_static_order.v +++ b/test_regress/t/t_class_static_order.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class ClsZ; diff --git a/test_regress/t/t_class_super_bad.py b/test_regress/t/t_class_super_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_super_bad.py +++ b/test_regress/t/t_class_super_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_super_bad.v b/test_regress/t/t_class_super_bad.v index cb84dab9c..e4de0c364 100644 --- a/test_regress/t/t_class_super_bad.v +++ b/test_regress/t/t_class_super_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Rafal Kapuscik +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Rafal Kapuscik // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_class_super_bad2.py b/test_regress/t/t_class_super_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_super_bad2.py +++ b/test_regress/t/t_class_super_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_super_bad2.v b/test_regress/t/t_class_super_bad2.v index ba31d657b..8a75239b5 100644 --- a/test_regress/t/t_class_super_bad2.v +++ b/test_regress/t/t_class_super_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Rafal Kapuscik +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Rafal Kapuscik // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_class_super_bad3.py b/test_regress/t/t_class_super_bad3.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_super_bad3.py +++ b/test_regress/t/t_class_super_bad3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_super_bad3.v b/test_regress/t/t_class_super_bad3.v index e50fd51fe..f18954f30 100644 --- a/test_regress/t/t_class_super_bad3.v +++ b/test_regress/t/t_class_super_bad3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_class_super_new.py b/test_regress/t/t_class_super_new.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_super_new.py +++ b/test_regress/t/t_class_super_new.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_super_new.v b/test_regress/t/t_class_super_new.v index 58fe8bc3b..e439cb91a 100644 --- a/test_regress/t/t_class_super_new.v +++ b/test_regress/t/t_class_super_new.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_class_super_new2.py b/test_regress/t/t_class_super_new2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_super_new2.py +++ b/test_regress/t/t_class_super_new2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_super_new2.v b/test_regress/t/t_class_super_new2.v index 5d5c455f9..c3b35deee 100644 --- a/test_regress/t/t_class_super_new2.v +++ b/test_regress/t/t_class_super_new2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Tudor Timi. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Tudor Timi // SPDX-License-Identifier: CC0-1.0 class svunit_base; diff --git a/test_regress/t/t_class_super_new3.py b/test_regress/t/t_class_super_new3.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_class_super_new3.py +++ b/test_regress/t/t_class_super_new3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_super_new3.v b/test_regress/t/t_class_super_new3.v index c216e91a9..77ccdf7b1 100644 --- a/test_regress/t/t_class_super_new3.v +++ b/test_regress/t/t_class_super_new3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Base; @@ -21,7 +21,7 @@ endclass module t; initial begin - Derived d = new; + automatic Derived d = new; if (d.j != 8) $stop; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_class_super_new_bad_nfirst.py b/test_regress/t/t_class_super_new_bad_nfirst.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_super_new_bad_nfirst.py +++ b/test_regress/t/t_class_super_new_bad_nfirst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_super_new_bad_nfirst.v b/test_regress/t/t_class_super_new_bad_nfirst.v index 7fbac76d4..f5505c012 100644 --- a/test_regress/t/t_class_super_new_bad_nfirst.v +++ b/test_regress/t/t_class_super_new_bad_nfirst.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Base; diff --git a/test_regress/t/t_class_super_new_noextend_bad.py b/test_regress/t/t_class_super_new_noextend_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_class_super_new_noextend_bad.py +++ b/test_regress/t/t_class_super_new_noextend_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_super_new_noextend_bad.v b/test_regress/t/t_class_super_new_noextend_bad.v index 7ea862a47..0e0bfee53 100644 --- a/test_regress/t/t_class_super_new_noextend_bad.v +++ b/test_regress/t/t_class_super_new_noextend_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_class_this_constructor.py b/test_regress/t/t_class_this_constructor.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_this_constructor.py +++ b/test_regress/t/t_class_this_constructor.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_this_constructor.v b/test_regress/t/t_class_this_constructor.v index 1fe870502..70bf8f045 100644 --- a/test_regress/t/t_class_this_constructor.v +++ b/test_regress/t/t_class_this_constructor.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_class_this_super.py b/test_regress/t/t_class_this_super.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_class_this_super.py +++ b/test_regress/t/t_class_this_super.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_this_super.v b/test_regress/t/t_class_this_super.v index bfb325783..186f59eb4 100644 --- a/test_regress/t/t_class_this_super.v +++ b/test_regress/t/t_class_this_super.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_class_to_basic_assignment_bad.out b/test_regress/t/t_class_to_basic_assignment_bad.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_class_to_basic_assignment_bad.py b/test_regress/t/t_class_to_basic_assignment_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_class_to_basic_assignment_bad.py +++ b/test_regress/t/t_class_to_basic_assignment_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_to_basic_assignment_bad.v b/test_regress/t/t_class_to_basic_assignment_bad.v index 711841e7b..59b670897 100644 --- a/test_regress/t/t_class_to_basic_assignment_bad.v +++ b/test_regress/t/t_class_to_basic_assignment_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_class_trigger_null.py b/test_regress/t/t_class_trigger_null.py new file mode 100755 index 000000000..4ee7f9e14 --- /dev/null +++ b/test_regress/t/t_class_trigger_null.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_trigger_null.v b/test_regress/t/t_class_trigger_null.v new file mode 100644 index 000000000..17a9175cf --- /dev/null +++ b/test_regress/t/t_class_trigger_null.v @@ -0,0 +1,136 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Cameron Waite +// SPDX-License-Identifier: CC0-1.0 + +// Test for null pointer dereference when sensitivity expressions reference +// class members. Verilator evaluates trigger expressions at simulation start, +// even for tasks that haven't been called yet. This caused null pointer +// dereference when accessing class_handle.event or class_handle.vif.signal +// because the task parameter didn't have a valid value yet. +// +// Also tests "instant fall-through" scenario: events triggered at time 0 +// (same timestep as class construction) should still be detected. + +interface my_if; + logic sig; +endinterface + +package my_pkg; + + class my_driver; + virtual my_if vif; + event my_event; + + function new(virtual my_if vif_in); + vif = vif_in; + endfunction + endclass + + // Task with sensitivity expressions on class member event and signals + task automatic my_task(my_driver drv, output int ev_cnt, pos_cnt, neg_cnt); + my_driver h = drv; + + if (h == null) begin + $display("Error: drv is NULL!"); + $finish; + end + + fork + begin + // Wait on class member event - previously caused null deref + @(h.my_event); + ev_cnt++; + end + begin + // Wait on posedge through virtual interface - previously caused null deref + @(posedge h.vif.sig); + pos_cnt++; + end + begin + // Wait on negedge through virtual interface - previously caused null deref + @(negedge h.vif.sig); + neg_cnt++; + end + begin + #10; + ->h.my_event; + #10; + h.vif.sig = 1; + #10; + h.vif.sig = 0; + end + join + endtask + +endpackage + +module t; + my_if intf (); + my_pkg::my_driver drv; + virtual my_if vif; + + int event_count; + int posedge_count; + int negedge_count; + + // Counter for instant (time 0) event detection + int instant_event_count = 0; + + // Test "instant fall-through": sensitivity on class member event at module level + // This always block is evaluated at elaboration when drv is still null. + // After construction, events triggered at time 0 should still be detected. + always @(drv.my_event) begin + instant_event_count++; + end + + // Construct the class at time 0 + initial begin + vif = intf; + drv = new(vif); + intf.sig = 0; + end + + // Trigger event at time 0 (same timestep as construction) - "instant fall-through" + // Use #0 to ensure construction happens first in delta cycle ordering + initial begin + #0; + ->drv.my_event; + end + + // Call the task later - trigger expressions were evaluated before this + initial begin + event_count = 0; + posedge_count = 0; + negedge_count = 0; + + #20; + my_pkg::my_task(drv, event_count, posedge_count, negedge_count); + + // Verify all triggers occurred + if (event_count != 1) begin + $display("%%Error: event_count = %0d, expected 1", event_count); + $stop; + end + if (posedge_count != 1) begin + $display("%%Error: posedge_count = %0d, expected 1", posedge_count); + $stop; + end + if (negedge_count != 1) begin + $display("%%Error: negedge_count = %0d, expected 1", negedge_count); + $stop; + end + + // Verify instant fall-through worked (time 0 event was detected) + // We expect 2: one from time 0, one from the task at time 30 + if (instant_event_count != 2) begin + $display("%%Error: instant_event_count = %0d, expected 2", instant_event_count); + $display("%%Error: Instant fall-through failed - events at time 0 were missed!"); + $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_class_typedef.py b/test_regress/t/t_class_typedef.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_typedef.py +++ b/test_regress/t/t_class_typedef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_typedef.v b/test_regress/t/t_class_typedef.v index 59426c68f..89a79f563 100644 --- a/test_regress/t/t_class_typedef.v +++ b/test_regress/t/t_class_typedef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class uvm_resource_types; @@ -23,7 +23,7 @@ endclass module t; initial begin - uvm_resource_pool pool = new; + automatic uvm_resource_pool pool = new; typedef logic [7:0] t_t0; C#(t_t0,3)::t_vector v0; C#(t_t0,3)::t_array a0; diff --git a/test_regress/t/t_class_unsup_bad.py b/test_regress/t/t_class_unsup_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_class_unsup_bad.py +++ b/test_regress/t/t_class_unsup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_unsup_bad.v b/test_regress/t/t_class_unsup_bad.v index 78e9b771c..776fc3590 100644 --- a/test_regress/t/t_class_unsup_bad.v +++ b/test_regress/t/t_class_unsup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 virtual interface vi_t vi; diff --git a/test_regress/t/t_class_uses_this.py b/test_regress/t/t_class_uses_this.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_uses_this.py +++ b/test_regress/t/t_class_uses_this.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_uses_this.v b/test_regress/t/t_class_uses_this.v index 8d7109866..5c34a587a 100644 --- a/test_regress/t/t_class_uses_this.v +++ b/test_regress/t/t_class_uses_this.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Rafal Kapuscik +// SPDX-FileCopyrightText: 2020 Rafal Kapuscik // SPDX-License-Identifier: CC0-1.0 // class Cls; diff --git a/test_regress/t/t_class_uses_this_bad.py b/test_regress/t/t_class_uses_this_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_class_uses_this_bad.py +++ b/test_regress/t/t_class_uses_this_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_uses_this_bad.v b/test_regress/t/t_class_uses_this_bad.v index 9d6019ed0..604eb42ed 100644 --- a/test_regress/t/t_class_uses_this_bad.v +++ b/test_regress/t/t_class_uses_this_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Rafal Kapuscik +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Rafal Kapuscik // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_class_virtual.py b/test_regress/t/t_class_virtual.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_virtual.py +++ b/test_regress/t/t_class_virtual.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_virtual.v b/test_regress/t/t_class_virtual.v index 8c0b80920..be46496e0 100644 --- a/test_regress/t/t_class_virtual.v +++ b/test_regress/t/t_class_virtual.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 virtual class VBase; @@ -72,12 +72,12 @@ endclass module t; initial begin - VA va = new; - VB vb = new; - VA::VNested vna = new; - VB::VNested vnb = new; - VBase b; - VBase::VNested bn; + automatic VA va = new; + automatic VB vb = new; + automatic VA::VNested vna = new; + automatic VB::VNested vnb = new; + automatic VBase b; + automatic VBase::VNested bn; uvm_build_phase ph; ExtendsCls ec; diff --git a/test_regress/t/t_class_virtual_bad.out b/test_regress/t/t_class_virtual_bad.out index 6ac64a912..9174bb2ab 100644 --- a/test_regress/t/t_class_virtual_bad.out +++ b/test_regress/t/t_class_virtual_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_class_virtual_bad.v:12:17: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2023 8.21) +%Error: t/t_class_virtual_bad.v:12:27: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2023 8.21) : ... note: In instance 't' - 12 | VBase b = new; - | ^~~ + 12 | automatic VBase b = new; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_virtual_bad.py b/test_regress/t/t_class_virtual_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_class_virtual_bad.py +++ b/test_regress/t/t_class_virtual_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_virtual_bad.v b/test_regress/t/t_class_virtual_bad.v index 5e87644a4..86e3d6fb8 100644 --- a/test_regress/t/t_class_virtual_bad.v +++ b/test_regress/t/t_class_virtual_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 virtual class VBase; @@ -9,6 +9,6 @@ endclass module t; initial begin - VBase b = new; // Error + automatic VBase b = new; // Error end endmodule diff --git a/test_regress/t/t_class_virtual_chain_ctor.py b/test_regress/t/t_class_virtual_chain_ctor.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_class_virtual_chain_ctor.py +++ b/test_regress/t/t_class_virtual_chain_ctor.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_virtual_chain_ctor.v b/test_regress/t/t_class_virtual_chain_ctor.v index 53a1b4ec8..0ac078f73 100644 --- a/test_regress/t/t_class_virtual_chain_ctor.v +++ b/test_regress/t/t_class_virtual_chain_ctor.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Check that an abstract class' contstructor // can be called indirectly from a constructor of a derived class. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Ilya Barkov +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Ilya Barkov // SPDX-License-Identifier: CC0-1.0 // It's illegal to call @@ -29,6 +29,6 @@ endclass module t; initial begin - VChild2 c = new; + automatic VChild2 c = new; end endmodule diff --git a/test_regress/t/t_class_virtual_protect_ids.py b/test_regress/t/t_class_virtual_protect_ids.py index b42e1e842..0cc1c4f4e 100755 --- a/test_regress/t/t_class_virtual_protect_ids.py +++ b/test_regress/t/t_class_virtual_protect_ids.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_virtual_pure.py b/test_regress/t/t_class_virtual_pure.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_virtual_pure.py +++ b/test_regress/t/t_class_virtual_pure.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_virtual_pure.v b/test_regress/t/t_class_virtual_pure.v index 7c33da780..22155e0bd 100644 --- a/test_regress/t/t_class_virtual_pure.v +++ b/test_regress/t/t_class_virtual_pure.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 virtual class VBase; diff --git a/test_regress/t/t_class_virtual_pure_bad.py b/test_regress/t/t_class_virtual_pure_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_class_virtual_pure_bad.py +++ b/test_regress/t/t_class_virtual_pure_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_virtual_pure_bad.v b/test_regress/t/t_class_virtual_pure_bad.v index 7b3754db3..f235902f3 100644 --- a/test_regress/t/t_class_virtual_pure_bad.v +++ b/test_regress/t/t_class_virtual_pure_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class VBase; diff --git a/test_regress/t/t_class_vparam.py b/test_regress/t/t_class_vparam.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_vparam.py +++ b/test_regress/t/t_class_vparam.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_vparam.v b/test_regress/t/t_class_vparam.v index 76403f03b..2ca8a683f 100644 --- a/test_regress/t/t_class_vparam.v +++ b/test_regress/t/t_class_vparam.v @@ -2,8 +2,8 @@ // // Simple bi-directional alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef class paramed_class_t; diff --git a/test_regress/t/t_class_wide.py b/test_regress/t/t_class_wide.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_class_wide.py +++ b/test_regress/t/t_class_wide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_class_wide.v b/test_regress/t/t_class_wide.v index a61944960..271d7c1a3 100644 --- a/test_regress/t/t_class_wide.v +++ b/test_regress/t/t_class_wide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Jomit626. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2022 Jomit626 // SPDX-License-Identifier: CC0-1.0 `ifndef WIDTH diff --git a/test_regress/t/t_clk_2in.cpp b/test_regress/t/t_clk_2in.cpp index a314d43a6..c6ed81e0f 100644 --- a/test_regress/t/t_clk_2in.cpp +++ b/test_regress/t/t_clk_2in.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_clk_2in.py b/test_regress/t/t_clk_2in.py index 69b0d367c..b208a8bbe 100755 --- a/test_regress/t/t_clk_2in.py +++ b/test_regress/t/t_clk_2in.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_2in.v b/test_regress/t/t_clk_2in.v index 9248dfb75..1f40623b3 100644 --- a/test_regress/t/t_clk_2in.v +++ b/test_regress/t/t_clk_2in.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifndef VERILATOR diff --git a/test_regress/t/t_clk_2in_vec.py b/test_regress/t/t_clk_2in_vec.py index 5939f11bf..14de7859a 100755 --- a/test_regress/t/t_clk_2in_vec.py +++ b/test_regress/t/t_clk_2in_vec.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_concat.py b/test_regress/t/t_clk_concat.py index 15f5ff1bb..fb2c945b4 100755 --- a/test_regress/t/t_clk_concat.py +++ b/test_regress/t/t_clk_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_concat.v b/test_regress/t/t_clk_concat.v index b66a9282d..7e432d795 100644 --- a/test_regress/t/t_clk_concat.v +++ b/test_regress/t/t_clk_concat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module some_module ( diff --git a/test_regress/t/t_clk_concat.vlt b/test_regress/t/t_clk_concat.vlt index f50d457be..3aee34ef2 100644 --- a/test_regress/t/t_clk_concat.vlt +++ b/test_regress/t/t_clk_concat.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed into the Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_clk_concat2.py b/test_regress/t/t_clk_concat2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_concat2.py +++ b/test_regress/t/t_clk_concat2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_concat2.v b/test_regress/t/t_clk_concat2.v index d1d641457..e13a56832 100644 --- a/test_regress/t/t_clk_concat2.v +++ b/test_regress/t/t_clk_concat2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module some_module ( diff --git a/test_regress/t/t_clk_concat3.py b/test_regress/t/t_clk_concat3.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_concat3.py +++ b/test_regress/t/t_clk_concat3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_concat3.v b/test_regress/t/t_clk_concat3.v index fe68657cb..aa5a67c9e 100644 --- a/test_regress/t/t_clk_concat3.v +++ b/test_regress/t/t_clk_concat3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off ASCRANGE */ diff --git a/test_regress/t/t_clk_concat4.py b/test_regress/t/t_clk_concat4.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_concat4.py +++ b/test_regress/t/t_clk_concat4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_concat4.v b/test_regress/t/t_clk_concat4.v index 58539dd4b..98a9b1407 100644 --- a/test_regress/t/t_clk_concat4.v +++ b/test_regress/t/t_clk_concat4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module some_module ( diff --git a/test_regress/t/t_clk_concat5.py b/test_regress/t/t_clk_concat5.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_concat5.py +++ b/test_regress/t/t_clk_concat5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_concat5.v b/test_regress/t/t_clk_concat5.v index 359ea01a2..245a0e323 100644 --- a/test_regress/t/t_clk_concat5.v +++ b/test_regress/t/t_clk_concat5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed into the Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module some_module ( diff --git a/test_regress/t/t_clk_concat6.py b/test_regress/t/t_clk_concat6.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_concat6.py +++ b/test_regress/t/t_clk_concat6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_concat6.v b/test_regress/t/t_clk_concat6.v index 87fad0d11..07b623e97 100644 --- a/test_regress/t/t_clk_concat6.v +++ b/test_regress/t/t_clk_concat6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module some_module ( diff --git a/test_regress/t/t_clk_concat_vlt.py b/test_regress/t/t_clk_concat_vlt.py index d7ab3967c..a9dcc2716 100755 --- a/test_regress/t/t_clk_concat_vlt.py +++ b/test_regress/t/t_clk_concat_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_condflop.py b/test_regress/t/t_clk_condflop.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_condflop.py +++ b/test_regress/t/t_clk_condflop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_condflop.v b/test_regress/t/t_clk_condflop.v index 5563b1b82..f64151e29 100644 --- a/test_regress/t/t_clk_condflop.v +++ b/test_regress/t/t_clk_condflop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_clk_dpulse.py b/test_regress/t/t_clk_dpulse.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_dpulse.py +++ b/test_regress/t/t_clk_dpulse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_dpulse.v b/test_regress/t/t_clk_dpulse.v index 5ab490ffa..6a7b74236 100644 --- a/test_regress/t/t_clk_dpulse.v +++ b/test_regress/t/t_clk_dpulse.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_dsp.py b/test_regress/t/t_clk_dsp.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_dsp.py +++ b/test_regress/t/t_clk_dsp.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_dsp.v b/test_regress/t/t_clk_dsp.v index 6e761b17b..5d3c205c0 100644 --- a/test_regress/t/t_clk_dsp.v +++ b/test_regress/t/t_clk_dsp.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_first.py b/test_regress/t/t_clk_first.py index 88dfd68d3..27c706704 100755 --- a/test_regress/t/t_clk_first.py +++ b/test_regress/t/t_clk_first.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_first.v b/test_regress/t/t_clk_first.v index b2de33e7c..2080733d0 100644 --- a/test_regress/t/t_clk_first.v +++ b/test_regress/t/t_clk_first.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_first_bad.py b/test_regress/t/t_clk_first_bad.py index d087349a1..ecaf194bb 100755 --- a/test_regress/t/t_clk_first_bad.py +++ b/test_regress/t/t_clk_first_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_first_deprecated.py b/test_regress/t/t_clk_first_deprecated.py index f87d01c5b..4ede20df8 100755 --- a/test_regress/t/t_clk_first_deprecated.py +++ b/test_regress/t/t_clk_first_deprecated.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_first_deprecated.v b/test_regress/t/t_clk_first_deprecated.v index 5bf460c19..f0f38a74c 100644 --- a/test_regress/t/t_clk_first_deprecated.v +++ b/test_regress/t/t_clk_first_deprecated.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_gate_ext.py b/test_regress/t/t_clk_gate_ext.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_gate_ext.py +++ b/test_regress/t/t_clk_gate_ext.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_gate_ext.v b/test_regress/t/t_clk_gate_ext.v index 5f50801bf..1be4eec74 100644 --- a/test_regress/t/t_clk_gate_ext.v +++ b/test_regress/t/t_clk_gate_ext.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_clk_gated_1.py b/test_regress/t/t_clk_gated_1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_gated_1.py +++ b/test_regress/t/t_clk_gated_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_gated_1.v b/test_regress/t/t_clk_gated_1.v index 91b547259..a4bbebcaf 100644 --- a/test_regress/t/t_clk_gated_1.v +++ b/test_regress/t/t_clk_gated_1.v @@ -14,8 +14,8 @@ // // This test is added to facilitate experiments with solutions. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett . +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_gater.py b/test_regress/t/t_clk_gater.py index 507391524..e29687a19 100755 --- a/test_regress/t/t_clk_gater.py +++ b/test_regress/t/t_clk_gater.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_gater.v b/test_regress/t/t_clk_gater.v index fb5f43c60..1b14bc9b3 100644 --- a/test_regress/t/t_clk_gater.v +++ b/test_regress/t/t_clk_gater.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_gen.py b/test_regress/t/t_clk_gen.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_gen.py +++ b/test_regress/t/t_clk_gen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_gen.v b/test_regress/t/t_clk_gen.v index 34b4d2f7b..1e5c4a15d 100644 --- a/test_regress/t/t_clk_gen.v +++ b/test_regress/t/t_clk_gen.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_inp_init.cpp b/test_regress/t/t_clk_inp_init.cpp index f6f91d8d6..2c9e1e5f2 100644 --- a/test_regress/t/t_clk_inp_init.cpp +++ b/test_regress/t/t_clk_inp_init.cpp @@ -1,5 +1,5 @@ -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_clk_inp_init.py b/test_regress/t/t_clk_inp_init.py index f840b04dc..e561a74aa 100755 --- a/test_regress/t/t_clk_inp_init.py +++ b/test_regress/t/t_clk_inp_init.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the -# GNU Lesser General Public License Version 3 or the Perl Artistic -# License Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_inp_init.v b/test_regress/t/t_clk_inp_init.v index cc8ae8b47..aafc767bb 100644 --- a/test_regress/t/t_clk_inp_init.v +++ b/test_regress/t/t_clk_inp_init.v @@ -3,8 +3,8 @@ // This tests issue #1327 (Strange initialization behavior with // "VinpClk" cloned clock variables) // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Rupert Swarbrick (Argon Design). +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Rupert Swarbrick (Argon Design) // SPDX-License-Identifier: CC0-1.0 // bug1327 diff --git a/test_regress/t/t_clk_latch.py b/test_regress/t/t_clk_latch.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_latch.py +++ b/test_regress/t/t_clk_latch.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_latch.v b/test_regress/t/t_clk_latch.v index 4f1bf498f..28cd61119 100644 --- a/test_regress/t/t_clk_latch.v +++ b/test_regress/t/t_clk_latch.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_latch_edgestyle.py b/test_regress/t/t_clk_latch_edgestyle.py index 395d09419..886d943e2 100755 --- a/test_regress/t/t_clk_latch_edgestyle.py +++ b/test_regress/t/t_clk_latch_edgestyle.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_latchgate.py b/test_regress/t/t_clk_latchgate.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_latchgate.py +++ b/test_regress/t/t_clk_latchgate.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_latchgate.v b/test_regress/t/t_clk_latchgate.v index db9dae13d..484083a8c 100644 --- a/test_regress/t/t_clk_latchgate.v +++ b/test_regress/t/t_clk_latchgate.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // -------------------------------------------------------- diff --git a/test_regress/t/t_clk_powerdn.py b/test_regress/t/t_clk_powerdn.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clk_powerdn.py +++ b/test_regress/t/t_clk_powerdn.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_powerdn.v b/test_regress/t/t_clk_powerdn.v index e8dec908f..64e8f6f64 100644 --- a/test_regress/t/t_clk_powerdn.v +++ b/test_regress/t/t_clk_powerdn.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_scope_bad.py b/test_regress/t/t_clk_scope_bad.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_clk_scope_bad.py +++ b/test_regress/t/t_clk_scope_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_scope_bad.v b/test_regress/t/t_clk_scope_bad.v index 08b480ee5..f0fe53a15 100644 --- a/test_regress/t/t_clk_scope_bad.v +++ b/test_regress/t/t_clk_scope_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_vecgen1.py b/test_regress/t/t_clk_vecgen1.py index a61cd74d6..b341eb3c4 100755 --- a/test_regress/t/t_clk_vecgen1.py +++ b/test_regress/t/t_clk_vecgen1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_vecgen1.v b/test_regress/t/t_clk_vecgen1.v index c4eb66356..0f8948d12 100644 --- a/test_regress/t/t_clk_vecgen1.v +++ b/test_regress/t/t_clk_vecgen1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clk_vecgen2.py b/test_regress/t/t_clk_vecgen2.py index 6c46e2c7c..75eed1071 100755 --- a/test_regress/t/t_clk_vecgen2.py +++ b/test_regress/t/t_clk_vecgen2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clk_vecgen3.py b/test_regress/t/t_clk_vecgen3.py index 7e8939ce1..c3f505618 100755 --- a/test_regress/t/t_clk_vecgen3.py +++ b/test_regress/t/t_clk_vecgen3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocked_release_combo.py b/test_regress/t/t_clocked_release_combo.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clocked_release_combo.py +++ b/test_regress/t/t_clocked_release_combo.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocked_release_combo.v b/test_regress/t/t_clocked_release_combo.v index fe0605223..0698ffbfd 100644 --- a/test_regress/t/t_clocked_release_combo.v +++ b/test_regress/t/t_clocked_release_combo.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTIDRIVEN diff --git a/test_regress/t/t_clocker.py b/test_regress/t/t_clocker.py index dbb378eea..db2685982 100755 --- a/test_regress/t/t_clocker.py +++ b/test_regress/t/t_clocker.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocker.v b/test_regress/t/t_clocker.v index 7b84db7d8..e51d195e9 100644 --- a/test_regress/t/t_clocker.v +++ b/test_regress/t/t_clocker.v @@ -2,8 +2,8 @@ // // Trigger the CLKDATA detection // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Jie Xu // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; diff --git a/test_regress/t/t_clocking_bad1.py b/test_regress/t/t_clocking_bad1.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_clocking_bad1.py +++ b/test_regress/t/t_clocking_bad1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_bad1.v b/test_regress/t/t_clocking_bad1.v index 306b502f6..deed6ce53 100644 --- a/test_regress/t/t_clocking_bad1.v +++ b/test_regress/t/t_clocking_bad1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_clocking_bad2.py b/test_regress/t/t_clocking_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_clocking_bad2.py +++ b/test_regress/t/t_clocking_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_bad2.v b/test_regress/t/t_clocking_bad2.v index 85a6a35d2..a9386b0e6 100644 --- a/test_regress/t/t_clocking_bad2.v +++ b/test_regress/t/t_clocking_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_clocking_bad3.py b/test_regress/t/t_clocking_bad3.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_clocking_bad3.py +++ b/test_regress/t/t_clocking_bad3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_bad3.v b/test_regress/t/t_clocking_bad3.v index a7949e4a0..a529a9f4c 100644 --- a/test_regress/t/t_clocking_bad3.v +++ b/test_regress/t/t_clocking_bad3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_clocking_bad4.py b/test_regress/t/t_clocking_bad4.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_clocking_bad4.py +++ b/test_regress/t/t_clocking_bad4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_bad4.v b/test_regress/t/t_clocking_bad4.v index 58707a1af..00a35ea6c 100644 --- a/test_regress/t/t_clocking_bad4.v +++ b/test_regress/t/t_clocking_bad4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_clocking_bad5.py b/test_regress/t/t_clocking_bad5.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_clocking_bad5.py +++ b/test_regress/t/t_clocking_bad5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_bad5.v b/test_regress/t/t_clocking_bad5.v index 31eb33744..7af05b672 100644 --- a/test_regress/t/t_clocking_bad5.v +++ b/test_regress/t/t_clocking_bad5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_clocking_concat.py b/test_regress/t/t_clocking_concat.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_clocking_concat.py +++ b/test_regress/t/t_clocking_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_concat.v b/test_regress/t/t_clocking_concat.v index 027264dad..17e1bfe70 100644 --- a/test_regress/t/t_clocking_concat.v +++ b/test_regress/t/t_clocking_concat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clocking_empty_block.py b/test_regress/t/t_clocking_empty_block.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_clocking_empty_block.py +++ b/test_regress/t/t_clocking_empty_block.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_empty_block.v b/test_regress/t/t_clocking_empty_block.v index 8210ffcfd..76d371dcb 100644 --- a/test_regress/t/t_clocking_empty_block.v +++ b/test_regress/t/t_clocking_empty_block.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Alex Mykyta. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Alex Mykyta // SPDX-License-Identifier: CC0-1.0 module t(); diff --git a/test_regress/t/t_clocking_inout.py b/test_regress/t/t_clocking_inout.py index a4406cb80..bb3cf3bf1 100755 --- a/test_regress/t/t_clocking_inout.py +++ b/test_regress/t/t_clocking_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_inout.v b/test_regress/t/t_clocking_inout.v index 2e89aa9a3..cf93fd18d 100644 --- a/test_regress/t/t_clocking_inout.v +++ b/test_regress/t/t_clocking_inout.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_clocking_input_0_delay.py b/test_regress/t/t_clocking_input_0_delay.py index c55d45e6a..f498514dd 100755 --- a/test_regress/t/t_clocking_input_0_delay.py +++ b/test_regress/t/t_clocking_input_0_delay.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_input_0_delay.v b/test_regress/t/t_clocking_input_0_delay.v index 0a74dd834..0720c98d3 100644 --- a/test_regress/t/t_clocking_input_0_delay.v +++ b/test_regress/t/t_clocking_input_0_delay.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `timescale 1ms / 1ns diff --git a/test_regress/t/t_clocking_input_default.py b/test_regress/t/t_clocking_input_default.py index c55d45e6a..f498514dd 100755 --- a/test_regress/t/t_clocking_input_default.py +++ b/test_regress/t/t_clocking_input_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_input_default.v b/test_regress/t/t_clocking_input_default.v index 5832f7e80..0f282665c 100644 --- a/test_regress/t/t_clocking_input_default.v +++ b/test_regress/t/t_clocking_input_default.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `timescale 1ms / 1ns diff --git a/test_regress/t/t_clocking_notiming.py b/test_regress/t/t_clocking_notiming.py index 3e536886c..32315fac3 100755 --- a/test_regress/t/t_clocking_notiming.py +++ b/test_regress/t/t_clocking_notiming.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_notiming.v b/test_regress/t/t_clocking_notiming.v index 1c718fda8..80c2eba0d 100644 --- a/test_regress/t/t_clocking_notiming.v +++ b/test_regress/t/t_clocking_notiming.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_clocking_out_on_change.py b/test_regress/t/t_clocking_out_on_change.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_clocking_out_on_change.py +++ b/test_regress/t/t_clocking_out_on_change.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_out_on_change.v b/test_regress/t/t_clocking_out_on_change.v index a8730ca9f..63e35e1a7 100644 --- a/test_regress/t/t_clocking_out_on_change.v +++ b/test_regress/t/t_clocking_out_on_change.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_clocking_react.py b/test_regress/t/t_clocking_react.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_clocking_react.py +++ b/test_regress/t/t_clocking_react.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_react.v b/test_regress/t/t_clocking_react.v index 2f8a111d9..fed57a5a2 100644 --- a/test_regress/t/t_clocking_react.v +++ b/test_regress/t/t_clocking_react.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 interface axi_if; diff --git a/test_regress/t/t_clocking_sched.py b/test_regress/t/t_clocking_sched.py index 97abb660e..c03eaf086 100755 --- a/test_regress/t/t_clocking_sched.py +++ b/test_regress/t/t_clocking_sched.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_sched.v b/test_regress/t/t_clocking_sched.v index 44007f266..df4950cc9 100644 --- a/test_regress/t/t_clocking_sched.v +++ b/test_regress/t/t_clocking_sched.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_clocking_sched_timing.py b/test_regress/t/t_clocking_sched_timing.py index 5737cc7a9..81c152f91 100755 --- a/test_regress/t/t_clocking_sched_timing.py +++ b/test_regress/t/t_clocking_sched_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_sched_timing_forkproc.out b/test_regress/t/t_clocking_sched_timing_forkproc.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_clocking_sched_timing_forkproc.py b/test_regress/t/t_clocking_sched_timing_forkproc.py index 25f9bb0ff..eef7522eb 100755 --- a/test_regress/t/t_clocking_sched_timing_forkproc.py +++ b/test_regress/t/t_clocking_sched_timing_forkproc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_timing.v b/test_regress/t/t_clocking_timing.v index 0c19d9a0e..b8188242f 100644 --- a/test_regress/t/t_clocking_timing.v +++ b/test_regress/t/t_clocking_timing.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `timescale 10ns/1ns diff --git a/test_regress/t/t_clocking_timing1.py b/test_regress/t/t_clocking_timing1.py index 23fe7bdeb..449fd97df 100755 --- a/test_regress/t/t_clocking_timing1.py +++ b/test_regress/t/t_clocking_timing1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_timing2.py b/test_regress/t/t_clocking_timing2.py index f34cb10f1..64fbfad5e 100755 --- a/test_regress/t/t_clocking_timing2.py +++ b/test_regress/t/t_clocking_timing2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_unsup1.py b/test_regress/t/t_clocking_unsup1.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_clocking_unsup1.py +++ b/test_regress/t/t_clocking_unsup1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_unsup1.v b/test_regress/t/t_clocking_unsup1.v index a15a9212d..16a14a248 100644 --- a/test_regress/t/t_clocking_unsup1.v +++ b/test_regress/t/t_clocking_unsup1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_clocking_unsup2.py b/test_regress/t/t_clocking_unsup2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_clocking_unsup2.py +++ b/test_regress/t/t_clocking_unsup2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_unsup2.v b/test_regress/t/t_clocking_unsup2.v index 17babaa15..4fec1b610 100644 --- a/test_regress/t/t_clocking_unsup2.v +++ b/test_regress/t/t_clocking_unsup2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_clocking_virtual.py b/test_regress/t/t_clocking_virtual.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_clocking_virtual.py +++ b/test_regress/t/t_clocking_virtual.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_virtual.v b/test_regress/t/t_clocking_virtual.v index 75a7d58fe..206b0495b 100644 --- a/test_regress/t/t_clocking_virtual.v +++ b/test_regress/t/t_clocking_virtual.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 interface Iface; diff --git a/test_regress/t/t_clocking_xref.py b/test_regress/t/t_clocking_xref.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_clocking_xref.py +++ b/test_regress/t/t_clocking_xref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_clocking_xref.v b/test_regress/t/t_clocking_xref.v index 8d4d021ad..ca70d7a5c 100644 --- a/test_regress/t/t_clocking_xref.v +++ b/test_regress/t/t_clocking_xref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module mod; diff --git a/test_regress/t/t_comb_do_not_convert_to.py b/test_regress/t/t_comb_do_not_convert_to.py index a5c94d9ff..b3e1bba47 100755 --- a/test_regress/t/t_comb_do_not_convert_to.py +++ b/test_regress/t/t_comb_do_not_convert_to.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_comb_do_not_convert_to.v b/test_regress/t/t_comb_do_not_convert_to.v index f80ce544b..33b172315 100644 --- a/test_regress/t/t_comb_do_not_convert_to.v +++ b/test_regress/t/t_comb_do_not_convert_to.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_comb_input_0.cpp b/test_regress/t/t_comb_input_0.cpp index b08087648..ae4dc3cf6 100644 --- a/test_regress/t/t_comb_input_0.cpp +++ b/test_regress/t/t_comb_input_0.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_comb_input_0.py b/test_regress/t/t_comb_input_0.py index 74e183dab..4af222ac3 100755 --- a/test_regress/t/t_comb_input_0.py +++ b/test_regress/t/t_comb_input_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_comb_input_0.v b/test_regress/t/t_comb_input_0.v index d66ba66c8..8ed63208b 100644 --- a/test_regress/t/t_comb_input_0.v +++ b/test_regress/t/t_comb_input_0.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 diff --git a/test_regress/t/t_comb_input_1.cpp b/test_regress/t/t_comb_input_1.cpp index 62acf8373..c1dfa74d9 100644 --- a/test_regress/t/t_comb_input_1.cpp +++ b/test_regress/t/t_comb_input_1.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_comb_input_1.py b/test_regress/t/t_comb_input_1.py index 4f9f6115e..f2488ae17 100755 --- a/test_regress/t/t_comb_input_1.py +++ b/test_regress/t/t_comb_input_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_comb_input_1.v b/test_regress/t/t_comb_input_1.v index 0d057b28d..98a81e175 100644 --- a/test_regress/t/t_comb_input_1.v +++ b/test_regress/t/t_comb_input_1.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 diff --git a/test_regress/t/t_comb_input_2.cpp b/test_regress/t/t_comb_input_2.cpp index 0f3534650..28e6f1793 100644 --- a/test_regress/t/t_comb_input_2.cpp +++ b/test_regress/t/t_comb_input_2.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_comb_input_2.py b/test_regress/t/t_comb_input_2.py index 4f9f6115e..f2488ae17 100755 --- a/test_regress/t/t_comb_input_2.py +++ b/test_regress/t/t_comb_input_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_comb_input_2.v b/test_regress/t/t_comb_input_2.v index f90d5bb9b..d2047021b 100644 --- a/test_regress/t/t_comb_input_2.v +++ b/test_regress/t/t_comb_input_2.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.py b/test_regress/t/t_comb_loop_through_unpacked_array.py index d16f85d79..9ecd0205a 100755 --- a/test_regress/t/t_comb_loop_through_unpacked_array.py +++ b/test_regress/t/t_comb_loop_through_unpacked_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.v b/test_regress/t/t_comb_loop_through_unpacked_array.v index 1e2d26052..d7992c98f 100644 --- a/test_regress/t/t_comb_loop_through_unpacked_array.v +++ b/test_regress/t/t_comb_loop_through_unpacked_array.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top( diff --git a/test_regress/t/t_compiler_include.cpp b/test_regress/t/t_compiler_include.cpp index 7c5792f66..c581a8d65 100644 --- a/test_regress/t/t_compiler_include.cpp +++ b/test_regress/t/t_compiler_include.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_compiler_include.h b/test_regress/t/t_compiler_include.h index 7a18a8501..71b43a9bf 100644 --- a/test_regress/t/t_compiler_include.h +++ b/test_regress/t/t_compiler_include.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_compiler_include.py b/test_regress/t/t_compiler_include.py index f2d4a6302..8f60d60bf 100755 --- a/test_regress/t/t_compiler_include.py +++ b/test_regress/t/t_compiler_include.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_compiler_include.v b/test_regress/t/t_compiler_include.v index a6d76d187..90437a0b3 100644 --- a/test_regress/t/t_compiler_include.v +++ b/test_regress/t/t_compiler_include.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (input logic[31:0] in, output logic[31:0] out); diff --git a/test_regress/t/t_compiler_include_dpi.cpp b/test_regress/t/t_compiler_include_dpi.cpp index e3ed99be7..9ecb583af 100644 --- a/test_regress/t/t_compiler_include_dpi.cpp +++ b/test_regress/t/t_compiler_include_dpi.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_compiler_include_dpi.h b/test_regress/t/t_compiler_include_dpi.h index a985d65a6..84fca1777 100644 --- a/test_regress/t/t_compiler_include_dpi.h +++ b/test_regress/t/t_compiler_include_dpi.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_compiler_include_dpi.py b/test_regress/t/t_compiler_include_dpi.py index af749e59f..880bd38ad 100755 --- a/test_regress/t/t_compiler_include_dpi.py +++ b/test_regress/t/t_compiler_include_dpi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_compiler_include_dpi.v b/test_regress/t/t_compiler_include_dpi.v index 4cc0c3d84..25f6dd00a 100644 --- a/test_regress/t/t_compiler_include_dpi.v +++ b/test_regress/t/t_compiler_include_dpi.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_compiler_include_dpi_split.py b/test_regress/t/t_compiler_include_dpi_split.py index 6f69ac393..fe8783f52 100755 --- a/test_regress/t/t_compiler_include_dpi_split.py +++ b/test_regress/t/t_compiler_include_dpi_split.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_compiler_include_split.py b/test_regress/t/t_compiler_include_split.py index daae2e49f..d69770ed4 100755 --- a/test_regress/t/t_compiler_include_split.py +++ b/test_regress/t/t_compiler_include_split.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_concat_casts.py b/test_regress/t/t_concat_casts.py index c39e83d77..903201f15 100755 --- a/test_regress/t/t_concat_casts.py +++ b/test_regress/t/t_concat_casts.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_concat_casts.v b/test_regress/t/t_concat_casts.v index beb5c8637..014348ad7 100644 --- a/test_regress/t/t_concat_casts.v +++ b/test_regress/t/t_concat_casts.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package my_pkg; diff --git a/test_regress/t/t_concat_impure.py b/test_regress/t/t_concat_impure.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_concat_impure.py +++ b/test_regress/t/t_concat_impure.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_concat_impure.v b/test_regress/t/t_concat_impure.v index fc7c1e9e3..16499b370 100644 --- a/test_regress/t/t_concat_impure.v +++ b/test_regress/t/t_concat_impure.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 int global_variable = 0; diff --git a/test_regress/t/t_concat_init_array_functions.py b/test_regress/t/t_concat_init_array_functions.py new file mode 100755 index 000000000..3cc73805c --- /dev/null +++ b/test_regress/t/t_concat_init_array_functions.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_init_array_functions.v b/test_regress/t/t_concat_init_array_functions.v new file mode 100644 index 000000000..5ea585894 --- /dev/null +++ b/test_regress/t/t_concat_init_array_functions.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Simple test for unpacked concatenation arrays used as function arguments. +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 +// + +class A; + int r1[2]; + int r2; +endclass + +class B; + virtual function int B_virt_func(int r[3], p[4]); + return r[0] + r[1] + r[2] + p[0] + p[1] + p[2] + p[3]; + endfunction +endclass + +function int func_1_concat(int r[4]); + // verilator no_inline_task + return r[0] + r[1] + r[2] + r[3]; +endfunction + +function int func_2_concat(int r[3], int p[4]); + // verilator no_inline_task + return r[0] + r[1] + r[2] + p[0] + p[1] + p[2] + p[3]; +endfunction + +module t; + int s; + A a = new; + B b = new; + initial begin + a.r1 = {1, 2}; + a.r2 = 5; + s = func_1_concat({a.r1, a.r1}); + if (s != 6) $stop; + + s = func_2_concat({a.r1, a.r2}, {a.r1, a.r1}); + if (s != 14) $stop; + + s = b.B_virt_func({a.r1, a.r2}, {a.r1, a.r1}); + if (s != 14) $stop; + + $write("*-* All finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_concat_large.py b/test_regress/t/t_concat_large.py index d4f986441..8d105c7c5 100755 --- a/test_regress/t/t_concat_large.py +++ b/test_regress/t/t_concat_large.py @@ -1,17 +1,17 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap -test.scenarios('simulator') +test.scenarios("simulator") -test.compile() +test.compile(verilator_flags2=["--Wno-WIDTHCONCAT"]) test.execute() diff --git a/test_regress/t/t_concat_large.v b/test_regress/t/t_concat_large.v index d95caf46c..3e4c37caf 100644 --- a/test_regress/t/t_concat_large.v +++ b/test_regress/t/t_concat_large.v @@ -1,20 +1,20 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - reg [32767:0] a; + reg [32767:0] a; - initial begin - // verilator lint_off WIDTHCONCAT - a = {32768{1'b1}}; - // verilator lint_on WIDTHCONCAT - if (a[32000] != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + a = {32768{1'b1}}; + if (a[32000] != 1'b1) $stop; + a = '0; + if (a[32000] != 1'b0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_concat_large_bad.out b/test_regress/t/t_concat_large_bad.out index 9ae1fcc8c..b38ad127c 100644 --- a/test_regress/t/t_concat_large_bad.out +++ b/test_regress/t/t_concat_large_bad.out @@ -1,7 +1,11 @@ -%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:9:29: More than a 8k bit replication is probably wrong: 32768 - : ... note: In instance 't' - 9 | wire [32767:0] a = {32768{1'b1}}; - | ^ +%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:10:22: Replication of more that --replication-limit 8192 is suspect: 32768 + : ... note: In instance 't' + 10 | wire [32767:0] b = '0; + | ^~ ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. +%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:9:28: Replication of more that --replication-limit 8192 is suspect: 32768 + : ... note: In instance 't' + 9 | wire [32767:0] a = {32768{1'b1}}; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_concat_large_bad.py b/test_regress/t/t_concat_large_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_concat_large_bad.py +++ b/test_regress/t/t_concat_large_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_concat_large_bad.v b/test_regress/t/t_concat_large_bad.v index 5b7309f84..5920c79fc 100644 --- a/test_regress/t/t_concat_large_bad.v +++ b/test_regress/t/t_concat_large_bad.v @@ -1,15 +1,16 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - wire [32767:0] a = {32768{1'b1}}; + wire [32767:0] a = {32768{1'b1}}; + wire [32767:0] b = '0; - initial begin - $stop; - end + initial begin + $stop; + end endmodule diff --git a/test_regress/t/t_concat_large_flag.py b/test_regress/t/t_concat_large_flag.py new file mode 100755 index 000000000..ba2879438 --- /dev/null +++ b/test_regress/t/t_concat_large_flag.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios("simulator") +test.top_filename = "t/t_concat_large.v" + +test.compile(verilator_flags2=["--replication-limit 32768"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_large_flag_zero.py b/test_regress/t/t_concat_large_flag_zero.py new file mode 100755 index 000000000..feda09073 --- /dev/null +++ b/test_regress/t/t_concat_large_flag_zero.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios("simulator") +test.top_filename = "t/t_concat_large.v" + +test.compile(verilator_flags2=["--replication-limit 0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_concat_link_bad.py b/test_regress/t/t_concat_link_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_concat_link_bad.py +++ b/test_regress/t/t_concat_link_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_concat_link_bad.v b/test_regress/t/t_concat_link_bad.v index 44f6cf068..576f03b59 100644 --- a/test_regress/t/t_concat_link_bad.v +++ b/test_regress/t/t_concat_link_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019. +// This file ONLY is placed into the Public Domain. +// SPDX-FileCopyrightText: 2019 // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_concat_opt.py b/test_regress/t/t_concat_opt.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_concat_opt.py +++ b/test_regress/t/t_concat_opt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_concat_opt.v b/test_regress/t/t_concat_opt.v index 5a09562af..3f85fa53b 100644 --- a/test_regress/t/t_concat_opt.v +++ b/test_regress/t/t_concat_opt.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Jie Xu // SPDX-License-Identifier: CC0-1.0 // // The test was added together with the concat optimization. diff --git a/test_regress/t/t_concat_or.py b/test_regress/t/t_concat_or.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_concat_or.py +++ b/test_regress/t/t_concat_or.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_concat_or.v b/test_regress/t/t_concat_or.v index 17b05cb4b..5fa2acd57 100644 --- a/test_regress/t/t_concat_or.v +++ b/test_regress/t/t_concat_or.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_concat_sel.py b/test_regress/t/t_concat_sel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_concat_sel.py +++ b/test_regress/t/t_concat_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_concat_sel.v b/test_regress/t/t_concat_sel.v index 605794d85..295680318 100644 --- a/test_regress/t/t_concat_sel.v +++ b/test_regress/t/t_concat_sel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_concat_string.py b/test_regress/t/t_concat_string.py index 52c58524e..a768af0c2 100755 --- a/test_regress/t/t_concat_string.py +++ b/test_regress/t/t_concat_string.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_concat_string.v b/test_regress/t/t_concat_string.v index c05655891..a8c36346e 100644 --- a/test_regress/t/t_concat_string.v +++ b/test_regress/t/t_concat_string.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef enum {efgh} en; diff --git a/test_regress/t/t_concat_unpack.py b/test_regress/t/t_concat_unpack.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_concat_unpack.py +++ b/test_regress/t/t_concat_unpack.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_concat_unpack.v b/test_regress/t/t_concat_unpack.v index 8d3f4bac2..41ff5f43c 100644 --- a/test_regress/t/t_concat_unpack.v +++ b/test_regress/t/t_concat_unpack.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_config_default.py b/test_regress/t/t_config_default.py index 628079b8b..5d7cf12fe 100755 --- a/test_regress/t/t_config_default.py +++ b/test_regress/t/t_config_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_default.v b/test_regress/t/t_config_default.v index 03a847904..d1e964e92 100644 --- a/test_regress/t/t_config_default.v +++ b/test_regress/t/t_config_default.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_config_hier.py b/test_regress/t/t_config_hier.py index d595a0443..c61d0cdbe 100755 --- a/test_regress/t/t_config_hier.py +++ b/test_regress/t/t_config_hier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_hier.v b/test_regress/t/t_config_hier.v index 2f71a6b91..87029b07e 100644 --- a/test_regress/t/t_config_hier.v +++ b/test_regress/t/t_config_hier.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Test several ways of using config to specify different hierarchies When done, diff --git a/test_regress/t/t_config_include_bad.py b/test_regress/t/t_config_include_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_config_include_bad.py +++ b/test_regress/t/t_config_include_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_include_bad.v b/test_regress/t/t_config_include_bad.v index 696d8f8e6..2c9aed81e 100644 --- a/test_regress/t/t_config_include_bad.v +++ b/test_regress/t/t_config_include_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 include "meant_to_tick_include.v" diff --git a/test_regress/t/t_config_inst.py b/test_regress/t/t_config_inst.py index 628079b8b..5d7cf12fe 100755 --- a/test_regress/t/t_config_inst.py +++ b/test_regress/t/t_config_inst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_inst.v b/test_regress/t/t_config_inst.v index 1f6bc507b..49620fe7d 100644 --- a/test_regress/t/t_config_inst.v +++ b/test_regress/t/t_config_inst.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_config_inst_missing.py b/test_regress/t/t_config_inst_missing.py index c920a018c..51390d67e 100755 --- a/test_regress/t/t_config_inst_missing.py +++ b/test_regress/t/t_config_inst_missing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_inst_missing.v b/test_regress/t/t_config_inst_missing.v index 43dbfebe0..5c6547265 100644 --- a/test_regress/t/t_config_inst_missing.v +++ b/test_regress/t/t_config_inst_missing.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_config_liblist.py b/test_regress/t/t_config_liblist.py index 628079b8b..5d7cf12fe 100755 --- a/test_regress/t/t_config_liblist.py +++ b/test_regress/t/t_config_liblist.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_liblist.v b/test_regress/t/t_config_liblist.v index 3d131145a..eb3ab8666 100644 --- a/test_regress/t/t_config_liblist.v +++ b/test_regress/t/t_config_liblist.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_config_libmap.py b/test_regress/t/t_config_libmap.py index cd5705948..aab9c894e 100755 --- a/test_regress/t/t_config_libmap.py +++ b/test_regress/t/t_config_libmap.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_libmap.v b/test_regress/t/t_config_libmap.v index 3d5df6376..56d5f5442 100644 --- a/test_regress/t/t_config_libmap.v +++ b/test_regress/t/t_config_libmap.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_config_libmap/lib.map b/test_regress/t/t_config_libmap/lib.map index 1393eb2d3..ab2d2941a 100644 --- a/test_regress/t/t_config_libmap/lib.map +++ b/test_regress/t/t_config_libmap/lib.map @@ -1,8 +1,8 @@ // -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // lib.map file: diff --git a/test_regress/t/t_config_libmap/m1.v b/test_regress/t/t_config_libmap/m1.v index 7322ff636..96df22b16 100644 --- a/test_regress/t/t_config_libmap/m1.v +++ b/test_regress/t/t_config_libmap/m1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m1; diff --git a/test_regress/t/t_config_libmap/m2.sv b/test_regress/t/t_config_libmap/m2.sv index debd8ce2b..78699ad87 100644 --- a/test_regress/t/t_config_libmap/m2.sv +++ b/test_regress/t/t_config_libmap/m2.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m2; diff --git a/test_regress/t/t_config_libmap/m3.vg b/test_regress/t/t_config_libmap/m3.vg index 4e28607c5..1cdd74c20 100644 --- a/test_regress/t/t_config_libmap/m3.vg +++ b/test_regress/t/t_config_libmap/m3.vg @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m3; diff --git a/test_regress/t/t_config_libmap/m5.v b/test_regress/t/t_config_libmap/m5.v index 45465c839..1dbb4731e 100644 --- a/test_regress/t/t_config_libmap/m5.v +++ b/test_regress/t/t_config_libmap/m5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m5; diff --git a/test_regress/t/t_config_libmap/sub/other.sv b/test_regress/t/t_config_libmap/sub/other.sv index e95618256..75023ab03 100644 --- a/test_regress/t/t_config_libmap/sub/other.sv +++ b/test_regress/t/t_config_libmap/sub/other.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module other; diff --git a/test_regress/t/t_config_libmap/x4.v b/test_regress/t/t_config_libmap/x4.v index d7b4f8e9f..918faa433 100644 --- a/test_regress/t/t_config_libmap/x4.v +++ b/test_regress/t/t_config_libmap/x4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module x4; diff --git a/test_regress/t/t_config_libmap_inc.map b/test_regress/t/t_config_libmap_inc.map index 1d01af834..ce80ea071 100644 --- a/test_regress/t/t_config_libmap_inc.map +++ b/test_regress/t/t_config_libmap_inc.map @@ -1,8 +1,8 @@ // -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // lib.map file: diff --git a/test_regress/t/t_config_libmap_inc.py b/test_regress/t/t_config_libmap_inc.py index 8f74f06cf..10db367a5 100755 --- a/test_regress/t/t_config_libmap_inc.py +++ b/test_regress/t/t_config_libmap_inc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_libmap_inc.v b/test_regress/t/t_config_libmap_inc.v index c24a75a62..64e5c0081 100644 --- a/test_regress/t/t_config_libmap_inc.v +++ b/test_regress/t/t_config_libmap_inc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_config_multitop.py b/test_regress/t/t_config_multitop.py index 55c7eceab..39cee3d81 100755 --- a/test_regress/t/t_config_multitop.py +++ b/test_regress/t/t_config_multitop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_multitop.v b/test_regress/t/t_config_multitop.v index 0fce4b478..16afd9b37 100644 --- a/test_regress/t/t_config_multitop.v +++ b/test_regress/t/t_config_multitop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTITOP diff --git a/test_regress/t/t_config_param.py b/test_regress/t/t_config_param.py index 6a0214ee8..81cb73e79 100755 --- a/test_regress/t/t_config_param.py +++ b/test_regress/t/t_config_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_param.v b/test_regress/t/t_config_param.v index 398a1486a..f3ba336ee 100644 --- a/test_regress/t/t_config_param.v +++ b/test_regress/t/t_config_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m1; diff --git a/test_regress/t/t_config_rules.py b/test_regress/t/t_config_rules.py index 2da127041..c422c716d 100755 --- a/test_regress/t/t_config_rules.py +++ b/test_regress/t/t_config_rules.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_rules.v b/test_regress/t/t_config_rules.v index 38f47a1ce..d6e3fafa6 100644 --- a/test_regress/t/t_config_rules.v +++ b/test_regress/t/t_config_rules.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_config_rules_sub.v b/test_regress/t/t_config_rules_sub.v index 5d8c7cbe7..1ed25de6c 100644 --- a/test_regress/t/t_config_rules_sub.v +++ b/test_regress/t/t_config_rules_sub.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_config_top.py b/test_regress/t/t_config_top.py index ca0397f58..4805ea972 100755 --- a/test_regress/t/t_config_top.py +++ b/test_regress/t/t_config_top.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_top.v b/test_regress/t/t_config_top.v index c444a4f19..550ed79c3 100644 --- a/test_regress/t/t_config_top.v +++ b/test_regress/t/t_config_top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m1; diff --git a/test_regress/t/t_config_top2.py b/test_regress/t/t_config_top2.py index 55622426b..fd2877e7a 100755 --- a/test_regress/t/t_config_top2.py +++ b/test_regress/t/t_config_top2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_top2.v b/test_regress/t/t_config_top2.v index e85336130..af646c698 100644 --- a/test_regress/t/t_config_top2.v +++ b/test_regress/t/t_config_top2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTITOP diff --git a/test_regress/t/t_config_work.map b/test_regress/t/t_config_work.map index 2e50445e4..fdc1bfb5d 100644 --- a/test_regress/t/t_config_work.map +++ b/test_regress/t/t_config_work.map @@ -1,8 +1,8 @@ // -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // lib.map file: diff --git a/test_regress/t/t_config_work.py b/test_regress/t/t_config_work.py index c39443cc5..939399456 100755 --- a/test_regress/t/t_config_work.py +++ b/test_regress/t/t_config_work.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_config_work.v b/test_regress/t/t_config_work.v index d82e87e3e..c1d7b1154 100644 --- a/test_regress/t/t_config_work.v +++ b/test_regress/t/t_config_work.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_config_work__liba.v b/test_regress/t/t_config_work__liba.v index e41e44fc4..8d1130376 100644 --- a/test_regress/t/t_config_work__liba.v +++ b/test_regress/t/t_config_work__liba.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m1; diff --git a/test_regress/t/t_config_work__libb.v b/test_regress/t/t_config_work__libb.v index 96b61c137..0d8a77c5b 100644 --- a/test_regress/t/t_config_work__libb.v +++ b/test_regress/t/t_config_work__libb.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m2; diff --git a/test_regress/t/t_const.py b/test_regress/t/t_const.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_const.py +++ b/test_regress/t/t_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const.v b/test_regress/t/t_const.v index 8c09bd483..e142ce051 100644 --- a/test_regress/t/t_const.v +++ b/test_regress/t/t_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_const_bad.py b/test_regress/t/t_const_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_const_bad.py +++ b/test_regress/t/t_const_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_bad.v b/test_regress/t/t_const_bad.v index c8f820d64..6d3edd361 100644 --- a/test_regress/t/t_const_bad.v +++ b/test_regress/t/t_const_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_const_bitoptree_bug3096.cpp b/test_regress/t/t_const_bitoptree_bug3096.cpp index e8fec7a42..ab61d7d29 100644 --- a/test_regress/t/t_const_bitoptree_bug3096.cpp +++ b/test_regress/t/t_const_bitoptree_bug3096.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_const_bitoptree_bug3096.py b/test_regress/t/t_const_bitoptree_bug3096.py index 1b17842fa..ab913e2a1 100755 --- a/test_regress/t/t_const_bitoptree_bug3096.py +++ b/test_regress/t/t_const_bitoptree_bug3096.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_bitoptree_bug3096.v b/test_regress/t/t_const_bitoptree_bug3096.v index 2f3e42f97..6d783a25e 100644 --- a/test_regress/t/t_const_bitoptree_bug3096.v +++ b/test_regress/t/t_const_bitoptree_bug3096.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // From issue #3096 diff --git a/test_regress/t/t_const_dec_mixed_bad.py b/test_regress/t/t_const_dec_mixed_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_const_dec_mixed_bad.py +++ b/test_regress/t/t_const_dec_mixed_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_dec_mixed_bad.v b/test_regress/t/t_const_dec_mixed_bad.v index 2e0008627..99ac432f4 100644 --- a/test_regress/t/t_const_dec_mixed_bad.v +++ b/test_regress/t/t_const_dec_mixed_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_const_hi.py b/test_regress/t/t_const_hi.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_const_hi.py +++ b/test_regress/t/t_const_hi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_hi.v b/test_regress/t/t_const_hi.v index edf2afef4..5843d2d18 100644 --- a/test_regress/t/t_const_hi.v +++ b/test_regress/t/t_const_hi.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Wilson Snyder. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_const_number_bad.py b/test_regress/t/t_const_number_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_const_number_bad.py +++ b/test_regress/t/t_const_number_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_number_bad.v b/test_regress/t/t_const_number_bad.v index 3d9499dd1..b10a58750 100644 --- a/test_regress/t/t_const_number_bad.v +++ b/test_regress/t/t_const_number_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_const_number_unsized.py b/test_regress/t/t_const_number_unsized.py index dbdaf4551..1a93d5310 100755 --- a/test_regress/t/t_const_number_unsized.py +++ b/test_regress/t/t_const_number_unsized.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_number_unsized.v b/test_regress/t/t_const_number_unsized.v index 2f9a54b63..e3d32a420 100644 --- a/test_regress/t/t_const_number_unsized.v +++ b/test_regress/t/t_const_number_unsized.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_const_number_unsized_parse.py b/test_regress/t/t_const_number_unsized_parse.py index 092854947..6b6dd57d9 100755 --- a/test_regress/t/t_const_number_unsized_parse.py +++ b/test_regress/t/t_const_number_unsized_parse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_number_v_bad.py b/test_regress/t/t_const_number_v_bad.py index 93c8b0951..d72fa2fd2 100755 --- a/test_regress/t/t_const_number_v_bad.py +++ b/test_regress/t/t_const_number_v_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_number_v_bad.v b/test_regress/t/t_const_number_v_bad.v index 6af2b6ec8..c9564cd70 100644 --- a/test_regress/t/t_const_number_v_bad.v +++ b/test_regress/t/t_const_number_v_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of Verilog and SystemVerilog integer literal differences // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Ethan Sifferman. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Ethan Sifferman // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_const_op_red_scope.py b/test_regress/t/t_const_op_red_scope.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_const_op_red_scope.py +++ b/test_regress/t/t_const_op_red_scope.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_op_red_scope.v b/test_regress/t/t_const_op_red_scope.v index 5e43e01c1..520bc2eb8 100644 --- a/test_regress/t/t_const_op_red_scope.v +++ b/test_regress/t/t_const_op_red_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_const_overflow_bad.py b/test_regress/t/t_const_overflow_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_const_overflow_bad.py +++ b/test_regress/t/t_const_overflow_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_overflow_bad.v b/test_regress/t/t_const_overflow_bad.v index c86566607..fd6301033 100644 --- a/test_regress/t/t_const_overflow_bad.v +++ b/test_regress/t/t_const_overflow_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_const_sel_sel_extend.py b/test_regress/t/t_const_sel_sel_extend.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_const_sel_sel_extend.py +++ b/test_regress/t/t_const_sel_sel_extend.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_sel_sel_extend.v b/test_regress/t/t_const_sel_sel_extend.v index c695de4f2..40304abc8 100644 --- a/test_regress/t/t_const_sel_sel_extend.v +++ b/test_regress/t/t_const_sel_sel_extend.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t( diff --git a/test_regress/t/t_const_slicesel.py b/test_regress/t/t_const_slicesel.py index 290deb6cd..dcd255012 100755 --- a/test_regress/t/t_const_slicesel.py +++ b/test_regress/t/t_const_slicesel.py @@ -2,10 +2,10 @@ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_slicesel.v b/test_regress/t/t_const_slicesel.v index 8b5bd8251..d77eb2696 100644 --- a/test_regress/t/t_const_slicesel.v +++ b/test_regress/t/t_const_slicesel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Michael Lefebvre. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Michael Lefebvre // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_const_slicesel_bad.py b/test_regress/t/t_const_slicesel_bad.py index 726bc29ec..9bae681d3 100755 --- a/test_regress/t/t_const_slicesel_bad.py +++ b/test_regress/t/t_const_slicesel_bad.py @@ -2,10 +2,10 @@ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_slicesel_bad.v b/test_regress/t/t_const_slicesel_bad.v index e5a9edbc5..afc37449f 100644 --- a/test_regress/t/t_const_slicesel_bad.v +++ b/test_regress/t/t_const_slicesel_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Michael Lefebvre. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Michael Lefebvre // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_const_string_func.py b/test_regress/t/t_const_string_func.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_const_string_func.py +++ b/test_regress/t/t_const_string_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_const_string_func.v b/test_regress/t/t_const_string_func.v index d410d7a27..275f37078 100644 --- a/test_regress/t/t_const_string_func.v +++ b/test_regress/t/t_const_string_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: constant string functions // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_constraint.py b/test_regress/t/t_constraint.py index dbae8a1dc..87b346af1 100755 --- a/test_regress/t/t_constraint.py +++ b/test_regress/t/t_constraint.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint.v b/test_regress/t/t_constraint.v index b3296fc16..d0240ece0 100644 --- a/test_regress/t/t_constraint.v +++ b/test_regress/t/t_constraint.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Packet; diff --git a/test_regress/t/t_constraint_assoc_arr_bad.py b/test_regress/t/t_constraint_assoc_arr_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_constraint_assoc_arr_bad.py +++ b/test_regress/t/t_constraint_assoc_arr_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_assoc_arr_bad.v b/test_regress/t/t_constraint_assoc_arr_bad.v old mode 100755 new mode 100644 index 644b19f30..05893bf2a --- a/test_regress/t/t_constraint_assoc_arr_bad.v +++ b/test_regress/t/t_constraint_assoc_arr_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 // Long String index associative array diff --git a/test_regress/t/t_constraint_assoc_arr_basic.py b/test_regress/t/t_constraint_assoc_arr_basic.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_assoc_arr_basic.py +++ b/test_regress/t/t_constraint_assoc_arr_basic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_assoc_arr_basic.v b/test_regress/t/t_constraint_assoc_arr_basic.v index 754b77221..02799421c 100644 --- a/test_regress/t/t_constraint_assoc_arr_basic.v +++ b/test_regress/t/t_constraint_assoc_arr_basic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 class constrained_associative_array_basic; diff --git a/test_regress/t/t_constraint_assoc_arr_others.py b/test_regress/t/t_constraint_assoc_arr_others.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_assoc_arr_others.py +++ b/test_regress/t/t_constraint_assoc_arr_others.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_assoc_arr_others.v b/test_regress/t/t_constraint_assoc_arr_others.v old mode 100755 new mode 100644 index badbc3387..3cae0007c --- a/test_regress/t/t_constraint_assoc_arr_others.v +++ b/test_regress/t/t_constraint_assoc_arr_others.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 // Enum-based associative array diff --git a/test_regress/t/t_constraint_assoc_arr_wide.py b/test_regress/t/t_constraint_assoc_arr_wide.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_assoc_arr_wide.py +++ b/test_regress/t/t_constraint_assoc_arr_wide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_assoc_arr_wide.v b/test_regress/t/t_constraint_assoc_arr_wide.v old mode 100755 new mode 100644 index 52dca3fc2..43dec6fac --- a/test_regress/t/t_constraint_assoc_arr_wide.v +++ b/test_regress/t/t_constraint_assoc_arr_wide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 class AssocIntegralWide; diff --git a/test_regress/t/t_constraint_before_randc_bad.py b/test_regress/t/t_constraint_before_randc_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_constraint_before_randc_bad.py +++ b/test_regress/t/t_constraint_before_randc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_before_randc_bad.v b/test_regress/t/t_constraint_before_randc_bad.v index e028f9096..9c8868d41 100644 --- a/test_regress/t/t_constraint_before_randc_bad.v +++ b/test_regress/t/t_constraint_before_randc_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls1; diff --git a/test_regress/t/t_constraint_cond.py b/test_regress/t/t_constraint_cond.py new file mode 100755 index 000000000..ab048b5e8 --- /dev/null +++ b/test_regress/t/t_constraint_cond.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_cond.v b/test_regress/t/t_constraint_cond.v new file mode 100644 index 000000000..18cf81dd5 --- /dev/null +++ b/test_regress/t/t_constraint_cond.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`define check_rand(cl, field, cond) \ +begin \ + automatic longint prev_result; \ + automatic int ok; \ + if (!bit'(cl.randomize())) $stop; \ + prev_result = longint'(field); \ + if (!(cond)) $stop; \ + repeat(9) begin \ + longint result; \ + if (!bit'(cl.randomize())) $stop; \ + result = longint'(field); \ + if (!(cond)) $stop; \ + if (result != prev_result) ok = 1; \ + prev_result = result; \ + end \ + if (ok != 1) $stop; \ +end + +class Cls; + int d; + rand int y; + rand bit i; + + constraint q { + if (i) { + ((d == 0) ? y == 0 : 1'b1); + } + } +endclass + +module t; + Cls cls = new; + initial begin + `check_rand(cls, cls.y, cls.i == 0 || cls.y == 0); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_countbits_unsup.out b/test_regress/t/t_constraint_countbits_unsup.out new file mode 100644 index 000000000..bdba624a0 --- /dev/null +++ b/test_regress/t/t_constraint_countbits_unsup.out @@ -0,0 +1,5 @@ +%Error-UNSUPPORTED: t/t_constraint_countbits_unsup.v:12:20: Unsupported: non-constant control in $countbits inside constraint + 12 | constraint cons {$countbits(value, ctrl) == 3;} + | ^~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_constraint_mode_unsup.py b/test_regress/t/t_constraint_countbits_unsup.py similarity index 53% rename from test_regress/t/t_constraint_mode_unsup.py rename to test_regress/t/t_constraint_countbits_unsup.py index 6585af685..b7449248c 100755 --- a/test_regress/t/t_constraint_mode_unsup.py +++ b/test_regress/t/t_constraint_countbits_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_countbits_unsup.v b/test_regress/t/t_constraint_countbits_unsup.v new file mode 100644 index 000000000..0f6211a02 --- /dev/null +++ b/test_regress/t/t_constraint_countbits_unsup.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// Test: non-constant control in $countbits inside constraint (unsupported) + +class Packet; + rand bit [7:0] value; + bit ctrl; + constraint cons {$countbits(value, ctrl) == 3;} +endclass + +module t; + Packet p; + + initial begin + p = new; + void'(p.randomize()); + end +endmodule diff --git a/test_regress/t/t_constraint_countones.py b/test_regress/t/t_constraint_countones.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_countones.py +++ b/test_regress/t/t_constraint_countones.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_countones.v b/test_regress/t/t_constraint_countones.v index 979f873ea..5ddce3e57 100644 --- a/test_regress/t/t_constraint_countones.v +++ b/test_regress/t/t_constraint_countones.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ diff --git a/test_regress/t/t_constraint_dist.py b/test_regress/t/t_constraint_dist.py index dbae8a1dc..87b346af1 100755 --- a/test_regress/t/t_constraint_dist.py +++ b/test_regress/t/t_constraint_dist.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_dist.v b/test_regress/t/t_constraint_dist.v index b138a3e33..56cacf9c6 100644 --- a/test_regress/t/t_constraint_dist.v +++ b/test_regress/t/t_constraint_dist.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ @@ -39,7 +39,8 @@ endclass module t; initial begin - C c = new; + C c; + c = new; `check_rand(c, c.x, 5 <= c.x && c.x <= 6); `check_rand(c, c.y, 5 <= c.y && c.y <= 6); `check_rand(c, c.z, 3 <= c.z && c.z <= 5); diff --git a/test_regress/t/t_constraint_dist_randc_bad.py b/test_regress/t/t_constraint_dist_randc_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_constraint_dist_randc_bad.py +++ b/test_regress/t/t_constraint_dist_randc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_dist_randc_bad.v b/test_regress/t/t_constraint_dist_randc_bad.v index f363b3aa2..9b1e13d7f 100644 --- a/test_regress/t/t_constraint_dist_randc_bad.v +++ b/test_regress/t/t_constraint_dist_randc_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls1; diff --git a/test_regress/t/t_constraint_dyn_array_reduction.py b/test_regress/t/t_constraint_dyn_array_reduction.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_dyn_array_reduction.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_dyn_array_reduction.v b/test_regress/t/t_constraint_dyn_array_reduction.v new file mode 100644 index 000000000..7c74a4e78 --- /dev/null +++ b/test_regress/t/t_constraint_dyn_array_reduction.v @@ -0,0 +1,114 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +// Test dynamic array reduction methods (xor, sum, and, or, product) +// without 'with' clause in constraints. +// Each method is tested in a separate class to avoid conflicting constraints. + +module t; + + class XorTest; + rand bit [7:0] data[]; + rand bit [7:0] result; + function new(); + data = new[4]; + endfunction + constraint c_size {data.size() == 4;} + constraint c_xor {result == data.xor();} + endclass + + class SumTest; + rand bit [7:0] data[]; + rand bit [7:0] result; + function new(); + data = new[4]; + endfunction + constraint c_size {data.size() == 4;} + constraint c_sum {result == data.sum();} + endclass + + class AndTest; + rand bit [7:0] data[]; + rand bit [7:0] result; + function new(); + data = new[4]; + endfunction + constraint c_size {data.size() == 4;} + constraint c_and {result == data.and();} + endclass + + class OrTest; + rand bit [7:0] data[]; + rand bit [7:0] result; + function new(); + data = new[4]; + endfunction + constraint c_size {data.size() == 4;} + constraint c_or {result == data.or();} + endclass + + class ProductTest; + rand bit [7:0] data[]; + rand bit [7:0] result; + function new(); + data = new[4]; + endfunction + constraint c_size {data.size() == 4;} + constraint c_prod {result == data.product();} + endclass + + initial begin + static XorTest t_xor = new(); + static SumTest t_sum = new(); + static AndTest t_and = new(); + static OrTest t_or = new(); + static ProductTest t_prod = new(); + + repeat (10) begin + bit [7:0] exp; + int i; + + // Test xor + `checkd(t_xor.randomize(), 1) + exp = 0; + foreach (t_xor.data[i]) exp ^= t_xor.data[i]; + `checkh(t_xor.result, exp) + + // Test sum + `checkd(t_sum.randomize(), 1) + exp = 0; + foreach (t_sum.data[i]) exp += t_sum.data[i]; + `checkh(t_sum.result, exp) + + // Test and + `checkd(t_and.randomize(), 1) + exp = 8'hff; + foreach (t_and.data[i]) exp &= t_and.data[i]; + `checkh(t_and.result, exp) + + // Test or + `checkd(t_or.randomize(), 1) + exp = 0; + foreach (t_or.data[i]) exp |= t_or.data[i]; + `checkh(t_or.result, exp) + + // Test product + `checkd(t_prod.randomize(), 1) + exp = 8'd1; + foreach (t_prod.data[i]) exp *= t_prod.data[i]; + `checkh(t_prod.result, exp) + end + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_constraint_dyn_queue_basic.py b/test_regress/t/t_constraint_dyn_queue_basic.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_dyn_queue_basic.py +++ b/test_regress/t/t_constraint_dyn_queue_basic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_dyn_queue_basic.v b/test_regress/t/t_constraint_dyn_queue_basic.v old mode 100755 new mode 100644 index f115be10c..ee1a5cd1a --- a/test_regress/t/t_constraint_dyn_queue_basic.v +++ b/test_regress/t/t_constraint_dyn_queue_basic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_constraint_extern.py b/test_regress/t/t_constraint_extern.py index dbae8a1dc..87b346af1 100755 --- a/test_regress/t/t_constraint_extern.py +++ b/test_regress/t/t_constraint_extern.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_extern.v b/test_regress/t/t_constraint_extern.v index abb7ae2b1..8e8103b4a 100644 --- a/test_regress/t/t_constraint_extern.v +++ b/test_regress/t/t_constraint_extern.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Packet; diff --git a/test_regress/t/t_constraint_extern_bad.py b/test_regress/t/t_constraint_extern_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_constraint_extern_bad.py +++ b/test_regress/t/t_constraint_extern_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_extern_bad.v b/test_regress/t/t_constraint_extern_bad.v index dd187a08a..7157122a8 100644 --- a/test_regress/t/t_constraint_extern_bad.v +++ b/test_regress/t/t_constraint_extern_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Packet; diff --git a/test_regress/t/t_constraint_foreach.py b/test_regress/t/t_constraint_foreach.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_foreach.py +++ b/test_regress/t/t_constraint_foreach.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_foreach.v b/test_regress/t/t_constraint_foreach.v index a2c7f9f93..bc56a8488 100644 --- a/test_regress/t/t_constraint_foreach.v +++ b/test_regress/t/t_constraint_foreach.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ @@ -61,8 +61,8 @@ endclass module t; initial begin - C c = new; - D d = new; + automatic C c = new; + automatic D d = new; `check_rand(c, c.x, 4 < c.x && c.x < 7); `check_rand(d, d.posit, (d.posit ? 4 : -3) < d.x && d.x < (d.posit ? 7 : 0)); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_constraint_foreach_classref.py b/test_regress/t/t_constraint_foreach_classref.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_foreach_classref.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_foreach_classref.v b/test_regress/t/t_constraint_foreach_classref.v new file mode 100644 index 000000000..797a1a1a7 --- /dev/null +++ b/test_regress/t/t_constraint_foreach_classref.v @@ -0,0 +1,110 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH. +// SPDX-License-Identifier: CC0-1.0 + +// Test: Inline foreach constraints on dynamic arrays and queues of class objects + +class Inner; + rand bit [7:0] val; + rand bit [3:0] tag; + + function new(); + val = 0; + tag = 0; + endfunction +endclass + +class OuterDyn; + rand Inner items[]; + + function new(int size = 3); + items = new[size]; + foreach (items[i]) items[i] = new(); + endfunction +endclass + +class OuterQueue; + rand Inner items[$]; + + function new(int size = 3); + Inner tmp; + for (int i = 0; i < size; i++) begin + tmp = new(); + items.push_back(tmp); + end + endfunction +endclass + +module t; + OuterDyn od; + OuterQueue oq; + + initial begin + // === Test 1: Dynamic array with inline foreach constraint === + od = new(3); + + if (od.randomize() with { + foreach (items[i]) { + items[i].val > 10; + items[i].val < 200; + items[i].tag > 0; + } + } == 0) begin + $display("FAIL: dyn randomize() returned 0"); + $stop; + end + + foreach (od.items[i]) begin + if (!(od.items[i].val > 10 && od.items[i].val < 200)) begin + $display("FAIL: dyn items[%0d].val=%0d out of range", i, od.items[i].val); + $stop; + end + if (od.items[i].tag == 0) begin + $display("FAIL: dyn items[%0d].tag=%0d should be > 0", i, od.items[i].tag); + $stop; + end + end + + // === Test 2: Empty dynamic array (should succeed trivially) === + od = new(0); + + if (od.randomize() with { + foreach (items[i]) { + items[i].val > 10; + } + } == 0) begin + $display("FAIL: empty dyn randomize() returned 0"); + $stop; + end + + // === Test 3: Queue with inline foreach constraint === + oq = new(3); + + if (oq.randomize() with { + foreach (items[i]) { + items[i].val > 50; + items[i].val < 150; + items[i].tag > 0; + } + } == 0) begin + $display("FAIL: queue randomize() returned 0"); + $stop; + end + + foreach (oq.items[i]) begin + if (!(oq.items[i].val > 50 && oq.items[i].val < 150)) begin + $display("FAIL: queue items[%0d].val=%0d out of range", i, oq.items[i].val); + $stop; + end + if (oq.items[i].tag == 0) begin + $display("FAIL: queue items[%0d].tag=%0d should be > 0", i, oq.items[i].tag); + $stop; + end + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_func_call.py b/test_regress/t/t_constraint_func_call.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_func_call.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_func_call.v b/test_regress/t/t_constraint_func_call.v new file mode 100644 index 000000000..d5b5a75dd --- /dev/null +++ b/test_regress/t/t_constraint_func_call.v @@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); +// verilog_format: on + +class FuncConstraintTest; + rand bit [7:0] value; + rand bit [7:0] mask; + + function bit [7:0] get_min_value(bit [7:0] m); + return m & 8'hF0; + endfunction + + function bit [7:0] get_max_value(bit [7:0] m); + return m | 8'h0F; + endfunction + + constraint func_con { + mask inside {[8'h10 : 8'hF0]}; + value >= get_min_value(mask); + value <= get_max_value(mask); + } + + function new(); + endfunction +endclass + +module t; + FuncConstraintTest fct; + int rand_ok; + bit [7:0] min_val; + bit [7:0] max_val; + + initial begin + fct = new(); + + repeat (10) begin + rand_ok = fct.randomize(); + `checkd(rand_ok, 1) + + `check_range(fct.mask, 8'h10, 8'hF0) + + min_val = fct.get_min_value(fct.mask); + max_val = fct.get_max_value(fct.mask); + `check_range(fct.value, min_val, max_val) + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_func_call_unsup.out b/test_regress/t/t_constraint_func_call_unsup.out new file mode 100644 index 000000000..fd5d905e3 --- /dev/null +++ b/test_regress/t/t_constraint_func_call_unsup.out @@ -0,0 +1,6 @@ +%Warning-CONSTRAINTIGN: t/t_constraint_func_call_unsup.v:16:22: Unsupported: complex function in constraint, treating as state + 16 | constraint c {x <= complex_func(y);} + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest + ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_constraint_func_call_unsup.py b/test_regress/t/t_constraint_func_call_unsup.py new file mode 100755 index 000000000..18ef27714 --- /dev/null +++ b/test_regress/t/t_constraint_func_call_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_func_call_unsup.v b/test_regress/t/t_constraint_func_call_unsup.v new file mode 100644 index 000000000..e640f56c9 --- /dev/null +++ b/test_regress/t/t_constraint_func_call_unsup.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +class Cls; + rand bit [7:0] x; + rand bit [7:0] y; + + function bit [7:0] complex_func(bit [7:0] m); + if (m > 128) return m; + else return m + 1; + endfunction + + constraint c {x <= complex_func(y);} +endclass + +module t; + Cls obj; + + initial begin + obj = new; + void'(obj.randomize()); + end +endmodule diff --git a/test_regress/t/t_constraint_global_arr_unsup.py b/test_regress/t/t_constraint_global_arr_unsup.py index e30916148..4cebd5d8e 100755 --- a/test_regress/t/t_constraint_global_arr_unsup.py +++ b/test_regress/t/t_constraint_global_arr_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_global_arr_unsup.v b/test_regress/t/t_constraint_global_arr_unsup.v old mode 100755 new mode 100644 index 8cf37ffb9..268e3ca0f --- a/test_regress/t/t_constraint_global_arr_unsup.v +++ b/test_regress/t/t_constraint_global_arr_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off WIDTHTRUNC */ @@ -56,7 +56,7 @@ endclass module t_constraint_global_arr_unsup; initial begin - Outer o = new; + automatic Outer o = new; if (o.randomize()) begin $display("Case 1 - Simple: mid.obj.x = %0d (expected 100)", o.m_mid.m_obj.m_x); $display("Case 1 - Simple: mid.obj.y = %0d (expected 101)", o.m_mid.m_obj.m_y); diff --git a/test_regress/t/t_constraint_global_nested.py b/test_regress/t/t_constraint_global_nested.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_constraint_global_nested.py +++ b/test_regress/t/t_constraint_global_nested.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_global_nested.v b/test_regress/t/t_constraint_global_nested.v old mode 100755 new mode 100644 index ee5d46fc3..0d9880ea0 --- a/test_regress/t/t_constraint_global_nested.v +++ b/test_regress/t/t_constraint_global_nested.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Test for unsupported multiple global constraints -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_constraint_global_nested_member.py b/test_regress/t/t_constraint_global_nested_member.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_constraint_global_nested_member.py +++ b/test_regress/t/t_constraint_global_nested_member.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_global_nested_member.v b/test_regress/t/t_constraint_global_nested_member.v old mode 100755 new mode 100644 index a2305e041..adce89ea7 --- a/test_regress/t/t_constraint_global_nested_member.v +++ b/test_regress/t/t_constraint_global_nested_member.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_constraint_global_nested_randmode.py b/test_regress/t/t_constraint_global_nested_randmode.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_global_nested_randmode.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_global_nested_randmode.v b/test_regress/t/t_constraint_global_nested_randmode.v new file mode 100644 index 000000000..91fe31f05 --- /dev/null +++ b/test_regress/t/t_constraint_global_nested_randmode.v @@ -0,0 +1,109 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// Test: rand_mode on nested object's variable should not cause Z3 solver error. +// Previously, the generated SMT constraint used "#x0" instead of the variable +// name for nested rand variables when rand_mode was involved, causing a width +// mismatch in the constraint solver. + +class InnerClass; + rand bit [7:0] inner_val1; + rand bit [7:0] inner_val2; + + constraint inner_con { + inner_val1 inside {[8'd10 : 8'd50]}; + inner_val2 inside {[8'd100 : 8'd200]}; + } + + function new(); + inner_val1 = 0; + inner_val2 = 0; + endfunction +endclass + +class OuterClass; + rand InnerClass nested_obj; + rand bit [7:0] outer_val; + + constraint outer_con {outer_val inside {[8'd1 : 8'd20]};} + + function new(); + nested_obj = new(); + outer_val = 0; + endfunction +endclass + +module t_constraint_global_nested_randmode; + OuterClass obj; + int rand_ok; + int change_count; + bit [7:0] prev_val; + + initial begin + obj = new(); + + // Test 1: Normal randomization of nested object with constraints + rand_ok = obj.randomize(); + if (rand_ok == 0) $stop; + if (obj.nested_obj.inner_val1 < 8'd10 || obj.nested_obj.inner_val1 > 8'd50) $stop; + if (obj.nested_obj.inner_val2 < 8'd100 || obj.nested_obj.inner_val2 > 8'd200) $stop; + if (obj.outer_val < 8'd1 || obj.outer_val > 8'd20) $stop; + + // Test 2: Multiple randomizations with constraint checking + change_count = 0; + prev_val = obj.nested_obj.inner_val1; + repeat (10) begin + rand_ok = obj.randomize(); + if (rand_ok == 0) $stop; + if (obj.nested_obj.inner_val1 < 8'd10 || obj.nested_obj.inner_val1 > 8'd50) $stop; + if (obj.nested_obj.inner_val2 < 8'd100 || obj.nested_obj.inner_val2 > 8'd200) $stop; + if (obj.outer_val < 8'd1 || obj.outer_val > 8'd20) $stop; + if (obj.nested_obj.inner_val1 != prev_val) change_count++; + prev_val = obj.nested_obj.inner_val1; + end + if (change_count == 0) $stop; + + // Test 3: rand_mode(0) on nested var - must not crash solver + void'(obj.nested_obj.inner_val1.rand_mode(0)); + if (obj.nested_obj.inner_val1.rand_mode() != 0) $stop; + // Calling randomize must not cause a solver crash + rand_ok = obj.randomize(); + // (randomize may return 0 due to constraint interaction - separate issue) + + // Test 4: Re-enable rand_mode and verify randomization resumes + void'(obj.nested_obj.inner_val1.rand_mode(1)); + if (obj.nested_obj.inner_val1.rand_mode() != 1) $stop; + change_count = 0; + prev_val = obj.nested_obj.inner_val1; + repeat (10) begin + rand_ok = obj.randomize(); + if (rand_ok == 0) $stop; + if (obj.nested_obj.inner_val1 != prev_val) change_count++; + prev_val = obj.nested_obj.inner_val1; + end + if (change_count == 0) $stop; + + // Test 5: rand_mode(0) on entire nested object - must not crash solver + void'(obj.nested_obj.rand_mode(0)); + rand_ok = obj.randomize(); + // (randomize may return 0 due to constraint interaction - separate issue) + + // Test 6: Re-enable nested object and verify randomization resumes + void'(obj.nested_obj.rand_mode(1)); + change_count = 0; + prev_val = obj.nested_obj.inner_val1; + repeat (10) begin + rand_ok = obj.randomize(); + if (rand_ok == 0) $stop; + if (obj.nested_obj.inner_val1 != prev_val) change_count++; + prev_val = obj.nested_obj.inner_val1; + end + if (change_count == 0) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_global_randMode.py b/test_regress/t/t_constraint_global_randMode.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_constraint_global_randMode.py +++ b/test_regress/t/t_constraint_global_randMode.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_global_randMode.v b/test_regress/t/t_constraint_global_randMode.v old mode 100755 new mode 100644 index 19920ce37..6322674c4 --- a/test_regress/t/t_constraint_global_randMode.v +++ b/test_regress/t/t_constraint_global_randMode.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 class RandomValue; diff --git a/test_regress/t/t_constraint_global_random.py b/test_regress/t/t_constraint_global_random.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_constraint_global_random.py +++ b/test_regress/t/t_constraint_global_random.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_global_random.v b/test_regress/t/t_constraint_global_random.v old mode 100755 new mode 100644 index e0dec8f4c..e92a0f9fd --- a/test_regress/t/t_constraint_global_random.v +++ b/test_regress/t/t_constraint_global_random.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 class Inner; diff --git a/test_regress/t/t_constraint_global_random_simple.py b/test_regress/t/t_constraint_global_random_simple.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_constraint_global_random_simple.py +++ b/test_regress/t/t_constraint_global_random_simple.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_global_random_simple.v b/test_regress/t/t_constraint_global_random_simple.v index 21340ec46..4d79b7fcf 100644 --- a/test_regress/t/t_constraint_global_random_simple.v +++ b/test_regress/t/t_constraint_global_random_simple.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 // Simple test for global constraints with 2-level nesting: Top -> Mid -> Inner diff --git a/test_regress/t/t_constraint_inheritance.py b/test_regress/t/t_constraint_inheritance.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_inheritance.py +++ b/test_regress/t/t_constraint_inheritance.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_inheritance.v b/test_regress/t/t_constraint_inheritance.v index 081d1cb0a..1759d8797 100644 --- a/test_regress/t/t_constraint_inheritance.v +++ b/test_regress/t/t_constraint_inheritance.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ @@ -47,11 +47,11 @@ endclass module t; initial begin - B b = new; - C c = new; - D d = new; - E e = new; - A a = b; + automatic B b = new; + automatic C c = new; + automatic D d = new; + automatic E e = new; + automatic A a = b; `check_rand(a, b.x, b.x > 0); `check_rand(c, c.x, c.x > 0); `check_rand(c, c.y, c.x > 0); diff --git a/test_regress/t/t_constraint_inheritance_with.py b/test_regress/t/t_constraint_inheritance_with.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_inheritance_with.py +++ b/test_regress/t/t_constraint_inheritance_with.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_inheritance_with.v b/test_regress/t/t_constraint_inheritance_with.v index b5e949dd6..23d23dc3d 100644 --- a/test_regress/t/t_constraint_inheritance_with.v +++ b/test_regress/t/t_constraint_inheritance_with.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, constr, cond) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ if (!bit'(cl.randomize() with { constr; })) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ @@ -47,11 +47,11 @@ endclass module t; initial begin - B b = new; - C c = new; - D d = new; - E e = new; - A a = b; + automatic B b = new; + automatic C c = new; + automatic D d = new; + automatic E e = new; + automatic A a = b; `check_rand(a, a.x, x < 10, a.x > 0 && a.x < 10); `check_rand(c, c.x, x < 100, c.x > 0 && c.x < 100); `check_rand(c, c.y, x == 5, c.x == 5); diff --git a/test_regress/t/t_constraint_json_only.out b/test_regress/t/t_constraint_json_only.out index cc4efdef4..96e145376 100644 --- a/test_regress/t/t_constraint_json_only.out +++ b/test_regress/t/t_constraint_json_only.out @@ -1,11 +1,11 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED","stlFirstIterationp":"UNLINKED", "modulesp": [ - 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{"type":"UNPACKARRAYDTYPE","name":"","addr":"(Y)","loc":"d,15:18,15:19","dtypep":"(Y)","isCompound":false,"declRange":"[0:1]","generic":false,"signed":true,"refDTypep":"(Q)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Y)","loc":"d,15:18,15:19","dtypep":"(Y)","declRange":"[0:1]","signed":true,"refDTypep":"(Q)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(PB)","loc":"d,15:18,15:19","ascending":true,"fromBracket":true, + {"type":"RANGE","name":"","addr":"(SB)","loc":"d,15:18,15:19","ascending":true,"fromBracket":true, "leftp": [ - {"type":"CONST","name":"32'h0","addr":"(QB)","loc":"d,15:19,15:20","dtypep":"(OB)"} + {"type":"CONST","name":"32'h0","addr":"(TB)","loc":"d,15:19,15:20","dtypep":"(RB)"} ], "rightp": [ - {"type":"CONST","name":"32'h1","addr":"(RB)","loc":"d,15:19,15:20","dtypep":"(OB)"} + {"type":"CONST","name":"32'h1","addr":"(UB)","loc":"d,15:19,15:20","dtypep":"(RB)"} ]} ]}, - {"type":"VOIDDTYPE","name":"","addr":"(LB)","loc":"d,7:1,7:6","dtypep":"(LB)","generic":false}, - {"type":"CLASSREFDTYPE","name":"Packet","addr":"(H)","loc":"d,69:4,69:10","dtypep":"(H)","generic":false,"classp":"(O)","classOrPackagep":"(O)","paramsp": []}, - {"type":"BASICDTYPE","name":"VlRandomizer","addr":"(NB)","loc":"d,7:1,7:6","dtypep":"(NB)","keyword":"VlRandomizer","generic":true,"rangep": []} + {"type":"VOIDDTYPE","name":"","addr":"(OB)","loc":"d,7:1,7:6","dtypep":"(OB)"}, + {"type":"CLASSREFDTYPE","name":"Packet","addr":"(H)","loc":"d,69:4,69:10","dtypep":"(H)","classp":"(O)","classOrPackagep":"(O)","paramsp": []}, + {"type":"BASICDTYPE","name":"VlRandomizer","addr":"(QB)","loc":"d,7:1,7:6","dtypep":"(QB)","keyword":"VlRandomizer","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(SB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(VB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ - {"type":"SCOPE","name":"@CONST-POOL@","addr":"(TB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(SB)","varsp": [],"blocksp": [],"inlinesp": []} + {"type":"SCOPE","name":"@CONST-POOL@","addr":"(WB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(VB)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} diff --git a/test_regress/t/t_constraint_json_only.py b/test_regress/t/t_constraint_json_only.py index 66928c7bf..6e5d7dcea 100755 --- a/test_regress/t/t_constraint_json_only.py +++ b/test_regress/t/t_constraint_json_only.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_json_only.v b/test_regress/t/t_constraint_json_only.v index c455e919d..93bb4ca33 100644 --- a/test_regress/t/t_constraint_json_only.v +++ b/test_regress/t/t_constraint_json_only.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Packet; diff --git a/test_regress/t/t_constraint_method_bad.py b/test_regress/t/t_constraint_method_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_constraint_method_bad.py +++ b/test_regress/t/t_constraint_method_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_method_bad.v b/test_regress/t/t_constraint_method_bad.v index ee215fbfd..af2252995 100644 --- a/test_regress/t/t_constraint_method_bad.v +++ b/test_regress/t/t_constraint_method_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Packet; diff --git a/test_regress/t/t_constraint_mode.py b/test_regress/t/t_constraint_mode.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_mode.py +++ b/test_regress/t/t_constraint_mode.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_mode.v b/test_regress/t/t_constraint_mode.v index de709afc0..4ea067f32 100644 --- a/test_regress/t/t_constraint_mode.v +++ b/test_regress/t/t_constraint_mode.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -62,10 +62,10 @@ endclass module t; initial begin - logic[1:0] ok = 0; - int res; - Qux qux = new; - Bar bar = qux; + automatic logic[1:0] ok = 0; + automatic int res; + automatic Qux qux = new; + automatic Bar bar = qux; qux.test; diff --git a/test_regress/t/t_constraint_mode_bad.py b/test_regress/t/t_constraint_mode_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_constraint_mode_bad.py +++ b/test_regress/t/t_constraint_mode_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_mode_bad.v b/test_regress/t/t_constraint_mode_bad.v index 408590ae9..7aa527fe8 100644 --- a/test_regress/t/t_constraint_mode_bad.v +++ b/test_regress/t/t_constraint_mode_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Packet; diff --git a/test_regress/t/t_constraint_mode_ctor.py b/test_regress/t/t_constraint_mode_ctor.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_mode_ctor.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_mode_ctor.v b/test_regress/t/t_constraint_mode_ctor.v new file mode 100644 index 000000000..460fd14fb --- /dev/null +++ b/test_regress/t/t_constraint_mode_ctor.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// Test constraint_mode() called inside class constructor (function new) + +class ConstraintModeInCtor; + rand bit [7:0] value; + + constraint low_range_c {value < 50;} + constraint high_range_c { + value >= 50; + value < 200; + } + + function new; + // Disable high_range_c in constructor - only low_range_c should be active + high_range_c.constraint_mode(0); + endfunction +endclass + +module t; + initial begin + automatic ConstraintModeInCtor obj = new; + automatic int i; + + // Test 1: constraint_mode(0) in constructor should disable constraint + for (i = 0; i < 20; i++) begin + void'(obj.randomize()); + if (obj.value >= 50) $stop; + end + + // Test 2: Query constraint_mode state set in constructor + if (obj.low_range_c.constraint_mode != 1) $stop; + if (obj.high_range_c.constraint_mode != 0) $stop; + + // Test 3: Switch constraints at runtime + obj.low_range_c.constraint_mode(0); + obj.high_range_c.constraint_mode(1); + for (i = 0; i < 20; i++) begin + void'(obj.randomize()); + if (obj.value < 50 || obj.value >= 200) $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_mode_static.py b/test_regress/t/t_constraint_mode_static.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_mode_static.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_mode_static.v b/test_regress/t/t_constraint_mode_static.v new file mode 100644 index 000000000..1acb7506f --- /dev/null +++ b/test_regress/t/t_constraint_mode_static.v @@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH. +// SPDX-License-Identifier: CC0-1.0 + +// Test static constraint_mode() support per IEEE 1800-2017 Section 18.4, 18.8 +// Static constraint mode should be shared across all instances. + +class StaticConstraintTest; + rand bit [7:0] value; + + // Static constraint - shared across all instances + static constraint static_con {value inside {[10 : 15]};} + + // Non-static constraint for comparison + constraint instance_con {value > 5;} +endclass + +module t; + StaticConstraintTest obj1, obj2; + + initial begin + obj1 = new(); + obj2 = new(); + + // Test 1: Verify static constraint_mode getter works + if (obj1.static_con.constraint_mode() != 1) $stop; + if (obj2.static_con.constraint_mode() != 1) $stop; + + // Test 2: Disable static constraint on one instance + obj1.static_con.constraint_mode(0); + + // Verify the state is shared across all instances + if (obj1.static_con.constraint_mode() != 0) $stop; + if (obj2.static_con.constraint_mode() != 0) $stop; + + // Test 3: Re-enable static constraint via different instance + obj2.static_con.constraint_mode(1); + + // Verify state is updated for all instances + if (obj1.static_con.constraint_mode() != 1) $stop; + if (obj2.static_con.constraint_mode() != 1) $stop; + + // Test 4: Verify randomization respects constraint mode when enabled + obj1.static_con.constraint_mode(1); + obj1.instance_con.constraint_mode(1); + for (int i = 0; i < 10; i++) begin + void'(obj1.randomize()); + if (!(obj1.value inside {[10 : 15]})) $stop; + if (!(obj1.value > 5)) $stop; + end + + // Test 5: Disable static constraint and verify randomization changes + obj1.static_con.constraint_mode(0); + // With static_con disabled, value only needs to be > 5 + for (int i = 0; i < 10; i++) begin + obj1.value = 1; // Reset to low value + void'(obj1.randomize()); + if (!(obj1.value > 5)) $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_mode_unsup.out b/test_regress/t/t_constraint_mode_unsup.out deleted file mode 100644 index 9a82c86f1..000000000 --- a/test_regress/t/t_constraint_mode_unsup.out +++ /dev/null @@ -1,14 +0,0 @@ -%Error-UNSUPPORTED: t/t_constraint_mode_unsup.v:17:55: Unsupported: 'constraint_mode()' on static constraint - : ... note: In instance 't' - 17 | $display("p.cons.constraint_mode()=%0d", p.cons.constraint_mode()); - | ^~~~~~~~~~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_constraint_mode_unsup.v:18:14: Unsupported: 'constraint_mode()' on static constraint - : ... note: In instance 't' - 18 | p.cons.constraint_mode(0); - | ^~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_constraint_mode_unsup.v:19:9: Unsupported: 'constraint_mode()' on static constraint: 'cons' - : ... note: In instance 't' - 19 | p.constraint_mode(0); - | ^~~~~~~~~~~~~~~ -%Error: Exiting due to diff --git a/test_regress/t/t_constraint_mode_unsup.v b/test_regress/t/t_constraint_mode_unsup.v deleted file mode 100644 index fceb38a44..000000000 --- a/test_regress/t/t_constraint_mode_unsup.v +++ /dev/null @@ -1,21 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. -// SPDX-License-Identifier: CC0-1.0 - -class Packet; - int m_one; - static constraint cons { m_one > 0 && m_one < 2; } -endclass - -module t; - Packet p; - - initial begin - p = new; - $display("p.cons.constraint_mode()=%0d", p.cons.constraint_mode()); - p.cons.constraint_mode(0); - p.constraint_mode(0); - end -endmodule diff --git a/test_regress/t/t_constraint_nested_class.py b/test_regress/t/t_constraint_nested_class.py new file mode 100755 index 000000000..87b346af1 --- /dev/null +++ b/test_regress/t/t_constraint_nested_class.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile(verilator_flags2=['-Wno-CONSTRAINTIGN']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_nested_class.v b/test_regress/t/t_constraint_nested_class.v new file mode 100644 index 000000000..5277010bb --- /dev/null +++ b/test_regress/t/t_constraint_nested_class.v @@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +parameter int LEN = 32; + +class A; + rand int x; + rand int array[5]; + constraint a_c { + x <= LEN; + x >= LEN; + foreach (array[i]) {array[i] == array[i-1];} + } +endclass + +class B; + rand A a; +endclass + +module t; + B b; + initial begin + b = new; + b.a = new; + if (b.randomize() == 0) $stop; + if (b.a.x != LEN) $stop; + for (int i = 0; i < 4; i++) begin + if (b.a.array[i] != b.a.array[i+1]) $stop; + end + $write("*-* All finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_non_const_exp_pow_unsup.out b/test_regress/t/t_constraint_non_const_exp_pow_unsup.out new file mode 100644 index 000000000..9589c77ad --- /dev/null +++ b/test_regress/t/t_constraint_non_const_exp_pow_unsup.out @@ -0,0 +1,6 @@ +%Warning-CONSTRAINTIGN: t/t_constraint_non_const_exp_pow_unsup.v:11:25: Unsupported: Power (**) expression with non-constant exponent in constraint + 11 | constraint c_power {x ** y < 10000;} + | ^~ + ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest + ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_static_in_loop_unsup.py b/test_regress/t/t_constraint_non_const_exp_pow_unsup.py similarity index 53% rename from test_regress/t/t_static_in_loop_unsup.py rename to test_regress/t/t_constraint_non_const_exp_pow_unsup.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_static_in_loop_unsup.py +++ b/test_regress/t/t_constraint_non_const_exp_pow_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_non_const_exp_pow_unsup.v b/test_regress/t/t_constraint_non_const_exp_pow_unsup.v new file mode 100644 index 000000000..65ad8be4b --- /dev/null +++ b/test_regress/t/t_constraint_non_const_exp_pow_unsup.v @@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +class Packet; + rand int x; + rand int y; + + constraint c_power {x ** y < 10000;} +endclass + +module t; + + Packet p; + + initial begin + p = new; + void'(p.randomize()); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_nosolver_bad.py b/test_regress/t/t_constraint_nosolver_bad.py index 69c260d6a..775575309 100755 --- a/test_regress/t/t_constraint_nosolver_bad.py +++ b/test_regress/t/t_constraint_nosolver_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_operators.py b/test_regress/t/t_constraint_operators.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_operators.py +++ b/test_regress/t/t_constraint_operators.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_operators.v b/test_regress/t/t_constraint_operators.v index 3a4134f9d..b9d1b1ba0 100644 --- a/test_regress/t/t_constraint_operators.v +++ b/test_regress/t/t_constraint_operators.v @@ -1,14 +1,21 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Packet; rand int x; + rand int y; + rand int z; + rand int w; + rand int v; + rand int u; rand bit [31:0] b; rand bit [31:0] c; rand bit [31:0] d; + rand bit [31:0] e; + rand bit [31:0] f; rand bit tiny; rand bit zero; rand bit one; @@ -22,6 +29,24 @@ class Packet; constraint arith { x + x - x == x; } constraint divmod { int'((x % 5) / 2) != (b % 99) / 7; } constraint mul { x * 9 != b * 3; } + constraint mul_signed { + y * y == 4; + y > 0; + y < 4; + z * z == 4; + z < 0; + z > -4; + } + constraint c_power { e ** 32'h5 < 10000; } + constraint c_power_ss { w ** 5 < 10000; } + constraint c_power_us { f ** 5 < 10000; } + constraint c_power_su { v ** 32'h5 < 10000; } + constraint c_power_many { u ** 2 ** 3 < 1000; u > 2; u < 10; } + // check for negative values in constant + constraint c_power_neg_exp { v ** 4'shf == 0; } + constraint c_power_u_neg_exp { f ** 4'shf == 0; } + constraint c_power_zero_exp { v ** 0 == 1; } + constraint c_power_u_zero_exp { f ** 0 == 1; } constraint impl { tiny == 1 -> x != 10; } constraint concat { {c, b} != 'h1111; } constraint unary { !(-~c == 'h22); } @@ -79,6 +104,13 @@ module t; if (v != 1) $stop; if ((p.x % 5) / 2 == (p.b % 99) / 7) $stop; if (p.x * 9 == p.b * 3) $stop; + if (p.y != 2) $stop; + if (p.z != -2) $stop; + if (p.w ** 5 >= 10000) $stop; + if (p.e ** 32'h5 >= 10000) $stop; + if (p.v ** 32'h5 >= 10000) $stop; + if (p.f ** 5 >= 10000) $stop; + if (p.u != 3) $stop; if (p.tiny && p.x == 10) $stop; if ({p.c, p.b} == 'h1111) $stop; if (-~p.c == 'h22) $stop; diff --git a/test_regress/t/t_constraint_pure.py b/test_regress/t/t_constraint_pure.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_pure.py +++ b/test_regress/t/t_constraint_pure.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_pure.v b/test_regress/t/t_constraint_pure.v index c3fc3f64a..17e5d7bd5 100644 --- a/test_regress/t/t_constraint_pure.v +++ b/test_regress/t/t_constraint_pure.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 virtual class Base; @@ -19,7 +19,7 @@ endclass module t; initial begin - Cls c = new; + automatic Cls c = new; $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_constraint_pure_missing_bad.py b/test_regress/t/t_constraint_pure_missing_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_constraint_pure_missing_bad.py +++ b/test_regress/t/t_constraint_pure_missing_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_pure_missing_bad.v b/test_regress/t/t_constraint_pure_missing_bad.v index 9d81382d5..39af139bb 100644 --- a/test_regress/t/t_constraint_pure_missing_bad.v +++ b/test_regress/t/t_constraint_pure_missing_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 virtual class Base; diff --git a/test_regress/t/t_constraint_pure_nonabs_bad.py b/test_regress/t/t_constraint_pure_nonabs_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_constraint_pure_nonabs_bad.py +++ b/test_regress/t/t_constraint_pure_nonabs_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_pure_nonabs_bad.v b/test_regress/t/t_constraint_pure_nonabs_bad.v index 0ea5366d2..9f3343f12 100644 --- a/test_regress/t/t_constraint_pure_nonabs_bad.v +++ b/test_regress/t/t_constraint_pure_nonabs_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class NonAsbstract; diff --git a/test_regress/t/t_constraint_soft_randc_bad.py b/test_regress/t/t_constraint_soft_randc_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_constraint_soft_randc_bad.py +++ b/test_regress/t/t_constraint_soft_randc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_soft_randc_bad.v b/test_regress/t/t_constraint_soft_randc_bad.v index a4b950f8a..f9581baf9 100644 --- a/test_regress/t/t_constraint_soft_randc_bad.v +++ b/test_regress/t/t_constraint_soft_randc_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls1; diff --git a/test_regress/t/t_constraint_solve_before.py b/test_regress/t/t_constraint_solve_before.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_solve_before.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_solve_before.v b/test_regress/t/t_constraint_solve_before.v new file mode 100644 index 000000000..a415f7432 --- /dev/null +++ b/test_regress/t/t_constraint_solve_before.v @@ -0,0 +1,112 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); +// verilog_format: on + +// Test solve...before constraint (IEEE 1800-2017 18.5.11) +// Verifies phased solving: 'before' variables are determined first, +// then 'after' variables are solved with all constraints applied. + +/* verilator lint_off UNSIGNED */ + +module t; + + // Test 1: solve with conditional constraints + class Packet; + rand bit [2:0] mode; + rand bit [7:0] data; + + constraint c_order { + solve mode before data; + mode inside {[0:3]}; + if (mode == 0) data == 8'h00; + else if (mode == 1) data inside {[8'h01:8'h0f]}; + else data < 8'h80; + } + endclass + + // Test 2: basic solve before with range constraints + class Simple; + rand bit [3:0] x; + rand bit [3:0] y; + + constraint c { + solve x before y; + x inside {[1:5]}; + y > x; + y < 4'hf; + } + endclass + + // Test 3: multi-level solve before (a -> b -> c) + class MultiLevel; + rand bit [3:0] a; + rand bit [3:0] b; + rand bit [3:0] c; + + constraint c_order { + solve a before b; + solve b before c; + a inside {[1:3]}; + b > a; + b < 8; + c > b; + c < 4'hf; + } + endclass + + initial begin + Packet p; + Simple s; + MultiLevel m; + int ok; + + // Test 1: Packet with conditional constraints + p = new; + repeat (20) begin + `checkd(p.randomize(), 1) + `check_range(p.mode, 0, 3) + if (p.mode == 0) `checkd(p.data, 0) + if (p.mode == 1) begin + `check_range(p.data, 1, 15) + end + if (p.mode >= 2) begin + ok = (p.data < 8'h80) ? 1 : 0; + `checkd(ok, 1) + end + end + + // Test 2: Simple range constraints + s = new; + repeat (20) begin + `checkd(s.randomize(), 1) + `check_range(s.x, 1, 5) + ok = (s.y > s.x) ? 1 : 0; + `checkd(ok, 1) + ok = (s.y < 4'hf) ? 1 : 0; + `checkd(ok, 1) + end + + // Test 3: Multi-level chain + m = new; + repeat (20) begin + `checkd(m.randomize(), 1) + `check_range(m.a, 1, 3) + ok = (m.b > m.a && m.b < 8) ? 1 : 0; + `checkd(ok, 1) + ok = (m.c > m.b && m.c < 4'hf) ? 1 : 0; + `checkd(ok, 1) + end + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_constraint_solve_before_expr_unsup.out b/test_regress/t/t_constraint_solve_before_expr_unsup.out new file mode 100644 index 000000000..41d9d6a4b --- /dev/null +++ b/test_regress/t/t_constraint_solve_before_expr_unsup.out @@ -0,0 +1,7 @@ +%Warning-CONSTRAINTIGN: t/t_constraint_solve_before_expr_unsup.v:12:27: Unsupported: non-variable expression in solve...before + : ... note: In instance 't' + 12 | constraint c { solve arr[0] before y; } + | ^ + ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest + ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_constraint_solve_before_expr_unsup.py b/test_regress/t/t_constraint_solve_before_expr_unsup.py new file mode 100755 index 000000000..a00127d05 --- /dev/null +++ b/test_regress/t/t_constraint_solve_before_expr_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_solve_before_expr_unsup.v b/test_regress/t/t_constraint_solve_before_expr_unsup.v new file mode 100644 index 000000000..2bedabd54 --- /dev/null +++ b/test_regress/t/t_constraint_solve_before_expr_unsup.v @@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +class Cls; + rand int x; + rand int y; + rand int arr[4]; + + constraint c { solve arr[0] before y; } // BAD: non-variable expression +endclass + +module t; + // verilator lint_off IMPLICITSTATIC + initial begin + Cls c = new; + void'(c.randomize()); + end +endmodule diff --git a/test_regress/t/t_constraint_solve_before_unsup.out b/test_regress/t/t_constraint_solve_before_unsup.out new file mode 100644 index 000000000..90519d765 --- /dev/null +++ b/test_regress/t/t_constraint_solve_before_unsup.out @@ -0,0 +1,12 @@ +%Warning-CONSTRAINTIGN: t/t_constraint_solve_before_unsup.v:20:7: Ignoring unsupported: solve-before only supported as top-level constraint statement + 20 | solve x before data[i]; + | ^~~~~ + ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest + ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. +%Warning-CONSTRAINTIGN: t/t_constraint_solve_before_unsup.v:29:7: Ignoring unsupported: solve-before only supported as top-level constraint statement + 29 | solve x before cfg[i].w, cfg[i].r; + | ^~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_solve_before_unsup.v:30:7: Ignoring unsupported: solve-before only supported as top-level constraint statement + 30 | solve cfg[i].l before cfg[i].x; + | ^~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_constraint_solve_before_unsup.py b/test_regress/t/t_constraint_solve_before_unsup.py new file mode 100755 index 000000000..b7449248c --- /dev/null +++ b/test_regress/t/t_constraint_solve_before_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_solve_before_unsup.v b/test_regress/t/t_constraint_solve_before_unsup.v new file mode 100644 index 000000000..4d4d2bce7 --- /dev/null +++ b/test_regress/t/t_constraint_solve_before_unsup.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +typedef struct { + rand bit l; + rand bit x; + rand bit w; + rand bit r; +} reg_t; + +class Packet; + rand bit [7:0] data[5]; + rand bit x; + + constraint c_data { + foreach (data[i]) { + solve x before data[i]; + data[i] inside {8'h10, 8'h20, 8'h30, 8'h40, 8'h50}; + } + } + + rand reg_t cfg[]; + + constraint solves_only_c { + foreach (cfg[i]) { + solve x before cfg[i].w, cfg[i].r; + solve cfg[i].l before cfg[i].x; + } + } +endclass + +module t; + Packet p; + + initial begin + p = new; + void'(p.randomize()); + end +endmodule diff --git a/test_regress/t/t_constraint_state.py b/test_regress/t/t_constraint_state.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_state.py +++ b/test_regress/t/t_constraint_state.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_state.v b/test_regress/t/t_constraint_state.v index ee0a8f103..6a6af40ac 100644 --- a/test_regress/t/t_constraint_state.v +++ b/test_regress/t/t_constraint_state.v @@ -1,14 +1,14 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ diff --git a/test_regress/t/t_constraint_struct.py b/test_regress/t/t_constraint_struct.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_struct.py +++ b/test_regress/t/t_constraint_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_struct.v b/test_regress/t/t_constraint_struct.v old mode 100755 new mode 100644 index 4462017bb..49f921015 --- a/test_regress/t/t_constraint_struct.v +++ b/test_regress/t/t_constraint_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 typedef struct packed { diff --git a/test_regress/t/t_constraint_struct_complex.py b/test_regress/t/t_constraint_struct_complex.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_constraint_struct_complex.py +++ b/test_regress/t/t_constraint_struct_complex.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_struct_complex.v b/test_regress/t/t_constraint_struct_complex.v old mode 100755 new mode 100644 index 6ad6ba90e..a9a319f83 --- a/test_regress/t/t_constraint_struct_complex.v +++ b/test_regress/t/t_constraint_struct_complex.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_constraint_sysfunc.py b/test_regress/t/t_constraint_sysfunc.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_sysfunc.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_sysfunc.v b/test_regress/t/t_constraint_sysfunc.v new file mode 100644 index 000000000..4b458c18a --- /dev/null +++ b/test_regress/t/t_constraint_sysfunc.v @@ -0,0 +1,98 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// Test: System functions ($onehot, $onehot0, $countbits, $clog2) inside +// constraint blocks (IEEE 1800-2017 Section 18.5.12) + +class test_onehot; + rand bit [7:0] value; + constraint c_hot {$onehot(value);} +endclass + +class test_onehot0; + rand bit [7:0] value; + constraint c_hot0 {$onehot0(value);} +endclass + +class test_countbits_ones; + rand bit [7:0] value; + constraint c_bits {$countbits(value, '1) == 3;} +endclass + +class test_countbits_zeros; + rand bit [7:0] value; + constraint c_bits {$countbits(value, '0) == 6;} // 6 zeros = 2 ones +endclass + +class test_clog2; + rand bit [7:0] data_width; + rand bit [7:0] addr_bits; + constraint c_log {addr_bits == 8'($clog2(data_width));} + constraint c_nonzero {data_width > 0;} +endclass + +module t; + initial begin + automatic test_onehot oh = new; + automatic test_onehot0 oh0 = new; + automatic test_countbits_ones cb1 = new; + automatic test_countbits_zeros cb0 = new; + automatic test_clog2 cl = new; + automatic bit ok = 1'b1; + + // Test $onehot: exactly one bit set + repeat (20) begin + if (oh.randomize() == 0) $fatal(1, "$onehot randomize failed"); + if ($onehot(oh.value) !== 1'b1) begin + $display("FAIL: $onehot value=%08b, $onehot=%0b", oh.value, $onehot(oh.value)); + ok = 1'b0; + end + end + + // Test $onehot0: zero or one bit set + repeat (20) begin + if (oh0.randomize() == 0) $fatal(1, "$onehot0 randomize failed"); + if ($onehot0(oh0.value) !== 1'b1) begin + $display("FAIL: $onehot0 value=%08b, $onehot0=%0b", oh0.value, $onehot0(oh0.value)); + ok = 1'b0; + end + end + + // Test $countbits counting ones: exactly 3 ones + repeat (20) begin + if (cb1.randomize() == 0) $fatal(1, "$countbits('1) randomize failed"); + if ($countbits(cb1.value, '1) != 3) begin + $display("FAIL: $countbits('1) value=%08b, count=%0d", cb1.value, $countbits(cb1.value, + '1)); + ok = 1'b0; + end + end + + // Test $countbits counting zeros: exactly 6 zeros (= 2 ones) + repeat (20) begin + if (cb0.randomize() == 0) $fatal(1, "$countbits('0) randomize failed"); + if ($countbits(cb0.value, '0) != 6) begin + $display("FAIL: $countbits('0) value=%08b, zeros=%0d ones=%0d", cb0.value, + $countbits(cb0.value, '0), $countbits(cb0.value, '1)); + ok = 1'b0; + end + end + + // Test $clog2: addr_bits == $clog2(data_width) + repeat (20) begin + if (cl.randomize() == 0) $fatal(1, "$clog2 randomize failed"); + if (cl.addr_bits != 8'($clog2(cl.data_width))) begin + $display("FAIL: $clog2 data_width=%0d, addr_bits=%0d, expected=%0d", cl.data_width, + cl.addr_bits, $clog2(cl.data_width)); + ok = 1'b0; + end + end + + if (ok) $display("All tests passed"); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_unpacked_array.py b/test_regress/t/t_constraint_unpacked_array.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_constraint_unpacked_array.py +++ b/test_regress/t/t_constraint_unpacked_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_unpacked_array.v b/test_regress/t/t_constraint_unpacked_array.v old mode 100755 new mode 100644 index 1d7ecfbc6..9ee4ae6c8 --- a/test_regress/t/t_constraint_unpacked_array.v +++ b/test_regress/t/t_constraint_unpacked_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field) \ diff --git a/test_regress/t/t_constraint_unq_arr_derived.py b/test_regress/t/t_constraint_unq_arr_derived.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_unq_arr_derived.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_unq_arr_derived.v b/test_regress/t/t_constraint_unq_arr_derived.v new file mode 100644 index 000000000..b4fcd2a57 --- /dev/null +++ b/test_regress/t/t_constraint_unq_arr_derived.v @@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +typedef enum bit [4:0] { + ZERO = 5'b00000, + RA, SP, GP, TP, T0, T1, T2, S0, S1, A0, A1, A2, A3, A4, A5, A6, A7, + S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, T3, T4, T5, T6 +} EnumType; +// verilog_format: on + +class Base; + rand EnumType b_scratch_reg; + rand EnumType b_pmp_reg[2]; + rand EnumType b_sp; + rand EnumType b_tp; + + constraint b_example_constraint { + unique {b_pmp_reg}; + {b_pmp_reg[0] > 0}; + {b_pmp_reg[0] < 3}; + {b_pmp_reg[1] > 0}; + {b_pmp_reg[1] < 3}; + } +endclass + +class Foo extends Base; + rand EnumType scratch_reg; + rand EnumType pmp_reg[2]; + rand EnumType sp; + rand EnumType tp; + + constraint example_constraint { + unique {pmp_reg}; + {pmp_reg[0] > 0}; + {pmp_reg[0] < 3}; + {pmp_reg[1] > 0}; + {pmp_reg[1] < 3}; + } +endclass + +module t; + Foo foo; + initial begin + foo = new; + repeat (100) if (foo.randomize() != 1 || foo.pmp_reg[0] == foo.pmp_reg[1]) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.out b/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.out new file mode 100644 index 000000000..36fefb227 --- /dev/null +++ b/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.out @@ -0,0 +1,7 @@ +%Warning-CONSTRAINTIGN: t/t_constraint_unq_arr_derived_inline_unsup.v:35:11: Unsupported: Unique constraint in randomize() with {} + : ... note: In instance 't' + 35 | unique {foo.pmp_reg}; + | ^~~~~~ + ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest + ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.py b/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.py new file mode 100755 index 000000000..18ef27714 --- /dev/null +++ b/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.v b/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.v new file mode 100644 index 000000000..0c04d4105 --- /dev/null +++ b/test_regress/t/t_constraint_unq_arr_derived_inline_unsup.v @@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +typedef enum bit [4:0] { + ZERO = 5'b00000, + RA, SP, GP, TP, T0, T1, T2, S0, S1, A0, A1, A2, A3, A4, A5, A6, A7, + S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, T3, T4, T5, T6 +} EnumType; +// verilog_format: on + +class Base; + rand EnumType b_scratch_reg; + rand EnumType b_pmp_reg[2]; + rand EnumType b_sp; + rand EnumType b_tp; +endclass + +class Foo extends Base; + rand EnumType scratch_reg; + rand EnumType pmp_reg[2]; + rand EnumType sp; + rand EnumType tp; +endclass + +module t; + Foo foo; + initial begin + foo = new; + repeat (100) + if (foo.randomize() with { + unique {foo.pmp_reg}; + foo.pmp_reg[0] inside {1, 2}; + foo.pmp_reg[1] inside {1, 2}; + } != 1 || foo.pmp_reg[0] == foo.pmp_reg[1]) + $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_unsat.out b/test_regress/t/t_constraint_unsat.out new file mode 100644 index 000000000..3cc41487e --- /dev/null +++ b/test_regress/t/t_constraint_unsat.out @@ -0,0 +1,30 @@ + +=== Test 1: Valid constraints === + +=== Test 2: addr out of range === +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:16: Unsatisfied constraint: 'if (!randomize() with { addr == a; data == d; }) begin' +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:12: Unsatisfied constraint: 'constraint data_range { data > 10 && data < 200; }' +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:11: Unsatisfied constraint: 'constraint addr_range { addr < 127; }' +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:16: Unsatisfied constraint: 'if (!randomize() with { addr == a; data == d; }) begin' +Randomization failed. + +=== Test 3: data out of range (too small) === +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:12: Unsatisfied constraint: 'constraint data_range { data > 10 && data < 200; }' +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:16: Unsatisfied constraint: 'if (!randomize() with { addr == a; data == d; }) begin' +Randomization failed. + +=== Test 4: data out of range (too large) === +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:12: Unsatisfied constraint: 'constraint data_range { data > 10 && data < 200; }' +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:16: Unsatisfied constraint: 'if (!randomize() with { addr == a; data == d; }) begin' +Randomization failed. + +=== Test 5: Both constraints violated === +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:11: Unsatisfied constraint: 'constraint addr_range { addr < 127; }' +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:16: Unsatisfied constraint: 'if (!randomize() with { addr == a; data == d; }) begin' +Randomization failed. + +=== Test 6: Conflicting constraints (x > 100 && x < 50) === +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:26: Unsatisfied constraint: 'constraint c1 { x > 100; }' +%Warning-UNSATCONSTR: t/t_constraint_unsat.v:27: Unsatisfied constraint: 'constraint c2 { x < 50; }' +Expected failure: conflicting constraints detected +*-* All Finished *-* diff --git a/test_regress/t/t_constraint_unsat.py b/test_regress/t/t_constraint_unsat.py new file mode 100755 index 000000000..a3389e00d --- /dev/null +++ b/test_regress/t/t_constraint_unsat.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +# Test default behavior (warnings enabled) +# To disable warnings: use +verilator+wno+unsatconstr+1 +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_unsat.v b/test_regress/t/t_constraint_unsat.v new file mode 100644 index 000000000..c37e6637b --- /dev/null +++ b/test_regress/t/t_constraint_unsat.v @@ -0,0 +1,77 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +class Packet; + rand bit [7:0] addr; + rand bit [7:0] data; + + constraint addr_range { addr < 127; } + constraint data_range { data > 10 && data < 200; } + + function void check(bit [7:0] a, bit [7:0] d); + /* verilator lint_off WIDTHTRUNC */ + if (!randomize() with { addr == a; data == d; }) begin + /* verilator lint_on WIDTHTRUNC */ + $display("Randomization failed."); + end + endfunction +endclass + +class TestConflict; + rand bit [7:0] x; + + constraint c1 { x > 100; } + constraint c2 { x < 50; } + + function bit try_randomize(); + /* verilator lint_off WIDTHTRUNC */ + return randomize(); + /* verilator lint_on WIDTHTRUNC */ + endfunction +endclass + +module t_constraint_unsat; + initial begin + Packet pkt; + TestConflict tc; + + pkt = new; + + // Test 1: Valid randomization + $display("\n=== Test 1: Valid constraints ==="); + pkt.check(50, 100); + + // Test 2: addr out of range + $display("\n=== Test 2: addr out of range ==="); + pkt.check(128, 18); + + // Test 3: data out of range (too small) + $display("\n=== Test 3: data out of range (too small) ==="); + pkt.check(100, 5); + + // Test 4: data out of range (too large) + $display("\n=== Test 4: data out of range (too large) ==="); + pkt.check(100, 250); + + // Test 5: Both constraints violated + $display("\n=== Test 5: Both constraints violated ==="); + pkt.check(200, 5); + + // Test 6: Conflicting constraints + $display("\n=== Test 6: Conflicting constraints (x > 100 && x < 50) ==="); + tc = new; + if (!tc.try_randomize()) begin + $display("Expected failure: conflicting constraints detected"); + end + else begin + $display("ERROR: Should have failed with conflicting constraints"); + $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_unsat_nowarn.out b/test_regress/t/t_constraint_unsat_nowarn.out new file mode 100644 index 000000000..7889ade0a --- /dev/null +++ b/test_regress/t/t_constraint_unsat_nowarn.out @@ -0,0 +1,18 @@ + +=== Test 1: Valid constraints === + +=== Test 2: addr out of range === +Randomization failed. + +=== Test 3: data out of range (too small) === +Randomization failed. + +=== Test 4: data out of range (too large) === +Randomization failed. + +=== Test 5: Both constraints violated === +Randomization failed. + +=== Test 6: Conflicting constraints (x > 100 && x < 50) === +Expected failure: conflicting constraints detected +*-* All Finished *-* diff --git a/test_regress/t/t_constraint_unsat_nowarn.py b/test_regress/t/t_constraint_unsat_nowarn.py new file mode 100755 index 000000000..1cd3c2d7c --- /dev/null +++ b/test_regress/t/t_constraint_unsat_nowarn.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_constraint_unsat.v" + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +# Test with warnings disabled via +verilator+wno+unsatconstr+1 +test.execute(all_run_flags=['+verilator+wno+unsatconstr+1'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_unsat_protect_ids.out b/test_regress/t/t_constraint_unsat_protect_ids.out new file mode 100644 index 000000000..8677a573f --- /dev/null +++ b/test_regress/t/t_constraint_unsat_protect_ids.out @@ -0,0 +1,30 @@ + +=== Test 1: Valid constraints === + +=== Test 2: addr out of range === +%Warning-UNSATCONSTR: PSTByA:16: Unsatisfied constraint +%Warning-UNSATCONSTR: PSTByA:12: Unsatisfied constraint +%Warning-UNSATCONSTR: PSTByA:11: Unsatisfied constraint +%Warning-UNSATCONSTR: PSTByA:16: Unsatisfied constraint +Randomization failed. + +=== Test 3: data out of range (too small) === +%Warning-UNSATCONSTR: PSTByA:12: Unsatisfied constraint +%Warning-UNSATCONSTR: PSTByA:16: Unsatisfied constraint +Randomization failed. + +=== Test 4: data out of range (too large) === +%Warning-UNSATCONSTR: PSTByA:12: Unsatisfied constraint +%Warning-UNSATCONSTR: PSTByA:16: Unsatisfied constraint +Randomization failed. + +=== Test 5: Both constraints violated === +%Warning-UNSATCONSTR: PSTByA:11: Unsatisfied constraint +%Warning-UNSATCONSTR: PSTByA:16: Unsatisfied constraint +Randomization failed. + +=== Test 6: Conflicting constraints (x > 100 && x < 50) === +%Warning-UNSATCONSTR: PSTByA:26: Unsatisfied constraint +%Warning-UNSATCONSTR: PSTByA:27: Unsatisfied constraint +Expected failure: conflicting constraints detected +*-* All Finished *-* diff --git a/test_regress/t/t_constraint_unsat_protect_ids.py b/test_regress/t/t_constraint_unsat_protect_ids.py new file mode 100755 index 000000000..ccab5b2e3 --- /dev/null +++ b/test_regress/t/t_constraint_unsat_protect_ids.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_constraint_unsat.v" + +if not test.have_solver: + test.skip("No constraint solver installed") + +# This test makes randomly named .cpp/.h files, which tend to collect, so remove them first +for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir + "/*_PS*.h") + + glob.glob(test.obj_dir + "/*.d")): + test.unlink_ok(filename) + +test.compile(verilator_flags2=["--protect-ids", "--protect-key SECRET_KEY"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_unsup.out b/test_regress/t/t_constraint_unsup.out index 2708313a4..1d67b149c 100644 --- a/test_regress/t/t_constraint_unsup.out +++ b/test_regress/t/t_constraint_unsup.out @@ -1,5 +1,6 @@ -%Error-UNSUPPORTED: t/t_constraint_unsup.v:9:22: Unsupported expression inside constraint - 9 | constraint cons { $onehot(m_one) == 1; } - | ^~~~~~~ +%Error-UNSUPPORTED: t/t_constraint_unsup.v:9:29: Unsupported expression inside constraint + : ... note: In instance 't' + 9 | constraint cons { x + 1.0 > 0.0; } + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_constraint_unsup.py b/test_regress/t/t_constraint_unsup.py index 6585af685..b7449248c 100755 --- a/test_regress/t/t_constraint_unsup.py +++ b/test_regress/t/t_constraint_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_constraint_unsup.v b/test_regress/t/t_constraint_unsup.v index 8369075bb..4b1c95031 100644 --- a/test_regress/t/t_constraint_unsup.v +++ b/test_regress/t/t_constraint_unsup.v @@ -1,19 +1,19 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 class Packet; - rand int m_one; - constraint cons { $onehot(m_one) == 1; } + rand real x; + constraint cons { x + 1.0 > 0.0; } endclass module t; - Packet p; + Packet p; - initial begin - p = new; - void'(p.randomize()); - end + initial begin + p = new; + void'(p.randomize()); + end endmodule diff --git a/test_regress/t/t_constraint_unsup_unq_arr.out b/test_regress/t/t_constraint_unsup_unq_arr.out new file mode 100644 index 000000000..9f96b4305 --- /dev/null +++ b/test_regress/t/t_constraint_unsup_unq_arr.out @@ -0,0 +1,23 @@ +%Warning-CONSTRAINTIGN: t/t_constraint_unsup_unq_arr.v:19:5: Unsupported: Unique constraint on static arrays of size > 100 + : ... note: In instance 't' + 19 | unique {uniq_val_arr_400}; + | ^~~~~~ + ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest + ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. +%Warning-CONSTRAINTIGN: t/t_constraint_unsup_unq_arr.v:22:5: Unsupported: Unique constraint on other than static arrays + : ... note: In instance 't' + 22 | unique {uniq_val_darr}; + | ^~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_unsup_unq_arr.v:23:5: Unsupported: Unique constraint on other than static arrays + : ... note: In instance 't' + 23 | unique {uniq_val_hash}; + | ^~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_unsup_unq_arr.v:24:5: Unsupported: Unique constraint on other than static arrays + : ... note: In instance 't' + 24 | unique {uniq_val_queue}; + | ^~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_unsup_unq_arr.v:25:5: Unsupported: Unique constraint on other than static arrays + : ... note: In instance 't' + 25 | unique {uniq_val_arr_mda}; + | ^~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_constraint_unsup_unq_arr.py b/test_regress/t/t_constraint_unsup_unq_arr.py new file mode 100755 index 000000000..b7449248c --- /dev/null +++ b/test_regress/t/t_constraint_unsup_unq_arr.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_constraint_unsup_unq_arr.v b/test_regress/t/t_constraint_unsup_unq_arr.v new file mode 100644 index 000000000..8759092c7 --- /dev/null +++ b/test_regress/t/t_constraint_unsup_unq_arr.v @@ -0,0 +1,67 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 AsFigo +// SPDX-License-Identifier: CC0-1.0 +class UniqueMultipleArray; + rand bit [15:0] uniq_val_arr[4]; + rand bit [15:0] uniq_val_arr_400[400]; + rand bit [15:0] uniq_val_arr_mda[4][]; + rand bit [15:0] uniq_val_darr[]; + rand bit [15:0] uniq_val_hash[int]; + rand bit [15:0] uniq_val_queue[$]; + rand bit b1; + rand int array[2]; // 2,4,6 // TODO: add rand when supported + + // Constraint to ensure the elements in the array are unique + constraint unique_c { + unique {uniq_val_arr}; // Ensure unique values in the array + unique {uniq_val_arr_400}; // Ensure unique values in the array + } + constraint unique_c1 { + unique {uniq_val_darr}; // Ensure unique values in the array + unique {uniq_val_hash}; // Ensure unique values in the array + unique {uniq_val_queue}; // Ensure unique values in the array + unique {uniq_val_arr_mda}; // Ensure unique values in the array + unique {array[0], array[1]}; + } + // -------------------------------------------------- + // Explicit uniqueness checker (post-solve validation) + // -------------------------------------------------- + function bit check_unique(); + for (int i = 0; i < $size(uniq_val_arr); i++) begin + for (int j = i + 1; j < $size(uniq_val_arr); j++) begin + if (uniq_val_arr[i] == uniq_val_arr[j]) begin + $error("UNIQUENESS VIOLATION: uniq_val_arr[%0d] == uniq_val_arr[%0d] == 0x%h", i, j, + uniq_val_arr[i]); + return 0; + end + end + end + return 1; + endfunction + + function void post_randomize(); + $display("Randomized values in uniq_val_arr: %p", uniq_val_arr); + + if (!check_unique()) begin + $fatal(1, "Post-randomize uniqueness check FAILED"); + end + foreach (uniq_val_arr[i]) begin + $display("uniq_val_arr[%0d] = 0x%h", i, uniq_val_arr[i]); + end + endfunction + +endclass : UniqueMultipleArray + +module t; + initial begin + // Create an instance of the UniqueMultipleArray class + automatic UniqueMultipleArray array_instance = new(); + + // Attempt to randomize and verify the constraints + /* verilator lint_off WIDTHTRUNC */ + assert (array_instance.randomize()) + else $error("Randomization failed!"); + end +endmodule : t diff --git a/test_regress/t/t_constraint_xml.out b/test_regress/t/t_constraint_xml.out deleted file mode 100644 index f332f7ec3..000000000 --- a/test_regress/t/t_constraint_xml.out +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_constraint_xml.py b/test_regress/t/t_constraint_xml.py deleted file mode 100755 index f2bffa381..000000000 --- a/test_regress/t/t_constraint_xml.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '-Wno-CONSTRAINTIGN'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_constraint_xml.v b/test_regress/t/t_constraint_xml.v deleted file mode 100644 index c455e919d..000000000 --- a/test_regress/t/t_constraint_xml.v +++ /dev/null @@ -1,76 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -class Packet; - rand int header; // 0..7 - rand int length; // 0..15 - rand int sublength; // 0..15 - rand bit if_4; - rand bit iff_5_6; - rand bit if_state_ok; - - rand int array[2]; // 2,4,6 - - string state; - - constraint empty {} - - constraint size { - header > 0 && header <= 7; - length <= 15; - length >= header; - length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; - } - - constraint ifs { - if (header > 4) { - if_4 == '1; - } - if (header == 5 || header == 6) { - iff_5_6 == '1; - iff_5_6 == '1; - iff_5_6 == '1; - } else { - iff_5_6 == '0; - } - } - - constraint arr_uniq { - foreach (array[i]) { - array[i] inside {2, 4, 6}; - } - unique { array[0], array[1] }; - } - - constraint order { solve length before header; } - - constraint dis { - soft sublength; - disable soft sublength; - sublength <= length; - } - - constraint meth { - if (strings_equal(state, "ok")) - if_state_ok == '1; - } - - function bit strings_equal(string a, string b); - return a == b; - endfunction - -endclass - -module t; - - Packet p; - - initial begin - // Not testing use of constraints - $write("*-* All Finished *-*\n"); - $finish; - end -endmodule diff --git a/test_regress/t/t_cover_assert.out b/test_regress/t/t_cover_assert.out index bfbf00219..f376db8e7 100644 --- a/test_regress/t/t_cover_assert.out +++ b/test_regress/t/t_cover_assert.out @@ -1,17 +1,6 @@ -%Warning-PROCASSINIT: t/t_cover_assert.v:13:18: Procedural assignment to declaration with initial value: 'cyc' - : ... note: In instance 't' - : ... Location of variable initialization - 13 | integer cyc = 0; - | ^ - t/t_cover_assert.v:19:7: ... Location of variable process write - : ... Perhaps should initialize instead using a reset in this process - 19 | cyc <= cyc + 1; - | ^~~ - ... For warning description see https://verilator.org/warn/PROCASSINIT?v=latest - ... Use "/* verilator lint_off PROCASSINIT */" and lint_on around source to disable this message. -%Error-UNSUPPORTED: t/t_cover_assert.v:39:11: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) - : ... note: In instance 't' - 39 | C1: cover property(a) - | ^~~~~ +%Error-UNSUPPORTED: t/t_cover_assert.v:38:5: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) + : ... note: In instance 't' + 38 | cover property (a) begin + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_cover_assert.py b/test_regress/t/t_cover_assert.py index 5ca9ccb5c..5a06bae30 100755 --- a/test_regress/t/t_cover_assert.py +++ b/test_regress/t/t_cover_assert.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_assert.v b/test_regress/t/t_cover_assert.v index 94ec4456b..8b5f8ae1b 100644 --- a/test_regress/t/t_cover_assert.v +++ b/test_regress/t/t_cover_assert.v @@ -1,46 +1,44 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - bit a; - bit b; + int cyc; + bit a; + bit b; - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - a <= '0; - b <= '0; - end - else if (cyc == 10) begin - a <= '1; - b <= '1; - end - else if (cyc == 11) begin - a <= '0; - b <= '1; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + a <= '0; + b <= '0; + end + else if (cyc == 10) begin + a <= '1; + b <= '1; + end + else if (cyc == 11) begin + a <= '0; + b <= '1; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always_ff @(posedge clk) begin - C1: cover property(a) - begin - // Assert under cover legal in some other simulators - A2: assert (b); - end - end + always_ff @(posedge clk) begin + C1 : + cover property (a) begin + // Assert under cover legal in some other simulators + A2 : assert (b); + end + end endmodule diff --git a/test_regress/t/t_cover_const_compare.py b/test_regress/t/t_cover_const_compare.py index 313bee7b5..1ccbf459d 100755 --- a/test_regress/t/t_cover_const_compare.py +++ b/test_regress/t/t_cover_const_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_const_compare.v b/test_regress/t/t_cover_const_compare.v index aba12c115..9b380cd25 100644 --- a/test_regress/t/t_cover_const_compare.v +++ b/test_regress/t/t_cover_const_compare.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_cover_expr.out b/test_regress/t/t_cover_expr.out index 336cf1c14..d82c98c8d 100644 --- a/test_regress/t/t_cover_expr.out +++ b/test_regress/t/t_cover_expr.out @@ -1,8 +1,8 @@ // // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2024 by Wilson Snyder. + // This file ONLY is placed under the Creative Commons Public Domain. + // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class cls; @@ -36,15 +36,15 @@ function automatic bit invert(bit x); %000005 return ~x; --000004 point: comment=(x==0) => 1 hier=top.t --000005 point: comment=(x==1) => 0 hier=top.t +-000004 point: type=expr comment=(x==0) => 1 hier=top.t +-000005 point: type=expr comment=(x==1) => 0 hier=top.t endfunction function automatic bit and_oper(bit a, bit b); %000005 return a & b; --000004 point: comment=(a==0) => 0 hier=top.t --000002 point: comment=(a==1 && b==1) => 1 hier=top.t --000005 point: comment=(b==0) => 0 hier=top.t +-000004 point: type=expr comment=(a==0) => 0 hier=top.t +-000002 point: type=expr comment=(a==1 && b==1) => 1 hier=top.t +-000005 point: type=expr comment=(b==0) => 0 hier=top.t endfunction localparam int NUM_INTFS = 4; @@ -57,216 +57,216 @@ always @ (posedge clk) begin cyc <= cyc + 1; %000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); --000002 point: comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t --000004 point: comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t --000002 point: comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t --000003 point: comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t --000002 point: comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t %000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); --000002 point: comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t --000002 point: comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t --000004 point: comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t --000002 point: comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t --000003 point: comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t --000002 point: comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t +-000004 point: type=expr comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t %000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); --000002 point: comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t --000002 point: comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t --000004 point: comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t --000002 point: comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t --000003 point: comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t --000002 point: comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t +-000002 point: type=expr comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t +-000002 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t +-000004 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t +-000002 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t +-000003 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t +-000002 point: type=expr comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t %000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t %000005 if (t3 && (t1 == t2)) $write(""); --000005 point: comment=((t1 == t2)==0) => 0 hier=top.t --000005 point: comment=(t3==0) => 0 hier=top.t --000002 point: comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t +-000005 point: type=expr comment=((t1 == t2)==0) => 0 hier=top.t +-000005 point: type=expr comment=(t3==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t %000005 if (123 == (124 - 32'(t1 || t2))) $write(""); --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000005 point: comment=(t1==1) => 1 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==1) => 1 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t %000004 some_int <= (t2 || t3) ? 345 : 567; --000003 point: comment=(t2==0 && t3==0) => 0 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t --000004 point: comment=(t3==1) => 1 hier=top.t +-000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t +-000004 point: type=expr comment=(t3==1) => 1 hier=top.t %000005 some_bool <= t1 && t2; --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2) $write(""); --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t %000003 if (t1 ^ t2) $write(""); --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t %000005 if (~(t1 & t2)) $write(""); --000004 point: comment=(t1==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t --000005 point: comment=(t2==0) => 1 hier=top.t +-000004 point: type=expr comment=(t1==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 1 hier=top.t %000004 if (t1 -> t2) $write(""); --000004 point: comment=(t1==0) => 1 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t +-000004 point: type=expr comment=(t1==0) => 1 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t %000003 if (t1 <-> t2) $write(""); --000002 point: comment=(t1==0 && t2==0) => 1 hier=top.t --000002 point: comment=(t1==0 && t2==1) => 0 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 0 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t %000005 if (&cyc[2:0]) $write(""); --000004 point: comment=(cyc[2:0][0]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t --000005 point: comment=(cyc[2:0][1]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][2]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][0]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][1]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][2]==0) => 0 hier=top.t %000007 if (&cyc[3:2]) $write(""); --000005 point: comment=(cyc[3:2][0]==0) => 0 hier=top.t --000000 point: comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t --000007 point: comment=(cyc[3:2][1]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[3:2][0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t +-000007 point: type=expr comment=(cyc[3:2][1]==0) => 0 hier=top.t %000005 if (|cyc[2:0]) $write(""); --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t %000002 if (^cyc[2:0]) $write(""); --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t --000002 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t %000005 if (|cyc[2:0] || cyc[3]) $write(""); --000000 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t --000002 point: comment=(cyc[3]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[3]==1) => 1 hier=top.t %000005 if (t1 & t2 & 1'b1) $write(""); --000000 point: comment=(1'h1==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000000 point: type=expr comment=(1'h1==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & 1'b0) $write(""); --000009 point: comment=(1'h0==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000009 point: type=expr comment=(1'h0==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2 & ONE) $write(""); --000000 point: comment=(ONE==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000000 point: type=expr comment=(ONE==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & ZERO) $write(""); --000009 point: comment=(ZERO==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000009 point: type=expr comment=(ZERO==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if (t1 && t2) begin --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t $write(""); %000003 end else if (t1 || t2) begin --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000003 point: comment=(t1==1) => 1 hier=top.t --000002 point: comment=(t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000003 point: type=expr comment=(t1==1) => 1 hier=top.t +-000002 point: type=expr comment=(t2==1) => 1 hier=top.t $write(""); end %000005 if (invert(t1) && t2) $write(""); --000005 point: comment=(invert(t1)==0) => 0 hier=top.t --000002 point: comment=(invert(t1)==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000005 point: type=expr comment=(invert(t1)==0) => 0 hier=top.t +-000002 point: type=expr comment=(invert(t1)==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t if (and_oper(t1, t2)) $write(""); %000005 if (t2 && t3) begin --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=(t2==1 && t3==1) => 1 hier=top.t --000005 point: comment=(t3==0) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==1 && t3==1) => 1 hier=top.t +-000005 point: type=expr comment=(t3==0) => 0 hier=top.t %000001 if (t1 && t2) $write(""); --000001 point: comment=(t1==0) => 0 hier=top.t --000001 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000000 point: comment=(t2==0) => 0 hier=top.t +-000001 point: type=expr comment=(t1==0) => 0 hier=top.t +-000001 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000000 point: type=expr comment=(t2==0) => 0 hier=top.t end if (0 == 1) begin for (int loop_var = 0; loop_var < 1; loop_var++) begin %000000 if (cyc[loop_var] && t2) $write(""); --000000 point: comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t --000000 point: comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t --000000 point: comment=(t2==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t +-000000 point: type=expr comment=(t2==0) => 0 hier=top.t end end // stop at the first layer even if there's more to find %000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); --000002 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t --000007 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t --000000 point: comment=(cyc[31]==1) => 1 hier=top.t +-000002 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t +-000007 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[31]==1) => 1 hier=top.t // impossible branches and redundant terms %000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); --000003 point: comment=(t1==0 && t4==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t --000001 point: comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t +-000001 point: type=expr comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); --000003 point: comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t // demonstrate current limitations of term matching scheme %000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); --000002 point: comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t --000003 point: comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t --000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t //verilator coverage_off if (t1 && t2) $write(""); //verilator coverage_on if ((~t1 && t2) %000004 || --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t (~t3 && t4)) $write(""); // intentionally testing wonkified expression terms if ( cyc[ 0 %000005 ] & --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t cyc [1]) $write(""); // for now each ternary condition is considered in isolation %000005 other_int <= t1 ? t2 ? 1 : 2 : 3; --000004 point: comment=(t1==0) => 0 hier=top.t --000005 point: comment=(t1==1) => 1 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==1) => 1 hier=top.t // no expression coverage for multi-bit expressions if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); // truth table is too large @@ -281,17 +281,17 @@ always_comb begin %000005 if (t1 && t2) $write(""); --000005 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t end logic ta, tb, tc; initial begin - cls obj = new; - cls null_obj = null; - int q[5]; - int qv[$]; + automatic cls obj = new; + automatic cls null_obj = null; + automatic int q[5]; + automatic int qv[$]; q = '{1, 2, 2, 4, 3}; // lambas not handled @@ -302,10 +302,10 @@ tb = '0; tc = '0; %000001 while (ta || tb || tc) begin --000001 point: comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t --000000 point: comment=(ta==1) => 1 hier=top.t --000000 point: comment=(tb==1) => 1 hier=top.t --000000 point: comment=(tc==1) => 1 hier=top.t +-000001 point: type=expr comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t +-000000 point: type=expr comment=(ta==1) => 1 hier=top.t +-000000 point: type=expr comment=(tb==1) => 1 hier=top.t +-000000 point: type=expr comment=(tc==1) => 1 hier=top.t tc = tb; tb = ta; ta = '0; @@ -326,7 +326,7 @@ // // Branches which are statically impossible to reach are still reported. // E.g. - // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t + // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. @@ -340,9 +340,9 @@ always_comb begin ~000019 if (p && q) $write(""); -+000017 point: comment=(p==0) => 0 hier=top.t.the_sub_* --000002 point: comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* -+000019 point: comment=(q==0) => 0 hier=top.t.the_sub_* ++000017 point: type=expr comment=(p==0) => 0 hier=top.t.the_sub_* +-000002 point: type=expr comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* ++000019 point: type=expr comment=(q==0) => 0 hier=top.t.the_sub_* end endmodule diff --git a/test_regress/t/t_cover_expr.py b/test_regress/t/t_cover_expr.py index 0f9b3aca8..413e34601 100755 --- a/test_regress/t/t_cover_expr.py +++ b/test_regress/t/t_cover_expr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_expr.v b/test_regress/t/t_cover_expr.v index cef3ec0d6..488569a2d 100644 --- a/test_regress/t/t_cover_expr.v +++ b/test_regress/t/t_cover_expr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class cls; @@ -128,10 +128,10 @@ module t (/*AUTOARG*/ logic ta, tb, tc; initial begin - cls obj = new; - cls null_obj = null; - int q[5]; - int qv[$]; + automatic cls obj = new; + automatic cls null_obj = null; + automatic int q[5]; + automatic int qv[$]; q = '{1, 2, 2, 4, 3}; // lambas not handled @@ -162,7 +162,7 @@ module t (/*AUTOARG*/ // // Branches which are statically impossible to reach are still reported. // E.g. - // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t + // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. diff --git a/test_regress/t/t_cover_expr_array_class.py b/test_regress/t/t_cover_expr_array_class.py index 27aec629f..ef0f2bae6 100755 --- a/test_regress/t/t_cover_expr_array_class.py +++ b/test_regress/t/t_cover_expr_array_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_expr_array_class.v b/test_regress/t/t_cover_expr_array_class.v index 1c82e6a45..e2f6f2d3a 100644 --- a/test_regress/t/t_cover_expr_array_class.v +++ b/test_regress/t/t_cover_expr_array_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Class1; @@ -10,10 +10,10 @@ endclass module t; initial begin - int i = 0; + int i; Class1 q[15]; for (int j = 0; j < 15; j = j + 1) begin - Class1 x = new; + automatic Class1 x = new; q[j] = x; end while (i < 15) begin diff --git a/test_regress/t/t_cover_expr_associative_array_class.py b/test_regress/t/t_cover_expr_associative_array_class.py index 27aec629f..ef0f2bae6 100755 --- a/test_regress/t/t_cover_expr_associative_array_class.py +++ b/test_regress/t/t_cover_expr_associative_array_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_expr_associative_array_class.v b/test_regress/t/t_cover_expr_associative_array_class.v index 2c1057a3b..ac7b1ef6c 100644 --- a/test_regress/t/t_cover_expr_associative_array_class.v +++ b/test_regress/t/t_cover_expr_associative_array_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Class1; @@ -10,10 +10,10 @@ endclass module t; initial begin - int i = 0; - Class1 q[int] = '{}; + int i; + automatic Class1 q[int] = '{}; for (int j = 0; j < 15; j = j + 1) begin - Class1 x = new; + automatic Class1 x = new; q[j] = x; end while (i < 15) begin diff --git a/test_regress/t/t_cover_expr_dyn_array_class.py b/test_regress/t/t_cover_expr_dyn_array_class.py index 27aec629f..ef0f2bae6 100755 --- a/test_regress/t/t_cover_expr_dyn_array_class.py +++ b/test_regress/t/t_cover_expr_dyn_array_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_expr_dyn_array_class.v b/test_regress/t/t_cover_expr_dyn_array_class.v index 5cd5ab1cc..47e4ede5b 100644 --- a/test_regress/t/t_cover_expr_dyn_array_class.v +++ b/test_regress/t/t_cover_expr_dyn_array_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Class1; @@ -10,10 +10,10 @@ endclass module t; initial begin - int i = 0; - Class1 q[] = new [15]; + automatic int i; + automatic Class1 q[] = new [15]; for (int j = 0; j < 15; j = j + 1) begin - Class1 x = new; + automatic Class1 x = new; q[j] = x; end while (i < 15) begin diff --git a/test_regress/t/t_cover_expr_max.out b/test_regress/t/t_cover_expr_max.out index 68ce59c64..39d5174f4 100644 --- a/test_regress/t/t_cover_expr_max.out +++ b/test_regress/t/t_cover_expr_max.out @@ -1,8 +1,8 @@ // // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2024 by Wilson Snyder. + // This file ONLY is placed under the Creative Commons Public Domain. + // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class cls; @@ -36,15 +36,15 @@ function automatic bit invert(bit x); %000005 return ~x; --000004 point: comment=(x==0) => 1 hier=top.t --000005 point: comment=(x==1) => 0 hier=top.t +-000004 point: type=expr comment=(x==0) => 1 hier=top.t +-000005 point: type=expr comment=(x==1) => 0 hier=top.t endfunction function automatic bit and_oper(bit a, bit b); %000005 return a & b; --000004 point: comment=(a==0) => 0 hier=top.t --000002 point: comment=(a==1 && b==1) => 1 hier=top.t --000005 point: comment=(b==0) => 0 hier=top.t +-000004 point: type=expr comment=(a==0) => 0 hier=top.t +-000002 point: type=expr comment=(a==1 && b==1) => 1 hier=top.t +-000005 point: type=expr comment=(b==0) => 0 hier=top.t endfunction localparam int NUM_INTFS = 4; @@ -57,348 +57,348 @@ always @ (posedge clk) begin cyc <= cyc + 1; %000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); --000002 point: comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t --000004 point: comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t --000002 point: comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t --000003 point: comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t --000002 point: comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t %000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); --000002 point: comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t --000002 point: comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t --000004 point: comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t --000002 point: comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t --000003 point: comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t --000002 point: comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t +-000004 point: type=expr comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t %000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); --000002 point: comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t --000002 point: comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t --000004 point: comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t --000002 point: comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t --000003 point: comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t --000002 point: comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t +-000002 point: type=expr comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t +-000002 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t +-000004 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t +-000002 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t +-000003 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t +-000002 point: type=expr comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t %000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t %000005 if (t3 && (t1 == t2)) $write(""); --000005 point: comment=((t1 == t2)==0) => 0 hier=top.t --000005 point: comment=(t3==0) => 0 hier=top.t --000002 point: comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t +-000005 point: type=expr comment=((t1 == t2)==0) => 0 hier=top.t +-000005 point: type=expr comment=(t3==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t %000005 if (123 == (124 - 32'(t1 || t2))) $write(""); --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000005 point: comment=(t1==1) => 1 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==1) => 1 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t %000004 some_int <= (t2 || t3) ? 345 : 567; --000003 point: comment=(t2==0 && t3==0) => 0 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t --000004 point: comment=(t3==1) => 1 hier=top.t +-000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t +-000004 point: type=expr comment=(t3==1) => 1 hier=top.t %000005 some_bool <= t1 && t2; --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2) $write(""); --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t %000003 if (t1 ^ t2) $write(""); --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t %000005 if (~(t1 & t2)) $write(""); --000004 point: comment=(t1==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t --000005 point: comment=(t2==0) => 1 hier=top.t +-000004 point: type=expr comment=(t1==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 1 hier=top.t %000004 if (t1 -> t2) $write(""); --000004 point: comment=(t1==0) => 1 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t +-000004 point: type=expr comment=(t1==0) => 1 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t %000003 if (t1 <-> t2) $write(""); --000002 point: comment=(t1==0 && t2==0) => 1 hier=top.t --000002 point: comment=(t1==0 && t2==1) => 0 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 0 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t %000005 if (&cyc[2:0]) $write(""); --000004 point: comment=(cyc[2:0][0]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t --000005 point: comment=(cyc[2:0][1]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][2]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][0]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][1]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][2]==0) => 0 hier=top.t %000007 if (&cyc[3:2]) $write(""); --000005 point: comment=(cyc[3:2][0]==0) => 0 hier=top.t --000000 point: comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t --000007 point: comment=(cyc[3:2][1]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[3:2][0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t +-000007 point: type=expr comment=(cyc[3:2][1]==0) => 0 hier=top.t %000005 if (|cyc[2:0]) $write(""); --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t %000002 if (^cyc[2:0]) $write(""); --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t --000002 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t %000005 if (|cyc[2:0] || cyc[3]) $write(""); --000000 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t --000002 point: comment=(cyc[3]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[3]==1) => 1 hier=top.t %000005 if (t1 & t2 & 1'b1) $write(""); --000000 point: comment=(1'h1==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000000 point: type=expr comment=(1'h1==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & 1'b0) $write(""); --000009 point: comment=(1'h0==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000009 point: type=expr comment=(1'h0==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2 & ONE) $write(""); --000000 point: comment=(ONE==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000000 point: type=expr comment=(ONE==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & ZERO) $write(""); --000009 point: comment=(ZERO==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000009 point: type=expr comment=(ZERO==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if (t1 && t2) begin --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t $write(""); %000003 end else if (t1 || t2) begin --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000003 point: comment=(t1==1) => 1 hier=top.t --000002 point: comment=(t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000003 point: type=expr comment=(t1==1) => 1 hier=top.t +-000002 point: type=expr comment=(t2==1) => 1 hier=top.t $write(""); end %000005 if (invert(t1) && t2) $write(""); --000005 point: comment=(invert(t1)==0) => 0 hier=top.t --000002 point: comment=(invert(t1)==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000005 point: type=expr comment=(invert(t1)==0) => 0 hier=top.t +-000002 point: type=expr comment=(invert(t1)==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t if (and_oper(t1, t2)) $write(""); %000005 if (t2 && t3) begin --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=(t2==1 && t3==1) => 1 hier=top.t --000005 point: comment=(t3==0) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==1 && t3==1) => 1 hier=top.t +-000005 point: type=expr comment=(t3==0) => 0 hier=top.t %000001 if (t1 && t2) $write(""); --000001 point: comment=(t1==0) => 0 hier=top.t --000001 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000000 point: comment=(t2==0) => 0 hier=top.t +-000001 point: type=expr comment=(t1==0) => 0 hier=top.t +-000001 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000000 point: type=expr comment=(t2==0) => 0 hier=top.t end if (0 == 1) begin for (int loop_var = 0; loop_var < 1; loop_var++) begin %000000 if (cyc[loop_var] && t2) $write(""); --000000 point: comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t --000000 point: comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t --000000 point: comment=(t2==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t +-000000 point: type=expr comment=(t2==0) => 0 hier=top.t end end // stop at the first layer even if there's more to find %000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); --000002 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t --000007 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t --000000 point: comment=(cyc[31]==1) => 1 hier=top.t +-000002 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t +-000007 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[31]==1) => 1 hier=top.t // impossible branches and redundant terms %000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); --000003 point: comment=(t1==0 && t4==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t --000001 point: comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t +-000001 point: type=expr comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); --000003 point: comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t // demonstrate current limitations of term matching scheme %000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); --000002 point: comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t --000003 point: comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t --000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t //verilator coverage_off if (t1 && t2) $write(""); //verilator coverage_on if ((~t1 && t2) %000004 || --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t (~t3 && t4)) $write(""); // intentionally testing wonkified expression terms if ( cyc[ 0 %000005 ] & --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t cyc [1]) $write(""); // for now each ternary condition is considered in isolation %000005 other_int <= t1 ? t2 ? 1 : 2 : 3; --000004 point: comment=(t1==0) => 0 hier=top.t --000005 point: comment=(t1==1) => 1 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==1) => 1 hier=top.t // no expression coverage for multi-bit expressions if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); // truth table is too large %000001 if (^cyc[6:0]) $write(""); --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t --000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t --000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t --000001 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && 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cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && 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cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t --000000 point: comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==0 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==0 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==0 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==0 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==0 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==0) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==0 && cyc[6:0][6]==1) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[6:0][0]==1 && cyc[6:0][1]==1 && cyc[6:0][2]==1 && cyc[6:0][3]==1 && cyc[6:0][4]==1 && cyc[6:0][5]==1 && cyc[6:0][6]==1) => 1 hier=top.t // this one is too big even for t_cover_expr_max if (^cyc) $write(""); if (cyc==9) begin @@ -409,17 +409,17 @@ always_comb begin %000005 if (t1 && t2) $write(""); --000005 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t end logic ta, tb, tc; initial begin - cls obj = new; - cls null_obj = null; - int q[5]; - int qv[$]; + automatic cls obj = new; + automatic cls null_obj = null; + automatic int q[5]; + automatic int qv[$]; q = '{1, 2, 2, 4, 3}; // lambas not handled @@ -430,10 +430,10 @@ tb = '0; tc = '0; %000001 while (ta || tb || tc) begin --000001 point: comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t --000000 point: comment=(ta==1) => 1 hier=top.t --000000 point: comment=(tb==1) => 1 hier=top.t --000000 point: comment=(tc==1) => 1 hier=top.t +-000001 point: type=expr comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t +-000000 point: type=expr comment=(ta==1) => 1 hier=top.t +-000000 point: type=expr comment=(tb==1) => 1 hier=top.t +-000000 point: type=expr comment=(tc==1) => 1 hier=top.t tc = tb; tb = ta; ta = '0; @@ -454,7 +454,7 @@ // // Branches which are statically impossible to reach are still reported. // E.g. - // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t + // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. @@ -468,9 +468,9 @@ always_comb begin ~000019 if (p && q) $write(""); -+000017 point: comment=(p==0) => 0 hier=top.t.the_sub_* --000002 point: comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* -+000019 point: comment=(q==0) => 0 hier=top.t.the_sub_* ++000017 point: type=expr comment=(p==0) => 0 hier=top.t.the_sub_* +-000002 point: type=expr comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* ++000019 point: type=expr comment=(q==0) => 0 hier=top.t.the_sub_* end endmodule diff --git a/test_regress/t/t_cover_expr_max.py b/test_regress/t/t_cover_expr_max.py index bc3049c66..9647dcec2 100755 --- a/test_regress/t/t_cover_expr_max.py +++ b/test_regress/t/t_cover_expr_max.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_expr_queue_class.py b/test_regress/t/t_cover_expr_queue_class.py index 27aec629f..ef0f2bae6 100755 --- a/test_regress/t/t_cover_expr_queue_class.py +++ b/test_regress/t/t_cover_expr_queue_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_expr_queue_class.v b/test_regress/t/t_cover_expr_queue_class.v index fefcb0f36..abae5e3b5 100644 --- a/test_regress/t/t_cover_expr_queue_class.v +++ b/test_regress/t/t_cover_expr_queue_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Class1; @@ -10,10 +10,10 @@ endclass module t; initial begin - int i = 0; + int i; Class1 q[$]; repeat(15) begin - Class1 x = new; + automatic Class1 x = new; q = { q, x }; end while (i < q.size()) begin diff --git a/test_regress/t/t_cover_expr_trace.out b/test_regress/t/t_cover_expr_trace.out index 336cf1c14..d82c98c8d 100644 --- a/test_regress/t/t_cover_expr_trace.out +++ b/test_regress/t/t_cover_expr_trace.out @@ -1,8 +1,8 @@ // // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2024 by Wilson Snyder. + // This file ONLY is placed under the Creative Commons Public Domain. + // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class cls; @@ -36,15 +36,15 @@ function automatic bit invert(bit x); %000005 return ~x; --000004 point: comment=(x==0) => 1 hier=top.t --000005 point: comment=(x==1) => 0 hier=top.t +-000004 point: type=expr comment=(x==0) => 1 hier=top.t +-000005 point: type=expr comment=(x==1) => 0 hier=top.t endfunction function automatic bit and_oper(bit a, bit b); %000005 return a & b; --000004 point: comment=(a==0) => 0 hier=top.t --000002 point: comment=(a==1 && b==1) => 1 hier=top.t --000005 point: comment=(b==0) => 0 hier=top.t +-000004 point: type=expr comment=(a==0) => 0 hier=top.t +-000002 point: type=expr comment=(a==1 && b==1) => 1 hier=top.t +-000005 point: type=expr comment=(b==0) => 0 hier=top.t endfunction localparam int NUM_INTFS = 4; @@ -57,216 +57,216 @@ always @ (posedge clk) begin cyc <= cyc + 1; %000004 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); --000002 point: comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t --000004 point: comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t --000002 point: comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t --000003 point: comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t --000002 point: comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t %000004 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); --000002 point: comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t --000002 point: comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t --000004 point: comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t --000002 point: comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t --000003 point: comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t --000002 point: comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t +-000004 point: type=expr comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t %000004 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); --000002 point: comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t --000002 point: comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t --000004 point: comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t --000002 point: comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t --000003 point: comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t --000002 point: comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t +-000002 point: type=expr comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t +-000002 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t +-000004 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t +-000002 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t +-000003 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t +-000002 point: type=expr comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t %000004 if ((~t1 && t2) || (~t3 && t4)) $write(""); --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t %000005 if (t3 && (t1 == t2)) $write(""); --000005 point: comment=((t1 == t2)==0) => 0 hier=top.t --000005 point: comment=(t3==0) => 0 hier=top.t --000002 point: comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t +-000005 point: type=expr comment=((t1 == t2)==0) => 0 hier=top.t +-000005 point: type=expr comment=(t3==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t %000005 if (123 == (124 - 32'(t1 || t2))) $write(""); --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000005 point: comment=(t1==1) => 1 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==1) => 1 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t %000004 some_int <= (t2 || t3) ? 345 : 567; --000003 point: comment=(t2==0 && t3==0) => 0 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t --000004 point: comment=(t3==1) => 1 hier=top.t +-000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t +-000004 point: type=expr comment=(t3==1) => 1 hier=top.t %000005 some_bool <= t1 && t2; --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2) $write(""); --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000004 if ((!t1 && t2) | (~t3 && t4)) $write(""); --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t %000003 if (t1 ^ t2) $write(""); --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t %000005 if (~(t1 & t2)) $write(""); --000004 point: comment=(t1==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t --000005 point: comment=(t2==0) => 1 hier=top.t +-000004 point: type=expr comment=(t1==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 1 hier=top.t %000004 if (t1 -> t2) $write(""); --000004 point: comment=(t1==0) => 1 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t +-000004 point: type=expr comment=(t1==0) => 1 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t %000003 if (t1 <-> t2) $write(""); --000002 point: comment=(t1==0 && t2==0) => 1 hier=top.t --000002 point: comment=(t1==0 && t2==1) => 0 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 0 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t %000005 if (&cyc[2:0]) $write(""); --000004 point: comment=(cyc[2:0][0]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t --000005 point: comment=(cyc[2:0][1]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][2]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][0]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][1]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][2]==0) => 0 hier=top.t %000007 if (&cyc[3:2]) $write(""); --000005 point: comment=(cyc[3:2][0]==0) => 0 hier=top.t --000000 point: comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t --000007 point: comment=(cyc[3:2][1]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[3:2][0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t +-000007 point: type=expr comment=(cyc[3:2][1]==0) => 0 hier=top.t %000005 if (|cyc[2:0]) $write(""); --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t %000002 if (^cyc[2:0]) $write(""); --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t --000002 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t %000005 if (|cyc[2:0] || cyc[3]) $write(""); --000000 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t --000002 point: comment=(cyc[3]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[3]==1) => 1 hier=top.t %000005 if (t1 & t2 & 1'b1) $write(""); --000000 point: comment=(1'h1==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000000 point: type=expr comment=(1'h1==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & 1'b0) $write(""); --000009 point: comment=(1'h0==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000009 point: type=expr comment=(1'h0==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if (t1 & t2 & ONE) $write(""); --000000 point: comment=(ONE==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000000 point: type=expr comment=(ONE==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000009 if (t1 & t2 & ZERO) $write(""); --000009 point: comment=(ZERO==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000009 point: type=expr comment=(ZERO==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if (t1 && t2) begin --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t $write(""); %000003 end else if (t1 || t2) begin --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000003 point: comment=(t1==1) => 1 hier=top.t --000002 point: comment=(t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000003 point: type=expr comment=(t1==1) => 1 hier=top.t +-000002 point: type=expr comment=(t2==1) => 1 hier=top.t $write(""); end %000005 if (invert(t1) && t2) $write(""); --000005 point: comment=(invert(t1)==0) => 0 hier=top.t --000002 point: comment=(invert(t1)==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000005 point: type=expr comment=(invert(t1)==0) => 0 hier=top.t +-000002 point: type=expr comment=(invert(t1)==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t if (and_oper(t1, t2)) $write(""); %000005 if (t2 && t3) begin --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=(t2==1 && t3==1) => 1 hier=top.t --000005 point: comment=(t3==0) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==1 && t3==1) => 1 hier=top.t +-000005 point: type=expr comment=(t3==0) => 0 hier=top.t %000001 if (t1 && t2) $write(""); --000001 point: comment=(t1==0) => 0 hier=top.t --000001 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000000 point: comment=(t2==0) => 0 hier=top.t +-000001 point: type=expr comment=(t1==0) => 0 hier=top.t +-000001 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000000 point: type=expr comment=(t2==0) => 0 hier=top.t end if (0 == 1) begin for (int loop_var = 0; loop_var < 1; loop_var++) begin %000000 if (cyc[loop_var] && t2) $write(""); --000000 point: comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t --000000 point: comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t --000000 point: comment=(t2==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t +-000000 point: type=expr comment=(t2==0) => 0 hier=top.t end end // stop at the first layer even if there's more to find %000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); --000002 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t --000007 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t --000000 point: comment=(cyc[31]==1) => 1 hier=top.t +-000002 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t +-000007 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[31]==1) => 1 hier=top.t // impossible branches and redundant terms %000005 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); --000003 point: comment=(t1==0 && t4==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t --000001 point: comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t +-000001 point: type=expr comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000005 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); --000003 point: comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t // demonstrate current limitations of term matching scheme %000005 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); --000002 point: comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t --000003 point: comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t --000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t //verilator coverage_off if (t1 && t2) $write(""); //verilator coverage_on if ((~t1 && t2) %000004 || --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t (~t3 && t4)) $write(""); // intentionally testing wonkified expression terms if ( cyc[ 0 %000005 ] & --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t cyc [1]) $write(""); // for now each ternary condition is considered in isolation %000005 other_int <= t1 ? t2 ? 1 : 2 : 3; --000004 point: comment=(t1==0) => 0 hier=top.t --000005 point: comment=(t1==1) => 1 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==1) => 1 hier=top.t // no expression coverage for multi-bit expressions if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); // truth table is too large @@ -281,17 +281,17 @@ always_comb begin %000005 if (t1 && t2) $write(""); --000005 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t end logic ta, tb, tc; initial begin - cls obj = new; - cls null_obj = null; - int q[5]; - int qv[$]; + automatic cls obj = new; + automatic cls null_obj = null; + automatic int q[5]; + automatic int qv[$]; q = '{1, 2, 2, 4, 3}; // lambas not handled @@ -302,10 +302,10 @@ tb = '0; tc = '0; %000001 while (ta || tb || tc) begin --000001 point: comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t --000000 point: comment=(ta==1) => 1 hier=top.t --000000 point: comment=(tb==1) => 1 hier=top.t --000000 point: comment=(tc==1) => 1 hier=top.t +-000001 point: type=expr comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t +-000000 point: type=expr comment=(ta==1) => 1 hier=top.t +-000000 point: type=expr comment=(tb==1) => 1 hier=top.t +-000000 point: type=expr comment=(tc==1) => 1 hier=top.t tc = tb; tb = ta; ta = '0; @@ -326,7 +326,7 @@ // // Branches which are statically impossible to reach are still reported. // E.g. - // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t + // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. @@ -340,9 +340,9 @@ always_comb begin ~000019 if (p && q) $write(""); -+000017 point: comment=(p==0) => 0 hier=top.t.the_sub_* --000002 point: comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* -+000019 point: comment=(q==0) => 0 hier=top.t.the_sub_* ++000017 point: type=expr comment=(p==0) => 0 hier=top.t.the_sub_* +-000002 point: type=expr comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* ++000019 point: type=expr comment=(q==0) => 0 hier=top.t.the_sub_* end endmodule diff --git a/test_regress/t/t_cover_expr_trace.py b/test_regress/t/t_cover_expr_trace.py index 5ea8ada9f..a2177bd02 100755 --- a/test_regress/t/t_cover_expr_trace.py +++ b/test_regress/t/t_cover_expr_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_lib.py b/test_regress/t/t_cover_lib.py index f2737198c..ca5f71d0e 100755 --- a/test_regress/t/t_cover_lib.py +++ b/test_regress/t/t_cover_lib.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_lib.v b/test_regress/t/t_cover_lib.v index 252a7d7f5..8450a4402 100644 --- a/test_regress/t/t_cover_lib.v +++ b/test_regress/t/t_cover_lib.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_cover_lib_c.cpp b/test_regress/t/t_cover_lib_c.cpp index 6afe305c6..3d12387b2 100644 --- a/test_regress/t/t_cover_lib_c.cpp +++ b/test_regress/t/t_cover_lib_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_cover_lib_legacy.py b/test_regress/t/t_cover_lib_legacy.py index 54ac9630f..df9cff6d3 100755 --- a/test_regress/t/t_cover_lib_legacy.py +++ b/test_regress/t/t_cover_lib_legacy.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_line.out b/test_regress/t/t_cover_line.out index 06d6e7515..e04e40fbc 100644 --- a/test_regress/t/t_cover_line.out +++ b/test_regress/t/t_cover_line.out @@ -1,8 +1,8 @@ // // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2008 by Wilson Snyder. + // This file ONLY is placed under the Creative Commons Public Domain. + // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ @@ -14,11 +14,11 @@ reg toggle; %000001 initial toggle=0; --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t integer cyc; %000001 initial cyc=1; --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t wire [7:0] cyc_copy = cyc[7:0]; @@ -56,136 +56,136 @@ .cyc (cyc)); 000010 always @ (posedge clk) begin -+000010 point: comment=block hier=top.t ++000010 point: type=line comment=block hier=top.t ~000010 if (cyc!=0) begin -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t 000010 cyc <= cyc + 1; -+000010 point: comment=if hier=top.t ++000010 point: type=branch comment=if hier=top.t 000010 toggle <= '0; -+000010 point: comment=if hier=top.t ++000010 point: type=branch comment=if hier=top.t // Single and multiline if %000009 if (cyc==3) $write(""); --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t %000009 if (cyc==3) --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t %000001 begin --000001 point: comment=if hier=top.t +-000001 point: type=branch comment=if hier=top.t %000001 $write(""); --000001 point: comment=if hier=top.t +-000001 point: type=branch comment=if hier=top.t end // Single and multiline else %000009 if (cyc==3) ; else $write(""); --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t %000009 if (cyc==3) ; --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t else %000009 begin --000009 point: comment=else hier=top.t +-000009 point: type=branch comment=else hier=top.t %000009 $write(""); --000009 point: comment=else hier=top.t +-000009 point: type=branch comment=else hier=top.t end // Single and multiline if else %000009 if (cyc==3) $write(""); else $write(""); --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t %000009 if (cyc==3) --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t %000001 begin --000001 point: comment=if hier=top.t +-000001 point: type=branch comment=if hier=top.t %000001 $write(""); --000001 point: comment=if hier=top.t +-000001 point: type=branch comment=if hier=top.t end else %000009 begin --000009 point: comment=else hier=top.t +-000009 point: type=branch comment=else hier=top.t %000009 $write(""); --000009 point: comment=else hier=top.t +-000009 point: type=branch comment=else hier=top.t end // multiline elseif %000001 if (cyc==3) --000001 point: comment=elsif hier=top.t +-000001 point: type=line comment=elsif hier=top.t %000001 begin --000001 point: comment=elsif hier=top.t +-000001 point: type=line comment=elsif hier=top.t %000001 $write(""); --000001 point: comment=elsif hier=top.t +-000001 point: type=line comment=elsif hier=top.t end %000001 else if (cyc==4) --000001 point: comment=elsif hier=top.t +-000001 point: type=line comment=elsif hier=top.t %000001 begin --000001 point: comment=elsif hier=top.t +-000001 point: type=line comment=elsif hier=top.t %000001 $write(""); --000001 point: comment=elsif hier=top.t +-000001 point: type=line comment=elsif hier=top.t end %000007 else if (cyc==5) --000001 point: comment=if hier=top.t --000007 point: comment=else hier=top.t +-000001 point: type=line comment=if hier=top.t +-000007 point: type=line comment=else hier=top.t %000001 begin --000001 point: comment=if hier=top.t +-000001 point: type=line comment=if hier=top.t %000001 $write(""); --000001 point: comment=if hier=top.t +-000001 point: type=line comment=if hier=top.t end else %000007 begin --000007 point: comment=else hier=top.t +-000007 point: type=line comment=else hier=top.t %000007 $write(""); --000007 point: comment=else hier=top.t +-000007 point: type=line comment=else hier=top.t end // Single and multiline while %000000 while (0); --000000 point: comment=block hier=top.t +-000000 point: type=line comment=block hier=top.t %000000 while (0) begin --000000 point: comment=block hier=top.t +-000000 point: type=line comment=block hier=top.t %000000 $write(""); --000000 point: comment=block hier=top.t +-000000 point: type=line comment=block hier=top.t end %000000 do ; while (0); --000000 point: comment=block hier=top.t +-000000 point: type=line comment=block hier=top.t ~000010 do begin --000000 point: comment=block hier=top.t -+000010 point: comment=block hier=top.t +-000000 point: type=line comment=block hier=top.t ++000010 point: type=line comment=block hier=top.t 000010 $write(""); -+000010 point: comment=block hier=top.t ++000010 point: type=line comment=block hier=top.t ~000010 end while (0); --000000 point: comment=block hier=top.t -+000010 point: comment=block hier=top.t +-000000 point: type=line comment=block hier=top.t ++000010 point: type=line comment=block hier=top.t //=== // Task and complicated %000001 if (cyc==3) begin --000001 point: comment=elsif hier=top.t +-000001 point: type=line comment=elsif hier=top.t %000001 toggle <= '1; --000001 point: comment=elsif hier=top.t +-000001 point: type=line comment=elsif hier=top.t end %000001 else if (cyc==5) begin --000001 point: comment=elsif hier=top.t +-000001 point: type=line comment=elsif hier=top.t `ifdef VERILATOR %000001 $c("this->call_task();"); --000001 point: comment=elsif hier=top.t +-000001 point: type=line comment=elsif hier=top.t `else call_task(); `endif end %000007 else if (cyc==10) begin --000001 point: comment=if hier=top.t --000007 point: comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000007 point: type=branch comment=else hier=top.t %000001 $write("*-* All Finished *-*\n"); --000001 point: comment=if hier=top.t +-000001 point: type=branch comment=if hier=top.t %000001 $finish; --000001 point: comment=if hier=top.t +-000001 point: type=branch comment=if hier=top.t end end end %000001 task call_task; --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t /* verilator public */ %000001 t1.center_task(1'b1); --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t endtask endmodule @@ -197,16 +197,16 @@ input clk; input toggle; 000020 always @ (posedge clk) begin -+000020 point: comment=block hier=top.t.a* ++000020 point: type=line comment=block hier=top.t.a* ~000018 if (toggle) begin // CHECK_COVER(0,"top.t.a*",18) --000002 point: comment=if hier=top.t.a* -+000018 point: comment=else hier=top.t.a* +-000002 point: type=branch comment=if hier=top.t.a* ++000018 point: type=branch comment=else hier=top.t.a* %000002 $write(""); --000002 point: comment=if hier=top.t.a* +-000002 point: type=branch comment=if hier=top.t.a* // t.a1 and t.a2 collapse to a count of 2 end 000018 if (toggle) begin // *** t_cover_line.vlt turns this off -+000018 point: comment=else hier=top.t.a* ++000018 point: type=line comment=else hier=top.t.a* $write(""); // CHECK_COVER_MISSING(0) // This doesn't even get added `ifdef ATTRIBUTE @@ -226,25 +226,25 @@ /* verilator public_module */ 000020 always @ (posedge clk) begin -+000020 point: comment=block hier=top.t.b* ++000020 point: type=line comment=block hier=top.t.b* 000020 $write(""); // Always covered -+000020 point: comment=block hier=top.t.b* ++000020 point: type=line comment=block hier=top.t.b* ~000020 if (0) begin // CHECK_COVER(0,"top.t.b*",0) --000000 point: comment=if hier=top.t.b* -+000020 point: comment=else hier=top.t.b* +-000000 point: type=branch comment=if hier=top.t.b* ++000020 point: type=branch comment=else hier=top.t.b* // Make sure that we don't optimize away zero buckets %000000 $write(""); --000000 point: comment=if hier=top.t.b* +-000000 point: type=branch comment=if hier=top.t.b* end ~000018 if (toggle) begin // CHECK_COVER(0,"top.t.b*",2) --000002 point: comment=if hier=top.t.b* -+000018 point: comment=else hier=top.t.b* +-000002 point: type=branch comment=if hier=top.t.b* ++000018 point: type=branch comment=else hier=top.t.b* // t.b1 and t.b2 collapse to a count of 2 %000002 $write(""); --000002 point: comment=if hier=top.t.b* +-000002 point: type=branch comment=if hier=top.t.b* end 000018 if (toggle) begin : block -+000018 point: comment=else hier=top.t.b* ++000018 point: type=line comment=else hier=top.t.b* // This doesn't `ifdef ATTRIBUTE // verilator coverage_block_off @@ -259,32 +259,32 @@ class Cls; bit m_toggle; 000011 function new(bit toggle); -+000011 point: comment=block hier=top.$unit::Cls__Vclpkg ++000011 point: type=line comment=block hier=top.$unit::Cls__Vclpkg 000011 m_toggle = toggle; -+000011 point: comment=block hier=top.$unit::Cls__Vclpkg ++000011 point: type=line comment=block hier=top.$unit::Cls__Vclpkg ~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) -+000011 point: comment=if hier=top.$unit::Cls__Vclpkg --000000 point: comment=else hier=top.$unit::Cls__Vclpkg ++000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg +-000000 point: type=branch comment=else hier=top.$unit::Cls__Vclpkg 000011 $write(""); -+000011 point: comment=if hier=top.$unit::Cls__Vclpkg ++000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg end endfunction 000011 static function void fstatic(bit toggle); -+000011 point: comment=block hier=top.$unit::Cls__Vclpkg ++000011 point: type=line comment=block hier=top.$unit::Cls__Vclpkg ~000011 if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) -+000011 point: comment=if hier=top.$unit::Cls__Vclpkg --000000 point: comment=else hier=top.$unit::Cls__Vclpkg ++000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg +-000000 point: type=branch comment=else hier=top.$unit::Cls__Vclpkg 000011 $write(""); -+000011 point: comment=if hier=top.$unit::Cls__Vclpkg ++000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg end endfunction 000011 function void fauto(); -+000011 point: comment=block hier=top.$unit::Cls__Vclpkg ++000011 point: type=line comment=block hier=top.$unit::Cls__Vclpkg ~000011 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",11) -+000011 point: comment=if hier=top.$unit::Cls__Vclpkg --000000 point: comment=else hier=top.$unit::Cls__Vclpkg ++000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg +-000000 point: type=branch comment=else hier=top.$unit::Cls__Vclpkg 000011 $write(""); -+000011 point: comment=if hier=top.$unit::Cls__Vclpkg ++000011 point: type=branch comment=if hier=top.$unit::Cls__Vclpkg end endfunction endclass @@ -299,38 +299,39 @@ /* verilator public_module */ 000010 always @ (posedge clk) begin -+000010 point: comment=block hier=top.t.t1 ++000010 point: type=line comment=block hier=top.t.t1 000010 center_task(1'b0); -+000010 point: comment=block hier=top.t.t1 ++000010 point: type=line comment=block hier=top.t.t1 end 000011 task automatic center_task; -+000011 point: comment=block hier=top.t.t1 ++000011 point: type=line comment=block hier=top.t.t1 input external; 000011 begin -+000011 point: comment=block hier=top.t.t1 ++000011 point: type=line comment=block hier=top.t.t1 ~000010 if (toggle) begin // CHECK_COVER(0,"top.t.t1",1) --000001 point: comment=if hier=top.t.t1 -+000010 point: comment=else hier=top.t.t1 +-000001 point: type=branch comment=if hier=top.t.t1 ++000010 point: type=branch comment=else hier=top.t.t1 %000001 $write(""); --000001 point: comment=if hier=top.t.t1 +-000001 point: type=branch comment=if hier=top.t.t1 end ~000010 if (external) begin // CHECK_COVER(0,"top.t.t1",1) --000001 point: comment=if hier=top.t.t1 -+000010 point: comment=else hier=top.t.t1 +-000001 point: type=branch comment=if hier=top.t.t1 ++000010 point: type=branch comment=else hier=top.t.t1 %000001 $write("[%0t] Got external pulse\n", $time); --000001 point: comment=if hier=top.t.t1 +-000001 point: type=branch comment=if hier=top.t.t1 end end 000011 begin -+000011 point: comment=block hier=top.t.t1 - Cls c; ++000011 point: type=line comment=block hier=top.t.t1 + 000011 Cls c; ++000011 point: type=line comment=block hier=top.t.t1 000011 c = new(1'b1); -+000011 point: comment=block hier=top.t.t1 ++000011 point: type=line comment=block hier=top.t.t1 000011 c.fauto(); -+000011 point: comment=block hier=top.t.t1 ++000011 point: type=line comment=block hier=top.t.t1 000011 Cls::fstatic(1'b1); -+000011 point: comment=block hier=top.t.t1 ++000011 point: type=line comment=block hier=top.t.t1 end endtask endmodule @@ -351,16 +352,16 @@ end // verilator coverage_on 000010 always @ (posedge clk) begin -+000010 point: comment=block hier=top.t.o1 ++000010 point: type=line comment=block hier=top.t.o1 %000009 if (toggle) begin --000001 point: comment=if hier=top.t.o1 --000009 point: comment=else hier=top.t.o1 +-000001 point: type=branch comment=if hier=top.t.o1 +-000009 point: type=branch comment=else hier=top.t.o1 // because under coverage_module_off %000001 $write(""); --000001 point: comment=if hier=top.t.o1 +-000001 point: type=branch comment=if hier=top.t.o1 %000001 if (0) ; // CHECK_COVER(0,"top.t.o1",1) --000000 point: comment=if hier=top.t.o1 --000001 point: comment=else hier=top.t.o1 +-000000 point: type=branch comment=if hier=top.t.o1 +-000001 point: type=branch comment=else hier=top.t.o1 end end endmodule @@ -370,28 +371,28 @@ int decoded; 000010 always @ (posedge clk) begin -+000010 point: comment=block hier=top.t.tab1 ++000010 point: type=line comment=block hier=top.t.tab1 000010 case (cyc4) -+000010 point: comment=block hier=top.t.tab1 ++000010 point: type=line comment=block hier=top.t.tab1 %000001 1: decoded = 10; --000001 point: comment=case hier=top.t.tab1 +-000001 point: type=line comment=case hier=top.t.tab1 %000001 2: decoded = 20; --000001 point: comment=case hier=top.t.tab1 +-000001 point: type=line comment=case hier=top.t.tab1 %000001 3: decoded = 30; --000001 point: comment=case hier=top.t.tab1 +-000001 point: type=line comment=case hier=top.t.tab1 %000001 4: decoded = 40; --000001 point: comment=case hier=top.t.tab1 +-000001 point: type=line comment=case hier=top.t.tab1 %000001 5: decoded = 50; --000001 point: comment=case hier=top.t.tab1 +-000001 point: type=line comment=case hier=top.t.tab1 %000005 default: decoded = 0; --000005 point: comment=case hier=top.t.tab1 +-000005 point: type=line comment=case hier=top.t.tab1 endcase end 000010 always @ (posedge clk) begin -+000010 point: comment=block hier=top.t.tab1 ++000010 point: type=line comment=block hier=top.t.tab1 000010 cyc4 <= cyc4 + 1; -+000010 point: comment=block hier=top.t.tab1 ++000010 point: type=line comment=block hier=top.t.tab1 end endmodule @@ -402,35 +403,35 @@ // seems safer for functions used both at elaboration time and not - but may // revisit this. %000000 function automatic int param_func(int i); --000000 point: comment=block hier=top.t.par1 +-000000 point: type=line comment=block hier=top.t.par1 %000000 if (i == 0) begin --000000 point: comment=if hier=top.t.par1 --000000 point: comment=else hier=top.t.par1 +-000000 point: type=branch comment=if hier=top.t.par1 +-000000 point: type=branch comment=else hier=top.t.par1 %000000 i = 99; // Uncovered --000000 point: comment=if hier=top.t.par1 +-000000 point: type=branch comment=if hier=top.t.par1 end %000000 else begin --000000 point: comment=else hier=top.t.par1 +-000000 point: type=branch comment=else hier=top.t.par1 %000000 i = i + 1; --000000 point: comment=else hier=top.t.par1 +-000000 point: type=branch comment=else hier=top.t.par1 end %000000 return i; --000000 point: comment=block hier=top.t.par1 +-000000 point: type=line comment=block hier=top.t.par1 endfunction endmodule package my_pkg; %000001 int x = 1 ? 1 : 0; --000001 point: comment=block hier=top.my_pkg +-000001 point: type=line comment=block hier=top.my_pkg endpackage %000001 class Getter1; --000001 point: comment=block hier=top.$unit::Getter1__Vclpkg +-000001 point: type=line comment=block hier=top.$unit::Getter1__Vclpkg 000020 function int get_1; -+000020 point: comment=block hier=top.$unit::Getter1__Vclpkg ++000020 point: type=line comment=block hier=top.$unit::Getter1__Vclpkg 000020 return 1; -+000020 point: comment=block hier=top.$unit::Getter1__Vclpkg ++000020 point: type=line comment=block hier=top.$unit::Getter1__Vclpkg endfunction endclass @@ -440,7 +441,7 @@ typedef logic [7:0] arr_t[1:0]; arr_t data[1:0]; %000001 Getter1 getter1 = new; --000001 point: comment=block hier=top.t.cond1 +-000001 point: type=line comment=block hier=top.t.cond1 string s; struct packed { @@ -449,108 +450,109 @@ } pstruct; 000021 function logic func_side_effect; -+000021 point: comment=block hier=top.t.cond1 ++000021 point: type=line comment=block hier=top.t.cond1 000021 $display("SIDE EFFECT"); -+000021 point: comment=block hier=top.t.cond1 ++000021 point: type=line comment=block hier=top.t.cond1 000021 return 1; -+000021 point: comment=block hier=top.t.cond1 ++000021 point: type=line comment=block hier=top.t.cond1 endfunction 000010 function arr_t get_arr; -+000010 point: comment=block hier=top.t.cond1 - arr_t arr; ++000010 point: type=line comment=block hier=top.t.cond1 + 000010 arr_t arr; ++000010 point: type=line comment=block hier=top.t.cond1 000010 return arr; -+000010 point: comment=block hier=top.t.cond1 ++000010 point: type=line comment=block hier=top.t.cond1 endfunction ~000031 assign a = (cyc == 0) ? clk : 1'bz; --000000 point: comment=cond_then hier=top.t.cond1 -+000031 point: comment=cond_else hier=top.t.cond1 +-000000 point: type=branch comment=cond_then hier=top.t.cond1 ++000031 point: type=branch comment=cond_else hier=top.t.cond1 ~000028 assign b = (cyc == 1) ? clk : 0; --000003 point: comment=cond_then hier=top.t.cond1 -+000028 point: comment=cond_else hier=top.t.cond1 +-000003 point: type=branch comment=cond_then hier=top.t.cond1 ++000028 point: type=branch comment=cond_else hier=top.t.cond1 ~000021 assign c = func_side_effect() ? clk : 0; -+000021 point: comment=cond_then hier=top.t.cond1 --000000 point: comment=cond_else hier=top.t.cond1 ++000021 point: type=branch comment=cond_then hier=top.t.cond1 +-000000 point: type=branch comment=cond_else hier=top.t.cond1 000010 always @(posedge clk) begin -+000010 point: comment=block hier=top.t.cond1 ++000010 point: type=line comment=block hier=top.t.cond1 ~000010 d = (cyc % 3 == 0) ? 1 : 0; -+000010 point: comment=block hier=top.t.cond1 --000003 point: comment=cond_then hier=top.t.cond1 --000007 point: comment=cond_else hier=top.t.cond1 ++000010 point: type=line comment=block hier=top.t.cond1 +-000003 point: type=branch comment=cond_then hier=top.t.cond1 +-000007 point: type=branch comment=cond_else hier=top.t.cond1 ~000010 s = (getter1.get_1() == 0) ? "abcd" : $sformatf("%d", getter1.get_1()[4:0]); -+000010 point: comment=block hier=top.t.cond1 --000000 point: comment=cond_then hier=top.t.cond1 -+000010 point: comment=cond_else hier=top.t.cond1 ++000010 point: type=line comment=block hier=top.t.cond1 +-000000 point: type=branch comment=cond_then hier=top.t.cond1 ++000010 point: type=branch comment=cond_else hier=top.t.cond1 end ~000019 assign e = (cyc % 3 == 1) ? (clk ? 1 : 0) : 1; -+000012 point: comment=cond_then hier=top.t.cond1 -+000019 point: comment=cond_else hier=top.t.cond1 --000007 point: comment=cond_then hier=top.t.cond1 --000005 point: comment=cond_else hier=top.t.cond1 ++000012 point: type=branch comment=cond_then hier=top.t.cond1 ++000019 point: type=branch comment=cond_else hier=top.t.cond1 +-000007 point: type=branch comment=cond_then hier=top.t.cond1 +-000005 point: type=branch comment=cond_else hier=top.t.cond1 // ternary operator in condition shouldn't be included to the coverae ~000011 assign f = (cyc != 0 ? 1 : 0) ? 1 : 0; -+000011 point: comment=cond_then hier=top.t.cond1 --000000 point: comment=cond_else hier=top.t.cond1 ++000011 point: type=branch comment=cond_then hier=top.t.cond1 +-000000 point: type=branch comment=cond_else hier=top.t.cond1 // the same as in index assign tab[clk ? 1 : 0] = 1; assign m = tab[clk ? 3 : 4]; for (genvar i = 0; i < 2; i++) begin 000011 assign g = clk ? 1 : 0; -+000010 point: comment=cond_then hier=top.t.cond1 -+000011 point: comment=cond_else hier=top.t.cond1 ++000010 point: type=branch comment=cond_then hier=top.t.cond1 ++000011 point: type=branch comment=cond_else hier=top.t.cond1 end 000011 always begin -+000011 point: comment=block hier=top.t.cond1 ++000011 point: type=line comment=block hier=top.t.cond1 ~000010 if (cyc == 5) h = cyc > 5 ? 1 : 0; --000000 point: comment=cond_then hier=top.t.cond1 --000001 point: comment=cond_else hier=top.t.cond1 --000001 point: comment=if hier=top.t.cond1 -+000010 point: comment=else hier=top.t.cond1 +-000000 point: type=branch comment=cond_then hier=top.t.cond1 +-000001 point: type=branch comment=cond_else hier=top.t.cond1 +-000001 point: type=branch comment=if hier=top.t.cond1 ++000010 point: type=branch comment=else hier=top.t.cond1 000010 else h = 1; -+000010 point: comment=else hier=top.t.cond1 ++000010 point: type=branch comment=else hier=top.t.cond1 ~000011 data[0] = (cyc == 2) ? '{8'h01, 8'h02} : get_arr(); -+000011 point: comment=block hier=top.t.cond1 --000001 point: comment=cond_then hier=top.t.cond1 -+000010 point: comment=cond_else hier=top.t.cond1 ++000011 point: type=line comment=block hier=top.t.cond1 +-000001 point: type=branch comment=cond_then hier=top.t.cond1 ++000010 point: type=branch comment=cond_else hier=top.t.cond1 // ternary operator in conditions should be skipped 000055 for (int i = 0; (i < 5) ? 1 : 0; i++) begin -+000011 point: comment=block hier=top.t.cond1 -+000055 point: comment=block hier=top.t.cond1 ++000011 point: type=line comment=block hier=top.t.cond1 ++000055 point: type=line comment=block hier=top.t.cond1 000055 k = 1'(i); -+000055 point: comment=block hier=top.t.cond1 ++000055 point: type=line comment=block hier=top.t.cond1 end 000044 for (int i = 0; i < 7; i = (i > 4) ? i + 1 : i + 2) begin -+000011 point: comment=block hier=top.t.cond1 -+000011 point: comment=cond_then hier=top.t.cond1 -+000033 point: comment=cond_else hier=top.t.cond1 -+000044 point: comment=block hier=top.t.cond1 ++000011 point: type=line comment=block hier=top.t.cond1 ++000011 point: type=branch comment=cond_then hier=top.t.cond1 ++000033 point: type=branch comment=cond_else hier=top.t.cond1 ++000044 point: type=line comment=block hier=top.t.cond1 000044 k = 1'(i); -+000044 point: comment=block hier=top.t.cond1 ++000044 point: type=line comment=block hier=top.t.cond1 end ~000011 if (k ? 1 : 0) k = 1; --000000 point: comment=if hier=top.t.cond1 -+000011 point: comment=else hier=top.t.cond1 +-000000 point: type=branch comment=if hier=top.t.cond1 ++000011 point: type=branch comment=else hier=top.t.cond1 000011 else k = 0; -+000011 point: comment=else hier=top.t.cond1 ++000011 point: type=branch comment=else hier=top.t.cond1 end ~000010 assign pstruct.a = cyc == 1 ? 16'd2 : 16'd3; --000001 point: comment=cond_then hier=top.t.cond1 -+000010 point: comment=cond_else hier=top.t.cond1 +-000001 point: type=branch comment=cond_then hier=top.t.cond1 ++000010 point: type=branch comment=cond_else hier=top.t.cond1 assign pstruct.b = 16'd0; 000010 always @(posedge clk) begin -+000010 point: comment=block hier=top.t.cond1 ++000010 point: type=line comment=block hier=top.t.cond1 %000009 if (cyc == 2) $display("%08x", pstruct); --000001 point: comment=if hier=top.t.cond1 --000009 point: comment=else hier=top.t.cond1 +-000001 point: type=branch comment=if hier=top.t.cond1 +-000009 point: type=branch comment=else hier=top.t.cond1 end endmodule diff --git a/test_regress/t/t_cover_line.v b/test_regress/t/t_cover_line.v index 8e8811068..64bf8350a 100644 --- a/test_regress/t/t_cover_line.v +++ b/test_regress/t/t_cover_line.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_cover_line.vlt b/test_regress/t/t_cover_line.vlt index 05502c414..f915e76e5 100644 --- a/test_regress/t/t_cover_line.vlt +++ b/test_regress/t/t_cover_line.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_cover_line_cc.info.out b/test_regress/t/t_cover_line_cc.info.out index edae983eb..6e42f53a9 100644 --- a/test_regress/t/t_cover_line_cc.info.out +++ b/test_regress/t/t_cover_line_cc.info.out @@ -115,6 +115,7 @@ BRDA:225,0,0,1 BRDA:225,0,1,10 DA:226,1 DA:229,11 +DA:230,11 DA:231,11 DA:232,11 DA:233,11 @@ -153,6 +154,7 @@ DA:323,21 DA:324,21 DA:325,21 DA:328,10 +DA:329,10 DA:330,10 DA:333,31 BRDA:333,0,0,0 diff --git a/test_regress/t/t_cover_line_cc.py b/test_regress/t/t_cover_line_cc.py index 5489f8dfc..132c62394 100755 --- a/test_regress/t/t_cover_line_cc.py +++ b/test_regress/t/t_cover_line_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_line_cc_vlt.py b/test_regress/t/t_cover_line_cc_vlt.py index fd97596c4..1d700d328 100755 --- a/test_regress/t/t_cover_line_cc_vlt.py +++ b/test_regress/t/t_cover_line_cc_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_line_expr.out b/test_regress/t/t_cover_line_expr.out index 24db5825f..df46e1e92 100644 --- a/test_regress/t/t_cover_line_expr.out +++ b/test_regress/t/t_cover_line_expr.out @@ -1,12 +1,12 @@ // // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2024 by Wilson Snyder. + // This file ONLY is placed under the Creative Commons Public Domain. + // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 %000001 class cls; --000001 point: comment=block hier=top.$unit::cls__Vclpkg +-000001 point: type=line comment=block hier=top.$unit::cls__Vclpkg rand int x; endclass @@ -19,11 +19,11 @@ integer cyc; %000001 initial cyc=1; --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t logic [63:32] cyc2; %000001 always_comb cyc2 = cyc; --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t integer some_int; integer other_int; @@ -38,404 +38,406 @@ localparam bit ZERO = 1'b0; %000009 function automatic bit invert(bit x); --000009 point: comment=block hier=top.t +-000009 point: type=line comment=block hier=top.t %000009 return ~x; --000009 point: comment=block hier=top.t --000004 point: comment=(x==0) => 1 hier=top.t --000005 point: comment=(x==1) => 0 hier=top.t +-000009 point: type=line comment=block hier=top.t +-000004 point: type=expr comment=(x==0) => 1 hier=top.t +-000005 point: type=expr comment=(x==1) => 0 hier=top.t endfunction %000009 function automatic bit and_oper(bit a, bit b); --000009 point: comment=block hier=top.t +-000009 point: type=line comment=block hier=top.t %000009 return a & b; --000009 point: comment=block hier=top.t --000004 point: comment=(a==0) => 0 hier=top.t --000002 point: comment=(a==1 && b==1) => 1 hier=top.t --000005 point: comment=(b==0) => 0 hier=top.t +-000009 point: type=line comment=block hier=top.t +-000004 point: type=expr comment=(a==0) => 0 hier=top.t +-000002 point: type=expr comment=(a==1 && b==1) => 1 hier=top.t +-000005 point: type=expr comment=(b==0) => 0 hier=top.t endfunction localparam int NUM_INTFS = 4; intf the_intfs [NUM_INTFS-1:0] (); genvar intf_i; %000004 for (intf_i = 0; intf_i < NUM_INTFS; intf_i++) begin --000004 point: comment=block hier=top.t +-000004 point: type=line comment=block hier=top.t %000004 always_comb the_intfs[intf_i].t = cyc[intf_i]; --000004 point: comment=block hier=top.t +-000004 point: type=line comment=block hier=top.t end %000009 always @ (posedge clk) begin --000009 point: comment=block hier=top.t +-000009 point: type=line comment=block hier=top.t %000009 cyc <= cyc + 1; --000009 point: comment=block hier=top.t +-000009 point: type=line comment=block hier=top.t %000005 if ((~cyc[0] && cyc[1]) || (~cyc[2] && cyc[3])) $write(""); --000005 point: comment=else hier=top.t --000002 point: comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t --000004 point: comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t --000002 point: comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t --000003 point: comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t --000002 point: comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000004 point: comment=if hier=top.t +-000005 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=(cyc[0]==0 && cyc[1]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==1 && cyc[3]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[1]==0 && cyc[2]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[1]==0 && cyc[3]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000004 point: type=branch comment=if hier=top.t %000005 if ((~cyc2[32] && cyc2[33]) || (~cyc2[34] && cyc2[35])) $write(""); --000005 point: comment=else hier=top.t --000002 point: comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t --000002 point: comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t --000004 point: comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t --000002 point: comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t --000003 point: comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t --000002 point: comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t --000004 point: comment=if hier=top.t +-000005 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=(cyc2[32]==0 && cyc2[33]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc2[32]==1 && cyc2[34]==1) => 0 hier=top.t +-000004 point: type=expr comment=(cyc2[32]==1 && cyc2[35]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc2[33]==0 && cyc2[34]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc2[33]==0 && cyc2[35]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc2[34]==0 && cyc2[35]==1) => 1 hier=top.t +-000004 point: type=branch comment=if hier=top.t %000005 if ((~the_intfs[0].t && the_intfs[1].t) || (~the_intfs[2].t && the_intfs[3].t)) $write(""); --000005 point: comment=else hier=top.t --000002 point: comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t --000002 point: comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t --000004 point: comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t --000002 point: comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t --000003 point: comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t --000002 point: comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t --000004 point: comment=if hier=top.t +-000005 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=(the_intfs[0].t==0 && the_intfs[1].t==1) => 1 hier=top.t +-000002 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[2].t==1) => 0 hier=top.t +-000004 point: type=expr comment=(the_intfs[0].t==1 && the_intfs[3].t==0) => 0 hier=top.t +-000002 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[2].t==1) => 0 hier=top.t +-000003 point: type=expr comment=(the_intfs[1].t==0 && the_intfs[3].t==0) => 0 hier=top.t +-000002 point: type=expr comment=(the_intfs[2].t==0 && the_intfs[3].t==1) => 1 hier=top.t +-000004 point: type=branch comment=if hier=top.t %000005 if ((~t1 && t2) || (~t3 && t4)) $write(""); --000005 point: comment=else hier=top.t --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t --000004 point: comment=if hier=top.t +-000005 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t +-000004 point: type=branch comment=if hier=top.t %000007 if (t3 && (t1 == t2)) $write(""); --000007 point: comment=else hier=top.t --000005 point: comment=((t1 == t2)==0) => 0 hier=top.t --000005 point: comment=(t3==0) => 0 hier=top.t --000002 point: comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t --000002 point: comment=if hier=top.t +-000007 point: type=branch comment=else hier=top.t +-000005 point: type=expr comment=((t1 == t2)==0) => 0 hier=top.t +-000005 point: type=expr comment=(t3==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==1 && (t1 == t2)==1) => 1 hier=top.t +-000002 point: type=branch comment=if hier=top.t %000007 if (123 == (124 - 32'(t1 || t2))) $write(""); --000002 point: comment=else hier=top.t --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000005 point: comment=(t1==1) => 1 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t --000007 point: comment=if hier=top.t +-000002 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==1) => 1 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t +-000007 point: type=branch comment=if hier=top.t %000009 some_int <= (t2 || t3) ? 345 : 567; --000009 point: comment=block hier=top.t --000003 point: comment=(t2==0 && t3==0) => 0 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t --000004 point: comment=(t3==1) => 1 hier=top.t --000006 point: comment=cond_then hier=top.t --000003 point: comment=cond_else hier=top.t +-000009 point: type=line comment=block hier=top.t +-000003 point: type=expr comment=(t2==0 && t3==0) => 0 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t +-000004 point: type=expr comment=(t3==1) => 1 hier=top.t +-000006 point: type=branch comment=cond_then hier=top.t +-000003 point: type=branch comment=cond_else hier=top.t %000009 some_bool <= t1 && t2; --000009 point: comment=block hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t +-000009 point: type=line comment=block hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t %000007 if (t1 & t2) $write(""); --000007 point: comment=else hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=if hier=top.t +-000007 point: type=branch comment=else hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000002 point: type=branch comment=if hier=top.t %000005 if ((!t1 && t2) | (~t3 && t4)) $write(""); --000005 point: comment=else hier=top.t --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t --000004 point: comment=if hier=top.t +-000005 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t +-000004 point: type=branch comment=if hier=top.t %000005 if (t1 ^ t2) $write(""); --000004 point: comment=else hier=top.t --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t --000005 point: comment=if hier=top.t +-000004 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t +-000005 point: type=branch comment=if hier=top.t %000007 if (~(t1 & t2)) $write(""); --000002 point: comment=else hier=top.t --000004 point: comment=(t1==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 0 hier=top.t --000005 point: comment=(t2==0) => 1 hier=top.t --000007 point: comment=if hier=top.t +-000002 point: type=branch comment=else hier=top.t +-000004 point: type=expr comment=(t1==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 1 hier=top.t +-000007 point: type=branch comment=if hier=top.t %000006 if (t1 -> t2) $write(""); --000003 point: comment=else hier=top.t --000004 point: comment=(t1==0) => 1 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t --000004 point: comment=(t2==1) => 1 hier=top.t --000006 point: comment=if hier=top.t +-000003 point: type=branch comment=else hier=top.t +-000004 point: type=expr comment=(t1==0) => 1 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t +-000004 point: type=expr comment=(t2==1) => 1 hier=top.t +-000006 point: type=branch comment=if hier=top.t %000005 if (t1 <-> t2) $write(""); --000005 point: comment=else hier=top.t --000002 point: comment=(t1==0 && t2==0) => 1 hier=top.t --000002 point: comment=(t1==0 && t2==1) => 0 hier=top.t --000003 point: comment=(t1==1 && t2==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000004 point: comment=if hier=top.t +-000005 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 0 hier=top.t +-000003 point: type=expr comment=(t1==1 && t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000004 point: type=branch comment=if hier=top.t %000008 if (&cyc[2:0]) $write(""); --000008 point: comment=else hier=top.t --000004 point: comment=(cyc[2:0][0]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t --000005 point: comment=(cyc[2:0][1]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=if hier=top.t +-000008 point: type=branch comment=else hier=top.t +-000004 point: type=expr comment=(cyc[2:0][0]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][1]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][2]==0) => 0 hier=top.t +-000001 point: type=branch comment=if hier=top.t %000009 if (&cyc[3:2]) $write(""); --000009 point: comment=else hier=top.t --000005 point: comment=(cyc[3:2][0]==0) => 0 hier=top.t --000000 point: comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t --000007 point: comment=(cyc[3:2][1]==0) => 0 hier=top.t --000000 point: comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t +-000005 point: type=expr comment=(cyc[3:2][0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[3:2][0]==1 && cyc[3:2][1]==1) => 1 hier=top.t +-000007 point: type=expr comment=(cyc[3:2][1]==0) => 0 hier=top.t +-000000 point: type=branch comment=if hier=top.t %000008 if (|cyc[2:0]) $write(""); --000001 point: comment=else hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t --000008 point: comment=if hier=top.t +-000001 point: type=branch comment=else hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t +-000008 point: type=branch comment=if hier=top.t %000005 if (^cyc[2:0]) $write(""); --000004 point: comment=else hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t --000002 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t --000001 point: comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t --000005 point: comment=if hier=top.t +-000004 point: type=branch comment=else hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==0) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==0 && cyc[2:0][2]==1) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==0) => 0 hier=top.t +-000001 point: type=expr comment=(cyc[2:0][0]==1 && cyc[2:0][1]==1 && cyc[2:0][2]==1) => 1 hier=top.t +-000005 point: type=branch comment=if hier=top.t %000009 if (|cyc[2:0] || cyc[3]) $write(""); --000000 point: comment=else hier=top.t --000000 point: comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t --000005 point: comment=(cyc[2:0][0]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][1]==1) => 1 hier=top.t --000004 point: comment=(cyc[2:0][2]==1) => 1 hier=top.t --000002 point: comment=(cyc[3]==1) => 1 hier=top.t --000009 point: comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t +-000000 point: type=expr comment=(cyc[2:0][0]==0 && cyc[2:0][1]==0 && cyc[2:0][2]==0 && cyc[3]==0) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[2:0][0]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][1]==1) => 1 hier=top.t +-000004 point: type=expr comment=(cyc[2:0][2]==1) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[3]==1) => 1 hier=top.t +-000009 point: type=branch comment=if hier=top.t %000007 if (t1 & t2 & 1'b1) $write(""); --000007 point: comment=else hier=top.t --000000 point: comment=(1'h1==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=if hier=top.t +-000007 point: type=branch comment=else hier=top.t +-000000 point: type=expr comment=(1'h1==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1 && 1'h1==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000002 point: type=branch comment=if hier=top.t %000009 if (t1 & t2 & 1'b0) $write(""); --000009 point: comment=else hier=top.t --000009 point: comment=(1'h0==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t --000000 point: comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t +-000009 point: type=expr comment=(1'h0==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && 1'h0==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000000 point: type=branch comment=if hier=top.t %000007 if (t1 & t2 & ONE) $write(""); --000007 point: comment=else hier=top.t --000000 point: comment=(ONE==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=if hier=top.t +-000007 point: type=branch comment=else hier=top.t +-000000 point: type=expr comment=(ONE==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1 && ONE==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000002 point: type=branch comment=if hier=top.t %000009 if (t1 & t2 & ZERO) $write(""); --000009 point: comment=else hier=top.t --000009 point: comment=(ZERO==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t --000000 point: comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t +-000009 point: type=expr comment=(ZERO==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && ZERO==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000000 point: type=branch comment=if hier=top.t %000005 if (t1 && t2) begin --000004 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=elsif hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000002 point: type=line comment=elsif hier=top.t %000002 $write(""); --000002 point: comment=elsif hier=top.t +-000002 point: type=line comment=elsif hier=top.t %000005 end else if (t1 || t2) begin --000005 point: comment=if hier=top.t --000002 point: comment=else hier=top.t --000002 point: comment=(t1==0 && t2==0) => 0 hier=top.t --000003 point: comment=(t1==1) => 1 hier=top.t --000002 point: comment=(t2==1) => 1 hier=top.t +-000005 point: type=branch comment=if hier=top.t +-000002 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==0) => 0 hier=top.t +-000003 point: type=expr comment=(t1==1) => 1 hier=top.t +-000002 point: type=expr comment=(t2==1) => 1 hier=top.t %000005 $write(""); --000005 point: comment=if hier=top.t +-000005 point: type=branch comment=if hier=top.t end %000007 if (invert(t1) && t2) $write(""); --000007 point: comment=else hier=top.t --000005 point: comment=(invert(t1)==0) => 0 hier=top.t --000002 point: comment=(invert(t1)==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=if hier=top.t +-000007 point: type=branch comment=else hier=top.t +-000005 point: type=expr comment=(invert(t1)==0) => 0 hier=top.t +-000002 point: type=expr comment=(invert(t1)==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000002 point: type=branch comment=if hier=top.t %000007 if (and_oper(t1, t2)) $write(""); --000007 point: comment=else hier=top.t --000002 point: comment=if hier=top.t +-000007 point: type=branch comment=else hier=top.t +-000002 point: type=branch comment=if hier=top.t %000007 if (t2 && t3) begin --000007 point: comment=else hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=(t2==1 && t3==1) => 1 hier=top.t --000005 point: comment=(t3==0) => 0 hier=top.t --000002 point: comment=if hier=top.t +-000007 point: type=branch comment=else hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==1 && t3==1) => 1 hier=top.t +-000005 point: type=expr comment=(t3==0) => 0 hier=top.t +-000002 point: type=branch comment=if hier=top.t %000001 if (t1 && t2) $write(""); --000001 point: comment=if hier=top.t --000001 point: comment=else hier=top.t --000001 point: comment=(t1==0) => 0 hier=top.t --000001 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000000 point: comment=(t2==0) => 0 hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000001 point: type=branch comment=else hier=top.t +-000001 point: type=expr comment=(t1==0) => 0 hier=top.t +-000001 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000000 point: type=expr comment=(t2==0) => 0 hier=top.t end %000009 if (0 == 1) begin --000009 point: comment=else hier=top.t --000000 point: comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t +-000000 point: type=branch comment=if hier=top.t %000000 for (int loop_var = 0; loop_var < 1; loop_var++) begin --000000 point: comment=if hier=top.t --000000 point: comment=block hier=top.t +-000000 point: type=branch comment=if hier=top.t +-000000 point: type=line comment=block hier=top.t %000000 if (cyc[loop_var] && t2) $write(""); --000000 point: comment=if hier=top.t --000000 point: comment=else hier=top.t --000000 point: comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t --000000 point: comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t --000000 point: comment=(t2==0) => 0 hier=top.t +-000000 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t +-000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[loop_var[4:0]+:1]==1 && t2==1) => 1 hier=top.t +-000000 point: type=expr comment=(t2==0) => 0 hier=top.t end end // stop at the first layer even if there's more to find %000007 if ((cyc[3+32'(t1 && t2)+:2] == cyc[5+32'(t3 || t4)+:2]) || cyc[31]) $write(""); --000002 point: comment=else hier=top.t --000002 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t --000007 point: comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t --000000 point: comment=(cyc[31]==1) => 1 hier=top.t --000007 point: comment=if hier=top.t +-000002 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==0 && cyc[31]==0) => 0 hier=top.t +-000007 point: type=expr comment=((cyc[(32'sh3 + (t1 && t2))[4:0]+:2] == cyc[(32'sh5 + (t3 || t4))[4:0]+:2])==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[31]==1) => 1 hier=top.t +-000007 point: type=branch comment=if hier=top.t // impossible branches and redundant terms %000008 if ((t1 && t2) && ~(t1 && t3) && (t1 || t4)) $write(""); --000008 point: comment=else hier=top.t --000003 point: comment=(t1==0 && t4==0) => 0 hier=top.t --000004 point: comment=(t1==0) => 0 hier=top.t --000000 point: comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t --000001 point: comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t --000001 point: comment=if hier=top.t +-000008 point: type=branch comment=else hier=top.t +-000003 point: type=expr comment=(t1==0 && t4==0) => 0 hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000000 point: type=expr comment=(t1==1 && t2==1 && t3==0 && t4==1) => 1 hier=top.t +-000001 point: type=expr comment=(t1==1 && t2==1 && t3==0) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000001 point: type=branch comment=if hier=top.t %000008 if ((cyc[0] && cyc[1]) && ~(cyc[0] && cyc[2]) && (cyc[0] || cyc[3])) $write(""); --000008 point: comment=else hier=top.t --000003 point: comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t --000001 point: comment=if hier=top.t +-000008 point: type=branch comment=else hier=top.t +-000003 point: type=expr comment=(cyc[0]==0 && cyc[3]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0) => 1 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[2]==1) => 0 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t +-000001 point: type=branch comment=if hier=top.t // demonstrate current limitations of term matching scheme %000008 if ((cyc[0] && cyc[1]) && ~(cyc[1-1] && cyc[2]) && (cyc[2-2] || cyc[3])) $write(""); --000008 point: comment=else hier=top.t --000002 point: comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t --000003 point: comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t --000001 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t --000000 point: comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t --000001 point: comment=if hier=top.t +-000008 point: type=branch comment=else hier=top.t +-000002 point: type=expr comment=(cyc[(32'sh1 - 32'sh1)[4:0]+:1]==1 && cyc[2]==1) => 0 hier=top.t +-000003 point: type=expr comment=(cyc[(32'sh2 - 32'sh2)[4:0]+:1]==0 && cyc[3]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[(32'sh1 - 32'sh1)[4:0]+:1]==0 && cyc[3]==1) => 1 hier=top.t +-000001 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[(32'sh2 - 32'sh2)[4:0]+:1]==1) => 1 hier=top.t +-000000 point: type=expr comment=(cyc[0]==1 && cyc[1]==1 && cyc[2]==0 && cyc[3]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t +-000001 point: type=branch comment=if hier=top.t //verilator coverage_off if (t1 && t2) $write(""); //verilator coverage_on %000005 if ((~t1 && t2) --000005 point: comment=else hier=top.t --000004 point: comment=if hier=top.t +-000005 point: type=branch comment=else hier=top.t +-000004 point: type=branch comment=if hier=top.t %000004 || --000002 point: comment=(t1==0 && t2==1) => 1 hier=top.t --000002 point: comment=(t1==1 && t3==1) => 0 hier=top.t --000004 point: comment=(t1==1 && t4==0) => 0 hier=top.t --000002 point: comment=(t2==0 && t3==1) => 0 hier=top.t --000003 point: comment=(t2==0 && t4==0) => 0 hier=top.t --000002 point: comment=(t3==0 && t4==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==0 && t2==1) => 1 hier=top.t +-000002 point: type=expr comment=(t1==1 && t3==1) => 0 hier=top.t +-000004 point: type=expr comment=(t1==1 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t2==0 && t3==1) => 0 hier=top.t +-000003 point: type=expr comment=(t2==0 && t4==0) => 0 hier=top.t +-000002 point: type=expr comment=(t3==0 && t4==1) => 1 hier=top.t %000004 (~t3 && t4)) $write(""); --000004 point: comment=if hier=top.t +-000004 point: type=branch comment=if hier=top.t // intentionally testing wonkified expression terms %000007 if ( --000007 point: comment=else hier=top.t --000002 point: comment=if hier=top.t +-000007 point: type=branch comment=else hier=top.t +-000002 point: type=branch comment=if hier=top.t cyc[ 0 %000005 ] & --000004 point: comment=(cyc[0]==0) => 0 hier=top.t --000002 point: comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t --000005 point: comment=(cyc[1]==0) => 0 hier=top.t +-000004 point: type=expr comment=(cyc[0]==0) => 0 hier=top.t +-000002 point: type=expr comment=(cyc[0]==1 && cyc[1]==1) => 1 hier=top.t +-000005 point: type=expr comment=(cyc[1]==0) => 0 hier=top.t cyc %000002 [1]) $write(""); --000002 point: comment=if hier=top.t +-000002 point: type=branch comment=if hier=top.t // for now each ternary condition is considered in isolation %000009 other_int <= t1 ? t2 ? 1 : 2 : 3; --000004 point: comment=(t1==0) => 0 hier=top.t --000005 point: comment=(t1==1) => 1 hier=top.t --000005 point: comment=cond_then hier=top.t --000004 point: comment=cond_else hier=top.t --000002 point: comment=cond_then hier=top.t --000003 point: comment=cond_else hier=top.t --000009 point: comment=block hier=top.t +-000004 point: type=expr comment=(t1==0) => 0 hier=top.t +-000005 point: type=expr comment=(t1==1) => 1 hier=top.t +-000005 point: type=branch comment=cond_then hier=top.t +-000004 point: type=branch comment=cond_else hier=top.t +-000002 point: type=branch comment=cond_then hier=top.t +-000003 point: type=branch comment=cond_else hier=top.t +-000009 point: type=line comment=block hier=top.t // no expression coverage for multi-bit expressions %000009 if ((cyc[1:0] & cyc[3:2]) == 2'b11) $write(""); --000009 point: comment=else hier=top.t --000000 point: comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t +-000000 point: type=branch comment=if hier=top.t // truth table is too large %000005 if (^cyc[6:0]) $write(""); --000004 point: comment=else hier=top.t --000005 point: comment=if hier=top.t +-000004 point: type=branch comment=else hier=top.t +-000005 point: type=branch comment=if hier=top.t // this one is too big even for t_cover_expr_max %000005 if (^cyc) $write(""); --000004 point: comment=else hier=top.t --000005 point: comment=if hier=top.t +-000004 point: type=branch comment=else hier=top.t +-000005 point: type=branch comment=if hier=top.t %000008 if (cyc==9) begin --000008 point: comment=else hier=top.t --000001 point: comment=if hier=top.t +-000008 point: type=branch comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t %000001 $write("*-* All Finished *-*\n"); --000001 point: comment=if hier=top.t +-000001 point: type=branch comment=if hier=top.t %000001 $finish; --000001 point: comment=if hier=top.t +-000001 point: type=branch comment=if hier=top.t end end 000010 always_comb begin -+000010 point: comment=block hier=top.t ++000010 point: type=line comment=block hier=top.t %000008 if (t1 && t2) $write(""); --000008 point: comment=else hier=top.t --000005 point: comment=(t1==0) => 0 hier=top.t --000002 point: comment=(t1==1 && t2==1) => 1 hier=top.t --000005 point: comment=(t2==0) => 0 hier=top.t --000002 point: comment=if hier=top.t +-000008 point: type=branch comment=else hier=top.t +-000005 point: type=expr comment=(t1==0) => 0 hier=top.t +-000002 point: type=expr comment=(t1==1 && t2==1) => 1 hier=top.t +-000005 point: type=expr comment=(t2==0) => 0 hier=top.t +-000002 point: type=branch comment=if hier=top.t end logic ta, tb, tc; %000001 initial begin --000001 point: comment=block hier=top.t -%000001 cls obj = new; --000001 point: comment=block hier=top.t -%000001 cls null_obj = null; --000001 point: comment=block hier=top.t - int q[5]; - int qv[$]; +-000001 point: type=line comment=block hier=top.t +%000001 automatic cls obj = new; +-000001 point: type=line comment=block hier=top.t +%000001 automatic cls null_obj = null; +-000001 point: type=line comment=block hier=top.t +%000001 automatic int q[5]; +-000001 point: type=line comment=block hier=top.t +%000001 automatic int qv[$]; +-000001 point: type=line comment=block hier=top.t %000001 q = '{1, 2, 2, 4, 3}; --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t // lambas not handled // NB: there is a bug w/ tracing find_first (maybe lambdas in general?) // tracing_off does not work around the bug %000001 qv = q.find_first with (item[0] & item[1]); --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t %000001 ta = '1; --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t %000001 tb = '0; --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t %000001 tc = '0; --000001 point: comment=block hier=top.t +-000001 point: type=line comment=block hier=top.t %000003 while (ta || tb || tc) begin --000001 point: comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t --000000 point: comment=(ta==1) => 1 hier=top.t --000000 point: comment=(tb==1) => 1 hier=top.t --000000 point: comment=(tc==1) => 1 hier=top.t --000003 point: comment=block hier=top.t +-000001 point: type=expr comment=(ta==0 && tb==0 && tc==0) => 0 hier=top.t +-000000 point: type=expr comment=(ta==1) => 1 hier=top.t +-000000 point: type=expr comment=(tb==1) => 1 hier=top.t +-000000 point: type=expr comment=(tc==1) => 1 hier=top.t +-000003 point: type=line comment=block hier=top.t %000003 tc = tb; --000003 point: comment=block hier=top.t +-000003 point: type=line comment=block hier=top.t %000003 tb = ta; --000003 point: comment=block hier=top.t +-000003 point: type=line comment=block hier=top.t %000003 ta = '0; --000003 point: comment=block hier=top.t +-000003 point: type=line comment=block hier=top.t end %000001 if (!bit'(obj.randomize() with {x < 100;})) $write(""); --000000 point: comment=else hier=top.t --000001 point: comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t %000001 if (null_obj != null && null_obj.x == 5) $write(""); --000001 point: comment=else hier=top.t --000000 point: comment=if hier=top.t +-000001 point: type=branch comment=else hier=top.t +-000000 point: type=branch comment=if hier=top.t end sub the_sub_1 (.p(t1), .q(t2)); @@ -450,7 +452,7 @@ // // Branches which are statically impossible to reach are still reported. // E.g. - // -000000 point: comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t + // -000000 point: type=expr comment=(t1=1 && t2=1 && 1'h0=1) => 1 hier=top.t // These could potentially be pruned, but they currently follow suit for // what branch coverage does. Perhaps a switch should be added to not // count statically impossible things. @@ -463,13 +465,13 @@ ); 000030 always_comb begin -+000030 point: comment=block hier=top.t.the_sub_* ++000030 point: type=line comment=block hier=top.t.the_sub_* ~000028 if (p && q) $write(""); -+000028 point: comment=else hier=top.t.the_sub_* -+000017 point: comment=(p==0) => 0 hier=top.t.the_sub_* --000002 point: comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* -+000019 point: comment=(q==0) => 0 hier=top.t.the_sub_* --000002 point: comment=if hier=top.t.the_sub_* ++000028 point: type=branch comment=else hier=top.t.the_sub_* ++000017 point: type=expr comment=(p==0) => 0 hier=top.t.the_sub_* +-000002 point: type=expr comment=(p==1 && q==1) => 1 hier=top.t.the_sub_* ++000019 point: type=expr comment=(q==0) => 0 hier=top.t.the_sub_* +-000002 point: type=branch comment=if hier=top.t.the_sub_* end endmodule diff --git a/test_regress/t/t_cover_line_expr_cc.py b/test_regress/t/t_cover_line_expr_cc.py index 7e7c3b5b4..2139f2018 100755 --- a/test_regress/t/t_cover_line_expr_cc.py +++ b/test_regress/t/t_cover_line_expr_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_line_sc.py b/test_regress/t/t_cover_line_sc.py index ff73bf508..2654687b3 100755 --- a/test_regress/t/t_cover_line_sc.py +++ b/test_regress/t/t_cover_line_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_line_trace.out b/test_regress/t/t_cover_line_trace.out index 42cced2fa..fee3a1c28 100644 --- a/test_regress/t/t_cover_line_trace.out +++ b/test_regress/t/t_cover_line_trace.out @@ -1,227 +1,222 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end - $var wire 1 >! clk $end + $var wire 1 ! clk $end - $var wire 1 = toggle $end - $var wire 32 # vlCoverageLineTrace_t_cover_line__15_block [31:0] $end - $var wire 32 > cyc [31:0] $end - $var wire 32 $ vlCoverageLineTrace_t_cover_line__18_block [31:0] $end - $var wire 8 ? cyc_copy [7:0] $end - $scope module b1 $end - $var wire 1 >! clk $end - $var wire 1 = toggle $end - $var wire 32 2! vlCoverageLineTrace_t_cover_line__164_block [31:0] $end - $var wire 32 3! vlCoverageLineTrace_t_cover_line__166_else [31:0] $end - $var wire 32 T! vlCoverageLineTrace_t_cover_line__166_if [31:0] $end - $var wire 32 4! vlCoverageLineTrace_t_cover_line__170_else [31:0] $end - $var wire 32 5! vlCoverageLineTrace_t_cover_line__170_if [31:0] $end - $var wire 32 6! vlCoverageLineTrace_t_cover_line__174_else [31:0] $end - $upscope $end - $scope module b2 $end - $var wire 1 >! clk $end - $var wire 1 = toggle $end - $var wire 32 7! vlCoverageLineTrace_t_cover_line__164_block [31:0] $end - $var wire 32 8! vlCoverageLineTrace_t_cover_line__166_else [31:0] $end - $var wire 32 U! vlCoverageLineTrace_t_cover_line__166_if [31:0] $end - $var wire 32 9! vlCoverageLineTrace_t_cover_line__170_else [31:0] $end - $var wire 32 :! vlCoverageLineTrace_t_cover_line__170_if [31:0] $end - $var wire 32 ;! vlCoverageLineTrace_t_cover_line__174_else [31:0] $end - $upscope $end - $scope module t1 $end - $var wire 1 >! clk $end - $var wire 1 = toggle $end - $var wire 32 cyc_copy [7:0] $end + $var wire 32 ? vlCoverageLineTrace_t_cover_line__55_block [31:0] $end + $var wire 32 @ vlCoverageLineTrace_t_cover_line__56_else [31:0] $end + $var wire 32 A vlCoverageLineTrace_t_cover_line__56_if [31:0] $end + $var wire 32 B vlCoverageLineTrace_t_cover_line__60_else [31:0] $end + $var wire 32 C vlCoverageLineTrace_t_cover_line__60_if [31:0] $end + $var wire 32 D vlCoverageLineTrace_t_cover_line__61_else [31:0] $end + $var wire 32 E vlCoverageLineTrace_t_cover_line__61_if [31:0] $end + $var wire 32 F vlCoverageLineTrace_t_cover_line__66_else [31:0] $end + $var wire 32 G vlCoverageLineTrace_t_cover_line__66_if [31:0] $end + $var wire 32 H vlCoverageLineTrace_t_cover_line__67_else [31:0] $end + $var wire 32 I vlCoverageLineTrace_t_cover_line__67_if [31:0] $end + $var wire 32 J vlCoverageLineTrace_t_cover_line__73_else [31:0] $end + $var wire 32 K vlCoverageLineTrace_t_cover_line__73_if [31:0] $end + $var wire 32 L vlCoverageLineTrace_t_cover_line__74_else [31:0] $end + $var wire 32 M vlCoverageLineTrace_t_cover_line__74_if [31:0] $end + $var wire 32 N vlCoverageLineTrace_t_cover_line__83_elsif [31:0] $end + $var wire 32 O vlCoverageLineTrace_t_cover_line__87_elsif [31:0] $end + $var wire 32 P vlCoverageLineTrace_t_cover_line__91_else [31:0] $end + $var wire 32 Q vlCoverageLineTrace_t_cover_line__91_if [31:0] $end + $var wire 32 C! vlCoverageLineTrace_t_cover_line__100_block [31:0] $end + $var wire 32 D! vlCoverageLineTrace_t_cover_line__101_block [31:0] $end + $var wire 32 E! vlCoverageLineTrace_t_cover_line__104_block [31:0] $end + $var wire 32 F! vlCoverageLineTrace_t_cover_line__105_block [31:0] $end + $var wire 32 R vlCoverageLineTrace_t_cover_line__107_block [31:0] $end + $var wire 32 S vlCoverageLineTrace_t_cover_line__110_elsif [31:0] $end + $var wire 32 T vlCoverageLineTrace_t_cover_line__113_elsif [31:0] $end + $var wire 32 U vlCoverageLineTrace_t_cover_line__120_else [31:0] $end + $var wire 32 V vlCoverageLineTrace_t_cover_line__120_if [31:0] $end + $var wire 32 =! vlCoverageLineTrace_t_cover_line__127_block [31:0] $end $scope module a1 $end - $var wire 1 >! clk $end - $var wire 1 = toggle $end - $var wire 32 X vlCoverageLineTrace_t_cover_line__140_block [31:0] $end - $var wire 32 Y vlCoverageLineTrace_t_cover_line__141_else [31:0] $end - $var wire 32 Z vlCoverageLineTrace_t_cover_line__141_if [31:0] $end - $var wire 32 [ vlCoverageLineTrace_t_cover_line__145_else [31:0] $end + $var wire 1 ! clk $end - $var wire 1 = toggle $end - $var wire 32 \ vlCoverageLineTrace_t_cover_line__140_block [31:0] $end - $var wire 32 ] vlCoverageLineTrace_t_cover_line__141_else [31:0] $end - $var wire 32 ^ vlCoverageLineTrace_t_cover_line__141_if [31:0] $end - $var wire 32 _ vlCoverageLineTrace_t_cover_line__145_else [31:0] $end + $var wire 1 ! clk $end - $var wire 32 > cyc [31:0] $end - $var wire 1 2 a $end - $var wire 1 3 b $end - $var wire 1 * c $end - $var wire 1 ` d $end - $var wire 1 4 e $end - $var wire 1 a f $end - $var wire 1 + g $end - $var wire 1 b h $end - $var wire 1 c k $end - $var wire 1 I! l $end - $var wire 1 @! m $end - $var wire 6 , tab [5:0] $end - $var wire 8 d data[0][0] [7:0] $end - $var wire 8 e data[0][1] [7:0] $end - $var wire 8 f data[1][0] [7:0] $end - $var wire 8 g data[1][1] [7:0] $end - $var wire 32 % vlCoverageLineTrace_t_cover_line__315_block [31:0] $end - $var wire 32 h pstruct [31:0] $end - $var wire 32 - vlCoverageLineTrace_t_cover_line__323_block [31:0] $end - $var wire 32 i vlCoverageLineTrace_t_cover_line__328_block [31:0] $end - $var wire 8 J! get_arr__Vstatic__arr[0] [7:0] $end - $var wire 8 K! get_arr__Vstatic__arr[1] [7:0] $end - $var wire 32 5 vlCoverageLineTrace_t_cover_line__333_cond_else [31:0] $end - $var wire 32 6 vlCoverageLineTrace_t_cover_line__333_cond_then [31:0] $end - $var wire 32 7 vlCoverageLineTrace_t_cover_line__334_cond_else [31:0] $end - $var wire 32 8 vlCoverageLineTrace_t_cover_line__334_cond_then [31:0] $end - $var wire 32 . vlCoverageLineTrace_t_cover_line__335_cond_else [31:0] $end - $var wire 32 / vlCoverageLineTrace_t_cover_line__335_cond_then [31:0] $end - $var wire 32 j vlCoverageLineTrace_t_cover_line__336_block [31:0] $end - $var wire 32 k vlCoverageLineTrace_t_cover_line__337_cond_else [31:0] $end - $var wire 32 l vlCoverageLineTrace_t_cover_line__337_cond_then [31:0] $end - $var wire 32 m vlCoverageLineTrace_t_cover_line__338_cond_else [31:0] $end - $var wire 32 n vlCoverageLineTrace_t_cover_line__338_cond_then [31:0] $end - $var wire 32 9 vlCoverageLineTrace_t_cover_line__340_cond_else_1 [31:0] $end - $var wire 32 : vlCoverageLineTrace_t_cover_line__340_cond_then_1 [31:0] $end - $var wire 32 ; vlCoverageLineTrace_t_cover_line__340_cond_else [31:0] $end - $var wire 32 < vlCoverageLineTrace_t_cover_line__340_cond_then [31:0] $end - $var wire 32 o vlCoverageLineTrace_t_cover_line__343_cond_else [31:0] $end - $var wire 32 p vlCoverageLineTrace_t_cover_line__343_cond_then [31:0] $end - $var wire 32 L! vlCoverageLineTrace_t_cover_line__349_cond_else [31:0] $end - $var wire 32 0 vlCoverageLineTrace_t_cover_line__349_cond_else_1 [31:0] $end - $var wire 32 M! vlCoverageLineTrace_t_cover_line__349_cond_then [31:0] $end - $var wire 32 1 vlCoverageLineTrace_t_cover_line__349_cond_then_1 [31:0] $end - $var wire 32 & vlCoverageLineTrace_t_cover_line__352_block [31:0] $end - $var wire 32 q vlCoverageLineTrace_t_cover_line__353_else [31:0] $end - $var wire 32 r vlCoverageLineTrace_t_cover_line__353_if [31:0] $end - $var wire 32 s vlCoverageLineTrace_t_cover_line__353_cond_else [31:0] $end - $var wire 32 t vlCoverageLineTrace_t_cover_line__353_cond_then [31:0] $end - $var wire 32 u vlCoverageLineTrace_t_cover_line__356_cond_else [31:0] $end - $var wire 32 v vlCoverageLineTrace_t_cover_line__356_cond_then [31:0] $end - $var wire 32 ' vlCoverageLineTrace_t_cover_line__359_block [31:0] $end - $var wire 32 w vlCoverageLineTrace_t_cover_line__362_block [31:0] $end - $var wire 32 x vlCoverageLineTrace_t_cover_line__362_cond_else [31:0] $end - $var wire 32 y vlCoverageLineTrace_t_cover_line__362_cond_then [31:0] $end - $var wire 32 z vlCoverageLineTrace_t_cover_line__366_else [31:0] $end - $var wire 32 { vlCoverageLineTrace_t_cover_line__366_if [31:0] $end - $var wire 32 | vlCoverageLineTrace_t_cover_line__370_cond_else [31:0] $end - $var wire 32 } vlCoverageLineTrace_t_cover_line__370_cond_then [31:0] $end - $var wire 32 ~ vlCoverageLineTrace_t_cover_line__373_block [31:0] $end - $var wire 32 !! vlCoverageLineTrace_t_cover_line__374_else [31:0] $end - $var wire 32 "! vlCoverageLineTrace_t_cover_line__374_if [31:0] $end - $scope module unnamedblk1 $end - $var wire 32 N! i [31:0] $end - $upscope $end - $scope module unnamedblk2 $end - $var wire 32 #! i [31:0] $end - $upscope $end + $var wire 1 ! m $end + $var wire 6 + tab [5:0] $end + $var wire 8 c data[0][0] [7:0] $end + $var wire 8 d data[0][1] [7:0] $end + $var wire 8 e data[1][0] [7:0] $end + $var wire 8 f data[1][1] [7:0] $end + $var wire 32 $ vlCoverageLineTrace_t_cover_line__315_block [31:0] $end + $var wire 32 g pstruct [31:0] $end + $var wire 32 , vlCoverageLineTrace_t_cover_line__323_block [31:0] $end + $var wire 32 h vlCoverageLineTrace_t_cover_line__328_block [31:0] $end + $var wire 8 H! get_arr__Vstatic__arr[0] [7:0] $end + $var wire 8 I! get_arr__Vstatic__arr[1] [7:0] $end + $var wire 32 4 vlCoverageLineTrace_t_cover_line__333_cond_else [31:0] $end + $var wire 32 5 vlCoverageLineTrace_t_cover_line__333_cond_then [31:0] $end + $var wire 32 6 vlCoverageLineTrace_t_cover_line__334_cond_else [31:0] $end + $var wire 32 7 vlCoverageLineTrace_t_cover_line__334_cond_then [31:0] $end + $var wire 32 - vlCoverageLineTrace_t_cover_line__335_cond_else [31:0] $end + $var wire 32 . vlCoverageLineTrace_t_cover_line__335_cond_then [31:0] $end + $var wire 32 i vlCoverageLineTrace_t_cover_line__336_block [31:0] $end + $var wire 32 j vlCoverageLineTrace_t_cover_line__337_cond_else [31:0] $end + $var wire 32 k vlCoverageLineTrace_t_cover_line__337_cond_then [31:0] $end + $var wire 32 l vlCoverageLineTrace_t_cover_line__338_cond_else [31:0] $end + $var wire 32 m vlCoverageLineTrace_t_cover_line__338_cond_then [31:0] $end + $var wire 32 8 vlCoverageLineTrace_t_cover_line__340_cond_else_1 [31:0] $end + $var wire 32 9 vlCoverageLineTrace_t_cover_line__340_cond_then_1 [31:0] $end + $var wire 32 : vlCoverageLineTrace_t_cover_line__340_cond_else [31:0] $end + $var wire 32 ; vlCoverageLineTrace_t_cover_line__340_cond_then [31:0] $end + $var wire 32 n vlCoverageLineTrace_t_cover_line__343_cond_else [31:0] $end + $var wire 32 o vlCoverageLineTrace_t_cover_line__343_cond_then [31:0] $end + $var wire 32 J! vlCoverageLineTrace_t_cover_line__349_cond_else [31:0] $end + $var wire 32 / vlCoverageLineTrace_t_cover_line__349_cond_else_1 [31:0] $end + $var wire 32 K! vlCoverageLineTrace_t_cover_line__349_cond_then [31:0] $end + $var wire 32 0 vlCoverageLineTrace_t_cover_line__349_cond_then_1 [31:0] $end + $var wire 32 % vlCoverageLineTrace_t_cover_line__352_block [31:0] $end + $var wire 32 p vlCoverageLineTrace_t_cover_line__353_else [31:0] $end + $var wire 32 q vlCoverageLineTrace_t_cover_line__353_if [31:0] $end + $var wire 32 r vlCoverageLineTrace_t_cover_line__353_cond_else [31:0] $end + $var wire 32 s vlCoverageLineTrace_t_cover_line__353_cond_then [31:0] $end + $var wire 32 t vlCoverageLineTrace_t_cover_line__356_cond_else [31:0] $end + $var wire 32 u vlCoverageLineTrace_t_cover_line__356_cond_then [31:0] $end + $var wire 32 & vlCoverageLineTrace_t_cover_line__359_block [31:0] $end + $var wire 32 v vlCoverageLineTrace_t_cover_line__362_block [31:0] $end + $var wire 32 w vlCoverageLineTrace_t_cover_line__362_cond_else [31:0] $end + $var wire 32 x vlCoverageLineTrace_t_cover_line__362_cond_then [31:0] $end + $var wire 32 y vlCoverageLineTrace_t_cover_line__366_else [31:0] $end + $var wire 32 z vlCoverageLineTrace_t_cover_line__366_if [31:0] $end + $var wire 32 { vlCoverageLineTrace_t_cover_line__370_cond_else [31:0] $end + $var wire 32 | vlCoverageLineTrace_t_cover_line__370_cond_then [31:0] $end + $var wire 32 } vlCoverageLineTrace_t_cover_line__373_block [31:0] $end + $var wire 32 ~ vlCoverageLineTrace_t_cover_line__374_else [31:0] $end + $var wire 32 !! vlCoverageLineTrace_t_cover_line__374_if [31:0] $end $upscope $end $scope module o1 $end - $var wire 1 >! clk $end - $var wire 1 = toggle $end - $var wire 32 $! vlCoverageLineTrace_t_cover_line__253_block [31:0] $end - $var wire 32 %! vlCoverageLineTrace_t_cover_line__254_else [31:0] $end - $var wire 32 &! vlCoverageLineTrace_t_cover_line__254_if [31:0] $end - $var wire 32 '! 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comment=(($exp($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($exp($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($exp($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($sqrt(123) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($sqrt($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($sqrt($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($sqrt($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($sqrt($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($pow(123, 2) != 0) && foo) bump <= bump + 1; --000000 point: comment=((($itor($signed(32'sh7b)) ** $itor($signed(32'sh2))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=((($itor($signed(32'sh7b)) ** $itor($signed(32'sh2))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=((($itor($signed(32'sh7b)) ** $itor($signed(32'sh2))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=((($itor($signed(32'sh7b)) ** $itor($signed(32'sh2))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($floor(1.23) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($floor(1.23) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($floor(1.23) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($floor(1.23) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($floor(1.23) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($ceil(1.23) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($ceil(1.23) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($ceil(1.23) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($ceil(1.23) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($ceil(1.23) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($sin(123) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($sin($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($sin($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($sin($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($sin($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($cos(123) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($cos($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($cos($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($cos($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($cos($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($tan(123) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($tan($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($tan($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($tan($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($tan($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($asin(123) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($asin($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($asin($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($asin($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($asin($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($acos(123) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($acos($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($acos($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($acos($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($acos($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($atan(123) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($atan($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($atan($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($atan($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($atan($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($atan2(123, 2) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($atan2($itor($signed(32'sh7b)),$itor($signed(32'sh2))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($atan2($itor($signed(32'sh7b)),$itor($signed(32'sh2))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($atan2($itor($signed(32'sh7b)),$itor($signed(32'sh2))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($atan2($itor($signed(32'sh7b)),$itor($signed(32'sh2))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($hypot(123, 2) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($hypot($itor($signed(32'sh7b)),$itor($signed(32'sh2))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($hypot($itor($signed(32'sh7b)),$itor($signed(32'sh2))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($hypot($itor($signed(32'sh7b)),$itor($signed(32'sh2))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($hypot($itor($signed(32'sh7b)),$itor($signed(32'sh2))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($sinh(123) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($sinh($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($sinh($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($sinh($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($sinh($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($cosh(123) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($cosh($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t -+000010 point: comment=(($cosh($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($cosh($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==0) => 0 hier=top.t ++000010 point: type=expr comment=(($cosh($itor($signed(32'sh7b))) != $itor($signed(32'sh0)))==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if 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comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($onehot(123) != 0) && foo) bump <= bump + 1; -+000010 point: comment=(($onehot(32'sh7b) != 32'sh0)==0) => 0 hier=top.t --000000 point: comment=(($onehot(32'sh7b) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t --000000 point: comment=if hier=top.t -+000010 point: comment=else hier=top.t ++000010 point: type=expr comment=(($onehot(32'sh7b) != 32'sh0)==0) => 0 hier=top.t +-000000 point: type=expr comment=(($onehot(32'sh7b) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t +-000000 point: type=branch comment=if hier=top.t ++000010 point: type=branch comment=else hier=top.t ~000010 if ($isunknown(foo) && foo) bump <= bump + 1; -+000010 point: comment=($isunknown(foo)==0) => 0 hier=top.t --000000 point: comment=($isunknown(foo)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t --000000 point: comment=if hier=top.t -+000010 point: comment=else hier=top.t ++000010 point: type=expr comment=($isunknown(foo)==0) => 0 hier=top.t +-000000 point: type=expr comment=($isunknown(foo)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t +-000000 point: type=branch comment=if hier=top.t ++000010 point: type=branch comment=else hier=top.t ~000010 if (($countones(123) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($countones(32'sh7b) != 32'sh0)==0) => 0 hier=top.t -+000010 point: comment=(($countones(32'sh7b) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($countones(32'sh7b) != 32'sh0)==0) => 0 hier=top.t ++000010 point: type=expr comment=(($countones(32'sh7b) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($onehot0(123) != 0) && foo) bump <= bump + 1; -+000010 point: comment=(($onehot0(32'sh7b) != 32'sh0)==0) => 0 hier=top.t --000000 point: comment=(($onehot0(32'sh7b) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t --000000 point: comment=if hier=top.t -+000010 point: comment=else hier=top.t ++000010 point: type=expr comment=(($onehot0(32'sh7b) != 32'sh0)==0) => 0 hier=top.t +-000000 point: type=expr comment=(($onehot0(32'sh7b) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t +-000000 point: type=branch comment=if hier=top.t ++000010 point: type=branch comment=else hier=top.t ~000010 if (($sampled(foo) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($sampled(foo) != 32'sh0)==0) => 0 hier=top.t -+000010 point: comment=(($sampled(foo) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($sampled(foo) != 32'sh0)==0) => 0 hier=top.t ++000010 point: type=expr comment=(($sampled(foo) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($fell(foo) != 0) && foo) bump <= bump + 1; -+000010 point: comment=(($fell(foo) != 32'sh0)==0) => 0 hier=top.t --000000 point: comment=(($fell(foo) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t --000000 point: comment=if hier=top.t -+000010 point: comment=else hier=top.t ++000010 point: type=expr comment=(($fell(foo) != 32'sh0)==0) => 0 hier=top.t +-000000 point: type=expr comment=(($fell(foo) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t +-000000 point: type=branch comment=if hier=top.t ++000010 point: type=branch comment=else hier=top.t %000009 if (($changed(foo) != 0) && foo) bump <= bump + 1; --000009 point: comment=(((! $stable(foo)) != 32'sh0)==0) => 0 hier=top.t --000001 point: comment=(((! $stable(foo)) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t +-000009 point: type=expr comment=(((! $stable(foo)) != 32'sh0)==0) => 0 hier=top.t +-000001 point: type=expr comment=(((! $stable(foo)) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t %000009 if (($rose(foo) != 0) && foo) bump <= bump + 1; --000009 point: comment=(($rose(foo) != 32'sh0)==0) => 0 hier=top.t --000001 point: comment=(($rose(foo) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t +-000009 point: type=expr comment=(($rose(foo) != 32'sh0)==0) => 0 hier=top.t +-000001 point: type=expr comment=(($rose(foo) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t %000009 if (($stable(foo) != 0) && foo) bump <= bump + 1; --000001 point: comment=(($stable(foo) != 32'sh0)==0) => 0 hier=top.t --000009 point: comment=(($stable(foo) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t --000009 point: comment=if hier=top.t --000001 point: comment=else hier=top.t +-000001 point: type=expr comment=(($stable(foo) != 32'sh0)==0) => 0 hier=top.t +-000009 point: type=expr comment=(($stable(foo) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t +-000009 point: type=branch comment=if hier=top.t +-000001 point: type=branch comment=else hier=top.t %000009 if (($past(foo) != 0) && foo) bump <= bump + 1; --000001 point: comment=(($past(foo) != 32'sh0)==0) => 0 hier=top.t --000009 point: comment=(($past(foo) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t --000009 point: comment=if hier=top.t --000001 point: comment=else hier=top.t +-000001 point: type=expr comment=(($past(foo) != 32'sh0)==0) => 0 hier=top.t +-000009 point: type=expr comment=(($past(foo) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t +-000009 point: type=branch comment=if hier=top.t +-000001 point: type=branch comment=else hier=top.t ~000010 if (($random != 0) && foo) bump <= bump + 1; -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($dist_erlang(result, 2, 3) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($dist_erlang(result, 32'sh2, 32'sh3) != 32'sh0)==0) => 0 hier=top.t -+000010 point: comment=(($dist_erlang(result, 32'sh2, 32'sh3) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($dist_erlang(result, 32'sh2, 32'sh3) != 32'sh0)==0) => 0 hier=top.t ++000010 point: type=expr comment=(($dist_erlang(result, 32'sh2, 32'sh3) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($dist_normal(result, 2, 3) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($dist_normal(result, 32'sh2, 32'sh3) != 32'sh0)==0) => 0 hier=top.t -+000010 point: comment=(($dist_normal(result, 32'sh2, 32'sh3) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($dist_normal(result, 32'sh2, 32'sh3) != 32'sh0)==0) => 0 hier=top.t ++000010 point: type=expr comment=(($dist_normal(result, 32'sh2, 32'sh3) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($dist_t(result, 2) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($dist_t(result, 32'sh2) != 32'sh0)==0) => 0 hier=top.t --000000 point: comment=(($dist_t(result, 32'sh2) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t --000000 point: comment=if hier=top.t -+000010 point: comment=else hier=top.t +-000000 point: type=expr comment=(($dist_t(result, 32'sh2) != 32'sh0)==0) => 0 hier=top.t +-000000 point: type=expr comment=(($dist_t(result, 32'sh2) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t +-000000 point: type=branch comment=if hier=top.t ++000010 point: type=branch comment=else hier=top.t ~000010 if (($dist_chi_square(result, 2) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($dist_chi_square(result, 32'sh2) != 32'sh0)==0) => 0 hier=top.t -+000010 point: comment=(($dist_chi_square(result, 32'sh2) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($dist_chi_square(result, 32'sh2) != 32'sh0)==0) => 0 hier=top.t ++000010 point: type=expr comment=(($dist_chi_square(result, 32'sh2) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($dist_exponential(result, 2) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($dist_exponential(result, 32'sh2) != 32'sh0)==0) => 0 hier=top.t --000000 point: comment=(($dist_exponential(result, 32'sh2) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($dist_exponential(result, 32'sh2) != 32'sh0)==0) => 0 hier=top.t +-000000 point: type=expr comment=(($dist_exponential(result, 32'sh2) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($dist_poisson(result, 2) != 0) && foo) bump <= bump + 1; -+000010 point: comment=(($dist_poisson(result, 32'sh2) != 32'sh0)==0) => 0 hier=top.t -+000010 point: comment=(($dist_poisson(result, 32'sh2) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t ++000010 point: type=expr comment=(($dist_poisson(result, 32'sh2) != 32'sh0)==0) => 0 hier=top.t ++000010 point: type=expr comment=(($dist_poisson(result, 32'sh2) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($dist_uniform(result, 2, 3) != 0) && foo) bump <= bump + 1; --000000 point: comment=(($dist_uniform(result, 32'sh2, 32'sh3) != 32'sh0)==0) => 0 hier=top.t -+000010 point: comment=(($dist_uniform(result, 32'sh2, 32'sh3) != 32'sh0)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(($dist_uniform(result, 32'sh2, 32'sh3) != 32'sh0)==0) => 0 hier=top.t ++000010 point: type=expr comment=(($dist_uniform(result, 32'sh2, 32'sh3) != 32'sh0)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t ~000010 if (($sformatf("abc") != "abc") && foo) bump <= bump + 1; -+000010 point: comment=(($sformatf(%22abc%22);%0A != %22abc%22)==0) => 0 hier=top.t --000000 point: comment=(($sformatf(%22abc%22);%0A != %22abc%22)==1 && foo==1) => 1 hier=top.t --000000 point: comment=(foo==0) => 0 hier=top.t --000000 point: comment=if hier=top.t -+000010 point: comment=else hier=top.t ++000010 point: type=expr comment=(($sformatf(%22abc%22);%0A != %22abc%22)==0) => 0 hier=top.t +-000000 point: type=expr comment=(($sformatf(%22abc%22);%0A != %22abc%22)==1 && foo==1) => 1 hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t +-000000 point: type=branch comment=if hier=top.t ++000010 point: type=branch comment=else hier=top.t ~000010 if (foo && foo) bump <= bump + 1; --000000 point: comment=(foo==0) => 0 hier=top.t -+000010 point: comment=(foo==1) => 1 hier=top.t -+000010 point: comment=if hier=top.t --000000 point: comment=else hier=top.t +-000000 point: type=expr comment=(foo==0) => 0 hier=top.t ++000010 point: type=expr comment=(foo==1) => 1 hier=top.t ++000010 point: type=branch comment=if hier=top.t +-000000 point: type=branch comment=else hier=top.t 000010 cyc <= cyc + 1; -+000010 point: comment=block hier=top.t ++000010 point: type=line comment=block hier=top.t %000009 if (cyc == 9) begin --000001 point: comment=if hier=top.t --000009 point: comment=else hier=top.t +-000001 point: type=branch comment=if hier=top.t +-000009 point: type=branch comment=else hier=top.t %000001 $write("*-* All Finished *-*\n"); --000001 point: comment=if hier=top.t +-000001 point: type=branch comment=if hier=top.t %000001 $finish; --000001 point: comment=if hier=top.t +-000001 point: type=branch comment=if hier=top.t end end endmodule diff --git a/test_regress/t/t_cover_sys_line_expr.py b/test_regress/t/t_cover_sys_line_expr.py index c1be5c43d..763e18bc3 100755 --- a/test_regress/t/t_cover_sys_line_expr.py +++ b/test_regress/t/t_cover_sys_line_expr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_sys_line_expr.v b/test_regress/t/t_cover_sys_line_expr.v index 02a13b068..2ef31c879 100644 --- a/test_regress/t/t_cover_sys_line_expr.v +++ b/test_regress/t/t_cover_sys_line_expr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_cover_sys_unsup.py b/test_regress/t/t_cover_sys_unsup.py index f41d93235..b7449248c 100755 --- a/test_regress/t/t_cover_sys_unsup.py +++ b/test_regress/t/t_cover_sys_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_sys_unsup.v b/test_regress/t/t_cover_sys_unsup.v index 7a192a78e..1aa1bf52f 100644 --- a/test_regress/t/t_cover_sys_unsup.v +++ b/test_regress/t/t_cover_sys_unsup.v @@ -2,8 +2,8 @@ // // Simple bi-directional alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_cover_toggle.out b/test_regress/t/t_cover_toggle.out index 9803cf737..ec84bf328 100644 --- a/test_regress/t/t_cover_toggle.out +++ b/test_regress/t/t_cover_toggle.out @@ -1,8 +1,8 @@ // // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2008 by Wilson Snyder. + // This file ONLY is placed under the Creative Commons Public Domain. + // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef struct packed {logic a;} str_logic; diff --git a/test_regress/t/t_cover_toggle.py b/test_regress/t/t_cover_toggle.py index 95a327b34..e15a9a488 100755 --- a/test_regress/t/t_cover_toggle.py +++ b/test_regress/t/t_cover_toggle.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_toggle.v b/test_regress/t/t_cover_toggle.v index c23c35835..e0a21df21 100644 --- a/test_regress/t/t_cover_toggle.v +++ b/test_regress/t/t_cover_toggle.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef struct packed {logic a;} str_logic; diff --git a/test_regress/t/t_cover_toggle__all.out b/test_regress/t/t_cover_toggle__all.out index da7f7bd30..61281e1da 100644 --- a/test_regress/t/t_cover_toggle__all.out +++ b/test_regress/t/t_cover_toggle__all.out @@ -1,8 +1,8 @@ // // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2008 by Wilson Snyder. + // This file ONLY is placed under the Creative Commons Public Domain. + // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef struct packed {logic a;} str_logic; diff --git a/test_regress/t/t_cover_toggle__points.out b/test_regress/t/t_cover_toggle__points.out index c63299952..25f537907 100644 --- a/test_regress/t/t_cover_toggle__points.out +++ b/test_regress/t/t_cover_toggle__points.out @@ -1,8 +1,8 @@ // // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // - // This file ONLY is placed under the Creative Commons Public Domain, for - // any use, without warranty, 2008 by Wilson Snyder. + // This file ONLY is placed under the Creative Commons Public Domain. + // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef struct packed {logic a;} str_logic; @@ -13,8 +13,8 @@ ); ~000010 input clk; -+000010 point: comment=clk:0->1 hier=top.t --000009 point: comment=clk:1->0 hier=top.t ++000010 point: type=toggle comment=clk:0->1 hier=top.t +-000009 point: type=toggle comment=clk:1->0 hier=top.t input real check_real; // Check issue #2741 input real check_array_real [1:0]; input string check_string; // Check issue #2766 @@ -28,20 +28,20 @@ } str_t; %000001 reg toggle; initial toggle='0; --000001 point: comment=toggle:0->1 hier=top.t --000001 point: comment=toggle:1->0 hier=top.t +-000001 point: type=toggle comment=toggle:0->1 hier=top.t +-000001 point: type=toggle comment=toggle:1->0 hier=top.t logic _under_toggle = toggle; // For --coverage-underscore %000001 str_t stoggle; initial stoggle='0; --000001 point: comment=stoggle.b:0->1 hier=top.t --000001 point: comment=stoggle.b:1->0 hier=top.t --000001 point: comment=stoggle.u.ua:0->1 hier=top.t --000001 point: comment=stoggle.u.ua:1->0 hier=top.t +-000001 point: type=toggle comment=stoggle.b:0->1 hier=top.t +-000001 point: type=toggle comment=stoggle.b:1->0 hier=top.t +-000001 point: type=toggle comment=stoggle.u.ua:0->1 hier=top.t +-000001 point: type=toggle comment=stoggle.u.ua:1->0 hier=top.t ~000010 str_logic strl; initial strl='0; -+000010 point: comment=strl.a:0->1 hier=top.t --000009 point: comment=strl.a:1->0 hier=top.t ++000010 point: type=toggle comment=strl.a:0->1 hier=top.t +-000009 point: type=toggle comment=strl.a:1->0 hier=top.t union { real val1; // TODO use bit [7:0] here @@ -51,36 +51,36 @@ const reg aconst = '0; %000001 reg [1:0][1:0] ptoggle; initial ptoggle=0; --000001 point: comment=ptoggle[0][0]:0->1 hier=top.t --000001 point: comment=ptoggle[0][0]:1->0 hier=top.t --000000 point: comment=ptoggle[0][1]:0->1 hier=top.t --000000 point: comment=ptoggle[0][1]:1->0 hier=top.t --000000 point: comment=ptoggle[1][0]:0->1 hier=top.t --000000 point: comment=ptoggle[1][0]:1->0 hier=top.t --000000 point: comment=ptoggle[1][1]:0->1 hier=top.t --000000 point: comment=ptoggle[1][1]:1->0 hier=top.t +-000001 point: type=toggle comment=ptoggle[0][0]:0->1 hier=top.t +-000001 point: type=toggle comment=ptoggle[0][0]:1->0 hier=top.t +-000000 point: type=toggle comment=ptoggle[0][1]:0->1 hier=top.t +-000000 point: type=toggle comment=ptoggle[0][1]:1->0 hier=top.t +-000000 point: type=toggle comment=ptoggle[1][0]:0->1 hier=top.t +-000000 point: type=toggle comment=ptoggle[1][0]:1->0 hier=top.t +-000000 point: type=toggle comment=ptoggle[1][1]:0->1 hier=top.t +-000000 point: type=toggle comment=ptoggle[1][1]:1->0 hier=top.t integer cyc; initial cyc=1; %000006 wire [7:0] cyc_copy = cyc[7:0]; --000006 point: comment=cyc_copy[0]:0->1 hier=top.t --000005 point: comment=cyc_copy[0]:1->0 hier=top.t --000003 point: comment=cyc_copy[1]:0->1 hier=top.t --000002 point: comment=cyc_copy[1]:1->0 hier=top.t --000001 point: comment=cyc_copy[2]:0->1 hier=top.t --000001 point: comment=cyc_copy[2]:1->0 hier=top.t --000001 point: comment=cyc_copy[3]:0->1 hier=top.t --000000 point: comment=cyc_copy[3]:1->0 hier=top.t --000000 point: comment=cyc_copy[4]:0->1 hier=top.t --000000 point: comment=cyc_copy[4]:1->0 hier=top.t --000000 point: comment=cyc_copy[5]:0->1 hier=top.t --000000 point: comment=cyc_copy[5]:1->0 hier=top.t --000000 point: comment=cyc_copy[6]:0->1 hier=top.t --000000 point: comment=cyc_copy[6]:1->0 hier=top.t --000000 point: comment=cyc_copy[7]:0->1 hier=top.t --000000 point: comment=cyc_copy[7]:1->0 hier=top.t +-000006 point: type=toggle comment=cyc_copy[0]:0->1 hier=top.t +-000005 point: type=toggle comment=cyc_copy[0]:1->0 hier=top.t +-000003 point: type=toggle comment=cyc_copy[1]:0->1 hier=top.t +-000002 point: type=toggle comment=cyc_copy[1]:1->0 hier=top.t +-000001 point: type=toggle comment=cyc_copy[2]:0->1 hier=top.t +-000001 point: type=toggle comment=cyc_copy[2]:1->0 hier=top.t +-000001 point: type=toggle comment=cyc_copy[3]:0->1 hier=top.t +-000000 point: type=toggle comment=cyc_copy[3]:1->0 hier=top.t +-000000 point: type=toggle comment=cyc_copy[4]:0->1 hier=top.t +-000000 point: type=toggle comment=cyc_copy[4]:1->0 hier=top.t +-000000 point: type=toggle comment=cyc_copy[5]:0->1 hier=top.t +-000000 point: type=toggle comment=cyc_copy[5]:1->0 hier=top.t +-000000 point: type=toggle comment=cyc_copy[6]:0->1 hier=top.t +-000000 point: type=toggle comment=cyc_copy[6]:1->0 hier=top.t +-000000 point: type=toggle comment=cyc_copy[7]:0->1 hier=top.t +-000000 point: type=toggle comment=cyc_copy[7]:1->0 hier=top.t %000001 wire toggle_up; --000001 point: comment=toggle_up:0->1 hier=top.t --000001 point: comment=toggle_up:1->0 hier=top.t +-000001 point: type=toggle comment=toggle_up:0->1 hier=top.t +-000001 point: type=toggle comment=toggle_up:1->0 hier=top.t typedef struct { int q[$]; @@ -94,47 +94,47 @@ bit [0:0] y; } str_bit_t; %000001 str_bit_t str_bit; --000001 point: comment=str_bit.x[3]:0->1 hier=top.t --000001 point: comment=str_bit.x[3]:1->0 hier=top.t --000001 point: comment=str_bit.x[4]:0->1 hier=top.t --000000 point: comment=str_bit.x[4]:1->0 hier=top.t --000001 point: comment=str_bit.x[5]:0->1 hier=top.t --000000 point: comment=str_bit.x[5]:1->0 hier=top.t --000001 point: comment=str_bit.y[0]:0->1 hier=top.t --000001 point: comment=str_bit.y[0]:1->0 hier=top.t +-000001 point: type=toggle comment=str_bit.x[3]:0->1 hier=top.t +-000001 point: type=toggle comment=str_bit.x[3]:1->0 hier=top.t +-000001 point: type=toggle comment=str_bit.x[4]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit.x[4]:1->0 hier=top.t +-000001 point: type=toggle comment=str_bit.x[5]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit.x[5]:1->0 hier=top.t +-000001 point: type=toggle comment=str_bit.y[0]:0->1 hier=top.t +-000001 point: type=toggle comment=str_bit.y[0]:1->0 hier=top.t %000001 str_bit_t [5:2] str_bit_arr; --000000 point: comment=str_bit_arr[2].x[3]:0->1 hier=top.t --000000 point: comment=str_bit_arr[2].x[3]:1->0 hier=top.t --000000 point: comment=str_bit_arr[2].x[4]:0->1 hier=top.t --000000 point: comment=str_bit_arr[2].x[4]:1->0 hier=top.t --000000 point: comment=str_bit_arr[2].x[5]:0->1 hier=top.t --000000 point: comment=str_bit_arr[2].x[5]:1->0 hier=top.t --000000 point: comment=str_bit_arr[2].y[0]:0->1 hier=top.t --000000 point: comment=str_bit_arr[2].y[0]:1->0 hier=top.t --000000 point: comment=str_bit_arr[3].x[3]:0->1 hier=top.t --000000 point: comment=str_bit_arr[3].x[3]:1->0 hier=top.t --000000 point: comment=str_bit_arr[3].x[4]:0->1 hier=top.t --000000 point: comment=str_bit_arr[3].x[4]:1->0 hier=top.t --000000 point: comment=str_bit_arr[3].x[5]:0->1 hier=top.t --000000 point: comment=str_bit_arr[3].x[5]:1->0 hier=top.t --000000 point: comment=str_bit_arr[3].y[0]:0->1 hier=top.t --000000 point: comment=str_bit_arr[3].y[0]:1->0 hier=top.t --000001 point: comment=str_bit_arr[4].x[3]:0->1 hier=top.t --000001 point: comment=str_bit_arr[4].x[3]:1->0 hier=top.t --000001 point: comment=str_bit_arr[4].x[4]:0->1 hier=top.t --000000 point: comment=str_bit_arr[4].x[4]:1->0 hier=top.t --000001 point: comment=str_bit_arr[4].x[5]:0->1 hier=top.t --000000 point: comment=str_bit_arr[4].x[5]:1->0 hier=top.t --000000 point: comment=str_bit_arr[4].y[0]:0->1 hier=top.t --000000 point: comment=str_bit_arr[4].y[0]:1->0 hier=top.t --000000 point: comment=str_bit_arr[5].x[3]:0->1 hier=top.t --000000 point: comment=str_bit_arr[5].x[3]:1->0 hier=top.t --000000 point: comment=str_bit_arr[5].x[4]:0->1 hier=top.t --000000 point: comment=str_bit_arr[5].x[4]:1->0 hier=top.t --000000 point: comment=str_bit_arr[5].x[5]:0->1 hier=top.t --000000 point: comment=str_bit_arr[5].x[5]:1->0 hier=top.t --000000 point: comment=str_bit_arr[5].y[0]:0->1 hier=top.t --000000 point: comment=str_bit_arr[5].y[0]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[2].x[3]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[2].x[3]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[2].x[4]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[2].x[4]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[2].x[5]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[2].x[5]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[2].y[0]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[2].y[0]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[3].x[3]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[3].x[3]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[3].x[4]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[3].x[4]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[3].x[5]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[3].x[5]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[3].y[0]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[3].y[0]:1->0 hier=top.t +-000001 point: type=toggle comment=str_bit_arr[4].x[3]:0->1 hier=top.t +-000001 point: type=toggle comment=str_bit_arr[4].x[3]:1->0 hier=top.t +-000001 point: type=toggle comment=str_bit_arr[4].x[4]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[4].x[4]:1->0 hier=top.t +-000001 point: type=toggle comment=str_bit_arr[4].x[5]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[4].x[5]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[4].y[0]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[4].y[0]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[5].x[3]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[5].x[3]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[5].x[4]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[5].x[4]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[5].x[5]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[5].x[5]:1->0 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[5].y[0]:0->1 hier=top.t +-000000 point: type=toggle comment=str_bit_arr[5].y[0]:1->0 hier=top.t assign strl.a = clk; @@ -179,54 +179,54 @@ %000001 reg [1:0] memory[121:110]; --000001 point: comment=memory[110][0]:0->1 hier=top.t --000000 point: comment=memory[110][0]:1->0 hier=top.t --000000 point: comment=memory[110][1]:0->1 hier=top.t --000000 point: comment=memory[110][1]:1->0 hier=top.t --000000 point: comment=memory[111][0]:0->1 hier=top.t --000000 point: comment=memory[111][0]:1->0 hier=top.t --000000 point: comment=memory[111][1]:0->1 hier=top.t --000000 point: comment=memory[111][1]:1->0 hier=top.t --000000 point: comment=memory[112][0]:0->1 hier=top.t --000000 point: comment=memory[112][0]:1->0 hier=top.t --000000 point: comment=memory[112][1]:0->1 hier=top.t --000000 point: comment=memory[112][1]:1->0 hier=top.t --000000 point: comment=memory[113][0]:0->1 hier=top.t --000000 point: comment=memory[113][0]:1->0 hier=top.t --000000 point: comment=memory[113][1]:0->1 hier=top.t --000000 point: comment=memory[113][1]:1->0 hier=top.t --000000 point: comment=memory[114][0]:0->1 hier=top.t --000000 point: comment=memory[114][0]:1->0 hier=top.t --000000 point: comment=memory[114][1]:0->1 hier=top.t --000000 point: comment=memory[114][1]:1->0 hier=top.t --000000 point: comment=memory[115][0]:0->1 hier=top.t --000000 point: comment=memory[115][0]:1->0 hier=top.t --000000 point: comment=memory[115][1]:0->1 hier=top.t --000000 point: comment=memory[115][1]:1->0 hier=top.t --000000 point: comment=memory[116][0]:0->1 hier=top.t --000000 point: comment=memory[116][0]:1->0 hier=top.t --000000 point: comment=memory[116][1]:0->1 hier=top.t --000000 point: comment=memory[116][1]:1->0 hier=top.t --000000 point: comment=memory[117][0]:0->1 hier=top.t --000000 point: comment=memory[117][0]:1->0 hier=top.t --000000 point: comment=memory[117][1]:0->1 hier=top.t --000000 point: comment=memory[117][1]:1->0 hier=top.t --000000 point: comment=memory[118][0]:0->1 hier=top.t --000000 point: comment=memory[118][0]:1->0 hier=top.t --000000 point: comment=memory[118][1]:0->1 hier=top.t --000000 point: comment=memory[118][1]:1->0 hier=top.t --000000 point: comment=memory[119][0]:0->1 hier=top.t --000000 point: comment=memory[119][0]:1->0 hier=top.t --000000 point: comment=memory[119][1]:0->1 hier=top.t --000000 point: comment=memory[119][1]:1->0 hier=top.t --000000 point: comment=memory[120][0]:0->1 hier=top.t --000000 point: comment=memory[120][0]:1->0 hier=top.t --000000 point: comment=memory[120][1]:0->1 hier=top.t --000000 point: comment=memory[120][1]:1->0 hier=top.t --000000 point: comment=memory[121][0]:0->1 hier=top.t --000000 point: comment=memory[121][0]:1->0 hier=top.t --000000 point: comment=memory[121][1]:0->1 hier=top.t --000000 point: comment=memory[121][1]:1->0 hier=top.t +-000001 point: type=toggle comment=memory[110][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[110][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[110][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[110][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[111][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[111][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[111][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[111][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[112][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[112][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[112][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[112][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[113][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[113][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[113][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[113][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[114][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[114][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[114][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[114][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[115][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[115][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[115][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[115][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[116][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[116][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[116][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[116][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[117][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[117][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[117][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[117][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[118][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[118][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[118][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[118][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[119][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[119][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[119][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[119][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[120][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[120][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[120][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[120][1]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[121][0]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[121][0]:1->0 hier=top.t +-000000 point: type=toggle comment=memory[121][1]:0->1 hier=top.t +-000000 point: type=toggle comment=memory[121][1]:1->0 hier=top.t wire [1023:0] largeish = {992'h0, cyc}; // CHECK_COVER_MISSING(-1) @@ -273,33 +273,33 @@ // t.a1 and t.a2 collapse to a count of 2 000020 input clk; -+000020 point: comment=clk:0->1 hier=top.t.a* -+000018 point: comment=clk:1->0 hier=top.t.a* ++000020 point: type=toggle comment=clk:0->1 hier=top.t.a* ++000018 point: type=toggle comment=clk:1->0 hier=top.t.a* %000002 input toggle; --000002 point: comment=toggle:0->1 hier=top.t.a* --000002 point: comment=toggle:1->0 hier=top.t.a* +-000002 point: type=toggle comment=toggle:0->1 hier=top.t.a* +-000002 point: type=toggle comment=toggle:1->0 hier=top.t.a* // CHECK_COVER(-1,"top.t.a*","toggle:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle:1->0",2) // (t.a1 and t.a2) ~000012 input [7:0] cyc_copy; -+000012 point: comment=cyc_copy[0]:0->1 hier=top.t.a* -+000010 point: comment=cyc_copy[0]:1->0 hier=top.t.a* --000006 point: comment=cyc_copy[1]:0->1 hier=top.t.a* --000004 point: comment=cyc_copy[1]:1->0 hier=top.t.a* --000002 point: comment=cyc_copy[2]:0->1 hier=top.t.a* --000002 point: comment=cyc_copy[2]:1->0 hier=top.t.a* --000002 point: comment=cyc_copy[3]:0->1 hier=top.t.a* --000000 point: comment=cyc_copy[3]:1->0 hier=top.t.a* --000000 point: comment=cyc_copy[4]:0->1 hier=top.t.a* --000000 point: comment=cyc_copy[4]:1->0 hier=top.t.a* --000000 point: comment=cyc_copy[5]:0->1 hier=top.t.a* --000000 point: comment=cyc_copy[5]:1->0 hier=top.t.a* --000000 point: comment=cyc_copy[6]:0->1 hier=top.t.a* --000000 point: comment=cyc_copy[6]:1->0 hier=top.t.a* --000000 point: comment=cyc_copy[7]:0->1 hier=top.t.a* --000000 point: comment=cyc_copy[7]:1->0 hier=top.t.a* ++000012 point: type=toggle comment=cyc_copy[0]:0->1 hier=top.t.a* ++000010 point: type=toggle comment=cyc_copy[0]:1->0 hier=top.t.a* +-000006 point: type=toggle comment=cyc_copy[1]:0->1 hier=top.t.a* +-000004 point: type=toggle comment=cyc_copy[1]:1->0 hier=top.t.a* +-000002 point: type=toggle comment=cyc_copy[2]:0->1 hier=top.t.a* +-000002 point: type=toggle comment=cyc_copy[2]:1->0 hier=top.t.a* +-000002 point: type=toggle comment=cyc_copy[3]:0->1 hier=top.t.a* +-000000 point: type=toggle comment=cyc_copy[3]:1->0 hier=top.t.a* +-000000 point: type=toggle comment=cyc_copy[4]:0->1 hier=top.t.a* +-000000 point: type=toggle comment=cyc_copy[4]:1->0 hier=top.t.a* +-000000 point: type=toggle comment=cyc_copy[5]:0->1 hier=top.t.a* +-000000 point: type=toggle comment=cyc_copy[5]:1->0 hier=top.t.a* +-000000 point: type=toggle comment=cyc_copy[6]:0->1 hier=top.t.a* +-000000 point: type=toggle comment=cyc_copy[6]:1->0 hier=top.t.a* +-000000 point: type=toggle comment=cyc_copy[7]:0->1 hier=top.t.a* +-000000 point: type=toggle comment=cyc_copy[7]:1->0 hier=top.t.a* // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]:0->1",12) // CHECK_COVER(-2,"top.t.a*","cyc_copy[0]:1->0",10) // CHECK_COVER(-3,"top.t.a*","cyc_copy[1]:0->1",6) @@ -318,15 +318,15 @@ // CHECK_COVER(-16,"top.t.a*","cyc_copy[7]:1->0",0) %000002 reg toggle_internal; --000002 point: comment=toggle_internal:0->1 hier=top.t.a* --000002 point: comment=toggle_internal:1->0 hier=top.t.a* +-000002 point: type=toggle comment=toggle_internal:0->1 hier=top.t.a* +-000002 point: type=toggle comment=toggle_internal:1->0 hier=top.t.a* // CHECK_COVER(-1,"top.t.a*","toggle_internal:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_internal:1->0",2) // (t.a1 and t.a2) %000002 output reg toggle_up; --000002 point: comment=toggle_up:0->1 hier=top.t.a* --000002 point: comment=toggle_up:1->0 hier=top.t.a* +-000002 point: type=toggle comment=toggle_up:0->1 hier=top.t.a* +-000002 point: type=toggle comment=toggle_up:1->0 hier=top.t.a* // CHECK_COVER(-1,"top.t.a*","toggle_up:0->1",2) // CHECK_COVER(-2,"top.t.a*","toggle_up:1->0",2) // (t.a1 and t.a2) @@ -343,12 +343,12 @@ ); ~000010 input clk; -+000010 point: comment=clk:0->1 hier=top.t.b1 --000009 point: comment=clk:1->0 hier=top.t.b1 ++000010 point: type=toggle comment=clk:0->1 hier=top.t.b1 +-000009 point: type=toggle comment=clk:1->0 hier=top.t.b1 %000001 input toggle_up; --000001 point: comment=toggle_up:0->1 hier=top.t.b1 --000001 point: comment=toggle_up:1->0 hier=top.t.b1 +-000001 point: type=toggle comment=toggle_up:0->1 hier=top.t.b1 +-000001 point: type=toggle comment=toggle_up:1->0 hier=top.t.b1 // CHECK_COVER(-1,"top.t.b1","toggle_up:0->1",1) // CHECK_COVER(-2,"top.t.b1","toggle_up:1->0",1) @@ -370,8 +370,8 @@ // verilator coverage_on %000001 input toggle; --000001 point: comment=toggle:0->1 hier=top.t.o1 --000001 point: comment=toggle:1->0 hier=top.t.o1 +-000001 point: type=toggle comment=toggle:0->1 hier=top.t.o1 +-000001 point: type=toggle comment=toggle:1->0 hier=top.t.o1 // CHECK_COVER(-1,"top.t.o1","toggle:0->1",1) // CHECK_COVER(-2,"top.t.o1","toggle:1->0",1) @@ -383,89 +383,89 @@ ); ~000010 input clk; -+000010 point: comment=clk:0->1 hier=top.t.p2 --000009 point: comment=clk:1->0 hier=top.t.p2 -+000010 point: comment=clk:0->1 hier=top.t.p1 --000009 point: comment=clk:1->0 hier=top.t.p1 ++000010 point: type=toggle comment=clk:0->1 hier=top.t.p2 +-000009 point: type=toggle comment=clk:1->0 hier=top.t.p2 ++000010 point: type=toggle comment=clk:0->1 hier=top.t.p1 +-000009 point: type=toggle comment=clk:1->0 hier=top.t.p1 %000001 input toggle; --000001 point: comment=toggle:0->1 hier=top.t.p2 --000001 point: comment=toggle:1->0 hier=top.t.p2 --000001 point: comment=toggle:0->1 hier=top.t.p1 --000001 point: comment=toggle:1->0 hier=top.t.p1 +-000001 point: type=toggle comment=toggle:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=toggle:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=toggle:0->1 hier=top.t.p1 +-000001 point: type=toggle comment=toggle:1->0 hier=top.t.p1 %000001 logic z; --000001 point: comment=z:0->1 hier=top.t.p2 --000000 point: comment=z:1->0 hier=top.t.p2 --000000 point: comment=z:0->1 hier=top.t.p1 --000000 point: comment=z:1->0 hier=top.t.p1 +-000001 point: type=toggle comment=z:0->1 hier=top.t.p2 +-000000 point: type=toggle comment=z:1->0 hier=top.t.p2 +-000000 point: type=toggle comment=z:0->1 hier=top.t.p1 +-000000 point: type=toggle comment=z:1->0 hier=top.t.p1 for (genvar i = 0; i < P; i++) begin %000001 logic x; --000001 point: comment=genblk1[0].x:0->1 hier=top.t.p2 --000001 point: comment=genblk1[0].x:1->0 hier=top.t.p2 --000001 point: comment=genblk1[1].x:0->1 hier=top.t.p2 --000001 point: comment=genblk1[1].x:1->0 hier=top.t.p2 --000001 point: comment=genblk1[0].x:0->1 hier=top.t.p1 --000001 point: comment=genblk1[0].x:1->0 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].x:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].x:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].x:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].x:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].x:0->1 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].x:1->0 hier=top.t.p1 always @ (posedge clk) begin x <= toggle; end for (genvar j = 0; j < 3; j++) begin %000002 logic [2:0] y; --000001 point: comment=genblk1[0].genblk1[0].y[0]:0->1 hier=top.t.p2 --000000 point: comment=genblk1[0].genblk1[0].y[0]:1->0 hier=top.t.p2 --000002 point: comment=genblk1[0].genblk1[0].y[1]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[0].y[1]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[0].y[2]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[0].y[2]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[1].y[0]:0->1 hier=top.t.p2 --000000 point: comment=genblk1[0].genblk1[1].y[0]:1->0 hier=top.t.p2 --000002 point: comment=genblk1[0].genblk1[1].y[1]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[1].y[1]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[1].y[2]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[1].y[2]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[2].y[0]:0->1 hier=top.t.p2 --000000 point: comment=genblk1[0].genblk1[2].y[0]:1->0 hier=top.t.p2 --000002 point: comment=genblk1[0].genblk1[2].y[1]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[2].y[1]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[2].y[2]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[2].y[2]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[0].y[0]:0->1 hier=top.t.p2 --000000 point: comment=genblk1[1].genblk1[0].y[0]:1->0 hier=top.t.p2 --000002 point: comment=genblk1[1].genblk1[0].y[1]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[0].y[1]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[0].y[2]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[0].y[2]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[1].y[0]:0->1 hier=top.t.p2 --000000 point: comment=genblk1[1].genblk1[1].y[0]:1->0 hier=top.t.p2 --000002 point: comment=genblk1[1].genblk1[1].y[1]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[1].y[1]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[1].y[2]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[1].y[2]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[2].y[0]:0->1 hier=top.t.p2 --000000 point: comment=genblk1[1].genblk1[2].y[0]:1->0 hier=top.t.p2 --000002 point: comment=genblk1[1].genblk1[2].y[1]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[2].y[1]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[2].y[2]:0->1 hier=top.t.p2 --000001 point: comment=genblk1[1].genblk1[2].y[2]:1->0 hier=top.t.p2 --000001 point: comment=genblk1[0].genblk1[0].y[0]:0->1 hier=top.t.p1 --000000 point: comment=genblk1[0].genblk1[0].y[0]:1->0 hier=top.t.p1 --000002 point: comment=genblk1[0].genblk1[0].y[1]:0->1 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[0].y[1]:1->0 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[0].y[2]:0->1 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[0].y[2]:1->0 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[1].y[0]:0->1 hier=top.t.p1 --000000 point: comment=genblk1[0].genblk1[1].y[0]:1->0 hier=top.t.p1 --000002 point: comment=genblk1[0].genblk1[1].y[1]:0->1 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[1].y[1]:1->0 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[1].y[2]:0->1 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[1].y[2]:1->0 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[2].y[0]:0->1 hier=top.t.p1 --000000 point: comment=genblk1[0].genblk1[2].y[0]:1->0 hier=top.t.p1 --000002 point: comment=genblk1[0].genblk1[2].y[1]:0->1 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[2].y[1]:1->0 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[2].y[2]:0->1 hier=top.t.p1 --000001 point: comment=genblk1[0].genblk1[2].y[2]:1->0 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[0].y[0]:0->1 hier=top.t.p2 +-000000 point: type=toggle comment=genblk1[0].genblk1[0].y[0]:1->0 hier=top.t.p2 +-000002 point: type=toggle comment=genblk1[0].genblk1[0].y[1]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[0].y[1]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[0].y[2]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[0].y[2]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[1].y[0]:0->1 hier=top.t.p2 +-000000 point: type=toggle comment=genblk1[0].genblk1[1].y[0]:1->0 hier=top.t.p2 +-000002 point: type=toggle comment=genblk1[0].genblk1[1].y[1]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[1].y[1]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[1].y[2]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[1].y[2]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[2].y[0]:0->1 hier=top.t.p2 +-000000 point: type=toggle comment=genblk1[0].genblk1[2].y[0]:1->0 hier=top.t.p2 +-000002 point: type=toggle comment=genblk1[0].genblk1[2].y[1]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[2].y[1]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[2].y[2]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[2].y[2]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[0].y[0]:0->1 hier=top.t.p2 +-000000 point: type=toggle comment=genblk1[1].genblk1[0].y[0]:1->0 hier=top.t.p2 +-000002 point: type=toggle comment=genblk1[1].genblk1[0].y[1]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[0].y[1]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[0].y[2]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[0].y[2]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[1].y[0]:0->1 hier=top.t.p2 +-000000 point: type=toggle comment=genblk1[1].genblk1[1].y[0]:1->0 hier=top.t.p2 +-000002 point: type=toggle comment=genblk1[1].genblk1[1].y[1]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[1].y[1]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[1].y[2]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[1].y[2]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[2].y[0]:0->1 hier=top.t.p2 +-000000 point: type=toggle comment=genblk1[1].genblk1[2].y[0]:1->0 hier=top.t.p2 +-000002 point: type=toggle comment=genblk1[1].genblk1[2].y[1]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[2].y[1]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[2].y[2]:0->1 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[1].genblk1[2].y[2]:1->0 hier=top.t.p2 +-000001 point: type=toggle comment=genblk1[0].genblk1[0].y[0]:0->1 hier=top.t.p1 +-000000 point: type=toggle comment=genblk1[0].genblk1[0].y[0]:1->0 hier=top.t.p1 +-000002 point: type=toggle comment=genblk1[0].genblk1[0].y[1]:0->1 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[0].y[1]:1->0 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[0].y[2]:0->1 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[0].y[2]:1->0 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[1].y[0]:0->1 hier=top.t.p1 +-000000 point: type=toggle comment=genblk1[0].genblk1[1].y[0]:1->0 hier=top.t.p1 +-000002 point: type=toggle comment=genblk1[0].genblk1[1].y[1]:0->1 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[1].y[1]:1->0 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[1].y[2]:0->1 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[1].y[2]:1->0 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[2].y[0]:0->1 hier=top.t.p1 +-000000 point: type=toggle comment=genblk1[0].genblk1[2].y[0]:1->0 hier=top.t.p1 +-000002 point: type=toggle comment=genblk1[0].genblk1[2].y[1]:0->1 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[2].y[1]:1->0 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[2].y[2]:0->1 hier=top.t.p1 +-000001 point: type=toggle comment=genblk1[0].genblk1[2].y[2]:1->0 hier=top.t.p1 always @ (negedge clk) begin y <= {toggle, ~toggle, 1'b1}; end @@ -482,7 +482,7 @@ ); ~000010 input str_logic input_struct; -+000010 point: comment=input_struct.a:0->1 hier=top.t.i_mod_struct --000009 point: comment=input_struct.a:1->0 hier=top.t.i_mod_struct ++000010 point: type=toggle comment=input_struct.a:0->1 hier=top.t.i_mod_struct +-000009 point: type=toggle comment=input_struct.a:1->0 hier=top.t.i_mod_struct endmodule diff --git a/test_regress/t/t_cover_toggle_min.py b/test_regress/t/t_cover_toggle_min.py index 83bd0383a..9c454c71c 100755 --- a/test_regress/t/t_cover_toggle_min.py +++ b/test_regress/t/t_cover_toggle_min.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_toggle_min.v b/test_regress/t/t_cover_toggle_min.v index 25c03b721..be1abc641 100644 --- a/test_regress/t/t_cover_toggle_min.v +++ b/test_regress/t/t_cover_toggle_min.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(); diff --git a/test_regress/t/t_cover_toggle_underscore.py b/test_regress/t/t_cover_toggle_underscore.py index 85dd0b999..0c7eb2ed7 100755 --- a/test_regress/t/t_cover_toggle_underscore.py +++ b/test_regress/t/t_cover_toggle_underscore.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_toggle_width.py b/test_regress/t/t_cover_toggle_width.py index 5b1711302..68185902b 100755 --- a/test_regress/t/t_cover_toggle_width.py +++ b/test_regress/t/t_cover_toggle_width.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_trace_always.py b/test_regress/t/t_cover_trace_always.py index 6d1e7aa98..05c05a4b2 100755 --- a/test_regress/t/t_cover_trace_always.py +++ b/test_regress/t/t_cover_trace_always.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_trace_always.v b/test_regress/t/t_cover_trace_always.v index 7c0175051..89fe43625 100644 --- a/test_regress/t/t_cover_trace_always.v +++ b/test_regress/t/t_cover_trace_always.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See bug5821 diff --git a/test_regress/t/t_cover_unused_bad.py b/test_regress/t/t_cover_unused_bad.py index 6818d8256..cc0bb1049 100755 --- a/test_regress/t/t_cover_unused_bad.py +++ b/test_regress/t/t_cover_unused_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cover_unused_bad.v b/test_regress/t/t_cover_unused_bad.v index c932ff440..f85b4a5f0 100644 --- a/test_regress/t/t_cover_unused_bad.v +++ b/test_regress/t/t_cover_unused_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_covergroup_args.py b/test_regress/t/t_covergroup_args.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_covergroup_args.py +++ b/test_regress/t/t_covergroup_args.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_args.v b/test_regress/t/t_covergroup_args.v index dad391a7e..ca8957a45 100644 --- a/test_regress/t/t_covergroup_args.v +++ b/test_regress/t/t_covergroup_args.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilator lint_off COVERIGN diff --git a/test_regress/t/t_covergroup_coverpoints_unsup.py b/test_regress/t/t_covergroup_coverpoints_unsup.py index e137e7309..7a4863922 100755 --- a/test_regress/t/t_covergroup_coverpoints_unsup.py +++ b/test_regress/t/t_covergroup_coverpoints_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_coverpoints_unsup.v b/test_regress/t/t_covergroup_coverpoints_unsup.v index 8bff89487..8a06ca3d6 100644 --- a/test_regress/t/t_covergroup_coverpoints_unsup.v +++ b/test_regress/t/t_covergroup_coverpoints_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_covergroup_extends.py b/test_regress/t/t_covergroup_extends.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_covergroup_extends.py +++ b/test_regress/t/t_covergroup_extends.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_extends.v b/test_regress/t/t_covergroup_extends.v index 68404631d..ddf547d28 100644 --- a/test_regress/t/t_covergroup_extends.v +++ b/test_regress/t/t_covergroup_extends.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_extends_newfirst.py b/test_regress/t/t_covergroup_extends_newfirst.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_covergroup_extends_newfirst.py +++ b/test_regress/t/t_covergroup_extends_newfirst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_extends_newfirst.v b/test_regress/t/t_covergroup_extends_newfirst.v index 62a2fe1d6..39a385529 100644 --- a/test_regress/t/t_covergroup_extends_newfirst.v +++ b/test_regress/t/t_covergroup_extends_newfirst.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_func_override_bad.py b/test_regress/t/t_covergroup_func_override_bad.py index e137e7309..7a4863922 100755 --- a/test_regress/t/t_covergroup_func_override_bad.py +++ b/test_regress/t/t_covergroup_func_override_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_func_override_bad.v b/test_regress/t/t_covergroup_func_override_bad.v index 927723573..ce1507536 100644 --- a/test_regress/t/t_covergroup_func_override_bad.v +++ b/test_regress/t/t_covergroup_func_override_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_in_class.py b/test_regress/t/t_covergroup_in_class.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_covergroup_in_class.py +++ b/test_regress/t/t_covergroup_in_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_in_class.v b/test_regress/t/t_covergroup_in_class.v index 5fe57773d..4ab0f383a 100644 --- a/test_regress/t/t_covergroup_in_class.v +++ b/test_regress/t/t_covergroup_in_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_in_class_colliding.py b/test_regress/t/t_covergroup_in_class_colliding.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_covergroup_in_class_colliding.py +++ b/test_regress/t/t_covergroup_in_class_colliding.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_in_class_colliding.v b/test_regress/t/t_covergroup_in_class_colliding.v index 1d9225f08..5760dc019 100644 --- a/test_regress/t/t_covergroup_in_class_colliding.v +++ b/test_regress/t/t_covergroup_in_class_colliding.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_in_class_duplicate_bad.out b/test_regress/t/t_covergroup_in_class_duplicate_bad.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_covergroup_in_class_duplicate_bad.py b/test_regress/t/t_covergroup_in_class_duplicate_bad.py index 59bdf12b5..dd4c4ea2d 100755 --- a/test_regress/t/t_covergroup_in_class_duplicate_bad.py +++ b/test_regress/t/t_covergroup_in_class_duplicate_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_in_class_duplicate_bad.v b/test_regress/t/t_covergroup_in_class_duplicate_bad.v index c7e7b94eb..2347e0ecd 100644 --- a/test_regress/t/t_covergroup_in_class_duplicate_bad.v +++ b/test_regress/t/t_covergroup_in_class_duplicate_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_in_class_with_sample.py b/test_regress/t/t_covergroup_in_class_with_sample.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_covergroup_in_class_with_sample.py +++ b/test_regress/t/t_covergroup_in_class_with_sample.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_in_class_with_sample.v b/test_regress/t/t_covergroup_in_class_with_sample.v index 0666f3457..df7a4611a 100644 --- a/test_regress/t/t_covergroup_in_class_with_sample.v +++ b/test_regress/t/t_covergroup_in_class_with_sample.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_method_bad.py b/test_regress/t/t_covergroup_method_bad.py index 25f9960b8..4d0f745d0 100755 --- a/test_regress/t/t_covergroup_method_bad.py +++ b/test_regress/t/t_covergroup_method_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_method_bad.v b/test_regress/t/t_covergroup_method_bad.v index 69723475d..77cb51f3b 100644 --- a/test_regress/t/t_covergroup_method_bad.v +++ b/test_regress/t/t_covergroup_method_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_covergroup_new_override_bad.py b/test_regress/t/t_covergroup_new_override_bad.py index e137e7309..7a4863922 100755 --- a/test_regress/t/t_covergroup_new_override_bad.py +++ b/test_regress/t/t_covergroup_new_override_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_new_override_bad.v b/test_regress/t/t_covergroup_new_override_bad.v index a215369e7..8a31bc11e 100644 --- a/test_regress/t/t_covergroup_new_override_bad.v +++ b/test_regress/t/t_covergroup_new_override_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_option.py b/test_regress/t/t_covergroup_option.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_covergroup_option.py +++ b/test_regress/t/t_covergroup_option.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_option.v b/test_regress/t/t_covergroup_option.v index 93d1b5871..e5b9e6339 100644 --- a/test_regress/t/t_covergroup_option.v +++ b/test_regress/t/t_covergroup_option.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_covergroup_option_bad.py b/test_regress/t/t_covergroup_option_bad.py index 25f9960b8..4d0f745d0 100755 --- a/test_regress/t/t_covergroup_option_bad.py +++ b/test_regress/t/t_covergroup_option_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_option_bad.v b/test_regress/t/t_covergroup_option_bad.v index e8a34d061..dbd33d866 100644 --- a/test_regress/t/t_covergroup_option_bad.v +++ b/test_regress/t/t_covergroup_option_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Verilator lint_off COVERIGN diff --git a/test_regress/t/t_covergroup_option_bad2.py b/test_regress/t/t_covergroup_option_bad2.py index 25f9960b8..4d0f745d0 100755 --- a/test_regress/t/t_covergroup_option_bad2.py +++ b/test_regress/t/t_covergroup_option_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_option_bad2.v b/test_regress/t/t_covergroup_option_bad2.v index 616aed372..b3f290cb1 100644 --- a/test_regress/t/t_covergroup_option_bad2.v +++ b/test_regress/t/t_covergroup_option_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Verilator lint_off COVERIGN diff --git a/test_regress/t/t_covergroup_unsup.out b/test_regress/t/t_covergroup_unsup.out index 1954b613b..963e36b49 100644 --- a/test_regress/t/t_covergroup_unsup.out +++ b/test_regress/t/t_covergroup_unsup.out @@ -243,154 +243,166 @@ %Warning-COVERIGN: t/t_covergroup_unsup.v:117:4: Ignoring unsupported: covergroup 117 | covergroup cg_binsoroptions_bk1; | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:151:23: Ignoring unsupported: coverage select expression 'binsof' - 151 | bins bin_a = binsof(a); +%Warning-COVERIGN: t/t_covergroup_unsup.v:150:26: Ignoring unsupported: cover bin 'with' specification + 150 | bins div_by_2 = a with (item % 2 == 0); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:151:34: Ignoring unsupported: cover bin 'with' specification + 151 | bins div_by_2_paren[] = a with (item % 2 == 0); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:149:6: Ignoring unsupported: coverpoint + 149 | coverpoint a { + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:148:4: Ignoring unsupported: covergroup + 148 | covergroup cg_coverpoint_ref; + | ^~~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:157:23: Ignoring unsupported: coverage select expression 'binsof' + 157 | bins bin_a = binsof(a); | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:151:10: Ignoring unsupported: coverage cross bin - 151 | bins bin_a = binsof(a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:152:24: Ignoring unsupported: coverage select expression 'binsof' - 152 | bins bin_ai = binsof(a) iff (!rst); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:152:34: Ignoring unsupported: cover 'iff' - 152 | bins bin_ai = binsof(a) iff (!rst); - | ^~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:152:10: Ignoring unsupported: coverage cross bin - 152 | bins bin_ai = binsof(a) iff (!rst); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:153:23: Ignoring unsupported: coverage select expression 'binsof' - 153 | bins bin_c = binsof(cp.x); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:153:10: Ignoring unsupported: coverage cross bin - 153 | bins bin_c = binsof(cp.x); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:154:24: Ignoring unsupported: coverage select expression 'binsof' - 154 | bins bin_na = ! binsof(a); - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:154:10: Ignoring unsupported: coverage cross bin - 154 | bins bin_na = ! binsof(a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:156:33: Ignoring unsupported: coverage select expression 'intersect' - 156 | bins bin_d = binsof(a) intersect { b }; - | ^~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:156:10: Ignoring unsupported: coverage cross bin - 156 | bins bin_d = binsof(a) intersect { b }; - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:157:34: Ignoring unsupported: coverage select expression 'intersect' - 157 | bins bin_nd = ! binsof(a) intersect { b }; - | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:157:10: Ignoring unsupported: coverage cross bin - 157 | bins bin_nd = ! binsof(a) intersect { b }; + 157 | bins bin_a = binsof(a); | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:159:23: Ignoring unsupported: coverage select expression with - 159 | bins bin_e = with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:159:10: Ignoring unsupported: coverage cross bin - 159 | bins bin_e = with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:160:27: Ignoring unsupported: coverage select expression with - 160 | bins bin_not_e = ! with (a); - | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:160:10: Ignoring unsupported: coverage cross bin - 160 | bins bin_not_e = ! with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:162:26: Ignoring unsupported: coverage select expression 'binsof' - 162 | bins bin_par = (binsof(a)); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:162:10: Ignoring unsupported: coverage cross bin - 162 | bins bin_par = (binsof(a)); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:163:25: Ignoring unsupported: coverage select expression 'binsof' - 163 | bins bin_and = binsof(a) && binsof(b); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:163:38: Ignoring unsupported: coverage select expression 'binsof' - 163 | bins bin_and = binsof(a) && binsof(b); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:163:35: Ignoring unsupported: coverage select expression '&&' - 163 | bins bin_and = binsof(a) && binsof(b); - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:163:10: Ignoring unsupported: coverage cross bin - 163 | bins bin_and = binsof(a) && binsof(b); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:164:24: Ignoring unsupported: coverage select expression 'binsof' - 164 | bins bin_or = binsof(a) || binsof(b); +%Warning-COVERIGN: t/t_covergroup_unsup.v:158:24: Ignoring unsupported: coverage select expression 'binsof' + 158 | bins bin_ai = binsof(a) iff (!rst); | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:164:37: Ignoring unsupported: coverage select expression 'binsof' - 164 | bins bin_or = binsof(a) || binsof(b); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:164:34: Ignoring unsupported: coverage select expression '||' - 164 | bins bin_or = binsof(a) || binsof(b); - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:164:10: Ignoring unsupported: coverage cross bin - 164 | bins bin_or = binsof(a) || binsof(b); +%Warning-COVERIGN: t/t_covergroup_unsup.v:158:34: Ignoring unsupported: cover 'iff' + 158 | bins bin_ai = binsof(a) iff (!rst); + | ^~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:158:10: Ignoring unsupported: coverage cross bin + 158 | bins bin_ai = binsof(a) iff (!rst); | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:165:26: Ignoring unsupported: coverage select expression 'binsof' - 165 | bins bin_with = binsof(a) with (a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:165:36: Ignoring unsupported: coverage select expression with - 165 | bins bin_with = binsof(a) with (a); - | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:159:23: Ignoring unsupported: coverage select expression 'binsof' + 159 | bins bin_c = binsof(cp.x); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:159:10: Ignoring unsupported: coverage cross bin + 159 | bins bin_c = binsof(cp.x); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:160:24: Ignoring unsupported: coverage select expression 'binsof' + 160 | bins bin_na = ! binsof(a); + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:160:10: Ignoring unsupported: coverage cross bin + 160 | bins bin_na = ! binsof(a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:162:33: Ignoring unsupported: coverage select expression 'intersect' + 162 | bins bin_d = binsof(a) intersect { b }; + | ^~~~~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:162:10: Ignoring unsupported: coverage cross bin + 162 | bins bin_d = binsof(a) intersect { b }; + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:163:34: Ignoring unsupported: coverage select expression 'intersect' + 163 | bins bin_nd = ! binsof(a) intersect { b }; + | ^ +%Warning-COVERIGN: t/t_covergroup_unsup.v:163:10: Ignoring unsupported: coverage cross bin + 163 | bins bin_nd = ! binsof(a) intersect { b }; + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:165:23: Ignoring unsupported: coverage select expression with + 165 | bins bin_e = with (a); + | ^~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:165:10: Ignoring unsupported: coverage cross bin - 165 | bins bin_with = binsof(a) with (a); + 165 | bins bin_e = with (a); | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:166:29: Ignoring unsupported: coverage select expression 'binsof' - 166 | bins bin_or_with = binsof(a) || binsof(a) with (a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:166:42: Ignoring unsupported: coverage select expression 'binsof' - 166 | bins bin_or_with = binsof(a) || binsof(a) with (a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:166:52: Ignoring unsupported: coverage select expression with - 166 | bins bin_or_with = binsof(a) || binsof(a) with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:166:39: Ignoring unsupported: coverage select expression '||' - 166 | bins bin_or_with = binsof(a) || binsof(a) with (a); - | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:166:27: Ignoring unsupported: coverage select expression with + 166 | bins bin_not_e = ! with (a); + | ^ %Warning-COVERIGN: t/t_covergroup_unsup.v:166:10: Ignoring unsupported: coverage cross bin - 166 | bins bin_or_with = binsof(a) || binsof(a) with (a); + 166 | bins bin_not_e = ! with (a); | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:167:30: Ignoring unsupported: coverage select expression 'binsof' - 167 | bins bin_and_with = binsof(a) && binsof(a) with (a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:167:43: Ignoring unsupported: coverage select expression 'binsof' - 167 | bins bin_and_with = binsof(a) && binsof(a) with (a); - | ^~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:167:53: Ignoring unsupported: coverage select expression with - 167 | bins bin_and_with = binsof(a) && binsof(a) with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:167:40: Ignoring unsupported: coverage select expression '&&' - 167 | bins bin_and_with = binsof(a) && binsof(a) with (a); - | ^~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:167:10: Ignoring unsupported: coverage cross bin - 167 | bins bin_and_with = binsof(a) && binsof(a) with (a); - | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:168:37: Ignoring unsupported: coverage select expression 'binsof' - 168 | bins bin_multiple_fields = binsof(p.inner_packet.field); - | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:168:26: Ignoring unsupported: coverage select expression 'binsof' + 168 | bins bin_par = (binsof(a)); + | ^~~~~~ %Warning-COVERIGN: t/t_covergroup_unsup.v:168:10: Ignoring unsupported: coverage cross bin - 168 | bins bin_multiple_fields = binsof(p.inner_packet.field); + 168 | bins bin_par = (binsof(a)); | ^~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:150:7: Ignoring unsupported: cover cross - 150 | cross a, b { +%Warning-COVERIGN: t/t_covergroup_unsup.v:169:25: Ignoring unsupported: coverage select expression 'binsof' + 169 | bins bin_and = binsof(a) && binsof(b); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:169:38: Ignoring unsupported: coverage select expression 'binsof' + 169 | bins bin_and = binsof(a) && binsof(b); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:169:35: Ignoring unsupported: coverage select expression '&&' + 169 | bins bin_and = binsof(a) && binsof(b); + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:169:10: Ignoring unsupported: coverage cross bin + 169 | bins bin_and = binsof(a) && binsof(b); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:170:24: Ignoring unsupported: coverage select expression 'binsof' + 170 | bins bin_or = binsof(a) || binsof(b); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:170:37: Ignoring unsupported: coverage select expression 'binsof' + 170 | bins bin_or = binsof(a) || binsof(b); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:170:34: Ignoring unsupported: coverage select expression '||' + 170 | bins bin_or = binsof(a) || binsof(b); + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:170:10: Ignoring unsupported: coverage cross bin + 170 | bins bin_or = binsof(a) || binsof(b); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:171:26: Ignoring unsupported: coverage select expression 'binsof' + 171 | bins bin_with = binsof(a) with (a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:171:36: Ignoring unsupported: coverage select expression with + 171 | bins bin_with = binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:171:10: Ignoring unsupported: coverage cross bin + 171 | bins bin_with = binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:172:29: Ignoring unsupported: coverage select expression 'binsof' + 172 | bins bin_or_with = binsof(a) || binsof(a) with (a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:172:42: Ignoring unsupported: coverage select expression 'binsof' + 172 | bins bin_or_with = binsof(a) || binsof(a) with (a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:172:52: Ignoring unsupported: coverage select expression with + 172 | bins bin_or_with = binsof(a) || binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:172:39: Ignoring unsupported: coverage select expression '||' + 172 | bins bin_or_with = binsof(a) || binsof(a) with (a); + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:172:10: Ignoring unsupported: coverage cross bin + 172 | bins bin_or_with = binsof(a) || binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:173:30: Ignoring unsupported: coverage select expression 'binsof' + 173 | bins bin_and_with = binsof(a) && binsof(a) with (a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:173:43: Ignoring unsupported: coverage select expression 'binsof' + 173 | bins bin_and_with = binsof(a) && binsof(a) with (a); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:173:53: Ignoring unsupported: coverage select expression with + 173 | bins bin_and_with = binsof(a) && binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:173:40: Ignoring unsupported: coverage select expression '&&' + 173 | bins bin_and_with = binsof(a) && binsof(a) with (a); + | ^~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:173:10: Ignoring unsupported: coverage cross bin + 173 | bins bin_and_with = binsof(a) && binsof(a) with (a); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:174:37: Ignoring unsupported: coverage select expression 'binsof' + 174 | bins bin_multiple_fields = binsof(p.inner_packet.field); + | ^~~~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:174:10: Ignoring unsupported: coverage cross bin + 174 | bins bin_multiple_fields = binsof(p.inner_packet.field); + | ^~~~ +%Warning-COVERIGN: t/t_covergroup_unsup.v:156:7: Ignoring unsupported: cover cross + 156 | cross a, b { | ^~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:149:4: Ignoring unsupported: covergroup - 149 | covergroup cg_cross_bins; +%Warning-COVERIGN: t/t_covergroup_unsup.v:155:4: Ignoring unsupported: covergroup + 155 | covergroup cg_cross_bins; | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:172:4: Ignoring unsupported: covergroup - 172 | covergroup cgArgs(int cg_lim); +%Warning-COVERIGN: t/t_covergroup_unsup.v:178:4: Ignoring unsupported: covergroup + 178 | covergroup cgArgs(int cg_lim); | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:179:23: Ignoring unsupported: coverage clocking event - 179 | covergroup cov1 @m_z; +%Warning-COVERIGN: t/t_covergroup_unsup.v:185:23: Ignoring unsupported: coverage clocking event + 185 | covergroup cov1 @m_z; | ^ -%Warning-COVERIGN: t/t_covergroup_unsup.v:180:10: Ignoring unsupported: coverpoint - 180 | coverpoint m_x; +%Warning-COVERIGN: t/t_covergroup_unsup.v:186:10: Ignoring unsupported: coverpoint + 186 | coverpoint m_x; | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:181:10: Ignoring unsupported: coverpoint - 181 | coverpoint m_y; +%Warning-COVERIGN: t/t_covergroup_unsup.v:187:10: Ignoring unsupported: coverpoint + 187 | coverpoint m_y; | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:179:7: Ignoring unsupported: covergroup - 179 | covergroup cov1 @m_z; +%Warning-COVERIGN: t/t_covergroup_unsup.v:185:7: Ignoring unsupported: covergroup + 185 | covergroup cov1 @m_z; | ^~~~~~~~~~ -%Warning-COVERIGN: t/t_covergroup_unsup.v:189:7: Ignoring unsupported: covergroup - 189 | covergroup extends cg_empty; +%Warning-COVERIGN: t/t_covergroup_unsup.v:195:7: Ignoring unsupported: covergroup + 195 | covergroup extends cg_empty; | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_covergroup_unsup.py b/test_regress/t/t_covergroup_unsup.py index 25f9960b8..4d0f745d0 100755 --- a/test_regress/t/t_covergroup_unsup.py +++ b/test_regress/t/t_covergroup_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_unsup.v b/test_regress/t/t_covergroup_unsup.v index d2b6db89d..dcdac2852 100644 --- a/test_regress/t/t_covergroup_unsup.v +++ b/test_regress/t/t_covergroup_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ @@ -143,7 +143,13 @@ module t (/*AUTOARG*/ { bins bts2 = ( 3 [->5:6] ) ; } { bins bts2 = ( 3 [=5] ) ; } { bins bts2 = ( 3 [=5:6] ) ; } + endgroup + covergroup cg_coverpoint_ref; + coverpoint a { + bins div_by_2 = a with (item % 2 == 0); + bins div_by_2_paren[] = a with (item % 2 == 0); + } endgroup covergroup cg_cross_bins; @@ -191,9 +197,9 @@ module t (/*AUTOARG*/ endclass initial begin - cg_empty cov1 = new; + automatic cg_empty cov1 = new; `ifndef T_COVERGROUP_UNSUP_IGN - cgArgs cov2 = new(2); + automatic cgArgs cov2 = new(2); `endif end diff --git a/test_regress/t/t_covergroup_unsup_ign.py b/test_regress/t/t_covergroup_unsup_ign.py index 363d55553..75107c00e 100755 --- a/test_regress/t/t_covergroup_unsup_ign.py +++ b/test_regress/t/t_covergroup_unsup_ign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_unsup_ign2.py b/test_regress/t/t_covergroup_unsup_ign2.py index 79faaec14..6efe69388 100755 --- a/test_regress/t/t_covergroup_unsup_ign2.py +++ b/test_regress/t/t_covergroup_unsup_ign2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_with_function_foo_bad.py b/test_regress/t/t_covergroup_with_function_foo_bad.py index 59bdf12b5..dd4c4ea2d 100755 --- a/test_regress/t/t_covergroup_with_function_foo_bad.py +++ b/test_regress/t/t_covergroup_with_function_foo_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_with_function_foo_bad.v b/test_regress/t/t_covergroup_with_function_foo_bad.v index c203e271e..5d4c91d33 100644 --- a/test_regress/t/t_covergroup_with_function_foo_bad.v +++ b/test_regress/t/t_covergroup_with_function_foo_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_with_sample_args.py b/test_regress/t/t_covergroup_with_sample_args.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_covergroup_with_sample_args.py +++ b/test_regress/t/t_covergroup_with_sample_args.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_with_sample_args.v b/test_regress/t/t_covergroup_with_sample_args.v index 4f45cbb57..a89b6de38 100644 --- a/test_regress/t/t_covergroup_with_sample_args.v +++ b/test_regress/t/t_covergroup_with_sample_args.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_with_sample_args_default.py b/test_regress/t/t_covergroup_with_sample_args_default.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_covergroup_with_sample_args_default.py +++ b/test_regress/t/t_covergroup_with_sample_args_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_with_sample_args_default.v b/test_regress/t/t_covergroup_with_sample_args_default.v index 878498a53..16ccf987b 100644 --- a/test_regress/t/t_covergroup_with_sample_args_default.v +++ b/test_regress/t/t_covergroup_with_sample_args_default.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_with_sample_args_too_few_bad.py b/test_regress/t/t_covergroup_with_sample_args_too_few_bad.py index 59bdf12b5..dd4c4ea2d 100755 --- a/test_regress/t/t_covergroup_with_sample_args_too_few_bad.py +++ b/test_regress/t/t_covergroup_with_sample_args_too_few_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_with_sample_args_too_few_bad.v b/test_regress/t/t_covergroup_with_sample_args_too_few_bad.v index bdee61669..f58dd1fe8 100644 --- a/test_regress/t/t_covergroup_with_sample_args_too_few_bad.v +++ b/test_regress/t/t_covergroup_with_sample_args_too_few_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_with_sample_args_too_many_bad.py b/test_regress/t/t_covergroup_with_sample_args_too_many_bad.py index 59bdf12b5..dd4c4ea2d 100755 --- a/test_regress/t/t_covergroup_with_sample_args_too_many_bad.py +++ b/test_regress/t/t_covergroup_with_sample_args_too_many_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_with_sample_args_too_many_bad.v b/test_regress/t/t_covergroup_with_sample_args_too_many_bad.v index 60ba2dc26..718188ae6 100644 --- a/test_regress/t/t_covergroup_with_sample_args_too_many_bad.v +++ b/test_regress/t/t_covergroup_with_sample_args_too_many_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_with_sample_namedargs.py b/test_regress/t/t_covergroup_with_sample_namedargs.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_covergroup_with_sample_namedargs.py +++ b/test_regress/t/t_covergroup_with_sample_namedargs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_with_sample_namedargs.v b/test_regress/t/t_covergroup_with_sample_namedargs.v index d8daa5437..0aa2c2e4e 100644 --- a/test_regress/t/t_covergroup_with_sample_namedargs.v +++ b/test_regress/t/t_covergroup_with_sample_namedargs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_covergroup_with_sample_zeroargs.py b/test_regress/t/t_covergroup_with_sample_zeroargs.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_covergroup_with_sample_zeroargs.py +++ b/test_regress/t/t_covergroup_with_sample_zeroargs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_covergroup_with_sample_zeroargs.v b/test_regress/t/t_covergroup_with_sample_zeroargs.v index e8b42e3f3..208a4e819 100644 --- a/test_regress/t/t_covergroup_with_sample_zeroargs.v +++ b/test_regress/t/t_covergroup_with_sample_zeroargs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ diff --git a/test_regress/t/t_cpure.py b/test_regress/t/t_cpure.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_cpure.py +++ b/test_regress/t/t_cpure.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cpure.v b/test_regress/t/t_cpure.v index 1fab00cbc..025b22e3f 100644 --- a/test_regress/t/t_cpure.v +++ b/test_regress/t/t_cpure.v @@ -2,8 +2,8 @@ // // Simple bi-directional transitive alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 function int func(); diff --git a/test_regress/t/t_cuse_forward.py b/test_regress/t/t_cuse_forward.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_cuse_forward.py +++ b/test_regress/t/t_cuse_forward.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_cuse_forward.v b/test_regress/t/t_cuse_forward.v index c1178a2d7..98f1f4995 100644 --- a/test_regress/t/t_cuse_forward.v +++ b/test_regress/t/t_cuse_forward.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Baz; diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out index e09dc1e14..aecca1cf7 100644 --- a/test_regress/t/t_debug_emitv.out +++ b/test_regress/t/t_debug_emitv.out @@ -33,6 +33,7 @@ module Vt_debug_emitv_t; function ident; input int signed value; begin : label0 + ident = /*CRESET*/; ident = value; disable label0; end @@ -125,6 +126,7 @@ module Vt_debug_emitv_t; initial begin begin : unnamedblk1 int signed other; + other = /*CRESET*/; begin begin : unnamedblk2 int signed i; @@ -290,6 +292,7 @@ module Vt_debug_emitv_t; sum = $random('sha); sum = $urandom(); sum = $urandom('sha); + sum = array.r_sum() with ((item * 'sh2)) ; if ((PKG_PARAM != 'sh1)) begin $stop; end @@ -653,7 +656,7 @@ module Vt_debug_emitv_t; begin : assert_intrinsic assert ((| $_EXPRSTMT( ao = (a); - , ); + , 32'h1); )) begin end else begin @@ -688,6 +691,7 @@ module Vt_debug_emitv_sub; task inc; input int signed i; output int signed o; + o = /*CRESET*/; o = ({32'h1{{1'h0, i[31:1]}}} + 32'h1); endtask function f; diff --git a/test_regress/t/t_debug_emitv.py b/test_regress/t/t_debug_emitv.py index c690916dc..b4f64ab37 100755 --- a/test_regress/t/t_debug_emitv.py +++ b/test_regress/t/t_debug_emitv.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_emitv.v b/test_regress/t/t_debug_emitv.v index e7915f47d..674b3537a 100644 --- a/test_regress/t/t_debug_emitv.v +++ b/test_regress/t/t_debug_emitv.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg; @@ -229,6 +229,8 @@ module t (/*AUTOARG*/ sum = $urandom; sum = $urandom(10); + sum = array.sum with (item * 2); + if (Pkg::PKG_PARAM != 1) $stop; sub.r = 62.0; diff --git a/test_regress/t/t_debug_emitv_addrids.py b/test_regress/t/t_debug_emitv_addrids.py index 84634c936..d6f139618 100755 --- a/test_regress/t/t_debug_emitv_addrids.py +++ b/test_regress/t/t_debug_emitv_addrids.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_exit_elab.py b/test_regress/t/t_debug_exit_elab.py index 837e2694f..0b91632b5 100755 --- a/test_regress/t/t_debug_exit_elab.py +++ b/test_regress/t/t_debug_exit_elab.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_exit_parse.py b/test_regress/t/t_debug_exit_parse.py index 51dded575..fed0e0003 100755 --- a/test_regress/t/t_debug_exit_parse.py +++ b/test_regress/t/t_debug_exit_parse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_fatalsrc_bad.py b/test_regress/t/t_debug_fatalsrc_bad.py index 9af7d79f1..a16c26aa1 100755 --- a/test_regress/t/t_debug_fatalsrc_bad.py +++ b/test_regress/t/t_debug_fatalsrc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_fatalsrc_bt_bad.py b/test_regress/t/t_debug_fatalsrc_bt_bad.py index aa8c484fb..9c3654ab8 100755 --- a/test_regress/t/t_debug_fatalsrc_bt_bad.py +++ b/test_regress/t/t_debug_fatalsrc_bt_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_gate.py b/test_regress/t/t_debug_gate.py index aa28d966e..a952ea027 100755 --- a/test_regress/t/t_debug_gate.py +++ b/test_regress/t/t_debug_gate.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_gate.v b/test_regress/t/t_debug_gate.v index 865e3f8ea..bb5eec667 100644 --- a/test_regress/t/t_debug_gate.v +++ b/test_regress/t/t_debug_gate.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_debug_graph_test.py b/test_regress/t/t_debug_graph_test.py index d88c7810b..2da8a6023 100755 --- a/test_regress/t/t_debug_graph_test.py +++ b/test_regress/t/t_debug_graph_test.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_graph_test.v b/test_regress/t/t_debug_graph_test.v index 9a259951f..8490acb3a 100644 --- a/test_regress/t/t_debug_graph_test.v +++ b/test_regress/t/t_debug_graph_test.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_debug_inputs.py b/test_regress/t/t_debug_inputs.py index 9f1e88804..d7dce552b 100755 --- a/test_regress/t/t_debug_inputs.py +++ b/test_regress/t/t_debug_inputs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_inputs.v b/test_regress/t/t_debug_inputs.v index c80142044..f251686ac 100644 --- a/test_regress/t/t_debug_inputs.v +++ b/test_regress/t/t_debug_inputs.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "t/t_debug_inputs_a.v" diff --git a/test_regress/t/t_debug_inputs_a.v b/test_regress/t/t_debug_inputs_a.v index 3af841409..58ffcab89 100644 --- a/test_regress/t/t_debug_inputs_a.v +++ b/test_regress/t/t_debug_inputs_a.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_debug_inputs_a; diff --git a/test_regress/t/t_debug_inputs_b.v b/test_regress/t/t_debug_inputs_b.v index 614de7579..ac20e361e 100644 --- a/test_regress/t/t_debug_inputs_b.v +++ b/test_regress/t/t_debug_inputs_b.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_debug_inputs_b; diff --git a/test_regress/t/t_debug_sigsegv_bad.py b/test_regress/t/t_debug_sigsegv_bad.py index 4a6710152..3421b823e 100755 --- a/test_regress/t/t_debug_sigsegv_bad.py +++ b/test_regress/t/t_debug_sigsegv_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_sigsegv_bt_bad.py b/test_regress/t/t_debug_sigsegv_bt_bad.py index da77759a5..3865841b9 100755 --- a/test_regress/t/t_debug_sigsegv_bt_bad.py +++ b/test_regress/t/t_debug_sigsegv_bt_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_trace.py b/test_regress/t/t_debug_trace.py index fddb42972..beaa9f09f 100755 --- a/test_regress/t/t_debug_trace.py +++ b/test_regress/t/t_debug_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_debug_trace.v b/test_regress/t/t_debug_trace.v index 36ce9c551..f1656701e 100644 --- a/test_regress/t/t_debug_trace.v +++ b/test_regress/t/t_debug_trace.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_debug_width.py b/test_regress/t/t_debug_width.py index 6a7313070..45a700fcb 100755 --- a/test_regress/t/t_debug_width.py +++ b/test_regress/t/t_debug_width.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_define_override.py b/test_regress/t/t_define_override.py index 97130569b..8ac381e6e 100755 --- a/test_regress/t/t_define_override.py +++ b/test_regress/t/t_define_override.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_define_override.v b/test_regress/t/t_define_override.v index 5ffb45cb7..aec0778da 100644 --- a/test_regress/t/t_define_override.v +++ b/test_regress/t/t_define_override.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Multiple `defines while using +define+ // as a command-line argument as well // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define TEST_MACRO 10 diff --git a/test_regress/t/t_define_override_empty.py b/test_regress/t/t_define_override_empty.py index 9fef50046..75d9e174e 100755 --- a/test_regress/t/t_define_override_empty.py +++ b/test_regress/t/t_define_override_empty.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_define_override_output.py b/test_regress/t/t_define_override_output.py index 6244ac55a..4c3ed92dc 100755 --- a/test_regress/t/t_define_override_output.py +++ b/test_regress/t/t_define_override_output.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_delay.py b/test_regress/t/t_delay.py index 231b3a573..614ab80c6 100755 --- a/test_regress/t/t_delay.py +++ b/test_regress/t/t_delay.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_delay.v b/test_regress/t/t_delay.v index 9f1cb5420..241d67644 100644 --- a/test_regress/t/t_delay.v +++ b/test_regress/t/t_delay.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 100ns/1ns diff --git a/test_regress/t/t_delay_1step.py b/test_regress/t/t_delay_1step.py index 671072f97..93e1f30e1 100755 --- a/test_regress/t/t_delay_1step.py +++ b/test_regress/t/t_delay_1step.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_delay_1step.v b/test_regress/t/t_delay_1step.v index c8f33d7d4..9cea059f0 100644 --- a/test_regress/t/t_delay_1step.v +++ b/test_regress/t/t_delay_1step.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_delay_compare.py b/test_regress/t/t_delay_compare.py index 9185571ea..9b8d8f041 100755 --- a/test_regress/t/t_delay_compare.py +++ b/test_regress/t/t_delay_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_delay_compare.v b/test_regress/t/t_delay_compare.v index b42a887d9..31723d1be 100644 --- a/test_regress/t/t_delay_compare.v +++ b/test_regress/t/t_delay_compare.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; @@ -10,6 +10,7 @@ module t; real rtim1; real rtim2; + // verilator lint_off ZERODLY initial begin tim1 = 2; tim2 = 3; @@ -31,5 +32,6 @@ module t; $write("*-* All Finished *-*\n"); $finish; end + // verilator lint_on ZERODLY endmodule diff --git a/test_regress/t/t_delay_incr.py b/test_regress/t/t_delay_incr.py index 621069809..988e85297 100755 --- a/test_regress/t/t_delay_incr.py +++ b/test_regress/t/t_delay_incr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_delay_incr.v b/test_regress/t/t_delay_incr.v index 2ba72abea..8242d5f92 100644 --- a/test_regress/t/t_delay_incr.v +++ b/test_regress/t/t_delay_incr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 100ns/1ns diff --git a/test_regress/t/t_delay_incr_timing.py b/test_regress/t/t_delay_incr_timing.py index f9892e531..0537dc2a5 100755 --- a/test_regress/t/t_delay_incr_timing.py +++ b/test_regress/t/t_delay_incr_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_delay_stmtdly_bad.py b/test_regress/t/t_delay_stmtdly_bad.py index a542f3311..2a313ca42 100755 --- a/test_regress/t/t_delay_stmtdly_bad.py +++ b/test_regress/t/t_delay_stmtdly_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_delay_timing.py b/test_regress/t/t_delay_timing.py index bcaa61195..859b85f99 100755 --- a/test_regress/t/t_delay_timing.py +++ b/test_regress/t/t_delay_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_delay_var.py b/test_regress/t/t_delay_var.py index 9185571ea..9b8d8f041 100755 --- a/test_regress/t/t_delay_var.py +++ b/test_regress/t/t_delay_var.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_delay_var.v b/test_regress/t/t_delay_var.v index e9382f469..a74b0857a 100644 --- a/test_regress/t/t_delay_var.v +++ b/test_regress/t/t_delay_var.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_depth_flop.py b/test_regress/t/t_depth_flop.py index a38d51df9..0c191b8c9 100755 --- a/test_regress/t/t_depth_flop.py +++ b/test_regress/t/t_depth_flop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_depth_flop.v b/test_regress/t/t_depth_flop.v index f6aa674c0..fd4f80dc0 100644 --- a/test_regress/t/t_depth_flop.v +++ b/test_regress/t/t_depth_flop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_detectarray_1.py b/test_regress/t/t_detectarray_1.py index 51e61aa39..0bed5b40c 100755 --- a/test_regress/t/t_detectarray_1.py +++ b/test_regress/t/t_detectarray_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_detectarray_1.v b/test_regress/t/t_detectarray_1.v index df266bb06..d0e4b2927 100644 --- a/test_regress/t/t_detectarray_1.v +++ b/test_regress/t/t_detectarray_1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Simple test of unoptflat // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; diff --git a/test_regress/t/t_detectarray_2.py b/test_regress/t/t_detectarray_2.py index 51e61aa39..0bed5b40c 100755 --- a/test_regress/t/t_detectarray_2.py +++ b/test_regress/t/t_detectarray_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_detectarray_2.v b/test_regress/t/t_detectarray_2.v index 141fc500e..2694efdb2 100644 --- a/test_regress/t/t_detectarray_2.v +++ b/test_regress/t/t_detectarray_2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Simple test of unoptflat // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; diff --git a/test_regress/t/t_detectarray_3.py b/test_regress/t/t_detectarray_3.py index 979bfb85d..c4cba146d 100755 --- a/test_regress/t/t_detectarray_3.py +++ b/test_regress/t/t_detectarray_3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_detectarray_3.v b/test_regress/t/t_detectarray_3.v index 07e7c1be2..fe0060533 100644 --- a/test_regress/t/t_detectarray_3.v +++ b/test_regress/t/t_detectarray_3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Simple test of unoptflat // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Jie Xu // SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; diff --git a/test_regress/t/t_dfg_3676.py b/test_regress/t/t_dfg_3676.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_dfg_3676.py +++ b/test_regress/t/t_dfg_3676.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_3676.v b/test_regress/t/t_dfg_3676.v index 8f01e471a..fdc6cb2b8 100644 --- a/test_regress/t/t_dfg_3676.v +++ b/test_regress/t/t_dfg_3676.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNOPTFLAT diff --git a/test_regress/t/t_dfg_3679.py b/test_regress/t/t_dfg_3679.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_dfg_3679.py +++ b/test_regress/t/t_dfg_3679.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_3679.v b/test_regress/t/t_dfg_3679.v index 206dd4691..f9b336625 100644 --- a/test_regress/t/t_dfg_3679.v +++ b/test_regress/t/t_dfg_3679.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_dfg_3726.py b/test_regress/t/t_dfg_3726.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_dfg_3726.py +++ b/test_regress/t/t_dfg_3726.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_3726.v b/test_regress/t/t_dfg_3726.v index 8331d8b95..3009d7545 100644 --- a/test_regress/t/t_dfg_3726.v +++ b/test_regress/t/t_dfg_3726.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_dfg_3817.py b/test_regress/t/t_dfg_3817.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_dfg_3817.py +++ b/test_regress/t/t_dfg_3817.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_3817.v b/test_regress/t/t_dfg_3817.v index 043142ab7..233a27b4f 100644 --- a/test_regress/t/t_dfg_3817.v +++ b/test_regress/t/t_dfg_3817.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #3817 // addDriver() was causing use-after-free and segfaulting during Verilation // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Jevin Sweval. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Jevin Sweval // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_dfg_3872.py b/test_regress/t/t_dfg_3872.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_dfg_3872.py +++ b/test_regress/t/t_dfg_3872.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_3872.v b/test_regress/t/t_dfg_3872.v index 2a7b0617a..3ce591f4b 100644 --- a/test_regress/t/t_dfg_3872.v +++ b/test_regress/t/t_dfg_3872.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Geza Lore // SPDX-License-Identifier: CC0-1.0 module top( diff --git a/test_regress/t/t_dfg_4943.py b/test_regress/t/t_dfg_4943.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_dfg_4943.py +++ b/test_regress/t/t_dfg_4943.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_4943.v b/test_regress/t/t_dfg_4943.v index 18f67606a..7546225a4 100644 --- a/test_regress/t/t_dfg_4943.v +++ b/test_regress/t/t_dfg_4943.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module top(input wire i, output wire o); diff --git a/test_regress/t/t_dfg_bin_to_one_hot.py b/test_regress/t/t_dfg_bin_to_one_hot.py index ef6de6244..9eba4ddc2 100755 --- a/test_regress/t/t_dfg_bin_to_one_hot.py +++ b/test_regress/t/t_dfg_bin_to_one_hot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_bin_to_one_hot.v b/test_regress/t/t_dfg_bin_to_one_hot.v index 260a0a78c..dad77a90f 100644 --- a/test_regress/t/t_dfg_bin_to_one_hot.v +++ b/test_regress/t/t_dfg_bin_to_one_hot.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_dfg_break_cycles.cpp b/test_regress/t/t_dfg_break_cycles.cpp index 0664397e1..d8bffdbaf 100644 --- a/test_regress/t/t_dfg_break_cycles.cpp +++ b/test_regress/t/t_dfg_break_cycles.cpp @@ -1,8 +1,8 @@ // // DESCRIPTION: Verilator: DFG optimizer equivalence testing // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_dfg_break_cycles.py b/test_regress/t/t_dfg_break_cycles.py index ab57b5b8e..583627873 100755 --- a/test_regress/t/t_dfg_break_cycles.py +++ b/test_regress/t/t_dfg_break_cycles.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_break_cycles.v b/test_regress/t/t_dfg_break_cycles.v index a123ca3b9..ec4c1599e 100644 --- a/test_regress/t/t_dfg_break_cycles.v +++ b/test_regress/t/t_dfg_break_cycles.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Geza Lore // SPDX-License-Identifier: CC0-1.0 `define signal(name, width) wire [width-1:0] name diff --git a/test_regress/t/t_dfg_circular.py b/test_regress/t/t_dfg_circular.py index ce29ad309..ed0001b8e 100755 --- a/test_regress/t/t_dfg_circular.py +++ b/test_regress/t/t_dfg_circular.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_circular.v b/test_regress/t/t_dfg_circular.v index 3d8e51f3a..f77c7fa98 100644 --- a/test_regress/t/t_dfg_circular.v +++ b/test_regress/t/t_dfg_circular.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNOPTFLAT diff --git a/test_regress/t/t_dfg_circular_merged_scc.py b/test_regress/t/t_dfg_circular_merged_scc.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_dfg_circular_merged_scc.py +++ b/test_regress/t/t_dfg_circular_merged_scc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_circular_merged_scc.v b/test_regress/t/t_dfg_circular_merged_scc.v index 9f976e0b4..2c19b08d1 100644 --- a/test_regress/t/t_dfg_circular_merged_scc.v +++ b/test_regress/t/t_dfg_circular_merged_scc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Geza Lore // SPDX-License-Identifier: CC0-1.0 module mul ( diff --git a/test_regress/t/t_dfg_inline_forced.py b/test_regress/t/t_dfg_inline_forced.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_dfg_inline_forced.py +++ b/test_regress/t/t_dfg_inline_forced.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_inline_forced.v b/test_regress/t/t_dfg_inline_forced.v index 7ba47864f..2de16d1b9 100644 --- a/test_regress/t/t_dfg_inline_forced.v +++ b/test_regress/t/t_dfg_inline_forced.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module top(input wire clk); diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.py b/test_regress/t/t_dfg_multidriver_dfg_bad.py index cdd7fb345..2b3ca29ee 100755 --- a/test_regress/t/t_dfg_multidriver_dfg_bad.py +++ b/test_regress/t/t_dfg_multidriver_dfg_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.v b/test_regress/t/t_dfg_multidriver_dfg_bad.v index d42e66fa1..0c629eae7 100644 --- a/test_regress/t/t_dfg_multidriver_dfg_bad.v +++ b/test_regress/t/t_dfg_multidriver_dfg_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 `default_nettype none diff --git a/test_regress/t/t_dfg_multidriver_non_dfg.py b/test_regress/t/t_dfg_multidriver_non_dfg.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_dfg_multidriver_non_dfg.py +++ b/test_regress/t/t_dfg_multidriver_non_dfg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_multidriver_non_dfg.v b/test_regress/t/t_dfg_multidriver_non_dfg.v index 9fcb61b5e..d3112693f 100644 --- a/test_regress/t/t_dfg_multidriver_non_dfg.v +++ b/test_regress/t/t_dfg_multidriver_non_dfg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 `default_nettype none diff --git a/test_regress/t/t_dfg_oob_sel_rvalue.py b/test_regress/t/t_dfg_oob_sel_rvalue.py index ed0e2a16e..7c1ccefb2 100755 --- a/test_regress/t/t_dfg_oob_sel_rvalue.py +++ b/test_regress/t/t_dfg_oob_sel_rvalue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_oob_sel_rvalue.v b/test_regress/t/t_dfg_oob_sel_rvalue.v index e27ad0333..43d3b87b9 100644 --- a/test_regress/t/t_dfg_oob_sel_rvalue.v +++ b/test_regress/t/t_dfg_oob_sel_rvalue.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_dfg_peephole.cpp b/test_regress/t/t_dfg_peephole.cpp index deb7da096..9508c7d75 100644 --- a/test_regress/t/t_dfg_peephole.cpp +++ b/test_regress/t/t_dfg_peephole.cpp @@ -1,8 +1,8 @@ // // DESCRIPTION: Verilator: DFG optimizer equivalence testing // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_dfg_peephole.py b/test_regress/t/t_dfg_peephole.py index 6dab26d98..71833c22c 100755 --- a/test_regress/t/t_dfg_peephole.py +++ b/test_regress/t/t_dfg_peephole.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_peephole.v b/test_regress/t/t_dfg_peephole.v index 73d3bd635..0b182343b 100644 --- a/test_regress/t/t_dfg_peephole.v +++ b/test_regress/t/t_dfg_peephole.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 `define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr @@ -245,6 +245,12 @@ module t ( end `signal(PUSH_SEL_THROUGH_SPLICE, sel_from_partial_tmp[1:0]); + `signal(PUSH_CONCAT_THROUGH_COND_LHS, {5'd0, rand_a[0] ? {rand_b[4], 1'b0} : {1'b0, rand_b[6]}}); + `signal(PUSH_CONCAT_THROUGH_COND_RHS, {rand_a[0] ? {rand_b[5], 1'b0} : {1'b0, rand_b[7]}, 5'd0}); + + `signal(REPLACE_SHIFTL_CAT, {31'd0, rand_a[42 +: 7]} << 31); + `signal(REPLACE_SHIFTRL_CAT, {rand_a[13 +: 7], rand_b[8 +: 27]} >> 27 << 27); + // Asscending ranges `signal(ASCENDNG_SEL, arand_a[0:4]); // verilator lint_off ASCRANGE @@ -264,6 +270,12 @@ module t ( wire sel_from_not = sel_from_not_tmp[2]; always @(posedge randbit_a) if ($c(0)) $display(sel_from_not); // Do not remove signal + // Narrow concatenation + wire [9:0] narrow_concat = {5'd0, ~rand_a[44 +: 5]}; + `signal(NARROW_CONCAT_A, narrow_concat[5:1]); + `signal(NARROW_CONCAT_B, narrow_concat[8:4]); + `signal(NARROW_CONCAT_C, narrow_concat[5:4]); + // Assigned at the end to avoid inlining by other passes assign const_a = 64'h0123456789abcdef; assign const_b = 64'h98badefc10325647; diff --git a/test_regress/t/t_dfg_peephole_off_all.py b/test_regress/t/t_dfg_peephole_off_all.py index 534bb7a6e..61d349322 100755 --- a/test_regress/t/t_dfg_peephole_off_all.py +++ b/test_regress/t/t_dfg_peephole_off_all.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_peephole_off_each.py b/test_regress/t/t_dfg_peephole_off_each.py index 534bb7a6e..61d349322 100755 --- a/test_regress/t/t_dfg_peephole_off_each.py +++ b/test_regress/t/t_dfg_peephole_off_each.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_push_sel.py b/test_regress/t/t_dfg_push_sel.py new file mode 100755 index 000000000..5e23ff9b3 --- /dev/null +++ b/test_regress/t/t_dfg_push_sel.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile(verilator_flags2=[ + "--binary", "--stats", "-fno-dfg-pre-inline", "-fno-dfg-post-inline", "-fno-dfg-peephole" +]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, DFG scoped PushDownSels, sels pushed down\s+(\d+)', + 49) + test.file_grep(test.stats, r'Optimizations, DFG scoped PushDownSels, would be cyclic\s+(\d+)', + 1) + +test.passes() diff --git a/test_regress/t/t_dfg_push_sel.v b/test_regress/t/t_dfg_push_sel.v new file mode 100644 index 000000000..0b1ef0f05 --- /dev/null +++ b/test_regress/t/t_dfg_push_sel.v @@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +module t; + + bit clk = 1'b0; + always #5 clk = ~clk; + + logic [63:0] crc = 64'h5aef0c8d_d70a4497; + + localparam N = 16; + + // Generate variables + for (genvar n = 0; n < N; ++n) begin : vars + logic [n:0] tmp; + logic out; + end + + // Generate logic + for (genvar n = 0; n < N; ++n) begin + if (n == 0) begin + assign vars[n].tmp = ~crc[n]; + assign vars[n].out = vars[n].tmp[n]; + end + else begin + assign vars[n].tmp = {~crc[n], vars[n-1].tmp}; + assign vars[n].out = vars[n].tmp[n] ^ vars[n-1].out; + end + end + + // Would create cycle: + wire [3:0] danger_src = {crc[4:3], crc[1:0]}; + wire [1:0] danger_sel = danger_src[2:1]; + wire [5:0] danger_dst = {~danger_sel, danger_src}; + + // Sink has no other sinks + wire [3:0] noother_src = {crc[5:4], crc[2:1]}; + wire [1:0] noother_sel = noother_src[2:1]; + wire [7:0] noother_dst = {crc[9:6], noother_src}; // singal intentianally unused + + int cyc; + always @(posedge clk) begin + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + //$display("%16b %16b", ~crc[N-1:0], vars[N-1].tmp); + //$display("%16b %16b", ^(~crc[N-1:0]), vars[N-1].out); + // Check halfway through, this prevents pushing sels past this point + `checkh(vars[N/2].tmp, ~crc[N/2:0]); + `checkh(vars[N/2].out, ^(~crc[N/2:0])); + // Check final value + `checkh(vars[N-1].tmp, ~crc[N-1:0]); + `checkh(vars[N-1].out, ^(~crc[N-1:0])); + if (cyc == 10) begin + // Observe danger_dst so it's not eliminated + $display("%0b", danger_dst); + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_dfg_push_sel_off.py b/test_regress/t/t_dfg_push_sel_off.py new file mode 100755 index 000000000..14b54340f --- /dev/null +++ b/test_regress/t/t_dfg_push_sel_off.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.top_filename = "t/t_dfg_push_sel.v" + +test.compile(verilator_flags2=[ + "--binary", "--stats", "-fno-dfg-pre-inline", "-fno-dfg-post-inline", "-fno-dfg-peephole", + "-fno-dfg-push-down-sels" +]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, DFG scoped PushDownSels, sels pushed down\s+(\d+)', + 0) + test.file_grep(test.stats, r'Optimizations, DFG scoped PushDownSels, would be cyclic\s+(\d+)', + 0) + +test.passes() diff --git a/test_regress/t/t_dfg_regularize_circular.py b/test_regress/t/t_dfg_regularize_circular.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_dfg_regularize_circular.py +++ b/test_regress/t/t_dfg_regularize_circular.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_regularize_circular.v b/test_regress/t/t_dfg_regularize_circular.v index 840f8d774..ca56732e7 100644 --- a/test_regress/t/t_dfg_regularize_circular.v +++ b/test_regress/t/t_dfg_regularize_circular.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module A ( diff --git a/test_regress/t/t_dfg_regularize_clk.py b/test_regress/t/t_dfg_regularize_clk.py index 4ee18ef12..63315cbc5 100755 --- a/test_regress/t/t_dfg_regularize_clk.py +++ b/test_regress/t/t_dfg_regularize_clk.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_regularize_clk.v b/test_regress/t/t_dfg_regularize_clk.v index 4dc240b79..a3a0ad64b 100644 --- a/test_regress/t/t_dfg_regularize_clk.v +++ b/test_regress/t/t_dfg_regularize_clk.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_dfg_regularize_driver_of_sc_var.py b/test_regress/t/t_dfg_regularize_driver_of_sc_var.py index 01c227501..1175ee8cc 100755 --- a/test_regress/t/t_dfg_regularize_driver_of_sc_var.py +++ b/test_regress/t/t_dfg_regularize_driver_of_sc_var.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_regularize_driver_of_sc_var.v b/test_regress/t/t_dfg_regularize_driver_of_sc_var.v index 507d9adf1..eedc4c76b 100644 --- a/test_regress/t/t_dfg_regularize_driver_of_sc_var.v +++ b/test_regress/t/t_dfg_regularize_driver_of_sc_var.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub(input in, output out); diff --git a/test_regress/t/t_dfg_result_var_ext_write.py b/test_regress/t/t_dfg_result_var_ext_write.py index aa5dacc93..3c6aa8922 100755 --- a/test_regress/t/t_dfg_result_var_ext_write.py +++ b/test_regress/t/t_dfg_result_var_ext_write.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_result_var_ext_write.v b/test_regress/t/t_dfg_result_var_ext_write.v index 3c41156bf..e50a267ea 100644 --- a/test_regress/t/t_dfg_result_var_ext_write.v +++ b/test_regress/t/t_dfg_result_var_ext_write.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_dfg_stats_patterns.v b/test_regress/t/t_dfg_stats_patterns.v index ac78a5da3..d539ea165 100644 --- a/test_regress/t/t_dfg_stats_patterns.v +++ b/test_regress/t/t_dfg_stats_patterns.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_dfg_stats_patterns_post_inline.out b/test_regress/t/t_dfg_stats_patterns_post_inline.out index 5984277cd..993127bf2 100644 --- a/test_regress/t/t_dfg_stats_patterns_post_inline.out +++ b/test_regress/t/t_dfg_stats_patterns_post_inline.out @@ -1,96 +1,98 @@ DFG 'post inline' patterns with depth 1 9 (CONCAT _A:1 _B:a):b 8 (REDXOR _A:a):1 - 3 (AND _A:a _B:a)*:a 3 (NOT vA:a)*:a - 2 (REPLICATE _A:a cA:a)*:b - 1 (CONCAT '0:a _A:b):A + 2 (AND _A:a _B:a):a + 1 (AND _A:a _B:a)*:a 1 (CONCAT _A:1 _B:1):a 1 (NOT _A:a):a 1 (REDXOR _A:a)*:1 1 (REPLICATE _A:1 cA:a)*:b + 1 (REPLICATE _A:a cA:a)*:b + 1 (REPLICATE _A:a cA:a):b 1 (REPLICATE _A:a cA:b)*:b 1 (REPLICATE _A:a cA:b)*:c - 1 (SEL@0 _A:a)*:1 - 1 (SEL@0 _A:a)*:b + 1 (SEL@0 _A:a):1 + 1 (SEL@0 _A:a):b 1 (SEL@A _A:a):1 DFG 'post inline' patterns with depth 2 6 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:b):c):d - 3 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a - 3 (REDXOR (AND _A:a _B:a)*:a):1 - 1 (CONCAT '0:a (REPLICATE _A:a cA:a)*:b):A + 2 (AND (NOT vA:a)*:a (NOT vB:a)*:a):a + 2 (REDXOR (AND _A:a _B:a):a):1 + 1 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a 1 (CONCAT (REDXOR _A:a)*:1 (CONCAT _B:1 _C:b):c):d 1 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:1):b):c 1 (CONCAT (REDXOR _A:a):1 (REDXOR _B:b)*:1):c - 1 (CONCAT (SEL@0 _A:a)*:1 (CONCAT _B:1 _C:b):c):d + 1 (CONCAT (SEL@0 _A:a):1 (CONCAT _B:1 _C:b):c):d 1 (NOT (REPLICATE _A:a cA:b)*:b):b + 1 (REDXOR (AND _A:a _B:a)*:a):1 1 (REDXOR (REPLICATE _A:1 cA:a)*:b):1 - 1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 1 (REDXOR (REPLICATE _A:a cA:a)*:b):1 + 1 (REDXOR (REPLICATE _A:a cA:a):b)*:1 1 (REDXOR (REPLICATE _A:a cA:b)*:b):1 1 (REDXOR (REPLICATE _A:a cA:b)*:c):1 - 1 (REDXOR (SEL@0 _A:a)*:b):1 + 1 (REDXOR (SEL@0 _A:a):b):1 1 (REPLICATE (NOT _A:a):a cA:a)*:b 1 (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c - 1 (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c + 1 (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b):c 1 (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b 1 (REPLICATE (SEL@A _A:a):1 cA:b)*:c - 1 (SEL@0 (AND _A:a _B:a)*:a)*:1 - 1 (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c + 1 (SEL@0 (AND _A:a _B:a)*:a):1 + 1 (SEL@0 (REPLICATE _A:a cA:a)*:b):c 1 (SEL@A (AND _A:a _B:a)*:a):1 DFG 'post inline' patterns with depth 3 - 3 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 - 2 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e - 1 (CONCAT '0:a (REPLICATE (REPLICATE _A:b cA:a)*:a cA:a)*:c):A - 1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e + 2 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a):a):1 + 1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e + 1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e + 1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (SEL@0 _C:a):1 (CONCAT _D:1 _E:b):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:1 cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (CONCAT _C:1 _D:d):e):f):g - 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:1):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (REDXOR _C:b)*:1):d):e + 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a):b)*:1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:1):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:b):1 (CONCAT (REDXOR _B:c)*:1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:c):1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:d):e):f):g - 1 (CONCAT (REDXOR (SEL@0 _A:a)*:b):1 (REDXOR (REPLICATE _B:c cA:c)*:a)*:1):d - 1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b + 1 (CONCAT (REDXOR (SEL@0 _A:a):b):1 (REDXOR (REPLICATE _B:c cA:c):a)*:1):d + 1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b 1 (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b + 1 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 1 (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 1 (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 - 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 + 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b):c)*:1 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 1 (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 - 1 (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 + 1 (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b):c):1 1 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c 1 (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a - 1 (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d + 1 (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b):d 1 (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c - 1 (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 - 1 (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c + 1 (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 + 1 (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b):c 1 (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 DFG 'post inline' patterns with depth 4 - 1 (CONCAT '0:a (REPLICATE (REPLICATE (REPLICATE _A:b cA:a)*:c cA:a)*:a cA:a)*:d):A - 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f - 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e):f - 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b):f - 1 (CONCAT (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 (CONCAT (REDXOR (SEL@0 _B:b)*:c):1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1):d):e + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a):a):1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (SEL@0 _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a):a):1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b):f + 1 (CONCAT (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 (CONCAT (REDXOR (SEL@0 _B:b):c):1 (REDXOR (REPLICATE _A:a cA:a):b)*:1):d):e 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:a)*:a):1 (CONCAT (REDXOR _C:d)*:1 (CONCAT _D:1 _E:e):f):g):h):i - 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:c):1 (CONCAT (REDXOR _C:d):1 (REDXOR _D:c)*:1):e):f):g - 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:d)*:1 (CONCAT (REDXOR _C:d):1 (CONCAT _D:1 _E:1):e):f):g):h + 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b):c)*:1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:c):1 (CONCAT (REDXOR _C:d):1 (REDXOR _D:c)*:1):e):f):g + 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 (CONCAT (REDXOR (REPLICATE _B:b cA:b):d)*:1 (CONCAT (REDXOR _C:d):1 (CONCAT _D:1 _E:1):e):f):g):h 1 (CONCAT (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:b)*:d):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:e):a):f):g):h - 1 (CONCAT (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 (REDXOR (REPLICATE (REPLICATE _B:d cA:a)*:a cA:a)*:b)*:1):e - 1 (CONCAT (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 (CONCAT (REDXOR (REPLICATE _A:1 cA:b)*:c):1 (CONCAT (REDXOR _B:d):1 (CONCAT _C:1 _D:a):e):f):g):c + 1 (CONCAT (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b):c):1 (REDXOR (REPLICATE (REPLICATE _B:d cA:a)*:a cA:a):b)*:1):e + 1 (CONCAT (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (REPLICATE _A:1 cA:b)*:c):1 (CONCAT (REDXOR _B:d):1 (CONCAT _C:1 _D:a):e):f):g):c 1 (NOT (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):a 1 (REDXOR (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c):1 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):1 - 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d)*:1 + 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b):d)*:1 1 (REDXOR (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d):1 1 (REDXOR (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c):1 - 1 (REDXOR (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c):1 + 1 (REDXOR (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b):c):1 1 (REPLICATE (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b cA:b)*:d - 1 (REPLICATE (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a cB:a)*:d + 1 (REPLICATE (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a cB:a):d 1 (REPLICATE (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d cB:b)*:b 1 (REPLICATE (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 cA:b)*:c - 1 (SEL@0 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c)*:d + 1 (SEL@0 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c):d diff --git a/test_regress/t/t_dfg_stats_patterns_post_inline.py b/test_regress/t/t_dfg_stats_patterns_post_inline.py index 329b7557b..afe7bc2ca 100755 --- a/test_regress/t/t_dfg_stats_patterns_post_inline.py +++ b/test_regress/t/t_dfg_stats_patterns_post_inline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_stats_patterns_pre_inline.out b/test_regress/t/t_dfg_stats_patterns_pre_inline.out index a34f6037c..f7b216e9b 100644 --- a/test_regress/t/t_dfg_stats_patterns_pre_inline.out +++ b/test_regress/t/t_dfg_stats_patterns_pre_inline.out @@ -1,96 +1,98 @@ DFG 'pre inline' patterns with depth 1 9 (CONCAT _A:1 _B:a):b 8 (REDXOR _A:a):1 - 3 (AND _A:a _B:a)*:a 3 (NOT vA:a)*:a - 2 (REPLICATE _A:a cA:a)*:b - 1 (CONCAT '0:a _A:b):A + 2 (AND _A:a _B:a):a + 1 (AND _A:a _B:a)*:a 1 (CONCAT _A:1 _B:1):a 1 (NOT _A:a):a 1 (REDXOR _A:a)*:1 1 (REPLICATE _A:1 cA:a)*:b + 1 (REPLICATE _A:a cA:a)*:b + 1 (REPLICATE _A:a cA:a):b 1 (REPLICATE _A:a cA:b)*:b 1 (REPLICATE _A:a cA:b)*:c - 1 (SEL@0 _A:a)*:1 - 1 (SEL@0 _A:a)*:b + 1 (SEL@0 _A:a):1 + 1 (SEL@0 _A:a):b 1 (SEL@A _A:a):1 DFG 'pre inline' patterns with depth 2 6 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:b):c):d - 3 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a - 3 (REDXOR (AND _A:a _B:a)*:a):1 - 1 (CONCAT '0:a (REPLICATE _A:a cA:a)*:b):A + 2 (AND (NOT vA:a)*:a (NOT vB:a)*:a):a + 2 (REDXOR (AND _A:a _B:a):a):1 + 1 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a 1 (CONCAT (REDXOR _A:a)*:1 (CONCAT _B:1 _C:b):c):d 1 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:1):b):c 1 (CONCAT (REDXOR _A:a):1 (REDXOR _B:b)*:1):c - 1 (CONCAT (SEL@0 _A:a)*:1 (CONCAT _B:1 _C:b):c):d + 1 (CONCAT (SEL@0 _A:a):1 (CONCAT _B:1 _C:b):c):d 1 (NOT (REPLICATE _A:a cA:b)*:b):b + 1 (REDXOR (AND _A:a _B:a)*:a):1 1 (REDXOR (REPLICATE _A:1 cA:a)*:b):1 - 1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 1 (REDXOR (REPLICATE _A:a cA:a)*:b):1 + 1 (REDXOR (REPLICATE _A:a cA:a):b)*:1 1 (REDXOR (REPLICATE _A:a cA:b)*:b):1 1 (REDXOR (REPLICATE _A:a cA:b)*:c):1 - 1 (REDXOR (SEL@0 _A:a)*:b):1 + 1 (REDXOR (SEL@0 _A:a):b):1 1 (REPLICATE (NOT _A:a):a cA:a)*:b 1 (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c - 1 (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c + 1 (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b):c 1 (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b 1 (REPLICATE (SEL@A _A:a):1 cA:b)*:c - 1 (SEL@0 (AND _A:a _B:a)*:a)*:1 - 1 (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c + 1 (SEL@0 (AND _A:a _B:a)*:a):1 + 1 (SEL@0 (REPLICATE _A:a cA:a)*:b):c 1 (SEL@A (AND _A:a _B:a)*:a):1 DFG 'pre inline' patterns with depth 3 - 3 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 - 2 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e - 1 (CONCAT '0:a (REPLICATE (REPLICATE _A:b cA:a)*:a cA:a)*:c):A - 1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e + 2 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a):a):1 + 1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e + 1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e + 1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (SEL@0 _C:a):1 (CONCAT _D:1 _E:b):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:1 cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (CONCAT _C:1 _D:d):e):f):g - 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:1):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (REDXOR _C:b)*:1):d):e + 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a):b)*:1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:1):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:b):1 (CONCAT (REDXOR _B:c)*:1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:c):1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:d):e):f):g - 1 (CONCAT (REDXOR (SEL@0 _A:a)*:b):1 (REDXOR (REPLICATE _B:c cA:c)*:a)*:1):d - 1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b + 1 (CONCAT (REDXOR (SEL@0 _A:a):b):1 (REDXOR (REPLICATE _B:c cA:c):a)*:1):d + 1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b 1 (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b + 1 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 1 (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 1 (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 - 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 + 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b):c)*:1 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 1 (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 - 1 (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 + 1 (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b):c):1 1 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c 1 (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a - 1 (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d + 1 (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b):d 1 (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c - 1 (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 - 1 (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c + 1 (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 + 1 (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b):c 1 (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 DFG 'pre inline' patterns with depth 4 - 1 (CONCAT '0:a (REPLICATE (REPLICATE (REPLICATE _A:b cA:a)*:c cA:a)*:a cA:a)*:d):A - 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f - 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e):f - 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b):f - 1 (CONCAT (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 (CONCAT (REDXOR (SEL@0 _B:b)*:c):1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1):d):e + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a):a):1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (SEL@0 _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a):a):1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b):f + 1 (CONCAT (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 (CONCAT (REDXOR (SEL@0 _B:b):c):1 (REDXOR (REPLICATE _A:a cA:a):b)*:1):d):e 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:a)*:a):1 (CONCAT (REDXOR _C:d)*:1 (CONCAT _D:1 _E:e):f):g):h):i - 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:c):1 (CONCAT (REDXOR _C:d):1 (REDXOR _D:c)*:1):e):f):g - 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:d)*:1 (CONCAT (REDXOR _C:d):1 (CONCAT _D:1 _E:1):e):f):g):h + 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b):c)*:1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:c):1 (CONCAT (REDXOR _C:d):1 (REDXOR _D:c)*:1):e):f):g + 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 (CONCAT (REDXOR (REPLICATE _B:b cA:b):d)*:1 (CONCAT (REDXOR _C:d):1 (CONCAT _D:1 _E:1):e):f):g):h 1 (CONCAT (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:b)*:d):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:e):a):f):g):h - 1 (CONCAT (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 (REDXOR (REPLICATE (REPLICATE _B:d cA:a)*:a cA:a)*:b)*:1):e - 1 (CONCAT (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 (CONCAT (REDXOR (REPLICATE _A:1 cA:b)*:c):1 (CONCAT (REDXOR _B:d):1 (CONCAT _C:1 _D:a):e):f):g):c + 1 (CONCAT (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b):c):1 (REDXOR (REPLICATE (REPLICATE _B:d cA:a)*:a cA:a):b)*:1):e + 1 (CONCAT (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (REPLICATE _A:1 cA:b)*:c):1 (CONCAT (REDXOR _B:d):1 (CONCAT _C:1 _D:a):e):f):g):c 1 (NOT (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):a 1 (REDXOR (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c):1 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):1 - 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d)*:1 + 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b):d)*:1 1 (REDXOR (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d):1 1 (REDXOR (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c):1 - 1 (REDXOR (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c):1 + 1 (REDXOR (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b):c):1 1 (REPLICATE (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b cA:b)*:d - 1 (REPLICATE (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a cB:a)*:d + 1 (REPLICATE (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a cB:a):d 1 (REPLICATE (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d cB:b)*:b 1 (REPLICATE (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 cA:b)*:c - 1 (SEL@0 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c)*:d + 1 (SEL@0 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c):d diff --git a/test_regress/t/t_dfg_stats_patterns_pre_inline.py b/test_regress/t/t_dfg_stats_patterns_pre_inline.py index bd1a3ca67..c5d54600c 100755 --- a/test_regress/t/t_dfg_stats_patterns_pre_inline.py +++ b/test_regress/t/t_dfg_stats_patterns_pre_inline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_stats_patterns_scoped.out b/test_regress/t/t_dfg_stats_patterns_scoped.out index bc5d34307..dc86b18e2 100644 --- a/test_regress/t/t_dfg_stats_patterns_scoped.out +++ b/test_regress/t/t_dfg_stats_patterns_scoped.out @@ -1,96 +1,98 @@ DFG 'scoped' patterns with depth 1 9 (CONCAT _A:1 _B:a):b 8 (REDXOR _A:a):1 - 3 (AND _A:a _B:a)*:a 3 (NOT vA:a)*:a - 2 (REPLICATE _A:a cA:a)*:b - 1 (CONCAT '0:a _A:b):A + 2 (AND _A:a _B:a):a + 1 (AND _A:a _B:a)*:a 1 (CONCAT _A:1 _B:1):a 1 (NOT _A:a):a 1 (REDXOR _A:a)*:1 1 (REPLICATE _A:1 cA:a)*:b + 1 (REPLICATE _A:a cA:a)*:b + 1 (REPLICATE _A:a cA:a):b 1 (REPLICATE _A:a cA:b)*:b 1 (REPLICATE _A:a cA:b)*:c - 1 (SEL@0 _A:a)*:1 - 1 (SEL@0 _A:a)*:b + 1 (SEL@0 _A:a):1 + 1 (SEL@0 _A:a):b 1 (SEL@A _A:a):1 DFG 'scoped' patterns with depth 2 6 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:b):c):d - 3 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a - 3 (REDXOR (AND _A:a _B:a)*:a):1 - 1 (CONCAT '0:a (REPLICATE _A:a cA:a)*:b):A + 2 (AND (NOT vA:a)*:a (NOT vB:a)*:a):a + 2 (REDXOR (AND _A:a _B:a):a):1 + 1 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a 1 (CONCAT (REDXOR _A:a)*:1 (CONCAT _B:1 _C:b):c):d 1 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:1):b):c 1 (CONCAT (REDXOR _A:a):1 (REDXOR _B:b)*:1):c - 1 (CONCAT (SEL@0 _A:a)*:1 (CONCAT _B:1 _C:b):c):d + 1 (CONCAT (SEL@0 _A:a):1 (CONCAT _B:1 _C:b):c):d 1 (NOT (REPLICATE _A:a cA:b)*:b):b + 1 (REDXOR (AND _A:a _B:a)*:a):1 1 (REDXOR (REPLICATE _A:1 cA:a)*:b):1 - 1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 1 (REDXOR (REPLICATE _A:a cA:a)*:b):1 + 1 (REDXOR (REPLICATE _A:a cA:a):b)*:1 1 (REDXOR (REPLICATE _A:a cA:b)*:b):1 1 (REDXOR (REPLICATE _A:a cA:b)*:c):1 - 1 (REDXOR (SEL@0 _A:a)*:b):1 + 1 (REDXOR (SEL@0 _A:a):b):1 1 (REPLICATE (NOT _A:a):a cA:a)*:b 1 (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c - 1 (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c + 1 (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b):c 1 (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b 1 (REPLICATE (SEL@A _A:a):1 cA:b)*:c - 1 (SEL@0 (AND _A:a _B:a)*:a)*:1 - 1 (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c + 1 (SEL@0 (AND _A:a _B:a)*:a):1 + 1 (SEL@0 (REPLICATE _A:a cA:a)*:b):c 1 (SEL@A (AND _A:a _B:a)*:a):1 DFG 'scoped' patterns with depth 3 - 3 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 - 2 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e - 1 (CONCAT '0:a (REPLICATE (REPLICATE _A:b cA:a)*:a cA:a)*:c):A - 1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e + 2 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a):a):1 + 1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e + 1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e + 1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (SEL@0 _C:a):1 (CONCAT _D:1 _E:b):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:1 cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (CONCAT _C:1 _D:d):e):f):g - 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:1):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (REDXOR _C:b)*:1):d):e + 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a):b)*:1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:1):c):d):e 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:b):1 (CONCAT (REDXOR _B:c)*:1 (CONCAT _C:1 _D:d):e):f):g 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:c):1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:d):e):f):g - 1 (CONCAT (REDXOR (SEL@0 _A:a)*:b):1 (REDXOR (REPLICATE _B:c cA:c)*:a)*:1):d - 1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b + 1 (CONCAT (REDXOR (SEL@0 _A:a):b):1 (REDXOR (REPLICATE _B:c cA:c):a)*:1):d + 1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b 1 (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b + 1 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 1 (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 1 (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 - 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 + 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b):c)*:1 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 1 (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 - 1 (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 + 1 (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b):c):1 1 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c 1 (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a - 1 (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d + 1 (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b):d 1 (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c - 1 (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 - 1 (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c + 1 (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 + 1 (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b):c 1 (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 DFG 'scoped' patterns with depth 4 - 1 (CONCAT '0:a (REPLICATE (REPLICATE (REPLICATE _A:b cA:a)*:c cA:a)*:a cA:a)*:d):A - 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f - 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e):f - 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b):f - 1 (CONCAT (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 (CONCAT (REDXOR (SEL@0 _B:b)*:c):1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1):d):e + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a):a):1 (CONCAT (REDXOR (AND _A:a _B:a):a):1 (CONCAT (SEL@0 _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a):a):1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b):f + 1 (CONCAT (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 (CONCAT (REDXOR (SEL@0 _B:b):c):1 (REDXOR (REPLICATE _A:a cA:a):b)*:1):d):e 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:a)*:a):1 (CONCAT (REDXOR _C:d)*:1 (CONCAT _D:1 _E:e):f):g):h):i - 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:c):1 (CONCAT (REDXOR _C:d):1 (REDXOR _D:c)*:1):e):f):g - 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:d)*:1 (CONCAT (REDXOR _C:d):1 (CONCAT _D:1 _E:1):e):f):g):h + 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b):c)*:1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:c):1 (CONCAT (REDXOR _C:d):1 (REDXOR _D:c)*:1):e):f):g + 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 (CONCAT (REDXOR (REPLICATE _B:b cA:b):d)*:1 (CONCAT (REDXOR _C:d):1 (CONCAT _D:1 _E:1):e):f):g):h 1 (CONCAT (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:b)*:d):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:e):a):f):g):h - 1 (CONCAT (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 (REDXOR (REPLICATE (REPLICATE _B:d cA:a)*:a cA:a)*:b)*:1):e - 1 (CONCAT (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 (CONCAT (REDXOR (REPLICATE _A:1 cA:b)*:c):1 (CONCAT (REDXOR _B:d):1 (CONCAT _C:1 _D:a):e):f):g):c + 1 (CONCAT (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b):c):1 (REDXOR (REPLICATE (REPLICATE _B:d cA:a)*:a cA:a):b)*:1):e + 1 (CONCAT (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (REPLICATE _A:1 cA:b)*:c):1 (CONCAT (REDXOR _B:d):1 (CONCAT _C:1 _D:a):e):f):g):c 1 (NOT (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):a 1 (REDXOR (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c):1 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):1 - 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d)*:1 + 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b):d)*:1 1 (REDXOR (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d):1 1 (REDXOR (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c):1 - 1 (REDXOR (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c):1 + 1 (REDXOR (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b):c):1 1 (REPLICATE (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b cA:b)*:d - 1 (REPLICATE (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a cB:a)*:d + 1 (REPLICATE (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a cB:a):d 1 (REPLICATE (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d cB:b)*:b 1 (REPLICATE (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c cB:b)*:d 1 (REPLICATE (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 cA:b)*:c - 1 (SEL@0 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c)*:d + 1 (SEL@0 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c):d diff --git a/test_regress/t/t_dfg_stats_patterns_scoped.py b/test_regress/t/t_dfg_stats_patterns_scoped.py index afd635460..a191c01ea 100755 --- a/test_regress/t/t_dfg_stats_patterns_scoped.py +++ b/test_regress/t/t_dfg_stats_patterns_scoped.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_synthesis.cpp b/test_regress/t/t_dfg_synthesis.cpp index 0664397e1..d8bffdbaf 100644 --- a/test_regress/t/t_dfg_synthesis.cpp +++ b/test_regress/t/t_dfg_synthesis.cpp @@ -1,8 +1,8 @@ // // DESCRIPTION: Verilator: DFG optimizer equivalence testing // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_dfg_synthesis.py b/test_regress/t/t_dfg_synthesis.py index 51d9aa16c..1fafff18e 100755 --- a/test_regress/t/t_dfg_synthesis.py +++ b/test_regress/t/t_dfg_synthesis.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -34,6 +34,8 @@ with open(rdFile, 'r', encoding="utf8") as rdFh, \ nAlwaysReverted += 1 elif re.search(r'^\s*always', line): nAlwaysSynthesized += 1 + elif re.search(r'^\s*wire.*=', line): + nAlwaysSynthesized += 1 line = line.split("//")[0] m = re.search(r'`signal\((\w+),', line) if not m: diff --git a/test_regress/t/t_dfg_synthesis.v b/test_regress/t/t_dfg_synthesis.v index ad76285cf..8bcb19f55 100644 --- a/test_regress/t/t_dfg_synthesis.v +++ b/test_regress/t/t_dfg_synthesis.v @@ -1,11 +1,39 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Geza Lore // SPDX-License-Identifier: CC0-1.0 `define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr +package pkg; + function automatic logic [7:0] sub(input logic [7:0] a, input logic [7:0] b); + return a - b; + endfunction + + function automatic logic [7:0] branchy(input logic [7:0] a, input logic [7:0] b); + if (a[0]) begin + return b + 8'd1; + end else if (a[1]) begin + return b + 8'd2; + end else if (a[2]) begin + return b + 8'd3; + end else if (a[3]) begin + return b + 8'd4; + end else if (a[4]) begin + return b + 8'd5; + end else if (a[5]) begin + return b + 8'd6; + end else if (a[6]) begin + return b + 8'd7; + end else if (a[7]) begin + return b + 8'd8; + end else begin + return b; + end + endfunction +endpackage + module t ( `include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py rand_a, rand_b, srand_a, srand_b @@ -502,4 +530,44 @@ module t ( end `signal(BOTH_BREAK, both_break); + logic [1:0] uses_tmp; + always_comb begin + uses_tmp = 2'd0; + if (rand_a[0]) begin + automatic logic [1:0] tmp; + tmp = rand_b[1:0]; + uses_tmp = tmp ^ rand_b[3:2]; + end + end + `signal(USES_TMP, uses_tmp); + + logic [3:0] uses_loop_var; + always_comb begin + uses_loop_var = 4'd0; + if (rand_a[0]) begin + for (int i = 0; i < 4; ++i) begin + uses_loop_var[i] = rand_b[2*i]; + end + end + end + `signal(USES_LOOP_VAR, uses_loop_var); + + function automatic logic [7:0] add(input logic [7:0] a, input logic [7:0] b); + return a + b; + endfunction + logic [7:0] func_1; + always_comb begin + func_1 = add(rand_a[7:0], rand_b[7:0]); + end + `signal(FUNC_1, func_1); + + logic [7:0] func_2; + always_comb begin + func_2 = pkg::sub(rand_a[7:0], rand_b[7:0]); + end + `signal(FUNC_2, func_2); + + wire logic [7:0] func_3 = pkg::branchy(rand_a[7:0], rand_b[7:0]); + `signal(FUNC_3, func_3); + endmodule diff --git a/test_regress/t/t_dfg_synthesis_pre_inline.cpp b/test_regress/t/t_dfg_synthesis_pre_inline.cpp index 0664397e1..d8bffdbaf 100644 --- a/test_regress/t/t_dfg_synthesis_pre_inline.cpp +++ b/test_regress/t/t_dfg_synthesis_pre_inline.cpp @@ -1,8 +1,8 @@ // // DESCRIPTION: Verilator: DFG optimizer equivalence testing // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_dfg_synthesis_pre_inline.py b/test_regress/t/t_dfg_synthesis_pre_inline.py index 2da0d567d..7636b80f9 100755 --- a/test_regress/t/t_dfg_synthesis_pre_inline.py +++ b/test_regress/t/t_dfg_synthesis_pre_inline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_synthesis_pre_inline.v b/test_regress/t/t_dfg_synthesis_pre_inline.v index 5c00f54c8..3bd47ef87 100644 --- a/test_regress/t/t_dfg_synthesis_pre_inline.v +++ b/test_regress/t/t_dfg_synthesis_pre_inline.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Geza Lore // SPDX-License-Identifier: CC0-1.0 `define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr diff --git a/test_regress/t/t_dfg_true_cycle_bad.py b/test_regress/t/t_dfg_true_cycle_bad.py index 1bf1426f9..f3bbcad9d 100755 --- a/test_regress/t/t_dfg_true_cycle_bad.py +++ b/test_regress/t/t_dfg_true_cycle_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dfg_true_cycle_bad.v b/test_regress/t/t_dfg_true_cycle_bad.v index 98186cdb4..57a8cba77 100644 --- a/test_regress/t/t_dfg_true_cycle_bad.v +++ b/test_regress/t/t_dfg_true_cycle_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Geza Lore // SPDX-License-Identifier: CC0-1.0 `default_nettype none diff --git a/test_regress/t/t_difftree.py b/test_regress/t/t_difftree.py index 645fa264e..e93664aca 100755 --- a/test_regress/t/t_difftree.py +++ b/test_regress/t/t_difftree.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable.py b/test_regress/t/t_disable.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_disable.py +++ b/test_regress/t/t_disable.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable.v b/test_regress/t/t_disable.v index ad52f005d..309983ddf 100644 --- a/test_regress/t/t_disable.v +++ b/test_regress/t/t_disable.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_disable_bad.py b/test_regress/t/t_disable_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_disable_bad.py +++ b/test_regress/t/t_disable_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_bad.v b/test_regress/t/t_disable_bad.v index 4d867b2da..08fd53c7d 100644 --- a/test_regress/t/t_disable_bad.v +++ b/test_regress/t/t_disable_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_disable_empty.py b/test_regress/t/t_disable_empty.py index efe8cc01c..382ad0d44 100755 --- a/test_regress/t/t_disable_empty.py +++ b/test_regress/t/t_disable_empty.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_empty.v b/test_regress/t/t_disable_empty.v index b11e20be6..2ed96492d 100644 --- a/test_regress/t/t_disable_empty.v +++ b/test_regress/t/t_disable_empty.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_disable_empty_outside.py b/test_regress/t/t_disable_empty_outside.py index 3476171ff..276645160 100755 --- a/test_regress/t/t_disable_empty_outside.py +++ b/test_regress/t/t_disable_empty_outside.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_empty_outside.v b/test_regress/t/t_disable_empty_outside.v index 4b023c1c1..de71c4429 100644 --- a/test_regress/t/t_disable_empty_outside.v +++ b/test_regress/t/t_disable_empty_outside.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; initial begin begin : blk - int x = 0; + static int x = 0; fork : fork_blk begin end diff --git a/test_regress/t/t_disable_fork1.py b/test_regress/t/t_disable_fork1.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_disable_fork1.py +++ b/test_regress/t/t_disable_fork1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_fork1.v b/test_regress/t/t_disable_fork1.v index e1f5cc711..6e05450e2 100644 --- a/test_regress/t/t_disable_fork1.v +++ b/test_regress/t/t_disable_fork1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define N 3 diff --git a/test_regress/t/t_disable_fork2.py b/test_regress/t/t_disable_fork2.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_disable_fork2.py +++ b/test_regress/t/t_disable_fork2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_fork2.v b/test_regress/t/t_disable_fork2.v index 6e52acac8..8df074fab 100644 --- a/test_regress/t/t_disable_fork2.v +++ b/test_regress/t/t_disable_fork2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 // USING THIS FOR DEBUGGING PROCESS PROPAGATION: diff --git a/test_regress/t/t_disable_fork2_split.py b/test_regress/t/t_disable_fork2_split.py index 3e66b3894..d7770982f 100755 --- a/test_regress/t/t_disable_fork2_split.py +++ b/test_regress/t/t_disable_fork2_split.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_fork3.py b/test_regress/t/t_disable_fork3.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_disable_fork3.py +++ b/test_regress/t/t_disable_fork3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_fork3.v b/test_regress/t/t_disable_fork3.v index d0408243c..10b1d27fb 100644 --- a/test_regress/t/t_disable_fork3.v +++ b/test_regress/t/t_disable_fork3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class C; diff --git a/test_regress/t/t_disable_fork_notiming.py b/test_regress/t/t_disable_fork_notiming.py index e07104c5c..c5854decc 100755 --- a/test_regress/t/t_disable_fork_notiming.py +++ b/test_regress/t/t_disable_fork_notiming.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_fork_notiming.v b/test_regress/t/t_disable_fork_notiming.v index 21ac2743e..519442866 100644 --- a/test_regress/t/t_disable_fork_notiming.v +++ b/test_regress/t/t_disable_fork_notiming.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_disable_func_bad.py b/test_regress/t/t_disable_func_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_disable_func_bad.py +++ b/test_regress/t/t_disable_func_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_func_bad.v b/test_regress/t/t_disable_func_bad.v index 7a1f8ef6a..b8479cf59 100644 --- a/test_regress/t/t_disable_func_bad.v +++ b/test_regress/t/t_disable_func_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 int x = 0; diff --git a/test_regress/t/t_disable_genfor2.py b/test_regress/t/t_disable_genfor2.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_disable_genfor2.py +++ b/test_regress/t/t_disable_genfor2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_genfor2.v b/test_regress/t/t_disable_genfor2.v index 4bb9a4c2e..bfa3ef56b 100644 --- a/test_regress/t/t_disable_genfor2.v +++ b/test_regress/t/t_disable_genfor2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_disable_genfor_unsup.py b/test_regress/t/t_disable_genfor_unsup.py index efe8cc01c..382ad0d44 100755 --- a/test_regress/t/t_disable_genfor_unsup.py +++ b/test_regress/t/t_disable_genfor_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_genfor_unsup.v b/test_regress/t/t_disable_genfor_unsup.v index c1f1e845b..295d5b7ce 100644 --- a/test_regress/t/t_disable_genfor_unsup.v +++ b/test_regress/t/t_disable_genfor_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_disable_iff_multi_bad.py b/test_regress/t/t_disable_iff_multi_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_disable_iff_multi_bad.py +++ b/test_regress/t/t_disable_iff_multi_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_iff_multi_bad.v b/test_regress/t/t_disable_iff_multi_bad.v index 624ab3268..6e2fd08fa 100644 --- a/test_regress/t/t_disable_iff_multi_bad.v +++ b/test_regress/t/t_disable_iff_multi_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_disable_inside.py b/test_regress/t/t_disable_inside.py index 3476171ff..276645160 100755 --- a/test_regress/t/t_disable_inside.py +++ b/test_regress/t/t_disable_inside.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_inside.v b/test_regress/t/t_disable_inside.v index 3292a3ef0..8cd151611 100644 --- a/test_regress/t/t_disable_inside.v +++ b/test_regress/t/t_disable_inside.v @@ -1,12 +1,12 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; initial begin - int x = 0; + static int x = 0; fork : fork_blk begin #1; @@ -28,7 +28,7 @@ module t; end initial begin - int y = 0; + static int y = 0; fork begin : fork_branch #1; diff --git a/test_regress/t/t_disable_outside.py b/test_regress/t/t_disable_outside.py index 3476171ff..276645160 100755 --- a/test_regress/t/t_disable_outside.py +++ b/test_regress/t/t_disable_outside.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_outside.v b/test_regress/t/t_disable_outside.v index 5cca902c5..065bdee7e 100644 --- a/test_regress/t/t_disable_outside.v +++ b/test_regress/t/t_disable_outside.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; initial begin begin : blk - int x = 0; + int x; fork : fork_blk begin x = 1; diff --git a/test_regress/t/t_disable_outside2.py b/test_regress/t/t_disable_outside2.py index 3476171ff..276645160 100755 --- a/test_regress/t/t_disable_outside2.py +++ b/test_regress/t/t_disable_outside2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_outside2.v b/test_regress/t/t_disable_outside2.v index 96f72a544..cd4a4e8f3 100644 --- a/test_regress/t/t_disable_outside2.v +++ b/test_regress/t/t_disable_outside2.v @@ -1,14 +1,14 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; initial begin for (int i = 0; i < 3; i++) begin begin : blk - int x = 0; + int x; fork : fork_blk begin x = 1; diff --git a/test_regress/t/t_disable_outside3.py b/test_regress/t/t_disable_outside3.py index 3476171ff..276645160 100755 --- a/test_regress/t/t_disable_outside3.py +++ b/test_regress/t/t_disable_outside3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_outside3.v b/test_regress/t/t_disable_outside3.v index 2a4e76636..0193608ea 100644 --- a/test_regress/t/t_disable_outside3.v +++ b/test_regress/t/t_disable_outside3.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; initial begin begin : blk - int x = 0; + int x; fork : fork_blk begin #4; diff --git a/test_regress/t/t_disable_outside4.py b/test_regress/t/t_disable_outside4.py index 3476171ff..276645160 100755 --- a/test_regress/t/t_disable_outside4.py +++ b/test_regress/t/t_disable_outside4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_outside4.v b/test_regress/t/t_disable_outside4.v index 7856abc1d..02942a608 100644 --- a/test_regress/t/t_disable_outside4.v +++ b/test_regress/t/t_disable_outside4.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; initial begin begin : blk - int x = 0; + int x; fork begin #1; diff --git a/test_regress/t/t_disable_task_simple.py b/test_regress/t/t_disable_task_simple.py index 3476171ff..276645160 100755 --- a/test_regress/t/t_disable_task_simple.py +++ b/test_regress/t/t_disable_task_simple.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_task_simple.v b/test_regress/t/t_disable_task_simple.v index d4983967f..a594146ad 100644 --- a/test_regress/t/t_disable_task_simple.v +++ b/test_regress/t/t_disable_task_simple.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Cls; @@ -34,7 +34,7 @@ endclass module t; initial begin - Cls c = new; + automatic Cls c = new; c.disable_outside_fork(); #2; if (c.x != 1) $stop; diff --git a/test_regress/t/t_disable_task_unsup.py b/test_regress/t/t_disable_task_unsup.py index efe8cc01c..382ad0d44 100755 --- a/test_regress/t/t_disable_task_unsup.py +++ b/test_regress/t/t_disable_task_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_task_unsup.v b/test_regress/t/t_disable_task_unsup.v index 346dd3c3c..6331ba64f 100644 --- a/test_regress/t/t_disable_task_unsup.v +++ b/test_regress/t/t_disable_task_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 int x = 0; diff --git a/test_regress/t/t_disable_within_task_unsup.py b/test_regress/t/t_disable_within_task_unsup.py index efe8cc01c..382ad0d44 100755 --- a/test_regress/t/t_disable_within_task_unsup.py +++ b/test_regress/t/t_disable_within_task_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_disable_within_task_unsup.v b/test_regress/t/t_disable_within_task_unsup.v index c3f3d13e7..4ae25c626 100644 --- a/test_regress/t/t_disable_within_task_unsup.v +++ b/test_regress/t/t_disable_within_task_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 task disable_fork_blk; @@ -11,7 +11,7 @@ endtask module t; initial begin : init - int x = 0; + int x; fork : fork_blk begin x = 1; diff --git a/test_regress/t/t_display.py b/test_regress/t/t_display.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_display.py +++ b/test_regress/t/t_display.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v index cf6b9b90f..f3526b9ad 100644 --- a/test_regress/t/t_display.v +++ b/test_regress/t/t_display.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_bad.py b/test_regress/t/t_display_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_display_bad.py +++ b/test_regress/t/t_display_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_bad.v b/test_regress/t/t_display_bad.v index 4bf715f80..00bc9d14d 100644 --- a/test_regress/t/t_display_bad.v +++ b/test_regress/t/t_display_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_brace.py b/test_regress/t/t_display_brace.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_display_brace.py +++ b/test_regress/t/t_display_brace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_brace.v b/test_regress/t/t_display_brace.v index f20ee5357..16f8b5b47 100644 --- a/test_regress/t/t_display_brace.v +++ b/test_regress/t/t_display_brace.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef int unsigned ahb_addr_t; diff --git a/test_regress/t/t_display_concat.py b/test_regress/t/t_display_concat.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_display_concat.py +++ b/test_regress/t/t_display_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_concat.v b/test_regress/t/t_display_concat.v index f0fa3fa81..557c25289 100644 --- a/test_regress/t/t_display_concat.v +++ b/test_regress/t/t_display_concat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_display_concat2.py b/test_regress/t/t_display_concat2.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_display_concat2.py +++ b/test_regress/t/t_display_concat2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_concat2.v b/test_regress/t/t_display_concat2.v index 11a6895f1..bed6d74f7 100644 --- a/test_regress/t/t_display_concat2.v +++ b/test_regress/t/t_display_concat2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module test( diff --git a/test_regress/t/t_display_cwide_bad.py b/test_regress/t/t_display_cwide_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_display_cwide_bad.py +++ b/test_regress/t/t_display_cwide_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_cwide_bad.v b/test_regress/t/t_display_cwide_bad.v index 0cd07beb4..ec30be7b7 100644 --- a/test_regress/t/t_display_cwide_bad.v +++ b/test_regress/t/t_display_cwide_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_esc_bad.py b/test_regress/t/t_display_esc_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_display_esc_bad.py +++ b/test_regress/t/t_display_esc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_esc_bad.v b/test_regress/t/t_display_esc_bad.v index fbce610e4..bd4df9d7c 100644 --- a/test_regress/t/t_display_esc_bad.v +++ b/test_regress/t/t_display_esc_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_format_wide_decimal.py b/test_regress/t/t_display_format_wide_decimal.py index ba4b18e85..0b47dd101 100755 --- a/test_regress/t/t_display_format_wide_decimal.py +++ b/test_regress/t/t_display_format_wide_decimal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_format_wide_decimal.v b/test_regress/t/t_display_format_wide_decimal.v index 280571bbe..3e2b3efeb 100644 --- a/test_regress/t/t_display_format_wide_decimal.v +++ b/test_regress/t/t_display_format_wide_decimal.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_display_impure.py b/test_regress/t/t_display_impure.py index 0dc2c2a5d..3342403e4 100755 --- a/test_regress/t/t_display_impure.py +++ b/test_regress/t/t_display_impure.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_impure.v b/test_regress/t/t_display_impure.v index ad24975d3..4e232adff 100644 --- a/test_regress/t/t_display_impure.v +++ b/test_regress/t/t_display_impure.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 function integer f; diff --git a/test_regress/t/t_display_io.py b/test_regress/t/t_display_io.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_display_io.py +++ b/test_regress/t/t_display_io.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_io.v b/test_regress/t/t_display_io.v index d9315fb54..14fac2d84 100644 --- a/test_regress/t/t_display_io.v +++ b/test_regress/t/t_display_io.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: $display() test for %l // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_display_l.py b/test_regress/t/t_display_l.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_display_l.py +++ b/test_regress/t/t_display_l.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_l.v b/test_regress/t/t_display_l.v index 6fc0ee214..cff26cf20 100644 --- a/test_regress/t/t_display_l.v +++ b/test_regress/t/t_display_l.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: $display() test for %l // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_mcd.py b/test_regress/t/t_display_mcd.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_display_mcd.py +++ b/test_regress/t/t_display_mcd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_mcd.v b/test_regress/t/t_display_mcd.v index b56bacc46..1d298549d 100644 --- a/test_regress/t/t_display_mcd.v +++ b/test_regress/t/t_display_mcd.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_merge.py b/test_regress/t/t_display_merge.py index 43eefcbe0..999f03507 100755 --- a/test_regress/t/t_display_merge.py +++ b/test_regress/t/t_display_merge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_merge.v b/test_regress/t/t_display_merge.v index e83b987f3..d53f2f3bd 100644 --- a/test_regress/t/t_display_merge.v +++ b/test_regress/t/t_display_merge.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_noopt.py b/test_regress/t/t_display_noopt.py index 9b159b6ba..aa3c4d3d3 100755 --- a/test_regress/t/t_display_noopt.py +++ b/test_regress/t/t_display_noopt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_p_elab.py b/test_regress/t/t_display_p_elab.py index 2b4837fcc..096e10e28 100755 --- a/test_regress/t/t_display_p_elab.py +++ b/test_regress/t/t_display_p_elab.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_p_elab.v b/test_regress/t/t_display_p_elab.v index 98af55b74..55df56055 100644 --- a/test_regress/t/t_display_p_elab.v +++ b/test_regress/t/t_display_p_elab.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_display_qqq.py b/test_regress/t/t_display_qqq.py index 97abb660e..c03eaf086 100755 --- a/test_regress/t/t_display_qqq.py +++ b/test_regress/t/t_display_qqq.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_qqq.v b/test_regress/t/t_display_qqq.v index 1b5568269..80c03f8d0 100644 --- a/test_regress/t/t_display_qqq.v +++ b/test_regress/t/t_display_qqq.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_real.py b/test_regress/t/t_display_real.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_display_real.py +++ b/test_regress/t/t_display_real.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_real.v b/test_regress/t/t_display_real.v index 33e15d81c..606813027 100644 --- a/test_regress/t/t_display_real.v +++ b/test_regress/t/t_display_real.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_real_noopt.py b/test_regress/t/t_display_real_noopt.py index ad0f55e3e..fa74c3c9e 100755 --- a/test_regress/t/t_display_real_noopt.py +++ b/test_regress/t/t_display_real_noopt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_realtime.py b/test_regress/t/t_display_realtime.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_display_realtime.py +++ b/test_regress/t/t_display_realtime.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_realtime.v b/test_regress/t/t_display_realtime.v index ec16d2e91..be6bfd6f6 100644 --- a/test_regress/t/t_display_realtime.v +++ b/test_regress/t/t_display_realtime.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_display_recurse.py b/test_regress/t/t_display_recurse.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_display_recurse.py +++ b/test_regress/t/t_display_recurse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_recurse.v b/test_regress/t/t_display_recurse.v index 877792b0f..40fd2eaee 100644 --- a/test_regress/t/t_display_recurse.v +++ b/test_regress/t/t_display_recurse.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_display_signed.py b/test_regress/t/t_display_signed.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_display_signed.py +++ b/test_regress/t/t_display_signed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_signed.v b/test_regress/t/t_display_signed.v index 0a4491071..accd614f0 100644 --- a/test_regress/t/t_display_signed.v +++ b/test_regress/t/t_display_signed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_signed_noopt.py b/test_regress/t/t_display_signed_noopt.py index e80552d48..8a54193d2 100755 --- a/test_regress/t/t_display_signed_noopt.py +++ b/test_regress/t/t_display_signed_noopt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_string.py b/test_regress/t/t_display_string.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_display_string.py +++ b/test_regress/t/t_display_string.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_string.v b/test_regress/t/t_display_string.v index aaa4aa3b4..768df39a4 100644 --- a/test_regress/t/t_display_string.v +++ b/test_regress/t/t_display_string.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_time.py b/test_regress/t/t_display_time.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_display_time.py +++ b/test_regress/t/t_display_time.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_time.v b/test_regress/t/t_display_time.v index f5d4c75da..79c8b5305 100644 --- a/test_regress/t/t_display_time.v +++ b/test_regress/t/t_display_time.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns diff --git a/test_regress/t/t_display_type_bad.py b/test_regress/t/t_display_type_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_display_type_bad.py +++ b/test_regress/t/t_display_type_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_type_bad.v b/test_regress/t/t_display_type_bad.v index ff17cf8b3..84407ecdd 100644 --- a/test_regress/t/t_display_type_bad.v +++ b/test_regress/t/t_display_type_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_display_wide.py b/test_regress/t/t_display_wide.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_display_wide.py +++ b/test_regress/t/t_display_wide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_wide.v b/test_regress/t/t_display_wide.v index c356ab0e4..ef3595e03 100644 --- a/test_regress/t/t_display_wide.v +++ b/test_regress/t/t_display_wide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_display_wide_bad.py b/test_regress/t/t_display_wide_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_display_wide_bad.py +++ b/test_regress/t/t_display_wide_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_display_wide_bad.v b/test_regress/t/t_display_wide_bad.v index cde9a15c2..7278a7480 100644 --- a/test_regress/t/t_display_wide_bad.v +++ b/test_regress/t/t_display_wide_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_dist_attributes/mt_disabled.cpp b/test_regress/t/t_dist_attributes/mt_disabled.cpp index 5211d804f..899cbbec1 100644 --- a/test_regress/t/t_dist_attributes/mt_disabled.cpp +++ b/test_regress/t/t_dist_attributes/mt_disabled.cpp @@ -4,10 +4,10 @@ // // Code available from: https://verilator.org // -// Copyright 2022-2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022-2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dist_attributes/mt_disabled.h b/test_regress/t/t_dist_attributes/mt_disabled.h index a39202444..70c2a5c32 100644 --- a/test_regress/t/t_dist_attributes/mt_disabled.h +++ b/test_regress/t/t_dist_attributes/mt_disabled.h @@ -4,10 +4,10 @@ // // Code available from: https://verilator.org // -// Copyright 2022-2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022-2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dist_attributes/mt_enabled.cpp b/test_regress/t/t_dist_attributes/mt_enabled.cpp index 569ed08d8..62a858961 100644 --- a/test_regress/t/t_dist_attributes/mt_enabled.cpp +++ b/test_regress/t/t_dist_attributes/mt_enabled.cpp @@ -4,10 +4,10 @@ // // Code available from: https://verilator.org // -// Copyright 2022-2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022-2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dist_attributes/mt_enabled.h b/test_regress/t/t_dist_attributes/mt_enabled.h index 045b80067..7c8021b4b 100644 --- a/test_regress/t/t_dist_attributes/mt_enabled.h +++ b/test_regress/t/t_dist_attributes/mt_enabled.h @@ -4,10 +4,10 @@ // // Code available from: https://verilator.org // -// Copyright 2022-2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022-2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dist_attributes_bad.py b/test_regress/t/t_dist_attributes_bad.py index 5fcf21e84..91cefda79 100755 --- a/test_regress/t/t_dist_attributes_bad.py +++ b/test_regress/t/t_dist_attributes_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import json diff --git a/test_regress/t/t_dist_attributes_include.py b/test_regress/t/t_dist_attributes_include.py index 5ec098959..be73d354b 100755 --- a/test_regress/t/t_dist_attributes_include.py +++ b/test_regress/t/t_dist_attributes_include.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_attributes_src.py b/test_regress/t/t_dist_attributes_src.py index f4bf78ea1..4de26cd9e 100755 --- a/test_regress/t/t_dist_attributes_src.py +++ b/test_regress/t/t_dist_attributes_src.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_cinclude.py b/test_regress/t/t_dist_cinclude.py index 68fba9c8a..e4b3dc810 100755 --- a/test_regress/t/t_dist_cinclude.py +++ b/test_regress/t/t_dist_cinclude.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_contributors.py b/test_regress/t/t_dist_contributors.py index 309ed2d66..514830f6c 100755 --- a/test_regress/t/t_dist_contributors.py +++ b/test_regress/t/t_dist_contributors.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_copyright.py b/test_regress/t/t_dist_copyright.py index 5411e6d94..53ee776c6 100755 --- a/test_regress/t/t_dist_copyright.py +++ b/test_regress/t/t_dist_copyright.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -14,23 +14,20 @@ test.scenarios('dist') RELEASE_OK_RE = r'(^test_regress/t/.*\.(cpp|h|map|mk|sv|v|vlt)|^test_regress/t_done/|^examples/)' -EXEMPT_AUTHOR_RE = r'(^ci/|^nodist/fastcov.py|^nodist/fuzzer|^test_regress/t/.*\.(cpp|h|v|vlt)$)' +EXEMPT_AUTHOR_RE = r'(^ci/|^nodist/fastcov.py|^nodist/fuzzer|^test_regress/t/.*\.(cpp|h|mk|s?vh?|vlt)$)' EXEMPT_FILES_RE = r'(^\.|/\.|\.gitignore$|\.dat|\.gprof|\.mem|\.out$|\.png$|\.tree|\.vc$|\.vcd$|^\.)' EXEMPT_FILES_LIST = """ - Artistic CITATION.cff CPPLINT.cfg LICENSE - README.rst + LICENSES/ + REUSE.toml ci/ci-win-compile.ps1 ci/ci-win-test.ps1 ci/codecov - docs/CONTRIBUTING.rst docs/CONTRIBUTORS - docs/README.rst - docs/security.rst docs/_static docs/gen docs/spelling.txt @@ -40,14 +37,7 @@ EXEMPT_FILES_LIST = """ install-sh src/mkinstalldirs test_regress/t/t_altera_lpm.v - test_regress/t/t_flag_f__3.v - test_regress/t/t_fuzz_eof_bad.v - test_regress/t/t_incr_void.v - test_regress/t/t_property_unsup.v test_regress/t/t_randsequence_svtests.v - test_regress/t/t_sequence_first_match_unsup.v - test_regress/t/tsub/t_flag_f_tsub.v - test_regress/t/tsub/t_flag_f_tsub_inc.v test_regress/t/uvm/ verilator.pc.in """ @@ -77,44 +67,36 @@ for filename in files: open_filename = os.path.join(test.root, filename) if not os.path.exists(open_filename): continue + + if "test_regress/t" in filename: + yeardash = str(year) + else: + yeardash = str(year) + '-' + str(year) + with open(open_filename, 'r', encoding="utf8") as fh: spdx = None copyright_msg = None - release = False for line in fh: line = line.rstrip() - if 'SPDX-License-Identifier:' in line: + if 'SP' + 'DX-License-Identifier:' in line: spdx = line - elif re.search(r'Copyright 20[0-9][0-9]', line): + elif re.search(r'(SP()DX-FileCopyrightText: 20[0-9][0-9])', line): copyright_msg = line if 'Wilson Snyder' in line: pass - elif re.search(r'\.pl$', filename): - pass elif re.search(EXEMPT_AUTHOR_RE, filename): pass else: - if "test_regress/t" in filename: - yeardash = str(year) - else: - yeardash = str(year) + '-' + str(year) print(" " + copyright_msg) - test.error_keep_going(filename + ": Please use standard 'Copyright " + - yeardash + " by Wilson Snyder'") - elif (('Creative Commons Public Domain' in line) - or ('freely copied and/or distributed' in line) - or ('placed into the Public Domain' in line)): - release = True + test.error_keep_going(filename + ": Please use standard 'SP" + + "DX-FileCopyrightText: " + yeardash + " Wilson Snyder'") - release_note = "" - if not re.search(RELEASE_OK_RE, filename): - release_note = " (has copyright release, but not part of " + RELEASE_OK_RE + ")" - if not copyright_msg and (not release or release_note): - test.error_keep_going(filename + ": Please add standard 'Copyright " + str(year) + - " ...', similar to in other files" + release_note) + if not copyright_msg: + test.error_keep_going(filename + ": Please add standard 'SP" + + "DX-FileCopyrightText: " + yeardash + + " ...', similar to in other files") if not spdx: - test.error_keep_going( - filename + - ": Please add standard 'SPDX-License_Identifier: ...', similar to in other files") + test.error_keep_going(filename + ": Please add standard 'SP" + + "DX-License-Identifier: ...', similar to in other files") test.passes() diff --git a/test_regress/t/t_dist_cppstyle.py b/test_regress/t/t_dist_cppstyle.py index f473f18fb..8c79df855 100755 --- a/test_regress/t/t_dist_cppstyle.py +++ b/test_regress/t/t_dist_cppstyle.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Primitive C++ style checker # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -62,7 +62,7 @@ for filename in sorted(files.keys()): contents = test.file_contents(filename) + "\n\n" - check_pattern(filename, contents, r"[^\']*virtual[^{};\n]+override[^\n]*", None, + check_pattern(filename, contents, r"[^\'/]*virtual[^{};\n]+override[^\n]*", None, "'virtual' keyword is redundant on 'override' method") check_pattern(filename, contents, diff --git a/test_regress/t/t_dist_docs_options.py b/test_regress/t/t_dist_docs_options.py index e02e9603d..63db6b4f8 100755 --- a/test_regress/t/t_dist_docs_options.py +++ b/test_regress/t/t_dist_docs_options.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Primitive C++ style checker # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -20,6 +20,8 @@ Doc_Waivers = [ '-order-clock-delay', # Deprecated '-pp-comments', # Deprecated '-prof-threads', # Deprecated + '-xml-only', # Removed + '-xml-output', # Removed ] Test_Waivers = [ diff --git a/test_regress/t/t_dist_docs_style.py b/test_regress/t/t_dist_docs_style.py index 3b2a7f3b8..dfbdc95e8 100755 --- a/test_regress/t/t_dist_docs_style.py +++ b/test_regress/t/t_dist_docs_style.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Primitive C++ style checker # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_docs_warnings.py b/test_regress/t/t_dist_docs_warnings.py index 94e9eca9a..65901f226 100755 --- a/test_regress/t/t_dist_docs_warnings.py +++ b/test_regress/t/t_dist_docs_warnings.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Primitive C++ style checker # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_error_format.py b/test_regress/t/t_dist_error_format.py index fe06aaddf..185f47218 100755 --- a/test_regress/t/t_dist_error_format.py +++ b/test_regress/t/t_dist_error_format.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_fixme.py b/test_regress/t/t_dist_fixme.py index 6aa19f1ae..91ce4a062 100755 --- a/test_regress/t/t_dist_fixme.py +++ b/test_regress/t/t_dist_fixme.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_getsetorder.py b/test_regress/t/t_dist_getsetorder.py index ee921e959..3722c3a09 100755 --- a/test_regress/t/t_dist_getsetorder.py +++ b/test_regress/t/t_dist_getsetorder.py @@ -2,10 +2,10 @@ # DESCRIPTION: Verilator: Hacky import order checker, used to ensure all getters # come before setters for consistent codegen when using autocxx (#5182) # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_header_cc.py b/test_regress/t/t_dist_header_cc.py index 2793c77a7..a864e0700 100755 --- a/test_regress/t/t_dist_header_cc.py +++ b/test_regress/t/t_dist_header_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_install.py b/test_regress/t/t_dist_install.py index 4c21c353e..0ff093baa 100755 --- a/test_regress/t/t_dist_install.py +++ b/test_regress/t/t_dist_install.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_lint_py.py b/test_regress/t/t_dist_lint_py.py index 8ed3c11be..212f9ffb1 100755 --- a/test_regress/t/t_dist_lint_py.py +++ b/test_regress/t/t_dist_lint_py.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_pl.py b/test_regress/t/t_dist_pl.py index 365ef0f0d..9e0602289 100755 --- a/test_regress/t/t_dist_pl.py +++ b/test_regress/t/t_dist_pl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_portability.py b/test_regress/t/t_dist_portability.py index 6d9f76c80..2386f6230 100755 --- a/test_regress/t/t_dist_portability.py +++ b/test_regress/t/t_dist_portability.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_untracked.py b/test_regress/t/t_dist_untracked.py index 52ce71974..1befc8686 100755 --- a/test_regress/t/t_dist_untracked.py +++ b/test_regress/t/t_dist_untracked.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dist_warn_coverage.py b/test_regress/t/t_dist_warn_coverage.py index 076454c2a..cc209bdbc 100755 --- a/test_regress/t/t_dist_warn_coverage.py +++ b/test_regress/t/t_dist_warn_coverage.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -14,29 +14,72 @@ test.scenarios('dist') Messages = {} Outputs = {} Suppressed = {} +Used_Suppressed = {} for s in [ # Cannot hit, and comment as to why # Instead of adding here, consider adding a LCOV_EXCL_LINE/START/STOP to the sources on the message 'exited with', # Is hit; driver.py filters out 'loading non-variable', # Instead 'storing to parameter' or syntax error - 'does not allow ' - ' in the middle of literal', # Is covered, this parser misses it due to quote 'Assigned pin is neither input nor output', # Instead earlier error 'Define missing argument \'', # Instead get Define passed too many arguments 'Define or directive not defined: `', # Instead V3ParseImp will warn 'Expecting define formal arguments. Found:', # Instead define syntax error 'Syntax error: Range \':\', \'+:\' etc are not allowed in the instance', # Instead get syntax error 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error + + # Tested in t_vpi_force.cpp, but not picked up by pattern matching in this script yet + '%s: Signal \'%s\' is marked forceable, but force', + '%s: Signal \'%s\' with vpiHandle \'%p\' is marked forceable, but force', + '%s: Trailing garbage \'%s\' in \'%s\' as value %s for %s', + '%s: Non hex character \'%c\' in \'%s\' as value %s for %s', + '%s: Non octal character \'%c\' in \'%s\' as value %s for %s', + '%s: VPI force or release requested for \'%s\', but vpiHandle \'%p\' of enable', # Emitted as part of a different error message because this is thrown by a nested function + '%s: VPI force or release requested for \'%s\', but vpiHandle \'%p\' of value', # Emitted as part of a different error message because this is thrown by a nested function + # Not yet analyzed '$VERILATOR_ROOT needs to be in environment', '--pipe-filter protocol error, unexpected:', '--pipe-filter returned bad status', '--pipe-filter: stdin/stdout closed before pipe opened', '--pipe-filter: write to closed file', - 'Array initialization has too few elements, need element', 'Assigning >32 bit to unranged parameter (defaults to 32 bits)', 'Assignment pattern with no members', + '%%Warning: DPI C Function called by Verilog DPI import with missing', + '%%Warning: DPI svOpenArrayHandle function called on', + '%%Warning: DPI svOpenArrayHandle function index 1', + '%%Warning: DPI svOpenArrayHandle function index 2', + '%%Warning: DPI svOpenArrayHandle function index 3', + '%s: Ignoring vpi_put_value to vpiConstant: %s', + '%s: Ignoring vpi_put_value to vpiParameter: %s', + '%s: Index %u for object \'%s\' is out of bounds [%u,%u]', + '%s: Parsing failed for \'%s\' as value %s for %s', + '%s: Requested elements (%u) exceed array size (%u)', + '%s: Requested elements to set (%u) exceed array size (%u)', + '%s: Unsupported callback type %s', + '%s: Unsupported flags (%x)', + '%s: Unsupported format (%s) as requested for %s', + '%s: Unsupported format (%s) for %s', + '%s: Unsupported p_vpi_value as requested for \'%s\' with vpiInertialDelay', + '%s: Unsupported property %s, nothing will be returned', + '%s: Unsupported type %s, ignoring', + '%s: Unsupported type %s, nothing will be returned', + '%s: Unsupported type (%d)', + '%s: Unsupported type (%p, %s)', + '%s: Unsupported vltype (%d)', + '%s: Unsupported vpiHandle (%p)', + '%s: Unsupported vpiHandle (%p) for type %s, nothing will be returned', + '%s: Unsupported vpiUserAllocFlag (%x)', + '%s: VPI callback data pointer is null', + 'Ignoring vpi_get_time with nullptr value pointer', + 'Ignoring vpi_get_value_array with null index pointer', + 'Ignoring vpi_get_value_array with null value pointer', + 'Ignoring vpi_put_value with nullptr value pointer', + 'Ignoring vpi_put_value_array to signal marked read-only,', + 'Ignoring vpi_put_value_array with null index pointer', + 'Ignoring vpi_put_value_array with null value pointer', + 'vpi_get_value with more than VL_VALUE_STRING_MAX_WORDS; increase and', + 'vpi_put_value was used on signal marked read-only,', 'Can\'t find varpin scope of', 'Can\'t read annotation file:', 'Can\'t resolve module reference: \'', @@ -67,6 +110,7 @@ for s in [ 'Slices of arrays in assignments have different unpacked dimensions,', 'String of', 'Symbol matching', + 'Thread scheduler is unable to provide requested', 'Unexpected connection to arrayed port', 'Unsized numbers/parameters not allowed in streams.', 'Unsupported (or syntax error): Foreach on this array\'s construct', @@ -78,7 +122,6 @@ for s in [ 'Unsupported tristate port expression:', 'Unsupported/unknown built-in queue method', 'Unsupported: $bits for queue', - 'Unsupported: &&& expression', 'Unsupported: 4-state numbers in this context', 'Unsupported: Assignments with signal strength with LHS of type:', 'Unsupported: Bind with instance list', @@ -103,11 +146,9 @@ for s in [ 'Unsupported: Stream operation on a variable of a type', 'Unsupported: Unclocked assertion', 'Unsupported: Using --protect-ids with public function', - 'Unsupported: Verilog 1995 deassign', 'Unsupported: Verilog 1995 gate primitive:', 'Unsupported: [] dimensions', 'Unsupported: \'default :/\' constraint', - 'Unsupported: \'{} .* patterns', 'Unsupported: assertion items in clocking blocks', 'Unsupported: don\'t know how to deal with', 'Unsupported: extern constraint definition with class-in-class', @@ -131,7 +172,8 @@ for s in [ def read_messages(): - for filename in test.glob_some(test.root + "/src/*"): + for filename in (test.glob_some(test.root + "/src/*") + + test.glob_some(test.root + "/include/*")): if not os.path.isfile(filename): continue if '#' in filename: @@ -146,13 +188,8 @@ def read_messages(): for origline in fh: line = origline lineno += 1 - if re.match(r'^\s*//', line): - continue - if re.match(r'^\s*/\*', line): - continue - excl = excl_next - # print(('C ' if (statement != "") else 'L') + line) + excl = excl_next if 'LCOV_EXCL_START' in line: excl = True excl_next = True @@ -164,11 +201,19 @@ def read_messages(): statement = "" continue + if re.match(r'^\s*//', line): + continue + if re.match(r'^\s*/\*', line): + continue + # print(('C ' if (statement != "") else 'L') + line) + line = re.sub(r'\\n', '', line) line = re.sub(r'\s+//.*', '', line) line = line.rstrip() - m = re.search(r'\b((v3error|v3warn|v3fatal|BBUNSUP)\b.*)', line) + m = re.search( + r'\b((v3error|v3warn|v3fatal|BBUNSUP|VL_FATAL|VL_FATAL_MT|VL_SVDPI_WARN_|VL_WARN|VL_WARN_MT|VL_VPI_ERROR_|VL_VPI_WARNING_)\b.*)', + line) if m: statement = m.group(1) statement_lineno = lineno @@ -207,16 +252,69 @@ def read_outputs(): test.glob_some(test.root + "/docs/gen/*.rst")): if "t_dist_warn_coverage" in filename: # Avoid our own suppressions continue + is_python = re.search(r'\.py$', filename) with open(filename, 'r', encoding="latin-1") as fh: for line in fh: - if re.match(r'^\$date', line): # Assume it is a VCD file + # File suppressions based on magic content + if re.match(r'^\$version', line): # Assume it is a VCD file break + if re.match(r'^# SystemC::Coverage', line): # Coverage data + break + if re.match(r'^//.*verilator_coverage annotation', line): # Coverage data + break + if re.match(r'^{"type":"NETLIST"', line): # JSON + break + if re.match(r'^// *Generated by verilated_saif', line): # SAIF + break + # Line suppressions + if is_python and re.match(r'^#', line): # Assume it is a VCD file + continue line = line.lstrip().rstrip() Outputs[line] = True print("Number of outputs = " + str(len(Outputs))) +def check_msg(msg): + fileline = Messages[msg]['fileline'] + # Fast first - exact match + for output in Outputs: + if msg in output: + # print(fileline+": M '" + msg + "' HIT '" + output) + return + + # Try regexp, with %s in message changed to .*? + if re.search(r'%[a-z]', msg): + msg_re = re.escape(msg) + msg_re = re.sub(r'^%[a-z]', r'', msg_re) + msg_re = re.sub(r'%[a-z]$', r'', msg_re) + msg_re = re.sub(r'%[a-z]', r'.*?', msg_re) + # print("msg_re='%s'" % (msg_re)) + m = re.compile(msg_re) + for output in Outputs: + if re.search(m, output): + # print(fileline+": M '" + msg + "' HIT '" + output) + return + + # Some exceptions + if re.match(r'internal:', msg, re.IGNORECASE): + return + + line = Messages[msg]['line'] + line = line.lstrip().rstrip() + + if msg in Suppressed: + Used_Suppressed[msg] = True + if test.verbose: + print(fileline + ": Suppressed check for message in source: '" + msg + "'") + else: + test.error_keep_going(fileline + + ": Missing test_regress/t/*.out test for message in source: '" + + msg + "'") + if test.verbose: + print(" Line is: " + line) + + def check(): read_messages() read_outputs() @@ -231,41 +329,12 @@ def check(): print("UASSERT or v3fatalSrc instead of v3error)") print() - used_suppressed = {} - for msg in sorted(Messages.keys()): - fileline = Messages[msg]['fileline'] - next_msg = False - for output in Outputs: - if msg in output: - # print(fileline+": M '" + msg + "' HIT '" + output) - next_msg = True - break - - if next_msg: - continue - - # Some exceptions - if re.match(r'internal:', msg, re.IGNORECASE): - continue - - line = Messages[msg]['line'] - line = line.lstrip().rstrip() - - if msg in Suppressed: - used_suppressed[msg] = True - if test.verbose: - print(fileline + ": Suppressed check for message in source: '" + msg + "'") - else: - test.error_keep_going(fileline + - ": Missing test_regress/t/*.out test for message in source: '" + - msg + "'") - if test.verbose: - print(" Line is: " + line) + check_msg(msg) print() for msg in sorted(Suppressed.keys()): - if msg not in used_suppressed: + if msg not in Used_Suppressed: print("Suppression not used: '" + msg + "'") print() diff --git a/test_regress/t/t_dist_whitespace.py b/test_regress/t/t_dist_whitespace.py index d4a22288b..2b4fa35f3 100755 --- a/test_regress/t/t_dist_whitespace.py +++ b/test_regress/t/t_dist_whitespace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -13,6 +13,8 @@ test.scenarios('dist') Tabs_Exempt_Re = r'(\.out$)|(/gtkwave)|(Makefile)|(\.mk$)|(\.mk\.in$)|test_regress/t/t_preproc\.v|install-sh' +Unicode_Exempt_Re = r'(Changes$|CONTRIBUTORS$|LICENSES?|contributors.rst$|spelling.txt$)' + def get_source_files(): git_files = test.run_capture("cd " + test.root + " && git ls-files") @@ -86,11 +88,11 @@ for filename in sorted(files.keys()): # Unicode checker; should this be done in another file? # No way to auto-fix. - unicode_exempt = (re.search(r'Changes$', filename) or re.search(r'CONTRIBUTORS$', filename) - or re.search(r'contributors.rst$', filename) - or re.search(r'spelling.txt$', filename)) - if not unicode_exempt and re.search(r'[^ \t\r\n\x20-\x7e]', contents): - warns[filename] = "Warning: non-ASCII contents in " + filename + unicode_exempt = re.search(Unicode_Exempt_Re, filename) + m = re.search(r'(([^ \t\r\n\x20-\x7e]).*)', contents) + if not unicode_exempt and m: + warns[filename] = "Warning: non-ASCII contents '" + m.group(2) + "' at '" + m.group( + 1) + "' in " + filename fcount += 1 diff --git a/test_regress/t/t_do_while.py b/test_regress/t/t_do_while.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_do_while.py +++ b/test_regress/t/t_do_while.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_do_while.v b/test_regress/t/t_do_while.v index 0f572a34c..10e734d52 100644 --- a/test_regress/t/t_do_while.v +++ b/test_regress/t/t_do_while.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 function automatic int get_1; @@ -20,7 +20,7 @@ module t; a = 0; do begin - int x = 1; + automatic int x = 1; a += x; if (a == 1) begin a = 2; @@ -55,7 +55,7 @@ module t; a = 1; do begin do begin - int x = 1; + automatic int x = 1; a += x; end while (a < 3); end while (a < 5); diff --git a/test_regress/t/t_do_while_continue_bad.py b/test_regress/t/t_do_while_continue_bad.py index 7e5bcdfe5..b5718946c 100755 --- a/test_regress/t/t_do_while_continue_bad.py +++ b/test_regress/t/t_do_while_continue_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_do_while_continue_bad.v b/test_regress/t/t_do_while_continue_bad.v index e1ba1eae9..e542ef30a 100644 --- a/test_regress/t/t_do_while_continue_bad.v +++ b/test_regress/t/t_do_while_continue_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_do_while_jumps.py b/test_regress/t/t_do_while_jumps.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_do_while_jumps.py +++ b/test_regress/t/t_do_while_jumps.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_do_while_jumps.v b/test_regress/t/t_do_while_jumps.v index 8920dfac1..74096ed8f 100644 --- a/test_regress/t/t_do_while_jumps.v +++ b/test_regress/t/t_do_while_jumps.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_dos.py b/test_regress/t/t_dos.py index c3fb5ff74..16059426c 100755 --- a/test_regress/t/t_dos.py +++ b/test_regress/t/t_dos.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dos.v b/test_regress/t/t_dos.v index 52707c713..f684b38ef 100644 --- a/test_regress/t/t_dos.v +++ b/test_regress/t/t_dos.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // This file has DOS carrage returns in it! diff --git a/test_regress/t/t_dotfiles.py b/test_regress/t/t_dotfiles.py index af9106160..3145748f6 100755 --- a/test_regress/t/t_dotfiles.py +++ b/test_regress/t/t_dotfiles.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_2exp_bad.py b/test_regress/t/t_dpi_2exp_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_dpi_2exp_bad.py +++ b/test_regress/t/t_dpi_2exp_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_2exp_bad.v b/test_regress/t/t_dpi_2exp_bad.v index 5188398aa..083077413 100644 --- a/test_regress/t/t_dpi_2exp_bad.v +++ b/test_regress/t/t_dpi_2exp_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_2exparg_bad.py b/test_regress/t/t_dpi_2exparg_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_dpi_2exparg_bad.py +++ b/test_regress/t/t_dpi_2exparg_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_2exparg_bad.v b/test_regress/t/t_dpi_2exparg_bad.v index cbc2f44b3..4771911e8 100644 --- a/test_regress/t/t_dpi_2exparg_bad.v +++ b/test_regress/t/t_dpi_2exparg_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module a; diff --git a/test_regress/t/t_dpi_accessors.cpp b/test_regress/t/t_dpi_accessors.cpp index 52ee5e539..6c034d0f1 100644 --- a/test_regress/t/t_dpi_accessors.cpp +++ b/test_regress/t/t_dpi_accessors.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2012 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // // Contributed by Jeremy Bennett and Jie Xu diff --git a/test_regress/t/t_dpi_accessors.py b/test_regress/t/t_dpi_accessors.py index 13bbc4ed4..df409b3e6 100755 --- a/test_regress/t/t_dpi_accessors.py +++ b/test_regress/t/t_dpi_accessors.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # 8-Mar-2012: Modifications for this test contributed by Jeremy Bennett and diff --git a/test_regress/t/t_dpi_accessors.v b/test_regress/t/t_dpi_accessors.v index b4b367a8e..8b22d6e09 100644 --- a/test_regress/t/t_dpi_accessors.v +++ b/test_regress/t/t_dpi_accessors.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test for using DPI as general accessors // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // // Contributed by Jeremy Bennett and Jie Xul diff --git a/test_regress/t/t_dpi_accessors_inc.vh b/test_regress/t/t_dpi_accessors_inc.vh index a258018f2..7a2339678 100644 --- a/test_regress/t/t_dpi_accessors_inc.vh +++ b/test_regress/t/t_dpi_accessors_inc.vh @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Accessor definitions for test of DPI accessors // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by Jeremy Bennett and Jie Xu diff --git a/test_regress/t/t_dpi_accessors_macros_inc.vh b/test_regress/t/t_dpi_accessors_macros_inc.vh index 9a4dafcb6..90c41f5ce 100644 --- a/test_regress/t/t_dpi_accessors_macros_inc.vh +++ b/test_regress/t/t_dpi_accessors_macros_inc.vh @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Generic accessor macros for test of DPI accessors // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // // Contributed by Jeremy Bennett and Jie Xu diff --git a/test_regress/t/t_dpi_arg_inout_type.cpp b/test_regress/t/t_dpi_arg_inout_type.cpp index a8f724c79..8f67abf3d 100644 --- a/test_regress/t/t_dpi_arg_inout_type.cpp +++ b/test_regress/t/t_dpi_arg_inout_type.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_arg_inout_type.py b/test_regress/t/t_dpi_arg_inout_type.py index 50423db37..14c3a8b01 100755 --- a/test_regress/t/t_dpi_arg_inout_type.py +++ b/test_regress/t/t_dpi_arg_inout_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_arg_inout_type.v b/test_regress/t/t_dpi_arg_inout_type.v index d19483b11..c09b4559b 100644 --- a/test_regress/t/t_dpi_arg_inout_type.v +++ b/test_regress/t/t_dpi_arg_inout_type.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_arg_inout_unpack.cpp b/test_regress/t/t_dpi_arg_inout_unpack.cpp index 859714ead..d1cb24965 100644 --- a/test_regress/t/t_dpi_arg_inout_unpack.cpp +++ b/test_regress/t/t_dpi_arg_inout_unpack.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_arg_inout_unpack.py b/test_regress/t/t_dpi_arg_inout_unpack.py index 866c0c9db..9e5ecc737 100755 --- a/test_regress/t/t_dpi_arg_inout_unpack.py +++ b/test_regress/t/t_dpi_arg_inout_unpack.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_arg_inout_unpack.v b/test_regress/t/t_dpi_arg_inout_unpack.v index db24bdc37..ef8655245 100644 --- a/test_regress/t/t_dpi_arg_inout_unpack.v +++ b/test_regress/t/t_dpi_arg_inout_unpack.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_arg_input_type.cpp b/test_regress/t/t_dpi_arg_input_type.cpp index 3502597c2..1b565fc8d 100644 --- a/test_regress/t/t_dpi_arg_input_type.cpp +++ b/test_regress/t/t_dpi_arg_input_type.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_arg_input_type.py b/test_regress/t/t_dpi_arg_input_type.py index 50423db37..14c3a8b01 100755 --- a/test_regress/t/t_dpi_arg_input_type.py +++ b/test_regress/t/t_dpi_arg_input_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_arg_input_type.v b/test_regress/t/t_dpi_arg_input_type.v index d057c1dc9..116149725 100644 --- a/test_regress/t/t_dpi_arg_input_type.v +++ b/test_regress/t/t_dpi_arg_input_type.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_arg_input_unpack.cpp b/test_regress/t/t_dpi_arg_input_unpack.cpp index 78129a800..1ec2c3ed9 100644 --- a/test_regress/t/t_dpi_arg_input_unpack.cpp +++ b/test_regress/t/t_dpi_arg_input_unpack.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_arg_input_unpack.py b/test_regress/t/t_dpi_arg_input_unpack.py index 866c0c9db..9e5ecc737 100755 --- a/test_regress/t/t_dpi_arg_input_unpack.py +++ b/test_regress/t/t_dpi_arg_input_unpack.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_arg_input_unpack.v b/test_regress/t/t_dpi_arg_input_unpack.v index 3b67031bc..854990f23 100644 --- a/test_regress/t/t_dpi_arg_input_unpack.v +++ b/test_regress/t/t_dpi_arg_input_unpack.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_arg_output_type.cpp b/test_regress/t/t_dpi_arg_output_type.cpp index af32754c5..a9092561d 100644 --- a/test_regress/t/t_dpi_arg_output_type.cpp +++ b/test_regress/t/t_dpi_arg_output_type.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_arg_output_type.py b/test_regress/t/t_dpi_arg_output_type.py index 50423db37..14c3a8b01 100755 --- a/test_regress/t/t_dpi_arg_output_type.py +++ b/test_regress/t/t_dpi_arg_output_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_arg_output_type.v b/test_regress/t/t_dpi_arg_output_type.v index b7a59f6bb..bc930b283 100644 --- a/test_regress/t/t_dpi_arg_output_type.v +++ b/test_regress/t/t_dpi_arg_output_type.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_arg_output_unpack.cpp b/test_regress/t/t_dpi_arg_output_unpack.cpp index a2c55aaf6..22ae61241 100644 --- a/test_regress/t/t_dpi_arg_output_unpack.cpp +++ b/test_regress/t/t_dpi_arg_output_unpack.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_arg_output_unpack.py b/test_regress/t/t_dpi_arg_output_unpack.py index 866c0c9db..9e5ecc737 100755 --- a/test_regress/t/t_dpi_arg_output_unpack.py +++ b/test_regress/t/t_dpi_arg_output_unpack.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_arg_output_unpack.v b/test_regress/t/t_dpi_arg_output_unpack.v index d4438e829..a513fab83 100644 --- a/test_regress/t/t_dpi_arg_output_unpack.v +++ b/test_regress/t/t_dpi_arg_output_unpack.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_argtype_bad.py b/test_regress/t/t_dpi_argtype_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_dpi_argtype_bad.py +++ b/test_regress/t/t_dpi_argtype_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_argtype_bad.v b/test_regress/t/t_dpi_argtype_bad.v index b6b18e608..f940448b4 100644 --- a/test_regress/t/t_dpi_argtype_bad.v +++ b/test_regress/t/t_dpi_argtype_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2021 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_binary.py b/test_regress/t/t_dpi_binary.py index 1663c1d56..5db7dec00 100755 --- a/test_regress/t/t_dpi_binary.py +++ b/test_regress/t/t_dpi_binary.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_binary.v b/test_regress/t/t_dpi_binary.v index 320ba11f4..5f97ed49e 100644 --- a/test_regress/t/t_dpi_binary.v +++ b/test_regress/t/t_dpi_binary.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_binary_c.cpp b/test_regress/t/t_dpi_binary_c.cpp index ffe6049d1..a7023e3c6 100644 --- a/test_regress/t/t_dpi_binary_c.cpp +++ b/test_regress/t/t_dpi_binary_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_binary_c.h b/test_regress/t/t_dpi_binary_c.h index d15da366a..4ce0d3498 100644 --- a/test_regress/t/t_dpi_binary_c.h +++ b/test_regress/t/t_dpi_binary_c.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_class_param.cpp b/test_regress/t/t_dpi_class_param.cpp index f49b38d93..fb7f323fd 100644 --- a/test_regress/t/t_dpi_class_param.cpp +++ b/test_regress/t/t_dpi_class_param.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_class_param.py b/test_regress/t/t_dpi_class_param.py index aae0ff397..e515b2452 100755 --- a/test_regress/t/t_dpi_class_param.py +++ b/test_regress/t/t_dpi_class_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_class_param.v b/test_regress/t/t_dpi_class_param.v index ab02fb58d..52d09dc52 100644 --- a/test_regress/t/t_dpi_class_param.v +++ b/test_regress/t/t_dpi_class_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_dpi_context.py b/test_regress/t/t_dpi_context.py index bcdb2941d..7defa7822 100755 --- a/test_regress/t/t_dpi_context.py +++ b/test_regress/t/t_dpi_context.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_context.v b/test_regress/t/t_dpi_context.v index d246db028..a23fa6abb 100644 --- a/test_regress/t/t_dpi_context.v +++ b/test_regress/t/t_dpi_context.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_context_c.cpp b/test_regress/t/t_dpi_context_c.cpp index 9d27e8fd8..9ca792a0c 100644 --- a/test_regress/t/t_dpi_context_c.cpp +++ b/test_regress/t/t_dpi_context_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_context_noopt.py b/test_regress/t/t_dpi_context_noopt.py index c9ef10cd5..091a0269c 100755 --- a/test_regress/t/t_dpi_context_noopt.py +++ b/test_regress/t/t_dpi_context_noopt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_display.py b/test_regress/t/t_dpi_display.py index 54a8c8ece..d7672721e 100755 --- a/test_regress/t/t_dpi_display.py +++ b/test_regress/t/t_dpi_display.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_display.v b/test_regress/t/t_dpi_display.v index 756199801..31bf4ad60 100644 --- a/test_regress/t/t_dpi_display.v +++ b/test_regress/t/t_dpi_display.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_display_bad.py b/test_regress/t/t_dpi_display_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_dpi_display_bad.py +++ b/test_regress/t/t_dpi_display_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_display_bad.v b/test_regress/t/t_dpi_display_bad.v index d9731bda3..536da6df3 100644 --- a/test_regress/t/t_dpi_display_bad.v +++ b/test_regress/t/t_dpi_display_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_display_c.cpp b/test_regress/t/t_dpi_display_c.cpp index 3a8f93c92..b93fa7f1c 100644 --- a/test_regress/t/t_dpi_display_c.cpp +++ b/test_regress/t/t_dpi_display_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_dup_bad.py b/test_regress/t/t_dpi_dup_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_dpi_dup_bad.py +++ b/test_regress/t/t_dpi_dup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_dup_bad.v b/test_regress/t/t_dpi_dup_bad.v index 145b72a1d..493613856 100644 --- a/test_regress/t/t_dpi_dup_bad.v +++ b/test_regress/t/t_dpi_dup_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_export.py b/test_regress/t/t_dpi_export.py index 481162f17..ff105941a 100755 --- a/test_regress/t/t_dpi_export.py +++ b/test_regress/t/t_dpi_export.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end diff --git a/test_regress/t/t_dpi_export.v b/test_regress/t/t_dpi_export.v index c224b1fae..85dc4ebec 100644 --- a/test_regress/t/t_dpi_export.v +++ b/test_regress/t/t_dpi_export.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_export_bad.py b/test_regress/t/t_dpi_export_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_dpi_export_bad.py +++ b/test_regress/t/t_dpi_export_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_export_bad.v b/test_regress/t/t_dpi_export_bad.v index 33a25fe95..13848a457 100644 --- a/test_regress/t/t_dpi_export_bad.v +++ b/test_regress/t/t_dpi_export_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_export_c.cpp b/test_regress/t/t_dpi_export_c.cpp index 5f6cd45f3..cbc479f04 100644 --- a/test_regress/t/t_dpi_export_c.cpp +++ b/test_regress/t/t_dpi_export_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_export_context2_bad.cpp b/test_regress/t/t_dpi_export_context2_bad.cpp index 02d92ece2..b597865e6 100644 --- a/test_regress/t/t_dpi_export_context2_bad.cpp +++ b/test_regress/t/t_dpi_export_context2_bad.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_dpi_export_context2_bad.py b/test_regress/t/t_dpi_export_context2_bad.py index b84ad228c..932273505 100755 --- a/test_regress/t/t_dpi_export_context2_bad.py +++ b/test_regress/t/t_dpi_export_context2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_export_context2_bad.v b/test_regress/t/t_dpi_export_context2_bad.v index 5002b95e2..2cb62b1be 100644 --- a/test_regress/t/t_dpi_export_context2_bad.v +++ b/test_regress/t/t_dpi_export_context2_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_export_context_bad.cpp b/test_regress/t/t_dpi_export_context_bad.cpp index 27a58730a..c563f0f8a 100644 --- a/test_regress/t/t_dpi_export_context_bad.cpp +++ b/test_regress/t/t_dpi_export_context_bad.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_dpi_export_context_bad.py b/test_regress/t/t_dpi_export_context_bad.py index b84ad228c..932273505 100755 --- a/test_regress/t/t_dpi_export_context_bad.py +++ b/test_regress/t/t_dpi_export_context_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_export_context_bad.v b/test_regress/t/t_dpi_export_context_bad.v index dc4c50655..9cb2f98ee 100644 --- a/test_regress/t/t_dpi_export_context_bad.v +++ b/test_regress/t/t_dpi_export_context_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_export_noopt.py b/test_regress/t/t_dpi_export_noopt.py index d6f865acf..0919e7c46 100755 --- a/test_regress/t/t_dpi_export_noopt.py +++ b/test_regress/t/t_dpi_export_noopt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end diff --git a/test_regress/t/t_dpi_export_scope_bad.cpp b/test_regress/t/t_dpi_export_scope_bad.cpp index 66a178afc..0fba1bce5 100644 --- a/test_regress/t/t_dpi_export_scope_bad.cpp +++ b/test_regress/t/t_dpi_export_scope_bad.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_dpi_export_scope_bad.py b/test_regress/t/t_dpi_export_scope_bad.py index 2f7249020..77de3b329 100755 --- a/test_regress/t/t_dpi_export_scope_bad.py +++ b/test_regress/t/t_dpi_export_scope_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_export_scope_bad.v b/test_regress/t/t_dpi_export_scope_bad.v index 6a78eaf48..3bd725bb9 100644 --- a/test_regress/t/t_dpi_export_scope_bad.v +++ b/test_regress/t/t_dpi_export_scope_bad.v @@ -1,21 +1,29 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; - s s(); + s s (); + other other (); - import "DPI-C" context function void dpix_run_tests(); - initial dpix_run_tests(); + import "DPI-C" context function void dpix_run_tests(); + initial dpix_run_tests(); endmodule module s; - export "DPI-C" task dpix_task; - task dpix_task(); - $write("Hello in %m\n"); - endtask + export "DPI-C" task dpix_task; + task dpix_task(); + $write("Hello in %m\n"); + endtask +endmodule + +module other; + export "DPI-C" task dpix_task; + task dpix_task(); + $write("Hello in %m\n"); + endtask endmodule diff --git a/test_regress/t/t_dpi_export_scope_flat.cpp b/test_regress/t/t_dpi_export_scope_flat.cpp new file mode 100644 index 000000000..d444e9fda --- /dev/null +++ b/test_regress/t/t_dpi_export_scope_flat.cpp @@ -0,0 +1,25 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +#include + +//====================================================================== + +#include "Vt_dpi_export_scope_flat__Dpi.h" + +#ifdef NEED_EXTERNS +extern "C" { +extern void dpix_task(); +} +#endif + +//====================================================================== + +void dpix_run_tests() { + dpix_task(); // Wrong scope +} diff --git a/test_regress/t/t_dpi_export_scope_flat.py b/test_regress/t/t_dpi_export_scope_flat.py new file mode 100755 index 000000000..e9528ed81 --- /dev/null +++ b/test_regress/t/t_dpi_export_scope_flat.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--binary", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_export_scope_flat.v b/test_regress/t/t_dpi_export_scope_flat.v new file mode 100644 index 000000000..75d304d57 --- /dev/null +++ b/test_regress/t/t_dpi_export_scope_flat.v @@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t; + s s (); + + import "DPI-C" context function void dpix_run_tests(); + initial dpix_run_tests(); +endmodule + +module s; + export "DPI-C" task dpix_task; + task dpix_task(); + $write("Hello in %m\n"); + endtask +endmodule diff --git a/test_regress/t/t_dpi_if_cond.py b/test_regress/t/t_dpi_if_cond.py index 7323376c7..acc933ae9 100755 --- a/test_regress/t/t_dpi_if_cond.py +++ b/test_regress/t/t_dpi_if_cond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_if_cond.v b/test_regress/t/t_dpi_if_cond.v index 306bb010b..e3db03d5f 100644 --- a/test_regress/t/t_dpi_if_cond.v +++ b/test_regress/t/t_dpi_if_cond.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_dpi_if_cond_c.cpp b/test_regress/t/t_dpi_if_cond_c.cpp index d654fbd62..0e0324a41 100644 --- a/test_regress/t/t_dpi_if_cond_c.cpp +++ b/test_regress/t/t_dpi_if_cond_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_imp_gen.py b/test_regress/t/t_dpi_imp_gen.py index 54580144a..940fbf7ba 100755 --- a/test_regress/t/t_dpi_imp_gen.py +++ b/test_regress/t/t_dpi_imp_gen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_imp_gen.v b/test_regress/t/t_dpi_imp_gen.v index dc9a49eb0..865f7d36b 100644 --- a/test_regress/t/t_dpi_imp_gen.v +++ b/test_regress/t/t_dpi_imp_gen.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_dpi_imp_gen_c.cpp b/test_regress/t/t_dpi_imp_gen_c.cpp index b55252b19..79bd06c16 100644 --- a/test_regress/t/t_dpi_imp_gen_c.cpp +++ b/test_regress/t/t_dpi_imp_gen_c.cpp @@ -2,10 +2,10 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* diff --git a/test_regress/t/t_dpi_import.py b/test_regress/t/t_dpi_import.py index c1a90041a..04c801021 100755 --- a/test_regress/t/t_dpi_import.py +++ b/test_regress/t/t_dpi_import.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_import.v b/test_regress/t/t_dpi_import.v index abe7d18d6..7c9e26140 100644 --- a/test_regress/t/t_dpi_import.v +++ b/test_regress/t/t_dpi_import.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_import_c.cpp b/test_regress/t/t_dpi_import_c.cpp index 8bd090c6e..52bcb2d1f 100644 --- a/test_regress/t/t_dpi_import_c.cpp +++ b/test_regress/t/t_dpi_import_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_import_hdr_only.py b/test_regress/t/t_dpi_import_hdr_only.py index edb00f4b9..a1a6d32bb 100755 --- a/test_regress/t/t_dpi_import_hdr_only.py +++ b/test_regress/t/t_dpi_import_hdr_only.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_import_mix_bad.py b/test_regress/t/t_dpi_import_mix_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_dpi_import_mix_bad.py +++ b/test_regress/t/t_dpi_import_mix_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_import_mix_bad.v b/test_regress/t/t_dpi_import_mix_bad.v index e924d2f94..bb6fa043f 100644 --- a/test_regress/t/t_dpi_import_mix_bad.v +++ b/test_regress/t/t_dpi_import_mix_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_inline_new.cpp b/test_regress/t/t_dpi_inline_new.cpp index bb2877cc1..869e2bec1 100644 --- a/test_regress/t/t_dpi_inline_new.cpp +++ b/test_regress/t/t_dpi_inline_new.cpp @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: DPI stub for t_dpi_inline_new // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Include the Verilator-generated DPI header so the C prototype matches diff --git a/test_regress/t/t_dpi_inline_new.py b/test_regress/t/t_dpi_inline_new.py index d235c4eb3..063915820 100755 --- a/test_regress/t/t_dpi_inline_new.py +++ b/test_regress/t/t_dpi_inline_new.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_inline_new.v b/test_regress/t/t_dpi_inline_new.v index ef8a8dd89..eee47f080 100644 --- a/test_regress/t/t_dpi_inline_new.v +++ b/test_regress/t/t_dpi_inline_new.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2025 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 package pyhdl_if; @@ -41,7 +41,7 @@ module t ( import pyhdl_if::*; initial begin - py_tuple t0 = new; + automatic py_tuple t0 = new; py_object o; o = t0.get_item(1); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_dpi_instr_count_large.cpp b/test_regress/t/t_dpi_instr_count_large.cpp index 5e7b3b122..c6f22bf3b 100644 --- a/test_regress/t/t_dpi_instr_count_large.cpp +++ b/test_regress/t/t_dpi_instr_count_large.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2025 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_instr_count_large.py b/test_regress/t/t_dpi_instr_count_large.py index 09a785c38..2f0525e31 100755 --- a/test_regress/t/t_dpi_instr_count_large.py +++ b/test_regress/t/t_dpi_instr_count_large.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_instr_count_large.v b/test_regress/t/t_dpi_instr_count_large.v index 56824ce4b..28f23f83a 100644 --- a/test_regress/t/t_dpi_instr_count_large.v +++ b/test_regress/t/t_dpi_instr_count_large.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_dpi_instr_count_large_hier.py b/test_regress/t/t_dpi_instr_count_large_hier.py index 1ecd190a0..23091d496 100755 --- a/test_regress/t/t_dpi_instr_count_large_hier.py +++ b/test_regress/t/t_dpi_instr_count_large_hier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_lib.py b/test_regress/t/t_dpi_lib.py index f193c7954..5dffee03b 100755 --- a/test_regress/t/t_dpi_lib.py +++ b/test_regress/t/t_dpi_lib.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_lib.v b/test_regress/t/t_dpi_lib.v index 2b4b54bda..4a88e6d9a 100644 --- a/test_regress/t/t_dpi_lib.v +++ b/test_regress/t/t_dpi_lib.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_lib_c.cpp b/test_regress/t/t_dpi_lib_c.cpp index 2667681bf..688cb5d65 100644 --- a/test_regress/t/t_dpi_lib_c.cpp +++ b/test_regress/t/t_dpi_lib_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_name_bad.py b/test_regress/t/t_dpi_name_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_dpi_name_bad.py +++ b/test_regress/t/t_dpi_name_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_name_bad.v b/test_regress/t/t_dpi_name_bad.v index bf07235c0..32cd549d2 100644 --- a/test_regress/t/t_dpi_name_bad.v +++ b/test_regress/t/t_dpi_name_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_open.py b/test_regress/t/t_dpi_open.py index 159176896..f5713ec78 100755 --- a/test_regress/t/t_dpi_open.py +++ b/test_regress/t/t_dpi_open.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_open.v b/test_regress/t/t_dpi_open.v index 80b35cd91..944c8dd1a 100644 --- a/test_regress/t/t_dpi_open.v +++ b/test_regress/t/t_dpi_open.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop diff --git a/test_regress/t/t_dpi_open_c.cpp b/test_regress/t/t_dpi_open_c.cpp index a09efcbab..57836cd27 100644 --- a/test_regress/t/t_dpi_open_c.cpp +++ b/test_regress/t/t_dpi_open_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_open_elem.py b/test_regress/t/t_dpi_open_elem.py index 447d00f22..685e2a7d4 100755 --- a/test_regress/t/t_dpi_open_elem.py +++ b/test_regress/t/t_dpi_open_elem.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_open_elem.v b/test_regress/t/t_dpi_open_elem.v index 72fd58619..4e65ec90a 100644 --- a/test_regress/t/t_dpi_open_elem.v +++ b/test_regress/t/t_dpi_open_elem.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop diff --git a/test_regress/t/t_dpi_open_elem_c.cpp b/test_regress/t/t_dpi_open_elem_c.cpp index 4df979b85..2f4f24f51 100644 --- a/test_regress/t/t_dpi_open_elem_c.cpp +++ b/test_regress/t/t_dpi_open_elem_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_open_oob_bad.py b/test_regress/t/t_dpi_open_oob_bad.py index a2a8336aa..cfdcefbbb 100755 --- a/test_regress/t/t_dpi_open_oob_bad.py +++ b/test_regress/t/t_dpi_open_oob_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_open_oob_bad.v b/test_regress/t/t_dpi_open_oob_bad.v index 6218fc2c6..36a8a8098 100644 --- a/test_regress/t/t_dpi_open_oob_bad.v +++ b/test_regress/t/t_dpi_open_oob_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_open_oob_bad_c.cpp b/test_regress/t/t_dpi_open_oob_bad_c.cpp index f3b44189c..4444a9654 100644 --- a/test_regress/t/t_dpi_open_oob_bad_c.cpp +++ b/test_regress/t/t_dpi_open_oob_bad_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_open_query.cpp b/test_regress/t/t_dpi_open_query.cpp index 0af718652..435562b86 100644 --- a/test_regress/t/t_dpi_open_query.cpp +++ b/test_regress/t/t_dpi_open_query.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_open_query.py b/test_regress/t/t_dpi_open_query.py index 347bb962e..f342aedb0 100755 --- a/test_regress/t/t_dpi_open_query.py +++ b/test_regress/t/t_dpi_open_query.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_open_query.v b/test_regress/t/t_dpi_open_query.v index 2dcd89741..3634738e0 100644 --- a/test_regress/t/t_dpi_open_query.v +++ b/test_regress/t/t_dpi_open_query.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop diff --git a/test_regress/t/t_dpi_open_vecval.py b/test_regress/t/t_dpi_open_vecval.py index e2ea46c98..dac21360a 100755 --- a/test_regress/t/t_dpi_open_vecval.py +++ b/test_regress/t/t_dpi_open_vecval.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_open_vecval.v b/test_regress/t/t_dpi_open_vecval.v index f3059b9bc..1b76664a3 100644 --- a/test_regress/t/t_dpi_open_vecval.v +++ b/test_regress/t/t_dpi_open_vecval.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop diff --git a/test_regress/t/t_dpi_open_vecval_c.cpp b/test_regress/t/t_dpi_open_vecval_c.cpp index 077aea0a6..e808239b2 100644 --- a/test_regress/t/t_dpi_open_vecval_c.cpp +++ b/test_regress/t/t_dpi_open_vecval_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_openfirst.py b/test_regress/t/t_dpi_openfirst.py index 13eebeba0..0175de062 100755 --- a/test_regress/t/t_dpi_openfirst.py +++ b/test_regress/t/t_dpi_openfirst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_openfirst.v b/test_regress/t/t_dpi_openfirst.v index 9033e0515..9c645cc9e 100644 --- a/test_regress/t/t_dpi_openfirst.v +++ b/test_regress/t/t_dpi_openfirst.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR diff --git a/test_regress/t/t_dpi_openfirst_c.cpp b/test_regress/t/t_dpi_openfirst_c.cpp index d33630fe2..97283a5b1 100644 --- a/test_regress/t/t_dpi_openfirst_c.cpp +++ b/test_regress/t/t_dpi_openfirst_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_qw.py b/test_regress/t/t_dpi_qw.py index b9e84b1c1..28ca854b2 100755 --- a/test_regress/t/t_dpi_qw.py +++ b/test_regress/t/t_dpi_qw.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_qw.v b/test_regress/t/t_dpi_qw.v index 42e580f3b..efb48fb8b 100644 --- a/test_regress/t/t_dpi_qw.v +++ b/test_regress/t/t_dpi_qw.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_qw_c.cpp b/test_regress/t/t_dpi_qw_c.cpp index 751e1c331..3bd07a405 100644 --- a/test_regress/t/t_dpi_qw_c.cpp +++ b/test_regress/t/t_dpi_qw_c.cpp @@ -2,10 +2,10 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* diff --git a/test_regress/t/t_dpi_result_type.cpp b/test_regress/t/t_dpi_result_type.cpp index 1e5bf2868..2be445490 100644 --- a/test_regress/t/t_dpi_result_type.cpp +++ b/test_regress/t/t_dpi_result_type.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_result_type.py b/test_regress/t/t_dpi_result_type.py index 50423db37..14c3a8b01 100755 --- a/test_regress/t/t_dpi_result_type.py +++ b/test_regress/t/t_dpi_result_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_result_type.v b/test_regress/t/t_dpi_result_type.v index d9f1f0150..2b4ce783d 100644 --- a/test_regress/t/t_dpi_result_type.v +++ b/test_regress/t/t_dpi_result_type.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_result_type_bad.py b/test_regress/t/t_dpi_result_type_bad.py index bedc7eb77..e4c660f24 100755 --- a/test_regress/t/t_dpi_result_type_bad.py +++ b/test_regress/t/t_dpi_result_type_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_result_type_bad.v b/test_regress/t/t_dpi_result_type_bad.v index 180c2c16d..28107ed70 100644 --- a/test_regress/t/t_dpi_result_type_bad.v +++ b/test_regress/t/t_dpi_result_type_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t_dpi_result_type_bad; diff --git a/test_regress/t/t_dpi_shortcircuit.py b/test_regress/t/t_dpi_shortcircuit.py index 349844c9a..52fe6337d 100755 --- a/test_regress/t/t_dpi_shortcircuit.py +++ b/test_regress/t/t_dpi_shortcircuit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_shortcircuit.v b/test_regress/t/t_dpi_shortcircuit.v index 3505268a2..89ef95c72 100644 --- a/test_regress/t/t_dpi_shortcircuit.v +++ b/test_regress/t/t_dpi_shortcircuit.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_shortcircuit2.py b/test_regress/t/t_dpi_shortcircuit2.py index 4dffb1ad7..76a71271a 100755 --- a/test_regress/t/t_dpi_shortcircuit2.py +++ b/test_regress/t/t_dpi_shortcircuit2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_shortcircuit2.v b/test_regress/t/t_dpi_shortcircuit2.v index c5c16bd76..8401d02c6 100644 --- a/test_regress/t/t_dpi_shortcircuit2.v +++ b/test_regress/t/t_dpi_shortcircuit2.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS diff --git a/test_regress/t/t_dpi_shortcircuit_c.cpp b/test_regress/t/t_dpi_shortcircuit_c.cpp index 9a352a6b6..00607cd3b 100644 --- a/test_regress/t/t_dpi_shortcircuit_c.cpp +++ b/test_regress/t/t_dpi_shortcircuit_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2011-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2011-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_string.py b/test_regress/t/t_dpi_string.py index b45da9e3c..64dcdf684 100755 --- a/test_regress/t/t_dpi_string.py +++ b/test_regress/t/t_dpi_string.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_string.v b/test_regress/t/t_dpi_string.v index 21141b81e..6c9c6dddc 100644 --- a/test_regress/t/t_dpi_string.v +++ b/test_regress/t/t_dpi_string.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_string_c.cpp b/test_regress/t/t_dpi_string_c.cpp index 9216d9316..fcf284699 100644 --- a/test_regress/t/t_dpi_string_c.cpp +++ b/test_regress/t/t_dpi_string_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_sys.py b/test_regress/t/t_dpi_sys.py index 292a39802..8e906e5c8 100755 --- a/test_regress/t/t_dpi_sys.py +++ b/test_regress/t/t_dpi_sys.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_sys.v b/test_regress/t/t_dpi_sys.v index 13673964e..1b0ab5082 100644 --- a/test_regress/t/t_dpi_sys.v +++ b/test_regress/t/t_dpi_sys.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // Global is the most likely usage scenario diff --git a/test_regress/t/t_dpi_sys_c.cpp b/test_regress/t/t_dpi_sys_c.cpp index d1e6baf8f..16553ca92 100644 --- a/test_regress/t/t_dpi_sys_c.cpp +++ b/test_regress/t/t_dpi_sys_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_threads.py b/test_regress/t/t_dpi_threads.py index f13ae5199..2b64cb099 100755 --- a/test_regress/t/t_dpi_threads.py +++ b/test_regress/t/t_dpi_threads.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_threads.v b/test_regress/t/t_dpi_threads.v index b8637e62c..36b6e3bdd 100644 --- a/test_regress/t/t_dpi_threads.v +++ b/test_regress/t/t_dpi_threads.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2018 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" dpii_sys_task = function void \$dpii_sys (); diff --git a/test_regress/t/t_dpi_threads_c.cpp b/test_regress/t/t_dpi_threads_c.cpp index 9e02f5416..09c61822c 100644 --- a/test_regress/t/t_dpi_threads_c.cpp +++ b/test_regress/t/t_dpi_threads_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2018-2018 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2018-2018 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_threads_collide.py b/test_regress/t/t_dpi_threads_collide.py index fe226e43a..fed2d3d28 100755 --- a/test_regress/t/t_dpi_threads_collide.py +++ b/test_regress/t/t_dpi_threads_collide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_type_bad.py b/test_regress/t/t_dpi_type_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_dpi_type_bad.py +++ b/test_regress/t/t_dpi_type_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_type_bad.v b/test_regress/t/t_dpi_type_bad.v index a5113f66e..92529cfd8 100644 --- a/test_regress/t/t_dpi_type_bad.v +++ b/test_regress/t/t_dpi_type_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2021 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_unpack_bad.py b/test_regress/t/t_dpi_unpack_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_dpi_unpack_bad.py +++ b/test_regress/t/t_dpi_unpack_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_unpack_bad.v b/test_regress/t/t_dpi_unpack_bad.v index 381fbe675..209d1d379 100644 --- a/test_regress/t/t_dpi_unpack_bad.v +++ b/test_regress/t/t_dpi_unpack_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_vams.cpp b/test_regress/t/t_dpi_vams.cpp index 33fac09c8..aacbaf9d6 100644 --- a/test_regress/t/t_dpi_vams.cpp +++ b/test_regress/t/t_dpi_vams.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_dpi_vams.py b/test_regress/t/t_dpi_vams.py index f37ad07c8..b6662862a 100755 --- a/test_regress/t/t_dpi_vams.py +++ b/test_regress/t/t_dpi_vams.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_vams.v b/test_regress/t/t_dpi_vams.v index 196b42f1b..50f5983c9 100644 --- a/test_regress/t/t_dpi_vams.v +++ b/test_regress/t/t_dpi_vams.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //`begin_keywords "VAMS-2.3" diff --git a/test_regress/t/t_dpi_var.cpp b/test_regress/t/t_dpi_var.cpp index 77cf84450..6a704aa38 100644 --- a/test_regress/t/t_dpi_var.cpp +++ b/test_regress/t/t_dpi_var.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_var.py b/test_regress/t/t_dpi_var.py index b54cadf07..a12e86457 100755 --- a/test_regress/t/t_dpi_var.py +++ b/test_regress/t/t_dpi_var.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dpi_var.v b/test_regress/t/t_dpi_var.v index c809a7825..b1675d334 100644 --- a/test_regress/t/t_dpi_var.v +++ b/test_regress/t/t_dpi_var.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_dpi_var.vlt b/test_regress/t/t_dpi_var.vlt index e3982c97e..6ae8b6632 100644 --- a/test_regress/t/t_dpi_var.vlt +++ b/test_regress/t/t_dpi_var.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_dpi_var_vlt.py b/test_regress/t/t_dpi_var_vlt.py index c43dca9c4..c013162fa 100755 --- a/test_regress/t/t_dpi_var_vlt.py +++ b/test_regress/t/t_dpi_var_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_driver_random.py b/test_regress/t/t_driver_random.py index 83ab65bdd..166c94587 100755 --- a/test_regress/t/t_driver_random.py +++ b/test_regress/t/t_driver_random.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_driver_timeout.py b/test_regress/t/t_driver_timeout.py index bd3c3c3c0..517f7aaf3 100755 --- a/test_regress/t/t_driver_timeout.py +++ b/test_regress/t/t_driver_timeout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dump.v b/test_regress/t/t_dump.v index c7f3fad8d..94624910a 100644 --- a/test_regress/t/t_dump.v +++ b/test_regress/t/t_dump.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_dump_dfg.py b/test_regress/t/t_dump_dfg.py index 6a8ee8087..052e2b396 100755 --- a/test_regress/t/t_dump_dfg.py +++ b/test_regress/t/t_dump_dfg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dump_inputs_rerun.py b/test_regress/t/t_dump_inputs_rerun.py index 16fd3a5d2..46ecea2e6 100755 --- a/test_regress/t/t_dump_inputs_rerun.py +++ b/test_regress/t/t_dump_inputs_rerun.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dump_json.out b/test_regress/t/t_dump_json.out index db772cdcc..7d4153c63 100644 --- a/test_regress/t/t_dump_json.out +++ b/test_regress/t/t_dump_json.out @@ -1,24 +1,24 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"(F)","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"(F)","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"t","addr":"(G)","loc":"e,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"t","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"t","addr":"(G)","loc":"e,7:8,7:9","origName":"t","verilogName":"t","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"PORT","name":"clk","addr":"(H)","loc":"e,9:4,9:7","exprp": []}, - {"type":"VAR","name":"clk","addr":"(I)","loc":"e,11:10,11:13","dtypep":"UNLINKED","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + {"type":"VAR","name":"clk","addr":"(I)","loc":"e,11:10,11:13","dtypep":"UNLINKED","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"NONE","varType":"PORT","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"LOGIC_IMPLICIT","addr":"(J)","loc":"e,11:10,11:13","dtypep":"(J)","keyword":"LOGIC_IMPLICIT","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"LOGIC_IMPLICIT","addr":"(J)","loc":"e,11:10,11:13","dtypep":"(J)","keyword":"LOGIC_IMPLICIT","rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"cyc","addr":"(K)","loc":"e,13:12,13:15","dtypep":"UNLINKED","origName":"cyc","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + {"type":"VAR","name":"cyc","addr":"(K)","loc":"e,13:12,13:15","dtypep":"UNLINKED","origName":"cyc","verilogName":"cyc","direction":"NONE","lifetime":"NONE","varType":"VAR","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"integer","addr":"(L)","loc":"e,13:4,13:11","dtypep":"(L)","keyword":"integer","range":"31:0","generic":false,"signed":true,"rangep": []} + {"type":"BASICDTYPE","name":"integer","addr":"(L)","loc":"e,13:4,13:11","dtypep":"(L)","keyword":"integer","range":"31:0","signed":true,"rangep": []} ],"delayp": [], "valuep": [ {"type":"CONST","name":"?32?sh0","addr":"(M)","loc":"e,13:18,13:19","dtypep":"(N)"} ],"attrsp": []}, - {"type":"VAR","name":"crc","addr":"(O)","loc":"e,14:15,14:18","dtypep":"UNLINKED","origName":"crc","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + {"type":"VAR","name":"crc","addr":"(O)","loc":"e,14:15,14:18","dtypep":"UNLINKED","origName":"crc","verilogName":"crc","direction":"NONE","lifetime":"NONE","varType":"VAR","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"logic","addr":"(P)","loc":"e,14:4,14:7","dtypep":"(P)","keyword":"logic","generic":false, + {"type":"BASICDTYPE","name":"logic","addr":"(P)","loc":"e,14:4,14:7","dtypep":"(P)","keyword":"logic", "rangep": [ - {"type":"RANGE","name":"","addr":"(Q)","loc":"e,14:8,14:9","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(Q)","loc":"e,14:8,14:9", "leftp": [ {"type":"CONST","name":"?32?sh3f","addr":"(R)","loc":"e,14:9,14:11","dtypep":"(S)"} ], @@ -27,11 +27,11 @@ ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"sum","addr":"(U)","loc":"e,15:15,15:18","dtypep":"UNLINKED","origName":"sum","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"VAR","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + {"type":"VAR","name":"sum","addr":"(U)","loc":"e,15:15,15:18","dtypep":"UNLINKED","origName":"sum","verilogName":"sum","direction":"NONE","lifetime":"NONE","varType":"VAR","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"logic","addr":"(V)","loc":"e,15:4,15:7","dtypep":"(V)","keyword":"logic","generic":false, + {"type":"BASICDTYPE","name":"logic","addr":"(V)","loc":"e,15:4,15:7","dtypep":"(V)","keyword":"logic", "rangep": [ - {"type":"RANGE","name":"","addr":"(W)","loc":"e,15:8,15:9","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(W)","loc":"e,15:8,15:9", "leftp": [ {"type":"CONST","name":"?32?sh3f","addr":"(X)","loc":"e,15:9,15:11","dtypep":"(S)"} ], @@ -40,11 +40,11 @@ ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"in","addr":"(Z)","loc":"e,18:16,18:18","dtypep":"UNLINKED","origName":"in","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"WIRE","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + {"type":"VAR","name":"in","addr":"(Z)","loc":"e,18:16,18:18","dtypep":"UNLINKED","origName":"in","verilogName":"in","direction":"NONE","lifetime":"NONE","varType":"WIRE","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"logic","addr":"(AB)","loc":"e,18:9,18:10","dtypep":"(AB)","keyword":"logic","generic":false, + {"type":"BASICDTYPE","name":"logic","addr":"(AB)","loc":"e,18:9,18:10","dtypep":"(AB)","keyword":"logic", "rangep": [ - {"type":"RANGE","name":"","addr":"(BB)","loc":"e,18:9,18:10","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(BB)","loc":"e,18:9,18:10", "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(CB)","loc":"e,18:10,18:12","dtypep":"(DB)"} ], @@ -53,7 +53,7 @@ ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(FB)","loc":"e,18:19,18:20","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(FB)","loc":"e,18:19,18:20","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(GB)","loc":"e,18:19,18:20","dtypep":"UNLINKED", "rhsp": [ @@ -72,11 +72,11 @@ {"type":"PARSEREF","name":"in","addr":"(LB)","loc":"e,18:16,18:18","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": [],"strengthSpecp": []} ]}, - {"type":"VAR","name":"out","addr":"(MB)","loc":"e,22:25,22:28","dtypep":"UNLINKED","origName":"out","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"WIRE","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + {"type":"VAR","name":"out","addr":"(MB)","loc":"e,22:25,22:28","dtypep":"UNLINKED","origName":"out","verilogName":"out","direction":"NONE","lifetime":"NONE","varType":"WIRE","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"logic","addr":"(NB)","loc":"e,22:9,22:10","dtypep":"(NB)","keyword":"logic","generic":false, + {"type":"BASICDTYPE","name":"logic","addr":"(NB)","loc":"e,22:9,22:10","dtypep":"(NB)","keyword":"logic", "rangep": [ - {"type":"RANGE","name":"","addr":"(OB)","loc":"e,22:9,22:10","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(OB)","loc":"e,22:9,22:10", "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(PB)","loc":"e,22:10,22:12","dtypep":"(DB)"} ], @@ -85,9 +85,9 @@ ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"CELL","name":"test","addr":"(RB)","loc":"e,25:9,25:13","origName":"test","recursive":false,"modp":"(SB)", + {"type":"CELL","name":"test","addr":"(RB)","loc":"e,25:9,25:13","origName":"test","verilogName":"test","modp":"(SB)", "pinsp": [ - {"type":"PIN","name":"out","addr":"(TB)","loc":"e,27:15,27:18","svDotName":true,"svImplicit":false,"modVarp":"UNLINKED","modPTypep":"UNLINKED", + {"type":"PIN","name":"out","addr":"(TB)","loc":"e,27:15,27:18","svDotName":true,"modVarp":"UNLINKED","modPTypep":"UNLINKED", "exprp": [ {"type":"SELEXTRACT","name":"","addr":"(UB)","loc":"e,27:45,27:46","dtypep":"UNLINKED", "fromp": [ @@ -100,11 +100,11 @@ {"type":"CONST","name":"?32?sh0","addr":"(XB)","loc":"e,27:49,27:50","dtypep":"(N)"} ],"attrp": []} ]}, - {"type":"PIN","name":"clk","addr":"(YB)","loc":"e,29:15,29:18","svDotName":true,"svImplicit":false,"modVarp":"UNLINKED","modPTypep":"UNLINKED", + {"type":"PIN","name":"clk","addr":"(YB)","loc":"e,29:15,29:18","svDotName":true,"modVarp":"UNLINKED","modPTypep":"UNLINKED", "exprp": [ {"type":"PARSEREF","name":"clk","addr":"(ZB)","loc":"e,29:42,29:45","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ]}, - {"type":"PIN","name":"in","addr":"(AC)","loc":"e,30:15,30:17","svDotName":true,"svImplicit":false,"modVarp":"UNLINKED","modPTypep":"UNLINKED", + {"type":"PIN","name":"in","addr":"(AC)","loc":"e,30:15,30:17","svDotName":true,"modVarp":"UNLINKED","modPTypep":"UNLINKED", "exprp": [ {"type":"SELEXTRACT","name":"","addr":"(BC)","loc":"e,30:44,30:45","dtypep":"UNLINKED", "fromp": [ @@ -118,11 +118,11 @@ ],"attrp": []} ]} ],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"VAR","name":"result","addr":"(FC)","loc":"e,33:16,33:22","dtypep":"UNLINKED","origName":"result","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"WIRE","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + {"type":"VAR","name":"result","addr":"(FC)","loc":"e,33:16,33:22","dtypep":"UNLINKED","origName":"result","verilogName":"result","direction":"NONE","lifetime":"NONE","varType":"WIRE","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"logic","addr":"(GC)","loc":"e,33:9,33:10","dtypep":"(GC)","keyword":"logic","generic":false, + {"type":"BASICDTYPE","name":"logic","addr":"(GC)","loc":"e,33:9,33:10","dtypep":"(GC)","keyword":"logic", "rangep": [ - {"type":"RANGE","name":"","addr":"(HC)","loc":"e,33:9,33:10","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(HC)","loc":"e,33:9,33:10", "leftp": [ {"type":"CONST","name":"?32?sh3f","addr":"(IC)","loc":"e,33:10,33:12","dtypep":"(S)"} ], @@ -131,7 +131,7 @@ ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(KC)","loc":"e,33:23,33:24","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(KC)","loc":"e,33:23,33:24","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(LC)","loc":"e,33:23,33:24","dtypep":"UNLINKED", "rhsp": [ @@ -153,11 +153,11 @@ {"type":"PARSEREF","name":"result","addr":"(TC)","loc":"e,33:16,33:22","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ],"timingControlp": [],"strengthSpecp": []} ]}, - {"type":"ALWAYS","name":"","addr":"(UC)","loc":"e,36:4,36:10","keyword":"always","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(UC)","loc":"e,36:4,36:10","keyword":"always","sentreep": [], "stmtsp": [ {"type":"EVENTCONTROL","name":"","addr":"(VC)","loc":"e,36:11,36:12", "sentreep": [ - {"type":"SENTREE","name":"","addr":"(WC)","loc":"e,36:11,36:12","isMulti":false, + {"type":"SENTREE","name":"","addr":"(WC)","loc":"e,36:11,36:12", "sensesp": [ {"type":"SENITEM","name":"","addr":"(XC)","loc":"e,36:14,36:21","edgeType":"POS", "sensp": [ @@ -166,7 +166,7 @@ ]} ], "stmtsp": [ - {"type":"BEGIN","name":"","addr":"(ZC)","loc":"e,36:27,36:32","implied":false,"needProcess":false,"unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(ZC)","loc":"e,36:27,36:32","unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGNDLY","name":"","addr":"(AD)","loc":"e,40:11,40:13","dtypep":"UNLINKED", "rhsp": [ @@ -314,7 +314,7 @@ ]} ], "thensp": [ - {"type":"BEGIN","name":"","addr":"(BF)","loc":"e,43:21,43:26","implied":false,"needProcess":false,"unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(BF)","loc":"e,43:21,43:26","unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGNDLY","name":"","addr":"(CF)","loc":"e,45:14,45:16","dtypep":"UNLINKED", "rhsp": [ @@ -344,7 +344,7 @@ ]} ], "thensp": [ - {"type":"BEGIN","name":"","addr":"(OF)","loc":"e,48:26,48:31","implied":false,"needProcess":false,"unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(OF)","loc":"e,48:26,48:31","unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGNDLY","name":"","addr":"(PF)","loc":"e,49:14,49:16","dtypep":"UNLINKED", "rhsp": [ @@ -367,7 +367,7 @@ ]} ], "thensp": [ - {"type":"BEGIN","name":"","addr":"(XF)","loc":"e,51:26,51:31","implied":false,"needProcess":false,"unnamed":true,"declsp": [],"stmtsp": []} + {"type":"BEGIN","name":"","addr":"(XF)","loc":"e,51:26,51:31","unnamed":true,"declsp": [],"stmtsp": []} ], "elsesp": [ {"type":"IF","name":"","addr":"(YF)","loc":"e,53:12,53:14", @@ -381,7 +381,7 @@ ]} ], "thensp": [ - {"type":"BEGIN","name":"","addr":"(CG)","loc":"e,53:27,53:32","implied":false,"needProcess":false,"unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(CG)","loc":"e,53:27,53:32","unnamed":true,"declsp": [], "stmtsp": [ {"type":"DISPLAY","name":"","addr":"(DG)","loc":"e,54:10,54:16", "fmtp": [ @@ -405,7 +405,7 @@ ]} ], "thensp": [ - {"type":"STOP","name":"","addr":"(RG)","loc":"e,55:44,55:49","isFatal":false} + {"type":"STOP","name":"","addr":"(RG)","loc":"e,55:44,55:49"} ],"elsesp": []}, {"type":"IF","name":"","addr":"(SG)","loc":"e,58:10,58:12", "condp": [ @@ -418,7 +418,7 @@ ]} ], "thensp": [ - {"type":"STOP","name":"","addr":"(WG)","loc":"e,58:44,58:49","isFatal":false} + {"type":"STOP","name":"","addr":"(WG)","loc":"e,58:44,58:49"} ],"elsesp": []}, {"type":"DISPLAY","name":"","addr":"(XG)","loc":"e,59:10,59:16", "fmtp": [ @@ -437,20 +437,20 @@ ]} ]} ]}, - {"type":"MODULE","name":"Test","addr":"(SB)","loc":"e,66:8,66:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"Test","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"Test","addr":"(SB)","loc":"e,66:8,66:12","origName":"Test","verilogName":"Test","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"PORT","name":"out","addr":"(CH)","loc":"e,68:4,68:7","exprp": []}, {"type":"PORT","name":"clk","addr":"(DH)","loc":"e,70:4,70:7","exprp": []}, {"type":"PORT","name":"in","addr":"(EH)","loc":"e,70:9,70:11","exprp": []}, - {"type":"VAR","name":"clk","addr":"(FH)","loc":"e,78:10,78:13","dtypep":"UNLINKED","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + {"type":"VAR","name":"clk","addr":"(FH)","loc":"e,78:10,78:13","dtypep":"UNLINKED","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"NONE","varType":"PORT","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"LOGIC_IMPLICIT","addr":"(GH)","loc":"e,78:10,78:13","dtypep":"(GH)","keyword":"LOGIC_IMPLICIT","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"LOGIC_IMPLICIT","addr":"(GH)","loc":"e,78:10,78:13","dtypep":"(GH)","keyword":"LOGIC_IMPLICIT","rangep": []} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"in","addr":"(HH)","loc":"e,79:17,79:19","dtypep":"UNLINKED","origName":"in","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + {"type":"VAR","name":"in","addr":"(HH)","loc":"e,79:17,79:19","dtypep":"UNLINKED","origName":"in","verilogName":"in","direction":"INPUT","lifetime":"NONE","varType":"PORT","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"logic","addr":"(IH)","loc":"e,79:10,79:11","dtypep":"(IH)","keyword":"logic","generic":false, + {"type":"BASICDTYPE","name":"logic","addr":"(IH)","loc":"e,79:10,79:11","dtypep":"(IH)","keyword":"logic", "rangep": [ - {"type":"RANGE","name":"","addr":"(JH)","loc":"e,79:10,79:11","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(JH)","loc":"e,79:10,79:11", "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(KH)","loc":"e,79:11,79:13","dtypep":"(DB)"} ], @@ -459,11 +459,11 @@ ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"out","addr":"(MH)","loc":"e,80:22,80:25","dtypep":"UNLINKED","origName":"out","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", + {"type":"VAR","name":"out","addr":"(MH)","loc":"e,80:22,80:25","dtypep":"UNLINKED","origName":"out","verilogName":"out","direction":"OUTPUT","lifetime":"NONE","varType":"PORT","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"logic","addr":"(NH)","loc":"e,80:11,80:14","dtypep":"(NH)","keyword":"logic","generic":false, + {"type":"BASICDTYPE","name":"logic","addr":"(NH)","loc":"e,80:11,80:14","dtypep":"(NH)","keyword":"logic", "rangep": [ - {"type":"RANGE","name":"","addr":"(OH)","loc":"e,80:15,80:16","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(OH)","loc":"e,80:15,80:16", "leftp": [ {"type":"CONST","name":"?32?sh1f","addr":"(PH)","loc":"e,80:16,80:18","dtypep":"(DB)"} ], @@ -472,11 +472,11 @@ ]} ]} ],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(RH)","loc":"e,82:4,82:10","keyword":"always","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(RH)","loc":"e,82:4,82:10","keyword":"always","sentreep": [], "stmtsp": [ {"type":"EVENTCONTROL","name":"","addr":"(SH)","loc":"e,82:11,82:12", "sentreep": [ - {"type":"SENTREE","name":"","addr":"(TH)","loc":"e,82:11,82:12","isMulti":false, + {"type":"SENTREE","name":"","addr":"(TH)","loc":"e,82:11,82:12", "sensesp": [ {"type":"SENITEM","name":"","addr":"(UH)","loc":"e,82:13,82:20","edgeType":"POS", "sensp": [ @@ -485,7 +485,7 @@ ]} ], "stmtsp": [ - {"type":"BEGIN","name":"","addr":"(WH)","loc":"e,82:26,82:31","implied":false,"needProcess":false,"unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(WH)","loc":"e,82:26,82:31","unnamed":true,"declsp": [], "stmtsp": [ {"type":"ASSIGNDLY","name":"","addr":"(XH)","loc":"e,83:11,83:13","dtypep":"UNLINKED", "rhsp": [ @@ -535,7 +535,7 @@ "assertTypesp": [ {"type":"CONST","name":"?32?sh8","addr":"(QI)","loc":"e,90:25,90:26","dtypep":"(NF)"} ],"directiveTypesp": []}, - {"type":"BEGIN","name":"blk","addr":"(RI)","loc":"e,91:7,91:12","implied":false,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"blk","addr":"(RI)","loc":"e,91:7,91:12","declsp": [], "stmtsp": [ {"type":"DISABLE","name":"","addr":"(SI)","loc":"e,92:10,92:17", "targetRefp": [ @@ -545,11 +545,11 @@ ]} ]} ]}, - {"type":"INITIAL","name":"","addr":"(UI)","loc":"e,95:4,95:11","isSuspendable":false,"needProcess":false, + {"type":"INITIAL","name":"","addr":"(UI)","loc":"e,95:4,95:11", "stmtsp": [ - {"type":"BEGIN","name":"","addr":"(VI)","loc":"e,95:12,95:17","implied":false,"needProcess":false,"unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(VI)","loc":"e,95:12,95:17","unnamed":true,"declsp": [], "stmtsp": [ - {"type":"BEGIN","name":"assert_simple_immediate_else","addr":"(WI)","loc":"e,96:7,96:35","implied":false,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assert_simple_immediate_else","addr":"(WI)","loc":"e,96:7,96:35","declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(XI)","loc":"e,96:37,96:43","type":"[SIMPLE_IMMEDIATE]", "propp": [ @@ -565,7 +565,7 @@ ],"filep": []} ],"passsp": []} ]}, - {"type":"BEGIN","name":"assert_simple_immediate_stmt","addr":"(CJ)","loc":"e,97:7,97:35","implied":false,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assert_simple_immediate_stmt","addr":"(CJ)","loc":"e,97:7,97:35","declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(DJ)","loc":"e,97:37,97:43","type":"[SIMPLE_IMMEDIATE]", "propp": [ @@ -581,7 +581,7 @@ ],"filep": []} ]} ]}, - {"type":"BEGIN","name":"assert_simple_immediate_stmt_else","addr":"(IJ)","loc":"e,98:7,98:40","implied":false,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assert_simple_immediate_stmt_else","addr":"(IJ)","loc":"e,98:7,98:40","declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(JJ)","loc":"e,98:42,98:48","type":"[SIMPLE_IMMEDIATE]", "propp": [ @@ -606,14 +606,14 @@ ],"filep": []} ]} ]}, - {"type":"BEGIN","name":"assume_simple_immediate","addr":"(RJ)","loc":"e,100:7,100:30","implied":false,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assume_simple_immediate","addr":"(RJ)","loc":"e,100:7,100:30","declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(SJ)","loc":"e,100:32,100:38","type":"[SIMPLE_IMMEDIATE]", "propp": [ {"type":"CONST","name":"?32?sh0","addr":"(TJ)","loc":"e,100:39,100:40","dtypep":"(N)"} ],"sentreep": [],"failsp": [],"passsp": []} ]}, - {"type":"BEGIN","name":"assume_simple_immediate_else","addr":"(UJ)","loc":"e,101:7,101:35","implied":false,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assume_simple_immediate_else","addr":"(UJ)","loc":"e,101:7,101:35","declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(VJ)","loc":"e,101:37,101:43","type":"[SIMPLE_IMMEDIATE]", "propp": [ @@ -629,7 +629,7 @@ ],"filep": []} ],"passsp": []} ]}, - {"type":"BEGIN","name":"assume_simple_immediate_stmt","addr":"(AK)","loc":"e,102:7,102:35","implied":false,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assume_simple_immediate_stmt","addr":"(AK)","loc":"e,102:7,102:35","declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(BK)","loc":"e,102:37,102:43","type":"[SIMPLE_IMMEDIATE]", "propp": [ @@ -645,7 +645,7 @@ ],"filep": []} ]} ]}, - {"type":"BEGIN","name":"assume_simple_immediate_stmt_else","addr":"(GK)","loc":"e,103:7,103:40","implied":false,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assume_simple_immediate_stmt_else","addr":"(GK)","loc":"e,103:7,103:40","declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(HK)","loc":"e,103:42,103:48","type":"[SIMPLE_IMMEDIATE]", "propp": [ @@ -672,9 +672,9 @@ ]} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(PK)","loc":"e,106:4,106:38","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(PK)","loc":"e,106:4,106:38","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assert_observed_deferred_immediate","addr":"(QK)","loc":"e,106:4,106:38","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assert_observed_deferred_immediate","addr":"(QK)","loc":"e,106:4,106:38","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(RK)","loc":"e,106:40,106:46","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ @@ -682,9 +682,9 @@ ],"sentreep": [],"failsp": [],"passsp": []} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(TK)","loc":"e,107:4,107:43","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(TK)","loc":"e,107:4,107:43","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assert_observed_deferred_immediate_else","addr":"(UK)","loc":"e,107:4,107:43","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assert_observed_deferred_immediate_else","addr":"(UK)","loc":"e,107:4,107:43","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(VK)","loc":"e,107:45,107:51","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ @@ -701,9 +701,9 @@ ],"passsp": []} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(AL)","loc":"e,108:4,108:43","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(AL)","loc":"e,108:4,108:43","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assert_observed_deferred_immediate_stmt","addr":"(BL)","loc":"e,108:4,108:43","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assert_observed_deferred_immediate_stmt","addr":"(BL)","loc":"e,108:4,108:43","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(CL)","loc":"e,108:45,108:51","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ @@ -720,9 +720,9 @@ ]} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(HL)","loc":"e,109:4,109:48","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(HL)","loc":"e,109:4,109:48","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assert_observed_deferred_immediate_stmt_else","addr":"(IL)","loc":"e,109:4,109:48","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assert_observed_deferred_immediate_stmt_else","addr":"(IL)","loc":"e,109:4,109:48","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(JL)","loc":"e,109:50,109:56","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ @@ -748,9 +748,9 @@ ]} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(RL)","loc":"e,111:4,111:38","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(RL)","loc":"e,111:4,111:38","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assume_observed_deferred_immediate","addr":"(SL)","loc":"e,111:4,111:38","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assume_observed_deferred_immediate","addr":"(SL)","loc":"e,111:4,111:38","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(TL)","loc":"e,111:40,111:46","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ @@ -758,9 +758,9 @@ ],"sentreep": [],"failsp": [],"passsp": []} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(VL)","loc":"e,112:4,112:43","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(VL)","loc":"e,112:4,112:43","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assume_observed_deferred_immediate_else","addr":"(WL)","loc":"e,112:4,112:43","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assume_observed_deferred_immediate_else","addr":"(WL)","loc":"e,112:4,112:43","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(XL)","loc":"e,112:45,112:51","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ @@ -777,9 +777,9 @@ ],"passsp": []} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(CM)","loc":"e,113:4,113:43","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(CM)","loc":"e,113:4,113:43","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assume_observed_deferred_immediate_stmt","addr":"(DM)","loc":"e,113:4,113:43","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assume_observed_deferred_immediate_stmt","addr":"(DM)","loc":"e,113:4,113:43","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(EM)","loc":"e,113:45,113:51","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ @@ -796,9 +796,9 @@ ]} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(JM)","loc":"e,114:4,114:48","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(JM)","loc":"e,114:4,114:48","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assume_observed_deferred_immediate_stmt_else","addr":"(KM)","loc":"e,114:4,114:48","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assume_observed_deferred_immediate_stmt_else","addr":"(KM)","loc":"e,114:4,114:48","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(LM)","loc":"e,114:50,114:56","type":"[OBSERVED_DEFERRED_IMMEDIATE]", "propp": [ @@ -824,9 +824,9 @@ ]} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(TM)","loc":"e,116:4,116:35","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(TM)","loc":"e,116:4,116:35","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assert_final_deferred_immediate","addr":"(UM)","loc":"e,116:4,116:35","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assert_final_deferred_immediate","addr":"(UM)","loc":"e,116:4,116:35","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(VM)","loc":"e,116:37,116:43","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ @@ -834,9 +834,9 @@ ],"sentreep": [],"failsp": [],"passsp": []} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(XM)","loc":"e,117:4,117:40","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(XM)","loc":"e,117:4,117:40","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assert_final_deferred_immediate_else","addr":"(YM)","loc":"e,117:4,117:40","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assert_final_deferred_immediate_else","addr":"(YM)","loc":"e,117:4,117:40","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(ZM)","loc":"e,117:42,117:48","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ @@ -853,9 +853,9 @@ ],"passsp": []} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(EN)","loc":"e,118:4,118:40","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(EN)","loc":"e,118:4,118:40","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assert_final_deferred_immediate_stmt","addr":"(FN)","loc":"e,118:4,118:40","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + {"type":"BEGIN","name":"assert_final_deferred_immediate_stmt","addr":"(FN)","loc":"e,118:4,118:40","implied":true,"declsp": [], "stmtsp": [ {"type":"ASSERT","name":"","addr":"(GN)","loc":"e,118:42,118:48","type":"[FINAL_DEFERRED_IMMEDIATE]", "propp": [ @@ -872,9 +872,9 @@ ]} ]} ]}, - {"type":"ALWAYS","name":"","addr":"(LN)","loc":"e,119:4,119:45","keyword":"always_comb","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(LN)","loc":"e,119:4,119:45","keyword":"always_comb","sentreep": [], "stmtsp": [ - {"type":"BEGIN","name":"assert_final_deferred_immediate_stmt_else","addr":"(MN)","loc":"e,119:4,119:45","implied":true,"needProcess":false,"unnamed":false,"declsp": [], + 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{"type":"ENUMITEM","name":"RUNNING","addr":"(SBB)","loc":"d,132:7,132:14","dtypep":"UNLINKED","rangep": [], + {"type":"ENUMITEM","name":"RUNNING","addr":"(KBB)","loc":"d,133:7,133:14","dtypep":"UNLINKED","rangep": [], "valuep": [ - {"type":"CONST","name":"?32?sh1","addr":"(TBB)","loc":"d,132:17,132:18","dtypep":"(N)"} + {"type":"CONST","name":"?32?sh1","addr":"(LBB)","loc":"d,133:17,133:18","dtypep":"(N)"} ]}, - {"type":"ENUMITEM","name":"WAITING","addr":"(UBB)","loc":"d,133:7,133:14","dtypep":"UNLINKED","rangep": [], + {"type":"ENUMITEM","name":"WAITING","addr":"(MBB)","loc":"d,134:7,134:14","dtypep":"UNLINKED","rangep": [], "valuep": [ - {"type":"CONST","name":"?32?sh2","addr":"(VBB)","loc":"d,133:17,133:18","dtypep":"(UD)"} + {"type":"CONST","name":"?32?sh2","addr":"(NBB)","loc":"d,134:17,134:18","dtypep":"(UD)"} ]}, - {"type":"ENUMITEM","name":"SUSPENDED","addr":"(WBB)","loc":"d,134:7,134:16","dtypep":"UNLINKED","rangep": [], + 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{"type":"VAR","name":"p","addr":"(XBB)","loc":"d,143:15,143:16","dtypep":"UNLINKED","origName":"p","verilogName":"p","direction":"NONE","lifetime":"NONE","varType":"VAR","sensIfacep":"UNLINKED", "childDTypep": [ - {"type":"REFDTYPE","name":"process","addr":"(GCB)","loc":"d,142:7,142:14","dtypep":"UNLINKED","generic":false,"typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} + {"type":"REFDTYPE","name":"process","addr":"(YBB)","loc":"d,143:7,143:14","dtypep":"UNLINKED","typedefp":"UNLINKED","refDTypep":"UNLINKED","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []} ],"delayp": [], "valuep": [ - {"type":"NEW","name":"new","addr":"(HCB)","loc":"d,142:19,142:22","dtypep":"UNLINKED","isImplicit":false,"isScoped":false,"dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","namep": [],"pinsp": [],"scopeNamep": []} + {"type":"NEW","name":"new","addr":"(ZBB)","loc":"d,143:19,143:22","dtypep":"UNLINKED","dotted":"","taskp":"UNLINKED","classOrPackagep":"UNLINKED","argsp": [],"withp": [],"scopeNamep": []} ],"attrsp": []}, - {"type":"CSTMTUSER","name":"","addr":"(ICB)","loc":"d,144:7,144:9", + {"type":"CSTMTUSER","name":"","addr":"(ACB)","loc":"d,145:7,145:9", "nodesp": [ - {"type":"DOT","name":"","addr":"(JCB)","loc":"d,144:11,144:12","dtypep":"UNLINKED","colon":false, + {"type":"DOT","name":"","addr":"(BCB)","loc":"d,145:11,145:12","dtypep":"UNLINKED", "lhsp": [ - {"type":"PARSEREF","name":"p","addr":"(KCB)","loc":"d,144:10,144:11","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + {"type":"PARSEREF","name":"p","addr":"(CCB)","loc":"d,145:10,145:11","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} ], "rhsp": [ - {"type":"PARSEREF","name":"m_process","addr":"(LCB)","loc":"d,144:12,144:21","dtypep":"UNLINKED","lhsp": [],"ftaskrefp": []} + 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{"type":"DISPLAY","name":"","addr":"(DDB)","loc":"d,169:7,169:13", "fmtp": [ - {"type":"SFORMATF","name":"","addr":"(MDB)","loc":"d,168:7,168:13","dtypep":"(FG)", + {"type":"SFORMATF","name":"","addr":"(EDB)","loc":"d,169:7,169:13","dtypep":"(FG)", "exprsp": [ - {"type":"CONST","name":"296'h7374643a3a70726f636573733a3a73757370656e642829206e6f7420737570706f72746564","addr":"(NDB)","loc":"d,168:14,168:53","dtypep":"(ODB)"} + {"type":"CONST","name":"296'h7374643a3a70726f636573733a3a73757370656e642829206e6f7420737570706f72746564","addr":"(FDB)","loc":"d,169:14,169:53","dtypep":"(GDB)"} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(PDB)","loc":"d,168:7,168:13","isFatal":false} + {"type":"STOP","name":"","addr":"(HDB)","loc":"d,169:7,169:13"} ],"scopeNamep": []}, - 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{"type":"MEMBERDTYPE","name":"cross_retain_auto_bins","addr":"(RIB)","loc":"d,278:9,278:31","dtypep":"UNLINKED","isConstrainedRand":false,"name":"cross_retain_auto_bins","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"cross_retain_auto_bins","addr":"(JIB)","loc":"d,279:9,279:31","dtypep":"UNLINKED","name":"cross_retain_auto_bins","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"bit","addr":"(SIB)","loc":"d,278:5,278:8","dtypep":"(SIB)","keyword":"bit","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"bit","addr":"(KIB)","loc":"d,279:5,279:8","dtypep":"(KIB)","keyword":"bit","rangep": []} ],"valuep": []} ]} ]} ],"attrsp": []}, - {"type":"TYPEDEF","name":"vl_covergroup_type_options_t","addr":"(TIB)","loc":"d,289:5,289:33","dtypep":"UNLINKED","attrPublic":false,"isUnderClass":false, + {"type":"TYPEDEF","name":"vl_covergroup_type_options_t","addr":"(LIB)","loc":"d,290:5,290:33","dtypep":"UNLINKED", "childDTypep": [ - {"type":"DEFIMPLICITDTYPE","name":"__typeimpsu4","addr":"(UIB)","loc":"d,281:11,281:17","dtypep":"UNLINKED","generic":false, + {"type":"DEFIMPLICITDTYPE","name":"__typeimpsu4","addr":"(MIB)","loc":"d,282:11,282:17","dtypep":"UNLINKED", "childDTypep": [ - {"type":"STRUCTDTYPE","name":"","addr":"(VIB)","loc":"d,281:11,281:17","dtypep":"UNLINKED","packed":false,"isFourstate":false,"generic":false,"classOrPackagep":"UNLINKED", + {"type":"STRUCTDTYPE","name":"","addr":"(NIB)","loc":"d,282:11,282:17","dtypep":"UNLINKED","classOrPackagep":"UNLINKED", "membersp": [ - {"type":"MEMBERDTYPE","name":"weight","addr":"(WIB)","loc":"d,282:9,282:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"weight","addr":"(OIB)","loc":"d,283:9,283:15","dtypep":"UNLINKED","name":"weight","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(XIB)","loc":"d,282:5,282:8","dtypep":"(XIB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(PIB)","loc":"d,283:5,283:8","dtypep":"(PIB)","keyword":"int","range":"31:0","signed":true,"rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"goal","addr":"(YIB)","loc":"d,283:9,283:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"goal","addr":"(QIB)","loc":"d,284:9,284:13","dtypep":"UNLINKED","name":"goal","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(ZIB)","loc":"d,283:5,283:8","dtypep":"(ZIB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(RIB)","loc":"d,284:5,284:8","dtypep":"(RIB)","keyword":"int","range":"31:0","signed":true,"rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"comment","addr":"(AJB)","loc":"d,284:12,284:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"comment","addr":"(SIB)","loc":"d,285:12,285:19","dtypep":"UNLINKED","name":"comment","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"string","addr":"(BJB)","loc":"d,284:5,284:11","dtypep":"(BJB)","keyword":"string","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"string","addr":"(TIB)","loc":"d,285:5,285:11","dtypep":"(TIB)","keyword":"string","rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"strobe","addr":"(CJB)","loc":"d,285:9,285:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"strobe","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"strobe","addr":"(UIB)","loc":"d,286:9,286:15","dtypep":"UNLINKED","name":"strobe","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"bit","addr":"(DJB)","loc":"d,285:5,285:8","dtypep":"(DJB)","keyword":"bit","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"bit","addr":"(VIB)","loc":"d,286:5,286:8","dtypep":"(VIB)","keyword":"bit","rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"merge_instances","addr":"(EJB)","loc":"d,286:9,286:24","dtypep":"UNLINKED","isConstrainedRand":false,"name":"merge_instances","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"merge_instances","addr":"(WIB)","loc":"d,287:9,287:24","dtypep":"UNLINKED","name":"merge_instances","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"bit","addr":"(FJB)","loc":"d,286:5,286:8","dtypep":"(FJB)","keyword":"bit","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"bit","addr":"(XIB)","loc":"d,287:5,287:8","dtypep":"(XIB)","keyword":"bit","rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"distribute_first","addr":"(GJB)","loc":"d,287:9,287:25","dtypep":"UNLINKED","isConstrainedRand":false,"name":"distribute_first","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"distribute_first","addr":"(YIB)","loc":"d,288:9,288:25","dtypep":"UNLINKED","name":"distribute_first","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"bit","addr":"(HJB)","loc":"d,287:5,287:8","dtypep":"(HJB)","keyword":"bit","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"bit","addr":"(ZIB)","loc":"d,288:5,288:8","dtypep":"(ZIB)","keyword":"bit","rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"real_interval","addr":"(IJB)","loc":"d,288:10,288:23","dtypep":"UNLINKED","isConstrainedRand":false,"name":"real_interval","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"real_interval","addr":"(AJB)","loc":"d,289:10,289:23","dtypep":"UNLINKED","name":"real_interval","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"real","addr":"(JJB)","loc":"d,288:5,288:9","dtypep":"(JJB)","keyword":"real","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"real","addr":"(BJB)","loc":"d,289:5,289:9","dtypep":"(BJB)","keyword":"real","rangep": []} ],"valuep": []} ]} ]} ],"attrsp": []}, - {"type":"TYPEDEF","name":"vl_coverpoint_type_options_t","addr":"(KJB)","loc":"d,296:5,296:33","dtypep":"UNLINKED","attrPublic":false,"isUnderClass":false, + {"type":"TYPEDEF","name":"vl_coverpoint_type_options_t","addr":"(CJB)","loc":"d,297:5,297:33","dtypep":"UNLINKED", "childDTypep": [ - {"type":"DEFIMPLICITDTYPE","name":"__typeimpsu5","addr":"(LJB)","loc":"d,291:11,291:17","dtypep":"UNLINKED","generic":false, + {"type":"DEFIMPLICITDTYPE","name":"__typeimpsu5","addr":"(DJB)","loc":"d,292:11,292:17","dtypep":"UNLINKED", "childDTypep": [ - {"type":"STRUCTDTYPE","name":"","addr":"(MJB)","loc":"d,291:11,291:17","dtypep":"UNLINKED","packed":false,"isFourstate":false,"generic":false,"classOrPackagep":"UNLINKED", + {"type":"STRUCTDTYPE","name":"","addr":"(EJB)","loc":"d,292:11,292:17","dtypep":"UNLINKED","classOrPackagep":"UNLINKED", "membersp": [ - {"type":"MEMBERDTYPE","name":"weight","addr":"(NJB)","loc":"d,292:9,292:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"weight","addr":"(FJB)","loc":"d,293:9,293:15","dtypep":"UNLINKED","name":"weight","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(OJB)","loc":"d,292:5,292:8","dtypep":"(OJB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(GJB)","loc":"d,293:5,293:8","dtypep":"(GJB)","keyword":"int","range":"31:0","signed":true,"rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"goal","addr":"(PJB)","loc":"d,293:9,293:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"goal","addr":"(HJB)","loc":"d,294:9,294:13","dtypep":"UNLINKED","name":"goal","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(QJB)","loc":"d,293:5,293:8","dtypep":"(QJB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(IJB)","loc":"d,294:5,294:8","dtypep":"(IJB)","keyword":"int","range":"31:0","signed":true,"rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"comment","addr":"(RJB)","loc":"d,294:12,294:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"comment","addr":"(JJB)","loc":"d,295:12,295:19","dtypep":"UNLINKED","name":"comment","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"string","addr":"(SJB)","loc":"d,294:5,294:11","dtypep":"(SJB)","keyword":"string","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"string","addr":"(KJB)","loc":"d,295:5,295:11","dtypep":"(KJB)","keyword":"string","rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"real_interval","addr":"(TJB)","loc":"d,295:10,295:23","dtypep":"UNLINKED","isConstrainedRand":false,"name":"real_interval","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"real_interval","addr":"(LJB)","loc":"d,296:10,296:23","dtypep":"UNLINKED","name":"real_interval","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"real","addr":"(UJB)","loc":"d,295:5,295:9","dtypep":"(UJB)","keyword":"real","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"real","addr":"(MJB)","loc":"d,296:5,296:9","dtypep":"(MJB)","keyword":"real","rangep": []} ],"valuep": []} ]} ]} ],"attrsp": []}, - {"type":"TYPEDEF","name":"vl_cross_type_options_t","addr":"(VJB)","loc":"d,302:5,302:28","dtypep":"UNLINKED","attrPublic":false,"isUnderClass":false, + {"type":"TYPEDEF","name":"vl_cross_type_options_t","addr":"(NJB)","loc":"d,303:5,303:28","dtypep":"UNLINKED", "childDTypep": [ - {"type":"DEFIMPLICITDTYPE","name":"__typeimpsu6","addr":"(WJB)","loc":"d,298:11,298:17","dtypep":"UNLINKED","generic":false, + {"type":"DEFIMPLICITDTYPE","name":"__typeimpsu6","addr":"(OJB)","loc":"d,299:11,299:17","dtypep":"UNLINKED", "childDTypep": [ - {"type":"STRUCTDTYPE","name":"","addr":"(XJB)","loc":"d,298:11,298:17","dtypep":"UNLINKED","packed":false,"isFourstate":false,"generic":false,"classOrPackagep":"UNLINKED", + {"type":"STRUCTDTYPE","name":"","addr":"(PJB)","loc":"d,299:11,299:17","dtypep":"UNLINKED","classOrPackagep":"UNLINKED", "membersp": [ - {"type":"MEMBERDTYPE","name":"weight","addr":"(YJB)","loc":"d,299:9,299:15","dtypep":"UNLINKED","isConstrainedRand":false,"name":"weight","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"weight","addr":"(QJB)","loc":"d,300:9,300:15","dtypep":"UNLINKED","name":"weight","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(ZJB)","loc":"d,299:5,299:8","dtypep":"(ZJB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(RJB)","loc":"d,300:5,300:8","dtypep":"(RJB)","keyword":"int","range":"31:0","signed":true,"rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"goal","addr":"(AKB)","loc":"d,300:9,300:13","dtypep":"UNLINKED","isConstrainedRand":false,"name":"goal","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"goal","addr":"(SJB)","loc":"d,301:9,301:13","dtypep":"UNLINKED","name":"goal","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"int","addr":"(BKB)","loc":"d,300:5,300:8","dtypep":"(BKB)","keyword":"int","range":"31:0","generic":false,"signed":true,"rangep": []} + {"type":"BASICDTYPE","name":"int","addr":"(TJB)","loc":"d,301:5,301:8","dtypep":"(TJB)","keyword":"int","range":"31:0","signed":true,"rangep": []} ],"valuep": []}, - {"type":"MEMBERDTYPE","name":"comment","addr":"(CKB)","loc":"d,301:12,301:19","dtypep":"UNLINKED","isConstrainedRand":false,"name":"comment","tag":"","generic":false,"refDTypep":"UNLINKED", + {"type":"MEMBERDTYPE","name":"comment","addr":"(UJB)","loc":"d,302:12,302:19","dtypep":"UNLINKED","name":"comment","tag":"","refDTypep":"UNLINKED", "childDTypep": [ - {"type":"BASICDTYPE","name":"string","addr":"(DKB)","loc":"d,301:5,301:11","dtypep":"(DKB)","keyword":"string","generic":false,"rangep": []} + {"type":"BASICDTYPE","name":"string","addr":"(VJB)","loc":"d,302:5,302:11","dtypep":"(VJB)","keyword":"string","rangep": []} ],"valuep": []} ]} ]} @@ -2323,16 +2299,16 @@ ]} ],"filesp": [], "miscsp": [ - {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(EV)", + {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(WU)", "typesp": [ - {"type":"BASICDTYPE","name":"integer","addr":"(ST)","loc":"d,37:25,37:26","dtypep":"(ST)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(N)","loc":"d,39:30,39:31","dtypep":"(N)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(YE)","loc":"d,49:22,49:24","dtypep":"(YE)","keyword":"logic","generic":true,"rangep": []}, - {"type":"VOIDDTYPE","name":"","addr":"(EV)","loc":"d,51:15,51:24","dtypep":"(EV)","generic":false}, - {"type":"BASICDTYPE","name":"logic","addr":"(UD)","loc":"d,133:17,133:18","dtypep":"(UD)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(ACB)","loc":"d,135:16,135:17","dtypep":"(ACB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(ODB)","loc":"d,168:14,168:53","dtypep":"(ODB)","keyword":"logic","range":"295:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"string","addr":"(FG)","loc":"d,168:7,168:13","dtypep":"(FG)","keyword":"string","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"integer","addr":"(KT)","loc":"d,38:25,38:26","dtypep":"(KT)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(N)","loc":"d,40:30,40:31","dtypep":"(N)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(YE)","loc":"d,50:22,50:24","dtypep":"(YE)","keyword":"logic","generic":true,"rangep": []}, + {"type":"VOIDDTYPE","name":"","addr":"(WU)","loc":"d,52:15,52:24","dtypep":"(WU)"}, + {"type":"BASICDTYPE","name":"logic","addr":"(UD)","loc":"d,134:17,134:18","dtypep":"(UD)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(SBB)","loc":"d,136:16,136:17","dtypep":"(SBB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(GDB)","loc":"d,169:14,169:53","dtypep":"(GDB)","keyword":"logic","range":"295:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"string","addr":"(FG)","loc":"d,169:7,169:13","dtypep":"(FG)","keyword":"string","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"e,14:9,14:11","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"e,18:10,18:12","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(QC)","loc":"e,33:26,33:31","dtypep":"(QC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, @@ -2343,13 +2319,13 @@ {"type":"BASICDTYPE","name":"logic","addr":"(HG)","loc":"e,54:17,54:49","dtypep":"(HG)","keyword":"logic","range":"231:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"QData","addr":"(JG)","loc":"e,54:51,54:56","dtypep":"(JG)","keyword":"QData","range":"63:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(AH)","loc":"e,59:17,59:41","dtypep":"(AH)","keyword":"logic","range":"167:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(PS)","loc":"e,147:20,147:24","dtypep":"(PS)","keyword":"logic","range":"15:0","generic":true,"rangep": []} + {"type":"BASICDTYPE","name":"logic","addr":"(HS)","loc":"e,147:20,147:24","dtypep":"(HS)","keyword":"logic","range":"15:0","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(EKB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(WJB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ - {"type":"SCOPE","name":"@CONST-POOL@","addr":"(FKB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(EKB)","varsp": [],"blocksp": [],"inlinesp": []} + {"type":"SCOPE","name":"@CONST-POOL@","addr":"(XJB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(WJB)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} diff --git a/test_regress/t/t_dump_json.py b/test_regress/t/t_dump_json.py index 71ce0e5d0..027ddadb2 100755 --- a/test_regress/t/t_dump_json.py +++ b/test_regress/t/t_dump_json.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dump_tree_dot.py b/test_regress/t/t_dump_tree_dot.py index e840dded0..0f5e72f2f 100755 --- a/test_regress/t/t_dump_tree_dot.py +++ b/test_regress/t/t_dump_tree_dot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray.py b/test_regress/t/t_dynarray.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_dynarray.py +++ b/test_regress/t/t_dynarray.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray.v b/test_regress/t/t_dynarray.v index f4827b712..caf299693 100644 --- a/test_regress/t/t_dynarray.v +++ b/test_regress/t/t_dynarray.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_dynarray_bad.py b/test_regress/t/t_dynarray_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_dynarray_bad.py +++ b/test_regress/t/t_dynarray_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray_bad.v b/test_regress/t/t_dynarray_bad.v index c14a8ac34..462ec0697 100644 --- a/test_regress/t/t_dynarray_bad.v +++ b/test_regress/t/t_dynarray_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_dynarray_bits.py b/test_regress/t/t_dynarray_bits.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_dynarray_bits.py +++ b/test_regress/t/t_dynarray_bits.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray_bits.v b/test_regress/t/t_dynarray_bits.v index f3aa78bd5..d9d8ad9f8 100644 --- a/test_regress/t/t_dynarray_bits.v +++ b/test_regress/t/t_dynarray_bits.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_dynarray_cast_write.py b/test_regress/t/t_dynarray_cast_write.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_dynarray_cast_write.py +++ b/test_regress/t/t_dynarray_cast_write.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray_cast_write.v b/test_regress/t/t_dynarray_cast_write.v index 9df1af50c..b7e69e509 100644 --- a/test_regress/t/t_dynarray_cast_write.v +++ b/test_regress/t/t_dynarray_cast_write.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -16,10 +16,10 @@ endclass module t; initial begin - int sel_bit = 3; - Bar bar = new; - Foo foo = bar; - Bar bars[] = new[4]; + automatic int sel_bit = 3; + automatic Bar bar = new; + automatic Foo foo = bar; + automatic Bar bars[] = new[4]; $cast(bars[0], foo); if (bars[0].x != 2) $stop; diff --git a/test_regress/t/t_dynarray_concat.py b/test_regress/t/t_dynarray_concat.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_dynarray_concat.py +++ b/test_regress/t/t_dynarray_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray_concat.v b/test_regress/t/t_dynarray_concat.v index 6ac0ed946..3333de4b3 100644 --- a/test_regress/t/t_dynarray_concat.v +++ b/test_regress/t/t_dynarray_concat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef VERILATOR diff --git a/test_regress/t/t_dynarray_init.py b/test_regress/t/t_dynarray_init.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_dynarray_init.py +++ b/test_regress/t/t_dynarray_init.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray_init.v b/test_regress/t/t_dynarray_init.v index df1e1430c..9f5439cc9 100644 --- a/test_regress/t/t_dynarray_init.v +++ b/test_regress/t/t_dynarray_init.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_dynarray_method.py b/test_regress/t/t_dynarray_method.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_dynarray_method.py +++ b/test_regress/t/t_dynarray_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray_method.v b/test_regress/t/t_dynarray_method.v index c46050d42..095d9c2fe 100644 --- a/test_regress/t/t_dynarray_method.v +++ b/test_regress/t/t_dynarray_method.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_dynarray_method_bad.py b/test_regress/t/t_dynarray_method_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_dynarray_method_bad.py +++ b/test_regress/t/t_dynarray_method_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray_method_bad.v b/test_regress/t/t_dynarray_method_bad.v index e6d9e2aff..4a0d82e41 100644 --- a/test_regress/t/t_dynarray_method_bad.v +++ b/test_regress/t/t_dynarray_method_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_dynarray_multid.py b/test_regress/t/t_dynarray_multid.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_dynarray_multid.py +++ b/test_regress/t/t_dynarray_multid.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray_multid.v b/test_regress/t/t_dynarray_multid.v index e7c8de884..f364e399a 100644 --- a/test_regress/t/t_dynarray_multid.v +++ b/test_regress/t/t_dynarray_multid.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_dynarray_param.py b/test_regress/t/t_dynarray_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_dynarray_param.py +++ b/test_regress/t/t_dynarray_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray_param.v b/test_regress/t/t_dynarray_param.v index f35a5a3b4..ca6e61b18 100644 --- a/test_regress/t/t_dynarray_param.v +++ b/test_regress/t/t_dynarray_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Noam Gallmann. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Noam Gallmann // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_dynarray_unpacked.py b/test_regress/t/t_dynarray_unpacked.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_dynarray_unpacked.py +++ b/test_regress/t/t_dynarray_unpacked.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_dynarray_unpacked.v b/test_regress/t/t_dynarray_unpacked.v index e23e549dc..ace98e6cb 100644 --- a/test_regress/t/t_dynarray_unpacked.v +++ b/test_regress/t/t_dynarray_unpacked.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_embed1.py b/test_regress/t/t_embed1.py index ff5997985..6d6bc7cf3 100755 --- a/test_regress/t/t_embed1.py +++ b/test_regress/t/t_embed1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_embed1.v b/test_regress/t/t_embed1.v index 94039be73..fa8a69c5f 100644 --- a/test_regress/t/t_embed1.v +++ b/test_regress/t/t_embed1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_embed1_c.cpp b/test_regress/t/t_embed1_c.cpp index ed536c524..d04d5b375 100644 --- a/test_regress/t/t_embed1_c.cpp +++ b/test_regress/t/t_embed1_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2011-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2011-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_embed1_child.v b/test_regress/t/t_embed1_child.v index 1af251ffd..0e6be3315 100644 --- a/test_regress/t/t_embed1_child.v +++ b/test_regress/t/t_embed1_child.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_embed1_child (/*AUTOARG*/ diff --git a/test_regress/t/t_embed1_wrap.v b/test_regress/t/t_embed1_wrap.v index 27432fb5b..e3d5694ac 100644 --- a/test_regress/t/t_embed1_wrap.v +++ b/test_regress/t/t_embed1_wrap.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_embed1_wrap (/*AUTOARG*/ diff --git a/test_regress/t/t_emit_accessors.cpp b/test_regress/t/t_emit_accessors.cpp index 817ae59bf..f08d04324 100644 --- a/test_regress/t/t_emit_accessors.cpp +++ b/test_regress/t/t_emit_accessors.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_emit_accessors.py b/test_regress/t/t_emit_accessors.py index 6bb128038..73516a2f2 100755 --- a/test_regress/t/t_emit_accessors.py +++ b/test_regress/t/t_emit_accessors.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_emit_accessors.v b/test_regress/t/t_emit_accessors.v index d23055ede..d92bd4f1d 100644 --- a/test_regress/t/t_emit_accessors.v +++ b/test_regress/t/t_emit_accessors.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_emit_accessors( diff --git a/test_regress/t/t_emit_constw.py b/test_regress/t/t_emit_constw.py index 32620aed3..ce4ff87ca 100755 --- a/test_regress/t/t_emit_constw.py +++ b/test_regress/t/t_emit_constw.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_emit_constw.v b/test_regress/t/t_emit_constw.v index 5a22ffc91..0e9546b07 100644 --- a/test_regress/t/t_emit_constw.v +++ b/test_regress/t/t_emit_constw.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_emit_memb_limit.py b/test_regress/t/t_emit_memb_limit.py index a6d6ef4d1..9fdb63b30 100755 --- a/test_regress/t/t_emit_memb_limit.py +++ b/test_regress/t/t_emit_memb_limit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum.py b/test_regress/t/t_enum.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum.py +++ b/test_regress/t/t_enum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum.v b/test_regress/t/t_enum.v index 747a4500a..d942d033b 100644 --- a/test_regress/t/t_enum.v +++ b/test_regress/t/t_enum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef enum logic [4:0] diff --git a/test_regress/t/t_enum_bad_cell.py b/test_regress/t/t_enum_bad_cell.py index 84ba24c85..836d3abfe 100755 --- a/test_regress/t/t_enum_bad_cell.py +++ b/test_regress/t/t_enum_bad_cell.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_bad_cell.v b/test_regress/t/t_enum_bad_cell.v index d5470bf6a..64fdc48c5 100644 --- a/test_regress/t/t_enum_bad_cell.v +++ b/test_regress/t/t_enum_bad_cell.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_bad_circdecl.py b/test_regress/t/t_enum_bad_circdecl.py index 84ba24c85..836d3abfe 100755 --- a/test_regress/t/t_enum_bad_circdecl.py +++ b/test_regress/t/t_enum_bad_circdecl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_bad_circdecl.v b/test_regress/t/t_enum_bad_circdecl.v index 8599269a3..5dc9c1de3 100644 --- a/test_regress/t/t_enum_bad_circdecl.v +++ b/test_regress/t/t_enum_bad_circdecl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_bad_dup.py b/test_regress/t/t_enum_bad_dup.py index 84ba24c85..836d3abfe 100755 --- a/test_regress/t/t_enum_bad_dup.py +++ b/test_regress/t/t_enum_bad_dup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_bad_dup.v b/test_regress/t/t_enum_bad_dup.v index 94874b91d..6986303a3 100644 --- a/test_regress/t/t_enum_bad_dup.v +++ b/test_regress/t/t_enum_bad_dup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_bad_hide.py b/test_regress/t/t_enum_bad_hide.py index 84ba24c85..836d3abfe 100755 --- a/test_regress/t/t_enum_bad_hide.py +++ b/test_regress/t/t_enum_bad_hide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_bad_hide.v b/test_regress/t/t_enum_bad_hide.v index a234a212e..fbaf4775c 100644 --- a/test_regress/t/t_enum_bad_hide.v +++ b/test_regress/t/t_enum_bad_hide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef enum { HIDE_VALUE = 0 } hide_enum_t; diff --git a/test_regress/t/t_enum_bad_value.py b/test_regress/t/t_enum_bad_value.py index 176cdf75d..210912499 100755 --- a/test_regress/t/t_enum_bad_value.py +++ b/test_regress/t/t_enum_bad_value.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_bad_value.v b/test_regress/t/t_enum_bad_value.v index 3834b382d..a9d71a590 100644 --- a/test_regress/t/t_enum_bad_value.v +++ b/test_regress/t/t_enum_bad_value.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(); diff --git a/test_regress/t/t_enum_bad_wrap.py b/test_regress/t/t_enum_bad_wrap.py index 84ba24c85..836d3abfe 100755 --- a/test_regress/t/t_enum_bad_wrap.py +++ b/test_regress/t/t_enum_bad_wrap.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_bad_wrap.v b/test_regress/t/t_enum_bad_wrap.v index 9219f08e8..2b796c591 100644 --- a/test_regress/t/t_enum_bad_wrap.v +++ b/test_regress/t/t_enum_bad_wrap.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_base.py b/test_regress/t/t_enum_base.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_enum_base.py +++ b/test_regress/t/t_enum_base.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_base.v b/test_regress/t/t_enum_base.v index 74a811edf..4e30997d6 100644 --- a/test_regress/t/t_enum_base.v +++ b/test_regress/t/t_enum_base.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_base_bad.py b/test_regress/t/t_enum_base_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_enum_base_bad.py +++ b/test_regress/t/t_enum_base_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_base_bad.v b/test_regress/t/t_enum_base_bad.v index 309bae927..65405f9ee 100644 --- a/test_regress/t/t_enum_base_bad.v +++ b/test_regress/t/t_enum_base_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_const_methods.py b/test_regress/t/t_enum_const_methods.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_const_methods.py +++ b/test_regress/t/t_enum_const_methods.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_const_methods.v b/test_regress/t/t_enum_const_methods.v index 547a19a02..0e4ed8596 100644 --- a/test_regress/t/t_enum_const_methods.v +++ b/test_regress/t/t_enum_const_methods.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: constant enum methods // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Todd Strader +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Todd Strader // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_enum_enumvalue_struct_bad.py b/test_regress/t/t_enum_enumvalue_struct_bad.py index 069c1f01e..931a1ce7a 100755 --- a/test_regress/t/t_enum_enumvalue_struct_bad.py +++ b/test_regress/t/t_enum_enumvalue_struct_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_enumvalue_struct_bad.v b/test_regress/t/t_enum_enumvalue_struct_bad.v index 232f4fc32..418d999ed 100644 --- a/test_regress/t/t_enum_enumvalue_struct_bad.v +++ b/test_regress/t/t_enum_enumvalue_struct_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See issue #2855 diff --git a/test_regress/t/t_enum_func.py b/test_regress/t/t_enum_func.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_func.py +++ b/test_regress/t/t_enum_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_func.v b/test_regress/t/t_enum_func.v index 429c2a7bb..ec148b28d 100644 --- a/test_regress/t/t_enum_func.v +++ b/test_regress/t/t_enum_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef enum { EN_ZERO, diff --git a/test_regress/t/t_enum_huge_methods.py b/test_regress/t/t_enum_huge_methods.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_huge_methods.py +++ b/test_regress/t/t_enum_huge_methods.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_huge_methods.v b/test_regress/t/t_enum_huge_methods.v index 400836f87..db8e653dd 100644 --- a/test_regress/t/t_enum_huge_methods.v +++ b/test_regress/t/t_enum_huge_methods.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_enum_huge_methods_bad.py b/test_regress/t/t_enum_huge_methods_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_enum_huge_methods_bad.py +++ b/test_regress/t/t_enum_huge_methods_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_huge_methods_bad.v b/test_regress/t/t_enum_huge_methods_bad.v index 21bcc4fcc..3d3eba9a4 100644 --- a/test_regress/t/t_enum_huge_methods_bad.v +++ b/test_regress/t/t_enum_huge_methods_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_enum_int.py b/test_regress/t/t_enum_int.py index aff901aa6..8edf7f9f6 100755 --- a/test_regress/t/t_enum_int.py +++ b/test_regress/t/t_enum_int.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_int.v b/test_regress/t/t_enum_int.v index 368c6b64b..2048e7254 100644 --- a/test_regress/t/t_enum_int.v +++ b/test_regress/t/t_enum_int.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_enum_large_methods.py b/test_regress/t/t_enum_large_methods.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_large_methods.py +++ b/test_regress/t/t_enum_large_methods.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_large_methods.v b/test_regress/t/t_enum_large_methods.v index 4ab01f2c9..64a73ec09 100644 --- a/test_regress/t/t_enum_large_methods.v +++ b/test_regress/t/t_enum_large_methods.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_enum_name2.py b/test_regress/t/t_enum_name2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_name2.py +++ b/test_regress/t/t_enum_name2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_name2.v b/test_regress/t/t_enum_name2.v index 776692f30..e99bd993f 100644 --- a/test_regress/t/t_enum_name2.v +++ b/test_regress/t/t_enum_name2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Jonathon Donaldson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Jonathon Donaldson // SPDX-License-Identifier: CC0-1.0 package our_pkg; diff --git a/test_regress/t/t_enum_name3.py b/test_regress/t/t_enum_name3.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_name3.py +++ b/test_regress/t/t_enum_name3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_name3.v b/test_regress/t/t_enum_name3.v index 80b3ae0ba..ca0d2e0f0 100644 --- a/test_regress/t/t_enum_name3.v +++ b/test_regress/t/t_enum_name3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Jonathon Donaldson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Jonathon Donaldson // SPDX-License-Identifier: CC0-1.0 // bug855 diff --git a/test_regress/t/t_enum_name_sformatf.py b/test_regress/t/t_enum_name_sformatf.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_name_sformatf.py +++ b/test_regress/t/t_enum_name_sformatf.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_name_sformatf.v b/test_regress/t/t_enum_name_sformatf.v index f629d1896..345c0862f 100644 --- a/test_regress/t/t_enum_name_sformatf.v +++ b/test_regress/t/t_enum_name_sformatf.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub #(parameter int param_a, parameter bit [1:0] enum_param = '0) (); diff --git a/test_regress/t/t_enum_overlap_bad.py b/test_regress/t/t_enum_overlap_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_enum_overlap_bad.py +++ b/test_regress/t/t_enum_overlap_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_overlap_bad.v b/test_regress/t/t_enum_overlap_bad.v index 69bb89af3..d61197640 100644 --- a/test_regress/t/t_enum_overlap_bad.v +++ b/test_regress/t/t_enum_overlap_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_param_class.py b/test_regress/t/t_enum_param_class.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_param_class.py +++ b/test_regress/t/t_enum_param_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_param_class.v b/test_regress/t/t_enum_param_class.v index c59f4b523..d710a0d33 100644 --- a/test_regress/t/t_enum_param_class.v +++ b/test_regress/t/t_enum_param_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 /// (See bug4551) diff --git a/test_regress/t/t_enum_param_class2.py b/test_regress/t/t_enum_param_class2.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_enum_param_class2.py +++ b/test_regress/t/t_enum_param_class2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_param_class2.v b/test_regress/t/t_enum_param_class2.v index 2dc5f76fc..de63ba373 100644 --- a/test_regress/t/t_enum_param_class2.v +++ b/test_regress/t/t_enum_param_class2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_enum_public.cpp b/test_regress/t/t_enum_public.cpp index 8dd9f8931..05469a73a 100644 --- a/test_regress/t/t_enum_public.cpp +++ b/test_regress/t/t_enum_public.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_enum_public.py b/test_regress/t/t_enum_public.py index 0916bd913..f89e20642 100755 --- a/test_regress/t/t_enum_public.py +++ b/test_regress/t/t_enum_public.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_public.v b/test_regress/t/t_enum_public.v index cb3a1d24e..7552280cc 100644 --- a/test_regress/t/t_enum_public.v +++ b/test_regress/t/t_enum_public.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package p3; diff --git a/test_regress/t/t_enum_recurse_bad.py b/test_regress/t/t_enum_recurse_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_enum_recurse_bad.py +++ b/test_regress/t/t_enum_recurse_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_recurse_bad.v b/test_regress/t/t_enum_recurse_bad.v index d6a62f6de..face4266b 100644 --- a/test_regress/t/t_enum_recurse_bad.v +++ b/test_regress/t/t_enum_recurse_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 enum {u=u} e_t; diff --git a/test_regress/t/t_enum_recurse_bad2.py b/test_regress/t/t_enum_recurse_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_enum_recurse_bad2.py +++ b/test_regress/t/t_enum_recurse_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_recurse_bad2.v b/test_regress/t/t_enum_recurse_bad2.v index 449b05bfa..4953384d2 100644 --- a/test_regress/t/t_enum_recurse_bad2.v +++ b/test_regress/t/t_enum_recurse_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef enum foo_t; diff --git a/test_regress/t/t_enum_size.py b/test_regress/t/t_enum_size.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_size.py +++ b/test_regress/t/t_enum_size.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_size.v b/test_regress/t/t_enum_size.v index 6231c405e..fb32336cf 100644 --- a/test_regress/t/t_enum_size.v +++ b/test_regress/t/t_enum_size.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_type_bad.py b/test_regress/t/t_enum_type_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_enum_type_bad.py +++ b/test_regress/t/t_enum_type_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_type_bad.v b/test_regress/t/t_enum_type_bad.v index d46fb9d67..29e4f9c96 100644 --- a/test_regress/t/t_enum_type_bad.v +++ b/test_regress/t/t_enum_type_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_type_methods.py b/test_regress/t/t_enum_type_methods.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_type_methods.py +++ b/test_regress/t/t_enum_type_methods.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_type_methods.v b/test_regress/t/t_enum_type_methods.v index 795aa8b92..40d21298c 100644 --- a/test_regress/t/t_enum_type_methods.v +++ b/test_regress/t/t_enum_type_methods.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_enum_type_methods_bad.py b/test_regress/t/t_enum_type_methods_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_enum_type_methods_bad.py +++ b/test_regress/t/t_enum_type_methods_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_type_methods_bad.v b/test_regress/t/t_enum_type_methods_bad.v index 3b0066db1..e365800df 100644 --- a/test_regress/t/t_enum_type_methods_bad.v +++ b/test_regress/t/t_enum_type_methods_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_enum_type_nomethod_bad.py b/test_regress/t/t_enum_type_nomethod_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_enum_type_nomethod_bad.py +++ b/test_regress/t/t_enum_type_nomethod_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_type_nomethod_bad.v b/test_regress/t/t_enum_type_nomethod_bad.v index 03bfa8e46..15232b5d1 100644 --- a/test_regress/t/t_enum_type_nomethod_bad.v +++ b/test_regress/t/t_enum_type_nomethod_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_type_pins.py b/test_regress/t/t_enum_type_pins.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_type_pins.py +++ b/test_regress/t/t_enum_type_pins.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_type_pins.v b/test_regress/t/t_enum_type_pins.v index a7f2b899a..d8ee48e4c 100644 --- a/test_regress/t/t_enum_type_pins.v +++ b/test_regress/t/t_enum_type_pins.v @@ -2,8 +2,8 @@ // // This code exercises the various enumeration methods // -// This file ONLY is placed into the Public Domain, for any use, without -// warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. diff --git a/test_regress/t/t_enum_value_assign.py b/test_regress/t/t_enum_value_assign.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enum_value_assign.py +++ b/test_regress/t/t_enum_value_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_value_assign.v b/test_regress/t/t_enum_value_assign.v index ff936d35a..fa71fd4f4 100644 --- a/test_regress/t/t_enum_value_assign.v +++ b/test_regress/t/t_enum_value_assign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enum_x_bad.py b/test_regress/t/t_enum_x_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_enum_x_bad.py +++ b/test_regress/t/t_enum_x_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enum_x_bad.v b/test_regress/t/t_enum_x_bad.v index 6e2d59774..b3fdaca91 100644 --- a/test_regress/t/t_enum_x_bad.v +++ b/test_regress/t/t_enum_x_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_enumeration.py b/test_regress/t/t_enumeration.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_enumeration.py +++ b/test_regress/t/t_enumeration.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_enumeration.v b/test_regress/t/t_enumeration.v index e8f5a5585..9af1c18eb 100644 --- a/test_regress/t/t_enumeration.v +++ b/test_regress/t/t_enumeration.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_eq_wild.py b/test_regress/t/t_eq_wild.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_eq_wild.py +++ b/test_regress/t/t_eq_wild.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_eq_wild.v b/test_regress/t/t_eq_wild.v index 891945d24..3a5f53a10 100644 --- a/test_regress/t/t_eq_wild.v +++ b/test_regress/t/t_eq_wild.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 function bit get_1_or_0(bit get_1); diff --git a/test_regress/t/t_eq_wild_unsup.py b/test_regress/t/t_eq_wild_unsup.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_eq_wild_unsup.py +++ b/test_regress/t/t_eq_wild_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_eq_wild_unsup.v b/test_regress/t/t_eq_wild_unsup.v index 9e7f8b7c6..8530cac45 100644 --- a/test_regress/t/t_eq_wild_unsup.v +++ b/test_regress/t/t_eq_wild_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 function logic get_x_or_0(logic get_x); diff --git a/test_regress/t/t_event.py b/test_regress/t/t_event.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_event.py +++ b/test_regress/t/t_event.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event.v b/test_regress/t/t_event.v index 4a0e98da6..d434ee958 100644 --- a/test_regress/t/t_event.v +++ b/test_regress/t/t_event.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE diff --git a/test_regress/t/t_event_array_fire.py b/test_regress/t/t_event_array_fire.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_event_array_fire.py +++ b/test_regress/t/t_event_array_fire.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_array_fire.v b/test_regress/t/t_event_array_fire.v index 09e2eedec..bd7991859 100644 --- a/test_regress/t/t_event_array_fire.v +++ b/test_regress/t/t_event_array_fire.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_event_class_fire.py b/test_regress/t/t_event_class_fire.py index 9de681711..331309e57 100755 --- a/test_regress/t/t_event_class_fire.py +++ b/test_regress/t/t_event_class_fire.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_class_fire.v b/test_regress/t/t_event_class_fire.v index 325fbafc0..8a7408b5f 100644 --- a/test_regress/t/t_event_class_fire.v +++ b/test_regress/t/t_event_class_fire.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_event_control.py b/test_regress/t/t_event_control.py index 330e93cb7..e568204b2 100755 --- a/test_regress/t/t_event_control.py +++ b/test_regress/t/t_event_control.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control.v b/test_regress/t/t_event_control.v index 447c189f2..806d00b62 100644 --- a/test_regress/t/t_event_control.v +++ b/test_regress/t/t_event_control.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_event_control_assign.py b/test_regress/t/t_event_control_assign.py index 913d8d7fd..4c4a6c85d 100755 --- a/test_regress/t/t_event_control_assign.py +++ b/test_regress/t/t_event_control_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_assign.v b/test_regress/t/t_event_control_assign.v index 980bd9ef8..1142d7eec 100644 --- a/test_regress/t/t_event_control_assign.v +++ b/test_regress/t/t_event_control_assign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules.py b/test_regress/t/t_event_control_double_excessive.py similarity index 53% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules.py rename to test_regress/t/t_event_control_double_excessive.py index c6e56559a..6fe7d000c 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules.py +++ b/test_regress/t/t_event_control_double_excessive.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_double_excessive.v b/test_regress/t/t_event_control_double_excessive.v new file mode 100644 index 000000000..c1e571e69 --- /dev/null +++ b/test_regress/t/t_event_control_double_excessive.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module x; + event a; + int counter = 0; + + initial begin + fork + begin + @a; + ->a; + @a; + counter++; + end + join_none + #1; + ->a; + end + always begin + @a; + ->a; + @a; + counter++; + end + final begin + if (counter != 1) $stop; + $write("*-* All Finished *-*\n"); + end +endmodule diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.py b/test_regress/t/t_event_control_double_lost.py similarity index 53% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.py rename to test_regress/t/t_event_control_double_lost.py index c6e56559a..6fe7d000c 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.py +++ b/test_regress/t/t_event_control_double_lost.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_double_lost.v b/test_regress/t/t_event_control_double_lost.v new file mode 100644 index 000000000..b27289784 --- /dev/null +++ b/test_regress/t/t_event_control_double_lost.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module x; + event a; + event b; + + bit ok = 0; + + task do_the_job(); + static bit first = 1; + if (first) begin + first = 0; + @a; + ok = 1; + end + else begin + ->a; + end + endtask + + initial begin + #1 ->b; + #100; + if (!ok) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + always @b do_the_job(); + always @b do_the_job(); +endmodule diff --git a/test_regress/t/t_event_control_expr.py b/test_regress/t/t_event_control_expr.py index ad96efae9..9ae6ac710 100755 --- a/test_regress/t/t_event_control_expr.py +++ b/test_regress/t/t_event_control_expr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_expr.v b/test_regress/t/t_event_control_expr.v index de3562a6a..76dc78392 100644 --- a/test_regress/t/t_event_control_expr.v +++ b/test_regress/t/t_event_control_expr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE diff --git a/test_regress/t/t_event_control_expr_noinl.py b/test_regress/t/t_event_control_expr_noinl.py index c96b715f6..cae1d7b22 100755 --- a/test_regress/t/t_event_control_expr_noinl.py +++ b/test_regress/t/t_event_control_expr_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_expr_unsup.py b/test_regress/t/t_event_control_expr_unsup.py index 685bf2355..33e555b41 100755 --- a/test_regress/t/t_event_control_expr_unsup.py +++ b/test_regress/t/t_event_control_expr_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_expr_unsup.v b/test_regress/t/t_event_control_expr_unsup.v index 7a89dfa30..4cce91b43 100644 --- a/test_regress/t/t_event_control_expr_unsup.v +++ b/test_regress/t/t_event_control_expr_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_event_control_pass.py b/test_regress/t/t_event_control_pass.py index 263880576..e959f91ea 100755 --- a/test_regress/t/t_event_control_pass.py +++ b/test_regress/t/t_event_control_pass.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_pass.v b/test_regress/t/t_event_control_pass.v index 5304a829b..1426a817e 100644 --- a/test_regress/t/t_event_control_pass.v +++ b/test_regress/t/t_event_control_pass.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Bar; diff --git a/test_regress/t/t_event_control_prev_name_collision.py b/test_regress/t/t_event_control_prev_name_collision.py index 54de0aad4..5d6840eb6 100755 --- a/test_regress/t/t_event_control_prev_name_collision.py +++ b/test_regress/t/t_event_control_prev_name_collision.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_prev_name_collision.v b/test_regress/t/t_event_control_prev_name_collision.v index ef9a9c660..58c6fefd0 100644 --- a/test_regress/t/t_event_control_prev_name_collision.v +++ b/test_regress/t/t_event_control_prev_name_collision.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module S( input reset, diff --git a/test_regress/t/t_event_control_scope_var.py b/test_regress/t/t_event_control_scope_var.py index e1fb39066..9f40badfa 100755 --- a/test_regress/t/t_event_control_scope_var.py +++ b/test_regress/t/t_event_control_scope_var.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_scope_var.v b/test_regress/t/t_event_control_scope_var.v index a83c8577e..66482fc3e 100644 --- a/test_regress/t/t_event_control_scope_var.v +++ b/test_regress/t/t_event_control_scope_var.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module test_mod(input reg clk, input reg reset, output integer result); diff --git a/test_regress/t/t_event_control_star.py b/test_regress/t/t_event_control_star.py index 07fc79e8e..3160d0589 100755 --- a/test_regress/t/t_event_control_star.py +++ b/test_regress/t/t_event_control_star.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_star.v b/test_regress/t/t_event_control_star.v index 7df4ae1d0..9b2579c8f 100644 --- a/test_regress/t/t_event_control_star.v +++ b/test_regress/t/t_event_control_star.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 Wilson Snyder. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Based on ivtest's nested_impl_event1.v by Martin Whitaker. diff --git a/test_regress/t/t_event_control_star_never.py b/test_regress/t/t_event_control_star_never.py index 3c530ac0d..17c73b581 100755 --- a/test_regress/t/t_event_control_star_never.py +++ b/test_regress/t/t_event_control_star_never.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_star_never.v b/test_regress/t/t_event_control_star_never.v index e0e62bf94..5f6a5c373 100644 --- a/test_regress/t/t_event_control_star_never.v +++ b/test_regress/t/t_event_control_star_never.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_event_control_star_never_bad.py b/test_regress/t/t_event_control_star_never_bad.py index 085ddf831..5c51906b1 100755 --- a/test_regress/t/t_event_control_star_never_bad.py +++ b/test_regress/t/t_event_control_star_never_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_control_timing.py b/test_regress/t/t_event_control_timing.py index dc5a3dbd2..1d941c9e1 100755 --- a/test_regress/t/t_event_control_timing.py +++ b/test_regress/t/t_event_control_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_copy.py b/test_regress/t/t_event_copy.py index a61e23c88..9c02d8bbc 100755 --- a/test_regress/t/t_event_copy.py +++ b/test_regress/t/t_event_copy.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_copy.v b/test_regress/t/t_event_copy.v index 30794a97a..208af79ff 100644 --- a/test_regress/t/t_event_copy.v +++ b/test_regress/t/t_event_copy.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE diff --git a/test_regress/t/t_event_method_bad.py b/test_regress/t/t_event_method_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_event_method_bad.py +++ b/test_regress/t/t_event_method_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_event_method_bad.v b/test_regress/t/t_event_method_bad.v index d3ae6b4d1..1cfbc7126 100644 --- a/test_regress/t/t_event_method_bad.v +++ b/test_regress/t/t_event_method_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_exit.py b/test_regress/t/t_exit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_exit.py +++ b/test_regress/t/t_exit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_exit.v b/test_regress/t/t_exit.v index 1533bb9b0..fb98d19a1 100644 --- a/test_regress/t/t_exit.v +++ b/test_regress/t/t_exit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Wilson Snyder. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 program t; diff --git a/test_regress/t/t_expect.py b/test_regress/t/t_expect.py index 7e5bcdfe5..b5718946c 100755 --- a/test_regress/t/t_expect.py +++ b/test_regress/t/t_expect.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_expect.v b/test_regress/t/t_expect.v index e51b22eaf..fd81ca4fe 100644 --- a/test_regress/t/t_expect.v +++ b/test_regress/t/t_expect.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_export_packed_struct.cpp b/test_regress/t/t_export_packed_struct.cpp index 552427106..0501b1f68 100644 --- a/test_regress/t/t_export_packed_struct.cpp +++ b/test_regress/t/t_export_packed_struct.cpp @@ -2,10 +2,10 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Kefa Chen. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Kefa Chen // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* diff --git a/test_regress/t/t_export_packed_struct.py b/test_regress/t/t_export_packed_struct.py index a08f8ed86..f975b0638 100755 --- a/test_regress/t/t_export_packed_struct.py +++ b/test_regress/t/t_export_packed_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_export_packed_struct.v b/test_regress/t/t_export_packed_struct.v index a96f92213..186ecd6cd 100644 --- a/test_regress/t/t_export_packed_struct.v +++ b/test_regress/t/t_export_packed_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Kefa Chen. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Kefa Chen // SPDX-License-Identifier: CC0-1.0 typedef logic [5:0] udata6_t; diff --git a/test_regress/t/t_export_packed_struct2.cpp b/test_regress/t/t_export_packed_struct2.cpp index c97e39392..94c6a3840 100644 --- a/test_regress/t/t_export_packed_struct2.cpp +++ b/test_regress/t/t_export_packed_struct2.cpp @@ -2,10 +2,10 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Kefa Chen. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Kefa Chen // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* diff --git a/test_regress/t/t_export_packed_struct2.py b/test_regress/t/t_export_packed_struct2.py index 9d1dcec8d..1864fa13a 100755 --- a/test_regress/t/t_export_packed_struct2.py +++ b/test_regress/t/t_export_packed_struct2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_export_packed_struct2.v b/test_regress/t/t_export_packed_struct2.v index 5a67b0842..6cfb37482 100644 --- a/test_regress/t/t_export_packed_struct2.v +++ b/test_regress/t/t_export_packed_struct2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Kefa Chen. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Kefa Chen // SPDX-License-Identifier: CC0-1.0 // Packed struct in package diff --git a/test_regress/t/t_expr_incr_unsup.py b/test_regress/t/t_expr_incr_unsup.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_expr_incr_unsup.py +++ b/test_regress/t/t_expr_incr_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_expr_incr_unsup.v b/test_regress/t/t_expr_incr_unsup.v index 9d6647cbf..0e48015f0 100644 --- a/test_regress/t/t_expr_incr_unsup.v +++ b/test_regress/t/t_expr_incr_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 Krzysztof Boronski. +// SPDX-FileCopyrightText: 2022 Krzysztof Boronski // SPDX-License-Identifier: CC0-1.0 int i = 0; @@ -12,7 +12,7 @@ endfunction module t; initial begin - int arr [1:0] = {0, 0}; + automatic int arr [1:0] = {0, 0}; i = 0; $display("Value: %d", arr[postincrement_i()]++); end diff --git a/test_regress/t/t_expr_shortcircuit.py b/test_regress/t/t_expr_shortcircuit.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_expr_shortcircuit.py +++ b/test_regress/t/t_expr_shortcircuit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_expr_shortcircuit.v b/test_regress/t/t_expr_shortcircuit.v index 61b175d55..3667152c3 100644 --- a/test_regress/t/t_expr_shortcircuit.v +++ b/test_regress/t/t_expr_shortcircuit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_exprstmt_on_lhs_of_nba.py b/test_regress/t/t_exprstmt_on_lhs_of_nba.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_exprstmt_on_lhs_of_nba.py +++ b/test_regress/t/t_exprstmt_on_lhs_of_nba.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_exprstmt_on_lhs_of_nba.v b/test_regress/t/t_exprstmt_on_lhs_of_nba.v index e9c7efb4e..41b76412f 100644 --- a/test_regress/t/t_exprstmt_on_lhs_of_nba.v +++ b/test_regress/t/t_exprstmt_on_lhs_of_nba.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_extend.py b/test_regress/t/t_extend.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_extend.py +++ b/test_regress/t/t_extend.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_extend.v b/test_regress/t/t_extend.v index 78cd9ede5..b0a9f7d75 100644 --- a/test_regress/t/t_extend.v +++ b/test_regress/t/t_extend.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_extend_c_class.py b/test_regress/t/t_extend_c_class.py index 56d3b8278..35c36ccca 100755 --- a/test_regress/t/t_extend_c_class.py +++ b/test_regress/t/t_extend_c_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_extend_c_class.v b/test_regress/t/t_extend_c_class.v index f564d06c3..265f835a6 100644 --- a/test_regress/t/t_extend_c_class.v +++ b/test_regress/t/t_extend_c_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_extend_c_class_c.h b/test_regress/t/t_extend_c_class_c.h index 6a4996916..b2bc0fd9d 100644 --- a/test_regress/t/t_extend_c_class_c.h +++ b/test_regress/t/t_extend_c_class_c.h @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006-2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006-2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class t_extend_c_class_c { diff --git a/test_regress/t/t_extend_class.py b/test_regress/t/t_extend_class.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_extend_class.py +++ b/test_regress/t/t_extend_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_extend_class.v b/test_regress/t/t_extend_class.v index dba989d06..af9d48f7b 100644 --- a/test_regress/t/t_extend_class.v +++ b/test_regress/t/t_extend_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Although strange, Verilog defines are expanded inside the C blocks diff --git a/test_regress/t/t_extract_static_const.py b/test_regress/t/t_extract_static_const.py index c48009a42..307854e91 100755 --- a/test_regress/t/t_extract_static_const.py +++ b/test_regress/t/t_extract_static_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_extract_static_const.v b/test_regress/t/t_extract_static_const.v index d04d2571f..c14d6a529 100644 --- a/test_regress/t/t_extract_static_const.v +++ b/test_regress/t/t_extract_static_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_extract_static_const_multimodule.py b/test_regress/t/t_extract_static_const_multimodule.py index c48009a42..307854e91 100755 --- a/test_regress/t/t_extract_static_const_multimodule.py +++ b/test_regress/t/t_extract_static_const_multimodule.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_extract_static_const_multimodule.v b/test_regress/t/t_extract_static_const_multimodule.v index 227fdcf1c..74ffc6d76 100644 --- a/test_regress/t/t_extract_static_const_multimodule.v +++ b/test_regress/t/t_extract_static_const_multimodule.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_extract_static_const_no_merge.py b/test_regress/t/t_extract_static_const_no_merge.py index 354d90d19..09f698726 100755 --- a/test_regress/t/t_extract_static_const_no_merge.py +++ b/test_regress/t/t_extract_static_const_no_merge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fallback_bad.py b/test_regress/t/t_fallback_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_fallback_bad.py +++ b/test_regress/t/t_fallback_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fallback_bad.v b/test_regress/t/t_fallback_bad.v index 6722238a7..f1215747e 100644 --- a/test_regress/t/t_fallback_bad.v +++ b/test_regress/t/t_fallback_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 int f = 5; diff --git a/test_regress/t/t_final.py b/test_regress/t/t_final.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_final.py +++ b/test_regress/t/t_final.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_final.v b/test_regress/t/t_final.v index 8d29e3e38..1a3156f4c 100644 --- a/test_regress/t/t_final.v +++ b/test_regress/t/t_final.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Charlie Brej. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Charlie Brej // SPDX-License-Identifier: CC0-1.0 module submodule (); diff --git a/test_regress/t/t_flag_aslr.py b/test_regress/t/t_flag_aslr.py index eb91ad9bc..d973c0dce 100755 --- a/test_regress/t/t_flag_aslr.py +++ b/test_regress/t/t_flag_aslr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_aslr_no.py b/test_regress/t/t_flag_aslr_no.py index 9e3e11aa1..e894e6f10 100755 --- a/test_regress/t/t_flag_aslr_no.py +++ b/test_regress/t/t_flag_aslr_no.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_bboxsys.py b/test_regress/t/t_flag_bboxsys.py index 9cdbf53a8..323bbdf34 100755 --- a/test_regress/t/t_flag_bboxsys.py +++ b/test_regress/t/t_flag_bboxsys.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_bboxsys.v b/test_regress/t/t_flag_bboxsys.v index 6dd8770e6..597eb4620 100644 --- a/test_regress/t/t_flag_bboxsys.v +++ b/test_regress/t/t_flag_bboxsys.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_binary.py b/test_regress/t/t_flag_binary.py index 3aca74af7..4ad27bef9 100755 --- a/test_regress/t/t_flag_binary.py +++ b/test_regress/t/t_flag_binary.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_binary_parallel.py b/test_regress/t/t_flag_binary_parallel.py index 3d881a0f1..68b8ea50c 100755 --- a/test_regress/t/t_flag_binary_parallel.py +++ b/test_regress/t/t_flag_binary_parallel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_build.py b/test_regress/t/t_flag_build.py index 6eff8cf80..59ded9803 100755 --- a/test_regress/t/t_flag_build.py +++ b/test_regress/t/t_flag_build.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_build_bad.py b/test_regress/t/t_flag_build_bad.py index 5bfed0801..98ab31dd7 100755 --- a/test_regress/t/t_flag_build_bad.py +++ b/test_regress/t/t_flag_build_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -15,10 +15,6 @@ test.compile(verilator_flags2=["--build --make gmake"], fails=True, expect_filename=test.golden_filename) -test.compile(verilator_flags2=["--build --make cmake -Wno-fatal"], - fails=True, - expect_filename="t/t_flag_build_bad_cmake.out") - test.compile(verilator_flags2=["--build --make json"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_flag_build_bad2.py b/test_regress/t/t_flag_build_bad2.py index b6404b8c7..6a07db640 100755 --- a/test_regress/t/t_flag_build_bad2.py +++ b/test_regress/t/t_flag_build_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_build_bad_cmake.out b/test_regress/t/t_flag_build_bad_cmake.out deleted file mode 100644 index 690010506..000000000 --- a/test_regress/t/t_flag_build_bad_cmake.out +++ /dev/null @@ -1,6 +0,0 @@ -%Warning-DEPRECATED: Option '--make cmake' is deprecated, use '--make json' instead - ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest - ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. -%Error: --make cannot be used together with --build. Suggest see manual - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: Exiting due to diff --git a/test_regress/t/t_flag_build_dep_bin.py b/test_regress/t/t_flag_build_dep_bin.py index fc4874e71..2f6a082b2 100755 --- a/test_regress/t/t_flag_build_dep_bin.py +++ b/test_regress/t/t_flag_build_dep_bin.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_build_dep_bin.v b/test_regress/t/t_flag_build_dep_bin.v index f6668377e..955d23308 100644 --- a/test_regress/t/t_flag_build_dep_bin.v +++ b/test_regress/t/t_flag_build_dep_bin.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_build_jobs_and_j.py b/test_regress/t/t_flag_build_jobs_and_j.py index bdc9b5ee9..50dcf2856 100755 --- a/test_regress/t/t_flag_build_jobs_and_j.py +++ b/test_regress/t/t_flag_build_jobs_and_j.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_build_jobs_bad.py b/test_regress/t/t_flag_build_jobs_bad.py index 8cb6ddd51..3135e3cbc 100755 --- a/test_regress/t/t_flag_build_jobs_bad.py +++ b/test_regress/t/t_flag_build_jobs_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_comp_limit_parens.py b/test_regress/t/t_flag_comp_limit_parens.py index bce8d15bc..d20f3ea69 100755 --- a/test_regress/t/t_flag_comp_limit_parens.py +++ b/test_regress/t/t_flag_comp_limit_parens.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_comp_limit_parens.v b/test_regress/t/t_flag_comp_limit_parens.v index bda8c841f..0f31e5f5d 100644 --- a/test_regress/t/t_flag_comp_limit_parens.v +++ b/test_regress/t/t_flag_comp_limit_parens.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_flag_compiler.v b/test_regress/t/t_flag_compiler.v index 826dc2ddd..32ed50ef4 100644 --- a/test_regress/t/t_flag_compiler.v +++ b/test_regress/t/t_flag_compiler.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_flag_compiler_bad.py b/test_regress/t/t_flag_compiler_bad.py index bd99f7973..08ff23c8a 100755 --- a/test_regress/t/t_flag_compiler_bad.py +++ b/test_regress/t/t_flag_compiler_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_compiler_clang.py b/test_regress/t/t_flag_compiler_clang.py index b3f8bb752..f7fc1d3e5 100755 --- a/test_regress/t/t_flag_compiler_clang.py +++ b/test_regress/t/t_flag_compiler_clang.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_compiler_gcc.py b/test_regress/t/t_flag_compiler_gcc.py index e868fd2f5..a822f1ba6 100755 --- a/test_regress/t/t_flag_compiler_gcc.py +++ b/test_regress/t/t_flag_compiler_gcc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_compiler_msvc.py b/test_regress/t/t_flag_compiler_msvc.py index 33ce62dd2..2898ff581 100755 --- a/test_regress/t/t_flag_compiler_msvc.py +++ b/test_regress/t/t_flag_compiler_msvc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_context_bad.py b/test_regress/t/t_flag_context_bad.py index b5c4b0655..4b079dd7c 100755 --- a/test_regress/t/t_flag_context_bad.py +++ b/test_regress/t/t_flag_context_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_context_bad.v b/test_regress/t/t_flag_context_bad.v index 89bcf330b..f9c43b66c 100644 --- a/test_regress/t/t_flag_context_bad.v +++ b/test_regress/t/t_flag_context_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_csplit.py b/test_regress/t/t_flag_csplit.py index 11a0ae93c..77b68dfd8 100755 --- a/test_regress/t/t_flag_csplit.py +++ b/test_regress/t/t_flag_csplit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_csplit.v b/test_regress/t/t_flag_csplit.v index 15182c347..8c287d5e9 100644 --- a/test_regress/t/t_flag_csplit.v +++ b/test_regress/t/t_flag_csplit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_flag_csplit_eval.py b/test_regress/t/t_flag_csplit_eval.py index 51756660b..1b88de3bb 100755 --- a/test_regress/t/t_flag_csplit_eval.py +++ b/test_regress/t/t_flag_csplit_eval.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_csplit_eval.v b/test_regress/t/t_flag_csplit_eval.v index 53c7976d9..ee9fd8d63 100644 --- a/test_regress/t/t_flag_csplit_eval.v +++ b/test_regress/t/t_flag_csplit_eval.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_flag_csplit_groups.py b/test_regress/t/t_flag_csplit_groups.py index 1530bf537..6e15ff128 100755 --- a/test_regress/t/t_flag_csplit_groups.py +++ b/test_regress/t/t_flag_csplit_groups.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -125,7 +125,7 @@ test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_clas test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_2") # Check combine count -test.file_grep(test.stats, r'Node count, CFILE + (\d+)', (272 if test.vltmt else 255)) +test.file_grep(test.stats, r'Node count, CFILE + (\d+)', (275 if test.vltmt else 258)) test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_FAST + (\d+)', 2) test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_SLOW + (\d+)', 2) diff --git a/test_regress/t/t_flag_csplit_off.py b/test_regress/t/t_flag_csplit_off.py index e42f5a725..b298d4700 100755 --- a/test_regress/t/t_flag_csplit_off.py +++ b/test_regress/t/t_flag_csplit_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_debug_noleak.py b/test_regress/t/t_flag_debug_noleak.py index effa05d68..00826f34d 100755 --- a/test_regress/t/t_flag_debug_noleak.py +++ b/test_regress/t/t_flag_debug_noleak.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_debug_noleak.v b/test_regress/t/t_flag_debug_noleak.v index 207a1d8d6..57d264ae8 100644 --- a/test_regress/t/t_flag_debug_noleak.v +++ b/test_regress/t/t_flag_debug_noleak.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_debugi9.py b/test_regress/t/t_flag_debugi9.py index c0da0071a..ca2cf5ca4 100755 --- a/test_regress/t/t_flag_debugi9.py +++ b/test_regress/t/t_flag_debugi9.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_debugi9.v b/test_regress/t/t_flag_debugi9.v index dcff6d1ff..be2eecd40 100644 --- a/test_regress/t/t_flag_debugi9.v +++ b/test_regress/t/t_flag_debugi9.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_flag_decoration.py b/test_regress/t/t_flag_decoration.py index 55807f346..d35d20972 100755 --- a/test_regress/t/t_flag_decoration.py +++ b/test_regress/t/t_flag_decoration.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_decoration.v b/test_regress/t/t_flag_decoration.v index 260106e4d..61aa9831a 100644 --- a/test_regress/t/t_flag_decoration.v +++ b/test_regress/t/t_flag_decoration.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_decoration_no.py b/test_regress/t/t_flag_decoration_no.py index af6c9f21b..b183d6dd6 100755 --- a/test_regress/t/t_flag_decoration_no.py +++ b/test_regress/t/t_flag_decoration_no.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_decorations_bad.py b/test_regress/t/t_flag_decorations_bad.py index 081a6cc01..428532d2f 100755 --- a/test_regress/t/t_flag_decorations_bad.py +++ b/test_regress/t/t_flag_decorations_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_decorations_node.py b/test_regress/t/t_flag_decorations_node.py index a3f6e7efe..22ca76502 100755 --- a/test_regress/t/t_flag_decorations_node.py +++ b/test_regress/t/t_flag_decorations_node.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_define.py b/test_regress/t/t_flag_define.py index 4bf777524..d444bb3fb 100755 --- a/test_regress/t/t_flag_define.py +++ b/test_regress/t/t_flag_define.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_define.v b/test_regress/t/t_flag_define.v index 1c1073eb4..bce17d483 100644 --- a/test_regress/t/t_flag_define.v +++ b/test_regress/t/t_flag_define.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // Special cases of "string parameters" : diff --git a/test_regress/t/t_flag_deprecated_bad.py b/test_regress/t/t_flag_deprecated_bad.py index 6cc83104f..8b192c851 100755 --- a/test_regress/t/t_flag_deprecated_bad.py +++ b/test_regress/t/t_flag_deprecated_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_deprecated_bad.v b/test_regress/t/t_flag_deprecated_bad.v index b102cb1b8..eb1adc426 100644 --- a/test_regress/t/t_flag_deprecated_bad.v +++ b/test_regress/t/t_flag_deprecated_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_errorlimit_bad.py b/test_regress/t/t_flag_errorlimit_bad.py index 41ee4fce1..bec542629 100755 --- a/test_regress/t/t_flag_errorlimit_bad.py +++ b/test_regress/t/t_flag_errorlimit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_errorlimit_bad.v b/test_regress/t/t_flag_errorlimit_bad.v index 1b792181f..55743c03a 100644 --- a/test_regress/t/t_flag_errorlimit_bad.v +++ b/test_regress/t/t_flag_errorlimit_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_expand_limit.py b/test_regress/t/t_flag_expand_limit.py index 4e3ca445a..8cacdb1ca 100755 --- a/test_regress/t/t_flag_expand_limit.py +++ b/test_regress/t/t_flag_expand_limit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_expand_limit.v b/test_regress/t/t_flag_expand_limit.v index 5e608ea2f..2ea408fec 100644 --- a/test_regress/t/t_flag_expand_limit.v +++ b/test_regress/t/t_flag_expand_limit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // issue3005 diff --git a/test_regress/t/t_flag_f.py b/test_regress/t/t_flag_f.py index 340eb7020..0fbab425f 100755 --- a/test_regress/t/t_flag_f.py +++ b/test_regress/t/t_flag_f.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_f.v b/test_regress/t/t_flag_f.v index e5ec47252..40f3d06ec 100644 --- a/test_regress/t/t_flag_f.v +++ b/test_regress/t/t_flag_f.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "t_flag_f_tsub_inc.v" diff --git a/test_regress/t/t_flag_f__3.v b/test_regress/t/t_flag_f__3.v index ccbf69772..7c46c9f4d 100644 --- a/test_regress/t/t_flag_f__3.v +++ b/test_regress/t/t_flag_f__3.v @@ -1 +1,4 @@ +// SPDX-FileCopyrightText: 2009 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + `define GOT_DEF3 1 diff --git a/test_regress/t/t_flag_f_bad.py b/test_regress/t/t_flag_f_bad.py index 3112b79ad..0e1f97341 100755 --- a/test_regress/t/t_flag_f_bad.py +++ b/test_regress/t/t_flag_f_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_f_bad_cmt.py b/test_regress/t/t_flag_f_bad_cmt.py index 19aee7a96..532953a8b 100755 --- a/test_regress/t/t_flag_f_bad_cmt.py +++ b/test_regress/t/t_flag_f_bad_cmt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_f_bad_cmt.v b/test_regress/t/t_flag_f_bad_cmt.v index e5ec47252..40f3d06ec 100644 --- a/test_regress/t/t_flag_f_bad_cmt.v +++ b/test_regress/t/t_flag_f_bad_cmt.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "t_flag_f_tsub_inc.v" diff --git a/test_regress/t/t_flag_f_bad_getenvend.py b/test_regress/t/t_flag_f_bad_getenvend.py index 24c6b121c..7c8fc08c8 100755 --- a/test_regress/t/t_flag_f_bad_getenvend.py +++ b/test_regress/t/t_flag_f_bad_getenvend.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_fi.cpp b/test_regress/t/t_flag_fi.cpp index 8ff1ba655..53d3b89dd 100644 --- a/test_regress/t/t_flag_fi.cpp +++ b/test_regress/t/t_flag_fi.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_flag_fi.py b/test_regress/t/t_flag_fi.py index 8bc5976ef..b0c829c5a 100755 --- a/test_regress/t/t_flag_fi.py +++ b/test_regress/t/t_flag_fi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_fi.v b/test_regress/t/t_flag_fi.v index bc826453a..28de5623e 100644 --- a/test_regress/t/t_flag_fi.v +++ b/test_regress/t/t_flag_fi.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_flag_fi_h.h b/test_regress/t/t_flag_fi_h.h index b104399bd..879e68608 100644 --- a/test_regress/t/t_flag_fi_h.h +++ b/test_regress/t/t_flag_fi_h.h @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_flag_future.py b/test_regress/t/t_flag_future.py index 68aa7e65a..e79af891f 100755 --- a/test_regress/t/t_flag_future.py +++ b/test_regress/t/t_flag_future.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_future.v b/test_regress/t/t_flag_future.v index ced0789ef..ea1f04dd1 100644 --- a/test_regress/t/t_flag_future.v +++ b/test_regress/t/t_flag_future.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_future_bad.py b/test_regress/t/t_flag_future_bad.py index 761b8b708..061d96ad9 100755 --- a/test_regress/t/t_flag_future_bad.py +++ b/test_regress/t/t_flag_future_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_generate_key.py b/test_regress/t/t_flag_generate_key.py index 4565feae4..f2ff1df35 100755 --- a/test_regress/t/t_flag_generate_key.py +++ b/test_regress/t/t_flag_generate_key.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_getenv.py b/test_regress/t/t_flag_getenv.py index 7410af807..a6344e4f5 100755 --- a/test_regress/t/t_flag_getenv.py +++ b/test_regress/t/t_flag_getenv.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_getenv.v b/test_regress/t/t_flag_getenv.v index 5a0ce9330..7153d78d2 100644 --- a/test_regress/t/t_flag_getenv.v +++ b/test_regress/t/t_flag_getenv.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define EMPTY 1 diff --git a/test_regress/t/t_flag_help.py b/test_regress/t/t_flag_help.py index 1aa4be54e..290a5ac6f 100755 --- a/test_regress/t/t_flag_help.py +++ b/test_regress/t/t_flag_help.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_help_valgrind.py b/test_regress/t/t_flag_help_valgrind.py index 3969109d8..966b0f356 100755 --- a/test_regress/t/t_flag_help_valgrind.py +++ b/test_regress/t/t_flag_help_valgrind.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 test.run(fails=False, diff --git a/test_regress/t/t_flag_hier0_bad.py b/test_regress/t/t_flag_hier0_bad.py index 9d9e638b4..ee49b0b0b 100755 --- a/test_regress/t/t_flag_hier0_bad.py +++ b/test_regress/t/t_flag_hier0_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_hier1_bad.py b/test_regress/t/t_flag_hier1_bad.py index 6c7b401a8..d1ddb265d 100755 --- a/test_regress/t/t_flag_hier1_bad.py +++ b/test_regress/t/t_flag_hier1_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_hierarchical_threads_bad.py b/test_regress/t/t_flag_hierarchical_threads_bad.py index f6f2005d4..388a16c71 100755 --- a/test_regress/t/t_flag_hierarchical_threads_bad.py +++ b/test_regress/t/t_flag_hierarchical_threads_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_i_empty.py b/test_regress/t/t_flag_i_empty.py index 885a35916..5b8f63784 100755 --- a/test_regress/t/t_flag_i_empty.py +++ b/test_regress/t/t_flag_i_empty.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_i_empty.v b/test_regress/t/t_flag_i_empty.v index df8679e7d..e248628f8 100644 --- a/test_regress/t/t_flag_i_empty.v +++ b/test_regress/t/t_flag_i_empty.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_incdir.py b/test_regress/t/t_flag_incdir.py index a4f25aabb..fa7b658d0 100755 --- a/test_regress/t/t_flag_incdir.py +++ b/test_regress/t/t_flag_incdir.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_incdir.v b/test_regress/t/t_flag_incdir.v index 1d6b33184..afd7eedb0 100644 --- a/test_regress/t/t_flag_incdir.v +++ b/test_regress/t/t_flag_incdir.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "t_flag_f_tsub_inc.v" diff --git a/test_regress/t/t_flag_instr_count_dpi_bad.py b/test_regress/t/t_flag_instr_count_dpi_bad.py index b3e8df414..acd6fa3c6 100755 --- a/test_regress/t/t_flag_instr_count_dpi_bad.py +++ b/test_regress/t/t_flag_instr_count_dpi_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_invalid2_bad.py b/test_regress/t/t_flag_invalid2_bad.py index a91c4f34f..8fa25d99f 100755 --- a/test_regress/t/t_flag_invalid2_bad.py +++ b/test_regress/t/t_flag_invalid2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_invalid_bad.py b/test_regress/t/t_flag_invalid_bad.py index 139abb1ab..948395ffa 100755 --- a/test_regress/t/t_flag_invalid_bad.py +++ b/test_regress/t/t_flag_invalid_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_j_hier.py b/test_regress/t/t_flag_j_hier.py index 4c393789a..bddf78458 100755 --- a/test_regress/t/t_flag_j_hier.py +++ b/test_regress/t/t_flag_j_hier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_j_hier.v b/test_regress/t/t_flag_j_hier.v index 6e3f17aa6..9b1f94756 100644 --- a/test_regress/t/t_flag_j_hier.v +++ b/test_regress/t/t_flag_j_hier.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_language.py b/test_regress/t/t_flag_language.py index 8ce75c418..e64371655 100755 --- a/test_regress/t/t_flag_language.py +++ b/test_regress/t/t_flag_language.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_language.v b/test_regress/t/t_flag_language.v index 23e4e35c2..d515f745e 100644 --- a/test_regress/t/t_flag_language.v +++ b/test_regress/t/t_flag_language.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_language_bad.py b/test_regress/t/t_flag_language_bad.py index 691152651..e363f9146 100755 --- a/test_regress/t/t_flag_language_bad.py +++ b/test_regress/t/t_flag_language_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_language_default.py b/test_regress/t/t_flag_language_default.py index 327acfd7d..1ab03ed5b 100755 --- a/test_regress/t/t_flag_language_default.py +++ b/test_regress/t/t_flag_language_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_ldflags.py b/test_regress/t/t_flag_ldflags.py index 276038a94..a4042eb96 100755 --- a/test_regress/t/t_flag_ldflags.py +++ b/test_regress/t/t_flag_ldflags.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_ldflags.v b/test_regress/t/t_flag_ldflags.v index 743c908a6..ee945cb7a 100644 --- a/test_regress/t/t_flag_ldflags.v +++ b/test_regress/t/t_flag_ldflags.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" pure function void dpii_a_library(); diff --git a/test_regress/t/t_flag_ldflags_a.cpp b/test_regress/t/t_flag_ldflags_a.cpp index 10d3b3ddd..6d5e8734d 100644 --- a/test_regress/t/t_flag_ldflags_a.cpp +++ b/test_regress/t/t_flag_ldflags_a.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_flag_ldflags_c.cpp b/test_regress/t/t_flag_ldflags_c.cpp index 113017b52..276801399 100644 --- a/test_regress/t/t_flag_ldflags_c.cpp +++ b/test_regress/t/t_flag_ldflags_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_flag_ldflags_so.cpp b/test_regress/t/t_flag_ldflags_so.cpp index d9b2707cf..4ee0285bb 100644 --- a/test_regress/t/t_flag_ldflags_so.cpp +++ b/test_regress/t/t_flag_ldflags_so.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_flag_lib.py b/test_regress/t/t_flag_lib.py index 59e45bab9..5820aeaff 100755 --- a/test_regress/t/t_flag_lib.py +++ b/test_regress/t/t_flag_lib.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_lib.v b/test_regress/t/t_flag_lib.v index bcc4c2bd0..17eec74ad 100644 --- a/test_regress/t/t_flag_lib.v +++ b/test_regress/t/t_flag_lib.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_lib_dpi.cpp b/test_regress/t/t_flag_lib_dpi.cpp index 60a3f7eb6..ca49b5b9c 100644 --- a/test_regress/t/t_flag_lib_dpi.cpp +++ b/test_regress/t/t_flag_lib_dpi.cpp @@ -1,8 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Shupei Fan. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Shupei Fan // SPDX-License-Identifier: CC0-1.0 // //************************************************************************* diff --git a/test_regress/t/t_flag_lib_dpi.mk b/test_regress/t/t_flag_lib_dpi.mk index d51f28ed7..823b643e0 100644 --- a/test_regress/t/t_flag_lib_dpi.mk +++ b/test_regress/t/t_flag_lib_dpi.mk @@ -1,7 +1,7 @@ # DESCRIPTION: Verilator: Makefile for Verilog Test module # -# This file ONLY is placed under the Creative Commons Public Domain, for -# any use, without warranty, 2023 by Shupei Fan. +# This file ONLY is placed under the Creative Commons Public Domain +# SPDX-FileCopyrightText: 2023 Shupei Fan # SPDX-License-Identifier: CC0-1.0 include Vt_flag_lib_dpi.mk diff --git a/test_regress/t/t_flag_lib_dpi.py b/test_regress/t/t_flag_lib_dpi.py index 225f73eb6..a62d86233 100755 --- a/test_regress/t/t_flag_lib_dpi.py +++ b/test_regress/t/t_flag_lib_dpi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_lib_dpi.v b/test_regress/t/t_flag_lib_dpi.v index 0f77883a6..8e770067a 100644 --- a/test_regress/t/t_flag_lib_dpi.v +++ b/test_regress/t/t_flag_lib_dpi.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Shupei Fan. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Shupei Fan // SPDX-License-Identifier: CC0-1.0 import "DPI-C" function void write_all_finished(); diff --git a/test_regress/t/t_flag_lib_dpi_main.cpp b/test_regress/t/t_flag_lib_dpi_main.cpp index 3fcfd8179..9e244e0aa 100644 --- a/test_regress/t/t_flag_lib_dpi_main.cpp +++ b/test_regress/t/t_flag_lib_dpi_main.cpp @@ -1,8 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Shupei Fan. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Shupei Fan // SPDX-License-Identifier: CC0-1.0 // //************************************************************************* diff --git a/test_regress/t/t_flag_libcreate_bad.py b/test_regress/t/t_flag_libcreate_bad.py index 8923eb5f0..bccee5896 100755 --- a/test_regress/t/t_flag_libcreate_bad.py +++ b/test_regress/t/t_flag_libcreate_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_libinc.v b/test_regress/t/t_flag_libinc.v index ddb9d5576..772d1bf9a 100644 --- a/test_regress/t/t_flag_libinc.v +++ b/test_regress/t/t_flag_libinc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module liblib_a; diff --git a/test_regress/t/t_flag_main.py b/test_regress/t/t_flag_main.py index 52df09333..f230d9ad8 100755 --- a/test_regress/t/t_flag_main.py +++ b/test_regress/t/t_flag_main.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_main.v b/test_regress/t/t_flag_main.v index 9acb32a0a..a8fe4a901 100644 --- a/test_regress/t/t_flag_main.v +++ b/test_regress/t/t_flag_main.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by engr248. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2020 engr248 // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_main_sc_bad.py b/test_regress/t/t_flag_main_sc_bad.py index 6912ff255..8417c5915 100755 --- a/test_regress/t/t_flag_main_sc_bad.py +++ b/test_regress/t/t_flag_main_sc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_main_top_name.py b/test_regress/t/t_flag_main_top_name.py index 40d6b3d44..b111ee977 100755 --- a/test_regress/t/t_flag_main_top_name.py +++ b/test_regress/t/t_flag_main_top_name.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_main_top_name.v b/test_regress/t/t_flag_main_top_name.v index ced845c9a..9d9198f78 100644 --- a/test_regress/t/t_flag_main_top_name.v +++ b/test_regress/t/t_flag_main_top_name.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2023 Don Williamson and Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top; diff --git a/test_regress/t/t_flag_main_top_name_empty.py b/test_regress/t/t_flag_main_top_name_empty.py index 872d0f076..367b55176 100755 --- a/test_regress/t/t_flag_main_top_name_empty.py +++ b/test_regress/t/t_flag_main_top_name_empty.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_make_bad.py b/test_regress/t/t_flag_make_bad.py index 39e7f80eb..230abbe4d 100755 --- a/test_regress/t/t_flag_make_bad.py +++ b/test_regress/t/t_flag_make_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_make_cmake.py b/test_regress/t/t_flag_make_cmake.py index da3b67fa1..903afd785 100755 --- a/test_regress/t/t_flag_make_cmake.py +++ b/test_regress/t/t_flag_make_cmake.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_make_cmake.v b/test_regress/t/t_flag_make_cmake.v index 2478ff819..45f3806ea 100644 --- a/test_regress/t/t_flag_make_cmake.v +++ b/test_regress/t/t_flag_make_cmake.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_flag_make_cmake_sc.py b/test_regress/t/t_flag_make_cmake_sc.py index b32ca9667..3f9a83e6f 100755 --- a/test_regress/t/t_flag_make_cmake_sc.py +++ b/test_regress/t/t_flag_make_cmake_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This test tests CMake support for SystemC diff --git a/test_regress/t/t_flag_make_cmake_sc.v b/test_regress/t/t_flag_make_cmake_sc.v index 2478ff819..45f3806ea 100644 --- a/test_regress/t/t_flag_make_cmake_sc.v +++ b/test_regress/t/t_flag_make_cmake_sc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_flag_make_gmake.py b/test_regress/t/t_flag_make_gmake.py index aa50772d8..997b187ea 100755 --- a/test_regress/t/t_flag_make_gmake.py +++ b/test_regress/t/t_flag_make_gmake.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_make_json.py b/test_regress/t/t_flag_make_json.py index 8d0ef863f..f4c7abc4b 100755 --- a/test_regress/t/t_flag_make_json.py +++ b/test_regress/t/t_flag_make_json.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_mmd.py b/test_regress/t/t_flag_mmd.py index 4709521ae..dca553a58 100755 --- a/test_regress/t/t_flag_mmd.py +++ b/test_regress/t/t_flag_mmd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_mmd.v b/test_regress/t/t_flag_mmd.v index df8679e7d..e248628f8 100644 --- a/test_regress/t/t_flag_mmd.v +++ b/test_regress/t/t_flag_mmd.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_modprefix_bad.py b/test_regress/t/t_flag_modprefix_bad.py index 7d78e05da..c964a07ae 100755 --- a/test_regress/t/t_flag_modprefix_bad.py +++ b/test_regress/t/t_flag_modprefix_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_names.py b/test_regress/t/t_flag_names.py index f4807c1bc..eb095d9d2 100755 --- a/test_regress/t/t_flag_names.py +++ b/test_regress/t/t_flag_names.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_names.v b/test_regress/t/t_flag_names.v index d8d17edfb..669d56c22 100644 --- a/test_regress/t/t_flag_names.v +++ b/test_regress/t/t_flag_names.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_no_unlimited_stack.py b/test_regress/t/t_flag_no_unlimited_stack.py index d414c3381..f89627fee 100755 --- a/test_regress/t/t_flag_no_unlimited_stack.py +++ b/test_regress/t/t_flag_no_unlimited_stack.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_no_unlimited_stack.v b/test_regress/t/t_flag_no_unlimited_stack.v index f6668377e..955d23308 100644 --- a/test_regress/t/t_flag_no_unlimited_stack.v +++ b/test_regress/t/t_flag_no_unlimited_stack.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_nofile_bad.out b/test_regress/t/t_flag_nofile_bad.out index 38697a96c..97ad5ccd8 100644 --- a/test_regress/t/t_flag_nofile_bad.out +++ b/test_regress/t/t_flag_nofile_bad.out @@ -1,2 +1,2 @@ -%Error: verilator: No Input Verilog file specified on command line, see verilator --help for more information +%Error: verilator: No input Verilog file specified on command line, see 'verilator --help' for more information ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. diff --git a/test_regress/t/t_flag_nofile_bad.py b/test_regress/t/t_flag_nofile_bad.py index 15e3547bb..bda3bb62a 100755 --- a/test_regress/t/t_flag_nofile_bad.py +++ b/test_regress/t/t_flag_nofile_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_nomod_bad.py b/test_regress/t/t_flag_nomod_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_flag_nomod_bad.py +++ b/test_regress/t/t_flag_nomod_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_nomod_bad.v b/test_regress/t/t_flag_nomod_bad.v index 5a0ce9330..7153d78d2 100644 --- a/test_regress/t/t_flag_nomod_bad.v +++ b/test_regress/t/t_flag_nomod_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define EMPTY 1 diff --git a/test_regress/t/t_flag_noop_bad.out b/test_regress/t/t_flag_noop_bad.out index 44c3e6392..ddfc7d07c 100644 --- a/test_regress/t/t_flag_noop_bad.out +++ b/test_regress/t/t_flag_noop_bad.out @@ -1,2 +1,2 @@ -%Error: verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, --xml-only, --json-only or --E option +%Error: verilator: Need --binary, --cc, --sc, --dpi-hdr-only, --lint-only, --json-only or --E option ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. diff --git a/test_regress/t/t_flag_noop_bad.py b/test_regress/t/t_flag_noop_bad.py index 8ac06d1a7..5712967fa 100755 --- a/test_regress/t/t_flag_noop_bad.py +++ b/test_regress/t/t_flag_noop_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_noop_bad.v b/test_regress/t/t_flag_noop_bad.v index 1b792181f..55743c03a 100644 --- a/test_regress/t/t_flag_noop_bad.v +++ b/test_regress/t/t_flag_noop_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_only_bad.out b/test_regress/t/t_flag_only_bad.out old mode 100755 new mode 100644 index 6fcbc3a92..5fef92226 --- a/test_regress/t/t_flag_only_bad.out +++ b/test_regress/t/t_flag_only_bad.out @@ -1,3 +1,3 @@ -%Error: The following cannot be used together: --binary, -E, --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual +%Error: The following cannot be used together: --binary, -E, --dpi-hdr-only, --lint-only, --json-only. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_flag_only_bad.py b/test_regress/t/t_flag_only_bad.py index ebce0ba4b..a622a4df6 100755 --- a/test_regress/t/t_flag_only_bad.py +++ b/test_regress/t/t_flag_only_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -13,7 +13,7 @@ test.scenarios('vlt') test.top_filename = "t/t_flag_main.v" test.lint( - verilator_flags2=["-Wno-DEPRECATED --binary -E --dpi-hdr-only --xml-only --json-only -Wall"], + verilator_flags2=["-Wno-DEPRECATED --binary -E --dpi-hdr-only --lint-only --json-only -Wall"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_flag_only_bad2.out b/test_regress/t/t_flag_only_bad2.out old mode 100755 new mode 100644 index ce4a5c345..d63f296b2 --- a/test_regress/t/t_flag_only_bad2.out +++ b/test_regress/t/t_flag_only_bad2.out @@ -1,3 +1,3 @@ -%Error: The following cannot be used together: --build, -E, --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual +%Error: The following cannot be used together: --build, -E, --dpi-hdr-only, --lint-only, --json-only. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_flag_only_bad2.py b/test_regress/t/t_flag_only_bad2.py index 98e0fe1aa..12455ee54 100755 --- a/test_regress/t/t_flag_only_bad2.py +++ b/test_regress/t/t_flag_only_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -13,7 +13,7 @@ test.scenarios('vlt') test.top_filename = "t/t_flag_main.v" test.lint(verilator_flags2=[ - "-Wno-DEPRECATED --build -E -Wno-fatal --dpi-hdr-only --xml-only --json-only" + "-Wno-DEPRECATED --build -E -Wno-fatal --dpi-hdr-only --lint-only --json-only" ], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_flag_only_bad3.out b/test_regress/t/t_flag_only_bad3.out old mode 100755 new mode 100644 index 604118317..d66aa2e93 --- a/test_regress/t/t_flag_only_bad3.out +++ b/test_regress/t/t_flag_only_bad3.out @@ -1,3 +1,3 @@ -%Error: The following cannot be used together: --dpi-hdr-only, --lint-only, --xml-only, --json-only. Suggest see manual +%Error: The following cannot be used together: --dpi-hdr-only, --lint-only, --json-only. Suggest see manual ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_flag_only_bad3.py b/test_regress/t/t_flag_only_bad3.py index 6f0ee1fe6..ea74d61ca 100755 --- a/test_regress/t/t_flag_only_bad3.py +++ b/test_regress/t/t_flag_only_bad3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -13,7 +13,7 @@ test.scenarios('vlt') test.top_filename = "t/t_flag_main.v" test.lint( - verilator_flags2=["-Wall -Wno-DEPRECATED -Wno-fatal --dpi-hdr-only --xml-only --json-only"], + verilator_flags2=["-Wall -Wno-DEPRECATED -Wno-fatal --dpi-hdr-only --lint-only --json-only"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_flag_output_groups.py b/test_regress/t/t_flag_output_groups.py index 37cfd95d2..1c6ccfaf8 100755 --- a/test_regress/t/t_flag_output_groups.py +++ b/test_regress/t/t_flag_output_groups.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_output_groups.v b/test_regress/t/t_flag_output_groups.v index 49e2ee98a..909fa1c23 100644 --- a/test_regress/t/t_flag_output_groups.v +++ b/test_regress/t/t_flag_output_groups.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 virtual class Base; @@ -27,7 +27,7 @@ module t (/*AUTOARG*/ genvar i; for (i = 0; i < MAX; i++) initial begin - Foo#(i) item = new; + automatic Foo#(i) item = new; q.push_back(item); end endgenerate diff --git a/test_regress/t/t_flag_output_groups_bad.py b/test_regress/t/t_flag_output_groups_bad.py index 830b04e80..bb33d6fda 100755 --- a/test_regress/t/t_flag_output_groups_bad.py +++ b/test_regress/t/t_flag_output_groups_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_parameter.py b/test_regress/t/t_flag_parameter.py index a0976af1a..2768b3967 100755 --- a/test_regress/t/t_flag_parameter.py +++ b/test_regress/t/t_flag_parameter.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_parameter.v b/test_regress/t/t_flag_parameter.v index 213d648bc..837b367e5 100644 --- a/test_regress/t/t_flag_parameter.v +++ b/test_regress/t/t_flag_parameter.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // Special cases of "string parameters" : diff --git a/test_regress/t/t_flag_parameter_bad.py b/test_regress/t/t_flag_parameter_bad.py index 79a16fac7..087adc1aa 100755 --- a/test_regress/t/t_flag_parameter_bad.py +++ b/test_regress/t/t_flag_parameter_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_parameter_hier.py b/test_regress/t/t_flag_parameter_hier.py index b795ba12c..083948238 100755 --- a/test_regress/t/t_flag_parameter_hier.py +++ b/test_regress/t/t_flag_parameter_hier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_parameter_hier.v b/test_regress/t/t_flag_parameter_hier.v index 0d611bbb1..d92484dd7 100644 --- a/test_regress/t/t_flag_parameter_hier.v +++ b/test_regress/t/t_flag_parameter_hier.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_flag_parameter_pkg.py b/test_regress/t/t_flag_parameter_pkg.py index 84bc7ac5a..8831c9d6d 100755 --- a/test_regress/t/t_flag_parameter_pkg.py +++ b/test_regress/t/t_flag_parameter_pkg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_parameter_pkg.v b/test_regress/t/t_flag_parameter_pkg.v index 5c16cf732..094ee408b 100644 --- a/test_regress/t/t_flag_parameter_pkg.v +++ b/test_regress/t/t_flag_parameter_pkg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Adrien Le Masle. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Adrien Le Masle // SPDX-License-Identifier: CC0-1.0 package pack_a; diff --git a/test_regress/t/t_flag_prefix.py b/test_regress/t/t_flag_prefix.py index 4d2149186..08a786f04 100755 --- a/test_regress/t/t_flag_prefix.py +++ b/test_regress/t/t_flag_prefix.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_prefix.v b/test_regress/t/t_flag_prefix.v index d350086b8..39470ac9b 100644 --- a/test_regress/t/t_flag_prefix.v +++ b/test_regress/t/t_flag_prefix.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_prefix_bad.py b/test_regress/t/t_flag_prefix_bad.py index 70b21989f..e51bad06a 100755 --- a/test_regress/t/t_flag_prefix_bad.py +++ b/test_regress/t/t_flag_prefix_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_quiet_build.py b/test_regress/t/t_flag_quiet_build.py index 558747e45..574f3c5fe 100755 --- a/test_regress/t/t_flag_quiet_build.py +++ b/test_regress/t/t_flag_quiet_build.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_quiet_build.v b/test_regress/t/t_flag_quiet_build.v index fbcbd7ce9..3fbbf0710 100644 --- a/test_regress/t/t_flag_quiet_build.v +++ b/test_regress/t/t_flag_quiet_build.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_quiet_exit.py b/test_regress/t/t_flag_quiet_exit.py index ad7e5791a..c7f044c49 100755 --- a/test_regress/t/t_flag_quiet_exit.py +++ b/test_regress/t/t_flag_quiet_exit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_quiet_stats.py b/test_regress/t/t_flag_quiet_stats.py index 03b230104..054116ec8 100755 --- a/test_regress/t/t_flag_quiet_stats.py +++ b/test_regress/t/t_flag_quiet_stats.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_quiet_stats.v b/test_regress/t/t_flag_quiet_stats.v index 207a1d8d6..57d264ae8 100644 --- a/test_regress/t/t_flag_quiet_stats.v +++ b/test_regress/t/t_flag_quiet_stats.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_quiet_stats2.py b/test_regress/t/t_flag_quiet_stats2.py index 0e875e258..1875afd76 100755 --- a/test_regress/t/t_flag_quiet_stats2.py +++ b/test_regress/t/t_flag_quiet_stats2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_quiet_stats3.py b/test_regress/t/t_flag_quiet_stats3.py index f7fb9b54b..e08e61b84 100755 --- a/test_regress/t/t_flag_quiet_stats3.py +++ b/test_regress/t/t_flag_quiet_stats3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_relinc.py b/test_regress/t/t_flag_relinc.py index af6f9fa75..b9f2a7213 100755 --- a/test_regress/t/t_flag_relinc.py +++ b/test_regress/t/t_flag_relinc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_relinc.v b/test_regress/t/t_flag_relinc.v index 477af105f..31f454451 100644 --- a/test_regress/t/t_flag_relinc.v +++ b/test_regress/t/t_flag_relinc.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v b/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v index 84a4c77df..2f5ff8b97 100644 --- a/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v +++ b/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v @@ -1,16 +1,16 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `include "../include/t_flag_relinc.vh" module t_flag_relinc_sub (); - initial begin - `all_finished; - $finish; - end + initial begin + `all_finished; + $finish; + end endmodule diff --git a/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh b/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh index af1265d3e..e3272ec45 100644 --- a/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh +++ b/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2017 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define all_finished $write("*-* All Finished *-*\n") diff --git a/test_regress/t/t_flag_runtime_debug.py b/test_regress/t/t_flag_runtime_debug.py index c275d96fa..eff3c3cc5 100755 --- a/test_regress/t/t_flag_runtime_debug.py +++ b/test_regress/t/t_flag_runtime_debug.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_runtime_timeout_bad.py b/test_regress/t/t_flag_runtime_timeout_bad.py index 9f223c3cd..119abcb33 100755 --- a/test_regress/t/t_flag_runtime_timeout_bad.py +++ b/test_regress/t/t_flag_runtime_timeout_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_runtime_timeout_bad.v b/test_regress/t/t_flag_runtime_timeout_bad.v index c996f9c8a..ea63d15eb 100644 --- a/test_regress/t/t_flag_runtime_timeout_bad.v +++ b/test_regress/t/t_flag_runtime_timeout_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_sched_zero_delay_none_bad.out b/test_regress/t/t_flag_sched_zero_delay_none_bad.out new file mode 100644 index 000000000..6ca898a42 --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_none_bad.out @@ -0,0 +1,17 @@ +%Warning-ZERODLY: t/t_flag_sched_zero_delay_none_bad.v:12:5: Value of # delay control statically unknown. Assuming it can be #0. + : ... If all # delays are non-zero at runtime, + : ... use '--no-sched-zero-delay' for improved performance. + : ... If a real #0 is expected at runtime, + : ... use '--sched-zero-delay' to suppress this warning. + 12 | #a; + | ^ + ... For warning description see https://verilator.org/warn/ZERODLY?v=latest + ... Use "/* verilator lint_off ZERODLY */" and lint_on around source to disable this message. +%Warning-ZERODLY: t/t_flag_sched_zero_delay_none_bad.v:14:5: Value of # delay control statically unknown. Assuming it can be #0. + : ... If all # delays are non-zero at runtime, + : ... use '--no-sched-zero-delay' for improved performance. + : ... If a real #0 is expected at runtime, + : ... use '--sched-zero-delay' to suppress this warning. + 14 | #a; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_flag_sched_zero_delay_none_bad.py b/test_regress/t/t_flag_sched_zero_delay_none_bad.py new file mode 100755 index 000000000..e242acd20 --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_none_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--binary"], fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_sched_zero_delay_none_bad.v b/test_regress/t/t_flag_sched_zero_delay_none_bad.v new file mode 100644 index 000000000..461405e8d --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_none_bad.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module top; + int a = 1; + initial begin + #a; + a = 2; + #a; + end +endmodule diff --git a/test_regress/t/t_flag_sched_zero_delay_off_bad.out b/test_regress/t/t_flag_sched_zero_delay_off_bad.out new file mode 100644 index 000000000..d2834c15e --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_off_bad.out @@ -0,0 +1,7 @@ +%Warning-ZERODLY: t/t_flag_sched_zero_delay_off_bad.v:10:11: Static #0 delay exists, but '--no-sched-zero-delay' was given. + : ... Can proceed, but this will fail at runtime if executed. + 10 | initial #0; + | ^ + ... For warning description see https://verilator.org/warn/ZERODLY?v=latest + ... Use "/* verilator lint_off ZERODLY */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_flag_sched_zero_delay_off_bad.py b/test_regress/t/t_flag_sched_zero_delay_off_bad.py new file mode 100755 index 000000000..7168a0155 --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_off_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--binary", "--no-sched-zero-delay"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_sched_zero_delay_off_bad.v b/test_regress/t/t_flag_sched_zero_delay_off_bad.v new file mode 100644 index 000000000..e0e03f3c3 --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_off_bad.v @@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module top; + initial #0; +endmodule diff --git a/test_regress/t/t_flag_sched_zero_delay_off_run.out b/test_regress/t/t_flag_sched_zero_delay_off_run.out new file mode 100644 index 000000000..fe0ff6f4a --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_off_run.out @@ -0,0 +1,6 @@ +%Warning-ZERODLY: t/t_flag_sched_zero_delay_off_run.v:17:9: Static #0 delay exists, but '--no-sched-zero-delay' was given. + : ... Can proceed, but this will fail at runtime if executed. + 17 | #0; + | ^ + ... For warning description see https://verilator.org/warn/ZERODLY?v=latest + ... Use "/* verilator lint_off ZERODLY */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_flag_sched_zero_delay_off_run.py b/test_regress/t/t_flag_sched_zero_delay_off_run.py new file mode 100755 index 000000000..208f69c94 --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_off_run.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=[ + "--timing", "--main", "--exe", "--no-skip-identical", "--no-sched-zero-delay", "-Wno-fatal" +], + expect_filename=test.golden_filename) + +test.execute(check_finished=True) + +test.passes() diff --git a/test_regress/t/t_flag_sched_zero_delay_off_run.v b/test_regress/t/t_flag_sched_zero_delay_off_run.v new file mode 100644 index 000000000..17957ce8d --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_off_run.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module top; + int n = 0; + initial begin + repeat (5) begin + #10; + $display("%02t tick", $time); + ++n; + if (n > 5) begin + #0; // Will not execute + $stop; + end + end + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_flag_sched_zero_delay_off_run_bad.out b/test_regress/t/t_flag_sched_zero_delay_off_run_bad.out new file mode 100644 index 000000000..471817f17 --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_off_run_bad.out @@ -0,0 +1,2 @@ +%Error-ZERODLY: t/t_flag_sched_zero_delay_off_bad.v:9: Design Verilated with '--no-sched-zero-delay', but #0 delay executed at runtime +Aborting... diff --git a/test_regress/t/t_flag_sched_zero_delay_off_run_bad.py b/test_regress/t/t_flag_sched_zero_delay_off_run_bad.py new file mode 100755 index 000000000..af4e99e4c --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_off_run_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.top_filename = "t_flag_sched_zero_delay_off_bad.v" + +test.compile(verilator_flags2=["--binary", "--no-sched-zero-delay", "-Wno-fatal"]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_flag_sched_zero_delay_on.py b/test_regress/t/t_flag_sched_zero_delay_on.py new file mode 100755 index 000000000..38a84cb84 --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_on.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--binary", "--sched-zero-delay"]) + +test.execute(check_finished=True) + +test.passes() diff --git a/test_regress/t/t_flag_sched_zero_delay_on.v b/test_regress/t/t_flag_sched_zero_delay_on.v new file mode 100644 index 000000000..d96eadab2 --- /dev/null +++ b/test_regress/t/t_flag_sched_zero_delay_on.v @@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module top; + initial begin + #0; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_flag_skipidentical.py b/test_regress/t/t_flag_skipidentical.py index 59c1f403d..793442553 100755 --- a/test_regress/t/t_flag_skipidentical.py +++ b/test_regress/t/t_flag_skipidentical.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_skipidentical.v b/test_regress/t/t_flag_skipidentical.v index 461271fca..4438b3e0a 100644 --- a/test_regress/t/t_flag_skipidentical.v +++ b/test_regress/t/t_flag_skipidentical.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_stats.py b/test_regress/t/t_flag_stats.py index e3ec064b6..a3dc08f02 100755 --- a/test_regress/t/t_flag_stats.py +++ b/test_regress/t/t_flag_stats.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_stats.v b/test_regress/t/t_flag_stats.v index 1026d969b..323b631fd 100644 --- a/test_regress/t/t_flag_stats.v +++ b/test_regress/t/t_flag_stats.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (b, b2); diff --git a/test_regress/t/t_flag_structs_packed.py b/test_regress/t/t_flag_structs_packed.py index 77a354d22..acc4cf764 100755 --- a/test_regress/t/t_flag_structs_packed.py +++ b/test_regress/t/t_flag_structs_packed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_structs_packed.v b/test_regress/t/t_flag_structs_packed.v index e062db15a..3d5a95760 100644 --- a/test_regress/t/t_flag_structs_packed.v +++ b/test_regress/t/t_flag_structs_packed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module x; diff --git a/test_regress/t/t_flag_structs_packed_bad.py b/test_regress/t/t_flag_structs_packed_bad.py index 002271397..e9f49f826 100755 --- a/test_regress/t/t_flag_structs_packed_bad.py +++ b/test_regress/t/t_flag_structs_packed_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_suggest.out b/test_regress/t/t_flag_suggest.out index d038c2b5a..0186ffb33 100644 --- a/test_regress/t/t_flag_suggest.out +++ b/test_regress/t/t_flag_suggest.out @@ -20,5 +20,5 @@ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Unknown language specified: 1364-1997... Suggested alternative: '1364-1995' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: verilator: No Input Verilog file specified on command line, see verilator --help for more information +%Error: verilator: No input Verilog file specified on command line, see 'verilator --help' for more information ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_flag_suggest.py b/test_regress/t/t_flag_suggest.py index baf7f8394..24bdc0223 100755 --- a/test_regress/t/t_flag_suggest.py +++ b/test_regress/t/t_flag_suggest.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_supported.py b/test_regress/t/t_flag_supported.py index 56d4984b8..b6d5d616c 100755 --- a/test_regress/t/t_flag_supported.py +++ b/test_regress/t/t_flag_supported.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_supported_1.out b/test_regress/t/t_flag_supported_1.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_flag_supported_empty.out b/test_regress/t/t_flag_supported_empty.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_flag_threads_bad.py b/test_regress/t/t_flag_threads_bad.py index 470ed6fe3..8f0fa4823 100755 --- a/test_regress/t/t_flag_threads_bad.py +++ b/test_regress/t/t_flag_threads_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_threads_bad2.py b/test_regress/t/t_flag_threads_bad2.py index 03f779c30..207bb3f42 100755 --- a/test_regress/t/t_flag_threads_bad2.py +++ b/test_regress/t/t_flag_threads_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_threads_dpi_bad.py b/test_regress/t/t_flag_threads_dpi_bad.py index e37bc99e3..78070246e 100755 --- a/test_regress/t/t_flag_threads_dpi_bad.py +++ b/test_regress/t/t_flag_threads_dpi_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_timescale.py b/test_regress/t/t_flag_timescale.py index 0aee7a5b7..a7e9d7fe1 100755 --- a/test_regress/t/t_flag_timescale.py +++ b/test_regress/t/t_flag_timescale.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_timescale.v b/test_regress/t/t_flag_timescale.v index ce1d0aee8..4f666928c 100644 --- a/test_regress/t/t_flag_timescale.v +++ b/test_regress/t/t_flag_timescale.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_timescale_override.py b/test_regress/t/t_flag_timescale_override.py index f3c33e6b1..50b24072d 100755 --- a/test_regress/t/t_flag_timescale_override.py +++ b/test_regress/t/t_flag_timescale_override.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_timescale_override.v b/test_regress/t/t_flag_timescale_override.v index e66060f4c..5de3ce48b 100644 --- a/test_regress/t/t_flag_timescale_override.v +++ b/test_regress/t/t_flag_timescale_override.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1s/1s diff --git a/test_regress/t/t_flag_timescale_override2.py b/test_regress/t/t_flag_timescale_override2.py index 1403c4c24..383c3c985 100755 --- a/test_regress/t/t_flag_timescale_override2.py +++ b/test_regress/t/t_flag_timescale_override2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_topmodule.py b/test_regress/t/t_flag_topmodule.py index 3d54ce7d9..ffb282f19 100755 --- a/test_regress/t/t_flag_topmodule.py +++ b/test_regress/t/t_flag_topmodule.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_topmodule.v b/test_regress/t/t_flag_topmodule.v index 403ab4299..68d3bd085 100644 --- a/test_regress/t/t_flag_topmodule.v +++ b/test_regress/t/t_flag_topmodule.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module a; diff --git a/test_regress/t/t_flag_topmodule_bad.py b/test_regress/t/t_flag_topmodule_bad.py index 55e58e547..8ebe14273 100755 --- a/test_regress/t/t_flag_topmodule_bad.py +++ b/test_regress/t/t_flag_topmodule_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_topmodule_bad2.py b/test_regress/t/t_flag_topmodule_bad2.py index e78d43f39..2a4292b99 100755 --- a/test_regress/t/t_flag_topmodule_bad2.py +++ b/test_regress/t/t_flag_topmodule_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_topmodule_bad3.out b/test_regress/t/t_flag_topmodule_bad3.out new file mode 100644 index 000000000..324be4de9 --- /dev/null +++ b/test_regress/t/t_flag_topmodule_bad3.out @@ -0,0 +1,4 @@ +%Error: Specified --top-module 'notfound' was not found in design. + ... Suggested alternative: 'notfound1' + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_flag_topmodule_bad3.py b/test_regress/t/t_flag_topmodule_bad3.py new file mode 100755 index 000000000..c7a296c34 --- /dev/null +++ b/test_regress/t/t_flag_topmodule_bad3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, v_flags2=["--top-module notfound"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_xml_output.v b/test_regress/t/t_flag_topmodule_bad3.v similarity index 59% rename from test_regress/t/t_xml_output.v rename to test_regress/t/t_flag_topmodule_bad3.v index ccde3378d..b88f2745b 100644 --- a/test_regress/t/t_xml_output.v +++ b/test_regress/t/t_flag_topmodule_bad3.v @@ -1,10 +1,11 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module m - (input clk); // verilator tag foo_op - +module notfound1; +endmodule + +module notfound2; endmodule diff --git a/test_regress/t/t_flag_topmodule_inline.py b/test_regress/t/t_flag_topmodule_inline.py index 5738ae537..037ac0456 100755 --- a/test_regress/t/t_flag_topmodule_inline.py +++ b/test_regress/t/t_flag_topmodule_inline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_topmodule_inline.v b/test_regress/t/t_flag_topmodule_inline.v index 4a75d8099..f27b3f2ea 100644 --- a/test_regress/t/t_flag_topmodule_inline.v +++ b/test_regress/t/t_flag_topmodule_inline.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module a; diff --git a/test_regress/t/t_flag_trace_threads_bad.py b/test_regress/t/t_flag_trace_threads_bad.py index 43768ff94..8fd91771b 100755 --- a/test_regress/t/t_flag_trace_threads_bad.py +++ b/test_regress/t/t_flag_trace_threads_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_unroll_limit_const.py b/test_regress/t/t_flag_unroll_limit_const.py index ce5bb61c7..a278fb0b8 100755 --- a/test_regress/t/t_flag_unroll_limit_const.py +++ b/test_regress/t/t_flag_unroll_limit_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_unroll_limit_const.v b/test_regress/t/t_flag_unroll_limit_const.v index 129cb4769..c50741308 100644 --- a/test_regress/t/t_flag_unroll_limit_const.v +++ b/test_regress/t/t_flag_unroll_limit_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 function automatic int f(int x); diff --git a/test_regress/t/t_flag_unroll_limit_gen.py b/test_regress/t/t_flag_unroll_limit_gen.py index ce5bb61c7..a278fb0b8 100755 --- a/test_regress/t/t_flag_unroll_limit_gen.py +++ b/test_regress/t/t_flag_unroll_limit_gen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_unroll_limit_gen.v b/test_regress/t/t_flag_unroll_limit_gen.v index 04bb741d2..af5f3c4a2 100644 --- a/test_regress/t/t_flag_unroll_limit_gen.v +++ b/test_regress/t/t_flag_unroll_limit_gen.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_unroll_limit_stmt.py b/test_regress/t/t_flag_unroll_limit_stmt.py index ce5bb61c7..a278fb0b8 100755 --- a/test_regress/t/t_flag_unroll_limit_stmt.py +++ b/test_regress/t/t_flag_unroll_limit_stmt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_unroll_limit_stmt.v b/test_regress/t/t_flag_unroll_limit_stmt.v index 1eec5e37f..9de6b1e51 100644 --- a/test_regress/t/t_flag_unroll_limit_stmt.v +++ b/test_regress/t/t_flag_unroll_limit_stmt.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_values_bad.out b/test_regress/t/t_flag_values_bad.out index ff3be40f5..d875faf80 100644 --- a/test_regress/t/t_flag_values_bad.out +++ b/test_regress/t/t_flag_values_bad.out @@ -3,4 +3,5 @@ %Error: --output-split-ctrace must be >= 0: -1 %Error: --preproc-token-limit must be > 0: 0 %Error: --reloop-limit must be >= 2: -1 +%Error: --replication-limit must be >= 0: -1 %Error: Exiting due to diff --git a/test_regress/t/t_flag_values_bad.py b/test_regress/t/t_flag_values_bad.py index 0bebd8379..e8b403f54 100755 --- a/test_regress/t/t_flag_values_bad.py +++ b/test_regress/t/t_flag_values_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -13,7 +13,7 @@ test.scenarios('vlt') test.lint(verilator_flags2=[ "--output-split-cfuncs -1", "--output-split-ctrace -1", "--preproc-token-limit 0", - "--reloop-limit -1" + "--reloop-limit -1", "--replication-limit -1" ], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_flag_values_deprecated.py b/test_regress/t/t_flag_values_deprecated.py index 8db5f897f..2ea3078be 100755 --- a/test_regress/t/t_flag_values_deprecated.py +++ b/test_regress/t/t_flag_values_deprecated.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_verilate.py b/test_regress/t/t_flag_verilate.py index 38928e3db..e70ca2d3e 100755 --- a/test_regress/t/t_flag_verilate.py +++ b/test_regress/t/t_flag_verilate.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_verilate_threads_bad.py b/test_regress/t/t_flag_verilate_threads_bad.py index ec9afe52a..cdb803dbb 100755 --- a/test_regress/t/t_flag_verilate_threads_bad.py +++ b/test_regress/t/t_flag_verilate_threads_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_version.py b/test_regress/t/t_flag_version.py index 05b74a5da..d712b34c9 100755 --- a/test_regress/t/t_flag_version.py +++ b/test_regress/t/t_flag_version.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_werror.v b/test_regress/t/t_flag_werror.v index fcf6dd9ac..445056058 100644 --- a/test_regress/t/t_flag_werror.v +++ b/test_regress/t/t_flag_werror.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_werror_bad1.py b/test_regress/t/t_flag_werror_bad1.py index 61de16fab..23f6deb8c 100755 --- a/test_regress/t/t_flag_werror_bad1.py +++ b/test_regress/t/t_flag_werror_bad1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_werror_bad2.py b/test_regress/t/t_flag_werror_bad2.py index 98c683a89..59105191b 100755 --- a/test_regress/t/t_flag_werror_bad2.py +++ b/test_regress/t/t_flag_werror_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_werror_bad3.py b/test_regress/t/t_flag_werror_bad3.py index 7d2cd8587..1062abf18 100755 --- a/test_regress/t/t_flag_werror_bad3.py +++ b/test_regress/t/t_flag_werror_bad3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_wfatal.py b/test_regress/t/t_flag_wfatal.py index 02fa078ff..997d6f424 100755 --- a/test_regress/t/t_flag_wfatal.py +++ b/test_regress/t/t_flag_wfatal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_wfatal.v b/test_regress/t/t_flag_wfatal.v index fcf6dd9ac..445056058 100644 --- a/test_regress/t/t_flag_wfatal.v +++ b/test_regress/t/t_flag_wfatal.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_woff.py b/test_regress/t/t_flag_woff.py index b31c5f049..c415f213a 100755 --- a/test_regress/t/t_flag_woff.py +++ b/test_regress/t/t_flag_woff.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_woff.v b/test_regress/t/t_flag_woff.v index 1626c524c..ee714358e 100644 --- a/test_regress/t/t_flag_woff.v +++ b/test_regress/t/t_flag_woff.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_woff_bad.py b/test_regress/t/t_flag_woff_bad.py index 23a96f684..6dd22d495 100755 --- a/test_regress/t/t_flag_woff_bad.py +++ b/test_regress/t/t_flag_woff_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_wpedantic_bad.py b/test_regress/t/t_flag_wpedantic_bad.py index 4cc015636..ac8e3fac3 100755 --- a/test_regress/t/t_flag_wpedantic_bad.py +++ b/test_regress/t/t_flag_wpedantic_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_wpedantic_bad.v b/test_regress/t/t_flag_wpedantic_bad.v index f0d3ac80a..9514dca08 100644 --- a/test_regress/t/t_flag_wpedantic_bad.v +++ b/test_regress/t/t_flag_wpedantic_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_wwarn_bad.py b/test_regress/t/t_flag_wwarn_bad.py index ec10e44d4..2c98087aa 100755 --- a/test_regress/t/t_flag_wwarn_bad.py +++ b/test_regress/t/t_flag_wwarn_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_x_assign_bad.py b/test_regress/t/t_flag_x_assign_bad.py index a800d4eb2..02a6f1414 100755 --- a/test_regress/t/t_flag_x_assign_bad.py +++ b/test_regress/t/t_flag_x_assign_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_x_initial_bad.py b/test_regress/t/t_flag_x_initial_bad.py index 98cc57a39..f5eb5d59f 100755 --- a/test_regress/t/t_flag_x_initial_bad.py +++ b/test_regress/t/t_flag_x_initial_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_xinitial_0.py b/test_regress/t/t_flag_xinitial_0.py index a5c7efa68..082f1d0ba 100755 --- a/test_regress/t/t_flag_xinitial_0.py +++ b/test_regress/t/t_flag_xinitial_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_xinitial_0.v b/test_regress/t/t_flag_xinitial_0.v index 1d3bcc9f5..1e5b9ae0b 100644 --- a/test_regress/t/t_flag_xinitial_0.v +++ b/test_regress/t/t_flag_xinitial_0.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_flag_xinitial_unique.py b/test_regress/t/t_flag_xinitial_unique.py index 2426f64bf..b9ca8f3e8 100755 --- a/test_regress/t/t_flag_xinitial_unique.py +++ b/test_regress/t/t_flag_xinitial_unique.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_flag_xinitial_unique.v b/test_regress/t/t_flag_xinitial_unique.v index aff70e92c..dd63dc905 100644 --- a/test_regress/t/t_flag_xinitial_unique.v +++ b/test_regress/t/t_flag_xinitial_unique.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_for_assign.py b/test_regress/t/t_for_assign.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_for_assign.py +++ b/test_regress/t/t_for_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_for_assign.v b/test_regress/t/t_for_assign.v index d2631f22a..41fe53660 100644 --- a/test_regress/t/t_for_assign.v +++ b/test_regress/t/t_for_assign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_for_break.py b/test_regress/t/t_for_break.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_for_break.py +++ b/test_regress/t/t_for_break.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_for_break.v b/test_regress/t/t_for_break.v index 0b12b7d38..0bfd96e95 100644 --- a/test_regress/t/t_for_break.v +++ b/test_regress/t/t_for_break.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_for_comma.py b/test_regress/t/t_for_comma.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_for_comma.py +++ b/test_regress/t/t_for_comma.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_for_comma.v b/test_regress/t/t_for_comma.v index b9e35a744..30e172be9 100644 --- a/test_regress/t/t_for_comma.v +++ b/test_regress/t/t_for_comma.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define checkc(expc) \ diff --git a/test_regress/t/t_for_count.py b/test_regress/t/t_for_count.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_for_count.py +++ b/test_regress/t/t_for_count.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_for_count.v b/test_regress/t/t_for_count.v index 97a2bbaee..ad30094d9 100644 --- a/test_regress/t/t_for_count.v +++ b/test_regress/t/t_for_count.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_for_disable_dot.py b/test_regress/t/t_for_disable_dot.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_for_disable_dot.py +++ b/test_regress/t/t_for_disable_dot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_for_disable_dot.v b/test_regress/t/t_for_disable_dot.v index f42f72e6c..fe51ef5a8 100644 --- a/test_regress/t/t_for_disable_dot.v +++ b/test_regress/t/t_for_disable_dot.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_for_funcbound.py b/test_regress/t/t_for_funcbound.py index f4b1881d1..ae9e9b886 100755 --- a/test_regress/t/t_for_funcbound.py +++ b/test_regress/t/t_for_funcbound.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_for_funcbound.v b/test_regress/t/t_for_funcbound.v index 91df6403b..992aa4f60 100644 --- a/test_regress/t/t_for_funcbound.v +++ b/test_regress/t/t_for_funcbound.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_for_init_bug.py b/test_regress/t/t_for_init_bug.py index 3aafd524c..f8083269e 100755 --- a/test_regress/t/t_for_init_bug.py +++ b/test_regress/t/t_for_init_bug.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_for_init_bug.v b/test_regress/t/t_for_init_bug.v index e638ffaac..27da2447f 100644 --- a/test_regress/t/t_for_init_bug.v +++ b/test_regress/t/t_for_init_bug.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_for_local.py b/test_regress/t/t_for_local.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_for_local.py +++ b/test_regress/t/t_for_local.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_for_local.v b/test_regress/t/t_for_local.v index 44d8b1359..44013f363 100644 --- a/test_regress/t/t_for_local.v +++ b/test_regress/t/t_for_local.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_for_loop.py b/test_regress/t/t_for_loop.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_for_loop.py +++ b/test_regress/t/t_for_loop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_for_loop.v b/test_regress/t/t_for_loop.v index 8569e0b0f..2f7c81088 100644 --- a/test_regress/t/t_for_loop.v +++ b/test_regress/t/t_for_loop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_force.py b/test_regress/t/t_force.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_force.py +++ b/test_regress/t/t_force.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force.v b/test_regress/t/t_force.v index fdcd0103b..0112a7c8a 100644 --- a/test_regress/t/t_force.v +++ b/test_regress/t/t_force.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_assign.py b/test_regress/t/t_force_assign.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_force_assign.py +++ b/test_regress/t/t_force_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_assign.v b/test_regress/t/t_force_assign.v index 7b3724dd5..a689c9008 100644 --- a/test_regress/t/t_force_assign.v +++ b/test_regress/t/t_force_assign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_force_bad_rw.py b/test_regress/t/t_force_bad_rw.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_force_bad_rw.py +++ b/test_regress/t/t_force_bad_rw.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_bad_rw.v b/test_regress/t/t_force_bad_rw.v index ffc7cf31c..b9259fb07 100644 --- a/test_regress/t/t_force_bad_rw.v +++ b/test_regress/t/t_force_bad_rw.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_force_chained.py b/test_regress/t/t_force_chained.py index 8084f4e71..e9f4a44c9 100755 --- a/test_regress/t/t_force_chained.py +++ b/test_regress/t/t_force_chained.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_chained.v b/test_regress/t/t_force_chained.v index e153980d5..c046aa8f4 100644 --- a/test_regress/t/t_force_chained.v +++ b/test_regress/t/t_force_chained.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_complex_sel_unsup.py b/test_regress/t/t_force_complex_sel_unsup.py index efe8cc01c..382ad0d44 100755 --- a/test_regress/t/t_force_complex_sel_unsup.py +++ b/test_regress/t/t_force_complex_sel_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_complex_sel_unsup.v b/test_regress/t/t_force_complex_sel_unsup.v index cefad335c..5822202c8 100644 --- a/test_regress/t/t_force_complex_sel_unsup.v +++ b/test_regress/t/t_force_complex_sel_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_func.py b/test_regress/t/t_force_func.py index 8084f4e71..e9f4a44c9 100755 --- a/test_regress/t/t_force_func.py +++ b/test_regress/t/t_force_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_func.v b/test_regress/t/t_force_func.v index a09453610..e61404763 100644 --- a/test_regress/t/t_force_func.v +++ b/test_regress/t/t_force_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_immediate_release.py b/test_regress/t/t_force_immediate_release.py index aa5dacc93..3c6aa8922 100755 --- a/test_regress/t/t_force_immediate_release.py +++ b/test_regress/t/t_force_immediate_release.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_immediate_release.v b/test_regress/t/t_force_immediate_release.v index 0debeeb65..959c920e5 100644 --- a/test_regress/t/t_force_immediate_release.v +++ b/test_regress/t/t_force_immediate_release.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_initial.py b/test_regress/t/t_force_initial.py index aa5dacc93..3c6aa8922 100755 --- a/test_regress/t/t_force_initial.py +++ b/test_regress/t/t_force_initial.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_initial.v b/test_regress/t/t_force_initial.v index 93f52c25c..bd25714ab 100644 --- a/test_regress/t/t_force_initial.v +++ b/test_regress/t/t_force_initial.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_input_assign_bad.py b/test_regress/t/t_force_input_assign_bad.py index d8bbae00a..7206b3e2f 100755 --- a/test_regress/t/t_force_input_assign_bad.py +++ b/test_regress/t/t_force_input_assign_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_input_assign_bad.v b/test_regress/t/t_force_input_assign_bad.v index 380dc433d..4635ca000 100644 --- a/test_regress/t/t_force_input_assign_bad.v +++ b/test_regress/t/t_force_input_assign_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module sub(input [1:0] i); diff --git a/test_regress/t/t_force_mid.cpp b/test_regress/t/t_force_mid.cpp index ca91e6179..162da8aae 100644 --- a/test_regress/t/t_force_mid.cpp +++ b/test_regress/t/t_force_mid.cpp @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Test defines diff --git a/test_regress/t/t_force_mid.py b/test_regress/t/t_force_mid.py index f37ad07c8..b6662862a 100755 --- a/test_regress/t/t_force_mid.py +++ b/test_regress/t/t_force_mid.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_mid.v b/test_regress/t/t_force_mid.v index ce9d67435..24209fab3 100644 --- a/test_regress/t/t_force_mid.v +++ b/test_regress/t/t_force_mid.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_multi.py b/test_regress/t/t_force_multi.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_force_multi.py +++ b/test_regress/t/t_force_multi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_multi.v b/test_regress/t/t_force_multi.v index 5ab3a10ce..9445577bf 100644 --- a/test_regress/t/t_force_multi.v +++ b/test_regress/t/t_force_multi.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_port_inline.py b/test_regress/t/t_force_port_inline.py index 587a5d18f..11549269c 100755 --- a/test_regress/t/t_force_port_inline.py +++ b/test_regress/t/t_force_port_inline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_port_inline.v b/test_regress/t/t_force_port_inline.v index 8be1995c6..cb5eee2b3 100644 --- a/test_regress/t/t_force_port_inline.v +++ b/test_regress/t/t_force_port_inline.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_readwrite.py b/test_regress/t/t_force_readwrite.py index aa5dacc93..3c6aa8922 100755 --- a/test_regress/t/t_force_readwrite.py +++ b/test_regress/t/t_force_readwrite.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_readwrite.v b/test_regress/t/t_force_readwrite.v index 3272b9e01..1382e7cc9 100644 --- a/test_regress/t/t_force_readwrite.v +++ b/test_regress/t/t_force_readwrite.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_force_readwrite_unsup.out b/test_regress/t/t_force_readwrite_unsup.out index a7423e077..e8f793171 100644 --- a/test_regress/t/t_force_readwrite_unsup.out +++ b/test_regress/t/t_force_readwrite_unsup.out @@ -1,8 +1,8 @@ -%Error-UNSUPPORTED: t/t_force_readwrite_unsup.v:25:18: Unsupported: Signals used via read-write reference cannot be forced - 25 | cls.take_ref(a); +%Error-UNSUPPORTED: t/t_force_readwrite_unsup.v:19:18: Unsupported: Signals used via read-write reference cannot be forced + 19 | cls.take_ref(a); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_force_readwrite_unsup.v:26:18: Unsupported: Signals used via read-write reference cannot be forced - 26 | cls.take_ref(b); +%Error-UNSUPPORTED: t/t_force_readwrite_unsup.v:20:18: Unsupported: Signals used via read-write reference cannot be forced + 20 | cls.take_ref(b); | ^ %Error: Exiting due to diff --git a/test_regress/t/t_force_readwrite_unsup.py b/test_regress/t/t_force_readwrite_unsup.py index efe8cc01c..382ad0d44 100755 --- a/test_regress/t/t_force_readwrite_unsup.py +++ b/test_regress/t/t_force_readwrite_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_readwrite_unsup.v b/test_regress/t/t_force_readwrite_unsup.v index 11bc3ce8a..799938d4a 100644 --- a/test_regress/t/t_force_readwrite_unsup.v +++ b/test_regress/t/t_force_readwrite_unsup.v @@ -1,13 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. -// SPDX-License-Identifier: CC0-1.0 - -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_force_release.py b/test_regress/t/t_force_release.py index 8084f4e71..e9f4a44c9 100755 --- a/test_regress/t/t_force_release.py +++ b/test_regress/t/t_force_release.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_release.v b/test_regress/t/t_force_release.v index 7dbff39c2..02908831d 100644 --- a/test_regress/t/t_force_release.v +++ b/test_regress/t/t_force_release.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_release_net.py b/test_regress/t/t_force_release_net.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_force_release_net.py +++ b/test_regress/t/t_force_release_net.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_release_net.v b/test_regress/t/t_force_release_net.v index 6bf47e073..4a7b71bce 100644 --- a/test_regress/t/t_force_release_net.v +++ b/test_regress/t/t_force_release_net.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_release_net_reverse.py b/test_regress/t/t_force_release_net_reverse.py index eee5aeb88..e45d4e931 100755 --- a/test_regress/t/t_force_release_net_reverse.py +++ b/test_regress/t/t_force_release_net_reverse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_release_net_trace.py b/test_regress/t/t_force_release_net_trace.py index 5e40d1a78..a26f72174 100755 --- a/test_regress/t/t_force_release_net_trace.py +++ b/test_regress/t/t_force_release_net_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_release_var.py b/test_regress/t/t_force_release_var.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_force_release_var.py +++ b/test_regress/t/t_force_release_var.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_release_var.v b/test_regress/t/t_force_release_var.v index 0790cc752..b98cc2608 100644 --- a/test_regress/t/t_force_release_var.v +++ b/test_regress/t/t_force_release_var.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_release_var_reverse.py b/test_regress/t/t_force_release_var_reverse.py index 624ccbc3b..d947b7f75 100755 --- a/test_regress/t/t_force_release_var_reverse.py +++ b/test_regress/t/t_force_release_var_reverse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_release_var_trace.py b/test_regress/t/t_force_release_var_trace.py index e58afb2bb..7d61c1978 100755 --- a/test_regress/t/t_force_release_var_trace.py +++ b/test_regress/t/t_force_release_var_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_rhs_ref.py b/test_regress/t/t_force_rhs_ref.py index aa5dacc93..3c6aa8922 100755 --- a/test_regress/t/t_force_rhs_ref.py +++ b/test_regress/t/t_force_rhs_ref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_rhs_ref.v b/test_regress/t/t_force_rhs_ref.v index 069adb0cf..b3be1e91b 100644 --- a/test_regress/t/t_force_rhs_ref.v +++ b/test_regress/t/t_force_rhs_ref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_rhs_ref_multi_lhs.py b/test_regress/t/t_force_rhs_ref_multi_lhs.py index aa5dacc93..3c6aa8922 100755 --- a/test_regress/t/t_force_rhs_ref_multi_lhs.py +++ b/test_regress/t/t_force_rhs_ref_multi_lhs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_rhs_ref_multi_lhs.v b/test_regress/t/t_force_rhs_ref_multi_lhs.v index 15fc1f711..ee73f478c 100644 --- a/test_regress/t/t_force_rhs_ref_multi_lhs.v +++ b/test_regress/t/t_force_rhs_ref_multi_lhs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_rhs_ref_multiple.py b/test_regress/t/t_force_rhs_ref_multiple.py index aa5dacc93..3c6aa8922 100755 --- a/test_regress/t/t_force_rhs_ref_multiple.py +++ b/test_regress/t/t_force_rhs_ref_multiple.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_rhs_ref_multiple.v b/test_regress/t/t_force_rhs_ref_multiple.v index afc2c390d..01736d068 100644 --- a/test_regress/t/t_force_rhs_ref_multiple.v +++ b/test_regress/t/t_force_rhs_ref_multiple.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_select_bad.py b/test_regress/t/t_force_select_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_force_select_bad.py +++ b/test_regress/t/t_force_select_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_select_bad.v b/test_regress/t/t_force_select_bad.v index 5b5bdb725..b9c2e29c7 100644 --- a/test_regress/t/t_force_select_bad.v +++ b/test_regress/t/t_force_select_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_force_struct_partial.py b/test_regress/t/t_force_struct_partial.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_force_struct_partial.py +++ b/test_regress/t/t_force_struct_partial.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_struct_partial.v b/test_regress/t/t_force_struct_partial.v index 7e4d452cf..a2e8f4762 100644 --- a/test_regress/t/t_force_struct_partial.v +++ b/test_regress/t/t_force_struct_partial.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_subnet.py b/test_regress/t/t_force_subnet.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_force_subnet.py +++ b/test_regress/t/t_force_subnet.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_subnet.v b/test_regress/t/t_force_subnet.v index 893b95096..1b3be4fc7 100644 --- a/test_regress/t/t_force_subnet.v +++ b/test_regress/t/t_force_subnet.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_subvar.py b/test_regress/t/t_force_subvar.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_force_subvar.py +++ b/test_regress/t/t_force_subvar.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_subvar.v b/test_regress/t/t_force_subvar.v index 21ebd199e..a53802be8 100644 --- a/test_regress/t/t_force_subvar.v +++ b/test_regress/t/t_force_subvar.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_tri.py b/test_regress/t/t_force_tri.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_force_tri.py +++ b/test_regress/t/t_force_tri.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_tri.v b/test_regress/t/t_force_tri.v index 517a4482f..bf6c26dc8 100644 --- a/test_regress/t/t_force_tri.v +++ b/test_regress/t/t_force_tri.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_unpacked.py b/test_regress/t/t_force_unpacked.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_force_unpacked.py +++ b/test_regress/t/t_force_unpacked.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_unpacked.v b/test_regress/t/t_force_unpacked.v index 1304bbbb4..e942d8523 100644 --- a/test_regress/t/t_force_unpacked.v +++ b/test_regress/t/t_force_unpacked.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_force_unpacked_struct.py b/test_regress/t/t_force_unpacked_struct.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_force_unpacked_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_unpacked_struct.v b/test_regress/t/t_force_unpacked_struct.v new file mode 100644 index 000000000..5aa2b28be --- /dev/null +++ b/test_regress/t/t_force_unpacked_struct.v @@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t ( + input clk +); + + integer cyc = 0; + + typedef struct { + int x; + logic y; + int arr[5]; + } struct_t; + + struct_t s_array[3]; + struct_t my_struct; + + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + s_array[1].x = 1; + s_array[1].arr[2] = 1; + my_struct.x <= 1; + end + else if (cyc == 1) begin + `checkh(s_array[1].x, 1); + `checkh(s_array[1].arr[2], 1); + `checkh(my_struct.x, 1); + end + else if (cyc == 2) begin + force s_array[1].x = 0; + force s_array[1].arr[2] = 2; + force my_struct.x = 0; + end + else if (cyc == 3) begin + `checkh(s_array[1].x, 0); + s_array[1].x = 1; + `checkh(s_array[1].arr[2], 2); + s_array[1].arr[2] = 3; + `checkh(my_struct.x, 0); + my_struct.x <= 1; + end + else if (cyc == 4) begin + `checkh(s_array[1].x, 0); + `checkh(s_array[1].arr[2], 2); + `checkh(my_struct.x, 0); + end + else if (cyc == 5) begin + release s_array[1].x; + release s_array[1].arr[2]; + release my_struct.x; + end + else if (cyc == 6) begin + `checkh(s_array[1].x, 0); + s_array[1].x = 1; + `checkh(s_array[1].arr[2], 2); + s_array[1].arr[2] = 4; + `checkh(my_struct.x, 0); + my_struct.x <= 1; + end + else if (cyc == 7) begin + `checkh(s_array[1].x, 1); + `checkh(s_array[1].arr[2], 4); + `checkh(my_struct.x, 1); + end + else if (cyc == 8) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_force_unpacked_unsup.out b/test_regress/t/t_force_unpacked_unsup.out index a770c9520..89b68ef55 100644 --- a/test_regress/t/t_force_unpacked_unsup.out +++ b/test_regress/t/t_force_unpacked_unsup.out @@ -1,17 +1,8 @@ -%Error-UNSUPPORTED: t/t_force_unpacked_unsup.v:23:8: Unsupported: Force of unpacked array variable with elements of complex data type - 23 | real r_array[2]; - | ^~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_force_unpacked_unsup.v:22:7: Unsupported: Force of unpacked array variable with >= 1000 elements +%Error-UNSUPPORTED: t/t_force_unpacked_unsup.v:22:7: Unsupported: Force of variable with >= 1000 unpacked elements 22 | bit big_array[40][40][40]; | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_force_unpacked_unsup.v:21:12: Unsupported: Force of unpacked array variable with >= 1000 elements + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_force_unpacked_unsup.v:21:12: Unsupported: Force of variable with >= 1000 unpacked elements 21 | struct_t s_array[3000]; | ^~~~~~~ -%Error-UNSUPPORTED: t/t_force_unpacked_unsup.v:21:12: Unsupported: Force of unpacked array variable with elements of complex data type - 21 | struct_t s_array[3000]; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_force_unpacked_unsup.v:24:12: Unsupported: Force of unpacked struct / union variable - 24 | struct_t my_struct; - | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_force_unpacked_unsup.py b/test_regress/t/t_force_unpacked_unsup.py index efe8cc01c..382ad0d44 100755 --- a/test_regress/t/t_force_unpacked_unsup.py +++ b/test_regress/t/t_force_unpacked_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_force_unpacked_unsup.v b/test_regress/t/t_force_unpacked_unsup.v index b98036d03..27562ed45 100644 --- a/test_regress/t/t_force_unpacked_unsup.v +++ b/test_regress/t/t_force_unpacked_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off @@ -21,7 +21,6 @@ module t ( struct_t s_array[3000]; bit big_array[40][40][40]; real r_array[2]; - struct_t my_struct; // Test loop always @(posedge clk) begin @@ -30,19 +29,16 @@ module t ( r_array[0] <= 1; big_array[1][2][3] <= 1; s_array[1].x <= 1; - my_struct.x <= 1; end else if (cyc == 1) begin `checkr(r_array[0], 1); `checkr(big_array[1][2][3], 1); `checkh(s_array[1].x, 1); - `checkh(my_struct.x, 1); end else if (cyc == 2) begin force r_array[0] = 0; force big_array[1][2][3] = 0; force s_array[1].x = 0; - force my_struct.x = 0; end else if (cyc == 3) begin `checkr(r_array[0], 0); @@ -51,20 +47,16 @@ module t ( big_array[1][2][3] <= 1; `checkh(s_array[1].x, 0); s_array[1].x <= 1; - `checkh(my_struct.x, 0); - my_struct.x <= 1; end else if (cyc == 4) begin `checkr(r_array[0], 0); `checkr(big_array[1][2][3], 0); `checkh(s_array[1].x, 0); - `checkh(my_struct.x, 0); end else if (cyc == 5) begin release r_array[0]; release big_array[1][2][3]; release s_array[1].x; - release my_struct.x; end else if (cyc == 6) begin `checkr(r_array[0], 0); @@ -73,14 +65,11 @@ module t ( big_array[1][2][3] <= 1; `checkh(s_array[1].x, 0); s_array[1].x <= 1; - `checkh(my_struct.x, 0); - my_struct.x <= 1; end else if (cyc == 7) begin `checkr(r_array[0], 1); `checkr(big_array[1][2][3], 1); `checkh(s_array[1].x, 1); - `checkh(my_struct.x, 1); end else if (cyc == 8) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_forceable_net.cpp b/test_regress/t/t_forceable_net.cpp index 7830e52f0..d6a556468 100644 --- a/test_regress/t/t_forceable_net.cpp +++ b/test_regress/t/t_forceable_net.cpp @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: CC0-1.0 #include "verilatedos.h" diff --git a/test_regress/t/t_forceable_net.v b/test_regress/t/t_forceable_net.v index ba18adc2c..910551852 100644 --- a/test_regress/t/t_forceable_net.v +++ b/test_regress/t/t_forceable_net.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_forceable_net.vlt b/test_regress/t/t_forceable_net.vlt index e551de233..77d6b2f9e 100644 --- a/test_regress/t/t_forceable_net.vlt +++ b/test_regress/t/t_forceable_net.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_forceable_net_cmt.py b/test_regress/t/t_forceable_net_cmt.py index 041bb0c49..6af4a2030 100755 --- a/test_regress/t/t_forceable_net_cmt.py +++ b/test_regress/t/t_forceable_net_cmt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_forceable_net_cmt_trace.py b/test_regress/t/t_forceable_net_cmt_trace.py index 50e909840..4a6c4e73a 100755 --- a/test_regress/t/t_forceable_net_cmt_trace.py +++ b/test_regress/t/t_forceable_net_cmt_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_forceable_net_vlt.py b/test_regress/t/t_forceable_net_vlt.py index 5d9d78291..6d2340766 100755 --- a/test_regress/t/t_forceable_net_vlt.py +++ b/test_regress/t/t_forceable_net_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_forceable_net_vlt_trace.py b/test_regress/t/t_forceable_net_vlt_trace.py index f268112b8..2dbbaadd9 100755 --- a/test_regress/t/t_forceable_net_vlt_trace.py +++ b/test_regress/t/t_forceable_net_vlt_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_forceable_public_flat.py b/test_regress/t/t_forceable_public_flat.py index 065390643..f18943111 100755 --- a/test_regress/t/t_forceable_public_flat.py +++ b/test_regress/t/t_forceable_public_flat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_forceable_public_flat.v b/test_regress/t/t_forceable_public_flat.v index 220aa150a..e5b842be6 100644 --- a/test_regress/t/t_forceable_public_flat.v +++ b/test_regress/t/t_forceable_public_flat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_forceable_string_bad.out b/test_regress/t/t_forceable_string_bad.out new file mode 100644 index 000000000..6735c1393 --- /dev/null +++ b/test_regress/t/t_forceable_string_bad.out @@ -0,0 +1,9 @@ +%Error: t/t_forceable_string_bad.v:8:10: Forcing strings is not permitted: t__DOT__str + 8 | string str /*verilator forceable*/; + | ^~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error-UNSUPPORTED: t/t_forceable_string_bad.v:8:10: Forcing variable of unsupported type: BASICDTYPE 'string' + 8 | string str /*verilator forceable*/; + | ^~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_forceable_string_bad.py b/test_regress/t/t_forceable_string_bad.py new file mode 100755 index 000000000..4cebd5d8e --- /dev/null +++ b/test_regress/t/t_forceable_string_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_forceable_string_bad.v b/test_regress/t/t_forceable_string_bad.v new file mode 100644 index 000000000..baadb84ce --- /dev/null +++ b/test_regress/t/t_forceable_string_bad.v @@ -0,0 +1,9 @@ +// ====================================================================== +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Christian Hecken +// SPDX-License-Identifier: CC0-1.0 +// ====================================================================== + +module t; + string str /*verilator forceable*/; +endmodule diff --git a/test_regress/t/t_forceable_unpacked_bad.out b/test_regress/t/t_forceable_unpacked_bad.out new file mode 100644 index 000000000..cdbd0181e --- /dev/null +++ b/test_regress/t/t_forceable_unpacked_bad.out @@ -0,0 +1,5 @@ +%Error-UNSUPPORTED: t/t_forceable_unpacked_bad.v:8:9: Unsupported: Forcing unpacked arrays: t__DOT__unpacked + 8 | logic unpacked[1] /*verilator forceable*/; + | ^~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_forceable_unpacked_bad.py b/test_regress/t/t_forceable_unpacked_bad.py new file mode 100755 index 000000000..4cebd5d8e --- /dev/null +++ b/test_regress/t/t_forceable_unpacked_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_forceable_unpacked_bad.v b/test_regress/t/t_forceable_unpacked_bad.v new file mode 100644 index 000000000..d48cc7e51 --- /dev/null +++ b/test_regress/t/t_forceable_unpacked_bad.v @@ -0,0 +1,9 @@ +// ====================================================================== +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Christian Hecken +// SPDX-License-Identifier: CC0-1.0 +// ====================================================================== + +module t; + logic unpacked[1] /*verilator forceable*/; +endmodule diff --git a/test_regress/t/t_forceable_var.cpp b/test_regress/t/t_forceable_var.cpp index f95b1c27c..60394d453 100644 --- a/test_regress/t/t_forceable_var.cpp +++ b/test_regress/t/t_forceable_var.cpp @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: CC0-1.0 #include "verilatedos.h" diff --git a/test_regress/t/t_forceable_var.v b/test_regress/t/t_forceable_var.v index 4079780e8..9423c942d 100644 --- a/test_regress/t/t_forceable_var.v +++ b/test_regress/t/t_forceable_var.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_forceable_var.vlt b/test_regress/t/t_forceable_var.vlt index c64f48200..70c62c881 100644 --- a/test_regress/t/t_forceable_var.vlt +++ b/test_regress/t/t_forceable_var.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_forceable_var_cmt.py b/test_regress/t/t_forceable_var_cmt.py index c79bd38ef..260ae98f4 100755 --- a/test_regress/t/t_forceable_var_cmt.py +++ b/test_regress/t/t_forceable_var_cmt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_forceable_var_cmt_trace.py b/test_regress/t/t_forceable_var_cmt_trace.py index 47c930538..a551105de 100755 --- a/test_regress/t/t_forceable_var_cmt_trace.py +++ b/test_regress/t/t_forceable_var_cmt_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_forceable_var_vlt.py b/test_regress/t/t_forceable_var_vlt.py index 83033dff9..db3e6fb03 100755 --- a/test_regress/t/t_forceable_var_vlt.py +++ b/test_regress/t/t_forceable_var_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_forceable_var_vlt_trace.py b/test_regress/t/t_forceable_var_vlt_trace.py index 569ee7f09..1ae5dec46 100755 --- a/test_regress/t/t_forceable_var_vlt_trace.py +++ b/test_regress/t/t_forceable_var_vlt_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach.py b/test_regress/t/t_foreach.py index 7a4bc150c..6a5a6175f 100755 --- a/test_regress/t/t_foreach.py +++ b/test_regress/t/t_foreach.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach.v b/test_regress/t/t_foreach.v index f9a700064..4020752bc 100644 --- a/test_regress/t/t_foreach.v +++ b/test_regress/t/t_foreach.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_foreach_array.py b/test_regress/t/t_foreach_array.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_foreach_array.py +++ b/test_regress/t/t_foreach_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_array.v b/test_regress/t/t_foreach_array.v old mode 100755 new mode 100644 index 2f4297c14..43e219448 --- a/test_regress/t/t_foreach_array.v +++ b/test_regress/t/t_foreach_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 module t_foreach_array; diff --git a/test_regress/t/t_foreach_bad.py b/test_regress/t/t_foreach_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_foreach_bad.py +++ b/test_regress/t/t_foreach_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_bad.v b/test_regress/t/t_foreach_bad.v index 971bf6c94..b2cd9e93e 100644 --- a/test_regress/t/t_foreach_bad.v +++ b/test_regress/t/t_foreach_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_foreach_blkname.py b/test_regress/t/t_foreach_blkname.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_foreach_blkname.py +++ b/test_regress/t/t_foreach_blkname.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_blkname.v b/test_regress/t/t_foreach_blkname.v index 3eceb8a3c..659c41bec 100644 --- a/test_regress/t/t_foreach_blkname.v +++ b/test_regress/t/t_foreach_blkname.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_foreach_class.py b/test_regress/t/t_foreach_class.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_foreach_class.py +++ b/test_regress/t/t_foreach_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_class.v b/test_regress/t/t_foreach_class.v index 7485c8c0f..13f3b61a1 100644 --- a/test_regress/t/t_foreach_class.v +++ b/test_regress/t/t_foreach_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_foreach_const.py b/test_regress/t/t_foreach_const.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_foreach_const.py +++ b/test_regress/t/t_foreach_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_const.v b/test_regress/t/t_foreach_const.v index 29cf8084b..cd8144c98 100644 --- a/test_regress/t/t_foreach_const.v +++ b/test_regress/t/t_foreach_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_foreach_iface.py b/test_regress/t/t_foreach_iface.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_foreach_iface.py +++ b/test_regress/t/t_foreach_iface.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_iface.v b/test_regress/t/t_foreach_iface.v index 0412c6821..7f7146ef2 100644 --- a/test_regress/t/t_foreach_iface.v +++ b/test_regress/t/t_foreach_iface.v @@ -1,12 +1,12 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Pawel Jewstafjew (Pawel.Jewstafjew@gmail.com). +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2022 Pawel Jewstafjew // SPDX-License-Identifier: CC0-1.0 interface Iface (input bit [31:0] regs [1]); initial begin - string instance_path = $sformatf("%m"); + automatic string instance_path = $sformatf("%m"); $display("Iface path %s\n", instance_path); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_foreach_nested.py b/test_regress/t/t_foreach_nested.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_foreach_nested.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_foreach_nested.v b/test_regress/t/t_foreach_nested.v new file mode 100644 index 000000000..9afa6e957 --- /dev/null +++ b/test_regress/t/t_foreach_nested.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +typedef struct {int x[9][9];} Foo; + +class Bar; + Foo foo; + + function automatic void test(); + foreach(this.foo.x[i]) + foreach(this.foo.x[i][j]) + this.foo.x[i][j] = i * j; + for (int i = 0; i < 9; i++) + for (int j = 0; j < 9; j++) + if (this.foo.x[i][j] != i * j) $stop; + endfunction +endclass + +module t; + initial begin + automatic Bar b = new; + b.test; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_foreach_nindex_bad.py b/test_regress/t/t_foreach_nindex_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_foreach_nindex_bad.py +++ b/test_regress/t/t_foreach_nindex_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_nindex_bad.v b/test_regress/t/t_foreach_nindex_bad.v index 125b8ff26..ee1a67340 100644 --- a/test_regress/t/t_foreach_nindex_bad.v +++ b/test_regress/t/t_foreach_nindex_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_foreach_noivar.py b/test_regress/t/t_foreach_noivar.py index 53f0d4385..865433d95 100755 --- a/test_regress/t/t_foreach_noivar.py +++ b/test_regress/t/t_foreach_noivar.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_noivar.v b/test_regress/t/t_foreach_noivar.v index 7f5606605..e722fcf18 100644 --- a/test_regress/t/t_foreach_noivar.v +++ b/test_regress/t/t_foreach_noivar.v @@ -1,18 +1,21 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on module t; reg [63:0] sum; // Checked not in objects reg [2:1][4:3] array[5:6][7:8]; + bit [3:2][2:1] array2[5:4][2]; + string did; initial begin sum = 0; @@ -27,6 +30,12 @@ module t; end `checkh(sum, 0); + foreach (array2[i, j,, l]) begin + did = {did, $sformatf("; %0d,%0d,,%0d", i, j, l)}; + end + `checks(did, "; 5,0,,2; 5,0,,1; 5,1,,2; 5,1,,1; 4,0,,2; 4,0,,1; 4,1,,2; 4,1,,1"); + $finish; + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_foreach_noivar_bad.out b/test_regress/t/t_foreach_noivar_bad.out index 0b411572c..75f0d451d 100644 --- a/test_regress/t/t_foreach_noivar_bad.out +++ b/test_regress/t/t_foreach_noivar_bad.out @@ -1,11 +1,11 @@ -%Warning-NOEFFECT: t/t_foreach_noivar.v:19:5: foreach with no loop variable has no effect +%Warning-NOEFFECT: t/t_foreach_noivar.v:22:5: foreach with no loop variable has no effect : ... note: In instance 't' - 19 | foreach (array[]) begin + 22 | foreach (array[]) begin | ^~~~~~~ ... For warning description see https://verilator.org/warn/NOEFFECT?v=latest ... Use "/* verilator lint_off NOEFFECT */" and lint_on around source to disable this message. -%Warning-NOEFFECT: t/t_foreach_noivar.v:25:5: foreach with no loop variable has no effect +%Warning-NOEFFECT: t/t_foreach_noivar.v:28:5: foreach with no loop variable has no effect : ... note: In instance 't' - 25 | foreach (array[,,]) begin + 28 | foreach (array[,,]) begin | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_foreach_noivar_bad.py b/test_regress/t/t_foreach_noivar_bad.py index 2101e3902..cfc73a4a4 100755 --- a/test_regress/t/t_foreach_noivar_bad.py +++ b/test_regress/t/t_foreach_noivar_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_sideeff_uvm.py b/test_regress/t/t_foreach_sideeff_uvm.py index 563b6fc6f..78ebab213 100755 --- a/test_regress/t/t_foreach_sideeff_uvm.py +++ b/test_regress/t/t_foreach_sideeff_uvm.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_sideeff_uvm.v b/test_regress/t/t_foreach_sideeff_uvm.v index c67b8e85c..298a5e427 100644 --- a/test_regress/t/t_foreach_sideeff_uvm.v +++ b/test_regress/t/t_foreach_sideeff_uvm.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_foreach_type_bad.py b/test_regress/t/t_foreach_type_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_foreach_type_bad.py +++ b/test_regress/t/t_foreach_type_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_foreach_type_bad.v b/test_regress/t/t_foreach_type_bad.v index 7623abb19..5a5abef15 100644 --- a/test_regress/t/t_foreach_type_bad.v +++ b/test_regress/t/t_foreach_type_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_fork.py b/test_regress/t/t_fork.py index bb6e45319..f1ea40d54 100755 --- a/test_regress/t/t_fork.py +++ b/test_regress/t/t_fork.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork.v b/test_regress/t/t_fork.v index c7b74933f..9759c2940 100644 --- a/test_regress/t/t_fork.v +++ b/test_regress/t/t_fork.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_bbox.py b/test_regress/t/t_fork_bbox.py index 0c1f1c71a..fd96137bc 100755 --- a/test_regress/t/t_fork_bbox.py +++ b/test_regress/t/t_fork_bbox.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_bbox.v b/test_regress/t/t_fork_bbox.v index 4920cb397..1a9fc9a95 100644 --- a/test_regress/t/t_fork_bbox.v +++ b/test_regress/t/t_fork_bbox.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_block_item_declaration.py b/test_regress/t/t_fork_block_item_declaration.py index c53b55262..4b9293add 100755 --- a/test_regress/t/t_fork_block_item_declaration.py +++ b/test_regress/t/t_fork_block_item_declaration.py @@ -1,17 +1,17 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--binary"]) +test.compile(verilator_flags2=["--binary", "--no-sched-zero-delay"]) test.execute() diff --git a/test_regress/t/t_fork_block_item_declaration.v b/test_regress/t/t_fork_block_item_declaration.v index 6f00d126e..79f996d63 100644 --- a/test_regress/t/t_fork_block_item_declaration.v +++ b/test_regress/t/t_fork_block_item_declaration.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 static int counts[10]; @@ -23,7 +23,7 @@ endclass module t(); initial begin - int desired_counts[10] = '{10{1}}; + automatic int desired_counts[10] = '{10{1}}; counts = '{10{0}}; Foo::do_something(); diff --git a/test_regress/t/t_fork_cfunc_finish.py b/test_regress/t/t_fork_cfunc_finish.py index 1c061c8c9..3a46a7545 100755 --- a/test_regress/t/t_fork_cfunc_finish.py +++ b/test_regress/t/t_fork_cfunc_finish.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_cfunc_finish.v b/test_regress/t/t_fork_cfunc_finish.v index 661718f14..e0d2dbcd4 100644 --- a/test_regress/t/t_fork_cfunc_finish.v +++ b/test_regress/t/t_fork_cfunc_finish.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_delay.py b/test_regress/t/t_fork_delay.py index 1c061c8c9..3a46a7545 100755 --- a/test_regress/t/t_fork_delay.py +++ b/test_regress/t/t_fork_delay.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_delay.v b/test_regress/t/t_fork_delay.v index fef847a6e..8897e0e7b 100644 --- a/test_regress/t/t_fork_delay.v +++ b/test_regress/t/t_fork_delay.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_delay_finish.py b/test_regress/t/t_fork_delay_finish.py index 1c061c8c9..3a46a7545 100755 --- a/test_regress/t/t_fork_delay_finish.py +++ b/test_regress/t/t_fork_delay_finish.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_delay_finish.v b/test_regress/t/t_fork_delay_finish.v index a36e09a02..65a046d04 100644 --- a/test_regress/t/t_fork_delay_finish.v +++ b/test_regress/t/t_fork_delay_finish.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_dynscope.py b/test_regress/t/t_fork_dynscope.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_fork_dynscope.py +++ b/test_regress/t/t_fork_dynscope.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_dynscope.v b/test_regress/t/t_fork_dynscope.v index e1264e238..64c36dfb1 100644 --- a/test_regress/t/t_fork_dynscope.v +++ b/test_regress/t/t_fork_dynscope.v @@ -1,51 +1,51 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; task do_something(int arg_v); int dynscope_var; int x; - dynscope_var = 0; + if (dynscope_var != 0) $stop; + dynscope_var = 10; + if (dynscope_var != 10) $stop; fork #10 begin x = 0; // Test capturing a variable that needs to be modified - $display("Incremented dynscope_var: %d", ++dynscope_var); - if (dynscope_var != 1) - $stop; + if (dynscope_var != 10) $stop; + $display("Incremented dynscope_var: %0d", ++dynscope_var); + if (dynscope_var != 11) $stop; // Check nested access fork #10 begin - $display("Incremented x: %d", ++x); - $display("Incremented dynscope_var: %d", ++dynscope_var); - if (dynscope_var != 2) - $stop; + $display("Incremented x: %0d", ++x); + $display("Incremented dynscope_var: %0d", ++dynscope_var); + if (dynscope_var != 12) $stop; end join_none end #10 begin // Same as the first check, but with an argument // (so it needs to be copied to the dynamic scope instead of being moved there) - $display("Incremented arg_v: %d", ++arg_v); - if (arg_v != 2) - $stop; + if (arg_v != 1) $stop; + $display("Incremented arg_v: %0d", ++arg_v); + if (arg_v != 2) $stop; end join_none // Check if regular access to arg_v has been substituted with access to its copy from // a dynamic scope - $display("Incremented arg_v: %d", ++arg_v); - if (arg_v != 1) - $stop; + $display("Incremented arg_v: %0d", ++arg_v); + if (arg_v != 1) $stop; endtask endclass -module t(); +module t; initial begin Foo foo; foo = new; diff --git a/test_regress/t/t_fork_dynscope_interface.py b/test_regress/t/t_fork_dynscope_interface.py index c1c09c48b..6ed2bc5c7 100755 --- a/test_regress/t/t_fork_dynscope_interface.py +++ b/test_regress/t/t_fork_dynscope_interface.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_dynscope_interface.v b/test_regress/t/t_fork_dynscope_interface.v index 59132d448..5f302f73d 100644 --- a/test_regress/t/t_fork_dynscope_interface.v +++ b/test_regress/t/t_fork_dynscope_interface.v @@ -1,21 +1,21 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - Iface ifc(); - rvlab_tests uut (.ifc); + Iface ifc (); + rvlab_tests uut (.ifc); - always begin - uut.test_idcode(); - end - initial begin - #1; - $write("*-* All Finished *-*\n"); - $finish; - end + always begin + uut.test_idcode(); + end + initial begin + #1; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule interface Iface; @@ -23,15 +23,16 @@ interface Iface; logic tdo; task tsk(output logic [31:0] data_o, input logic [31:0] data_i); - @(posedge tck); - data_o[$size(data_i)-1] <= tdo; + @(posedge tck); + data_o[$size(data_i)-1] <= tdo; endtask endinterface module rvlab_tests ( - Iface ifc); - task test_idcode(); - bit [31:0] idcode_read; - ifc.tsk(idcode_read, '0); - endtask + Iface ifc +); + task test_idcode(); + bit [31:0] idcode_read; + ifc.tsk(idcode_read, '0); + endtask endmodule diff --git a/test_regress/t/t_fork_dynscope_out.py b/test_regress/t/t_fork_dynscope_out.py index e555ab909..f478cb764 100755 --- a/test_regress/t/t_fork_dynscope_out.py +++ b/test_regress/t/t_fork_dynscope_out.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_dynscope_out.v b/test_regress/t/t_fork_dynscope_out.v index c4e25a014..ab1b3f8fd 100644 --- a/test_regress/t/t_fork_dynscope_out.v +++ b/test_regress/t/t_fork_dynscope_out.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_dynscope_unsup.py b/test_regress/t/t_fork_dynscope_unsup.py index efe8cc01c..382ad0d44 100755 --- a/test_regress/t/t_fork_dynscope_unsup.py +++ b/test_regress/t/t_fork_dynscope_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_dynscope_unsup.v b/test_regress/t/t_fork_dynscope_unsup.v index dd1e02c2e..893c44a8b 100644 --- a/test_regress/t/t_fork_dynscope_unsup.v +++ b/test_regress/t/t_fork_dynscope_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_finish.py b/test_regress/t/t_fork_finish.py index 1c061c8c9..3a46a7545 100755 --- a/test_regress/t/t_fork_finish.py +++ b/test_regress/t/t_fork_finish.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_finish.v b/test_regress/t/t_fork_finish.v index 3bb0a1193..a8d9172fc 100644 --- a/test_regress/t/t_fork_finish.v +++ b/test_regress/t/t_fork_finish.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_func2_bad.py b/test_regress/t/t_fork_func2_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_fork_func2_bad.py +++ b/test_regress/t/t_fork_func2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_func2_bad.v b/test_regress/t/t_fork_func2_bad.v index 5627dca5f..90242c1b8 100644 --- a/test_regress/t/t_fork_func2_bad.v +++ b/test_regress/t/t_fork_func2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_func_bad.py b/test_regress/t/t_fork_func_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_fork_func_bad.py +++ b/test_regress/t/t_fork_func_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_func_bad.v b/test_regress/t/t_fork_func_bad.v index 1ecede931..9ec53517a 100644 --- a/test_regress/t/t_fork_func_bad.v +++ b/test_regress/t/t_fork_func_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_initial.py b/test_regress/t/t_fork_initial.py index 8dbd20354..621c29dcc 100755 --- a/test_regress/t/t_fork_initial.py +++ b/test_regress/t/t_fork_initial.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_initial.v b/test_regress/t/t_fork_initial.v index ef6ed69b1..8bf3bee57 100644 --- a/test_regress/t/t_fork_initial.v +++ b/test_regress/t/t_fork_initial.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(); diff --git a/test_regress/t/t_fork_join_none_any_nested.py b/test_regress/t/t_fork_join_none_any_nested.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_fork_join_none_any_nested.py +++ b/test_regress/t/t_fork_join_none_any_nested.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_join_none_any_nested.v b/test_regress/t/t_fork_join_none_any_nested.v index 69f043e0c..6a0f99875 100644 --- a/test_regress/t/t_fork_join_none_any_nested.v +++ b/test_regress/t/t_fork_join_none_any_nested.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 event evt1, evt2, evt3; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules3.py b/test_regress/t/t_fork_join_none_capture.py similarity index 53% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules3.py rename to test_regress/t/t_fork_join_none_capture.py index c6e56559a..6fe7d000c 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules3.py +++ b/test_regress/t/t_fork_join_none_capture.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_join_none_capture.v b/test_regress/t/t_fork_join_none_capture.v new file mode 100644 index 000000000..5f4ecb464 --- /dev/null +++ b/test_regress/t/t_fork_join_none_capture.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +module test; + mailbox #(int) mbox; + initial begin + mbox = new(); + mbox.put(10); + mbox.put(30); + + repeat (2) begin + automatic int item; + mbox.get(item); + fork + begin + $display("got", item); + if (item == 10) $finish; + end + join_none + end + + #0; + $stop; + end +endmodule diff --git a/test_regress/t/t_fork_join_none_class_cap.py b/test_regress/t/t_fork_join_none_class_cap.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_fork_join_none_class_cap.py +++ b/test_regress/t/t_fork_join_none_class_cap.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_join_none_class_cap.v b/test_regress/t/t_fork_join_none_class_cap.v index 36ba60f03..49cd26392 100644 --- a/test_regress/t/t_fork_join_none_class_cap.v +++ b/test_regress/t/t_fork_join_none_class_cap.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 event evt1; diff --git a/test_regress/t/t_fork_join_none_inactive.out b/test_regress/t/t_fork_join_none_inactive.out new file mode 100644 index 000000000..536aaaf4e --- /dev/null +++ b/test_regress/t/t_fork_join_none_inactive.out @@ -0,0 +1,3 @@ +This should be first +This should be second +This should be last diff --git a/test_regress/t/t_fork_join_none_inactive.py b/test_regress/t/t_fork_join_none_inactive.py new file mode 100755 index 000000000..9aad707de --- /dev/null +++ b/test_regress/t/t_fork_join_none_inactive.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fork_join_none_inactive.v b/test_regress/t/t_fork_join_none_inactive.v new file mode 100644 index 000000000..053a840bc --- /dev/null +++ b/test_regress/t/t_fork_join_none_inactive.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro Ltd +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial + fork + #0 $write("This should be last\n"); + begin + fork + $write("This should be second\n"); + join_none + $write("This should be first\n"); + end + join_none +endmodule diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.py b/test_regress/t/t_fork_join_none_nested_triggered.py similarity index 53% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.py rename to test_regress/t/t_fork_join_none_nested_triggered.py index c6e56559a..6fe7d000c 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.py +++ b/test_regress/t/t_fork_join_none_nested_triggered.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_join_none_nested_triggered.v b/test_regress/t/t_fork_join_none_nested_triggered.v new file mode 100644 index 000000000..41039e68c --- /dev/null +++ b/test_regress/t/t_fork_join_none_nested_triggered.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro Ltd +// SPDX-License-Identifier: CC0-1.0 + +module test; + mailbox #(int) mbox; + initial begin + mbox = new(); + + fork + repeat (2) begin + int val; + mbox.get(val); + fork + fork + begin + $finish; + end + join_none + join_none + end + join_none + + mbox.put(1); + #1; + $stop; + end +endmodule diff --git a/test_regress/t/t_fork_join_none_stmt.py b/test_regress/t/t_fork_join_none_stmt.py new file mode 100755 index 000000000..4ee7f9e14 --- /dev/null +++ b/test_regress/t/t_fork_join_none_stmt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_join_none_stmt.v b/test_regress/t/t_fork_join_none_stmt.v new file mode 100644 index 000000000..82601cf93 --- /dev/null +++ b/test_regress/t/t_fork_join_none_stmt.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t; + + bit stmt2 = '0; + bit proc1 = '0; + + initial begin + $display("Statement 1"); + fork + begin + // The join_none implies that here there's effectively a: #0; + $display("Process 1"); + proc1 = '1; + `checkh(stmt2, 1'b1); + end + join_none + $display("Statement 2"); + stmt2 = '1; + `checkh(proc1, 1'b0); + + #1; + `checkh(proc1, 1'b1); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_fork_join_none_virtual.py b/test_regress/t/t_fork_join_none_virtual.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_fork_join_none_virtual.py +++ b/test_regress/t/t_fork_join_none_virtual.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_join_none_virtual.v b/test_regress/t/t_fork_join_none_virtual.v index 717f7707c..6a0df7c6a 100644 --- a/test_regress/t/t_fork_join_none_virtual.v +++ b/test_regress/t/t_fork_join_none_virtual.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 event evt1; diff --git a/test_regress/t/t_fork_join_none_waiters.py b/test_regress/t/t_fork_join_none_waiters.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_fork_join_none_waiters.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fork_join_none_waiters.v b/test_regress/t/t_fork_join_none_waiters.v new file mode 100644 index 000000000..bf39d1d0d --- /dev/null +++ b/test_regress/t/t_fork_join_none_waiters.v @@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro Ltd +// SPDX-License-Identifier: CC0-1.0 + +class events_holder; + event ev; +endclass + +module test; + events_holder m_events[int]; + int waiters_done = 0; + + initial begin + m_events[0] = new; + fork + begin + @(m_events[0].ev); + waiters_done++; + end + begin + @(m_events[0].ev); + waiters_done++; + end + join_none + #1; + ->m_events[0].ev; + + #1; + if (waiters_done == 2) $finish; + end + + initial #10000ns $stop; +endmodule diff --git a/test_regress/t/t_fork_jumpblock.py b/test_regress/t/t_fork_jumpblock.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_fork_jumpblock.py +++ b/test_regress/t/t_fork_jumpblock.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_jumpblock.v b/test_regress/t/t_fork_jumpblock.v index 13ef8e9f3..f4309f903 100644 --- a/test_regress/t/t_fork_jumpblock.v +++ b/test_regress/t/t_fork_jumpblock.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class bar; diff --git a/test_regress/t/t_fork_label.py b/test_regress/t/t_fork_label.py index 46560bc9c..346ef8602 100755 --- a/test_regress/t/t_fork_label.py +++ b/test_regress/t/t_fork_label.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_label.v b/test_regress/t/t_fork_label.v index 60552db4b..316ed630d 100644 --- a/test_regress/t/t_fork_label.v +++ b/test_regress/t/t_fork_label.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_label_timing.py b/test_regress/t/t_fork_label_timing.py index e7139372c..00c84e8d2 100755 --- a/test_regress/t/t_fork_label_timing.py +++ b/test_regress/t/t_fork_label_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_none_var.py b/test_regress/t/t_fork_none_var.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_fork_none_var.py +++ b/test_regress/t/t_fork_none_var.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_none_var.v b/test_regress/t/t_fork_none_var.v index 5c9085492..bbf2b5b6c 100644 --- a/test_regress/t/t_fork_none_var.v +++ b/test_regress/t/t_fork_none_var.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; @@ -10,7 +10,7 @@ module t; initial begin int i; - int n = 4; + automatic int n = 4; m_mask = 0; fork begin diff --git a/test_regress/t/t_fork_output_arg.py b/test_regress/t/t_fork_output_arg.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_fork_output_arg.py +++ b/test_regress/t/t_fork_output_arg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_output_arg.v b/test_regress/t/t_fork_output_arg.v index e5c5169e5..7c80d81d7 100644 --- a/test_regress/t/t_fork_output_arg.v +++ b/test_regress/t/t_fork_output_arg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_fork_port.py b/test_regress/t/t_fork_port.py index a1700c6d9..a36e184d4 100755 --- a/test_regress/t/t_fork_port.py +++ b/test_regress/t/t_fork_port.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_port.v b/test_regress/t/t_fork_port.v index f294278fd..96d169dfa 100644 --- a/test_regress/t/t_fork_port.v +++ b/test_regress/t/t_fork_port.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_repeat.py b/test_regress/t/t_fork_repeat.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_fork_repeat.py +++ b/test_regress/t/t_fork_repeat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_repeat.v b/test_regress/t/t_fork_repeat.v index 8eb5100d8..6f5fcc46c 100644 --- a/test_regress/t/t_fork_repeat.v +++ b/test_regress/t/t_fork_repeat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_repeat_reset.py b/test_regress/t/t_fork_repeat_reset.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_fork_repeat_reset.py +++ b/test_regress/t/t_fork_repeat_reset.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fork_repeat_reset.v b/test_regress/t/t_fork_repeat_reset.v index e24b67e9a..28a95c071 100644 --- a/test_regress/t/t_fork_repeat_reset.v +++ b/test_regress/t/t_fork_repeat_reset.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_fork_timing.py b/test_regress/t/t_fork_timing.py index 8c92975ff..8d0ca51d2 100755 --- a/test_regress/t/t_fork_timing.py +++ b/test_regress/t/t_fork_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fourstate_assign.py b/test_regress/t/t_fourstate_assign.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_fourstate_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_fourstate_assign.v b/test_regress/t/t_fourstate_assign.v new file mode 100644 index 000000000..c518b5bdb --- /dev/null +++ b/test_regress/t/t_fourstate_assign.v @@ -0,0 +1,41 @@ +// DESCRIPTION: Test for IEEE 1800-2023 6.22.2 - valid array assignments with matching state types +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + // 2-state arrays - assignment should work + bit [7:0] arr_2state_a[3:0]; + bit [7:0] arr_2state_b[3:0]; + + // 4-state arrays - assignment should work + logic [7:0] arr_4state_a[3:0]; + logic [7:0] arr_4state_b[3:0]; + + initial begin + // Initialize + arr_2state_a[0] = 8'h10; + arr_2state_a[1] = 8'h20; + arr_2state_a[2] = 8'h30; + arr_2state_a[3] = 8'h40; + + arr_4state_a[0] = 8'hA0; + arr_4state_a[1] = 8'hB0; + arr_4state_a[2] = 8'hC0; + arr_4state_a[3] = 8'hD0; + + // Valid assignments: same state types + arr_2state_b = arr_2state_a; // 2-state to 2-state: OK + arr_4state_b = arr_4state_a; // 4-state to 4-state: OK + + // Verify + if (arr_2state_b[0] !== 8'h10) $stop; + if (arr_2state_b[3] !== 8'h40) $stop; + if (arr_4state_b[0] !== 8'hA0) $stop; + if (arr_4state_b[3] !== 8'hD0) $stop; + + $write("*-* All Coverage *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_fourstate_assign_bad.out b/test_regress/t/t_fourstate_assign_bad.out new file mode 100644 index 000000000..a43b8027e --- /dev/null +++ b/test_regress/t/t_fourstate_assign_bad.out @@ -0,0 +1,8 @@ +%Error: t/t_fourstate_assign_bad.v:23:16: Assignment between 2-state and 4-state types requires equivalent element types (IEEE 1800-2023 6.22.2, 7.6) + : ... note: In instance 't' + : ... LHS type: 'bit[7:0]$[3:0]' (2-state) + : ... RHS type: 'logic[7:0]$[3:0]' (4-state) + 23 | arr_2state = arr_4state; + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_fourstate_assign_bad.py b/test_regress/t/t_fourstate_assign_bad.py new file mode 100755 index 000000000..38cf36b43 --- /dev/null +++ b/test_regress/t/t_fourstate_assign_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_fourstate_assign_bad.v b/test_regress/t/t_fourstate_assign_bad.v new file mode 100644 index 000000000..79cb1b92f --- /dev/null +++ b/test_regress/t/t_fourstate_assign_bad.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Test for IEEE 1800-2023 6.22.2 - 4-state to 2-state type equivalence +// This should produce a type error because bit and logic are not equivalent types +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + // IEEE 6.22.2: Packed arrays are equivalent if they contain the same number + // of total bits, are either all 2-state or all 4-state, and are either all + // signed or all unsigned. + + // 2-state array + bit [7:0] arr_2state[3:0]; + + // 4-state array (should not be assignment compatible for unpacked arrays) + logic [7:0] arr_4state[3:0]; + + initial begin + // Per IEEE 7.6: For unpacked arrays to be assignment compatible, + // the element types shall be equivalent. + // bit[7:0] and logic[7:0] are NOT equivalent (one is 2-state, one is 4-state) + arr_2state = arr_4state; + $write("*-* All Coverage *-*\n"); + $stop; + end +endmodule diff --git a/test_regress/t/t_func.py b/test_regress/t/t_func.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func.py +++ b/test_regress/t/t_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func.v b/test_regress/t/t_func.v index 7f9817703..1421c5ef1 100644 --- a/test_regress/t/t_func.v +++ b/test_regress/t/t_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_arg_complex.py b/test_regress/t/t_func_arg_complex.py index b9135448f..4292bd231 100755 --- a/test_regress/t/t_func_arg_complex.py +++ b/test_regress/t/t_func_arg_complex.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_arg_complex.v b/test_regress/t/t_func_arg_complex.v index a6c365678..7f44912ec 100644 --- a/test_regress/t/t_func_arg_complex.v +++ b/test_regress/t/t_func_arg_complex.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_func_automatic_clear.py b/test_regress/t/t_func_automatic_clear.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_func_automatic_clear.py +++ b/test_regress/t/t_func_automatic_clear.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_automatic_clear.v b/test_regress/t/t_func_automatic_clear.v index 5b1dd3ef1..512f8c529 100644 --- a/test_regress/t/t_func_automatic_clear.v +++ b/test_regress/t/t_func_automatic_clear.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test automatic function variables lifetime // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Augustin Fabre. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Augustin Fabre // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_func_bad.py b/test_regress/t/t_func_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_bad.py +++ b/test_regress/t/t_func_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_bad.v b/test_regress/t/t_func_bad.v index 835ab2b45..6e546f489 100644 --- a/test_regress/t/t_func_bad.v +++ b/test_regress/t/t_func_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_bad_width.py b/test_regress/t/t_func_bad_width.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_func_bad_width.py +++ b/test_regress/t/t_func_bad_width.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_bad_width.v b/test_regress/t/t_func_bad_width.v index 22d9af299..490b56341 100644 --- a/test_regress/t/t_func_bad_width.v +++ b/test_regress/t/t_func_bad_width.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_begin2.py b/test_regress/t/t_func_begin2.py index 93ef8a8f0..1ceba33c4 100755 --- a/test_regress/t/t_func_begin2.py +++ b/test_regress/t/t_func_begin2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_begin2.v b/test_regress/t/t_func_begin2.v index 57f1dc4a0..38d0a1283 100644 --- a/test_regress/t/t_func_begin2.v +++ b/test_regress/t/t_func_begin2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module init; diff --git a/test_regress/t/t_func_call_order.py b/test_regress/t/t_func_call_order.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_call_order.py +++ b/test_regress/t/t_func_call_order.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_call_order.v b/test_regress/t/t_func_call_order.v index 91866bb52..8df21f945 100644 --- a/test_regress/t/t_func_call_order.v +++ b/test_regress/t/t_func_call_order.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_func_call_super_arg.py b/test_regress/t/t_func_call_super_arg.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_func_call_super_arg.py +++ b/test_regress/t/t_func_call_super_arg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_call_super_arg.v b/test_regress/t/t_func_call_super_arg.v index 6c2af983c..2e0065931 100644 --- a/test_regress/t/t_func_call_super_arg.v +++ b/test_regress/t/t_func_call_super_arg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class base; @@ -23,6 +23,6 @@ endclass module t; initial begin - derived test = new; + automatic derived test = new; end endmodule diff --git a/test_regress/t/t_func_check.py b/test_regress/t/t_func_check.py index 629441927..af8b14903 100755 --- a/test_regress/t/t_func_check.py +++ b/test_regress/t/t_func_check.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_check.v b/test_regress/t/t_func_check.v index 28425e791..e593e39e0 100644 --- a/test_regress/t/t_func_check.v +++ b/test_regress/t/t_func_check.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH diff --git a/test_regress/t/t_func_complex.py b/test_regress/t/t_func_complex.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_complex.py +++ b/test_regress/t/t_func_complex.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_complex.v b/test_regress/t/t_func_complex.v index d249426b5..0489cf568 100644 --- a/test_regress/t/t_func_complex.v +++ b/test_regress/t/t_func_complex.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(); @@ -15,6 +15,22 @@ module t(); if (q.size() != 1) $stop; endfunction + // verilator lint_off NORETURN + function int get_noreturn(); +`ifdef TEST_NOINLINE + // verilator no_inline_task +`endif + endfunction + // verilator lint_on NORETURN + + function int get_uninit(); +`ifdef TEST_NOINLINE + // verilator no_inline_task +`endif + int uninit; + return get_uninit; + endfunction + function void queue_check_nref(q_t q); `ifdef TEST_NOINLINE // verilator no_inline_task @@ -50,6 +66,9 @@ module t(); iq = queue_ret(); if (iq[0] != 101) $stop; + if (get_noreturn() != 0) $stop; + if (get_uninit() != 0) $stop; + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_func_complex_noinl.py b/test_regress/t/t_func_complex_noinl.py index b5ec76840..b50a4cab1 100755 --- a/test_regress/t/t_func_complex_noinl.py +++ b/test_regress/t/t_func_complex_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 test.top_filename = "t/t_func_complex.v" diff --git a/test_regress/t/t_func_cond.py b/test_regress/t/t_func_cond.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_cond.py +++ b/test_regress/t/t_func_cond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_cond.v b/test_regress/t/t_func_cond.v index 16b664a77..e5cea95fd 100644 --- a/test_regress/t/t_func_cond.v +++ b/test_regress/t/t_func_cond.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_const.py b/test_regress/t/t_func_const.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_const.py +++ b/test_regress/t/t_func_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_const.v b/test_regress/t/t_func_const.v index d1abd415e..8ce636ef2 100644 --- a/test_regress/t/t_func_const.v +++ b/test_regress/t/t_func_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package testpackage; diff --git a/test_regress/t/t_func_const2_bad.py b/test_regress/t/t_func_const2_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_const2_bad.py +++ b/test_regress/t/t_func_const2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_const2_bad.v b/test_regress/t/t_func_const2_bad.v index f4515b317..5cabc03b5 100644 --- a/test_regress/t/t_func_const2_bad.v +++ b/test_regress/t/t_func_const2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 function integer f_add(input [31:0] a, input [31:0] b); diff --git a/test_regress/t/t_func_const3_bad.out b/test_regress/t/t_func_const3_bad.out index 6172af3b0..4c996d982 100644 --- a/test_regress/t/t_func_const3_bad.out +++ b/test_regress/t/t_func_const3_bad.out @@ -1,4 +1,4 @@ -%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:12:28: More than a 8k bit replication is probably wrong: 9000 +%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:12:28: Replication of more that --replication-limit 8192 is suspect: 9000 : ... note: In instance 't.b9k.c9' 12 | localparam SOMEP = {BITS{1'b0}}; | ^ diff --git a/test_regress/t/t_func_const3_bad.py b/test_regress/t/t_func_const3_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_func_const3_bad.py +++ b/test_regress/t/t_func_const3_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_const3_bad.v b/test_regress/t/t_func_const3_bad.v index 9d45b03a9..65a46a6c1 100644 --- a/test_regress/t/t_func_const3_bad.v +++ b/test_regress/t/t_func_const3_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module c9 diff --git a/test_regress/t/t_func_const_bad.py b/test_regress/t/t_func_const_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_const_bad.py +++ b/test_regress/t/t_func_const_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_const_bad.v b/test_regress/t/t_func_const_bad.v index 1ebe7c765..99e44d3b0 100644 --- a/test_regress/t/t_func_const_bad.v +++ b/test_regress/t/t_func_const_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_const_packed_array_bad.py b/test_regress/t/t_func_const_packed_array_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_const_packed_array_bad.py +++ b/test_regress/t/t_func_const_packed_array_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_const_packed_array_bad.v b/test_regress/t/t_func_const_packed_array_bad.v index 25fbc4988..07d7a7138 100644 --- a/test_regress/t/t_func_const_packed_array_bad.v +++ b/test_regress/t/t_func_const_packed_array_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_const_packed_struct_bad.py b/test_regress/t/t_func_const_packed_struct_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_const_packed_struct_bad.py +++ b/test_regress/t/t_func_const_packed_struct_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_const_packed_struct_bad.v b/test_regress/t/t_func_const_packed_struct_bad.v index 2ad2586ce..577e85cb6 100644 --- a/test_regress/t/t_func_const_packed_struct_bad.v +++ b/test_regress/t/t_func_const_packed_struct_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_const_packed_struct_bad2.py b/test_regress/t/t_func_const_packed_struct_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_const_packed_struct_bad2.py +++ b/test_regress/t/t_func_const_packed_struct_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_const_packed_struct_bad2.v b/test_regress/t/t_func_const_packed_struct_bad2.v index 77be332a6..746e321c3 100644 --- a/test_regress/t/t_func_const_packed_struct_bad2.v +++ b/test_regress/t/t_func_const_packed_struct_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_const_struct_bad.py b/test_regress/t/t_func_const_struct_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_const_struct_bad.py +++ b/test_regress/t/t_func_const_struct_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_const_struct_bad.v b/test_regress/t/t_func_const_struct_bad.v index c7e75afa5..767761763 100644 --- a/test_regress/t/t_func_const_struct_bad.v +++ b/test_regress/t/t_func_const_struct_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_crc.py b/test_regress/t/t_func_crc.py index 0304e7ed5..0f6ce0c75 100755 --- a/test_regress/t/t_func_crc.py +++ b/test_regress/t/t_func_crc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_crc.v b/test_regress/t/t_func_crc.v index 34a510412..f8ef4126a 100644 --- a/test_regress/t/t_func_crc.v +++ b/test_regress/t/t_func_crc.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_default_warn.py b/test_regress/t/t_func_default_warn.py index 78d425f95..35bc0fd0e 100755 --- a/test_regress/t/t_func_default_warn.py +++ b/test_regress/t/t_func_default_warn.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_default_warn.v b/test_regress/t/t_func_default_warn.v index a0c5ec436..5172cc469 100644 --- a/test_regress/t/t_func_default_warn.v +++ b/test_regress/t/t_func_default_warn.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Test for warning (not error) on improperly width'ed // default function argument // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 function automatic logic foo diff --git a/test_regress/t/t_func_defaults.py b/test_regress/t/t_func_defaults.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_defaults.py +++ b/test_regress/t/t_func_defaults.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_defaults.v b/test_regress/t/t_func_defaults.v index 907e50e92..3c56a6b7e 100644 --- a/test_regress/t/t_func_defaults.v +++ b/test_regress/t/t_func_defaults.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Test for warning (not error) on improperly width'ed // default function argument // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 parameter logic BAR = 1'b1; diff --git a/test_regress/t/t_func_dotted.v b/test_regress/t/t_func_dotted.v index 17653192b..172eef864 100644 --- a/test_regress/t/t_func_dotted.v +++ b/test_regress/t/t_func_dotted.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_dotted_inl0.py b/test_regress/t/t_func_dotted_inl0.py index 9d666e421..97e26834a 100755 --- a/test_regress/t/t_func_dotted_inl0.py +++ b/test_regress/t/t_func_dotted_inl0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_dotted_inl0.vlt b/test_regress/t/t_func_dotted_inl0.vlt index 74d8c961a..7a9f34eac 100644 --- a/test_regress/t/t_func_dotted_inl0.vlt +++ b/test_regress/t/t_func_dotted_inl0.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_func_dotted_inl0_vlt.py b/test_regress/t/t_func_dotted_inl0_vlt.py index eefa82526..20d633489 100755 --- a/test_regress/t/t_func_dotted_inl0_vlt.py +++ b/test_regress/t/t_func_dotted_inl0_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_dotted_inl1.py b/test_regress/t/t_func_dotted_inl1.py index a60a34cb4..4f57eb710 100755 --- a/test_regress/t/t_func_dotted_inl1.py +++ b/test_regress/t/t_func_dotted_inl1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_dotted_inl1.vlt b/test_regress/t/t_func_dotted_inl1.vlt index f930d70a0..9da0a3c07 100644 --- a/test_regress/t/t_func_dotted_inl1.vlt +++ b/test_regress/t/t_func_dotted_inl1.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_func_dotted_inl1_vlt.py b/test_regress/t/t_func_dotted_inl1_vlt.py index bd48a7f96..5051ce0ad 100755 --- a/test_regress/t/t_func_dotted_inl1_vlt.py +++ b/test_regress/t/t_func_dotted_inl1_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_dotted_inl2.py b/test_regress/t/t_func_dotted_inl2.py index f0180cc32..701407a39 100755 --- a/test_regress/t/t_func_dotted_inl2.py +++ b/test_regress/t/t_func_dotted_inl2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_dotted_inl2.vlt b/test_regress/t/t_func_dotted_inl2.vlt index 855db3058..d628c1a38 100644 --- a/test_regress/t/t_func_dotted_inl2.vlt +++ b/test_regress/t/t_func_dotted_inl2.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_func_dotted_inl2_vlt.py b/test_regress/t/t_func_dotted_inl2_vlt.py index f572fb45b..bac3557bc 100755 --- a/test_regress/t/t_func_dotted_inl2_vlt.py +++ b/test_regress/t/t_func_dotted_inl2_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_endian.py b/test_regress/t/t_func_endian.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_endian.py +++ b/test_regress/t/t_func_endian.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_endian.v b/test_regress/t/t_func_endian.v index 260e3a987..09fe4c966 100644 --- a/test_regress/t/t_func_endian.v +++ b/test_regress/t/t_func_endian.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_first.py b/test_regress/t/t_func_first.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_first.py +++ b/test_regress/t/t_func_first.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_first.v b/test_regress/t/t_func_first.v index 22c7c52dd..a0b80224c 100644 --- a/test_regress/t/t_func_first.v +++ b/test_regress/t/t_func_first.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_flip.py b/test_regress/t/t_func_flip.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_flip.py +++ b/test_regress/t/t_func_flip.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_flip.v b/test_regress/t/t_func_flip.v index ad1e197f0..911484111 100644 --- a/test_regress/t/t_func_flip.v +++ b/test_regress/t/t_func_flip.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define INT_RANGE 31:0 diff --git a/test_regress/t/t_func_gen.py b/test_regress/t/t_func_gen.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_gen.py +++ b/test_regress/t/t_func_gen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_gen.v b/test_regress/t/t_func_gen.v index 1904643cf..c87019760 100644 --- a/test_regress/t/t_func_gen.v +++ b/test_regress/t/t_func_gen.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2012 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_graphcirc.py b/test_regress/t/t_func_graphcirc.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_graphcirc.py +++ b/test_regress/t/t_func_graphcirc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_graphcirc.v b/test_regress/t/t_func_graphcirc.v index 8097ca345..5550bf81e 100644 --- a/test_regress/t/t_func_graphcirc.v +++ b/test_regress/t/t_func_graphcirc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_grey.py b/test_regress/t/t_func_grey.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_grey.py +++ b/test_regress/t/t_func_grey.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_grey.v b/test_regress/t/t_func_grey.v index c93305c3f..b4a458155 100644 --- a/test_regress/t/t_func_grey.v +++ b/test_regress/t/t_func_grey.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_impure_bad.py b/test_regress/t/t_func_impure_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_func_impure_bad.py +++ b/test_regress/t/t_func_impure_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_impure_bad.v b/test_regress/t/t_func_impure_bad.v index a042b770a..d45511ad3 100644 --- a/test_regress/t/t_func_impure_bad.v +++ b/test_regress/t/t_func_impure_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_inconly.py b/test_regress/t/t_func_inconly.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_inconly.py +++ b/test_regress/t/t_func_inconly.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_inconly.v b/test_regress/t/t_func_inconly.v index af4eb9a42..043f7e340 100644 --- a/test_regress/t/t_func_inconly.v +++ b/test_regress/t/t_func_inconly.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_inout_bit_sel.py b/test_regress/t/t_func_inout_bit_sel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_inout_bit_sel.py +++ b/test_regress/t/t_func_inout_bit_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_inout_bit_sel.v b/test_regress/t/t_func_inout_bit_sel.v index 926cf14dc..d407267e1 100644 --- a/test_regress/t/t_func_inout_bit_sel.v +++ b/test_regress/t/t_func_inout_bit_sel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_func_io_order.py b/test_regress/t/t_func_io_order.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_io_order.py +++ b/test_regress/t/t_func_io_order.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_io_order.v b/test_regress/t/t_func_io_order.v index c7b90d5c5..682f41ca7 100644 --- a/test_regress/t/t_func_io_order.v +++ b/test_regress/t/t_func_io_order.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_func_lib.py b/test_regress/t/t_func_lib.py index 1b870040f..ea10931a5 100755 --- a/test_regress/t/t_func_lib.py +++ b/test_regress/t/t_func_lib.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_lib.v b/test_regress/t/t_func_lib.v index 5882728ba..6006e2aa5 100644 --- a/test_regress/t/t_func_lib.v +++ b/test_regress/t/t_func_lib.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_lib_sub.py b/test_regress/t/t_func_lib_sub.py index de97f6118..ce610dcf1 100755 --- a/test_regress/t/t_func_lib_sub.py +++ b/test_regress/t/t_func_lib_sub.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_lib_sub.v b/test_regress/t/t_func_lib_sub.v index 23eca8af5..13bca13cc 100644 --- a/test_regress/t/t_func_lib_sub.v +++ b/test_regress/t/t_func_lib_sub.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define zednkw 200 diff --git a/test_regress/t/t_func_lib_sub_timing.py b/test_regress/t/t_func_lib_sub_timing.py index 7c9bdb51b..6ec93499c 100755 --- a/test_regress/t/t_func_lib_sub_timing.py +++ b/test_regress/t/t_func_lib_sub_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_link.py b/test_regress/t/t_func_link.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_link.py +++ b/test_regress/t/t_func_link.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_link.v b/test_regress/t/t_func_link.v index 8921a89cc..31950f388 100644 --- a/test_regress/t/t_func_link.v +++ b/test_regress/t/t_func_link.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module Test(/*AUTOARG*/ diff --git a/test_regress/t/t_func_many_return.py b/test_regress/t/t_func_many_return.py index 5b582e767..09e1e8923 100755 --- a/test_regress/t/t_func_many_return.py +++ b/test_regress/t/t_func_many_return.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_many_return.v b/test_regress/t/t_func_many_return.v index b4f1fe8a7..89c157369 100644 --- a/test_regress/t/t_func_many_return.v +++ b/test_regress/t/t_func_many_return.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_mlog2.py b/test_regress/t/t_func_mlog2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_mlog2.py +++ b/test_regress/t/t_func_mlog2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_mlog2.v b/test_regress/t/t_func_mlog2.v index 1d85a39f6..3ee90fc89 100644 --- a/test_regress/t/t_func_mlog2.v +++ b/test_regress/t/t_func_mlog2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_modify_input.py b/test_regress/t/t_func_modify_input.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_func_modify_input.py +++ b/test_regress/t/t_func_modify_input.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_modify_input.v b/test_regress/t/t_func_modify_input.v index b1005d1e9..5a7bbadd6 100644 --- a/test_regress/t/t_func_modify_input.v +++ b/test_regress/t/t_func_modify_input.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class foo; diff --git a/test_regress/t/t_func_named.py b/test_regress/t/t_func_named.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_named.py +++ b/test_regress/t/t_func_named.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_named.v b/test_regress/t/t_func_named.v index 4d57317f0..11c41bb7f 100644 --- a/test_regress/t/t_func_named.v +++ b/test_regress/t/t_func_named.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_func_nansi_dup_bad.py b/test_regress/t/t_func_nansi_dup_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_func_nansi_dup_bad.py +++ b/test_regress/t/t_func_nansi_dup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_nansi_dup_bad.v b/test_regress/t/t_func_nansi_dup_bad.v index 06efe7e21..7095c9647 100644 --- a/test_regress/t/t_func_nansi_dup_bad.v +++ b/test_regress/t/t_func_nansi_dup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef int T; diff --git a/test_regress/t/t_func_nansi_mism_bad.py b/test_regress/t/t_func_nansi_mism_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_func_nansi_mism_bad.py +++ b/test_regress/t/t_func_nansi_mism_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_nansi_mism_bad.v b/test_regress/t/t_func_nansi_mism_bad.v index b5d0038a3..dd5e687eb 100644 --- a/test_regress/t/t_func_nansi_mism_bad.v +++ b/test_regress/t/t_func_nansi_mism_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef int T; diff --git a/test_regress/t/t_func_no_lifetime_bad.out b/test_regress/t/t_func_no_lifetime_bad.out index 148325abf..5bf7797db 100644 --- a/test_regress/t/t_func_no_lifetime_bad.out +++ b/test_regress/t/t_func_no_lifetime_bad.out @@ -1,4 +1,4 @@ -%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:26:17: Function/task's lifetime implicitly set to static +%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:26:17: Function/task's lifetime implicitly set to static; variables made static (IEEE 1800-2023 6.21) : ... Suggest use 'function automatic' or 'function static' 26 | function int f_implicit_static(); | ^~~~~~~~~~~~~~~~~ @@ -8,7 +8,7 @@ | ^~~ ... For warning description see https://verilator.org/warn/IMPLICITSTATIC?v=latest ... Use "/* verilator lint_off IMPLICITSTATIC */" and lint_on around source to disable this message. -%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:31:9: Function/task's lifetime implicitly set to static +%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:31:9: Function/task's lifetime implicitly set to static; variables made static (IEEE 1800-2023 6.21) : ... Suggest use 'task automatic' or 'task static' 31 | task t_implicit_static(); | ^~~~~~~~~~~~~~~~~ @@ -16,12 +16,12 @@ : ... The initializer value will only be set once 32 | int cnt = 0; | ^~~ -%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:9:8: Variable's lifetime implicitly set to static +%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:9:8: Variable's lifetime implicitly set to static (IEEE 1800-2023 6.21) : ... The initializer value will only be set once : ... Suggest use 'static' before variable declaration' 9 | int cnt = 0; | ^~~ -%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:15:8: Variable's lifetime implicitly set to static +%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:15:8: Variable's lifetime implicitly set to static (IEEE 1800-2023 6.21) : ... The initializer value will only be set once : ... Suggest use 'static' before variable declaration' 15 | int cnt = 0; diff --git a/test_regress/t/t_func_no_lifetime_bad.py b/test_regress/t/t_func_no_lifetime_bad.py index 966dc53da..20b96a7d7 100755 --- a/test_regress/t/t_func_no_lifetime_bad.py +++ b/test_regress/t/t_func_no_lifetime_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_no_lifetime_bad.v b/test_regress/t/t_func_no_lifetime_bad.v index db183549e..bd1f74be1 100644 --- a/test_regress/t/t_func_no_lifetime_bad.v +++ b/test_regress/t/t_func_no_lifetime_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 // Not legal to put "static" here, so no warning diff --git a/test_regress/t/t_func_no_paren.py b/test_regress/t/t_func_no_paren.py index cca4c9e73..d6d35e7fd 100755 --- a/test_regress/t/t_func_no_paren.py +++ b/test_regress/t/t_func_no_paren.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_no_paren.v b/test_regress/t/t_func_no_paren.v index 13a56eff9..50353b698 100644 --- a/test_regress/t/t_func_no_paren.v +++ b/test_regress/t/t_func_no_paren.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_func_no_parentheses_bad.py b/test_regress/t/t_func_no_parentheses_bad.py index 966dc53da..20b96a7d7 100755 --- a/test_regress/t/t_func_no_parentheses_bad.py +++ b/test_regress/t/t_func_no_parentheses_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_no_parentheses_bad.v b/test_regress/t/t_func_no_parentheses_bad.v index 0427f1d3d..80c20f2a8 100644 --- a/test_regress/t/t_func_no_parentheses_bad.v +++ b/test_regress/t/t_func_no_parentheses_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 function static int func(); diff --git a/test_regress/t/t_func_noinl.py b/test_regress/t/t_func_noinl.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_noinl.py +++ b/test_regress/t/t_func_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_noinl.v b/test_regress/t/t_func_noinl.v index 2b280291b..62d2ff7fb 100644 --- a/test_regress/t/t_func_noinl.v +++ b/test_regress/t/t_func_noinl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_numones.py b/test_regress/t/t_func_numones.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_numones.py +++ b/test_regress/t/t_func_numones.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_numones.v b/test_regress/t/t_func_numones.v index 2de8d7427..4de7ae579 100644 --- a/test_regress/t/t_func_numones.v +++ b/test_regress/t/t_func_numones.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_outfirst.py b/test_regress/t/t_func_outfirst.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_outfirst.py +++ b/test_regress/t/t_func_outfirst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_outfirst.v b/test_regress/t/t_func_outfirst.v index 4b79becd2..366217711 100644 --- a/test_regress/t/t_func_outfirst.v +++ b/test_regress/t/t_func_outfirst.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define DDIFF_BITS 9 diff --git a/test_regress/t/t_func_outp.py b/test_regress/t/t_func_outp.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_outp.py +++ b/test_regress/t/t_func_outp.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_outp.v b/test_regress/t/t_func_outp.v index 23f8f82dc..dd320cb68 100644 --- a/test_regress/t/t_func_outp.v +++ b/test_regress/t/t_func_outp.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_paramed.py b/test_regress/t/t_func_paramed.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_paramed.py +++ b/test_regress/t/t_func_paramed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_paramed.v b/test_regress/t/t_func_paramed.v index b52c17812..a37955179 100644 --- a/test_regress/t/t_func_paramed.v +++ b/test_regress/t/t_func_paramed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_plog.py b/test_regress/t/t_func_plog.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_plog.py +++ b/test_regress/t/t_func_plog.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_plog.v b/test_regress/t/t_func_plog.v index 0e21e3253..f4aaafe3d 100644 --- a/test_regress/t/t_func_plog.v +++ b/test_regress/t/t_func_plog.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_public.py b/test_regress/t/t_func_public.py index 8c9c746dc..b9e93fcc8 100755 --- a/test_regress/t/t_func_public.py +++ b/test_regress/t/t_func_public.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_public.v b/test_regress/t/t_func_public.v index 08549a602..ad2aa7882 100644 --- a/test_regress/t/t_func_public.v +++ b/test_regress/t/t_func_public.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_public_trace.py b/test_regress/t/t_func_public_trace.py index e7cacfb8f..07719b2e0 100755 --- a/test_regress/t/t_func_public_trace.py +++ b/test_regress/t/t_func_public_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_purification.py b/test_regress/t/t_func_purification.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_func_purification.py +++ b/test_regress/t/t_func_purification.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_purification.v b/test_regress/t/t_func_purification.v index 50dd549f3..0800130d9 100644 --- a/test_regress/t/t_func_purification.v +++ b/test_regress/t/t_func_purification.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_rand.cpp b/test_regress/t/t_func_rand.cpp index c11d28602..e177457d6 100644 --- a/test_regress/t/t_func_rand.cpp +++ b/test_regress/t/t_func_rand.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_func_rand.py b/test_regress/t/t_func_rand.py index 7b94250d8..eb8f88301 100755 --- a/test_regress/t/t_func_rand.py +++ b/test_regress/t/t_func_rand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_rand.v b/test_regress/t/t_func_rand.v index 053ffe78d..bb3c7d5eb 100644 --- a/test_regress/t/t_func_rand.v +++ b/test_regress/t/t_func_rand.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk, Rand); diff --git a/test_regress/t/t_func_range.py b/test_regress/t/t_func_range.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_range.py +++ b/test_regress/t/t_func_range.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_range.v b/test_regress/t/t_func_range.v index 3f1de54f6..e618c09a8 100644 --- a/test_regress/t/t_func_range.v +++ b/test_regress/t/t_func_range.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_real_abs.py b/test_regress/t/t_func_real_abs.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_real_abs.py +++ b/test_regress/t/t_func_real_abs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_real_abs.v b/test_regress/t/t_func_real_abs.v index 247477e97..bc13a7451 100644 --- a/test_regress/t/t_func_real_abs.v +++ b/test_regress/t/t_func_real_abs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug591 diff --git a/test_regress/t/t_func_real_exprstmt.py b/test_regress/t/t_func_real_exprstmt.py index f8d9a4ad0..0b222644d 100755 --- a/test_regress/t/t_func_real_exprstmt.py +++ b/test_regress/t/t_func_real_exprstmt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_real_exprstmt.v b/test_regress/t/t_func_real_exprstmt.v index 4df720960..a8a0d93a1 100644 --- a/test_regress/t/t_func_real_exprstmt.v +++ b/test_regress/t/t_func_real_exprstmt.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_real_param.py b/test_regress/t/t_func_real_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_real_param.py +++ b/test_regress/t/t_func_real_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_real_param.v b/test_regress/t/t_func_real_param.v index d446632ba..21a95626b 100644 --- a/test_regress/t/t_func_real_param.v +++ b/test_regress/t/t_func_real_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug475 diff --git a/test_regress/t/t_func_recurse.py b/test_regress/t/t_func_recurse.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_recurse.py +++ b/test_regress/t/t_func_recurse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_recurse.v b/test_regress/t/t_func_recurse.v index 2b03f09e4..9aca61ca2 100644 --- a/test_regress/t/t_func_recurse.v +++ b/test_regress/t/t_func_recurse.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_recurse2.py b/test_regress/t/t_func_recurse2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_recurse2.py +++ b/test_regress/t/t_func_recurse2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_recurse2.v b/test_regress/t/t_func_recurse2.v index 6ef719186..bf003b5a2 100644 --- a/test_regress/t/t_func_recurse2.v +++ b/test_regress/t/t_func_recurse2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_recurse_param.py b/test_regress/t/t_func_recurse_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_recurse_param.py +++ b/test_regress/t/t_func_recurse_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_recurse_param.v b/test_regress/t/t_func_recurse_param.v index cf82c3993..567b36b1f 100644 --- a/test_regress/t/t_func_recurse_param.v +++ b/test_regress/t/t_func_recurse_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_func_recurse_param_bad.py b/test_regress/t/t_func_recurse_param_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_func_recurse_param_bad.py +++ b/test_regress/t/t_func_recurse_param_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_recurse_param_bad.v b/test_regress/t/t_func_recurse_param_bad.v index f3e88f9ba..54c7c6c89 100644 --- a/test_regress/t/t_func_recurse_param_bad.v +++ b/test_regress/t/t_func_recurse_param_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_redef.py b/test_regress/t/t_func_redef.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_func_redef.py +++ b/test_regress/t/t_func_redef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_redef.v b/test_regress/t/t_func_redef.v index 19d4f4a89..b26be4e64 100644 --- a/test_regress/t/t_func_redef.v +++ b/test_regress/t/t_func_redef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 function automatic integer min(input integer a, input integer b); diff --git a/test_regress/t/t_func_ref.py b/test_regress/t/t_func_ref.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_ref.py +++ b/test_regress/t/t_func_ref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_ref.v b/test_regress/t/t_func_ref.v index 3627e76e7..d142afe12 100644 --- a/test_regress/t/t_func_ref.v +++ b/test_regress/t/t_func_ref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_func_ref_arg.py b/test_regress/t/t_func_ref_arg.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_ref_arg.py +++ b/test_regress/t/t_func_ref_arg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_ref_arg.v b/test_regress/t/t_func_ref_arg.v index d2c371762..29abf15fb 100644 --- a/test_regress/t/t_func_ref_arg.v +++ b/test_regress/t/t_func_ref_arg.v @@ -1,60 +1,95 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); class MyInt; - int x; - function new(int a); - x = a; - endfunction + int x; + function new(int a); + x = a; + endfunction endclass function int get_val_set_5(ref int x); - automatic int y = x; - x = 5; - return y; + automatic int y = x; + x = 5; + return y; endfunction class Cls; - function int get_val_set_2(ref int x); - automatic int y = x; - x = 2; - return y; - endfunction + function int get_val_set_2(ref int x); + automatic int y = x; + x = 2; + return y; + endfunction endclass +typedef struct { + MyInt arr[2][][$]; +} struct_t; + module t; - int a, b; - int arr[1]; - Cls cls; - MyInt mi; - initial begin - a = 10; - b = get_val_set_5(a); - `checkh(a, 5); - `checkh(b, 10); + int a, b; + int arr[1]; + int dyn_arr[]; + int dyn_arr_2d[][]; + struct_t st; + Cls cls; + MyInt mi; + initial begin + a = 10; + b = get_val_set_5(a); + `checkh(a, 5); + `checkh(b, 10); - cls = new; - b = cls.get_val_set_2(a); - `checkh(a, 2); - `checkh(b, 5); + cls = new; + b = cls.get_val_set_2(a); + `checkh(a, 2); + `checkh(b, 5); - mi = new(1); - b = cls.get_val_set_2(mi.x); - `checkh(mi.x, 2); - `checkh(b, 1); + mi = new(1); + b = cls.get_val_set_2(mi.x); + `checkh(mi.x, 2); + `checkh(b, 1); - arr[0] = 10; - b = cls.get_val_set_2(arr[0]); - `checkh(arr[0], 2); - `checkh(b, 10); + arr[0] = 10; + b = cls.get_val_set_2(arr[0]); + `checkh(arr[0], 2); + `checkh(b, 10); - $write("*-* All Finished *-*\n"); - $finish; - end + dyn_arr = new[3]; + dyn_arr[1] = 10; + b = get_val_set_5(dyn_arr[1]); + `checkh(dyn_arr[1], 5); + `checkh(b, 10); + b = cls.get_val_set_2(dyn_arr[1]); + `checkh(dyn_arr[1], 2); + `checkh(b, 5); + + dyn_arr_2d = new[2]; + dyn_arr_2d[0] = new[4]; + dyn_arr_2d[0][1] = 10; + b = get_val_set_5(dyn_arr_2d[0][1]); + `checkh(dyn_arr_2d[0][1], 5); + `checkh(b, 10); + b = cls.get_val_set_2(dyn_arr_2d[0][1]); + `checkh(dyn_arr_2d[0][1], 2); + `checkh(b, 5); + + st.arr[1] = new[3]; + st.arr[1][2][0] = new(10); + b = get_val_set_5(st.arr[1][2][0].x); + `checkh(st.arr[1][2][0].x, 5); + `checkh(b, 10); + b = cls.get_val_set_2(st.arr[1][2][0].x); + `checkh(st.arr[1][2][0].x, 2); + `checkh(b, 5); + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_func_ref_bad.py b/test_regress/t/t_func_ref_bad.py index 34f78aa37..7a7714003 100755 --- a/test_regress/t/t_func_ref_bad.py +++ b/test_regress/t/t_func_ref_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_ref_bad.v b/test_regress/t/t_func_ref_bad.v index 50099dd67..5abadd8c5 100644 --- a/test_regress/t/t_func_ref_bad.v +++ b/test_regress/t/t_func_ref_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_func_ref_noinline.py b/test_regress/t/t_func_ref_noinline.py index 475f46f55..ba85fe71d 100755 --- a/test_regress/t/t_func_ref_noinline.py +++ b/test_regress/t/t_func_ref_noinline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_ref_noparen.py b/test_regress/t/t_func_ref_noparen.py index 319c0ff4a..10ad7f0de 100755 --- a/test_regress/t/t_func_ref_noparen.py +++ b/test_regress/t/t_func_ref_noparen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_ref_noparen.v b/test_regress/t/t_func_ref_noparen.v index b006b9d1f..893dccaf7 100644 --- a/test_regress/t/t_func_ref_noparen.v +++ b/test_regress/t/t_func_ref_noparen.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class c; diff --git a/test_regress/t/t_func_refio_bad.py b/test_regress/t/t_func_refio_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_func_refio_bad.py +++ b/test_regress/t/t_func_refio_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_refio_bad.v b/test_regress/t/t_func_refio_bad.v index dc117ac4f..a8eef79b2 100644 --- a/test_regress/t/t_func_refio_bad.v +++ b/test_regress/t/t_func_refio_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(); diff --git a/test_regress/t/t_func_regfirst.py b/test_regress/t/t_func_regfirst.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_regfirst.py +++ b/test_regress/t/t_func_regfirst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_regfirst.v b/test_regress/t/t_func_regfirst.v index 3d868a17c..24c24a561 100644 --- a/test_regress/t/t_func_regfirst.v +++ b/test_regress/t/t_func_regfirst.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_return.py b/test_regress/t/t_func_return.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_return.py +++ b/test_regress/t/t_func_return.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_return.v b/test_regress/t/t_func_return.v index 93f8d9538..4b09e6de9 100644 --- a/test_regress/t/t_func_return.v +++ b/test_regress/t/t_func_return.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug420 diff --git a/test_regress/t/t_func_return_bad.py b/test_regress/t/t_func_return_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_return_bad.py +++ b/test_regress/t/t_func_return_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_return_bad.v b/test_regress/t/t_func_return_bad.v index 0a3ac1f0c..331382f93 100644 --- a/test_regress/t/t_func_return_bad.v +++ b/test_regress/t/t_func_return_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_return_init.py b/test_regress/t/t_func_return_init.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_func_return_init.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_return_init.v b/test_regress/t/t_func_return_init.v new file mode 100644 index 000000000..6eeec9fa0 --- /dev/null +++ b/test_regress/t/t_func_return_init.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`ifdef verilator + `define no_optimize(v) $c(v) +`else + `define no_optimize(v) (v) +`endif +// verilog_format: on + +module t; + + class Cls; + function string unpack_string(int n); + for (int i = 0; i < n; ++i) begin + unpack_string = {unpack_string, "."}; + unpack_string[i] = "x"; + end + endfunction + endclass + + function static string unpack_static(int n); + for (int i = 0; i < n; ++i) begin + unpack_static = {unpack_static, "."}; + unpack_static[i] = "x"; + end + endfunction + + initial begin + Cls c; + string str1[]; + string str2[]; + string s; + + c = new; + str1 = new[2]; + foreach (str1[i]) str1[i] = c.unpack_string(`no_optimize(3 + i)); + `checks(str1[0], "xxx"); + `checks(str1[1], "xxxx"); + + str2 = new[2]; + foreach (str2[i]) str2[i] = unpack_static(`no_optimize(3 + i)); + `checks(str2[0], "xxx"); + `checks(str2[1], "xxxx..."); + + $finish; + end +endmodule diff --git a/test_regress/t/t_func_sel.py b/test_regress/t/t_func_sel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_sel.py +++ b/test_regress/t/t_func_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_sel.v b/test_regress/t/t_func_sel.v index 53ab12b1f..1b5e3fba6 100644 --- a/test_regress/t/t_func_sel.v +++ b/test_regress/t/t_func_sel.v @@ -3,8 +3,8 @@ // The code as shown applies a random vector to the Test // module, then calculates a CRC on the Test module's outputs. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_func_sum.py b/test_regress/t/t_func_sum.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_sum.py +++ b/test_regress/t/t_func_sum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_sum.v b/test_regress/t/t_func_sum.v index 38d9689dd..32000941f 100644 --- a/test_regress/t/t_func_sum.v +++ b/test_regress/t/t_func_sum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008-2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008-2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_task_bad.py b/test_regress/t/t_func_task_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_task_bad.py +++ b/test_regress/t/t_func_task_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_task_bad.v b/test_regress/t/t_func_task_bad.v index 9f0e668b3..01b81fb99 100644 --- a/test_regress/t/t_func_task_bad.v +++ b/test_regress/t/t_func_task_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_task_bad2.py b/test_regress/t/t_func_task_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_task_bad2.py +++ b/test_regress/t/t_func_task_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_task_bad2.v b/test_regress/t/t_func_task_bad2.v index 61d06bfe6..5599b11c9 100644 --- a/test_regress/t/t_func_task_bad2.v +++ b/test_regress/t/t_func_task_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_tie_bad.py b/test_regress/t/t_func_tie_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_tie_bad.py +++ b/test_regress/t/t_func_tie_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_tie_bad.v b/test_regress/t/t_func_tie_bad.v index d15bc31e1..2e0e0df37 100644 --- a/test_regress/t/t_func_tie_bad.v +++ b/test_regress/t/t_func_tie_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_twocall.py b/test_regress/t/t_func_twocall.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_twocall.py +++ b/test_regress/t/t_func_twocall.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_twocall.v b/test_regress/t/t_func_twocall.v index 3181bf757..850d9690c 100644 --- a/test_regress/t/t_func_twocall.v +++ b/test_regress/t/t_func_twocall.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_twocall_noexpand.py b/test_regress/t/t_func_twocall_noexpand.py index 995ad7526..ae6db56dd 100755 --- a/test_regress/t/t_func_twocall_noexpand.py +++ b/test_regress/t/t_func_twocall_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_types.py b/test_regress/t/t_func_types.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_types.py +++ b/test_regress/t/t_func_types.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_types.v b/test_regress/t/t_func_types.v index 23e02f76d..6c0fefc86 100644 --- a/test_regress/t/t_func_types.v +++ b/test_regress/t/t_func_types.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_under.py b/test_regress/t/t_func_under.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_under.py +++ b/test_regress/t/t_func_under.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_under.v b/test_regress/t/t_func_under.v index dabe8f2b9..80cad6e78 100644 --- a/test_regress/t/t_func_under.v +++ b/test_regress/t/t_func_under.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_func_under2.py b/test_regress/t/t_func_under2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_under2.py +++ b/test_regress/t/t_func_under2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_under2.v b/test_regress/t/t_func_under2.v index 7976de909..db9eb731c 100644 --- a/test_regress/t/t_func_under2.v +++ b/test_regress/t/t_func_under2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug598 diff --git a/test_regress/t/t_func_uninit.py b/test_regress/t/t_func_uninit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_uninit.py +++ b/test_regress/t/t_func_uninit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_uninit.v b/test_regress/t/t_func_uninit.v index 1e688c113..a9152f83a 100644 --- a/test_regress/t/t_func_uninit.v +++ b/test_regress/t/t_func_uninit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off NORETURN diff --git a/test_regress/t/t_func_unit.py b/test_regress/t/t_func_unit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_unit.py +++ b/test_regress/t/t_func_unit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_unit.v b/test_regress/t/t_func_unit.v index 6f92f2ee0..85692325b 100644 --- a/test_regress/t/t_func_unit.v +++ b/test_regress/t/t_func_unit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 task tsk(output tfo); diff --git a/test_regress/t/t_func_v.py b/test_regress/t/t_func_v.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_v.py +++ b/test_regress/t/t_func_v.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_v.v b/test_regress/t/t_func_v.v index 0d553cf79..b7ab4cfb2 100644 --- a/test_regress/t/t_func_v.v +++ b/test_regress/t/t_func_v.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Chandan Egbert. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Chandan Egbert // SPDX-License-Identifier: CC0-1.0 // See bug569 diff --git a/test_regress/t/t_func_v_noinl.py b/test_regress/t/t_func_v_noinl.py index eb69b64b8..f359974de 100755 --- a/test_regress/t/t_func_v_noinl.py +++ b/test_regress/t/t_func_v_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_virt_new.py b/test_regress/t/t_func_virt_new.py index 80ec03e15..00b50b5db 100755 --- a/test_regress/t/t_func_virt_new.py +++ b/test_regress/t/t_func_virt_new.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_virt_new.v b/test_regress/t/t_func_virt_new.v index b7e0d2b1c..394f662ca 100644 --- a/test_regress/t/t_func_virt_new.v +++ b/test_regress/t/t_func_virt_new.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class cl #( diff --git a/test_regress/t/t_func_virt_new_bad.out b/test_regress/t/t_func_virt_new_bad.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_func_virt_new_bad.py b/test_regress/t/t_func_virt_new_bad.py index 1bf1426f9..f3bbcad9d 100755 --- a/test_regress/t/t_func_virt_new_bad.py +++ b/test_regress/t/t_func_virt_new_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_virt_new_bad.v b/test_regress/t/t_func_virt_new_bad.v index 125cb9c13..0ea029e73 100644 --- a/test_regress/t/t_func_virt_new_bad.v +++ b/test_regress/t/t_func_virt_new_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class cl #( diff --git a/test_regress/t/t_func_void.py b/test_regress/t/t_func_void.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_void.py +++ b/test_regress/t/t_func_void.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_void.v b/test_regress/t/t_func_void.v index 5d013b936..22c3f0bb5 100644 --- a/test_regress/t/t_func_void.v +++ b/test_regress/t/t_func_void.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_void_bad.py b/test_regress/t/t_func_void_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_func_void_bad.py +++ b/test_regress/t/t_func_void_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_void_bad.v b/test_regress/t/t_func_void_bad.v index e9552e58c..4bf00d330 100644 --- a/test_regress/t/t_func_void_bad.v +++ b/test_regress/t/t_func_void_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_func_while.py b/test_regress/t/t_func_while.py index 6827b0e69..43e84d59a 100755 --- a/test_regress/t/t_func_while.py +++ b/test_regress/t/t_func_while.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_while.v b/test_regress/t/t_func_while.v index 0f848e3c2..bab93123a 100644 --- a/test_regress/t/t_func_while.v +++ b/test_regress/t/t_func_while.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Julien Margetts. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Julien Margetts // SPDX-License-Identifier: CC0-1.0 module t #(parameter SZ = 4096) diff --git a/test_regress/t/t_func_while2.py b/test_regress/t/t_func_while2.py index 563b6fc6f..78ebab213 100755 --- a/test_regress/t/t_func_while2.py +++ b/test_regress/t/t_func_while2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_while2.v b/test_regress/t/t_func_while2.v index 8cbb204a5..c89528c38 100644 --- a/test_regress/t/t_func_while2.v +++ b/test_regress/t/t_func_while2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_func_wide.py b/test_regress/t/t_func_wide.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_func_wide.py +++ b/test_regress/t/t_func_wide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_wide.v b/test_regress/t/t_func_wide.v index 18884e285..dff6fc994 100644 --- a/test_regress/t/t_func_wide.v +++ b/test_regress/t/t_func_wide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_wide_out.py b/test_regress/t/t_func_wide_out.py index a4ec64568..e8e85a995 100755 --- a/test_regress/t/t_func_wide_out.py +++ b/test_regress/t/t_func_wide_out.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_wide_out.v b/test_regress/t/t_func_wide_out.v index 6a7c9fb1c..55f779165 100644 --- a/test_regress/t/t_func_wide_out.v +++ b/test_regress/t/t_func_wide_out.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_func_wide_out_bad.py b/test_regress/t/t_func_wide_out_bad.py index f2623d634..71309d152 100755 --- a/test_regress/t/t_func_wide_out_bad.py +++ b/test_regress/t/t_func_wide_out_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_func_wide_out_c.cpp b/test_regress/t/t_func_wide_out_c.cpp index 7518d510b..5f80aa1b3 100644 --- a/test_regress/t/t_func_wide_out_c.cpp +++ b/test_regress/t/t_func_wide_out_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_func_wide_out_noinl.py b/test_regress/t/t_func_wide_out_noinl.py index a27b30540..63c25c186 100755 --- a/test_regress/t/t_func_wide_out_noinl.py +++ b/test_regress/t/t_func_wide_out_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fuzz_always_bad.py b/test_regress/t/t_fuzz_always_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_fuzz_always_bad.py +++ b/test_regress/t/t_fuzz_always_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fuzz_always_bad.v b/test_regress/t/t_fuzz_always_bad.v index da50b761f..3eebbeaca 100644 --- a/test_regress/t/t_fuzz_always_bad.v +++ b/test_regress/t/t_fuzz_always_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug1577 diff --git a/test_regress/t/t_fuzz_eof_bad.out b/test_regress/t/t_fuzz_eof_bad.out index f46de5f58..1bfbafbac 100644 --- a/test_regress/t/t_fuzz_eof_bad.out +++ b/test_regress/t/t_fuzz_eof_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_fuzz_eof_bad.v:3:31: Unterminated string +%Error: t/t_fuzz_eof_bad.v:5:31: Unterminated string ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_fuzz_eof_bad.v:2:21: EOF in (* - 2 | initial $lay(*Hello!=nendmodule +%Error: t/t_fuzz_eof_bad.v:4:21: EOF in (* + 4 | initial $lay(*Hello!=nendmodule | ^ -%Error: t/t_fuzz_eof_bad.v:2:21: syntax error, unexpected end of file - 2 | initial $lay(*Hello!=nendmodule +%Error: t/t_fuzz_eof_bad.v:4:21: syntax error, unexpected end of file + 4 | initial $lay(*Hello!=nendmodule | ^ %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_fuzz_eof_bad.py b/test_regress/t/t_fuzz_eof_bad.py index 0dd5f3628..a16dfd494 100755 --- a/test_regress/t/t_fuzz_eof_bad.py +++ b/test_regress/t/t_fuzz_eof_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fuzz_eof_bad.v b/test_regress/t/t_fuzz_eof_bad.v index 3b3591544..333f76069 100644 --- a/test_regress/t/t_fuzz_eof_bad.v +++ b/test_regress/t/t_fuzz_eof_bad.v @@ -1,3 +1,5 @@ +// SPDX-FileCopyrightText: 2022 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 module a; initial $lay(*Hello!=n"); endmodule diff --git a/test_regress/t/t_fuzz_eqne_bad.py b/test_regress/t/t_fuzz_eqne_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_fuzz_eqne_bad.py +++ b/test_regress/t/t_fuzz_eqne_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fuzz_eqne_bad.v b/test_regress/t/t_fuzz_eqne_bad.v index c4cd201fa..a39d87716 100644 --- a/test_regress/t/t_fuzz_eqne_bad.v +++ b/test_regress/t/t_fuzz_eqne_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug1587 diff --git a/test_regress/t/t_fuzz_genintf_bad.py b/test_regress/t/t_fuzz_genintf_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_fuzz_genintf_bad.py +++ b/test_regress/t/t_fuzz_genintf_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fuzz_genintf_bad.v b/test_regress/t/t_fuzz_genintf_bad.v index 99fad227c..26f981d71 100644 --- a/test_regress/t/t_fuzz_genintf_bad.v +++ b/test_regress/t/t_fuzz_genintf_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug1588 diff --git a/test_regress/t/t_fuzz_negwidth_bad.py b/test_regress/t/t_fuzz_negwidth_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_fuzz_negwidth_bad.py +++ b/test_regress/t/t_fuzz_negwidth_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fuzz_negwidth_bad.v b/test_regress/t/t_fuzz_negwidth_bad.v index 242f0a64b..3562cd781 100644 --- a/test_regress/t/t_fuzz_negwidth_bad.v +++ b/test_regress/t/t_fuzz_negwidth_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 int a = -12'd1; diff --git a/test_regress/t/t_fuzz_triand_bad.py b/test_regress/t/t_fuzz_triand_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_fuzz_triand_bad.py +++ b/test_regress/t/t_fuzz_triand_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_fuzz_triand_bad.v b/test_regress/t/t_fuzz_triand_bad.v index 525b2c55b..648e830f1 100644 --- a/test_regress/t/t_fuzz_triand_bad.v +++ b/test_regress/t/t_fuzz_triand_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_gantt.py b/test_regress/t/t_gantt.py index 4523e81e5..17f3728e4 100755 --- a/test_regress/t/t_gantt.py +++ b/test_regress/t/t_gantt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test for bin/verilator_gantt, diff --git a/test_regress/t/t_gantt.v b/test_regress/t/t_gantt.v index 678f4b28e..8abab6f77 100644 --- a/test_regress/t/t_gantt.v +++ b/test_regress/t/t_gantt.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t( diff --git a/test_regress/t/t_gantt_c.cpp b/test_regress/t/t_gantt_c.cpp index 670b78ebc..f356ada29 100644 --- a/test_regress/t/t_gantt_c.cpp +++ b/test_regress/t/t_gantt_c.cpp @@ -1,8 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // //************************************************************************* diff --git a/test_regress/t/t_gantt_hier.py b/test_regress/t/t_gantt_hier.py index 86c6ce7bf..28f6e1427 100755 --- a/test_regress/t/t_gantt_hier.py +++ b/test_regress/t/t_gantt_hier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test for bin/verilator_gantt, diff --git a/test_regress/t/t_gantt_io.py b/test_regress/t/t_gantt_io.py index 03f00fd52..d96c404f6 100755 --- a/test_regress/t/t_gantt_io.py +++ b/test_regress/t/t_gantt_io.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gantt_io_arm.py b/test_regress/t/t_gantt_io_arm.py index 99cb09f47..2c471f032 100755 --- a/test_regress/t/t_gantt_io_arm.py +++ b/test_regress/t/t_gantt_io_arm.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gantt_io_noproc.py b/test_regress/t/t_gantt_io_noproc.py index d5270ebae..27aedb654 100755 --- a/test_regress/t/t_gantt_io_noproc.py +++ b/test_regress/t/t_gantt_io_noproc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gantt_numa.py b/test_regress/t/t_gantt_numa.py index a58c53bda..bdb6722d3 100755 --- a/test_regress/t/t_gantt_numa.py +++ b/test_regress/t/t_gantt_numa.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test for bin/verilator_gantt, @@ -45,4 +45,34 @@ for trial in range(0, trials): # False fails occasionally # test.file_grep_not(gantt_log, r'%Warning:') # e.g. There were fewer CPUs (1) than threads (3). +if sys.platform != "darwin": + # Test disabling NUMA assignment + gantt_log_numa_none = test.obj_dir + "/gantt_numa_none.log" + test.execute(run_env='VERILATOR_NUMA_STRATEGY=none', + all_run_flags=[ + "+verilator+prof+exec+start+2", " +verilator+prof+exec+window+2", + " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat" + ]) + test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", "--no-vcd", test.obj_dir + + "/profile_exec.dat", "| tee " + gantt_log_numa_none + ]) + test.file_grep(gantt_log_numa_none, r'NUMA status += no NUMA assignment requested') + + # Test invalid NUMA assignment + gantt_log_numa_invalid = test.obj_dir + "/gantt_numa_invalid.log" + test.execute(run_env='VERILATOR_NUMA_STRATEGY=invalid_value', + all_run_flags=[ + "+verilator+prof+exec+start+2", " +verilator+prof+exec+window+2", + " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat" + ]) + test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", "--no-vcd", test.obj_dir + + "/profile_exec.dat", "| tee " + gantt_log_numa_invalid + ]) + # %Warning: unknown VERILATOR_NUMA_STRATEGY value 'invalid_value' + test.file_grep( + gantt_log_numa_invalid, + r"NUMA status += %Warning: unknown VERILATOR_NUMA_STRATEGY value 'invalid_value'") + test.passes() diff --git a/test_regress/t/t_gantt_numa_default_threads.cpp b/test_regress/t/t_gantt_numa_default_threads.cpp new file mode 100644 index 000000000..25ffeae42 --- /dev/null +++ b/test_regress/t/t_gantt_numa_default_threads.cpp @@ -0,0 +1,53 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +// Generated header +#include "Vt_gantt_numa_default_threads.h" +// General headers +#include "verilated.h" + +#include "TestCheck.h" + +int errors = 0; + +std::unique_ptr topp; + +int main(int argc, char** argv) { + vluint64_t sim_time = 1100; + const std::unique_ptr contextp{new VerilatedContext}; + contextp->debug(0); + contextp->commandArgs(argc, argv); + srand48(5); + TEST_CHECK_EQ(contextp->useNumaAssign(), false); + contextp->threads(3); + TEST_CHECK_EQ(contextp->useNumaAssign(), true); + contextp->useNumaAssign(false); + TEST_CHECK_EQ(contextp->useNumaAssign(), false); + topp.reset(new VM_PREFIX{"top"}); + + topp->clk = 0; + topp->eval(); + { contextp->timeInc(10); } + + while ((contextp->time() < sim_time) && !contextp->gotFinish()) { + topp->eval(); + topp->clk = !topp->clk; + topp->eval(); + contextp->timeInc(5); + } + if (!contextp->gotFinish()) { + vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); + } + topp->final(); + + topp.reset(); + return (errors ? 10 : 0); +} diff --git a/test_regress/t/t_gantt_numa_default_threads.py b/test_regress/t/t_gantt_numa_default_threads.py new file mode 100755 index 000000000..8daad4e3b --- /dev/null +++ b/test_regress/t/t_gantt_numa_default_threads.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import os +import sys +import vltest_bootstrap + +test.scenarios('vltmt') + +test.top_filename = "t/t_gantt.v" +test.pli_filename = "t/t_gantt_numa_default_threads.cpp" + +# Require enough cores so default thread count stays >= model threads +# (we don't call contextp->threads in this test) +test.skip_if_too_few_cores() + +test.compile( + make_main=False, + verilator_flags2=[ + "--prof-exec", + "--exe", + test.pli_filename, + test.t_dir + "/t_gantt_c.cpp", + ], + threads=test.get_default_vltmt_threads, +) + +test.execute(all_run_flags=[ + "+verilator+prof+exec+start+2", + " +verilator+prof+exec+window+2", + " +verilator+prof+exec+file+" + test.obj_dir + "/profile_exec.dat", +]) + +gantt_log = test.obj_dir + "/gantt_default_threads.log" +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator_gantt", + "--no-vcd", + test.obj_dir + "/profile_exec.dat", + "| tee " + gantt_log, +]) + +if sys.platform != "darwin": + test.file_grep(gantt_log, r"NUMA status += NUMA assignment not requested") + +test.passes() diff --git a/test_regress/t/t_gantt_two.cpp b/test_regress/t/t_gantt_two.cpp index 484fd4072..ae5c7744f 100644 --- a/test_regress/t/t_gantt_two.cpp +++ b/test_regress/t/t_gantt_two.cpp @@ -1,8 +1,8 @@ // // DESCRIPTION: Verilator: Verilog Multiple Model Test Module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_gantt_two.py b/test_regress/t/t_gantt_two.py index 2b1a2125e..5019bcd40 100755 --- a/test_regress/t/t_gantt_two.py +++ b/test_regress/t/t_gantt_two.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test for bin/verilator_gantt, diff --git a/test_regress/t/t_gate_array.py b/test_regress/t/t_gate_array.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gate_array.py +++ b/test_regress/t/t_gate_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_array.v b/test_regress/t/t_gate_array.v index 224946680..7d5b378ca 100644 --- a/test_regress/t/t_gate_array.v +++ b/test_regress/t/t_gate_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_gate_basic.py b/test_regress/t/t_gate_basic.py index c98cbe4f8..543805b26 100755 --- a/test_regress/t/t_gate_basic.py +++ b/test_regress/t/t_gate_basic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_basic.v b/test_regress/t/t_gate_basic.v index d7c9b2690..d09b5b3ca 100644 --- a/test_regress/t/t_gate_basic.v +++ b/test_regress/t/t_gate_basic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gate_basic_specify_bad.py b/test_regress/t/t_gate_basic_specify_bad.py index 07db30dae..203508fa3 100755 --- a/test_regress/t/t_gate_basic_specify_bad.py +++ b/test_regress/t/t_gate_basic_specify_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_basic_timing.py b/test_regress/t/t_gate_basic_timing.py index 12c73db41..eadcbdea3 100755 --- a/test_regress/t/t_gate_basic_timing.py +++ b/test_regress/t/t_gate_basic_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_chained.py b/test_regress/t/t_gate_chained.py index ce19841e5..b164183a5 100755 --- a/test_regress/t/t_gate_chained.py +++ b/test_regress/t/t_gate_chained.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_delay_unsup.py b/test_regress/t/t_gate_delay_unsup.py index 1e19ff45d..ddce87727 100755 --- a/test_regress/t/t_gate_delay_unsup.py +++ b/test_regress/t/t_gate_delay_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_delref.py b/test_regress/t/t_gate_delref.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_gate_delref.py +++ b/test_regress/t/t_gate_delref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_delref.v b/test_regress/t/t_gate_delref.v index c9255a9ee..db32a89dd 100644 --- a/test_regress/t/t_gate_delref.v +++ b/test_regress/t/t_gate_delref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug1475 diff --git a/test_regress/t/t_gate_elim.py b/test_regress/t/t_gate_elim.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gate_elim.py +++ b/test_regress/t/t_gate_elim.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_elim.v b/test_regress/t/t_gate_elim.v index a85443d10..6d0bfb65f 100644 --- a/test_regress/t/t_gate_elim.v +++ b/test_regress/t/t_gate_elim.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gate_elim_cycle.py b/test_regress/t/t_gate_elim_cycle.py index 147fe6faf..0379f0dd0 100755 --- a/test_regress/t/t_gate_elim_cycle.py +++ b/test_regress/t/t_gate_elim_cycle.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_elim_cycle.v b/test_regress/t/t_gate_elim_cycle.v index adc3ed1f0..8885eb608 100644 --- a/test_regress/t/t_gate_elim_cycle.v +++ b/test_regress/t/t_gate_elim_cycle.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module GND(output G); diff --git a/test_regress/t/t_gate_fdup.py b/test_regress/t/t_gate_fdup.py index 648df1761..d63392a97 100755 --- a/test_regress/t/t_gate_fdup.py +++ b/test_regress/t/t_gate_fdup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_fdup.v b/test_regress/t/t_gate_fdup.v index 8e829f33a..cc5dfb8ff 100644 --- a/test_regress/t/t_gate_fdup.v +++ b/test_regress/t/t_gate_fdup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Thomas Dzetkulic. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Thomas Dzetkulic // SPDX-License-Identifier: CC0-1.0 module fnor2(f, a, b); diff --git a/test_regress/t/t_gate_implicit.py b/test_regress/t/t_gate_implicit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gate_implicit.py +++ b/test_regress/t/t_gate_implicit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_implicit.v b/test_regress/t/t_gate_implicit.v index 0a1dd648e..953d2af6f 100644 --- a/test_regress/t/t_gate_implicit.v +++ b/test_regress/t/t_gate_implicit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gate_inline_wide_exclude_multiple.py b/test_regress/t/t_gate_inline_wide_exclude_multiple.py index fa749e5aa..76a8991cf 100755 --- a/test_regress/t/t_gate_inline_wide_exclude_multiple.py +++ b/test_regress/t/t_gate_inline_wide_exclude_multiple.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_inline_wide_exclude_multiple.v b/test_regress/t/t_gate_inline_wide_exclude_multiple.v index 5e2ae1a80..e416e73ec 100644 --- a/test_regress/t/t_gate_inline_wide_exclude_multiple.v +++ b/test_regress/t/t_gate_inline_wide_exclude_multiple.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 localparam N = 256; // Wider than expand limit. diff --git a/test_regress/t/t_gate_inline_wide_noexclude_arraysel.py b/test_regress/t/t_gate_inline_wide_noexclude_arraysel.py index 16d0c0d48..ccbd8c7e7 100755 --- a/test_regress/t/t_gate_inline_wide_noexclude_arraysel.py +++ b/test_regress/t/t_gate_inline_wide_noexclude_arraysel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_inline_wide_noexclude_arraysel.v b/test_regress/t/t_gate_inline_wide_noexclude_arraysel.v index 282929316..19e20c90a 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_arraysel.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_arraysel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gate_inline_wide_noexclude_const.py b/test_regress/t/t_gate_inline_wide_noexclude_const.py index 00b053a42..5102631f7 100755 --- a/test_regress/t/t_gate_inline_wide_noexclude_const.py +++ b/test_regress/t/t_gate_inline_wide_noexclude_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_inline_wide_noexclude_const.v b/test_regress/t/t_gate_inline_wide_noexclude_const.v index d45648982..0fe85071e 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_const.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gate_inline_wide_noexclude_other_scope.py b/test_regress/t/t_gate_inline_wide_noexclude_other_scope.py index 0226ac927..c20d324db 100755 --- a/test_regress/t/t_gate_inline_wide_noexclude_other_scope.py +++ b/test_regress/t/t_gate_inline_wide_noexclude_other_scope.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_inline_wide_noexclude_other_scope.v b/test_regress/t/t_gate_inline_wide_noexclude_other_scope.v index 2181f9504..c49112c4d 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_other_scope.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_other_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 localparam N = 256; // Wider than expand limit. diff --git a/test_regress/t/t_gate_inline_wide_noexclude_sel.py b/test_regress/t/t_gate_inline_wide_noexclude_sel.py index d94bc0982..aa65429ab 100755 --- a/test_regress/t/t_gate_inline_wide_noexclude_sel.py +++ b/test_regress/t/t_gate_inline_wide_noexclude_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_inline_wide_noexclude_sel.v b/test_regress/t/t_gate_inline_wide_noexclude_sel.v index 931ca0d62..d4061c2d3 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_sel.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_sel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_gate_inline_wide_noexclude_small_wide.py b/test_regress/t/t_gate_inline_wide_noexclude_small_wide.py index 0226ac927..c20d324db 100755 --- a/test_regress/t/t_gate_inline_wide_noexclude_small_wide.py +++ b/test_regress/t/t_gate_inline_wide_noexclude_small_wide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_inline_wide_noexclude_small_wide.v b/test_regress/t/t_gate_inline_wide_noexclude_small_wide.v index bbb3022a3..072fe1eae 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_small_wide.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_small_wide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 localparam N = 65; // Wide but narrower than expand limit diff --git a/test_regress/t/t_gate_inline_wide_noexclude_varref.py b/test_regress/t/t_gate_inline_wide_noexclude_varref.py index 7917af8ae..1d91e6493 100755 --- a/test_regress/t/t_gate_inline_wide_noexclude_varref.py +++ b/test_regress/t/t_gate_inline_wide_noexclude_varref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_inline_wide_noexclude_varref.v b/test_regress/t/t_gate_inline_wide_noexclude_varref.v index 4b4b94d64..392bf4b07 100644 --- a/test_regress/t/t_gate_inline_wide_noexclude_varref.v +++ b/test_regress/t/t_gate_inline_wide_noexclude_varref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t(input [255:0] clk); diff --git a/test_regress/t/t_gate_loop.py b/test_regress/t/t_gate_loop.py index 8e15ef2eb..1e5dd26b7 100755 --- a/test_regress/t/t_gate_loop.py +++ b/test_regress/t/t_gate_loop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_loop.v b/test_regress/t/t_gate_loop.v index 13ce7c416..122f3bb88 100644 --- a/test_regress/t/t_gate_loop.v +++ b/test_regress/t/t_gate_loop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gate_lvalue_const.py b/test_regress/t/t_gate_lvalue_const.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gate_lvalue_const.py +++ b/test_regress/t/t_gate_lvalue_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_lvalue_const.v b/test_regress/t/t_gate_lvalue_const.v index 90082787a..22fe2958c 100644 --- a/test_regress/t/t_gate_lvalue_const.v +++ b/test_regress/t/t_gate_lvalue_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gate_opt.py b/test_regress/t/t_gate_opt.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gate_opt.py +++ b/test_regress/t/t_gate_opt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_opt.v b/test_regress/t/t_gate_opt.v index be6b9dc68..aacdc2fd0 100644 --- a/test_regress/t/t_gate_opt.v +++ b/test_regress/t/t_gate_opt.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Yutetsu TAKATSUKASA. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 // bug5101 diff --git a/test_regress/t/t_gate_ormux.py b/test_regress/t/t_gate_ormux.py index 3fb514208..65a710e42 100755 --- a/test_regress/t/t_gate_ormux.py +++ b/test_regress/t/t_gate_ormux.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_ormux.v b/test_regress/t/t_gate_ormux.v index 26d254632..b061450a1 100644 --- a/test_regress/t/t_gate_ormux.v +++ b/test_regress/t/t_gate_ormux.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_gate_primitives_implicit_net.out b/test_regress/t/t_gate_primitives_implicit_net.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_gate_primitives_implicit_net.py b/test_regress/t/t_gate_primitives_implicit_net.py index 30e8dbdb0..b93d271a7 100755 --- a/test_regress/t/t_gate_primitives_implicit_net.py +++ b/test_regress/t/t_gate_primitives_implicit_net.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_primitives_implicit_net.v b/test_regress/t/t_gate_primitives_implicit_net.v old mode 100755 new mode 100644 index 97759afbf..f3bf1f44e --- a/test_regress/t/t_gate_primitives_implicit_net.v +++ b/test_regress/t/t_gate_primitives_implicit_net.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_gate_strength.py b/test_regress/t/t_gate_strength.py index e838b9b8f..eddea7e80 100755 --- a/test_regress/t/t_gate_strength.py +++ b/test_regress/t/t_gate_strength.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_strength.v b/test_regress/t/t_gate_strength.v index 038ca9cfb..d9b1805dc 100644 --- a/test_regress/t/t_gate_strength.v +++ b/test_regress/t/t_gate_strength.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gate_tree.py b/test_regress/t/t_gate_tree.py index 49fa92260..685e592d7 100755 --- a/test_regress/t/t_gate_tree.py +++ b/test_regress/t/t_gate_tree.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_unsup.py b/test_regress/t/t_gate_unsup.py index fcdfcc6f4..ec058f6d6 100755 --- a/test_regress/t/t_gate_unsup.py +++ b/test_regress/t/t_gate_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_unsup.v b/test_regress/t/t_gate_unsup.v index ed1e43175..357e72b33 100644 --- a/test_regress/t/t_gate_unsup.v +++ b/test_regress/t/t_gate_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gate_width_bad.py b/test_regress/t/t_gate_width_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_gate_width_bad.py +++ b/test_regress/t/t_gate_width_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gate_width_bad.v b/test_regress/t/t_gate_width_bad.v index 2d0d0b424..ba3f0948c 100644 --- a/test_regress/t/t_gate_width_bad.v +++ b/test_regress/t/t_gate_width_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gen_alw.py b/test_regress/t/t_gen_alw.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_alw.py +++ b/test_regress/t/t_gen_alw.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_alw.v b/test_regress/t/t_gen_alw.v index 3ca0abff4..517e8f9d7 100644 --- a/test_regress/t/t_gen_alw.v +++ b/test_regress/t/t_gen_alw.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_assign.py b/test_regress/t/t_gen_assign.py index 3527cdb06..fabbdb10f 100755 --- a/test_regress/t/t_gen_assign.py +++ b/test_regress/t/t_gen_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_assign.v b/test_regress/t/t_gen_assign.v index d3f3a0e05..33ce5aa84 100644 --- a/test_regress/t/t_gen_assign.v +++ b/test_regress/t/t_gen_assign.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps diff --git a/test_regress/t/t_gen_class.py b/test_regress/t/t_gen_class.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_gen_class.py +++ b/test_regress/t/t_gen_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_class.v b/test_regress/t/t_gen_class.v index 6fc26c1ba..02bb776f2 100644 --- a/test_regress/t/t_gen_class.v +++ b/test_regress/t/t_gen_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_gen_cond_bitrange.py b/test_regress/t/t_gen_cond_bitrange.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_cond_bitrange.py +++ b/test_regress/t/t_gen_cond_bitrange.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_cond_bitrange.v b/test_regress/t/t_gen_cond_bitrange.v index 5a1ea06b9..1e90d2603 100644 --- a/test_regress/t/t_gen_cond_bitrange.v +++ b/test_regress/t/t_gen_cond_bitrange.v @@ -4,8 +4,8 @@ // is defined by SIZE. However since the loop range is larger, this only works // if short-circuited evaluation of the generate loop is in place. -// This file ONLY is placed into the Public Domain, for any use, without -// warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 `define MAX_SIZE 4 diff --git a/test_regress/t/t_gen_cond_bitrange_bad.py b/test_regress/t/t_gen_cond_bitrange_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_gen_cond_bitrange_bad.py +++ b/test_regress/t/t_gen_cond_bitrange_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_cond_bitrange_bad.v b/test_regress/t/t_gen_cond_bitrange_bad.v index 3ca0614cf..617cdf8c0 100644 --- a/test_regress/t/t_gen_cond_bitrange_bad.v +++ b/test_regress/t/t_gen_cond_bitrange_bad.v @@ -6,8 +6,8 @@ // is defined by SIZE. However since the loop range is larger, this only works // if short-circuited evaluation of the generate loop is in place. -// This file ONLY is placed into the Public Domain, for any use, without -// warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed into the Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 `define MAX_SIZE 3 diff --git a/test_regress/t/t_gen_cond_const.py b/test_regress/t/t_gen_cond_const.py index 4aa451103..837003ca3 100755 --- a/test_regress/t/t_gen_cond_const.py +++ b/test_regress/t/t_gen_cond_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_cond_const.v b/test_regress/t/t_gen_cond_const.v index 3b47a45fd..3abd26625 100644 --- a/test_regress/t/t_gen_cond_const.v +++ b/test_regress/t/t_gen_cond_const.v @@ -3,8 +3,8 @@ // The given generate loop should have a constant expression as argument. This // test checks it really does evaluate as constant. -// This file ONLY is placed into the Public Domain, for any use, without -// warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed into the Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_gen_defparam.py b/test_regress/t/t_gen_defparam.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_defparam.py +++ b/test_regress/t/t_gen_defparam.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_defparam.v b/test_regress/t/t_gen_defparam.v index c8a61a1a9..b2395a467 100644 --- a/test_regress/t/t_gen_defparam.v +++ b/test_regress/t/t_gen_defparam.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_defparam_bad.py b/test_regress/t/t_gen_defparam_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_gen_defparam_bad.py +++ b/test_regress/t/t_gen_defparam_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_defparam_bad.v b/test_regress/t/t_gen_defparam_bad.v index ba1edba9c..a1b265dc3 100644 --- a/test_regress/t/t_gen_defparam_bad.v +++ b/test_regress/t/t_gen_defparam_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gen_defparam_multi.out b/test_regress/t/t_gen_defparam_multi.out index 3d15e0f23..978c2c93a 100644 --- a/test_regress/t/t_gen_defparam_multi.out +++ b/test_regress/t/t_gen_defparam_multi.out @@ -1,18 +1,17 @@ -%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:14:17: Unsupported: defparam with no dot - 14 | defparam PAR = 5; - | ^ +%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:12:16: Unsupported: defparam with no dot + 12 | defparam PAR = 5; + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:39:24: Unsupported: defparam with more than one dot - 39 | defparam m2.m3.PAR3 = 80; - | ^ -%Error: t/t_gen_defparam_multi.v:39:25: syntax error, unexpected IDENTIFIER, expecting ',' or ';' - 39 | defparam m2.m3.PAR3 = 80; - | ^~~~ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:44:24: Unsupported: defparam with more than one dot - 44 | defparam m2.m3.PAR3 = 40; - | ^ -%Error: t/t_gen_defparam_multi.v:44:25: syntax error, unexpected IDENTIFIER, expecting ',' or ';' - 44 | defparam m2.m3.PAR3 = 40; - | ^~~~ +%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:28:19: Unsupported: defparam with arrayed instance + 28 | defparam blk[i].u_m3.PAR3 = i; + | ^ +%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:28:27: Unsupported: defparam with more than one dot + 28 | defparam blk[i].u_m3.PAR3 = i; + | ^ +%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:51:43: Unsupported: defparam with more than one dot + 51 | defparam m2.PAR2 = 8; defparam m2.m3.PAR3 = 80; + | ^ +%Error-UNSUPPORTED: t/t_gen_defparam_multi.v:55:43: Unsupported: defparam with more than one dot + 55 | defparam m2.PAR2 = 4; defparam m2.m3.PAR3 = 40; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_gen_defparam_multi.py b/test_regress/t/t_gen_defparam_multi.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_gen_defparam_multi.py +++ b/test_regress/t/t_gen_defparam_multi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_defparam_multi.v b/test_regress/t/t_gen_defparam_multi.v index 8f4642bc7..b0011a063 100644 --- a/test_regress/t/t_gen_defparam_multi.v +++ b/test_regress/t/t_gen_defparam_multi.v @@ -1,59 +1,74 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - parameter PAR = 3; +module t ( + input clk +); + parameter PAR = 3; - defparam PAR = 5; + defparam PAR = 5; - wire [31:0] o2a, o2b, o3a, o3b; + wire [31:0] o2a, o2b, o3a, o3b; - m1 #(0) m1a(.o2(o2a), .o3(o3a)); - m1 #(1) m1b(.o2(o2b), .o3(o3b)); + m1 #(0) m1a ( + .o2(o2a), + .o3(o3a) + ); + m1 #(1) m1b ( + .o2(o2b), + .o3(o3b) + ); - always @ (posedge clk) begin - if (PAR != 5) $stop; - if (o2a != 8) $stop; - if (o2b != 4) $stop; - if (o3a != 80) $stop; - if (o3b != 40) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + generate + for (genvar i = 0; i < 8; i = i + 1) begin : blk + m3 u_m3 (); + defparam blk[i].u_m3.PAR3 = i; + end + endgenerate + + always @(posedge clk) begin + if (PAR != 5) $stop; + if (o2a != 8) $stop; + if (o2b != 4) $stop; + if (o3a != 80) $stop; + if (o3b != 40) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module m1 (output wire [31:0] o2, - output wire [31:0] o3); - parameter W = 0; - generate - if (W == 0) begin - m2 m2 (.*); - defparam m2.PAR2 = 8; - defparam m2.m3.PAR3 = 80; - end - else begin - m2 m2 (.*); - defparam m2.PAR2 = 4; - defparam m2.m3.PAR3 = 40; - end - endgenerate +module m1 ( + output wire [31:0] o2, + output wire [31:0] o3 +); + parameter W = 0; + generate + if (W == 0) begin + m2 m2 (.*); + defparam m2.PAR2 = 8; defparam m2.m3.PAR3 = 80; + end + else begin + m2 m2 (.*); + defparam m2.PAR2 = 4; defparam m2.m3.PAR3 = 40; + end + endgenerate endmodule -module m2 (output wire [31:0] o2, - output wire [31:0] o3); - parameter PAR2 = 20; - assign o2 = PAR2; - m3 m3 (.*); +module m2 ( + output wire [31:0] o2, + output wire [31:0] o3 +); + parameter PAR2 = 20; + assign o2 = PAR2; + m3 m3 (.*); endmodule -module m3 (output wire [31:0] o3); - parameter PAR3 = 40; - assign o3 = PAR3; +module m3 ( + output wire [31:0] o3 +); + parameter PAR3 = 40; + assign o3 = PAR3; endmodule diff --git a/test_regress/t/t_gen_defparam_nfound_bad.py b/test_regress/t/t_gen_defparam_nfound_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_gen_defparam_nfound_bad.py +++ b/test_regress/t/t_gen_defparam_nfound_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_defparam_nfound_bad.v b/test_regress/t/t_gen_defparam_nfound_bad.v index 0ad34d49b..b00bc1460 100644 --- a/test_regress/t/t_gen_defparam_nfound_bad.v +++ b/test_regress/t/t_gen_defparam_nfound_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gen_div0.py b/test_regress/t/t_gen_div0.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_div0.py +++ b/test_regress/t/t_gen_div0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_div0.v b/test_regress/t/t_gen_div0.v index d9cc0eb07..050f2da30 100644 --- a/test_regress/t/t_gen_div0.v +++ b/test_regress/t/t_gen_div0.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOINST*/); diff --git a/test_regress/t/t_gen_duplicated_blocks_bad.py b/test_regress/t/t_gen_duplicated_blocks_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_gen_duplicated_blocks_bad.py +++ b/test_regress/t/t_gen_duplicated_blocks_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_duplicated_blocks_bad.v b/test_regress/t/t_gen_duplicated_blocks_bad.v index c8d581b98..67a430da2 100644 --- a/test_regress/t/t_gen_duplicated_blocks_bad.v +++ b/test_regress/t/t_gen_duplicated_blocks_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gen_for.py b/test_regress/t/t_gen_for.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_for.py +++ b/test_regress/t/t_gen_for.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_for.v b/test_regress/t/t_gen_for.v index fb48c7a08..2deda7334 100644 --- a/test_regress/t/t_gen_for.v +++ b/test_regress/t/t_gen_for.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_for0.py b/test_regress/t/t_gen_for0.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_for0.py +++ b/test_regress/t/t_gen_for0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_for0.v b/test_regress/t/t_gen_for0.v index 541824d87..79f9c281c 100644 --- a/test_regress/t/t_gen_for0.v +++ b/test_regress/t/t_gen_for0.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_for1.py b/test_regress/t/t_gen_for1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_for1.py +++ b/test_regress/t/t_gen_for1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_for1.v b/test_regress/t/t_gen_for1.v index 599cd55e1..36a1b9fc1 100644 --- a/test_regress/t/t_gen_for1.v +++ b/test_regress/t/t_gen_for1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_for_interface.py b/test_regress/t/t_gen_for_interface.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_for_interface.py +++ b/test_regress/t/t_gen_for_interface.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_for_interface.v b/test_regress/t/t_gen_for_interface.v index 63dff454d..14663e3fc 100644 --- a/test_regress/t/t_gen_for_interface.v +++ b/test_regress/t/t_gen_for_interface.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Johan Bjork. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Johan Bjork // SPDX-License-Identifier: CC0-1.0 parameter N = 5; diff --git a/test_regress/t/t_gen_for_overlap.py b/test_regress/t/t_gen_for_overlap.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_for_overlap.py +++ b/test_regress/t/t_gen_for_overlap.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_for_overlap.v b/test_regress/t/t_gen_for_overlap.v index 7c72bd1ca..20addc698 100644 --- a/test_regress/t/t_gen_for_overlap.v +++ b/test_regress/t/t_gen_for_overlap.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug749 diff --git a/test_regress/t/t_gen_for_shuffle.py b/test_regress/t/t_gen_for_shuffle.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_for_shuffle.py +++ b/test_regress/t/t_gen_for_shuffle.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_for_shuffle.v b/test_regress/t/t_gen_for_shuffle.v index 85316549f..4d59a72dc 100644 --- a/test_regress/t/t_gen_for_shuffle.v +++ b/test_regress/t/t_gen_for_shuffle.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_forif.py b/test_regress/t/t_gen_forif.py index c8913bea4..ab0e2f0f5 100755 --- a/test_regress/t/t_gen_forif.py +++ b/test_regress/t/t_gen_forif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_forif.v b/test_regress/t/t_gen_forif.v index 73fa55138..44319dbc6 100644 --- a/test_regress/t/t_gen_forif.v +++ b/test_regress/t/t_gen_forif.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_genblk.py b/test_regress/t/t_gen_genblk.py index b89e72146..a0efd81cb 100755 --- a/test_regress/t/t_gen_genblk.py +++ b/test_regress/t/t_gen_genblk.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_genblk.v b/test_regress/t/t_gen_genblk.v index 0a9b85582..0d90ff9a4 100644 --- a/test_regress/t/t_gen_genblk.v +++ b/test_regress/t/t_gen_genblk.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define CONCAT(a,b) a``b diff --git a/test_regress/t/t_gen_genblk_noinl.py b/test_regress/t/t_gen_genblk_noinl.py index 0b6136eb6..6412dc2e4 100755 --- a/test_regress/t/t_gen_genblk_noinl.py +++ b/test_regress/t/t_gen_genblk_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_if.py b/test_regress/t/t_gen_if.py index 3527cdb06..fabbdb10f 100755 --- a/test_regress/t/t_gen_if.py +++ b/test_regress/t/t_gen_if.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_if.v b/test_regress/t/t_gen_if.v index b5e724d23..08aba68e2 100644 --- a/test_regress/t/t_gen_if.v +++ b/test_regress/t/t_gen_if.v @@ -2,8 +2,8 @@ // simplistic example, should choose 1st conditional generate and assign straight through // the tool also compiles the special case and determines an error (replication value is 0) // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps diff --git a/test_regress/t/t_gen_ifelse.py b/test_regress/t/t_gen_ifelse.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_ifelse.py +++ b/test_regress/t/t_gen_ifelse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_ifelse.v b/test_regress/t/t_gen_ifelse.v index c23565d85..cdcab94b1 100644 --- a/test_regress/t/t_gen_ifelse.v +++ b/test_regress/t/t_gen_ifelse.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module s; diff --git a/test_regress/t/t_gen_inc.py b/test_regress/t/t_gen_inc.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_inc.py +++ b/test_regress/t/t_gen_inc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_inc.v b/test_regress/t/t_gen_inc.v index 1a0caf555..8048bf163 100644 --- a/test_regress/t/t_gen_inc.v +++ b/test_regress/t/t_gen_inc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_index.py b/test_regress/t/t_gen_index.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_gen_index.py +++ b/test_regress/t/t_gen_index.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_index.v b/test_regress/t/t_gen_index.v index 47e5cd994..51321d684 100644 --- a/test_regress/t/t_gen_index.v +++ b/test_regress/t/t_gen_index.v @@ -8,8 +8,8 @@ // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 `define START 8 diff --git a/test_regress/t/t_gen_intdot.py b/test_regress/t/t_gen_intdot.py index e5667d0d0..49a98679f 100755 --- a/test_regress/t/t_gen_intdot.py +++ b/test_regress/t/t_gen_intdot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_intdot.v b/test_regress/t/t_gen_intdot.v index 249af3417..070baff8a 100644 --- a/test_regress/t/t_gen_intdot.v +++ b/test_regress/t/t_gen_intdot.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_gen_intdot2.py b/test_regress/t/t_gen_intdot2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_intdot2.py +++ b/test_regress/t/t_gen_intdot2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_intdot2.v b/test_regress/t/t_gen_intdot2.v index 785d9dd13..42e2d11e8 100644 --- a/test_regress/t/t_gen_intdot2.v +++ b/test_regress/t/t_gen_intdot2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_gen_local.py b/test_regress/t/t_gen_local.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_local.py +++ b/test_regress/t/t_gen_local.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_local.v b/test_regress/t/t_gen_local.v index 782e74a70..4f7b7420c 100644 --- a/test_regress/t/t_gen_local.v +++ b/test_regress/t/t_gen_local.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_lsb.py b/test_regress/t/t_gen_lsb.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_lsb.py +++ b/test_regress/t/t_gen_lsb.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_lsb.v b/test_regress/t/t_gen_lsb.v index 87282d9c4..7978ceac2 100644 --- a/test_regress/t/t_gen_lsb.v +++ b/test_regress/t/t_gen_lsb.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_mislevel.py b/test_regress/t/t_gen_mislevel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_mislevel.py +++ b/test_regress/t/t_gen_mislevel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_mislevel.v b/test_regress/t/t_gen_mislevel.v index 671f2b00f..7a66963e9 100644 --- a/test_regress/t/t_gen_mislevel.v +++ b/test_regress/t/t_gen_mislevel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 /// We define the modules in "backward" order. diff --git a/test_regress/t/t_gen_missing.py b/test_regress/t/t_gen_missing.py index 1421dc553..6e83f4dbb 100755 --- a/test_regress/t/t_gen_missing.py +++ b/test_regress/t/t_gen_missing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_missing.v b/test_regress/t/t_gen_missing.v index 459c7fb65..960c1cf49 100644 --- a/test_regress/t/t_gen_missing.v +++ b/test_regress/t/t_gen_missing.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gen_missing_bad.py b/test_regress/t/t_gen_missing_bad.py index 8be012ec5..a13895572 100755 --- a/test_regress/t/t_gen_missing_bad.py +++ b/test_regress/t/t_gen_missing_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_missing_bad2.py b/test_regress/t/t_gen_missing_bad2.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_gen_missing_bad2.py +++ b/test_regress/t/t_gen_missing_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_missing_bad2.v b/test_regress/t/t_gen_missing_bad2.v index 6f8b9a350..691c04365 100644 --- a/test_regress/t/t_gen_missing_bad2.v +++ b/test_regress/t/t_gen_missing_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gen_nonconst_bad.py b/test_regress/t/t_gen_nonconst_bad.py index a3ece0800..8fbb4c1fd 100755 --- a/test_regress/t/t_gen_nonconst_bad.py +++ b/test_regress/t/t_gen_nonconst_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_nonconst_bad.v b/test_regress/t/t_gen_nonconst_bad.v index c4edbc3e4..ade175eb7 100644 --- a/test_regress/t/t_gen_nonconst_bad.v +++ b/test_regress/t/t_gen_nonconst_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_gen_self_return.py b/test_regress/t/t_gen_self_return.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_gen_self_return.py +++ b/test_regress/t/t_gen_self_return.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_self_return.v b/test_regress/t/t_gen_self_return.v index 708e50058..0ba7a9743 100644 --- a/test_regress/t/t_gen_self_return.v +++ b/test_regress/t/t_gen_self_return.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Roman Popov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Roman Popov // SPDX-License-Identifier: CC0-1.0 module dut diff --git a/test_regress/t/t_gen_upscope.py b/test_regress/t/t_gen_upscope.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_gen_upscope.py +++ b/test_regress/t/t_gen_upscope.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_upscope.v b/test_regress/t/t_gen_upscope.v index f765423d8..f7fecf2ce 100644 --- a/test_regress/t/t_gen_upscope.v +++ b/test_regress/t/t_gen_upscope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 /* Acceptable answer 1 diff --git a/test_regress/t/t_gen_var_bad.py b/test_regress/t/t_gen_var_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_gen_var_bad.py +++ b/test_regress/t/t_gen_var_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_gen_var_bad.v b/test_regress/t/t_gen_var_bad.v index f410dbed6..5a38223e0 100644 --- a/test_regress/t/t_gen_var_bad.v +++ b/test_regress/t/t_gen_var_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_generate_fatal_bad.py b/test_regress/t/t_generate_fatal_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_generate_fatal_bad.py +++ b/test_regress/t/t_generate_fatal_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_generate_fatal_bad.v b/test_regress/t/t_generate_fatal_bad.v index 48b6dc761..02b03c8a4 100644 --- a/test_regress/t/t_generate_fatal_bad.v +++ b/test_regress/t/t_generate_fatal_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Todd Strader // SPDX-License-Identifier: CC0-1.0 function integer get_baz(input integer bar); diff --git a/test_regress/t/t_genfor_hier.py b/test_regress/t/t_genfor_hier.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_genfor_hier.py +++ b/test_regress/t/t_genfor_hier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_genfor_hier.v b/test_regress/t/t_genfor_hier.v index 4832aaef1..db73bbb02 100644 --- a/test_regress/t/t_genfor_hier.v +++ b/test_regress/t/t_genfor_hier.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Demonstrate deferred linking across module // bondaries // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 module m1(); diff --git a/test_regress/t/t_genfor_init_o0.py b/test_regress/t/t_genfor_init_o0.py index 3eb087ae6..681d24ad0 100755 --- a/test_regress/t/t_genfor_init_o0.py +++ b/test_regress/t/t_genfor_init_o0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_genfor_init_o0.v b/test_regress/t/t_genfor_init_o0.v index 93318168b..70fec250c 100644 --- a/test_regress/t/t_genfor_init_o0.v +++ b/test_regress/t/t_genfor_init_o0.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_genfor_signed.py b/test_regress/t/t_genfor_signed.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_genfor_signed.py +++ b/test_regress/t/t_genfor_signed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_genfor_signed.v b/test_regress/t/t_genfor_signed.v index bcddeb761..8ee774a5f 100644 --- a/test_regress/t/t_genfor_signed.v +++ b/test_regress/t/t_genfor_signed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t # diff --git a/test_regress/t/t_genvar_for_bad.py b/test_regress/t/t_genvar_for_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_genvar_for_bad.py +++ b/test_regress/t/t_genvar_for_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_genvar_for_bad.v b/test_regress/t/t_genvar_for_bad.v index f8ffc0068..172cc0f8e 100644 --- a/test_regress/t/t_genvar_for_bad.v +++ b/test_regress/t/t_genvar_for_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_genvar_misuse_bad.py b/test_regress/t/t_genvar_misuse_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_genvar_misuse_bad.py +++ b/test_regress/t/t_genvar_misuse_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_genvar_misuse_bad.v b/test_regress/t/t_genvar_misuse_bad.v index 4e35a65a0..3633d5bbe 100644 --- a/test_regress/t/t_genvar_misuse_bad.v +++ b/test_regress/t/t_genvar_misuse_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See bug408 diff --git a/test_regress/t/t_hier_block.cpp b/test_regress/t/t_hier_block.cpp index 75f09abf1..a2675eb8a 100644 --- a/test_regress/t/t_hier_block.cpp +++ b/test_regress/t/t_hier_block.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_hier_block.py b/test_regress/t/t_hier_block.py index ff13a4925..1eea403ac 100755 --- a/test_regress/t/t_hier_block.py +++ b/test_regress/t/t_hier_block.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block.v b/test_regress/t/t_hier_block.v index 06c94efc2..16bc20b2f 100644 --- a/test_regress/t/t_hier_block.v +++ b/test_regress/t/t_hier_block.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Yutetsu TAKATSUKASA +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense `ifdef USE_VLT @@ -14,6 +14,17 @@ `timescale 1ns/1ps `endif +package stateless_pkg; + localparam int ONE = 1; +endpackage + +`ifdef STATEFUL_PKG +// This is in the $unit package, and will have a copy in every library, which +// is functionally incorrect, but testing it here to make sure it's at least +// traced properly. +logic global_flag = 1'b0; +`endif + interface byte_ifs(input clk); logic [7:0] data; modport sender(input clk, output data); @@ -27,6 +38,13 @@ typedef enum logic [1:0] { enum_val_3 = 2'd3 } enum_t; +typedef enum logic [1:0] { + alt_enum_0 = 2'd0, + alt_enum_1 = 2'd1, + alt_enum_2 = 2'd2, + alt_enum_3 = 2'd3 +} alt_enum_t; + `ifdef AS_PROT_LIB module secret ( clk @@ -87,6 +105,9 @@ module t #( end end count <= count + 1; +`ifdef STATEFUL_PKG + global_flag <= ~global_flag; +`endif end `ifdef CPP_MACRO @@ -126,21 +147,33 @@ module sub0( input wire clk, input wire [7:0] in, output wire [7:0] out); `HIER_BLOCK +`ifdef NO_INLINE + /* verilator no_inline_module */ +`endif logic [7:0] ff; always_ff @(posedge clk) ff <= in; assign out = ff; + +`ifdef STATEFUL_PKG + always_ff @(posedge clk) if (ff[0]) global_flag <= ff[1]; +`endif endmodule module sub1( input wire clk, input wire [11:4] in, // Uses higher LSB to cover bug3539 output wire [7:0] out); `HIER_BLOCK +`ifdef NO_INLINE + /* verilator no_inline_module */ +`endif logic [7:0] ff; + enum_t enum_v; - always_ff @(posedge clk) ff <= in + 1; + always_ff @(posedge clk) ff <= in + 8'(stateless_pkg::ONE); + always_ff @(posedge clk) enum_v <= enum_v.next(); assign out = ff; endmodule @@ -150,6 +183,7 @@ module sub2( output wire [7:0] out); `HIER_BLOCK logic [7:0] ff; + alt_enum_t alt_enum_v; // dpi_import_func returns (dpi_eport_func(v) -1) import "DPI-C" context function int dpi_import_func(int v); @@ -160,6 +194,7 @@ module sub2( endfunction always_ff @(posedge clk) ff <= 8'(dpi_import_func({24'b0, in})) + 8'd2; + always_ff @(posedge clk) alt_enum_v <= alt_enum_v.next(); byte_ifs in_ifs(.clk(clk)); byte_ifs out_ifs(.clk(clk)); @@ -202,6 +237,9 @@ module sub3 #( input wire clk, input wire [7:0] in, output wire [7:0] out); `HIER_BLOCK +`ifdef NO_INLINE + /* verilator no_inline_module */ +`endif initial $display("P0:%d UNUSED:%d %s %d", P0, UNUSED, STR, ENUM); @@ -233,6 +271,9 @@ module sub4 #( input wire clk, input wire [7:0] in, output wire[7:0] out); `HIER_BLOCK +`ifdef NO_INLINE + /* verilator no_inline_module */ +`endif initial begin if (P1 == 2) begin @@ -296,6 +337,9 @@ module sub4 #( endmodule module sub5 (input wire clk, input wire [127:0] in[2][3], output logic [7:0] out[2][3]); `HIER_BLOCK +`ifdef NO_INLINE + /* verilator no_inline_module */ +`endif int count = 0; always @(posedge clk) begin @@ -349,6 +393,9 @@ module sub5 (input wire clk, input wire [127:0] in[2][3], output logic [7:0] out endmodule module sub6 #(parameter P0 = 1, parameter P1 = 2) (output wire [7:0] out[2]); `HIER_BLOCK +`ifdef NO_INLINE + /* verilator no_inline_module */ +`endif assign out[0] = 8'(P0); assign out[1] = 8'(P1); endmodule diff --git a/test_regress/t/t_hier_block0_bad.py b/test_regress/t/t_hier_block0_bad.py index c80415ffe..6199d736e 100755 --- a/test_regress/t/t_hier_block0_bad.py +++ b/test_regress/t/t_hier_block0_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block0_bad.v b/test_regress/t/t_hier_block0_bad.v index 75019af6e..73cb1cab8 100644 --- a/test_regress/t/t_hier_block0_bad.v +++ b/test_regress/t/t_hier_block0_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020-2024 by Yutetsu TAKATSUKASA and Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020-2024 Yutetsu TAKATSUKASA and Antmicro // SPDX-License-Identifier: Unlicense `define HIER_BLOCK /*verilator hier_block*/ diff --git a/test_regress/t/t_hier_block1_bad.py b/test_regress/t/t_hier_block1_bad.py index ef7f2d674..0b4856f98 100755 --- a/test_regress/t/t_hier_block1_bad.py +++ b/test_regress/t/t_hier_block1_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block1_bad.v b/test_regress/t/t_hier_block1_bad.v index 8427b6c27..aa6e9c58d 100644 --- a/test_regress/t/t_hier_block1_bad.v +++ b/test_regress/t/t_hier_block1_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Yutetsu TAKATSUKASA +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense `define HIER_BLOCK /*verilator hier_block*/ diff --git a/test_regress/t/t_hier_block_binary.py b/test_regress/t/t_hier_block_binary.py index e0b1706b4..775bd9b18 100755 --- a/test_regress/t/t_hier_block_binary.py +++ b/test_regress/t/t_hier_block_binary.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_chained.py b/test_regress/t/t_hier_block_chained.py index d03dfedd9..fb17db8e6 100755 --- a/test_regress/t/t_hier_block_chained.py +++ b/test_regress/t/t_hier_block_chained.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -31,9 +31,9 @@ test.compile(v_flags2=[ if test.vltmt: test.file_grep(test.obj_dir + "/V" + test.name + "__hier.dir/V" + test.name + "__stats.txt", - r'Optimizations, Thread schedule count\s+(\d+)', 4) + r'Optimizations, Thread schedule count\s+(\d+)', 3) test.file_grep(test.obj_dir + "/V" + test.name + "__hier.dir/V" + test.name + "__stats.txt", - r'Optimizations, Thread schedule total tasks\s+(\d+)', 6) + r'Optimizations, Thread schedule total tasks\s+(\d+)', 5) test.execute() diff --git a/test_regress/t/t_hier_block_chained.v b/test_regress/t/t_hier_block_chained.v index d03d46706..5d3739823 100644 --- a/test_regress/t/t_hier_block_chained.v +++ b/test_regress/t/t_hier_block_chained.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // Based on tests emitted by t_gate_tree.py diff --git a/test_regress/t/t_hier_block_chained.vlt b/test_regress/t/t_hier_block_chained.vlt index 9740d5a91..6fb66a30b 100644 --- a/test_regress/t/t_hier_block_chained.vlt +++ b/test_regress/t/t_hier_block_chained.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_hier_block_cmake.py b/test_regress/t/t_hier_block_cmake.py index 80161d6c1..0d500703f 100755 --- a/test_regress/t/t_hier_block_cmake.py +++ b/test_regress/t/t_hier_block_cmake.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_cmake/CMakeLists.txt b/test_regress/t/t_hier_block_cmake/CMakeLists.txt index f39db2c11..802f77245 100644 --- a/test_regress/t/t_hier_block_cmake/CMakeLists.txt +++ b/test_regress/t/t_hier_block_cmake/CMakeLists.txt @@ -2,10 +2,10 @@ # # DESCRIPTION: CMake script for t_hier_block_cmake # -# Copyright 2003-2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2003-2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/test_regress/t/t_hier_block_cmake/main.cpp b/test_regress/t/t_hier_block_cmake/main.cpp index 731237b88..e380f57a8 100644 --- a/test_regress/t/t_hier_block_cmake/main.cpp +++ b/test_regress/t/t_hier_block_cmake/main.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_hier_block_import.py b/test_regress/t/t_hier_block_import.py index 12bfe08f5..92c27cdf9 100755 --- a/test_regress/t/t_hier_block_import.py +++ b/test_regress/t/t_hier_block_import.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_import.v b/test_regress/t/t_hier_block_import.v index c2ad81e44..d728e50ae 100644 --- a/test_regress/t/t_hier_block_import.v +++ b/test_regress/t/t_hier_block_import.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_hier_block_import/t_hier_block_import.vh b/test_regress/t/t_hier_block_import/t_hier_block_import.vh index d0cc5e74d..22e0d82c2 100644 --- a/test_regress/t/t_hier_block_import/t_hier_block_import.vh +++ b/test_regress/t/t_hier_block_import/t_hier_block_import.vh @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // No include guards to validate if included once. diff --git a/test_regress/t/t_hier_block_import/t_hier_block_import_args.vc b/test_regress/t/t_hier_block_import/t_hier_block_import_args.vc index 11c92e3ab..3567915c2 100644 --- a/test_regress/t/t_hier_block_import/t_hier_block_import_args.vc +++ b/test_regress/t/t_hier_block_import/t_hier_block_import_args.vc @@ -1,7 +1,7 @@ -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 --stats diff --git a/test_regress/t/t_hier_block_import/t_hier_block_import_def.vh b/test_regress/t/t_hier_block_import/t_hier_block_import_def.vh index e2877ac06..81709cdfe 100644 --- a/test_regress/t/t_hier_block_import/t_hier_block_import_def.vh +++ b/test_regress/t/t_hier_block_import/t_hier_block_import_def.vh @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // No include guards to validate if included once. diff --git a/test_regress/t/t_hier_block_import/t_hier_block_import_subA.v b/test_regress/t/t_hier_block_import/t_hier_block_import_subA.v index 770b57f67..5e8435380 100644 --- a/test_regress/t/t_hier_block_import/t_hier_block_import_subA.v +++ b/test_regress/t/t_hier_block_import/t_hier_block_import_subA.v @@ -1,11 +1,11 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module subA (output bit [31:0] out); /*verilator hier_block*/ - subsub subsub(.out(out)); + subsub subsub(.out(out)); endmodule diff --git a/test_regress/t/t_hier_block_import/t_hier_block_import_subB.v b/test_regress/t/t_hier_block_import/t_hier_block_import_subB.v index 3fb930bd8..37d0c6f28 100644 --- a/test_regress/t/t_hier_block_import/t_hier_block_import_subB.v +++ b/test_regress/t/t_hier_block_import/t_hier_block_import_subB.v @@ -1,12 +1,12 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // Note: no hier_block pragma here to validate partial hier_block design module subB (output bit [31:0] out); - assign out = `VALUE_B; + assign out = `VALUE_B; endmodule diff --git a/test_regress/t/t_hier_block_import/t_hier_block_import_subsub.v b/test_regress/t/t_hier_block_import/t_hier_block_import_subsub.v index 13d6d4014..e8a1dc59d 100644 --- a/test_regress/t/t_hier_block_import/t_hier_block_import_subsub.v +++ b/test_regress/t/t_hier_block_import/t_hier_block_import_subsub.v @@ -1,15 +1,15 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module subsub -#( - `include "t_hier_block_import.vh" -) -(output bit [31:0] out); /*verilator hier_block*/ - assign out = pt.PARAM_VALUE; +module subsub #( + `include "t_hier_block_import.vh" +) ( + output bit [31:0] out +); /*verilator hier_block*/ + assign out = pt.PARAM_VALUE; endmodule diff --git a/test_regress/t/t_hier_block_import_cmake.py b/test_regress/t/t_hier_block_import_cmake.py index 0f246454d..fb565ef8d 100755 --- a/test_regress/t/t_hier_block_import_cmake.py +++ b/test_regress/t/t_hier_block_import_cmake.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_int.py b/test_regress/t/t_hier_block_int.py index 0384eccd5..2377a6597 100755 --- a/test_regress/t/t_hier_block_int.py +++ b/test_regress/t/t_hier_block_int.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_int.v b/test_regress/t/t_hier_block_int.v index 8ff804d88..6738b53f9 100644 --- a/test_regress/t/t_hier_block_int.v +++ b/test_regress/t/t_hier_block_int.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2025 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_hier_block_libmod.py b/test_regress/t/t_hier_block_libmod.py index 7b78daf9c..6ab133aa1 100755 --- a/test_regress/t/t_hier_block_libmod.py +++ b/test_regress/t/t_hier_block_libmod.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_libmod.v b/test_regress/t/t_hier_block_libmod.v index 91a96da98..a32bb5e7f 100644 --- a/test_regress/t/t_hier_block_libmod.v +++ b/test_regress/t/t_hier_block_libmod.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Yutetsu TAKATSUKASA +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense module t; diff --git a/test_regress/t/t_hier_block_nohier.py b/test_regress/t/t_hier_block_nohier.py index 514491950..a5d3dd14e 100755 --- a/test_regress/t/t_hier_block_nohier.py +++ b/test_regress/t/t_hier_block_nohier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This test makes sure that the internal check of t_hier_block.v is correct. diff --git a/test_regress/t/t_hier_block_perf.py b/test_regress/t/t_hier_block_perf.py index e1dc4c9c9..d91e3475e 100755 --- a/test_regress/t/t_hier_block_perf.py +++ b/test_regress/t/t_hier_block_perf.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_perf.v b/test_regress/t/t_hier_block_perf.v index 03f7e0bfd..ab1ac4b80 100644 --- a/test_regress/t/t_hier_block_perf.v +++ b/test_regress/t/t_hier_block_perf.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // based on t_gate_ormux diff --git a/test_regress/t/t_hier_block_perf.vlt b/test_regress/t/t_hier_block_perf.vlt index 1f7e0240a..f676614ad 100644 --- a/test_regress/t/t_hier_block_perf.vlt +++ b/test_regress/t/t_hier_block_perf.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_hier_block_prot_lib.py b/test_regress/t/t_hier_block_prot_lib.py index b20c4eec4..32898dd0b 100755 --- a/test_regress/t/t_hier_block_prot_lib.py +++ b/test_regress/t/t_hier_block_prot_lib.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_prot_lib_shared.py b/test_regress/t/t_hier_block_prot_lib_shared.py index 09db88bb1..07162c019 100755 --- a/test_regress/t/t_hier_block_prot_lib_shared.py +++ b/test_regress/t/t_hier_block_prot_lib_shared.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_sc.py b/test_regress/t/t_hier_block_sc.py index 3660f8311..0baec1b0f 100755 --- a/test_regress/t/t_hier_block_sc.py +++ b/test_regress/t/t_hier_block_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_sc_trace_fst.out b/test_regress/t/t_hier_block_sc_trace_fst.out index 269d9bb2e..1ebd77252 100644 --- a/test_regress/t/t_hier_block_sc_trace_fst.out +++ b/test_regress/t/t_hier_block_sc_trace_fst.out @@ -1,5 +1,5 @@ $date - Mon Nov 10 12:31:08 2025 + Tue Feb 17 01:31:48 2026 $end $version @@ -10,1056 +10,771 @@ $timescale $end $scope module top $end $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 1 $end +$scope module stateless_pkg $end +$var parameter 32 ! ONE [31:0] $end +$upscope $end $scope module t $end -$var parameter 32 ! PARAM_A [31:0] $end -$var parameter 32 " PARAM_B [31:0] $end -$var wire 1 # clk $end -$var wire 8 $ out0 [7:0] $end -$var wire 8 % out1 [7:0] $end -$var wire 8 & out2 [7:0] $end -$var wire 8 ' out3 [7:0] $end -$var wire 8 ( out3_2 [7:0] $end -$var wire 8 ) out5 [7:0] $end -$var wire 8 * out6 [7:0] $end -$var int 32 + count [31:0] $end +$var parameter 32 " PARAM_A [31:0] $end +$var parameter 32 # PARAM_B [31:0] $end +$var wire 1 $ clk $end +$var wire 8 % out0 [7:0] $end +$var wire 8 & out1 [7:0] $end +$var wire 8 ' out2 [7:0] $end +$var wire 8 ( out3 [7:0] $end +$var wire 8 ) out3_2 [7:0] $end +$var wire 8 * out5 [7:0] $end +$var wire 8 + out6 [7:0] $end +$var int 32 , count [31:0] $end $scope module i_delay0 $end -$var parameter 32 , N [31:0] $end -$var parameter 32 - WIDTH [31:0] $end -$var wire 1 # clk $end -$var wire 8 ' in [7:0] $end -$var wire 8 ) out [7:0] $end -$var logic 8 . tmp [7:0] $end +$var parameter 32 - N [31:0] $end +$var parameter 32 . WIDTH [31:0] $end +$var wire 1 $ clk $end +$var wire 8 ( in [7:0] $end +$var wire 8 * out [7:0] $end +$var logic 8 / tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end -$var parameter 32 / N [31:0] $end -$var parameter 32 - WIDTH [31:0] $end -$var wire 1 # clk $end -$var wire 8 . in [7:0] $end -$var wire 8 ) out [7:0] $end -$var logic 8 ) tmp [7:0] $end -$upscope $end -$upscope $end -$upscope $end -$scope module i_delay1 $end $var parameter 32 0 N [31:0] $end -$var parameter 32 - WIDTH [31:0] $end -$var wire 1 # clk $end -$var wire 8 ) in [7:0] $end -$var wire 8 * out [7:0] $end -$var logic 8 1 tmp [7:0] $end -$scope module genblk1 $end -$scope module i_delay $end -$var parameter 32 , N [31:0] $end -$var parameter 32 - WIDTH [31:0] $end -$var wire 1 # clk $end -$var wire 8 1 in [7:0] $end -$var wire 8 * out [7:0] $end -$var logic 8 2 tmp [7:0] $end -$scope module genblk1 $end -$scope module i_delay $end -$var parameter 32 / N [31:0] $end -$var parameter 32 - WIDTH [31:0] $end -$var wire 1 # clk $end -$var wire 8 2 in [7:0] $end +$var parameter 32 . WIDTH [31:0] $end +$var wire 1 $ clk $end +$var wire 8 / in [7:0] $end $var wire 8 * out [7:0] $end $var logic 8 * tmp [7:0] $end $upscope $end $upscope $end $upscope $end +$scope module i_delay1 $end +$var parameter 32 1 N [31:0] $end +$var parameter 32 . WIDTH [31:0] $end +$var wire 1 $ clk $end +$var wire 8 * in [7:0] $end +$var wire 8 + out [7:0] $end +$var logic 8 2 tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var parameter 32 - N [31:0] $end +$var parameter 32 . WIDTH [31:0] $end +$var wire 1 $ clk $end +$var wire 8 2 in [7:0] $end +$var wire 8 + out [7:0] $end +$var logic 8 3 tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var parameter 32 0 N [31:0] $end +$var parameter 32 . WIDTH [31:0] $end +$var wire 1 $ clk $end +$var wire 8 3 in [7:0] $end +$var wire 8 + out [7:0] $end +$var logic 8 + tmp [7:0] $end +$upscope $end +$upscope $end +$upscope $end $upscope $end $upscope $end $scope module i_sub0 $end -$var wire 1 # clk $end -$var wire 8 ' in [7:0] $end -$var wire 8 $ out [7:0] $end +$var wire 1 $ clk $end +$var wire 8 ( in [7:0] $end +$var wire 8 % out [7:0] $end $scope module i_sub0 $end -$var wire 1 # clk $end -$var wire 8 ' in [7:0] $end -$var wire 8 $ out [7:0] $end +$var wire 1 4 clk $end +$var wire 8 5 in [7:0] $end +$var wire 8 6 out [7:0] $end +$var logic 8 7 ff [7:0] $end $upscope $end $upscope $end $scope module i_sub1 $end -$var wire 1 # clk $end -$var wire 8 $ in [11:4] $end -$var wire 8 % out [7:0] $end +$attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 2 $end +$var wire 1 8 clk $end +$var wire 8 9 in [11:4] $end +$var wire 8 : out [7:0] $end +$var logic 8 ; ff [7:0] $end +$attrbegin misc 07 "" 2 $end +$var logic 2 < enum_v [1:0] $end $upscope $end $scope module i_sub2 $end -$var wire 1 # clk $end -$var wire 8 % in [7:0] $end -$var wire 8 & out [7:0] $end -$upscope $end +$attrbegin misc 07 $unit::alt_enum_t 4 alt_enum_0 alt_enum_1 alt_enum_2 alt_enum_3 00 01 10 11 3 $end +$attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 4 $end +$var wire 1 = clk $end +$var wire 8 > in [7:0] $end +$var wire 8 ? out [7:0] $end +$var logic 8 @ ff [7:0] $end +$attrbegin misc 07 "" 3 $end +$var logic 2 A alt_enum_v [1:0] $end $scope module i_sub3 $end -$var parameter 8 3 P0 [7:0] $end -$var parameter 32 4 UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 5 UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 6 UNUSED [15:0] $end -$attrbegin misc 07 "" 1 $end -$var parameter 2 7 ENUM [1:0] $end -$var wire 1 # clk $end -$var wire 8 & in [7:0] $end -$var wire 8 ' out [7:0] $end -$var logic 8 8 ff [7:0] $end -$var wire 8 ' out4 [7:0] $end -$var wire 8 9 out4_2 [7:0] $end +$var wire 8 @ in_wire [7:0] $end +$var wire 8 B out_1 [7:0] $end +$var wire 8 C out_2 [7:0] $end +$scope module i_sub3 $end +$var parameter 8 D P0 [7:0] $end +$var parameter 32 E UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 F UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 G UNUSED [15:0] $end +$attrbegin misc 07 "" 4 $end +$var parameter 2 H ENUM [1:0] $end +$var wire 1 = clk $end +$var wire 8 @ in [7:0] $end +$var wire 8 B out [7:0] $end +$var logic 8 I ff [7:0] $end +$var wire 8 B out4 [7:0] $end +$var wire 8 J out4_2 [7:0] $end $scope module i_sub4_0 $end -$var parameter 32 : P0 [31:0] $end -$var real_parameter 64 ; P1 $end -$var real_parameter 64 < P3 $end -$var wire 1 # clk $end -$var wire 8 8 in [7:0] $end -$var wire 8 ' out [7:0] $end -$var logic 8 ' ff [7:0] $end -$var logic 128 = sub5_in[0][0] [127:0] $end -$var logic 128 > sub5_in[0][1] [127:0] $end -$var logic 128 ? sub5_in[0][2] [127:0] $end -$var logic 128 @ sub5_in[1][0] [127:0] $end -$var logic 128 A sub5_in[1][1] [127:0] $end -$var logic 128 B sub5_in[1][2] [127:0] $end -$var wire 8 C sub5_out[0][0] [7:0] $end -$var wire 8 D sub5_out[0][1] [7:0] $end -$var wire 8 E sub5_out[0][2] [7:0] $end -$var wire 8 F sub5_out[1][0] [7:0] $end -$var wire 8 G sub5_out[1][1] [7:0] $end -$var wire 8 H sub5_out[1][2] [7:0] $end -$var int 32 I count [31:0] $end -$var int 32 J driven_from_bind [31:0] $end +$var parameter 32 K P0 [31:0] $end +$var real_parameter 64 L P1 $end +$var real_parameter 64 M P3 $end +$var wire 1 = clk $end +$var wire 8 I in [7:0] $end +$var wire 8 B out [7:0] $end +$var logic 8 B ff [7:0] $end +$var logic 128 N sub5_in[0][0] [127:0] $end +$var logic 128 O sub5_in[0][1] [127:0] $end +$var logic 128 P sub5_in[0][2] [127:0] $end +$var logic 128 Q sub5_in[1][0] [127:0] $end +$var logic 128 R sub5_in[1][1] [127:0] $end +$var logic 128 S sub5_in[1][2] [127:0] $end +$var wire 8 T sub5_out[0][0] [7:0] $end +$var wire 8 U sub5_out[0][1] [7:0] $end +$var wire 8 V sub5_out[0][2] [7:0] $end +$var wire 8 W sub5_out[1][0] [7:0] $end +$var wire 8 X sub5_out[1][1] [7:0] $end +$var wire 8 Y sub5_out[1][2] [7:0] $end +$var int 32 Z count [31:0] $end +$var int 32 [ driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 ; P1 $end -$var wire 32 J driven_from_bind [31:0] $end +$var real_parameter 64 L P1 $end +$var wire 32 [ driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 # clk $end -$var wire 128 K in[0][0] [127:0] $end -$var wire 128 L in[0][1] [127:0] $end -$var wire 128 M in[0][2] [127:0] $end -$var wire 128 N in[1][0] [127:0] $end -$var wire 128 O in[1][1] [127:0] $end -$var wire 128 P in[1][2] [127:0] $end -$var wire 8 Q out[0][0] [7:0] $end -$var wire 8 R out[0][1] [7:0] $end -$var wire 8 S out[0][2] [7:0] $end -$var wire 8 T out[1][0] [7:0] $end -$var wire 8 U out[1][1] [7:0] $end -$var wire 8 V out[1][2] [7:0] $end +$var wire 1 = clk $end +$var wire 128 \ in[0][0] [127:0] $end +$var wire 128 ] in[0][1] [127:0] $end +$var wire 128 ^ in[0][2] [127:0] $end +$var wire 128 _ in[1][0] [127:0] $end +$var wire 128 ` in[1][1] [127:0] $end +$var wire 128 a in[1][2] [127:0] $end +$var wire 8 b out[0][0] [7:0] $end +$var wire 8 c out[0][1] [7:0] $end +$var wire 8 d out[0][2] [7:0] $end +$var wire 8 e out[1][0] [7:0] $end +$var wire 8 f out[1][1] [7:0] $end +$var wire 8 g out[1][2] [7:0] $end +$var int 32 h count [31:0] $end +$var wire 8 i val0[0] [7:0] $end +$var wire 8 j val0[1] [7:0] $end +$var wire 8 k val1[0] [7:0] $end +$var wire 8 l val1[1] [7:0] $end +$var wire 8 m val2[0] [7:0] $end +$var wire 8 n val2[1] [7:0] $end +$var wire 8 o val3[0] [7:0] $end +$var wire 8 p val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 s out[0] [7:0] $end +$var wire 8 t out[1] [7:0] $end $upscope $end -$scope module unnamedblk1 $end -$var int 32 W i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 X j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 Y exp [7:0] $end +$scope module i_sub1 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 u out[0] [7:0] $end +$var wire 8 v out[1] [7:0] $end $upscope $end +$scope module i_sub2 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 w out[0] [7:0] $end +$var wire 8 x out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 y P1 [31:0] $end +$var wire 8 z out[0] [7:0] $end +$var wire 8 { out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end -$var parameter 32 : P0 [31:0] $end -$var real_parameter 64 ; P1 $end -$var real_parameter 64 Z P3 $end -$var wire 1 # clk $end -$var wire 8 8 in [7:0] $end -$var wire 8 9 out [7:0] $end -$var logic 8 9 ff [7:0] $end -$var logic 128 [ sub5_in[0][0] [127:0] $end -$var logic 128 \ sub5_in[0][1] [127:0] $end -$var logic 128 ] sub5_in[0][2] [127:0] $end -$var logic 128 ^ sub5_in[1][0] [127:0] $end -$var logic 128 _ sub5_in[1][1] [127:0] $end -$var logic 128 ` sub5_in[1][2] [127:0] $end -$var wire 8 a sub5_out[0][0] [7:0] $end -$var wire 8 b sub5_out[0][1] [7:0] $end -$var wire 8 c sub5_out[0][2] [7:0] $end -$var wire 8 d sub5_out[1][0] [7:0] $end -$var wire 8 e sub5_out[1][1] [7:0] $end -$var wire 8 f sub5_out[1][2] [7:0] $end -$var int 32 g count [31:0] $end -$var int 32 h driven_from_bind [31:0] $end +$var parameter 32 K P0 [31:0] $end +$var real_parameter 64 L P1 $end +$var real_parameter 64 | P3 $end +$var wire 1 = clk $end +$var wire 8 I in [7:0] $end +$var wire 8 J out [7:0] $end +$var logic 8 J ff [7:0] $end +$var logic 128 } sub5_in[0][0] [127:0] $end +$var logic 128 ~ sub5_in[0][1] [127:0] $end +$var logic 128 !! sub5_in[0][2] [127:0] $end +$var logic 128 "! sub5_in[1][0] [127:0] $end +$var logic 128 #! sub5_in[1][1] [127:0] $end +$var logic 128 $! sub5_in[1][2] [127:0] $end +$var wire 8 %! sub5_out[0][0] [7:0] $end +$var wire 8 &! sub5_out[0][1] [7:0] $end +$var wire 8 '! sub5_out[0][2] [7:0] $end +$var wire 8 (! sub5_out[1][0] [7:0] $end +$var wire 8 )! sub5_out[1][1] [7:0] $end +$var wire 8 *! sub5_out[1][2] [7:0] $end +$var int 32 +! count [31:0] $end +$var int 32 ,! driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 ; P1 $end -$var wire 32 h driven_from_bind [31:0] $end +$var real_parameter 64 L P1 $end +$var wire 32 ,! driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 # clk $end -$var wire 128 i in[0][0] [127:0] $end -$var wire 128 j in[0][1] [127:0] $end -$var wire 128 k in[0][2] [127:0] $end -$var wire 128 l in[1][0] [127:0] $end -$var wire 128 m in[1][1] [127:0] $end -$var wire 128 n in[1][2] [127:0] $end -$var wire 8 o out[0][0] [7:0] $end -$var wire 8 p out[0][1] [7:0] $end -$var wire 8 q out[0][2] [7:0] $end -$var wire 8 r out[1][0] [7:0] $end -$var wire 8 s out[1][1] [7:0] $end -$var wire 8 t out[1][2] [7:0] $end +$var wire 1 = clk $end +$var wire 128 -! in[0][0] [127:0] $end +$var wire 128 .! in[0][1] [127:0] $end +$var wire 128 /! in[0][2] [127:0] $end +$var wire 128 0! in[1][0] [127:0] $end +$var wire 128 1! in[1][1] [127:0] $end +$var wire 128 2! in[1][2] [127:0] $end +$var wire 8 3! out[0][0] [7:0] $end +$var wire 8 4! out[0][1] [7:0] $end +$var wire 8 5! out[0][2] [7:0] $end +$var wire 8 6! out[1][0] [7:0] $end +$var wire 8 7! out[1][1] [7:0] $end +$var wire 8 8! out[1][2] [7:0] $end +$var int 32 9! count [31:0] $end +$var wire 8 :! val0[0] [7:0] $end +$var wire 8 ;! val0[1] [7:0] $end +$var wire 8 ! val2[0] [7:0] $end +$var wire 8 ?! val2[1] [7:0] $end +$var wire 8 @! val3[0] [7:0] $end +$var wire 8 A! val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 B! out[0] [7:0] $end +$var wire 8 C! out[1] [7:0] $end $upscope $end -$scope module unnamedblk1 $end -$var int 32 u i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 v j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 w exp [7:0] $end +$scope module i_sub1 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 D! out[0] [7:0] $end +$var wire 8 E! out[1] [7:0] $end $upscope $end +$scope module i_sub2 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 F! out[0] [7:0] $end +$var wire 8 G! out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 y P1 [31:0] $end +$var wire 8 H! out[0] [7:0] $end +$var wire 8 I! out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end -$var parameter 8 3 P0 [7:0] $end -$var parameter 32 x UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 y UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 6 UNUSED [15:0] $end -$attrbegin misc 07 "" 1 $end -$var parameter 2 7 ENUM [1:0] $end -$var wire 1 # clk $end -$var wire 8 & in [7:0] $end -$var wire 8 ( out [7:0] $end -$var logic 8 z ff [7:0] $end -$var wire 8 ( out4 [7:0] $end -$var wire 8 { out4_2 [7:0] $end +$var parameter 8 D P0 [7:0] $end +$var parameter 32 J! UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 K! UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 G UNUSED [15:0] $end +$attrbegin misc 07 "" 4 $end +$var parameter 2 H ENUM [1:0] $end +$var wire 1 = clk $end +$var wire 8 @ in [7:0] $end +$var wire 8 C out [7:0] $end +$var logic 8 L! ff [7:0] $end +$var wire 8 C out4 [7:0] $end +$var wire 8 M! out4_2 [7:0] $end $scope module i_sub4_0 $end -$var parameter 32 : P0 [31:0] $end -$var real_parameter 64 ; P1 $end -$var real_parameter 64 < P3 $end -$var wire 1 # clk $end -$var wire 8 z in [7:0] $end -$var wire 8 ( out [7:0] $end -$var logic 8 ( ff [7:0] $end -$var logic 128 | sub5_in[0][0] [127:0] $end -$var logic 128 } sub5_in[0][1] [127:0] $end -$var logic 128 ~ sub5_in[0][2] [127:0] $end -$var logic 128 !! sub5_in[1][0] [127:0] $end -$var logic 128 "! sub5_in[1][1] [127:0] $end -$var logic 128 #! sub5_in[1][2] [127:0] $end -$var wire 8 $! sub5_out[0][0] [7:0] $end -$var wire 8 %! sub5_out[0][1] [7:0] $end -$var wire 8 &! sub5_out[0][2] [7:0] $end -$var wire 8 '! sub5_out[1][0] [7:0] $end -$var wire 8 (! sub5_out[1][1] [7:0] $end -$var wire 8 )! sub5_out[1][2] [7:0] $end -$var int 32 *! count [31:0] $end -$var int 32 +! driven_from_bind [31:0] $end +$var parameter 32 K P0 [31:0] $end +$var real_parameter 64 L P1 $end +$var real_parameter 64 M P3 $end +$var wire 1 = clk $end +$var wire 8 L! in [7:0] $end +$var wire 8 C out [7:0] $end +$var logic 8 C ff [7:0] $end +$var logic 128 N! sub5_in[0][0] [127:0] $end +$var logic 128 O! sub5_in[0][1] [127:0] $end +$var logic 128 P! sub5_in[0][2] [127:0] $end +$var logic 128 Q! sub5_in[1][0] [127:0] $end +$var logic 128 R! sub5_in[1][1] [127:0] $end +$var logic 128 S! sub5_in[1][2] [127:0] $end +$var wire 8 T! sub5_out[0][0] [7:0] $end +$var wire 8 U! sub5_out[0][1] [7:0] $end +$var wire 8 V! sub5_out[0][2] [7:0] $end +$var wire 8 W! sub5_out[1][0] [7:0] $end +$var wire 8 X! sub5_out[1][1] [7:0] $end +$var wire 8 Y! sub5_out[1][2] [7:0] $end +$var int 32 Z! count [31:0] $end +$var int 32 [! driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 ; P1 $end -$var wire 32 +! driven_from_bind [31:0] $end +$var real_parameter 64 L P1 $end +$var wire 32 [! driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 # clk $end -$var wire 128 ,! in[0][0] [127:0] $end -$var wire 128 -! in[0][1] [127:0] $end -$var wire 128 .! in[0][2] [127:0] $end -$var wire 128 /! in[1][0] [127:0] $end -$var wire 128 0! in[1][1] [127:0] $end -$var wire 128 1! in[1][2] [127:0] $end -$var wire 8 2! out[0][0] [7:0] $end -$var wire 8 3! out[0][1] [7:0] $end -$var wire 8 4! out[0][2] [7:0] $end -$var wire 8 5! out[1][0] [7:0] $end -$var wire 8 6! out[1][1] [7:0] $end -$var wire 8 7! out[1][2] [7:0] $end +$var wire 1 = clk $end +$var wire 128 \! in[0][0] [127:0] $end +$var wire 128 ]! in[0][1] [127:0] $end +$var wire 128 ^! in[0][2] [127:0] $end +$var wire 128 _! in[1][0] [127:0] $end +$var wire 128 `! in[1][1] [127:0] $end +$var wire 128 a! in[1][2] [127:0] $end +$var wire 8 b! out[0][0] [7:0] $end +$var wire 8 c! out[0][1] [7:0] $end +$var wire 8 d! out[0][2] [7:0] $end +$var wire 8 e! out[1][0] [7:0] $end +$var wire 8 f! out[1][1] [7:0] $end +$var wire 8 g! out[1][2] [7:0] $end +$var int 32 h! count [31:0] $end +$var wire 8 i! val0[0] [7:0] $end +$var wire 8 j! val0[1] [7:0] $end +$var wire 8 k! val1[0] [7:0] $end +$var wire 8 l! val1[1] [7:0] $end +$var wire 8 m! val2[0] [7:0] $end +$var wire 8 n! val2[1] [7:0] $end +$var wire 8 o! val3[0] [7:0] $end +$var wire 8 p! val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 q! out[0] [7:0] $end +$var wire 8 r! out[1] [7:0] $end $upscope $end -$scope module unnamedblk1 $end -$var int 32 8! i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 9! j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 :! exp [7:0] $end +$scope module i_sub1 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 s! out[0] [7:0] $end +$var wire 8 t! out[1] [7:0] $end $upscope $end +$scope module i_sub2 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 u! out[0] [7:0] $end +$var wire 8 v! out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 y P1 [31:0] $end +$var wire 8 w! out[0] [7:0] $end +$var wire 8 x! out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end -$var parameter 32 : P0 [31:0] $end -$var real_parameter 64 ; P1 $end -$var real_parameter 64 Z P3 $end -$var wire 1 # clk $end -$var wire 8 z in [7:0] $end -$var wire 8 { out [7:0] $end -$var logic 8 { ff [7:0] $end -$var logic 128 ;! sub5_in[0][0] [127:0] $end -$var logic 128 ! sub5_in[1][0] [127:0] $end -$var logic 128 ?! sub5_in[1][1] [127:0] $end -$var logic 128 @! sub5_in[1][2] [127:0] $end -$var wire 8 A! sub5_out[0][0] [7:0] $end -$var wire 8 B! sub5_out[0][1] [7:0] $end -$var wire 8 C! sub5_out[0][2] [7:0] $end -$var wire 8 D! sub5_out[1][0] [7:0] $end -$var wire 8 E! sub5_out[1][1] [7:0] $end -$var wire 8 F! sub5_out[1][2] [7:0] $end -$var int 32 G! count [31:0] $end -$var int 32 H! driven_from_bind [31:0] $end +$var parameter 32 K P0 [31:0] $end +$var real_parameter 64 L P1 $end +$var real_parameter 64 | P3 $end +$var wire 1 = clk $end +$var wire 8 L! in [7:0] $end +$var wire 8 M! out [7:0] $end +$var logic 8 M! ff [7:0] $end +$var logic 128 y! sub5_in[0][0] [127:0] $end +$var logic 128 z! sub5_in[0][1] [127:0] $end +$var logic 128 {! sub5_in[0][2] [127:0] $end +$var logic 128 |! sub5_in[1][0] [127:0] $end +$var logic 128 }! sub5_in[1][1] [127:0] $end +$var logic 128 ~! sub5_in[1][2] [127:0] $end +$var wire 8 !" sub5_out[0][0] [7:0] $end +$var wire 8 "" sub5_out[0][1] [7:0] $end +$var wire 8 #" sub5_out[0][2] [7:0] $end +$var wire 8 $" sub5_out[1][0] [7:0] $end +$var wire 8 %" sub5_out[1][1] [7:0] $end +$var wire 8 &" sub5_out[1][2] [7:0] $end +$var int 32 '" count [31:0] $end +$var int 32 (" driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 ; P1 $end -$var wire 32 H! driven_from_bind [31:0] $end +$var real_parameter 64 L P1 $end +$var wire 32 (" driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 # clk $end -$var wire 128 I! in[0][0] [127:0] $end -$var wire 128 J! in[0][1] [127:0] $end -$var wire 128 K! in[0][2] [127:0] $end -$var wire 128 L! in[1][0] [127:0] $end -$var wire 128 M! in[1][1] [127:0] $end -$var wire 128 N! in[1][2] [127:0] $end -$var wire 8 O! out[0][0] [7:0] $end -$var wire 8 P! out[0][1] [7:0] $end -$var wire 8 Q! out[0][2] [7:0] $end -$var wire 8 R! out[1][0] [7:0] $end -$var wire 8 S! out[1][1] [7:0] $end -$var wire 8 T! out[1][2] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 U! i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 V! j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 W! exp [7:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module top.t.i_sub0.i_sub0 $end -$var wire 1 X! clk $end -$var wire 8 Y! in [7:0] $end -$var wire 8 Z! out [7:0] $end -$scope module sub0 $end -$var wire 1 X! clk $end -$var wire 8 Y! in [7:0] $end -$var wire 8 Z! out [7:0] $end -$var logic 8 [! ff [7:0] $end -$upscope $end -$upscope $end -$scope module top.t.i_sub1 $end -$var wire 1 \! clk $end -$var wire 8 ]! in [11:4] $end -$var wire 8 ^! out [7:0] $end -$scope module sub1 $end -$var wire 1 \! clk $end -$var wire 8 ]! in [11:4] $end -$var wire 8 ^! out [7:0] $end -$var logic 8 _! ff [7:0] $end -$upscope $end -$upscope $end -$scope module top.t.i_sub2 $end -$attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 2 $end -$var wire 1 `! clk $end -$var wire 8 a! in [7:0] $end -$var wire 8 b! out [7:0] $end -$scope module sub2 $end -$var wire 1 `! clk $end -$var wire 8 a! in [7:0] $end -$var wire 8 b! out [7:0] $end -$var logic 8 c! ff [7:0] $end -$scope interface in_ifs $end -$var wire 1 `! clk $end -$var logic 8 c! data [7:0] $end -$upscope $end -$scope interface out_ifs $end -$var wire 1 `! clk $end -$var logic 8 d! data [7:0] $end -$upscope $end -$scope module i_sub3 $end -$scope interface in $end -$var wire 1 `! clk $end -$var logic 8 c! data [7:0] $end -$upscope $end -$scope interface out $end -$var wire 1 `! clk $end -$var logic 8 d! data [7:0] $end -$upscope $end -$var wire 8 c! in_wire [7:0] $end -$var wire 8 d! out_1 [7:0] $end -$var wire 8 e! out_2 [7:0] $end -$scope module i_sub3 $end -$var parameter 8 f! P0 [7:0] $end -$var parameter 32 g! UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 h! UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 i! UNUSED [15:0] $end -$attrbegin misc 07 "" 2 $end -$var parameter 2 j! ENUM [1:0] $end -$var wire 1 `! clk $end -$var wire 8 c! in [7:0] $end -$var wire 8 d! out [7:0] $end -$var logic 8 k! ff [7:0] $end -$var wire 8 d! out4 [7:0] $end -$var wire 8 l! out4_2 [7:0] $end -$scope module i_sub4_0 $end -$var parameter 32 m! P0 [31:0] $end -$var real_parameter 64 n! P1 $end -$var real_parameter 64 o! P3 $end -$var wire 1 `! clk $end -$var wire 8 k! in [7:0] $end -$var wire 8 d! out [7:0] $end -$var logic 8 d! ff [7:0] $end -$var logic 128 p! sub5_in[0][0] [127:0] $end -$var logic 128 q! sub5_in[0][1] [127:0] $end -$var logic 128 r! sub5_in[0][2] [127:0] $end -$var logic 128 s! sub5_in[1][0] [127:0] $end -$var logic 128 t! sub5_in[1][1] [127:0] $end -$var logic 128 u! sub5_in[1][2] [127:0] $end -$var wire 8 v! sub5_out[0][0] [7:0] $end -$var wire 8 w! sub5_out[0][1] [7:0] $end -$var wire 8 x! sub5_out[0][2] [7:0] $end -$var wire 8 y! sub5_out[1][0] [7:0] $end -$var wire 8 z! sub5_out[1][1] [7:0] $end -$var wire 8 {! sub5_out[1][2] [7:0] $end -$var int 32 |! count [31:0] $end -$var int 32 }! driven_from_bind [31:0] $end -$scope module i_sub4_bound $end -$var real_parameter 64 n! P1 $end -$var wire 32 }! driven_from_bind [31:0] $end -$upscope $end -$scope module i_sub5 $end -$var wire 1 `! clk $end -$var wire 128 ~! in[0][0] [127:0] $end -$var wire 128 !" in[0][1] [127:0] $end -$var wire 128 "" in[0][2] [127:0] $end -$var wire 128 #" in[1][0] [127:0] $end -$var wire 128 $" in[1][1] [127:0] $end -$var wire 128 %" in[1][2] [127:0] $end -$var wire 8 &" out[0][0] [7:0] $end -$var wire 8 '" out[0][1] [7:0] $end -$var wire 8 (" out[0][2] [7:0] $end -$var wire 8 )" out[1][0] [7:0] $end -$var wire 8 *" out[1][1] [7:0] $end -$var wire 8 +" out[1][2] [7:0] $end -$var int 32 ," count [31:0] $end -$var wire 8 -" val0[0] [7:0] $end -$var wire 8 ." val0[1] [7:0] $end -$var wire 8 /" val1[0] [7:0] $end -$var wire 8 0" val1[1] [7:0] $end -$var wire 8 1" val2[0] [7:0] $end -$var wire 8 2" val2[1] [7:0] $end -$var wire 8 3" val3[0] [7:0] $end -$var wire 8 4" val3[1] [7:0] $end +$var wire 1 = clk $end +$var wire 128 )" in[0][0] [127:0] $end +$var wire 128 *" in[0][1] [127:0] $end +$var wire 128 +" in[0][2] [127:0] $end +$var wire 128 ," in[1][0] [127:0] $end +$var wire 128 -" in[1][1] [127:0] $end +$var wire 128 ." in[1][2] [127:0] $end +$var wire 8 /" out[0][0] [7:0] $end +$var wire 8 0" out[0][1] [7:0] $end +$var wire 8 1" out[0][2] [7:0] $end +$var wire 8 2" out[1][0] [7:0] $end +$var wire 8 3" out[1][1] [7:0] $end +$var wire 8 4" out[1][2] [7:0] $end +$var int 32 5" count [31:0] $end +$var wire 8 6" val0[0] [7:0] $end +$var wire 8 7" val0[1] [7:0] $end +$var wire 8 8" val1[0] [7:0] $end +$var wire 8 9" val1[1] [7:0] $end +$var wire 8 :" val2[0] [7:0] $end +$var wire 8 ;" val2[1] [7:0] $end +$var wire 8 <" val3[0] [7:0] $end +$var wire 8 =" val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 7" out[0] [7:0] $end -$var wire 8 8" out[1] [7:0] $end -$upscope $end -$scope module i_sub1 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 9" out[0] [7:0] $end -$var wire 8 :" out[1] [7:0] $end -$upscope $end -$scope module i_sub2 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 ;" out[0] [7:0] $end -$var wire 8 <" out[1] [7:0] $end -$upscope $end -$scope module i_sub3 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 =" P1 [31:0] $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end $var wire 8 >" out[0] [7:0] $end $var wire 8 ?" out[1] [7:0] $end $upscope $end -$scope module unnamedblk1 $end -$var int 32 @" i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 A" j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 B" exp [127:0] $end +$scope module i_sub1 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 @" out[0] [7:0] $end +$var wire 8 A" out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 r P1 [31:0] $end +$var wire 8 B" out[0] [7:0] $end +$var wire 8 C" out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var parameter 32 q P0 [31:0] $end +$var parameter 32 y P1 [31:0] $end +$var wire 8 D" out[0] [7:0] $end +$var wire 8 E" out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end -$scope module unnamedblk1 $end -$var int 32 C" i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 D" j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 E" exp [7:0] $end +$scope interface in $end +$var wire 1 = clk $end +$var logic 8 @ data [7:0] $end $upscope $end +$scope interface out $end +$var wire 1 = clk $end +$var logic 8 B data [7:0] $end +$upscope $end +$upscope $end +$scope interface in_ifs $end +$var wire 1 = clk $end +$var logic 8 @ data [7:0] $end +$upscope $end +$scope interface out_ifs $end +$var wire 1 = clk $end +$var logic 8 B data [7:0] $end +$upscope $end +$upscope $end +$scope module i_sub3 $end +$var parameter 8 F" P0 [7:0] $end +$var parameter 32 G" UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 H" UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 I" UNUSED [15:0] $end +$attrbegin misc 07 "" 1 $end +$var parameter 2 J" ENUM [1:0] $end +$var wire 1 $ clk $end +$var wire 8 ' in [7:0] $end +$var wire 8 ( out [7:0] $end +$var logic 8 K" ff [7:0] $end +$var wire 8 ( out4 [7:0] $end +$var wire 8 L" out4_2 [7:0] $end +$scope module i_sub4_0 $end +$var parameter 32 M" P0 [31:0] $end +$var real_parameter 64 N" P1 $end +$var real_parameter 64 O" P3 $end +$var wire 1 $ clk $end +$var wire 8 K" in [7:0] $end +$var wire 8 ( out [7:0] $end +$var logic 8 ( ff [7:0] $end +$var logic 128 P" sub5_in[0][0] [127:0] $end +$var logic 128 Q" sub5_in[0][1] [127:0] $end +$var logic 128 R" sub5_in[0][2] [127:0] $end +$var logic 128 S" sub5_in[1][0] [127:0] $end +$var logic 128 T" sub5_in[1][1] [127:0] $end +$var logic 128 U" sub5_in[1][2] [127:0] $end +$var wire 8 V" sub5_out[0][0] [7:0] $end +$var wire 8 W" sub5_out[0][1] [7:0] $end +$var wire 8 X" sub5_out[0][2] [7:0] $end +$var wire 8 Y" sub5_out[1][0] [7:0] $end +$var wire 8 Z" sub5_out[1][1] [7:0] $end +$var wire 8 [" sub5_out[1][2] [7:0] $end +$var int 32 \" count [31:0] $end +$var int 32 ]" driven_from_bind [31:0] $end +$scope module i_sub4_bound $end +$var real_parameter 64 N" P1 $end +$var wire 32 ]" driven_from_bind [31:0] $end +$upscope $end +$scope module i_sub5 $end +$var wire 1 ^" clk $end +$var wire 128 _" in[0][0] [127:0] $end +$var wire 128 `" in[0][1] [127:0] $end +$var wire 128 a" in[0][2] [127:0] $end +$var wire 128 b" in[1][0] [127:0] $end +$var wire 128 c" in[1][1] [127:0] $end +$var wire 128 d" in[1][2] [127:0] $end +$var wire 8 e" out[0][0] [7:0] $end +$var wire 8 f" out[0][1] [7:0] $end +$var wire 8 g" out[0][2] [7:0] $end +$var wire 8 h" out[1][0] [7:0] $end +$var wire 8 i" out[1][1] [7:0] $end +$var wire 8 j" out[1][2] [7:0] $end +$var int 32 k" count [31:0] $end +$var wire 8 l" val0[0] [7:0] $end +$var wire 8 m" val0[1] [7:0] $end +$var wire 8 n" val1[0] [7:0] $end +$var wire 8 o" val1[1] [7:0] $end +$var wire 8 p" val2[0] [7:0] $end +$var wire 8 q" val2[1] [7:0] $end +$var wire 8 r" val3[0] [7:0] $end +$var wire 8 s" val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 t" P0 [31:0] $end +$var parameter 32 u" P1 [31:0] $end +$var wire 8 v" out[0] [7:0] $end +$var wire 8 w" out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 t" P0 [31:0] $end +$var parameter 32 u" P1 [31:0] $end +$var wire 8 x" out[0] [7:0] $end +$var wire 8 y" out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 t" P0 [31:0] $end +$var parameter 32 u" P1 [31:0] $end +$var wire 8 z" out[0] [7:0] $end +$var wire 8 {" out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var parameter 32 t" P0 [31:0] $end +$var parameter 32 |" P1 [31:0] $end +$var wire 8 }" out[0] [7:0] $end +$var wire 8 ~" out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end -$var parameter 32 m! P0 [31:0] $end -$var real_parameter 64 n! P1 $end -$var real_parameter 64 F" P3 $end -$var wire 1 `! clk $end -$var wire 8 k! in [7:0] $end -$var wire 8 l! out [7:0] $end -$var logic 8 l! ff [7:0] $end -$var logic 128 G" sub5_in[0][0] [127:0] $end -$var logic 128 H" sub5_in[0][1] [127:0] $end -$var logic 128 I" sub5_in[0][2] [127:0] $end -$var logic 128 J" sub5_in[1][0] [127:0] $end -$var logic 128 K" sub5_in[1][1] [127:0] $end -$var logic 128 L" sub5_in[1][2] [127:0] $end -$var wire 8 M" sub5_out[0][0] [7:0] $end -$var wire 8 N" sub5_out[0][1] [7:0] $end -$var wire 8 O" sub5_out[0][2] [7:0] $end -$var wire 8 P" sub5_out[1][0] [7:0] $end -$var wire 8 Q" sub5_out[1][1] [7:0] $end -$var wire 8 R" sub5_out[1][2] [7:0] $end -$var int 32 S" count [31:0] $end -$var int 32 T" driven_from_bind [31:0] $end +$var parameter 32 M" P0 [31:0] $end +$var real_parameter 64 N" P1 $end +$var real_parameter 64 !# P3 $end +$var wire 1 $ clk $end +$var wire 8 K" in [7:0] $end +$var wire 8 L" out [7:0] $end +$var logic 8 L" ff [7:0] $end +$var logic 128 "# sub5_in[0][0] [127:0] $end +$var logic 128 ## sub5_in[0][1] [127:0] $end +$var logic 128 $# sub5_in[0][2] [127:0] $end +$var logic 128 %# sub5_in[1][0] [127:0] $end +$var logic 128 &# sub5_in[1][1] [127:0] $end +$var logic 128 '# sub5_in[1][2] [127:0] $end +$var wire 8 (# sub5_out[0][0] [7:0] $end +$var wire 8 )# sub5_out[0][1] [7:0] $end +$var wire 8 *# sub5_out[0][2] [7:0] $end +$var wire 8 +# sub5_out[1][0] [7:0] $end +$var wire 8 ,# sub5_out[1][1] [7:0] $end +$var wire 8 -# sub5_out[1][2] [7:0] $end +$var int 32 .# count [31:0] $end +$var int 32 /# driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 n! P1 $end -$var wire 32 T" driven_from_bind [31:0] $end +$var real_parameter 64 N" P1 $end +$var wire 32 /# driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 `! clk $end -$var wire 128 U" in[0][0] [127:0] $end -$var wire 128 V" in[0][1] [127:0] $end -$var wire 128 W" in[0][2] [127:0] $end -$var wire 128 X" in[1][0] [127:0] $end -$var wire 128 Y" in[1][1] [127:0] $end -$var wire 128 Z" in[1][2] [127:0] $end -$var wire 8 [" out[0][0] [7:0] $end -$var wire 8 \" out[0][1] [7:0] $end -$var wire 8 ]" out[0][2] [7:0] $end -$var wire 8 ^" out[1][0] [7:0] $end -$var wire 8 _" out[1][1] [7:0] $end -$var wire 8 `" out[1][2] [7:0] $end -$var int 32 a" count [31:0] $end -$var wire 8 b" val0[0] [7:0] $end -$var wire 8 c" val0[1] [7:0] $end -$var wire 8 d" val1[0] [7:0] $end -$var wire 8 e" val1[1] [7:0] $end -$var wire 8 f" val2[0] [7:0] $end -$var wire 8 g" val2[1] [7:0] $end -$var wire 8 h" val3[0] [7:0] $end -$var wire 8 i" val3[1] [7:0] $end +$var wire 1 0# clk $end +$var wire 128 1# in[0][0] [127:0] $end +$var wire 128 2# in[0][1] [127:0] $end +$var wire 128 3# in[0][2] [127:0] $end +$var wire 128 4# in[1][0] [127:0] $end +$var wire 128 5# in[1][1] [127:0] $end +$var wire 128 6# in[1][2] [127:0] $end +$var wire 8 7# out[0][0] [7:0] $end +$var wire 8 8# out[0][1] [7:0] $end +$var wire 8 9# out[0][2] [7:0] $end +$var wire 8 :# out[1][0] [7:0] $end +$var wire 8 ;# out[1][1] [7:0] $end +$var wire 8 <# out[1][2] [7:0] $end +$var int 32 =# count [31:0] $end +$var wire 8 ># val0[0] [7:0] $end +$var wire 8 ?# val0[1] [7:0] $end +$var wire 8 @# val1[0] [7:0] $end +$var wire 8 A# val1[1] [7:0] $end +$var wire 8 B# val2[0] [7:0] $end +$var wire 8 C# val2[1] [7:0] $end +$var wire 8 D# val3[0] [7:0] $end +$var wire 8 E# val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 j" out[0] [7:0] $end -$var wire 8 k" out[1] [7:0] $end +$var parameter 32 F# P0 [31:0] $end +$var parameter 32 G# P1 [31:0] $end +$var wire 8 H# out[0] [7:0] $end +$var wire 8 I# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 l" out[0] [7:0] $end -$var wire 8 m" out[1] [7:0] $end +$var parameter 32 F# P0 [31:0] $end +$var parameter 32 G# P1 [31:0] $end +$var wire 8 J# out[0] [7:0] $end +$var wire 8 K# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 n" out[0] [7:0] $end -$var wire 8 o" out[1] [7:0] $end +$var parameter 32 F# P0 [31:0] $end +$var parameter 32 G# P1 [31:0] $end +$var wire 8 L# out[0] [7:0] $end +$var wire 8 M# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 =" P1 [31:0] $end -$var wire 8 p" out[0] [7:0] $end -$var wire 8 q" out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 r" i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 s" j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 t" exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 u" i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 v" j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 w" exp [7:0] $end -$upscope $end +$var parameter 32 F# P0 [31:0] $end +$var parameter 32 N# P1 [31:0] $end +$var wire 8 O# out[0] [7:0] $end +$var wire 8 P# out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end -$var parameter 8 f! P0 [7:0] $end -$var parameter 32 x" UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 y" UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 i! UNUSED [15:0] $end -$attrbegin misc 07 "" 2 $end -$var parameter 2 j! ENUM [1:0] $end -$var wire 1 `! clk $end -$var wire 8 c! in [7:0] $end -$var wire 8 e! out [7:0] $end -$var logic 8 z" ff [7:0] $end -$var wire 8 e! out4 [7:0] $end -$var wire 8 {" out4_2 [7:0] $end +$var parameter 8 F" P0 [7:0] $end +$var parameter 32 Q# UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 R# UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 I" UNUSED [15:0] $end +$attrbegin misc 07 "" 1 $end +$var parameter 2 J" ENUM [1:0] $end +$var wire 1 $ clk $end +$var wire 8 ' in [7:0] $end +$var wire 8 ) out [7:0] $end +$var logic 8 S# ff [7:0] $end +$var wire 8 ) out4 [7:0] $end +$var wire 8 T# out4_2 [7:0] $end $scope module i_sub4_0 $end -$var parameter 32 m! P0 [31:0] $end -$var real_parameter 64 n! P1 $end -$var real_parameter 64 o! P3 $end -$var wire 1 `! clk $end -$var wire 8 z" in [7:0] $end -$var wire 8 e! out [7:0] $end -$var logic 8 e! ff [7:0] $end -$var logic 128 |" sub5_in[0][0] [127:0] $end -$var logic 128 }" sub5_in[0][1] [127:0] $end -$var logic 128 ~" sub5_in[0][2] [127:0] $end -$var logic 128 !# sub5_in[1][0] [127:0] $end -$var logic 128 "# sub5_in[1][1] [127:0] $end -$var logic 128 ## sub5_in[1][2] [127:0] $end -$var wire 8 $# sub5_out[0][0] [7:0] $end -$var wire 8 %# sub5_out[0][1] [7:0] $end -$var wire 8 &# sub5_out[0][2] [7:0] $end -$var wire 8 '# sub5_out[1][0] [7:0] $end -$var wire 8 (# sub5_out[1][1] [7:0] $end -$var wire 8 )# sub5_out[1][2] [7:0] $end -$var int 32 *# count [31:0] $end -$var int 32 +# driven_from_bind [31:0] $end +$var parameter 32 M" P0 [31:0] $end +$var real_parameter 64 N" P1 $end +$var real_parameter 64 O" P3 $end +$var wire 1 $ clk $end +$var wire 8 S# in [7:0] $end +$var wire 8 ) out [7:0] $end +$var logic 8 ) ff [7:0] $end +$var logic 128 U# sub5_in[0][0] [127:0] $end +$var logic 128 V# sub5_in[0][1] [127:0] $end +$var logic 128 W# sub5_in[0][2] [127:0] $end +$var logic 128 X# sub5_in[1][0] [127:0] $end +$var logic 128 Y# sub5_in[1][1] [127:0] $end +$var logic 128 Z# sub5_in[1][2] [127:0] $end +$var wire 8 [# sub5_out[0][0] [7:0] $end +$var wire 8 \# sub5_out[0][1] [7:0] $end +$var wire 8 ]# sub5_out[0][2] [7:0] $end +$var wire 8 ^# sub5_out[1][0] [7:0] $end +$var wire 8 _# sub5_out[1][1] [7:0] $end +$var wire 8 `# sub5_out[1][2] [7:0] $end +$var int 32 a# count [31:0] $end +$var int 32 b# driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 n! P1 $end -$var wire 32 +# driven_from_bind [31:0] $end +$var real_parameter 64 N" P1 $end +$var wire 32 b# driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 `! clk $end -$var wire 128 ,# in[0][0] [127:0] $end -$var wire 128 -# in[0][1] [127:0] $end -$var wire 128 .# in[0][2] [127:0] $end -$var wire 128 /# in[1][0] [127:0] $end -$var wire 128 0# in[1][1] [127:0] $end -$var wire 128 1# in[1][2] [127:0] $end -$var wire 8 2# out[0][0] [7:0] $end -$var wire 8 3# out[0][1] [7:0] $end -$var wire 8 4# out[0][2] [7:0] $end -$var wire 8 5# out[1][0] [7:0] $end -$var wire 8 6# out[1][1] [7:0] $end -$var wire 8 7# out[1][2] [7:0] $end -$var int 32 8# count [31:0] $end -$var wire 8 9# val0[0] [7:0] $end -$var wire 8 :# val0[1] [7:0] $end -$var wire 8 ;# val1[0] [7:0] $end -$var wire 8 <# val1[1] [7:0] $end -$var wire 8 =# val2[0] [7:0] $end -$var wire 8 ># val2[1] [7:0] $end -$var wire 8 ?# val3[0] [7:0] $end -$var wire 8 @# val3[1] [7:0] $end +$var wire 1 c# clk $end +$var wire 128 d# in[0][0] [127:0] $end +$var wire 128 e# in[0][1] [127:0] $end +$var wire 128 f# in[0][2] [127:0] $end +$var wire 128 g# in[1][0] [127:0] $end +$var wire 128 h# in[1][1] [127:0] $end +$var wire 128 i# in[1][2] [127:0] $end +$var wire 8 j# out[0][0] [7:0] $end +$var wire 8 k# out[0][1] [7:0] $end +$var wire 8 l# out[0][2] [7:0] $end +$var wire 8 m# out[1][0] [7:0] $end +$var wire 8 n# out[1][1] [7:0] $end +$var wire 8 o# out[1][2] [7:0] $end +$var int 32 p# count [31:0] $end +$var wire 8 q# val0[0] [7:0] $end +$var wire 8 r# val0[1] [7:0] $end +$var wire 8 s# val1[0] [7:0] $end +$var wire 8 t# val1[1] [7:0] $end +$var wire 8 u# val2[0] [7:0] $end +$var wire 8 v# val2[1] [7:0] $end +$var wire 8 w# val3[0] [7:0] $end +$var wire 8 x# val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 A# out[0] [7:0] $end -$var wire 8 B# out[1] [7:0] $end +$var parameter 32 y# P0 [31:0] $end +$var parameter 32 z# P1 [31:0] $end +$var wire 8 {# out[0] [7:0] $end +$var wire 8 |# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 C# out[0] [7:0] $end -$var wire 8 D# out[1] [7:0] $end +$var parameter 32 y# P0 [31:0] $end +$var parameter 32 z# P1 [31:0] $end +$var wire 8 }# out[0] [7:0] $end +$var wire 8 ~# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 E# out[0] [7:0] $end -$var wire 8 F# out[1] [7:0] $end +$var parameter 32 y# P0 [31:0] $end +$var parameter 32 z# P1 [31:0] $end +$var wire 8 !$ out[0] [7:0] $end +$var wire 8 "$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 =" P1 [31:0] $end -$var wire 8 G# out[0] [7:0] $end -$var wire 8 H# out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 I# i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 J# j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 K# exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 L# i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 M# j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 N# exp [7:0] $end -$upscope $end +$var parameter 32 y# P0 [31:0] $end +$var parameter 32 #$ P1 [31:0] $end +$var wire 8 $$ out[0] [7:0] $end +$var wire 8 %$ out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end -$var parameter 32 m! P0 [31:0] $end -$var real_parameter 64 n! P1 $end -$var real_parameter 64 F" P3 $end -$var wire 1 `! clk $end -$var wire 8 z" in [7:0] $end -$var wire 8 {" out [7:0] $end -$var logic 8 {" ff [7:0] $end -$var logic 128 O# sub5_in[0][0] [127:0] $end -$var logic 128 P# sub5_in[0][1] [127:0] $end -$var logic 128 Q# sub5_in[0][2] [127:0] $end -$var logic 128 R# sub5_in[1][0] [127:0] $end -$var logic 128 S# sub5_in[1][1] [127:0] $end -$var logic 128 T# sub5_in[1][2] [127:0] $end -$var wire 8 U# sub5_out[0][0] [7:0] $end -$var wire 8 V# sub5_out[0][1] [7:0] $end -$var wire 8 W# sub5_out[0][2] [7:0] $end -$var wire 8 X# sub5_out[1][0] [7:0] $end -$var wire 8 Y# sub5_out[1][1] [7:0] $end -$var wire 8 Z# sub5_out[1][2] [7:0] $end -$var int 32 [# count [31:0] $end -$var int 32 \# driven_from_bind [31:0] $end +$var parameter 32 M" P0 [31:0] $end +$var real_parameter 64 N" P1 $end +$var real_parameter 64 !# P3 $end +$var wire 1 $ clk $end +$var wire 8 S# in [7:0] $end +$var wire 8 T# out [7:0] $end +$var logic 8 T# ff [7:0] $end +$var logic 128 &$ sub5_in[0][0] [127:0] $end +$var logic 128 '$ sub5_in[0][1] [127:0] $end +$var logic 128 ($ sub5_in[0][2] [127:0] $end +$var logic 128 )$ sub5_in[1][0] [127:0] $end +$var logic 128 *$ sub5_in[1][1] [127:0] $end +$var logic 128 +$ sub5_in[1][2] [127:0] $end +$var wire 8 ,$ sub5_out[0][0] [7:0] $end +$var wire 8 -$ sub5_out[0][1] [7:0] $end +$var wire 8 .$ sub5_out[0][2] [7:0] $end +$var wire 8 /$ sub5_out[1][0] [7:0] $end +$var wire 8 0$ sub5_out[1][1] [7:0] $end +$var wire 8 1$ sub5_out[1][2] [7:0] $end +$var int 32 2$ count [31:0] $end +$var int 32 3$ driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 n! P1 $end -$var wire 32 \# driven_from_bind [31:0] $end +$var real_parameter 64 N" P1 $end +$var wire 32 3$ driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 `! clk $end -$var wire 128 ]# in[0][0] [127:0] $end -$var wire 128 ^# in[0][1] [127:0] $end -$var wire 128 _# in[0][2] [127:0] $end -$var wire 128 `# in[1][0] [127:0] $end -$var wire 128 a# in[1][1] [127:0] $end -$var wire 128 b# in[1][2] [127:0] $end -$var wire 8 c# out[0][0] [7:0] $end -$var wire 8 d# out[0][1] [7:0] $end -$var wire 8 e# out[0][2] [7:0] $end -$var wire 8 f# out[1][0] [7:0] $end -$var wire 8 g# out[1][1] [7:0] $end -$var wire 8 h# out[1][2] [7:0] $end -$var int 32 i# count [31:0] $end -$var wire 8 j# val0[0] [7:0] $end -$var wire 8 k# val0[1] [7:0] $end -$var wire 8 l# val1[0] [7:0] $end -$var wire 8 m# val1[1] [7:0] $end -$var wire 8 n# val2[0] [7:0] $end -$var wire 8 o# val2[1] [7:0] $end -$var wire 8 p# val3[0] [7:0] $end -$var wire 8 q# val3[1] [7:0] $end +$var wire 1 4$ clk $end +$var wire 128 5$ in[0][0] [127:0] $end +$var wire 128 6$ in[0][1] [127:0] $end +$var wire 128 7$ in[0][2] [127:0] $end +$var wire 128 8$ in[1][0] [127:0] $end +$var wire 128 9$ in[1][1] [127:0] $end +$var wire 128 :$ in[1][2] [127:0] $end +$var wire 8 ;$ out[0][0] [7:0] $end +$var wire 8 <$ out[0][1] [7:0] $end +$var wire 8 =$ out[0][2] [7:0] $end +$var wire 8 >$ out[1][0] [7:0] $end +$var wire 8 ?$ out[1][1] [7:0] $end +$var wire 8 @$ out[1][2] [7:0] $end +$var int 32 A$ count [31:0] $end +$var wire 8 B$ val0[0] [7:0] $end +$var wire 8 C$ val0[1] [7:0] $end +$var wire 8 D$ val1[0] [7:0] $end +$var wire 8 E$ val1[1] [7:0] $end +$var wire 8 F$ val2[0] [7:0] $end +$var wire 8 G$ val2[1] [7:0] $end +$var wire 8 H$ val3[0] [7:0] $end +$var wire 8 I$ val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 r# out[0] [7:0] $end -$var wire 8 s# out[1] [7:0] $end +$var parameter 32 J$ P0 [31:0] $end +$var parameter 32 K$ P1 [31:0] $end +$var wire 8 L$ out[0] [7:0] $end +$var wire 8 M$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 t# out[0] [7:0] $end -$var wire 8 u# out[1] [7:0] $end +$var parameter 32 J$ P0 [31:0] $end +$var parameter 32 K$ P1 [31:0] $end +$var wire 8 N$ out[0] [7:0] $end +$var wire 8 O$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 v# out[0] [7:0] $end -$var wire 8 w# out[1] [7:0] $end +$var parameter 32 J$ P0 [31:0] $end +$var parameter 32 K$ P1 [31:0] $end +$var wire 8 P$ out[0] [7:0] $end +$var wire 8 Q$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 =" P1 [31:0] $end -$var wire 8 x# out[0] [7:0] $end -$var wire 8 y# out[1] [7:0] $end +$var parameter 32 J$ P0 [31:0] $end +$var parameter 32 R$ P1 [31:0] $end +$var wire 8 S$ out[0] [7:0] $end +$var wire 8 T$ out[1] [7:0] $end $upscope $end -$scope module unnamedblk1 $end -$var int 32 z# i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 {# j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 |# exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 }# i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 ~# j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 !$ exp [7:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module top.t.i_sub3.i_sub4_0.i_sub5 $end -$var wire 1 "$ clk $end -$var wire 128 #$ in[0][0] [127:0] $end -$var wire 128 $$ in[0][1] [127:0] $end -$var wire 128 %$ in[0][2] [127:0] $end -$var wire 128 &$ in[1][0] [127:0] $end -$var wire 128 '$ in[1][1] [127:0] $end -$var wire 128 ($ in[1][2] [127:0] $end -$var wire 8 )$ out[0][0] [7:0] $end -$var wire 8 *$ out[0][1] [7:0] $end -$var wire 8 +$ out[0][2] [7:0] $end -$var wire 8 ,$ out[1][0] [7:0] $end -$var wire 8 -$ out[1][1] [7:0] $end -$var wire 8 .$ out[1][2] [7:0] $end -$scope module sub5 $end -$var wire 1 "$ clk $end -$var wire 128 /$ in[0][0] [127:0] $end -$var wire 128 0$ in[0][1] [127:0] $end -$var wire 128 1$ in[0][2] [127:0] $end -$var wire 128 2$ in[1][0] [127:0] $end -$var wire 128 3$ in[1][1] [127:0] $end -$var wire 128 4$ in[1][2] [127:0] $end -$var wire 8 5$ out[0][0] [7:0] $end -$var wire 8 6$ out[0][1] [7:0] $end -$var wire 8 7$ out[0][2] [7:0] $end -$var wire 8 8$ out[1][0] [7:0] $end -$var wire 8 9$ out[1][1] [7:0] $end -$var wire 8 :$ out[1][2] [7:0] $end -$var int 32 ;$ count [31:0] $end -$var wire 8 <$ val0[0] [7:0] $end -$var wire 8 =$ val0[1] [7:0] $end -$var wire 8 >$ val1[0] [7:0] $end -$var wire 8 ?$ val1[1] [7:0] $end -$var wire 8 @$ val2[0] [7:0] $end -$var wire 8 A$ val2[1] [7:0] $end -$var wire 8 B$ val3[0] [7:0] $end -$var wire 8 C$ val3[1] [7:0] $end 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-$scope module top.t.i_sub3.i_sub4_1.i_sub5 $end -$var wire 1 R$ clk $end -$var wire 128 S$ in[0][0] [127:0] $end -$var wire 128 T$ in[0][1] [127:0] $end -$var wire 128 U$ in[0][2] [127:0] $end -$var wire 128 V$ in[1][0] [127:0] $end -$var wire 128 W$ in[1][1] [127:0] $end -$var wire 128 X$ in[1][2] [127:0] $end -$var wire 8 Y$ out[0][0] [7:0] $end -$var wire 8 Z$ out[0][1] [7:0] $end -$var wire 8 [$ out[0][2] [7:0] $end -$var wire 8 \$ out[1][0] [7:0] $end -$var wire 8 ]$ out[1][1] [7:0] $end -$var wire 8 ^$ out[1][2] [7:0] $end -$scope module sub5 $end -$var wire 1 R$ clk $end -$var wire 128 _$ in[0][0] [127:0] $end -$var wire 128 `$ in[0][1] [127:0] $end -$var wire 128 a$ in[0][2] [127:0] $end -$var wire 128 b$ in[1][0] [127:0] $end -$var wire 128 c$ in[1][1] [127:0] $end -$var wire 128 d$ in[1][2] [127:0] $end -$var wire 8 e$ out[0][0] [7:0] $end -$var wire 8 f$ out[0][1] [7:0] $end -$var wire 8 g$ out[0][2] [7:0] $end -$var wire 8 h$ out[1][0] [7:0] $end -$var wire 8 i$ out[1][1] [7:0] $end -$var wire 8 j$ out[1][2] [7:0] $end -$var int 32 k$ count [31:0] $end -$var wire 8 l$ val0[0] [7:0] $end -$var wire 8 m$ val0[1] [7:0] $end -$var wire 8 n$ val1[0] [7:0] $end -$var wire 8 o$ val1[1] [7:0] $end -$var wire 8 p$ val2[0] [7:0] $end -$var wire 8 q$ val2[1] [7:0] $end -$var wire 8 r$ val3[0] [7:0] $end -$var wire 8 s$ val3[1] [7:0] $end -$scope module i_sub0 $end -$var parameter 32 t$ P0 [31:0] $end -$var parameter 32 u$ P1 [31:0] $end -$var wire 8 v$ out[0] [7:0] $end -$var wire 8 w$ out[1] [7:0] $end -$upscope $end -$scope module i_sub1 $end -$var parameter 32 t$ P0 [31:0] $end -$var parameter 32 u$ P1 [31:0] $end -$var wire 8 x$ out[0] [7:0] $end -$var wire 8 y$ out[1] [7:0] $end -$upscope $end -$scope module i_sub2 $end -$var parameter 32 t$ P0 [31:0] $end -$var parameter 32 u$ P1 [31:0] $end -$var wire 8 z$ out[0] [7:0] $end -$var wire 8 {$ out[1] [7:0] $end -$upscope $end -$scope module i_sub3 $end -$var parameter 32 t$ P0 [31:0] $end -$var parameter 32 |$ P1 [31:0] $end -$var wire 8 }$ out[0] [7:0] $end -$var wire 8 ~$ out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 !% i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 "% j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 #% exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module top.t.i_sub3_2.i_sub4_0.i_sub5 $end -$var wire 1 $% clk $end -$var wire 128 %% in[0][0] [127:0] $end -$var wire 128 &% in[0][1] [127:0] $end -$var wire 128 '% in[0][2] [127:0] $end -$var wire 128 (% in[1][0] [127:0] $end -$var wire 128 )% in[1][1] [127:0] $end -$var wire 128 *% in[1][2] [127:0] $end -$var wire 8 +% out[0][0] [7:0] $end -$var wire 8 ,% out[0][1] [7:0] $end -$var wire 8 -% out[0][2] [7:0] $end -$var wire 8 .% out[1][0] [7:0] $end -$var wire 8 /% out[1][1] [7:0] $end -$var wire 8 0% out[1][2] [7:0] $end -$scope module sub5 $end -$var wire 1 $% clk $end -$var wire 128 1% in[0][0] [127:0] $end -$var wire 128 2% in[0][1] [127:0] $end -$var wire 128 3% in[0][2] [127:0] $end -$var wire 128 4% in[1][0] [127:0] $end -$var wire 128 5% in[1][1] [127:0] $end -$var wire 128 6% in[1][2] [127:0] $end -$var wire 8 7% out[0][0] [7:0] $end -$var wire 8 8% out[0][1] [7:0] $end -$var wire 8 9% out[0][2] [7:0] $end -$var wire 8 :% out[1][0] [7:0] $end -$var wire 8 ;% out[1][1] [7:0] $end -$var wire 8 <% out[1][2] [7:0] $end -$var int 32 =% count [31:0] $end -$var wire 8 >% val0[0] [7:0] $end -$var wire 8 ?% val0[1] [7:0] $end -$var wire 8 @% val1[0] [7:0] $end -$var wire 8 A% val1[1] [7:0] $end -$var wire 8 B% val2[0] [7:0] $end -$var wire 8 C% val2[1] [7:0] $end -$var wire 8 D% val3[0] [7:0] $end -$var wire 8 E% val3[1] [7:0] $end -$scope module i_sub0 $end -$var parameter 32 F% P0 [31:0] $end -$var parameter 32 G% P1 [31:0] $end -$var wire 8 H% out[0] [7:0] $end -$var wire 8 I% out[1] [7:0] $end -$upscope $end -$scope module i_sub1 $end -$var parameter 32 F% P0 [31:0] $end -$var parameter 32 G% P1 [31:0] $end -$var wire 8 J% out[0] [7:0] $end -$var wire 8 K% out[1] [7:0] $end -$upscope $end -$scope module i_sub2 $end -$var parameter 32 F% P0 [31:0] $end -$var parameter 32 G% P1 [31:0] $end -$var wire 8 L% out[0] [7:0] $end -$var wire 8 M% out[1] [7:0] $end -$upscope $end -$scope module i_sub3 $end -$var parameter 32 F% P0 [31:0] $end -$var parameter 32 N% P1 [31:0] $end -$var wire 8 O% out[0] [7:0] $end -$var wire 8 P% out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 Q% i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 R% j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 S% exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module top.t.i_sub3_2.i_sub4_1.i_sub5 $end -$var wire 1 T% clk $end -$var wire 128 U% in[0][0] [127:0] $end -$var wire 128 V% in[0][1] [127:0] $end -$var wire 128 W% in[0][2] [127:0] $end -$var wire 128 X% in[1][0] [127:0] $end -$var wire 128 Y% in[1][1] [127:0] $end -$var wire 128 Z% in[1][2] [127:0] $end -$var wire 8 [% out[0][0] [7:0] $end -$var wire 8 \% out[0][1] [7:0] $end -$var wire 8 ]% out[0][2] [7:0] $end -$var wire 8 ^% out[1][0] [7:0] $end -$var wire 8 _% out[1][1] [7:0] $end -$var wire 8 `% out[1][2] [7:0] $end -$scope module sub5 $end -$var wire 1 T% clk $end -$var wire 128 a% in[0][0] [127:0] $end -$var wire 128 b% in[0][1] [127:0] $end -$var wire 128 c% in[0][2] [127:0] $end -$var wire 128 d% in[1][0] [127:0] $end -$var wire 128 e% in[1][1] [127:0] $end -$var wire 128 f% in[1][2] [127:0] $end -$var wire 8 g% out[0][0] [7:0] $end -$var wire 8 h% out[0][1] [7:0] $end -$var wire 8 i% out[0][2] [7:0] $end -$var wire 8 j% out[1][0] [7:0] $end -$var wire 8 k% out[1][1] [7:0] $end -$var wire 8 l% out[1][2] [7:0] $end -$var int 32 m% count [31:0] $end -$var wire 8 n% val0[0] [7:0] $end -$var wire 8 o% val0[1] [7:0] $end -$var wire 8 p% val1[0] [7:0] $end -$var wire 8 q% val1[1] [7:0] $end -$var wire 8 r% val2[0] [7:0] $end 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b/test_regress/t/t_hier_block_sc_trace_fst.py index b3ca507cc..3ce35e02c 100755 --- a/test_regress/t/t_hier_block_sc_trace_fst.py +++ b/test_regress/t/t_hier_block_sc_trace_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.out b/test_regress/t/t_hier_block_sc_trace_vcd.out index c7c90d0a2..dfa2c07dd 100644 --- a/test_regress/t/t_hier_block_sc_trace_vcd.out +++ b/test_regress/t/t_hier_block_sc_trace_vcd.out @@ -1,1052 +1,763 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end + $scope module stateless_pkg $end + $var wire 32 h! ONE [31:0] $end + $upscope $end $scope module t $end - $var wire 32 {" PARAM_A [31:0] $end - $var wire 32 |" PARAM_B [31:0] $end - $var wire 1 z" clk $end - $var wire 8 G" out0 [7:0] $end - $var wire 8 H" out1 [7:0] $end - $var wire 8 I" out2 [7:0] $end - $var wire 8 C! out3 [7:0] $end - $var wire 8 ' out3_2 [7:0] $end - $var wire 8 ( out5 [7:0] $end - $var wire 8 ) out6 [7:0] $end - $var wire 32 * count [31:0] $end + $var wire 32 T! PARAM_A [31:0] $end + $var wire 32 U! PARAM_B [31:0] $end + $var wire 1 Q! clk $end + $var wire 8 6! out0 [7:0] $end + $var wire 8 7! out1 [7:0] $end + $var wire 8 8! out2 [7:0] $end + $var wire 8 R! out3 [7:0] $end + $var wire 8 & out3_2 [7:0] $end + $var wire 8 ' out5 [7:0] $end + $var wire 8 ( out6 [7:0] $end + $var wire 32 ) count [31:0] $end $scope module i_delay0 $end - $var wire 32 }" N [31:0] $end - $var wire 32 ~" WIDTH [31:0] $end - $var wire 1 z" clk $end - $var wire 8 C! in [7:0] $end - $var wire 8 ( out [7:0] $end - $var wire 8 + tmp [7:0] $end + $var wire 32 V! N [31:0] $end + $var wire 32 W! WIDTH [31:0] $end + $var wire 1 Q! clk $end + $var wire 8 R! in [7:0] $end + $var wire 8 ' out [7:0] $end + $var wire 8 * tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end - $var wire 32 !# N [31:0] $end - $var wire 32 ~" WIDTH [31:0] $end - $var wire 1 z" clk $end - $var wire 8 + in [7:0] $end - $var wire 8 ( out [7:0] $end - $var wire 8 ( tmp [7:0] $end + $var wire 32 X! N [31:0] $end + $var wire 32 W! WIDTH [31:0] $end + $var wire 1 Q! clk $end + $var wire 8 * in [7:0] $end + $var wire 8 ' out [7:0] $end + $var wire 8 ' tmp [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_delay1 $end - $var wire 32 "# N [31:0] $end - $var wire 32 ~" WIDTH [31:0] $end - $var wire 1 z" clk $end - $var wire 8 ( in [7:0] $end - $var wire 8 ) out [7:0] $end - $var wire 8 , tmp [7:0] $end + $var wire 32 Y! N [31:0] $end + $var wire 32 W! WIDTH [31:0] $end + $var wire 1 Q! clk $end + $var wire 8 ' in [7:0] $end + $var wire 8 ( out [7:0] $end + $var wire 8 + tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end - $var wire 32 }" N [31:0] $end - $var wire 32 ~" WIDTH [31:0] $end - $var wire 1 z" clk $end - $var wire 8 , in [7:0] $end - $var wire 8 ) out [7:0] $end - $var wire 8 - tmp [7:0] $end + $var wire 32 V! N [31:0] $end + $var wire 32 W! WIDTH [31:0] $end + $var wire 1 Q! clk $end + $var wire 8 + in [7:0] $end + $var wire 8 ( out [7:0] $end + $var wire 8 , tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end - $var wire 32 !# N [31:0] $end - $var wire 32 ~" WIDTH [31:0] $end - $var wire 1 z" clk $end - $var wire 8 - in [7:0] $end - $var wire 8 ) out [7:0] $end - $var wire 8 ) tmp [7:0] $end + $var wire 32 X! N [31:0] $end + $var wire 32 W! WIDTH [31:0] $end + $var wire 1 Q! clk $end + $var wire 8 , in [7:0] $end + $var wire 8 ( out [7:0] $end + $var wire 8 ( tmp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub0 $end - $var wire 1 z" clk $end - $var wire 8 C! in [7:0] $end - $var wire 8 G" out [7:0] $end + $var wire 1 Q! clk $end + $var wire 8 R! in [7:0] $end + $var wire 8 6! out [7:0] $end $scope module i_sub0 $end - $var wire 1 z" clk $end - $var wire 8 C! in [7:0] $end - $var wire 8 G" out [7:0] $end + $var wire 1 i! clk $end + $var wire 8 j! in [7:0] $end + $var wire 8 k! out [7:0] $end + $var wire 8 l! ff [7:0] $end $upscope $end $upscope $end $scope module i_sub1 $end - $var wire 1 z" clk $end - $var wire 8 G" in [11:4] $end - $var wire 8 H" out [7:0] $end + $var wire 1 m! clk $end + $var wire 8 n! in [11:4] $end + $var wire 8 o! out [7:0] $end + $var wire 8 p! ff [7:0] $end + $var wire 2 q! enum_v [1:0] $end $upscope $end $scope module i_sub2 $end - $var wire 1 z" clk $end - $var wire 8 H" in [7:0] $end - $var wire 8 I" out [7:0] $end + $var wire 1 >% clk $end + $var wire 8 ?% in [7:0] $end + $var wire 8 @% out [7:0] $end + $var wire 8 X" ff [7:0] $end + $var wire 2 Y" alt_enum_v [1:0] $end + $scope module i_sub3 $end + $var wire 8 X" in_wire [7:0] $end + $var wire 8 Z" out_1 [7:0] $end + $var wire 8 [" out_2 [7:0] $end + $scope module i_sub3 $end + $var wire 8 A% P0 [7:0] $end + $var wire 32 B% UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 C% UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 D% UNUSED [15:0] $end + $var wire 2 E% ENUM [1:0] $end + $var wire 1 >% clk $end + $var wire 8 X" in [7:0] $end + $var wire 8 Z" out [7:0] $end + $var wire 8 \" ff [7:0] $end + $var wire 8 Z" out4 [7:0] $end + $var wire 8 ]" out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 32 F% P0 [31:0] $end + $var real 64 G% P1 $end + $var real 64 I% P3 $end + $var wire 1 >% clk $end + $var wire 8 \" in [7:0] $end + $var wire 8 Z" out [7:0] $end + $var wire 8 Z" ff [7:0] $end + $var wire 128 ^" sub5_in[0][0] [127:0] $end + $var wire 128 b" sub5_in[0][1] [127:0] $end + $var wire 128 f" sub5_in[0][2] [127:0] $end + $var wire 128 j" sub5_in[1][0] [127:0] $end + $var wire 128 n" sub5_in[1][1] [127:0] $end + $var wire 128 r" sub5_in[1][2] [127:0] $end + $var wire 8 v" sub5_out[0][0] [7:0] $end + $var wire 8 w" sub5_out[0][1] [7:0] $end + $var wire 8 x" sub5_out[0][2] [7:0] $end + $var wire 8 y" sub5_out[1][0] [7:0] $end + $var wire 8 z" sub5_out[1][1] [7:0] $end + $var wire 8 {" sub5_out[1][2] [7:0] $end + $var wire 32 |" count [31:0] $end + $var wire 32 r! driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 G% P1 $end + $var wire 32 r! driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 >% clk $end + $var wire 128 }" in[0][0] [127:0] $end + $var wire 128 ## in[0][1] [127:0] $end + $var wire 128 '# in[0][2] [127:0] $end + $var wire 128 +# in[1][0] [127:0] $end + $var wire 128 /# in[1][1] [127:0] $end + $var wire 128 3# in[1][2] [127:0] $end + $var wire 8 7# out[0][0] [7:0] $end + $var wire 8 8# out[0][1] [7:0] $end + $var wire 8 9# out[0][2] [7:0] $end + $var wire 8 :# out[1][0] [7:0] $end + $var wire 8 ;# out[1][1] [7:0] $end + $var wire 8 <# out[1][2] [7:0] $end + $var wire 32 =# count [31:0] $end + $var wire 8 s! val0[0] [7:0] $end + $var wire 8 t! val0[1] [7:0] $end + $var wire 8 u! val1[0] [7:0] $end + $var wire 8 v! val1[1] [7:0] $end + $var wire 8 w! val2[0] [7:0] $end + $var wire 8 x! val2[1] [7:0] $end + $var wire 8 y! val3[0] [7:0] $end + $var wire 8 z! val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 {! out[0] [7:0] $end + $var wire 8 |! out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 }! out[0] [7:0] $end + $var wire 8 ~! out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 !" out[0] [7:0] $end + $var wire 8 "" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 M% P1 [31:0] $end + $var wire 8 #" out[0] [7:0] $end + $var wire 8 $" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 32 F% P0 [31:0] $end + $var real 64 G% P1 $end + $var real 64 N% P3 $end + $var wire 1 >% clk $end + $var wire 8 \" in [7:0] $end + $var wire 8 ]" out [7:0] $end + $var wire 8 ]" ff [7:0] $end + $var wire 128 ># sub5_in[0][0] [127:0] $end + $var wire 128 B# sub5_in[0][1] [127:0] $end + $var wire 128 F# sub5_in[0][2] [127:0] $end + $var wire 128 J# sub5_in[1][0] [127:0] $end + $var wire 128 N# sub5_in[1][1] [127:0] $end + $var wire 128 R# sub5_in[1][2] [127:0] $end + $var wire 8 V# sub5_out[0][0] [7:0] $end + $var wire 8 W# sub5_out[0][1] [7:0] $end + $var wire 8 X# sub5_out[0][2] [7:0] $end + $var wire 8 Y# sub5_out[1][0] [7:0] $end + $var wire 8 Z# sub5_out[1][1] [7:0] $end + $var wire 8 [# sub5_out[1][2] [7:0] $end + $var wire 32 \# count [31:0] $end + $var wire 32 %" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 G% P1 $end + $var wire 32 %" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 >% clk $end + $var wire 128 ]# in[0][0] [127:0] $end + $var wire 128 a# in[0][1] [127:0] $end + $var wire 128 e# in[0][2] [127:0] $end + $var wire 128 i# in[1][0] [127:0] $end + $var wire 128 m# in[1][1] [127:0] $end + $var wire 128 q# in[1][2] [127:0] $end + $var wire 8 u# out[0][0] [7:0] $end + $var wire 8 v# out[0][1] [7:0] $end + $var wire 8 w# out[0][2] [7:0] $end + $var wire 8 x# out[1][0] [7:0] $end + $var wire 8 y# out[1][1] [7:0] $end + $var wire 8 z# out[1][2] [7:0] $end + $var wire 32 {# count [31:0] $end + $var wire 8 &" val0[0] [7:0] $end + $var wire 8 '" val0[1] [7:0] $end + $var wire 8 (" val1[0] [7:0] $end + $var wire 8 )" val1[1] [7:0] $end + $var wire 8 *" val2[0] [7:0] $end + $var wire 8 +" val2[1] [7:0] $end + $var wire 8 ," val3[0] [7:0] $end + $var wire 8 -" val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 ." out[0] [7:0] $end + $var wire 8 /" out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 0" out[0] [7:0] $end + $var wire 8 1" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 2" out[0] [7:0] $end + $var wire 8 3" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 M% P1 [31:0] $end + $var wire 8 4" out[0] [7:0] $end + $var wire 8 5" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub3_2 $end + $var wire 8 A% P0 [7:0] $end + $var wire 32 P% UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 Q% UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 D% UNUSED [15:0] $end + $var wire 2 E% ENUM [1:0] $end + $var wire 1 >% clk $end + $var wire 8 X" in [7:0] $end + $var wire 8 [" out [7:0] $end + $var wire 8 |# ff [7:0] $end + $var wire 8 [" out4 [7:0] $end + $var wire 8 }# out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 32 F% P0 [31:0] $end + $var real 64 G% P1 $end + $var real 64 I% P3 $end + $var wire 1 >% clk $end + $var wire 8 |# in [7:0] $end + $var wire 8 [" out [7:0] $end + $var wire 8 [" ff [7:0] $end + $var wire 128 ~# sub5_in[0][0] [127:0] $end + $var wire 128 $$ sub5_in[0][1] [127:0] $end + $var wire 128 ($ sub5_in[0][2] [127:0] $end + $var wire 128 ,$ sub5_in[1][0] [127:0] $end + $var wire 128 0$ sub5_in[1][1] [127:0] $end + $var wire 128 4$ sub5_in[1][2] [127:0] $end + $var wire 8 8$ sub5_out[0][0] [7:0] $end + $var wire 8 9$ sub5_out[0][1] [7:0] $end + $var wire 8 :$ sub5_out[0][2] [7:0] $end + $var wire 8 ;$ sub5_out[1][0] [7:0] $end + $var wire 8 <$ sub5_out[1][1] [7:0] $end + $var wire 8 =$ sub5_out[1][2] [7:0] $end + $var wire 32 >$ count [31:0] $end + $var wire 32 6" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 G% P1 $end + $var wire 32 6" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 >% clk $end + $var wire 128 ?$ in[0][0] [127:0] $end + $var wire 128 C$ in[0][1] [127:0] $end + $var wire 128 G$ in[0][2] [127:0] $end + $var wire 128 K$ in[1][0] [127:0] $end + $var wire 128 O$ in[1][1] [127:0] $end + $var wire 128 S$ in[1][2] [127:0] $end + $var wire 8 W$ out[0][0] [7:0] $end + $var wire 8 X$ out[0][1] [7:0] $end + $var wire 8 Y$ out[0][2] [7:0] $end + $var wire 8 Z$ out[1][0] [7:0] $end + $var wire 8 [$ out[1][1] [7:0] $end + $var wire 8 \$ out[1][2] [7:0] $end + $var wire 32 ]$ count [31:0] $end + $var wire 8 7" val0[0] [7:0] $end + $var wire 8 8" val0[1] [7:0] $end + $var wire 8 9" val1[0] [7:0] $end + $var wire 8 :" val1[1] [7:0] $end + $var wire 8 ;" val2[0] [7:0] $end + $var wire 8 <" val2[1] [7:0] $end + $var wire 8 =" val3[0] [7:0] $end + $var wire 8 >" val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 ?" out[0] [7:0] $end + $var wire 8 @" out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 A" out[0] [7:0] $end + $var wire 8 B" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 C" out[0] [7:0] $end + $var wire 8 D" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 M% P1 [31:0] $end + $var wire 8 E" out[0] [7:0] $end + $var wire 8 F" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 32 F% P0 [31:0] $end + $var real 64 G% P1 $end + $var real 64 N% P3 $end + $var wire 1 >% clk $end + $var wire 8 |# in [7:0] $end + $var wire 8 }# out [7:0] $end + $var wire 8 }# ff [7:0] $end + $var wire 128 ^$ sub5_in[0][0] [127:0] $end + $var wire 128 b$ sub5_in[0][1] [127:0] $end + $var wire 128 f$ sub5_in[0][2] [127:0] $end + $var wire 128 j$ sub5_in[1][0] [127:0] $end + $var wire 128 n$ sub5_in[1][1] [127:0] $end + $var wire 128 r$ sub5_in[1][2] [127:0] $end + $var wire 8 v$ sub5_out[0][0] [7:0] $end + $var wire 8 w$ sub5_out[0][1] [7:0] $end + $var wire 8 x$ sub5_out[0][2] [7:0] $end + $var wire 8 y$ sub5_out[1][0] [7:0] $end + $var wire 8 z$ sub5_out[1][1] [7:0] $end + $var wire 8 {$ sub5_out[1][2] [7:0] $end + $var wire 32 |$ count [31:0] $end + $var wire 32 G" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 G% P1 $end + $var wire 32 G" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 >% clk $end + $var wire 128 }$ in[0][0] [127:0] $end + $var wire 128 #% in[0][1] [127:0] $end + $var wire 128 '% in[0][2] [127:0] $end + $var wire 128 +% in[1][0] [127:0] $end + $var wire 128 /% in[1][1] [127:0] $end + $var wire 128 3% in[1][2] [127:0] $end + $var wire 8 7% out[0][0] [7:0] $end + $var wire 8 8% out[0][1] [7:0] $end + $var wire 8 9% out[0][2] [7:0] $end + $var wire 8 :% out[1][0] [7:0] $end + $var wire 8 ;% out[1][1] [7:0] $end + $var wire 8 <% out[1][2] [7:0] $end + $var wire 32 =% count [31:0] $end + $var wire 8 H" val0[0] [7:0] $end + $var wire 8 I" val0[1] [7:0] $end + $var wire 8 J" val1[0] [7:0] $end + $var wire 8 K" val1[1] [7:0] $end + $var wire 8 L" val2[0] [7:0] $end + $var wire 8 M" val2[1] [7:0] $end + $var wire 8 N" val3[0] [7:0] $end + $var wire 8 O" val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 P" out[0] [7:0] $end + $var wire 8 Q" out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 R" out[0] [7:0] $end + $var wire 8 S" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 L% P1 [31:0] $end + $var wire 8 T" out[0] [7:0] $end + $var wire 8 U" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 K% P0 [31:0] $end + $var wire 32 M% P1 [31:0] $end + $var wire 8 V" out[0] [7:0] $end + $var wire 8 W" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module in $end + $var wire 1 >% clk $end + $var wire 8 X" data [7:0] $end + $upscope $end + $scope module out $end + $var wire 1 >% clk $end + $var wire 8 Z" data [7:0] $end + $upscope $end + $upscope $end + $scope module in_ifs $end + $var wire 1 >% clk $end + $var wire 8 X" data [7:0] $end + $upscope $end + $scope module out_ifs $end + $var wire 1 >% clk $end + $var wire 8 Z" data [7:0] $end + $upscope $end $upscope $end $scope module i_sub3 $end - $var wire 8 ## P0 [7:0] $end - $var wire 32 $# UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 %# UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 &# UNUSED [15:0] $end - $var wire 2 '# ENUM [1:0] $end - $var wire 1 z" clk $end - $var wire 8 I" in [7:0] $end - $var wire 8 C! out [7:0] $end - $var wire 8 D! ff [7:0] $end - $var wire 8 C! out4 [7:0] $end - $var wire 8 . out4_2 [7:0] $end + $var wire 8 Z! P0 [7:0] $end + $var wire 32 [! UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 \! UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 ]! UNUSED [15:0] $end + $var wire 2 ^! ENUM [1:0] $end + $var wire 1 Q! clk $end + $var wire 8 8! in [7:0] $end + $var wire 8 R! out [7:0] $end + $var wire 8 S! ff [7:0] $end + $var wire 8 R! out4 [7:0] $end + $var wire 8 - out4_2 [7:0] $end $scope module i_sub4_0 $end - $var wire 32 (# P0 [31:0] $end - $var real 64 )# P1 $end - $var real 64 +# P3 $end - $var wire 1 z" clk $end - $var wire 8 D! in [7:0] $end - $var wire 8 C! out [7:0] $end - $var wire 8 C! ff [7:0] $end - $var wire 128 / sub5_in[0][0] [127:0] $end - $var wire 128 3 sub5_in[0][1] [127:0] $end - $var wire 128 7 sub5_in[0][2] [127:0] $end - $var wire 128 ; sub5_in[1][0] [127:0] $end - $var wire 128 ? sub5_in[1][1] [127:0] $end - $var wire 128 C sub5_in[1][2] [127:0] $end - $var wire 8 J" sub5_out[0][0] [7:0] $end - $var wire 8 K" sub5_out[0][1] [7:0] $end - $var wire 8 L" sub5_out[0][2] [7:0] $end - $var wire 8 M" sub5_out[1][0] [7:0] $end - $var wire 8 N" sub5_out[1][1] [7:0] $end - $var wire 8 O" sub5_out[1][2] [7:0] $end - $var wire 32 G count [31:0] $end - $var wire 32 # driven_from_bind [31:0] $end + $var wire 32 _! P0 [31:0] $end + $var real 64 `! P1 $end + $var real 64 b! P3 $end + $var wire 1 Q! clk $end + $var wire 8 S! in [7:0] $end + $var wire 8 R! out [7:0] $end + $var wire 8 R! ff [7:0] $end + $var wire 128 . sub5_in[0][0] [127:0] $end + $var wire 128 2 sub5_in[0][1] [127:0] $end + $var wire 128 6 sub5_in[0][2] [127:0] $end + $var wire 128 : sub5_in[1][0] [127:0] $end + $var wire 128 > sub5_in[1][1] [127:0] $end + $var wire 128 B sub5_in[1][2] [127:0] $end + $var wire 8 9! sub5_out[0][0] [7:0] $end + $var wire 8 :! sub5_out[0][1] [7:0] $end + $var wire 8 ;! sub5_out[0][2] [7:0] $end + $var wire 8 ! sub5_out[1][2] [7:0] $end + $var wire 32 F count [31:0] $end + $var wire 32 " driven_from_bind [31:0] $end $scope module i_sub4_bound $end - $var real 64 )# P1 $end - $var wire 32 # driven_from_bind [31:0] $end + $var real 64 `! P1 $end + $var wire 32 " driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end - $var wire 1 z" clk $end - $var wire 128 E! in[0][0] [127:0] $end - $var wire 128 I! in[0][1] [127:0] $end - $var wire 128 M! in[0][2] [127:0] $end - $var wire 128 Q! in[1][0] [127:0] $end - $var wire 128 U! in[1][1] [127:0] $end - $var wire 128 Y! in[1][2] [127:0] $end - $var wire 8 P" out[0][0] [7:0] $end - $var wire 8 Q" out[0][1] [7:0] $end - $var wire 8 R" out[0][2] [7:0] $end - $var wire 8 S" out[1][0] [7:0] $end - $var wire 8 T" out[1][1] [7:0] $end - $var wire 8 U" out[1][2] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 H i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 I j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 J exp [7:0] $end - $upscope $end + $var wire 1 #& clk $end + $var wire 128 b% in[0][0] [127:0] $end + $var wire 128 f% in[0][1] [127:0] $end + $var wire 128 j% in[0][2] [127:0] $end + $var wire 128 n% in[1][0] [127:0] $end + $var wire 128 r% in[1][1] [127:0] $end + $var wire 128 v% in[1][2] [127:0] $end + $var wire 8 z% out[0][0] [7:0] $end + $var wire 8 {% out[0][1] [7:0] $end + $var wire 8 |% out[0][2] [7:0] $end + $var wire 8 }% out[1][0] [7:0] $end + $var wire 8 ~% out[1][1] [7:0] $end + $var wire 8 !& out[1][2] [7:0] $end + $var wire 32 "& count [31:0] $end + $var wire 8 R% val0[0] [7:0] $end + $var wire 8 S% val0[1] [7:0] $end + $var wire 8 T% val1[0] [7:0] $end + $var wire 8 U% val1[1] [7:0] $end + $var wire 8 V% val2[0] [7:0] $end + $var wire 8 W% val2[1] [7:0] $end + $var wire 8 X% val3[0] [7:0] $end + $var wire 8 Y% val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 $& P0 [31:0] $end + $var wire 32 %& P1 [31:0] $end + $var wire 8 Z% out[0] [7:0] $end + $var wire 8 [% out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 $& P0 [31:0] $end + $var wire 32 %& P1 [31:0] $end + $var wire 8 \% out[0] [7:0] $end + $var wire 8 ]% out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 $& P0 [31:0] $end + $var wire 32 %& P1 [31:0] $end + $var wire 8 ^% out[0] [7:0] $end + $var wire 8 _% out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 $& P0 [31:0] $end + $var wire 32 && P1 [31:0] $end + $var wire 8 `% out[0] [7:0] $end + $var wire 8 a% out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end - $var wire 32 (# P0 [31:0] $end - $var real 64 )# P1 $end - $var real 64 -# P3 $end - $var wire 1 z" clk $end - $var wire 8 D! in [7:0] $end - $var wire 8 . out [7:0] $end - $var wire 8 . ff [7:0] $end - $var wire 128 K sub5_in[0][0] [127:0] $end - $var wire 128 O sub5_in[0][1] [127:0] $end - $var wire 128 S sub5_in[0][2] [127:0] $end - $var wire 128 W sub5_in[1][0] [127:0] $end - $var wire 128 [ sub5_in[1][1] [127:0] $end - $var wire 128 _ sub5_in[1][2] [127:0] $end - $var wire 8 V" sub5_out[0][0] [7:0] $end - $var wire 8 W" sub5_out[0][1] [7:0] $end - $var wire 8 X" sub5_out[0][2] [7:0] $end - $var wire 8 Y" sub5_out[1][0] [7:0] $end - $var wire 8 Z" sub5_out[1][1] [7:0] $end - $var wire 8 [" sub5_out[1][2] [7:0] $end - $var wire 32 c count [31:0] $end - $var wire 32 $ driven_from_bind [31:0] $end + $var wire 32 _! P0 [31:0] $end + $var real 64 `! P1 $end + $var real 64 d! P3 $end + $var wire 1 Q! clk $end + $var wire 8 S! in [7:0] $end + $var wire 8 - out [7:0] $end + $var wire 8 - ff [7:0] $end + $var wire 128 G sub5_in[0][0] [127:0] $end + $var wire 128 K sub5_in[0][1] [127:0] $end + $var wire 128 O sub5_in[0][2] [127:0] $end + $var wire 128 S sub5_in[1][0] [127:0] $end + $var wire 128 W sub5_in[1][1] [127:0] $end + $var wire 128 [ sub5_in[1][2] [127:0] $end + $var wire 8 ?! sub5_out[0][0] [7:0] $end + $var wire 8 @! sub5_out[0][1] [7:0] $end + $var wire 8 A! sub5_out[0][2] [7:0] $end + $var wire 8 B! sub5_out[1][0] [7:0] $end + $var wire 8 C! sub5_out[1][1] [7:0] $end + $var wire 8 D! sub5_out[1][2] [7:0] $end + $var wire 32 _ count [31:0] $end + $var wire 32 # driven_from_bind [31:0] $end $scope module i_sub4_bound $end - $var real 64 )# P1 $end - $var wire 32 $ driven_from_bind [31:0] $end + $var real 64 `! P1 $end + $var wire 32 # driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end - $var wire 1 z" clk $end - $var wire 128 ]! in[0][0] [127:0] $end - $var wire 128 a! in[0][1] [127:0] $end - $var wire 128 e! in[0][2] [127:0] $end - $var wire 128 i! in[1][0] [127:0] $end - $var wire 128 m! in[1][1] [127:0] $end - $var wire 128 q! in[1][2] [127:0] $end - $var wire 8 \" out[0][0] [7:0] $end - $var wire 8 ]" out[0][1] [7:0] $end - $var wire 8 ^" out[0][2] [7:0] $end - $var wire 8 _" out[1][0] [7:0] $end - $var wire 8 `" out[1][1] [7:0] $end - $var wire 8 a" out[1][2] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 d i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 e j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 f exp [7:0] $end - $upscope $end + $var wire 1 V& clk $end + $var wire 128 7& in[0][0] [127:0] $end + $var wire 128 ;& in[0][1] [127:0] $end + $var wire 128 ?& in[0][2] [127:0] $end + $var wire 128 C& in[1][0] [127:0] $end + $var wire 128 G& in[1][1] [127:0] $end + $var wire 128 K& in[1][2] [127:0] $end + $var wire 8 O& out[0][0] [7:0] $end + $var wire 8 P& out[0][1] [7:0] $end + $var wire 8 Q& out[0][2] [7:0] $end + $var wire 8 R& out[1][0] [7:0] $end + $var wire 8 S& out[1][1] [7:0] $end + $var wire 8 T& out[1][2] [7:0] $end + $var wire 32 U& count [31:0] $end + $var wire 8 '& val0[0] [7:0] $end + $var wire 8 (& val0[1] [7:0] $end + $var wire 8 )& val1[0] [7:0] $end + $var wire 8 *& val1[1] [7:0] $end + $var wire 8 +& val2[0] [7:0] $end + $var wire 8 ,& val2[1] [7:0] $end + $var wire 8 -& val3[0] [7:0] $end + $var wire 8 .& val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 W& P0 [31:0] $end + $var wire 32 X& P1 [31:0] $end + $var wire 8 /& out[0] [7:0] $end + $var wire 8 0& out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 W& P0 [31:0] $end + $var wire 32 X& P1 [31:0] $end + $var wire 8 1& out[0] [7:0] $end + $var wire 8 2& out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 W& P0 [31:0] $end + $var wire 32 X& P1 [31:0] $end + $var wire 8 3& out[0] [7:0] $end + $var wire 8 4& out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 W& P0 [31:0] $end + $var wire 32 Y& P1 [31:0] $end + $var wire 8 5& out[0] [7:0] $end + $var wire 8 6& out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end - $var wire 8 ## P0 [7:0] $end - $var wire 32 /# UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 0# UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 &# UNUSED [15:0] $end - $var wire 2 '# ENUM [1:0] $end - $var wire 1 z" clk $end - $var wire 8 I" in [7:0] $end - $var wire 8 ' out [7:0] $end - $var wire 8 g ff [7:0] $end - $var wire 8 ' out4 [7:0] $end - $var wire 8 h out4_2 [7:0] $end + $var wire 8 Z! P0 [7:0] $end + $var wire 32 f! UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 g! UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 ]! UNUSED [15:0] $end + $var wire 2 ^! ENUM [1:0] $end + $var wire 1 Q! clk $end + $var wire 8 8! in [7:0] $end + $var wire 8 & out [7:0] $end + $var wire 8 ` ff [7:0] $end + $var wire 8 & out4 [7:0] $end + $var wire 8 a out4_2 [7:0] $end $scope module i_sub4_0 $end - $var wire 32 (# P0 [31:0] $end - $var real 64 )# P1 $end - $var real 64 +# P3 $end - $var wire 1 z" clk $end - $var wire 8 g in [7:0] $end - $var wire 8 ' out [7:0] $end - $var wire 8 ' ff [7:0] $end - $var wire 128 i sub5_in[0][0] [127:0] $end - $var wire 128 m sub5_in[0][1] [127:0] $end - $var wire 128 q sub5_in[0][2] [127:0] $end - $var wire 128 u sub5_in[1][0] [127:0] $end - $var wire 128 y sub5_in[1][1] [127:0] $end - $var wire 128 } sub5_in[1][2] [127:0] $end - $var wire 8 b" sub5_out[0][0] [7:0] $end - $var wire 8 c" sub5_out[0][1] [7:0] $end - $var wire 8 d" sub5_out[0][2] [7:0] $end - $var wire 8 e" sub5_out[1][0] [7:0] $end - $var wire 8 f" sub5_out[1][1] [7:0] $end - $var wire 8 g" sub5_out[1][2] [7:0] $end - $var wire 32 #! count [31:0] $end - $var wire 32 % driven_from_bind [31:0] $end + $var wire 32 _! P0 [31:0] $end + $var real 64 `! P1 $end + $var real 64 b! P3 $end + $var wire 1 Q! clk $end + $var wire 8 ` in [7:0] $end + $var wire 8 & out [7:0] $end + $var wire 8 & ff [7:0] $end + $var wire 128 b sub5_in[0][0] [127:0] $end + $var wire 128 f sub5_in[0][1] [127:0] $end + $var wire 128 j sub5_in[0][2] [127:0] $end + $var wire 128 n sub5_in[1][0] [127:0] $end + $var wire 128 r sub5_in[1][1] [127:0] $end + $var wire 128 v sub5_in[1][2] [127:0] $end + $var wire 8 E! sub5_out[0][0] [7:0] $end + $var wire 8 F! sub5_out[0][1] [7:0] $end + $var wire 8 G! sub5_out[0][2] [7:0] $end + $var wire 8 H! sub5_out[1][0] [7:0] $end + $var wire 8 I! sub5_out[1][1] [7:0] $end + $var wire 8 J! sub5_out[1][2] [7:0] $end + $var wire 32 z count [31:0] $end + $var wire 32 $ driven_from_bind [31:0] $end $scope module i_sub4_bound $end - $var real 64 )# P1 $end - $var wire 32 % driven_from_bind [31:0] $end + $var real 64 `! P1 $end + $var wire 32 $ driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end - $var wire 1 z" clk $end - $var wire 128 u! in[0][0] [127:0] $end - $var wire 128 y! in[0][1] [127:0] $end - $var wire 128 }! in[0][2] [127:0] $end - $var wire 128 #" in[1][0] [127:0] $end - $var wire 128 '" in[1][1] [127:0] $end - $var wire 128 +" in[1][2] [127:0] $end - $var wire 8 h" out[0][0] [7:0] $end - $var wire 8 i" out[0][1] [7:0] $end - $var wire 8 j" out[0][2] [7:0] $end - $var wire 8 k" out[1][0] [7:0] $end - $var wire 8 l" out[1][1] [7:0] $end - $var wire 8 m" out[1][2] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 $! i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 %! j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 &! exp [7:0] $end - $upscope $end + $var wire 1 +' clk $end + $var wire 128 j& in[0][0] [127:0] $end + $var wire 128 n& in[0][1] [127:0] $end + $var wire 128 r& in[0][2] [127:0] $end + $var wire 128 v& in[1][0] [127:0] $end + $var wire 128 z& in[1][1] [127:0] $end + $var wire 128 ~& in[1][2] [127:0] $end + $var wire 8 $' out[0][0] [7:0] $end + $var wire 8 %' out[0][1] [7:0] $end + $var wire 8 &' out[0][2] [7:0] $end + $var wire 8 '' out[1][0] [7:0] $end + $var wire 8 (' out[1][1] [7:0] $end + $var wire 8 )' out[1][2] [7:0] $end + $var wire 32 *' count [31:0] $end + $var wire 8 Z& val0[0] [7:0] $end + $var wire 8 [& val0[1] [7:0] $end + $var wire 8 \& val1[0] [7:0] $end + $var wire 8 ]& val1[1] [7:0] $end + $var wire 8 ^& val2[0] [7:0] $end + $var wire 8 _& val2[1] [7:0] $end + $var wire 8 `& val3[0] [7:0] $end + $var wire 8 a& val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 ,' P0 [31:0] $end + $var wire 32 -' P1 [31:0] $end + $var wire 8 b& out[0] [7:0] $end + $var wire 8 c& out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 ,' P0 [31:0] $end + $var wire 32 -' P1 [31:0] $end + $var wire 8 d& out[0] [7:0] $end + $var wire 8 e& out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 ,' P0 [31:0] $end + $var wire 32 -' P1 [31:0] $end + $var wire 8 f& out[0] [7:0] $end + $var wire 8 g& out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 ,' P0 [31:0] $end + $var wire 32 .' P1 [31:0] $end + $var wire 8 h& out[0] [7:0] $end + $var wire 8 i& out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end - $var wire 32 (# P0 [31:0] $end - $var real 64 )# P1 $end - $var real 64 -# P3 $end - $var wire 1 z" clk $end - $var wire 8 g in [7:0] $end - $var wire 8 h out [7:0] $end - $var wire 8 h ff [7:0] $end - $var wire 128 '! sub5_in[0][0] [127:0] $end - $var wire 128 +! sub5_in[0][1] [127:0] $end - $var wire 128 /! sub5_in[0][2] [127:0] $end - $var wire 128 3! sub5_in[1][0] [127:0] $end - $var wire 128 7! sub5_in[1][1] [127:0] $end - $var wire 128 ;! sub5_in[1][2] [127:0] $end - $var wire 8 n" sub5_out[0][0] [7:0] $end - $var wire 8 o" sub5_out[0][1] [7:0] $end - $var wire 8 p" sub5_out[0][2] [7:0] $end - $var wire 8 q" sub5_out[1][0] [7:0] $end - $var wire 8 r" sub5_out[1][1] [7:0] $end - $var wire 8 s" sub5_out[1][2] [7:0] $end - $var wire 32 ?! count [31:0] $end - $var wire 32 & driven_from_bind [31:0] $end + $var wire 32 _! P0 [31:0] $end + $var real 64 `! P1 $end + $var real 64 d! P3 $end + $var wire 1 Q! clk $end + $var wire 8 ` in [7:0] $end + $var wire 8 a out [7:0] $end + $var wire 8 a ff [7:0] $end + $var wire 128 { sub5_in[0][0] [127:0] $end + $var wire 128 !! sub5_in[0][1] [127:0] $end + $var wire 128 %! sub5_in[0][2] [127:0] $end + $var wire 128 )! sub5_in[1][0] [127:0] $end + $var wire 128 -! sub5_in[1][1] [127:0] $end + $var wire 128 1! sub5_in[1][2] [127:0] $end + $var wire 8 K! sub5_out[0][0] [7:0] $end + $var wire 8 L! sub5_out[0][1] [7:0] $end + $var wire 8 M! sub5_out[0][2] [7:0] $end + $var wire 8 N! sub5_out[1][0] [7:0] $end + $var wire 8 O! sub5_out[1][1] [7:0] $end + $var wire 8 P! sub5_out[1][2] [7:0] $end + $var wire 32 5! count [31:0] $end + $var wire 32 % driven_from_bind [31:0] $end $scope module i_sub4_bound $end - $var real 64 )# P1 $end - $var wire 32 & driven_from_bind [31:0] $end + $var real 64 `! P1 $end + $var wire 32 % driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end - $var wire 1 z" clk $end - $var wire 128 /" in[0][0] [127:0] $end - $var wire 128 3" in[0][1] [127:0] $end - $var wire 128 7" in[0][2] [127:0] $end - $var wire 128 ;" in[1][0] [127:0] $end - $var wire 128 ?" in[1][1] [127:0] $end - $var wire 128 C" in[1][2] [127:0] $end - $var wire 8 t" out[0][0] [7:0] $end - $var wire 8 u" out[0][1] [7:0] $end - $var wire 8 v" out[0][2] [7:0] $end - $var wire 8 w" out[1][0] [7:0] $end - $var wire 8 x" out[1][1] [7:0] $end - $var wire 8 y" out[1][2] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 @! i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 A! j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 B! exp [7:0] $end - $upscope $end + $var wire 1 ^' clk $end + $var wire 128 ?' in[0][0] [127:0] $end + $var wire 128 C' in[0][1] [127:0] $end + $var wire 128 G' in[0][2] [127:0] $end + $var wire 128 K' in[1][0] [127:0] $end + $var wire 128 O' in[1][1] [127:0] $end + $var wire 128 S' in[1][2] [127:0] $end + $var wire 8 W' out[0][0] [7:0] $end + $var wire 8 X' out[0][1] [7:0] $end + $var wire 8 Y' out[0][2] [7:0] $end + $var wire 8 Z' out[1][0] [7:0] $end + $var wire 8 [' out[1][1] [7:0] $end + $var wire 8 \' out[1][2] [7:0] $end + $var wire 32 ]' count [31:0] $end + $var wire 8 /' val0[0] [7:0] $end + $var wire 8 0' val0[1] [7:0] $end + $var wire 8 1' val1[0] [7:0] $end + $var wire 8 2' val1[1] [7:0] $end + $var wire 8 3' val2[0] [7:0] $end + $var wire 8 4' val2[1] [7:0] $end + $var wire 8 5' val3[0] [7:0] $end + $var wire 8 6' val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 _' P0 [31:0] $end + $var wire 32 `' P1 [31:0] $end + $var wire 8 7' out[0] [7:0] $end + $var wire 8 8' out[1] [7:0] $end $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.i_sub0.i_sub0 $end - $var wire 1 2# clk $end - $var wire 8 3# in [7:0] $end - $var wire 8 4# out [7:0] $end - $scope module sub0 $end - $var wire 1 2# clk $end - $var wire 8 3# in [7:0] $end - $var wire 8 4# out [7:0] $end - $var wire 8 5# ff [7:0] $end - $upscope $end - $upscope $end - $scope module top.t.i_sub1 $end - $var wire 1 7# clk $end - $var wire 8 8# in [11:4] $end - $var wire 8 9# out [7:0] $end - $scope module sub1 $end - $var wire 1 7# clk $end - $var wire 8 8# in [11:4] $end - $var wire 8 9# out [7:0] $end - $var wire 8 :# ff [7:0] $end - $upscope $end - $upscope $end - $scope module top.t.i_sub2 $end - $var wire 1 +' clk $end - $var wire 8 ,' in [7:0] $end - $var wire 8 -' out [7:0] $end - $scope module sub2 $end - $var wire 1 +' clk $end - $var wire 8 ,' in [7:0] $end - $var wire 8 -' out [7:0] $end - $var wire 8 "$ ff [7:0] $end - $scope module in_ifs $end - $var wire 1 +' clk $end - $var wire 8 "$ data [7:0] $end - $upscope $end - $scope module out_ifs $end - $var wire 1 +' clk $end - $var wire 8 #$ data [7:0] $end - $upscope $end - $scope module i_sub3 $end - $scope module in $end - $var wire 1 +' clk $end - $var wire 8 "$ data [7:0] $end - $upscope $end - $scope module out $end - $var wire 1 +' clk $end - $var wire 8 #$ data [7:0] $end - $upscope $end - $var wire 8 "$ in_wire [7:0] $end - $var wire 8 #$ out_1 [7:0] $end - $var wire 8 $$ out_2 [7:0] $end - $scope module i_sub3 $end - $var wire 8 .' P0 [7:0] $end - $var wire 32 /' UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 0' UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 1' UNUSED [15:0] $end - $var wire 2 2' ENUM [1:0] $end - $var wire 1 +' clk $end - $var wire 8 "$ in [7:0] $end - $var wire 8 #$ out [7:0] $end - $var wire 8 %$ ff [7:0] $end - $var wire 8 #$ out4 [7:0] $end - $var wire 8 &$ out4_2 [7:0] $end - $scope module i_sub4_0 $end - $var wire 32 3' P0 [31:0] $end - $var real 64 4' P1 $end - $var real 64 6' P3 $end - $var wire 1 +' clk $end - $var wire 8 %$ in [7:0] $end - $var wire 8 #$ out [7:0] $end - $var wire 8 #$ ff [7:0] $end - $var wire 128 '$ sub5_in[0][0] [127:0] $end - $var wire 128 +$ sub5_in[0][1] [127:0] $end - $var wire 128 /$ sub5_in[0][2] [127:0] $end - $var wire 128 3$ sub5_in[1][0] [127:0] $end - $var wire 128 7$ sub5_in[1][1] [127:0] $end - $var wire 128 ;$ sub5_in[1][2] [127:0] $end - $var wire 8 ?$ sub5_out[0][0] [7:0] $end - $var wire 8 @$ sub5_out[0][1] [7:0] $end - $var wire 8 A$ sub5_out[0][2] [7:0] $end - $var wire 8 B$ sub5_out[1][0] [7:0] $end - $var wire 8 C$ sub5_out[1][1] [7:0] $end - $var wire 8 D$ sub5_out[1][2] [7:0] $end - $var wire 32 E$ count [31:0] $end - $var wire 32 <# driven_from_bind [31:0] $end - $scope module i_sub4_bound $end - $var real 64 4' P1 $end - $var wire 32 <# driven_from_bind [31:0] $end + $scope module i_sub1 $end + $var wire 32 _' P0 [31:0] $end + $var wire 32 `' P1 [31:0] $end + $var wire 8 9' out[0] [7:0] $end + $var wire 8 :' out[1] [7:0] $end $upscope $end - $scope module i_sub5 $end - $var wire 1 +' clk $end - $var wire 128 F$ in[0][0] [127:0] $end - $var wire 128 J$ in[0][1] [127:0] $end - $var wire 128 N$ in[0][2] [127:0] $end - $var wire 128 R$ in[1][0] [127:0] $end - $var wire 128 V$ in[1][1] [127:0] $end - $var wire 128 Z$ in[1][2] [127:0] $end - $var wire 8 ^$ out[0][0] [7:0] $end - $var wire 8 _$ out[0][1] [7:0] $end - $var wire 8 `$ out[0][2] [7:0] $end - $var wire 8 a$ out[1][0] [7:0] $end - $var wire 8 b$ out[1][1] [7:0] $end - $var wire 8 c$ out[1][2] [7:0] $end - $var wire 32 d$ count [31:0] $end - $var wire 8 =# val0[0] [7:0] $end - $var wire 8 ># val0[1] [7:0] $end - $var wire 8 ?# val1[0] [7:0] $end - $var wire 8 @# val1[1] [7:0] $end - $var wire 8 A# val2[0] [7:0] $end - $var wire 8 B# val2[1] [7:0] $end - $var wire 8 C# val3[0] [7:0] $end - $var wire 8 D# val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 E# out[0] [7:0] $end - $var wire 8 F# out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 G# out[0] [7:0] $end - $var wire 8 H# out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 I# out[0] [7:0] $end - $var wire 8 J# out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 :' P1 [31:0] $end - $var wire 8 K# out[0] [7:0] $end - $var wire 8 L# out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 e$ i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 f$ j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 g$ exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end + $scope module i_sub2 $end + $var wire 32 _' P0 [31:0] $end + $var wire 32 `' P1 [31:0] $end + $var wire 8 ;' out[0] [7:0] $end + $var wire 8 <' out[1] [7:0] $end $upscope $end - $scope module unnamedblk1 $end - $var wire 32 k$ i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 l$ j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 m$ exp [7:0] $end - $upscope $end - $upscope $end + $scope module i_sub3 $end + $var wire 32 _' P0 [31:0] $end + $var wire 32 a' P1 [31:0] $end + $var wire 8 =' out[0] [7:0] $end + $var wire 8 >' out[1] [7:0] $end $upscope $end $upscope $end - $scope module i_sub4_1 $end - $var wire 32 3' P0 [31:0] $end - $var real 64 4' P1 $end - $var real 64 ;' P3 $end - $var wire 1 +' clk $end - $var wire 8 %$ in [7:0] $end - $var wire 8 &$ out [7:0] $end - $var wire 8 &$ ff [7:0] $end - $var wire 128 n$ sub5_in[0][0] [127:0] $end - $var wire 128 r$ sub5_in[0][1] [127:0] $end - $var wire 128 v$ sub5_in[0][2] [127:0] $end - $var wire 128 z$ sub5_in[1][0] [127:0] $end - $var wire 128 ~$ sub5_in[1][1] [127:0] $end - $var wire 128 $% sub5_in[1][2] [127:0] $end - $var wire 8 (% sub5_out[0][0] [7:0] $end - $var wire 8 )% sub5_out[0][1] [7:0] $end - $var wire 8 *% sub5_out[0][2] [7:0] $end - $var wire 8 +% sub5_out[1][0] [7:0] $end - $var wire 8 ,% sub5_out[1][1] [7:0] $end - $var wire 8 -% sub5_out[1][2] [7:0] $end - $var wire 32 .% count [31:0] $end - $var wire 32 M# driven_from_bind [31:0] $end - $scope module i_sub4_bound $end - $var real 64 4' P1 $end - $var wire 32 M# driven_from_bind [31:0] $end - $upscope $end - $scope module i_sub5 $end - $var wire 1 +' clk $end - $var wire 128 /% in[0][0] [127:0] $end - $var wire 128 3% in[0][1] [127:0] $end - $var wire 128 7% in[0][2] [127:0] $end - $var wire 128 ;% in[1][0] [127:0] $end - $var wire 128 ?% in[1][1] [127:0] $end - $var wire 128 C% in[1][2] [127:0] $end - $var wire 8 G% out[0][0] [7:0] $end - $var wire 8 H% out[0][1] [7:0] $end - $var wire 8 I% out[0][2] [7:0] $end - $var wire 8 J% out[1][0] [7:0] $end - $var wire 8 K% out[1][1] [7:0] $end - $var wire 8 L% out[1][2] [7:0] $end - $var wire 32 M% count [31:0] $end - $var wire 8 N# val0[0] [7:0] $end - $var wire 8 O# val0[1] [7:0] $end - $var wire 8 P# val1[0] [7:0] $end - $var wire 8 Q# val1[1] [7:0] $end - $var wire 8 R# val2[0] [7:0] $end - $var wire 8 S# val2[1] [7:0] $end - $var wire 8 T# val3[0] [7:0] $end - $var wire 8 U# val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 V# out[0] [7:0] $end - $var wire 8 W# out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 X# out[0] [7:0] $end - $var wire 8 Y# out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 Z# out[0] [7:0] $end - $var wire 8 [# out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 :' P1 [31:0] $end - $var wire 8 \# out[0] [7:0] $end - $var wire 8 ]# out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 N% i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 O% j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 P% exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 T% i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 U% j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 V% exp [7:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module i_sub3_2 $end - $var wire 8 .' P0 [7:0] $end - $var wire 32 =' UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 >' UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 1' UNUSED [15:0] $end - $var wire 2 2' ENUM [1:0] $end - $var wire 1 +' clk $end - $var wire 8 "$ in [7:0] $end - $var wire 8 $$ out [7:0] $end - $var wire 8 W% ff [7:0] $end - $var wire 8 $$ out4 [7:0] $end - $var wire 8 X% out4_2 [7:0] $end - $scope module i_sub4_0 $end - $var wire 32 3' P0 [31:0] $end - $var real 64 4' P1 $end - $var real 64 6' P3 $end - $var wire 1 +' clk $end - $var wire 8 W% in [7:0] $end - $var wire 8 $$ out [7:0] $end - $var wire 8 $$ ff [7:0] $end - $var wire 128 Y% sub5_in[0][0] [127:0] $end - $var wire 128 ]% sub5_in[0][1] [127:0] $end - $var wire 128 a% sub5_in[0][2] [127:0] $end - $var wire 128 e% sub5_in[1][0] [127:0] $end - $var wire 128 i% sub5_in[1][1] [127:0] $end - $var wire 128 m% sub5_in[1][2] [127:0] $end - $var wire 8 q% sub5_out[0][0] [7:0] $end - $var wire 8 r% sub5_out[0][1] [7:0] $end - $var wire 8 s% sub5_out[0][2] [7:0] $end - $var wire 8 t% sub5_out[1][0] [7:0] $end - $var wire 8 u% sub5_out[1][1] [7:0] $end - $var wire 8 v% sub5_out[1][2] [7:0] $end - $var wire 32 w% count [31:0] $end - $var wire 32 ^# driven_from_bind [31:0] $end - $scope module i_sub4_bound $end - $var real 64 4' P1 $end - $var wire 32 ^# driven_from_bind [31:0] $end - $upscope $end - $scope module i_sub5 $end - $var wire 1 +' clk $end - $var wire 128 x% in[0][0] [127:0] $end - $var wire 128 |% in[0][1] [127:0] $end - $var wire 128 "& in[0][2] [127:0] $end - $var wire 128 && in[1][0] [127:0] $end - $var wire 128 *& in[1][1] [127:0] $end - $var wire 128 .& in[1][2] [127:0] $end - $var wire 8 2& out[0][0] [7:0] $end - $var wire 8 3& out[0][1] [7:0] $end - $var wire 8 4& out[0][2] [7:0] $end - $var wire 8 5& out[1][0] [7:0] $end - $var wire 8 6& out[1][1] [7:0] $end - $var wire 8 7& out[1][2] [7:0] $end - $var wire 32 8& count [31:0] $end - $var wire 8 _# val0[0] [7:0] $end - $var wire 8 `# val0[1] [7:0] $end - $var wire 8 a# val1[0] [7:0] $end - $var wire 8 b# val1[1] [7:0] $end - $var wire 8 c# val2[0] [7:0] $end - $var wire 8 d# val2[1] [7:0] $end - $var wire 8 e# val3[0] [7:0] $end - $var wire 8 f# val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 g# out[0] [7:0] $end - $var wire 8 h# out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 i# out[0] [7:0] $end - $var wire 8 j# out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 k# out[0] [7:0] $end - $var wire 8 l# out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 :' P1 [31:0] $end - $var wire 8 m# out[0] [7:0] $end - $var wire 8 n# out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 9& i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 :& j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 ;& exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 ?& i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 @& j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 A& exp [7:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module i_sub4_1 $end - $var wire 32 3' P0 [31:0] $end - $var real 64 4' P1 $end - $var real 64 ;' P3 $end - $var wire 1 +' clk $end - $var wire 8 W% in [7:0] $end - $var wire 8 X% out [7:0] $end - $var wire 8 X% ff [7:0] $end - $var wire 128 B& sub5_in[0][0] [127:0] $end - $var wire 128 F& sub5_in[0][1] [127:0] $end - $var wire 128 J& sub5_in[0][2] [127:0] $end - $var wire 128 N& sub5_in[1][0] [127:0] $end - $var wire 128 R& sub5_in[1][1] [127:0] $end - $var wire 128 V& sub5_in[1][2] [127:0] $end - $var wire 8 Z& sub5_out[0][0] [7:0] $end - $var wire 8 [& sub5_out[0][1] [7:0] $end - $var wire 8 \& sub5_out[0][2] [7:0] $end - $var wire 8 ]& sub5_out[1][0] [7:0] $end - $var wire 8 ^& sub5_out[1][1] [7:0] $end - $var wire 8 _& sub5_out[1][2] [7:0] $end - $var wire 32 `& count [31:0] $end - $var wire 32 o# driven_from_bind [31:0] $end - $scope module i_sub4_bound $end - $var real 64 4' P1 $end - $var wire 32 o# driven_from_bind [31:0] $end - $upscope $end - $scope module i_sub5 $end - $var wire 1 +' clk $end - $var wire 128 a& in[0][0] [127:0] $end - $var wire 128 e& in[0][1] [127:0] $end - $var wire 128 i& in[0][2] [127:0] $end - $var wire 128 m& in[1][0] [127:0] $end - $var wire 128 q& in[1][1] [127:0] $end - $var wire 128 u& in[1][2] [127:0] $end - $var wire 8 y& out[0][0] [7:0] $end - $var wire 8 z& out[0][1] [7:0] $end - $var wire 8 {& out[0][2] [7:0] $end - $var wire 8 |& out[1][0] [7:0] $end - $var wire 8 }& out[1][1] [7:0] $end - $var wire 8 ~& out[1][2] [7:0] $end - $var wire 32 !' count [31:0] $end - $var wire 8 p# val0[0] [7:0] $end - $var wire 8 q# val0[1] [7:0] $end - $var wire 8 r# val1[0] [7:0] $end - $var wire 8 s# val1[1] [7:0] $end - $var wire 8 t# val2[0] [7:0] $end - $var wire 8 u# val2[1] [7:0] $end - $var wire 8 v# val3[0] [7:0] $end - $var wire 8 w# val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 x# out[0] [7:0] $end - $var wire 8 y# out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 z# out[0] [7:0] $end - $var wire 8 {# out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 |# out[0] [7:0] $end - $var wire 8 }# out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 :' P1 [31:0] $end - $var wire 8 ~# out[0] [7:0] $end - $var wire 8 !$ out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 "' i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 #' j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 $' exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 (' i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 )' j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 *' exp [7:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.i_sub3.i_sub4_0.i_sub5 $end - $var wire 1 u' clk $end - $var wire 128 v' in[0][0] [127:0] $end - $var wire 128 z' in[0][1] [127:0] $end - $var wire 128 ~' in[0][2] [127:0] $end - $var wire 128 $( in[1][0] [127:0] $end - $var wire 128 (( in[1][1] [127:0] $end - $var wire 128 ,( in[1][2] [127:0] $end - $var wire 8 0( out[0][0] [7:0] $end - $var wire 8 1( out[0][1] [7:0] $end - $var wire 8 2( out[0][2] [7:0] $end - $var wire 8 3( out[1][0] [7:0] $end - $var wire 8 4( out[1][1] [7:0] $end - $var wire 8 5( out[1][2] [7:0] $end - $scope module sub5 $end - $var wire 1 u' clk $end - $var wire 128 P' in[0][0] [127:0] $end - $var wire 128 T' in[0][1] [127:0] $end - $var wire 128 X' in[0][2] [127:0] $end - $var wire 128 \' in[1][0] [127:0] $end - $var wire 128 `' in[1][1] [127:0] $end - $var wire 128 d' in[1][2] [127:0] $end - $var wire 8 h' out[0][0] [7:0] $end - $var wire 8 i' out[0][1] [7:0] $end - $var wire 8 j' out[0][2] [7:0] $end - $var wire 8 k' out[1][0] [7:0] $end - $var wire 8 l' out[1][1] [7:0] $end - $var wire 8 m' out[1][2] [7:0] $end - $var wire 32 n' count [31:0] $end - $var wire 8 @' val0[0] [7:0] $end - $var wire 8 A' val0[1] [7:0] $end - $var wire 8 B' val1[0] [7:0] $end - $var wire 8 C' val1[1] [7:0] $end - $var wire 8 D' val2[0] [7:0] $end - $var wire 8 E' val2[1] [7:0] $end - $var wire 8 F' val3[0] [7:0] $end - $var wire 8 G' val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 6( P0 [31:0] $end - $var wire 32 7( P1 [31:0] $end - $var wire 8 H' out[0] [7:0] $end - $var wire 8 I' out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 6( P0 [31:0] $end - $var wire 32 7( P1 [31:0] $end - $var wire 8 J' out[0] [7:0] $end - $var wire 8 K' out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 6( P0 [31:0] $end - $var wire 32 7( P1 [31:0] $end - $var wire 8 L' out[0] [7:0] $end - $var wire 8 M' out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 6( P0 [31:0] $end - $var wire 32 8( P1 [31:0] $end - $var wire 8 N' out[0] [7:0] $end - $var wire 8 O' out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 o' i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 p' j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 q' exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.i_sub3.i_sub4_1.i_sub5 $end - $var wire 1 o( clk $end - $var wire 128 p( in[0][0] [127:0] $end - $var wire 128 t( in[0][1] [127:0] $end - $var wire 128 x( in[0][2] [127:0] $end - $var wire 128 |( in[1][0] [127:0] $end - $var wire 128 ") in[1][1] [127:0] $end - $var wire 128 &) in[1][2] [127:0] $end - $var wire 8 *) out[0][0] [7:0] $end - $var wire 8 +) out[0][1] [7:0] $end - $var wire 8 ,) out[0][2] [7:0] $end - $var wire 8 -) out[1][0] [7:0] $end - $var wire 8 .) out[1][1] [7:0] $end - $var wire 8 /) out[1][2] [7:0] $end - $scope module sub5 $end - $var wire 1 o( clk $end - $var wire 128 J( in[0][0] [127:0] $end - $var wire 128 N( in[0][1] [127:0] $end - $var wire 128 R( in[0][2] [127:0] $end - $var wire 128 V( in[1][0] [127:0] $end - $var wire 128 Z( in[1][1] [127:0] $end - $var wire 128 ^( in[1][2] [127:0] $end - $var wire 8 b( out[0][0] [7:0] $end - $var wire 8 c( out[0][1] [7:0] $end - $var wire 8 d( out[0][2] [7:0] $end - $var wire 8 e( out[1][0] [7:0] $end - $var wire 8 f( out[1][1] [7:0] $end - $var wire 8 g( out[1][2] [7:0] $end - $var wire 32 h( count [31:0] $end - $var wire 8 :( val0[0] [7:0] $end - $var wire 8 ;( val0[1] [7:0] $end - $var wire 8 <( val1[0] [7:0] $end - $var wire 8 =( val1[1] [7:0] $end - $var wire 8 >( val2[0] [7:0] $end - $var wire 8 ?( val2[1] [7:0] $end - $var wire 8 @( val3[0] [7:0] $end - $var wire 8 A( val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 0) P0 [31:0] $end - $var wire 32 1) P1 [31:0] $end - $var wire 8 B( out[0] [7:0] $end - $var wire 8 C( out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 0) P0 [31:0] $end - $var wire 32 1) P1 [31:0] $end - $var wire 8 D( out[0] [7:0] $end - $var wire 8 E( out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 0) P0 [31:0] $end - $var wire 32 1) P1 [31:0] $end - $var wire 8 F( out[0] [7:0] $end - $var wire 8 G( out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 0) P0 [31:0] $end - $var wire 32 2) P1 [31:0] $end - $var wire 8 H( out[0] [7:0] $end - $var wire 8 I( out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 i( i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 j( j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 k( exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.i_sub3_2.i_sub4_0.i_sub5 $end - $var wire 1 i) clk $end - $var wire 128 j) in[0][0] [127:0] $end - $var wire 128 n) in[0][1] [127:0] $end - $var wire 128 r) in[0][2] [127:0] $end - $var wire 128 v) in[1][0] [127:0] $end - $var wire 128 z) in[1][1] [127:0] $end - $var wire 128 ~) in[1][2] [127:0] $end - $var wire 8 $* out[0][0] [7:0] $end - $var wire 8 %* out[0][1] [7:0] $end - $var wire 8 &* out[0][2] [7:0] $end - $var wire 8 '* out[1][0] [7:0] $end - $var wire 8 (* out[1][1] [7:0] $end - $var wire 8 )* out[1][2] [7:0] $end - $scope module sub5 $end - $var wire 1 i) clk $end - $var wire 128 D) in[0][0] [127:0] $end - $var wire 128 H) in[0][1] [127:0] $end - $var wire 128 L) in[0][2] [127:0] $end - $var wire 128 P) in[1][0] [127:0] $end - $var wire 128 T) in[1][1] [127:0] $end - $var wire 128 X) in[1][2] [127:0] $end - $var wire 8 \) out[0][0] [7:0] $end - $var wire 8 ]) out[0][1] [7:0] $end - $var wire 8 ^) out[0][2] [7:0] $end - $var wire 8 _) out[1][0] [7:0] $end - $var wire 8 `) out[1][1] [7:0] $end - $var wire 8 a) out[1][2] [7:0] $end - $var wire 32 b) count [31:0] $end - $var wire 8 4) val0[0] [7:0] $end - $var wire 8 5) val0[1] [7:0] $end - $var wire 8 6) val1[0] [7:0] $end - $var wire 8 7) val1[1] [7:0] $end - $var wire 8 8) val2[0] [7:0] $end - $var wire 8 9) val2[1] [7:0] $end - $var wire 8 :) val3[0] [7:0] $end - $var wire 8 ;) val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 ** P0 [31:0] $end - $var wire 32 +* P1 [31:0] $end - $var wire 8 <) out[0] [7:0] $end - $var wire 8 =) out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 ** P0 [31:0] $end - $var wire 32 +* P1 [31:0] $end - $var wire 8 >) out[0] [7:0] $end - $var wire 8 ?) out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 ** P0 [31:0] $end - $var wire 32 +* P1 [31:0] $end - $var wire 8 @) out[0] [7:0] $end - $var wire 8 A) out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 ** P0 [31:0] $end - $var wire 32 ,* P1 [31:0] $end - $var wire 8 B) out[0] [7:0] $end - $var wire 8 C) out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 c) i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 d) j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 e) exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.i_sub3_2.i_sub4_1.i_sub5 $end - $var wire 1 c* clk $end - $var wire 128 d* in[0][0] [127:0] $end - $var wire 128 h* in[0][1] [127:0] $end - $var wire 128 l* in[0][2] [127:0] $end - $var wire 128 p* in[1][0] [127:0] $end - $var wire 128 t* in[1][1] [127:0] $end - $var wire 128 x* in[1][2] [127:0] $end - $var wire 8 |* out[0][0] [7:0] $end - $var wire 8 }* out[0][1] [7:0] $end - $var wire 8 ~* out[0][2] [7:0] $end - $var wire 8 !+ out[1][0] [7:0] $end - $var wire 8 "+ out[1][1] [7:0] $end - $var wire 8 #+ out[1][2] [7:0] $end - $scope module sub5 $end - $var wire 1 c* clk $end - $var wire 128 >* in[0][0] [127:0] $end - $var wire 128 B* in[0][1] [127:0] $end - $var wire 128 F* in[0][2] [127:0] $end - $var wire 128 J* in[1][0] [127:0] $end - $var wire 128 N* in[1][1] [127:0] $end - $var wire 128 R* in[1][2] [127:0] $end - $var wire 8 V* out[0][0] [7:0] $end - $var wire 8 W* out[0][1] [7:0] $end - $var wire 8 X* out[0][2] [7:0] $end - $var wire 8 Y* out[1][0] [7:0] $end - $var wire 8 Z* out[1][1] [7:0] $end - $var wire 8 [* out[1][2] [7:0] $end - $var wire 32 \* count [31:0] $end - $var wire 8 .* val0[0] [7:0] $end - $var wire 8 /* val0[1] [7:0] $end - $var wire 8 0* val1[0] [7:0] $end - $var wire 8 1* val1[1] [7:0] $end - $var wire 8 2* val2[0] [7:0] $end - $var wire 8 3* val2[1] [7:0] $end - $var wire 8 4* val3[0] [7:0] $end - $var wire 8 5* val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 $+ P0 [31:0] $end - $var wire 32 %+ P1 [31:0] $end - $var wire 8 6* out[0] [7:0] $end - $var wire 8 7* out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 $+ P0 [31:0] $end - $var wire 32 %+ P1 [31:0] $end - $var wire 8 8* out[0] [7:0] $end - $var wire 8 9* out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 $+ P0 [31:0] $end - $var wire 32 %+ P1 [31:0] $end - $var wire 8 :* out[0] [7:0] $end - $var wire 8 ;* out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 $+ P0 [31:0] $end - $var wire 32 &+ P1 [31:0] $end - $var wire 8 <* out[0] [7:0] $end - $var wire 8 =* out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 ]* i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 ^* j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 _* exp [127:0] $end - $upscope $end $upscope $end $upscope $end $upscope $end @@ -1055,6196 +766,4361 @@ $enddefinitions $end #0 +b00000000000000000000000000000110 " b00000000000000000000000000000110 # b00000000000000000000000000000110 $ b00000000000000000000000000000110 % -b00000000000000000000000000000110 & +b00000000 & b00000000 ' b00000000 ( -b00000000 ) -b00000000000000000000000000000000 * +b00000000000000000000000000000000 ) +b00000000 * b00000000 + b00000000 , b00000000 - -b00000000 . -b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 / -b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3 -b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 7 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+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 K' +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 O' +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 S' +b00000000 W' +b00000000 X' +b00000000 Y' +b00000000 Z' +b00000000 [' +b00000000 \' +b00000000000000000000000000010001 ]' +1^' #174 diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.py b/test_regress/t/t_hier_block_sc_trace_vcd.py index 0fbd7237a..3611b93bf 100755 --- a/test_regress/t/t_hier_block_sc_trace_vcd.py +++ b/test_regress/t/t_hier_block_sc_trace_vcd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_signed_logic.py b/test_regress/t/t_hier_block_signed_logic.py index 7bba1f55e..cb667c1ec 100755 --- a/test_regress/t/t_hier_block_signed_logic.py +++ b/test_regress/t/t_hier_block_signed_logic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_signed_logic.v b/test_regress/t/t_hier_block_signed_logic.v index a77fe0101..b2dcd97c8 100644 --- a/test_regress/t/t_hier_block_signed_logic.v +++ b/test_regress/t/t_hier_block_signed_logic.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_hier_block_struct.py b/test_regress/t/t_hier_block_struct.py index 1f3ee62cc..86f31f21b 100755 --- a/test_regress/t/t_hier_block_struct.py +++ b/test_regress/t/t_hier_block_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_struct.v b/test_regress/t/t_hier_block_struct.v index a3bec94b6..168392b72 100644 --- a/test_regress/t/t_hier_block_struct.v +++ b/test_regress/t/t_hier_block_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Varun Koyyalagunta. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 typedef struct packed { diff --git a/test_regress/t/t_hier_block_struct_nohier.py b/test_regress/t/t_hier_block_struct_nohier.py index 8545961d7..f212303f1 100755 --- a/test_regress/t/t_hier_block_struct_nohier.py +++ b/test_regress/t/t_hier_block_struct_nohier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_threads_bad.py b/test_regress/t/t_hier_block_threads_bad.py index d766e4db1..f26c32f77 100755 --- a/test_regress/t/t_hier_block_threads_bad.py +++ b/test_regress/t/t_hier_block_threads_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_threads_bad.v b/test_regress/t/t_hier_block_threads_bad.v index 04c72b276..b2dc314a0 100644 --- a/test_regress/t/t_hier_block_threads_bad.v +++ b/test_regress/t/t_hier_block_threads_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_hier_block_threads_bad.vlt b/test_regress/t/t_hier_block_threads_bad.vlt index d6cf050b2..b79332c29 100644 --- a/test_regress/t/t_hier_block_threads_bad.vlt +++ b/test_regress/t/t_hier_block_threads_bad.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_hier_block_trace_fst.out b/test_regress/t/t_hier_block_trace_fst.out index 8f3aa8849..1c1fcda23 100644 --- a/test_regress/t/t_hier_block_trace_fst.out +++ b/test_regress/t/t_hier_block_trace_fst.out @@ -1,5 +1,5 @@ $date - Mon Nov 10 12:27:19 2025 + Tue Feb 17 01:31:48 2026 $end $version @@ -11,846 +11,753 @@ $end $scope module top $end $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 1 $end $var wire 1 ! clk $end +$scope module stateless_pkg $end +$var parameter 32 " ONE [31:0] $end +$upscope $end $scope module t $end -$var parameter 32 " PARAM_A [31:0] $end -$var parameter 32 # PARAM_B [31:0] $end +$var parameter 32 # PARAM_A [31:0] $end +$var parameter 32 $ PARAM_B [31:0] $end $var wire 1 ! clk $end -$var wire 8 $ out0 [7:0] $end -$var wire 8 % out1 [7:0] $end -$var wire 8 & out2 [7:0] $end -$var wire 8 ' out3 [7:0] $end -$var wire 8 ( out3_2 [7:0] $end -$var wire 8 ) out5 [7:0] $end -$var wire 8 * out6 [7:0] $end -$var int 32 + count [31:0] $end +$var wire 8 % out0 [7:0] $end +$var wire 8 & out1 [7:0] $end +$var wire 8 ' out2 [7:0] $end +$var wire 8 ( out3 [7:0] $end +$var wire 8 ) out3_2 [7:0] $end +$var wire 8 * out5 [7:0] $end +$var wire 8 + out6 [7:0] $end +$var int 32 , count [31:0] $end $scope module i_delay0 $end -$var parameter 32 , N [31:0] $end -$var parameter 32 - WIDTH [31:0] $end +$var parameter 32 - N [31:0] $end +$var parameter 32 . WIDTH [31:0] $end $var wire 1 ! clk $end -$var wire 8 ' in [7:0] $end -$var wire 8 ) out [7:0] $end -$var logic 8 . tmp [7:0] $end +$var wire 8 ( in [7:0] $end +$var wire 8 * out [7:0] $end +$var logic 8 / tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end -$var parameter 32 / N [31:0] $end -$var parameter 32 - WIDTH [31:0] $end -$var wire 1 ! clk $end -$var wire 8 . in [7:0] $end -$var wire 8 ) out [7:0] $end -$var logic 8 ) tmp [7:0] $end -$upscope $end -$upscope $end -$upscope $end -$scope module i_delay1 $end $var parameter 32 0 N [31:0] $end -$var parameter 32 - WIDTH [31:0] $end +$var parameter 32 . WIDTH [31:0] $end $var wire 1 ! clk $end -$var wire 8 ) in [7:0] $end -$var wire 8 * out [7:0] $end -$var logic 8 1 tmp [7:0] $end -$scope module genblk1 $end -$scope module i_delay $end -$var parameter 32 , N [31:0] $end -$var parameter 32 - WIDTH [31:0] $end -$var wire 1 ! clk $end -$var wire 8 1 in [7:0] $end -$var wire 8 * out [7:0] $end -$var logic 8 2 tmp [7:0] $end -$scope module genblk1 $end -$scope module i_delay $end -$var parameter 32 / N [31:0] $end -$var parameter 32 - WIDTH [31:0] $end -$var wire 1 ! clk $end -$var wire 8 2 in [7:0] $end +$var wire 8 / in [7:0] $end $var wire 8 * out [7:0] $end $var logic 8 * tmp [7:0] $end $upscope $end $upscope $end $upscope $end +$scope module i_delay1 $end +$var parameter 32 1 N [31:0] $end +$var parameter 32 . WIDTH [31:0] $end +$var wire 1 ! clk $end +$var wire 8 * in [7:0] $end +$var wire 8 + out [7:0] $end +$var logic 8 2 tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var parameter 32 - N [31:0] $end +$var parameter 32 . WIDTH [31:0] $end +$var wire 1 ! clk $end +$var wire 8 2 in [7:0] $end +$var wire 8 + out [7:0] $end +$var logic 8 3 tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var parameter 32 0 N [31:0] $end +$var parameter 32 . WIDTH [31:0] $end +$var wire 1 ! clk $end +$var wire 8 3 in [7:0] $end +$var wire 8 + out [7:0] $end +$var logic 8 + tmp [7:0] $end +$upscope $end +$upscope $end +$upscope $end $upscope $end $upscope $end $scope module i_sub0 $end $var wire 1 ! clk $end -$var wire 8 ' in [7:0] $end -$var wire 8 $ out [7:0] $end +$var wire 8 ( in [7:0] $end +$var wire 8 % out [7:0] $end $scope module i_sub0 $end -$var wire 1 ! clk $end -$var wire 8 ' in [7:0] $end -$var wire 8 $ out [7:0] $end +$var wire 1 4 clk $end +$var wire 8 5 in [7:0] $end +$var wire 8 6 out [7:0] $end +$var logic 8 6 ff [7:0] $end $upscope $end $upscope $end $scope module i_sub1 $end -$var wire 1 ! clk $end -$var wire 8 $ in [11:4] $end -$var wire 8 % out [7:0] $end -$upscope $end -$scope module i_sub2 $end -$var wire 1 ! clk $end -$var wire 8 % in [7:0] $end -$var wire 8 & out [7:0] $end -$upscope $end -$scope module i_sub3 $end -$var parameter 8 3 P0 [7:0] $end -$var parameter 32 4 UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 5 UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 6 UNUSED [15:0] $end -$attrbegin misc 07 "" 1 $end -$var parameter 2 7 ENUM [1:0] $end -$var wire 1 ! clk $end -$var wire 8 & in [7:0] $end -$var wire 8 ' out [7:0] $end -$var logic 8 8 ff [7:0] $end -$var wire 8 ' out4 [7:0] $end -$var wire 8 9 out4_2 [7:0] $end -$scope module i_sub4_0 $end -$var parameter 32 : P0 [31:0] $end -$var real_parameter 64 ; P1 $end -$var real_parameter 64 < P3 $end -$var wire 1 ! clk $end -$var wire 8 8 in [7:0] $end -$var wire 8 ' out [7:0] $end -$var logic 8 ' ff [7:0] $end -$var logic 128 = sub5_in[0][0] [127:0] $end -$var logic 128 > sub5_in[0][1] [127:0] $end -$var logic 128 ? sub5_in[0][2] [127:0] $end -$var logic 128 @ sub5_in[1][0] [127:0] $end -$var logic 128 A sub5_in[1][1] [127:0] $end -$var logic 128 B sub5_in[1][2] [127:0] $end -$var wire 8 C sub5_out[0][0] [7:0] $end -$var wire 8 D sub5_out[0][1] [7:0] $end -$var wire 8 E sub5_out[0][2] [7:0] $end -$var wire 8 F sub5_out[1][0] [7:0] $end -$var wire 8 G sub5_out[1][1] [7:0] $end -$var wire 8 H sub5_out[1][2] [7:0] $end -$var int 32 I count [31:0] $end -$var int 32 J driven_from_bind [31:0] $end -$scope module i_sub4_bound $end -$var real_parameter 64 ; P1 $end -$var wire 32 J driven_from_bind [31:0] $end -$upscope $end -$scope module i_sub5 $end -$var wire 1 ! clk $end -$var wire 128 K in[0][0] [127:0] $end -$var wire 128 L in[0][1] [127:0] $end -$var wire 128 M in[0][2] [127:0] $end -$var wire 128 N in[1][0] [127:0] $end -$var wire 128 O in[1][1] [127:0] $end -$var wire 128 P in[1][2] [127:0] $end -$var wire 8 Q out[0][0] [7:0] $end -$var wire 8 R out[0][1] [7:0] $end -$var wire 8 S out[0][2] [7:0] $end -$var wire 8 T out[1][0] [7:0] $end -$var wire 8 U out[1][1] [7:0] $end -$var wire 8 V out[1][2] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 W i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 X j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 Y exp [7:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module i_sub4_1 $end -$var parameter 32 : P0 [31:0] $end -$var real_parameter 64 ; P1 $end -$var real_parameter 64 Z P3 $end -$var wire 1 ! clk $end -$var wire 8 8 in [7:0] $end +$attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 2 $end +$var wire 1 7 clk $end +$var wire 8 8 in [11:4] $end $var wire 8 9 out [7:0] $end $var logic 8 9 ff [7:0] $end -$var logic 128 [ sub5_in[0][0] [127:0] $end -$var logic 128 \ sub5_in[0][1] [127:0] $end -$var logic 128 ] sub5_in[0][2] [127:0] $end -$var logic 128 ^ sub5_in[1][0] [127:0] $end -$var logic 128 _ sub5_in[1][1] [127:0] $end -$var logic 128 ` sub5_in[1][2] [127:0] $end -$var wire 8 a sub5_out[0][0] [7:0] $end -$var wire 8 b sub5_out[0][1] [7:0] $end -$var wire 8 c sub5_out[0][2] [7:0] $end -$var wire 8 d sub5_out[1][0] [7:0] $end -$var wire 8 e sub5_out[1][1] [7:0] $end -$var wire 8 f sub5_out[1][2] [7:0] $end -$var int 32 g count [31:0] $end -$var int 32 h driven_from_bind [31:0] $end +$attrbegin misc 07 "" 2 $end +$var logic 2 : enum_v [1:0] $end +$upscope $end +$scope module i_sub2 $end +$attrbegin misc 07 $unit::alt_enum_t 4 alt_enum_0 alt_enum_1 alt_enum_2 alt_enum_3 00 01 10 11 3 $end +$attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 4 $end +$var wire 1 ; clk $end +$var wire 8 < in [7:0] $end +$var wire 8 = out [7:0] $end +$var logic 8 > ff [7:0] $end +$attrbegin misc 07 "" 3 $end +$var logic 2 ? alt_enum_v [1:0] $end +$scope module i_sub3 $end +$var wire 8 > in_wire [7:0] $end +$var wire 8 @ out_1 [7:0] $end +$var wire 8 A out_2 [7:0] $end +$scope module i_sub3 $end +$var parameter 8 B P0 [7:0] $end +$var parameter 32 C UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 D UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 E UNUSED [15:0] $end +$attrbegin misc 07 "" 4 $end +$var parameter 2 F ENUM [1:0] $end +$var wire 1 ; clk $end +$var wire 8 > in [7:0] $end +$var wire 8 @ out [7:0] $end +$var logic 1 G ff[0] $end +$var logic 1 H ff[1] $end +$var logic 1 I ff[2] $end +$var logic 1 J ff[3] $end +$var logic 1 K ff[4] $end +$var logic 1 L ff[5] $end +$var logic 1 M ff[6] $end +$var logic 1 N ff[7] $end +$var wire 8 @ out4 [7:0] $end +$var wire 8 O out4_2 [7:0] $end +$scope module i_sub4_0 $end +$var parameter 32 P P0 [31:0] $end +$var real_parameter 64 Q P1 $end +$var real_parameter 64 R P3 $end +$var wire 1 ; clk $end +$var wire 8 S in [7:0] $end +$var wire 8 @ out [7:0] $end +$var logic 8 @ ff [7:0] $end +$var logic 128 T sub5_in[0][0] [127:0] $end +$var logic 128 U sub5_in[0][1] [127:0] $end +$var logic 128 V sub5_in[0][2] [127:0] $end +$var logic 128 W sub5_in[1][0] [127:0] $end +$var logic 128 X sub5_in[1][1] [127:0] $end +$var logic 128 Y sub5_in[1][2] [127:0] $end +$var wire 8 Z sub5_out[0][0] [7:0] $end +$var wire 8 [ sub5_out[0][1] [7:0] $end +$var wire 8 \ sub5_out[0][2] [7:0] $end +$var wire 8 ] sub5_out[1][0] [7:0] $end +$var wire 8 ^ sub5_out[1][1] [7:0] $end +$var wire 8 _ sub5_out[1][2] [7:0] $end +$var int 32 ` count [31:0] $end +$var int 32 a driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 ; P1 $end -$var wire 32 h driven_from_bind [31:0] $end +$var real_parameter 64 Q P1 $end +$var wire 32 a driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 ! clk $end -$var wire 128 i in[0][0] [127:0] $end -$var wire 128 j in[0][1] [127:0] $end -$var wire 128 k in[0][2] [127:0] $end -$var wire 128 l in[1][0] [127:0] $end -$var wire 128 m in[1][1] [127:0] $end -$var wire 128 n in[1][2] [127:0] $end -$var wire 8 o out[0][0] [7:0] $end -$var wire 8 p out[0][1] [7:0] $end -$var wire 8 q out[0][2] [7:0] $end -$var wire 8 r out[1][0] [7:0] $end -$var wire 8 s out[1][1] [7:0] $end -$var wire 8 t out[1][2] [7:0] $end +$var wire 1 ; clk $end +$var wire 128 b in[0][0] [127:0] $end +$var wire 128 c in[0][1] [127:0] $end +$var wire 128 d in[0][2] [127:0] $end +$var wire 128 e in[1][0] [127:0] $end +$var wire 128 f in[1][1] [127:0] $end +$var wire 128 g in[1][2] [127:0] $end +$var wire 8 h out[0][0] [7:0] $end +$var wire 8 i out[0][1] [7:0] $end +$var wire 8 j out[0][2] [7:0] $end +$var wire 8 k out[1][0] [7:0] $end +$var wire 8 l out[1][1] [7:0] $end +$var wire 8 m out[1][2] [7:0] $end +$var int 32 n count [31:0] $end +$var wire 8 o val0[0] [7:0] $end +$var wire 8 p val0[1] [7:0] $end +$var wire 8 q val1[0] [7:0] $end +$var wire 8 r val1[1] [7:0] $end +$var wire 8 s val2[0] [7:0] $end +$var wire 8 t val2[1] [7:0] $end +$var wire 8 u val3[0] [7:0] $end +$var wire 8 v val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 y out[0] [7:0] $end +$var wire 8 z out[1] [7:0] $end $upscope $end -$scope module unnamedblk1 $end -$var int 32 u i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 v j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 w exp [7:0] $end +$scope module i_sub1 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 { out[0] [7:0] $end +$var wire 8 | out[1] [7:0] $end $upscope $end +$scope module i_sub2 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 } out[0] [7:0] $end +$var wire 8 ~ out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 !! P1 [31:0] $end +$var wire 8 "! out[0] [7:0] $end +$var wire 8 #! out[1] [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module i_sub4_1 $end +$var parameter 32 P P0 [31:0] $end +$var real_parameter 64 Q P1 $end +$var real_parameter 64 $! P3 $end +$var wire 1 ; clk $end +$var wire 8 S in [7:0] $end +$var wire 8 O out [7:0] $end +$var logic 8 O ff [7:0] $end +$var logic 128 %! sub5_in[0][0] [127:0] $end +$var logic 128 &! sub5_in[0][1] [127:0] $end +$var logic 128 '! sub5_in[0][2] [127:0] $end +$var logic 128 (! sub5_in[1][0] [127:0] $end +$var logic 128 )! sub5_in[1][1] [127:0] $end +$var logic 128 *! sub5_in[1][2] [127:0] $end +$var wire 8 +! sub5_out[0][0] [7:0] $end +$var wire 8 ,! sub5_out[0][1] [7:0] $end +$var wire 8 -! sub5_out[0][2] [7:0] $end +$var wire 8 .! sub5_out[1][0] [7:0] $end +$var wire 8 /! sub5_out[1][1] [7:0] $end +$var wire 8 0! sub5_out[1][2] [7:0] $end +$var int 32 1! count [31:0] $end +$var int 32 2! driven_from_bind [31:0] $end +$scope module i_sub4_bound $end +$var real_parameter 64 Q P1 $end +$var wire 32 2! driven_from_bind [31:0] $end +$upscope $end +$scope module i_sub5 $end +$var wire 1 ; clk $end +$var wire 128 3! in[0][0] [127:0] $end +$var wire 128 4! in[0][1] [127:0] $end +$var wire 128 5! in[0][2] [127:0] $end +$var wire 128 6! in[1][0] [127:0] $end +$var wire 128 7! in[1][1] [127:0] $end +$var wire 128 8! in[1][2] [127:0] $end +$var wire 8 9! out[0][0] [7:0] $end +$var wire 8 :! out[0][1] [7:0] $end +$var wire 8 ;! out[0][2] [7:0] $end +$var wire 8 ! out[1][2] [7:0] $end +$var int 32 ?! count [31:0] $end +$var wire 8 @! val0[0] [7:0] $end +$var wire 8 A! val0[1] [7:0] $end +$var wire 8 B! val1[0] [7:0] $end +$var wire 8 C! val1[1] [7:0] $end +$var wire 8 D! val2[0] [7:0] $end +$var wire 8 E! val2[1] [7:0] $end +$var wire 8 F! val3[0] [7:0] $end +$var wire 8 G! val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 H! out[0] [7:0] $end +$var wire 8 I! out[1] [7:0] $end +$upscope $end +$scope module i_sub1 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 J! out[0] [7:0] $end +$var wire 8 K! out[1] [7:0] $end +$upscope $end +$scope module i_sub2 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 L! out[0] [7:0] $end +$var wire 8 M! out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 !! P1 [31:0] $end +$var wire 8 N! out[0] [7:0] $end +$var wire 8 O! out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end -$var parameter 8 3 P0 [7:0] $end -$var parameter 32 x UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 y UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 6 UNUSED [15:0] $end -$attrbegin misc 07 "" 1 $end -$var parameter 2 7 ENUM [1:0] $end -$var wire 1 ! clk $end -$var wire 8 & in [7:0] $end -$var wire 8 ( out [7:0] $end -$var logic 8 z ff [7:0] $end -$var wire 8 ( out4 [7:0] $end -$var wire 8 { out4_2 [7:0] $end +$var parameter 8 B P0 [7:0] $end +$var parameter 32 P! UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 Q! UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 E UNUSED [15:0] $end +$attrbegin misc 07 "" 4 $end +$var parameter 2 F ENUM [1:0] $end +$var wire 1 ; clk $end +$var wire 8 > in [7:0] $end +$var wire 8 A out [7:0] $end +$var logic 1 R! ff[0] $end +$var logic 1 S! ff[1] $end +$var logic 1 T! ff[2] $end +$var logic 1 U! ff[3] $end +$var logic 1 V! ff[4] $end +$var logic 1 W! ff[5] $end +$var logic 1 X! ff[6] $end +$var logic 1 Y! ff[7] $end +$var wire 8 A out4 [7:0] $end +$var wire 8 Z! out4_2 [7:0] $end $scope module i_sub4_0 $end -$var parameter 32 : P0 [31:0] $end -$var real_parameter 64 ; P1 $end -$var real_parameter 64 < P3 $end -$var wire 1 ! clk $end -$var wire 8 z in [7:0] $end -$var wire 8 ( out [7:0] $end -$var logic 8 ( ff [7:0] $end -$var logic 128 | sub5_in[0][0] [127:0] $end -$var logic 128 } sub5_in[0][1] [127:0] $end -$var logic 128 ~ sub5_in[0][2] [127:0] $end -$var logic 128 !! sub5_in[1][0] [127:0] $end -$var logic 128 "! sub5_in[1][1] [127:0] $end -$var logic 128 #! sub5_in[1][2] [127:0] $end -$var wire 8 $! sub5_out[0][0] [7:0] $end -$var wire 8 %! sub5_out[0][1] [7:0] $end -$var wire 8 &! sub5_out[0][2] [7:0] $end -$var wire 8 '! sub5_out[1][0] [7:0] $end -$var wire 8 (! sub5_out[1][1] [7:0] $end -$var wire 8 )! sub5_out[1][2] [7:0] $end -$var int 32 *! count [31:0] $end -$var int 32 +! driven_from_bind [31:0] $end +$var parameter 32 P P0 [31:0] $end +$var real_parameter 64 Q P1 $end +$var real_parameter 64 R P3 $end +$var wire 1 ; clk $end +$var wire 8 [! in [7:0] $end +$var wire 8 A out [7:0] $end +$var logic 8 A ff [7:0] $end +$var logic 128 \! sub5_in[0][0] [127:0] $end +$var logic 128 ]! sub5_in[0][1] [127:0] $end +$var logic 128 ^! sub5_in[0][2] [127:0] $end +$var logic 128 _! sub5_in[1][0] [127:0] $end +$var logic 128 `! sub5_in[1][1] [127:0] $end +$var logic 128 a! sub5_in[1][2] [127:0] $end +$var wire 8 b! sub5_out[0][0] [7:0] $end +$var wire 8 c! sub5_out[0][1] [7:0] $end +$var wire 8 d! sub5_out[0][2] [7:0] $end +$var wire 8 e! sub5_out[1][0] [7:0] $end +$var wire 8 f! sub5_out[1][1] [7:0] $end +$var wire 8 g! sub5_out[1][2] [7:0] $end +$var int 32 h! count [31:0] $end +$var int 32 i! driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 ; P1 $end -$var wire 32 +! driven_from_bind [31:0] $end +$var real_parameter 64 Q P1 $end +$var wire 32 i! driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 ! clk $end -$var wire 128 ,! in[0][0] [127:0] $end -$var wire 128 -! in[0][1] [127:0] $end -$var wire 128 .! in[0][2] [127:0] $end -$var wire 128 /! in[1][0] [127:0] $end -$var wire 128 0! in[1][1] [127:0] $end -$var wire 128 1! in[1][2] [127:0] $end -$var wire 8 2! out[0][0] [7:0] $end -$var wire 8 3! out[0][1] [7:0] $end -$var wire 8 4! out[0][2] [7:0] $end -$var wire 8 5! out[1][0] [7:0] $end -$var wire 8 6! out[1][1] [7:0] $end -$var wire 8 7! out[1][2] [7:0] $end +$var wire 1 ; clk $end +$var wire 128 j! in[0][0] [127:0] $end +$var wire 128 k! in[0][1] [127:0] $end +$var wire 128 l! in[0][2] [127:0] $end +$var wire 128 m! in[1][0] [127:0] $end +$var wire 128 n! in[1][1] [127:0] $end +$var wire 128 o! in[1][2] [127:0] $end +$var wire 8 p! out[0][0] [7:0] $end +$var wire 8 q! out[0][1] [7:0] $end +$var wire 8 r! out[0][2] [7:0] $end +$var wire 8 s! out[1][0] [7:0] $end +$var wire 8 t! out[1][1] [7:0] $end +$var wire 8 u! out[1][2] [7:0] $end +$var int 32 v! count [31:0] $end +$var wire 8 w! val0[0] [7:0] $end +$var wire 8 x! val0[1] [7:0] $end +$var wire 8 y! val1[0] [7:0] $end +$var wire 8 z! val1[1] [7:0] $end +$var wire 8 {! val2[0] [7:0] $end +$var wire 8 |! val2[1] [7:0] $end +$var wire 8 }! val3[0] [7:0] $end +$var wire 8 ~! val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 !" out[0] [7:0] $end +$var wire 8 "" out[1] [7:0] $end $upscope $end -$scope module unnamedblk1 $end -$var int 32 8! i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 9! j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 :! exp [7:0] $end +$scope module i_sub1 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 #" out[0] [7:0] $end +$var wire 8 $" out[1] [7:0] $end $upscope $end +$scope module i_sub2 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 %" out[0] [7:0] $end +$var wire 8 &" out[1] [7:0] $end +$upscope $end +$scope module i_sub3 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 !! P1 [31:0] $end +$var wire 8 '" out[0] [7:0] $end +$var wire 8 (" out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end -$var parameter 32 : P0 [31:0] $end -$var real_parameter 64 ; P1 $end -$var real_parameter 64 Z P3 $end -$var wire 1 ! clk $end -$var wire 8 z in [7:0] $end -$var wire 8 { out [7:0] $end -$var logic 8 { ff [7:0] $end -$var logic 128 ;! sub5_in[0][0] [127:0] $end -$var logic 128 ! sub5_in[1][0] [127:0] $end -$var logic 128 ?! sub5_in[1][1] [127:0] $end -$var logic 128 @! sub5_in[1][2] [127:0] $end -$var wire 8 A! sub5_out[0][0] [7:0] $end -$var wire 8 B! sub5_out[0][1] [7:0] $end -$var wire 8 C! sub5_out[0][2] [7:0] $end -$var wire 8 D! sub5_out[1][0] [7:0] $end -$var wire 8 E! sub5_out[1][1] [7:0] $end -$var wire 8 F! sub5_out[1][2] [7:0] $end -$var int 32 G! count [31:0] $end -$var int 32 H! driven_from_bind [31:0] $end +$var parameter 32 P P0 [31:0] $end +$var real_parameter 64 Q P1 $end +$var real_parameter 64 $! P3 $end +$var wire 1 ; clk $end +$var wire 8 [! in [7:0] $end +$var wire 8 Z! out [7:0] $end +$var logic 8 Z! ff [7:0] $end +$var logic 128 )" sub5_in[0][0] [127:0] $end +$var logic 128 *" sub5_in[0][1] [127:0] $end +$var logic 128 +" sub5_in[0][2] [127:0] $end +$var logic 128 ," sub5_in[1][0] [127:0] $end +$var logic 128 -" sub5_in[1][1] [127:0] $end +$var logic 128 ." sub5_in[1][2] [127:0] $end +$var wire 8 /" sub5_out[0][0] [7:0] $end +$var wire 8 0" sub5_out[0][1] [7:0] $end +$var wire 8 1" sub5_out[0][2] [7:0] $end +$var wire 8 2" sub5_out[1][0] [7:0] $end +$var wire 8 3" sub5_out[1][1] [7:0] $end +$var wire 8 4" sub5_out[1][2] [7:0] $end +$var int 32 5" count [31:0] $end +$var int 32 6" driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 ; P1 $end -$var wire 32 H! driven_from_bind [31:0] $end +$var real_parameter 64 Q P1 $end +$var wire 32 6" driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 ! clk $end -$var wire 128 I! in[0][0] [127:0] $end -$var wire 128 J! in[0][1] [127:0] $end -$var wire 128 K! in[0][2] [127:0] $end -$var wire 128 L! in[1][0] [127:0] $end -$var wire 128 M! in[1][1] [127:0] $end -$var wire 128 N! in[1][2] [127:0] $end -$var wire 8 O! out[0][0] [7:0] $end -$var wire 8 P! out[0][1] [7:0] $end -$var wire 8 Q! out[0][2] [7:0] $end -$var wire 8 R! out[1][0] [7:0] $end -$var wire 8 S! out[1][1] [7:0] $end -$var wire 8 T! out[1][2] [7:0] $end +$var wire 1 ; clk $end +$var wire 128 7" in[0][0] [127:0] $end +$var wire 128 8" in[0][1] [127:0] $end +$var wire 128 9" in[0][2] [127:0] $end +$var wire 128 :" in[1][0] [127:0] $end +$var wire 128 ;" in[1][1] [127:0] $end +$var wire 128 <" in[1][2] [127:0] $end +$var wire 8 =" out[0][0] [7:0] $end +$var wire 8 >" out[0][1] [7:0] $end +$var wire 8 ?" out[0][2] [7:0] $end +$var wire 8 @" out[1][0] [7:0] $end +$var wire 8 A" out[1][1] [7:0] $end +$var wire 8 B" out[1][2] [7:0] $end +$var int 32 C" count [31:0] $end +$var wire 8 D" val0[0] [7:0] $end +$var wire 8 E" val0[1] [7:0] $end +$var wire 8 F" val1[0] [7:0] $end +$var wire 8 G" val1[1] [7:0] $end +$var wire 8 H" val2[0] [7:0] $end +$var wire 8 I" val2[1] [7:0] $end +$var wire 8 J" val3[0] [7:0] $end +$var wire 8 K" val3[1] [7:0] $end +$scope module i_sub0 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 L" out[0] [7:0] $end +$var wire 8 M" out[1] [7:0] $end $upscope $end -$scope module unnamedblk1 $end -$var int 32 U! i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 V! j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 W! exp [7:0] $end +$scope module i_sub1 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 N" out[0] [7:0] $end +$var wire 8 O" out[1] [7:0] $end $upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module top.t.i_sub0.i_sub0 $end -$var wire 1 X! clk $end -$var wire 8 Y! in [7:0] $end -$var wire 8 Z! out [7:0] $end -$scope module sub0 $end -$var wire 1 X! clk $end -$var wire 8 Y! in [7:0] $end -$var wire 8 Z! out [7:0] $end -$var logic 8 [! ff [7:0] $end -$upscope $end -$upscope $end -$scope module top.t.i_sub1 $end -$var wire 1 \! clk $end -$var wire 8 ]! in [11:4] $end -$var wire 8 ^! out [7:0] $end -$scope module sub1 $end -$var wire 1 \! clk $end -$var wire 8 ]! in [11:4] $end -$var wire 8 ^! out [7:0] $end -$var logic 8 _! ff [7:0] $end -$upscope $end -$upscope $end -$scope module top.t.i_sub2 $end -$attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 2 $end -$var wire 1 `! clk $end -$var wire 8 a! in [7:0] $end -$var wire 8 b! out [7:0] $end -$scope module sub2 $end -$var wire 1 `! clk $end -$var wire 8 a! in [7:0] $end -$var wire 8 b! out [7:0] $end -$var logic 8 c! ff [7:0] $end -$scope interface in_ifs $end -$var wire 1 `! clk $end -$var logic 8 c! data [7:0] $end -$upscope $end -$scope interface out_ifs $end -$var wire 1 `! clk $end -$var logic 8 d! data [7:0] $end +$scope module i_sub2 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 x P1 [31:0] $end +$var wire 8 P" out[0] [7:0] $end +$var wire 8 Q" out[1] [7:0] $end $upscope $end $scope module i_sub3 $end +$var parameter 32 w P0 [31:0] $end +$var parameter 32 !! P1 [31:0] $end +$var wire 8 R" out[0] [7:0] $end +$var wire 8 S" out[1] [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end $scope interface in $end -$var wire 1 `! clk $end -$var logic 8 c! data [7:0] $end +$var wire 1 ; clk $end +$var logic 8 > data [7:0] $end $upscope $end $scope interface out $end -$var wire 1 `! clk $end -$var logic 8 d! data [7:0] $end +$var wire 1 ; clk $end +$var logic 8 @ data [7:0] $end +$upscope $end +$upscope $end +$scope interface in_ifs $end +$var wire 1 ; clk $end +$var logic 8 > data [7:0] $end +$upscope $end +$scope interface out_ifs $end +$var wire 1 ; clk $end +$var logic 8 @ data [7:0] $end +$upscope $end $upscope $end -$var wire 8 c! in_wire [7:0] $end -$var wire 8 d! out_1 [7:0] $end -$var wire 8 e! out_2 [7:0] $end $scope module i_sub3 $end -$var parameter 8 f! P0 [7:0] $end -$var parameter 32 g! UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 h! UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 i! UNUSED [15:0] $end -$attrbegin misc 07 "" 2 $end -$var parameter 2 j! ENUM [1:0] $end -$var wire 1 `! clk $end -$var wire 8 c! in [7:0] $end -$var wire 8 d! out [7:0] $end -$var logic 8 k! ff [7:0] $end -$var wire 8 d! out4 [7:0] $end -$var wire 8 l! out4_2 [7:0] $end +$var parameter 8 T" P0 [7:0] $end +$var parameter 32 U" UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 V" UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 W" UNUSED [15:0] $end +$attrbegin misc 07 "" 1 $end +$var parameter 2 X" ENUM [1:0] $end +$var wire 1 ! clk $end +$var wire 8 ' in [7:0] $end +$var wire 8 ( out [7:0] $end +$var logic 1 Y" ff[0] $end +$var logic 1 Z" ff[1] $end +$var logic 1 [" ff[2] $end +$var logic 1 \" ff[3] $end +$var logic 1 ]" ff[4] $end +$var logic 1 ^" ff[5] $end +$var logic 1 _" ff[6] $end +$var logic 1 `" ff[7] $end +$var wire 8 ( out4 [7:0] $end +$var wire 8 a" out4_2 [7:0] $end $scope module i_sub4_0 $end -$var parameter 32 m! P0 [31:0] $end -$var real_parameter 64 n! P1 $end -$var real_parameter 64 o! P3 $end -$var wire 1 `! clk $end -$var wire 8 k! in [7:0] $end -$var wire 8 d! out [7:0] $end -$var logic 8 d! ff [7:0] $end -$var logic 128 p! sub5_in[0][0] [127:0] $end -$var logic 128 q! sub5_in[0][1] [127:0] $end -$var logic 128 r! sub5_in[0][2] [127:0] $end -$var logic 128 s! sub5_in[1][0] [127:0] $end -$var logic 128 t! sub5_in[1][1] [127:0] $end -$var logic 128 u! sub5_in[1][2] [127:0] $end -$var wire 8 v! sub5_out[0][0] [7:0] $end -$var wire 8 w! sub5_out[0][1] [7:0] $end -$var wire 8 x! sub5_out[0][2] [7:0] $end -$var wire 8 y! sub5_out[1][0] [7:0] $end -$var wire 8 z! sub5_out[1][1] [7:0] $end -$var wire 8 {! sub5_out[1][2] [7:0] $end -$var int 32 |! count [31:0] $end -$var int 32 }! driven_from_bind [31:0] $end +$var parameter 32 b" P0 [31:0] $end +$var real_parameter 64 c" P1 $end +$var real_parameter 64 d" P3 $end +$var wire 1 ! clk $end +$var wire 8 e" in [7:0] $end +$var wire 8 ( out [7:0] $end +$var logic 8 ( ff [7:0] $end +$var logic 128 f" sub5_in[0][0] [127:0] $end +$var logic 128 g" sub5_in[0][1] [127:0] $end +$var logic 128 h" sub5_in[0][2] [127:0] $end +$var logic 128 i" sub5_in[1][0] [127:0] $end +$var logic 128 j" sub5_in[1][1] [127:0] $end +$var logic 128 k" sub5_in[1][2] [127:0] $end +$var wire 8 l" sub5_out[0][0] [7:0] $end +$var wire 8 m" sub5_out[0][1] [7:0] $end +$var wire 8 n" sub5_out[0][2] [7:0] $end +$var wire 8 o" sub5_out[1][0] [7:0] $end +$var wire 8 p" sub5_out[1][1] [7:0] $end +$var wire 8 q" sub5_out[1][2] [7:0] $end +$var int 32 r" count [31:0] $end +$var int 32 s" driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 n! P1 $end -$var wire 32 }! driven_from_bind [31:0] $end +$var real_parameter 64 c" P1 $end +$var wire 32 s" driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 `! clk $end -$var wire 128 ~! in[0][0] [127:0] $end -$var wire 128 !" in[0][1] [127:0] $end -$var wire 128 "" in[0][2] [127:0] $end -$var wire 128 #" in[1][0] [127:0] $end -$var wire 128 $" in[1][1] [127:0] $end -$var wire 128 %" in[1][2] [127:0] $end -$var wire 8 &" out[0][0] [7:0] $end -$var wire 8 '" out[0][1] [7:0] $end -$var wire 8 (" out[0][2] [7:0] $end -$var wire 8 )" out[1][0] [7:0] $end -$var wire 8 *" out[1][1] [7:0] $end -$var wire 8 +" out[1][2] [7:0] $end -$var int 32 ," count [31:0] $end -$var wire 8 -" val0[0] [7:0] $end -$var wire 8 ." val0[1] [7:0] $end -$var wire 8 /" val1[0] [7:0] $end -$var wire 8 0" val1[1] [7:0] $end -$var wire 8 1" val2[0] [7:0] $end -$var wire 8 2" val2[1] [7:0] $end -$var wire 8 3" val3[0] [7:0] $end -$var wire 8 4" val3[1] [7:0] $end +$var wire 1 t" clk $end +$var wire 128 u" in[0][0] [127:0] $end +$var wire 128 v" in[0][1] [127:0] $end +$var wire 128 w" in[0][2] [127:0] $end +$var wire 128 x" in[1][0] [127:0] $end +$var wire 128 y" in[1][1] [127:0] $end +$var wire 128 z" in[1][2] [127:0] $end +$var wire 8 {" out[0][0] [7:0] $end +$var wire 8 |" out[0][1] [7:0] $end +$var wire 8 }" out[0][2] [7:0] $end +$var wire 8 ~" out[1][0] [7:0] $end +$var wire 8 !# out[1][1] [7:0] $end +$var wire 8 "# out[1][2] [7:0] $end +$var int 32 ## count [31:0] $end +$var wire 8 $# val0[0] [7:0] $end +$var wire 8 %# val0[1] [7:0] $end +$var wire 8 &# val1[0] [7:0] $end +$var wire 8 '# val1[1] [7:0] $end +$var wire 8 (# val2[0] [7:0] $end +$var wire 8 )# val2[1] [7:0] $end +$var wire 8 *# val3[0] [7:0] $end +$var wire 8 +# val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 7" out[0] [7:0] $end -$var wire 8 8" out[1] [7:0] $end +$var parameter 32 ,# P0 [31:0] $end +$var parameter 32 -# P1 [31:0] $end +$var wire 8 .# out[0] [7:0] $end +$var wire 8 /# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 9" out[0] [7:0] $end -$var wire 8 :" out[1] [7:0] $end +$var parameter 32 ,# P0 [31:0] $end +$var parameter 32 -# P1 [31:0] $end +$var wire 8 0# out[0] [7:0] $end +$var wire 8 1# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 ;" out[0] [7:0] $end -$var wire 8 <" out[1] [7:0] $end +$var parameter 32 ,# P0 [31:0] $end +$var parameter 32 -# P1 [31:0] $end +$var wire 8 2# out[0] [7:0] $end +$var wire 8 3# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 =" P1 [31:0] $end -$var wire 8 >" out[0] [7:0] $end -$var wire 8 ?" out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 @" i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 A" j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 B" exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 C" i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 D" j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 E" exp [7:0] $end -$upscope $end +$var parameter 32 ,# P0 [31:0] $end +$var parameter 32 4# P1 [31:0] $end +$var wire 8 5# out[0] [7:0] $end +$var wire 8 6# out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end -$var parameter 32 m! P0 [31:0] $end -$var real_parameter 64 n! P1 $end -$var real_parameter 64 F" P3 $end -$var wire 1 `! clk $end -$var wire 8 k! in [7:0] $end -$var wire 8 l! out [7:0] $end -$var logic 8 l! ff [7:0] $end -$var logic 128 G" sub5_in[0][0] [127:0] $end -$var logic 128 H" sub5_in[0][1] [127:0] $end -$var logic 128 I" sub5_in[0][2] [127:0] $end -$var logic 128 J" sub5_in[1][0] [127:0] $end -$var logic 128 K" sub5_in[1][1] [127:0] $end -$var logic 128 L" sub5_in[1][2] [127:0] $end -$var wire 8 M" sub5_out[0][0] [7:0] $end -$var wire 8 N" sub5_out[0][1] [7:0] $end -$var wire 8 O" sub5_out[0][2] [7:0] $end -$var wire 8 P" sub5_out[1][0] [7:0] $end -$var wire 8 Q" sub5_out[1][1] [7:0] $end -$var wire 8 R" sub5_out[1][2] [7:0] $end -$var int 32 S" count [31:0] $end -$var int 32 T" driven_from_bind [31:0] $end +$var parameter 32 b" P0 [31:0] $end +$var real_parameter 64 c" P1 $end +$var real_parameter 64 7# P3 $end +$var wire 1 ! clk $end +$var wire 8 e" in [7:0] $end +$var wire 8 a" out [7:0] $end +$var logic 8 a" ff [7:0] $end +$var logic 128 8# sub5_in[0][0] [127:0] $end +$var logic 128 9# sub5_in[0][1] [127:0] $end +$var logic 128 :# sub5_in[0][2] [127:0] $end +$var logic 128 ;# sub5_in[1][0] [127:0] $end +$var logic 128 <# sub5_in[1][1] [127:0] $end +$var logic 128 =# sub5_in[1][2] [127:0] $end +$var wire 8 ># sub5_out[0][0] [7:0] $end +$var wire 8 ?# sub5_out[0][1] [7:0] $end +$var wire 8 @# sub5_out[0][2] [7:0] $end +$var wire 8 A# sub5_out[1][0] [7:0] $end +$var wire 8 B# sub5_out[1][1] [7:0] $end +$var wire 8 C# sub5_out[1][2] [7:0] $end +$var int 32 D# count [31:0] $end +$var int 32 E# driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 n! P1 $end -$var wire 32 T" driven_from_bind [31:0] $end +$var real_parameter 64 c" P1 $end +$var wire 32 E# driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 `! clk $end -$var wire 128 U" in[0][0] [127:0] $end -$var wire 128 V" in[0][1] [127:0] $end -$var wire 128 W" in[0][2] [127:0] $end -$var wire 128 X" in[1][0] [127:0] $end -$var wire 128 Y" in[1][1] [127:0] $end -$var wire 128 Z" in[1][2] [127:0] $end -$var wire 8 [" out[0][0] [7:0] $end -$var wire 8 \" out[0][1] [7:0] $end -$var wire 8 ]" out[0][2] [7:0] $end -$var wire 8 ^" out[1][0] [7:0] $end -$var wire 8 _" out[1][1] [7:0] $end -$var wire 8 `" out[1][2] [7:0] $end -$var int 32 a" count [31:0] $end -$var wire 8 b" val0[0] [7:0] $end -$var wire 8 c" val0[1] [7:0] $end -$var wire 8 d" val1[0] [7:0] $end -$var wire 8 e" val1[1] [7:0] $end -$var wire 8 f" val2[0] [7:0] $end -$var wire 8 g" val2[1] [7:0] $end -$var wire 8 h" val3[0] [7:0] $end -$var wire 8 i" val3[1] [7:0] $end +$var wire 1 F# clk $end +$var wire 128 G# in[0][0] [127:0] $end +$var wire 128 H# in[0][1] [127:0] $end +$var wire 128 I# in[0][2] [127:0] $end +$var wire 128 J# in[1][0] [127:0] $end +$var wire 128 K# in[1][1] [127:0] $end +$var wire 128 L# in[1][2] [127:0] $end +$var wire 8 M# out[0][0] [7:0] $end +$var wire 8 N# out[0][1] [7:0] $end +$var wire 8 O# out[0][2] [7:0] $end +$var wire 8 P# out[1][0] [7:0] $end +$var wire 8 Q# out[1][1] [7:0] $end +$var wire 8 R# out[1][2] [7:0] $end +$var int 32 S# count [31:0] $end +$var wire 8 T# val0[0] [7:0] $end +$var wire 8 U# val0[1] [7:0] $end +$var wire 8 V# val1[0] [7:0] $end +$var wire 8 W# val1[1] [7:0] $end +$var wire 8 X# val2[0] [7:0] $end +$var wire 8 Y# val2[1] [7:0] $end +$var wire 8 Z# val3[0] [7:0] $end +$var wire 8 [# val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 j" out[0] [7:0] $end -$var wire 8 k" out[1] [7:0] $end +$var parameter 32 \# P0 [31:0] $end +$var parameter 32 ]# P1 [31:0] $end +$var wire 8 ^# out[0] [7:0] $end +$var wire 8 _# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 l" out[0] [7:0] $end -$var wire 8 m" out[1] [7:0] $end +$var parameter 32 \# P0 [31:0] $end +$var parameter 32 ]# P1 [31:0] $end +$var wire 8 `# out[0] [7:0] $end +$var wire 8 a# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 n" out[0] [7:0] $end -$var wire 8 o" out[1] [7:0] $end +$var parameter 32 \# P0 [31:0] $end +$var parameter 32 ]# P1 [31:0] $end +$var wire 8 b# out[0] [7:0] $end +$var wire 8 c# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 =" P1 [31:0] $end -$var wire 8 p" out[0] [7:0] $end -$var wire 8 q" out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 r" i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 s" j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 t" exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 u" i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 v" j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 w" exp [7:0] $end -$upscope $end +$var parameter 32 \# P0 [31:0] $end +$var parameter 32 d# P1 [31:0] $end +$var wire 8 e# out[0] [7:0] $end +$var wire 8 f# out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end -$var parameter 8 f! P0 [7:0] $end -$var parameter 32 x" UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 y" UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 i! UNUSED [15:0] $end -$attrbegin misc 07 "" 2 $end -$var parameter 2 j! ENUM [1:0] $end -$var wire 1 `! clk $end -$var wire 8 c! in [7:0] $end -$var wire 8 e! out [7:0] $end -$var logic 8 z" ff [7:0] $end -$var wire 8 e! out4 [7:0] $end -$var wire 8 {" out4_2 [7:0] $end +$var parameter 8 T" P0 [7:0] $end +$var parameter 32 g# UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 h# UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 W" UNUSED [15:0] $end +$attrbegin misc 07 "" 1 $end +$var parameter 2 X" ENUM [1:0] $end +$var wire 1 ! clk $end +$var wire 8 ' in [7:0] $end +$var wire 8 ) out [7:0] $end +$var logic 1 i# ff[0] $end +$var logic 1 j# ff[1] $end +$var logic 1 k# ff[2] $end +$var logic 1 l# ff[3] $end +$var logic 1 m# ff[4] $end +$var logic 1 n# ff[5] $end +$var logic 1 o# ff[6] $end +$var logic 1 p# ff[7] $end +$var wire 8 ) out4 [7:0] $end +$var wire 8 q# out4_2 [7:0] $end $scope module i_sub4_0 $end -$var parameter 32 m! P0 [31:0] $end -$var real_parameter 64 n! P1 $end -$var real_parameter 64 o! P3 $end -$var wire 1 `! clk $end -$var wire 8 z" in [7:0] $end -$var wire 8 e! out [7:0] $end -$var logic 8 e! ff [7:0] $end -$var logic 128 |" sub5_in[0][0] [127:0] $end -$var logic 128 }" sub5_in[0][1] [127:0] $end -$var logic 128 ~" sub5_in[0][2] [127:0] $end -$var logic 128 !# sub5_in[1][0] [127:0] $end -$var logic 128 "# sub5_in[1][1] [127:0] $end -$var logic 128 ## sub5_in[1][2] [127:0] $end -$var wire 8 $# sub5_out[0][0] [7:0] $end -$var wire 8 %# sub5_out[0][1] [7:0] $end -$var wire 8 &# sub5_out[0][2] [7:0] $end -$var wire 8 '# sub5_out[1][0] [7:0] $end -$var wire 8 (# sub5_out[1][1] [7:0] $end -$var wire 8 )# sub5_out[1][2] [7:0] $end -$var int 32 *# count [31:0] $end -$var int 32 +# driven_from_bind [31:0] $end +$var parameter 32 b" P0 [31:0] $end +$var real_parameter 64 c" P1 $end +$var real_parameter 64 d" P3 $end +$var wire 1 ! clk $end +$var wire 8 r# in [7:0] $end +$var wire 8 ) out [7:0] $end +$var logic 8 ) ff [7:0] $end +$var logic 128 s# sub5_in[0][0] [127:0] $end +$var logic 128 t# sub5_in[0][1] [127:0] $end +$var logic 128 u# sub5_in[0][2] [127:0] $end +$var logic 128 v# sub5_in[1][0] [127:0] $end +$var logic 128 w# sub5_in[1][1] [127:0] $end +$var logic 128 x# sub5_in[1][2] [127:0] $end +$var wire 8 y# sub5_out[0][0] [7:0] $end +$var wire 8 z# sub5_out[0][1] [7:0] $end +$var wire 8 {# sub5_out[0][2] [7:0] $end +$var wire 8 |# sub5_out[1][0] [7:0] $end +$var wire 8 }# sub5_out[1][1] [7:0] $end +$var wire 8 ~# sub5_out[1][2] [7:0] $end +$var int 32 !$ count [31:0] $end +$var int 32 "$ driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 n! P1 $end -$var wire 32 +# driven_from_bind [31:0] $end +$var real_parameter 64 c" P1 $end +$var wire 32 "$ driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 `! clk $end -$var wire 128 ,# in[0][0] [127:0] $end -$var wire 128 -# in[0][1] [127:0] $end -$var wire 128 .# in[0][2] [127:0] $end -$var wire 128 /# in[1][0] [127:0] $end -$var wire 128 0# in[1][1] [127:0] $end -$var wire 128 1# in[1][2] [127:0] $end -$var wire 8 2# out[0][0] [7:0] $end -$var wire 8 3# out[0][1] [7:0] $end -$var wire 8 4# out[0][2] [7:0] $end -$var wire 8 5# out[1][0] [7:0] $end -$var wire 8 6# out[1][1] [7:0] $end -$var wire 8 7# out[1][2] [7:0] $end -$var int 32 8# count [31:0] $end -$var wire 8 9# val0[0] [7:0] $end -$var wire 8 :# val0[1] [7:0] $end -$var wire 8 ;# val1[0] [7:0] $end -$var wire 8 <# val1[1] [7:0] $end -$var wire 8 =# val2[0] [7:0] $end -$var wire 8 ># val2[1] [7:0] $end -$var wire 8 ?# val3[0] [7:0] $end -$var wire 8 @# val3[1] [7:0] $end +$var wire 1 #$ clk $end +$var wire 128 $$ in[0][0] [127:0] $end +$var wire 128 %$ in[0][1] [127:0] $end +$var wire 128 &$ in[0][2] [127:0] $end +$var wire 128 '$ in[1][0] [127:0] $end +$var wire 128 ($ in[1][1] [127:0] $end +$var wire 128 )$ in[1][2] [127:0] $end +$var wire 8 *$ out[0][0] [7:0] $end +$var wire 8 +$ out[0][1] [7:0] $end +$var wire 8 ,$ out[0][2] [7:0] $end +$var wire 8 -$ out[1][0] [7:0] $end +$var wire 8 .$ out[1][1] [7:0] $end +$var wire 8 /$ out[1][2] [7:0] $end +$var int 32 0$ count [31:0] $end +$var wire 8 1$ val0[0] [7:0] $end +$var wire 8 2$ val0[1] [7:0] $end +$var wire 8 3$ val1[0] [7:0] $end +$var wire 8 4$ val1[1] [7:0] $end +$var wire 8 5$ val2[0] [7:0] $end +$var wire 8 6$ val2[1] [7:0] $end +$var wire 8 7$ val3[0] [7:0] $end +$var wire 8 8$ val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 A# out[0] [7:0] $end -$var wire 8 B# out[1] [7:0] $end +$var parameter 32 9$ P0 [31:0] $end +$var parameter 32 :$ P1 [31:0] $end +$var wire 8 ;$ out[0] [7:0] $end +$var wire 8 <$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 C# out[0] [7:0] $end -$var wire 8 D# out[1] [7:0] $end +$var parameter 32 9$ P0 [31:0] $end +$var parameter 32 :$ P1 [31:0] $end +$var wire 8 =$ out[0] [7:0] $end +$var wire 8 >$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 E# out[0] [7:0] $end -$var wire 8 F# out[1] [7:0] $end +$var parameter 32 9$ P0 [31:0] $end +$var parameter 32 :$ P1 [31:0] $end +$var wire 8 ?$ out[0] [7:0] $end +$var wire 8 @$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 =" P1 [31:0] $end -$var wire 8 G# out[0] [7:0] $end -$var wire 8 H# out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 I# i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 J# j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 K# exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 L# i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 M# j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 N# exp [7:0] $end -$upscope $end +$var parameter 32 9$ P0 [31:0] $end +$var parameter 32 A$ P1 [31:0] $end +$var wire 8 B$ out[0] [7:0] $end +$var wire 8 C$ out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end -$var parameter 32 m! P0 [31:0] $end -$var real_parameter 64 n! P1 $end -$var real_parameter 64 F" P3 $end -$var wire 1 `! clk $end -$var wire 8 z" in [7:0] $end -$var wire 8 {" out [7:0] $end -$var logic 8 {" ff [7:0] $end -$var logic 128 O# sub5_in[0][0] [127:0] $end -$var logic 128 P# sub5_in[0][1] [127:0] $end -$var logic 128 Q# sub5_in[0][2] [127:0] $end -$var logic 128 R# sub5_in[1][0] [127:0] $end -$var logic 128 S# sub5_in[1][1] [127:0] $end -$var logic 128 T# sub5_in[1][2] [127:0] $end -$var wire 8 U# sub5_out[0][0] [7:0] $end -$var wire 8 V# sub5_out[0][1] [7:0] $end -$var wire 8 W# sub5_out[0][2] [7:0] $end -$var wire 8 X# sub5_out[1][0] [7:0] $end -$var wire 8 Y# sub5_out[1][1] [7:0] $end -$var wire 8 Z# sub5_out[1][2] [7:0] $end -$var int 32 [# count [31:0] $end -$var int 32 \# driven_from_bind [31:0] $end +$var parameter 32 b" P0 [31:0] $end +$var real_parameter 64 c" P1 $end +$var real_parameter 64 7# P3 $end +$var wire 1 ! clk $end +$var wire 8 r# in [7:0] $end +$var wire 8 q# out [7:0] $end +$var logic 8 q# ff [7:0] $end +$var logic 128 D$ sub5_in[0][0] [127:0] $end +$var logic 128 E$ sub5_in[0][1] [127:0] $end +$var logic 128 F$ sub5_in[0][2] [127:0] $end +$var logic 128 G$ sub5_in[1][0] [127:0] $end +$var logic 128 H$ sub5_in[1][1] [127:0] $end +$var logic 128 I$ sub5_in[1][2] [127:0] $end +$var wire 8 J$ sub5_out[0][0] [7:0] $end +$var wire 8 K$ sub5_out[0][1] [7:0] $end +$var wire 8 L$ sub5_out[0][2] [7:0] $end +$var wire 8 M$ sub5_out[1][0] [7:0] $end +$var wire 8 N$ sub5_out[1][1] [7:0] $end +$var wire 8 O$ sub5_out[1][2] [7:0] $end +$var int 32 P$ count [31:0] $end +$var int 32 Q$ driven_from_bind [31:0] $end $scope module i_sub4_bound $end -$var real_parameter 64 n! P1 $end -$var wire 32 \# driven_from_bind [31:0] $end +$var real_parameter 64 c" P1 $end +$var wire 32 Q$ driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end -$var wire 1 `! clk $end -$var wire 128 ]# in[0][0] [127:0] $end -$var wire 128 ^# in[0][1] [127:0] $end -$var wire 128 _# in[0][2] [127:0] $end -$var wire 128 `# in[1][0] [127:0] $end -$var wire 128 a# in[1][1] [127:0] $end -$var wire 128 b# in[1][2] [127:0] $end -$var wire 8 c# out[0][0] [7:0] $end -$var wire 8 d# out[0][1] [7:0] $end -$var wire 8 e# out[0][2] [7:0] $end -$var wire 8 f# out[1][0] [7:0] $end -$var wire 8 g# out[1][1] [7:0] $end -$var wire 8 h# out[1][2] [7:0] $end -$var int 32 i# count [31:0] $end -$var wire 8 j# val0[0] [7:0] $end -$var wire 8 k# val0[1] [7:0] $end -$var wire 8 l# val1[0] [7:0] $end -$var wire 8 m# val1[1] [7:0] $end -$var wire 8 n# val2[0] [7:0] $end -$var wire 8 o# val2[1] [7:0] $end -$var wire 8 p# val3[0] [7:0] $end -$var wire 8 q# val3[1] [7:0] $end -$scope module i_sub0 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 r# out[0] [7:0] $end -$var wire 8 s# out[1] [7:0] $end -$upscope $end -$scope module i_sub1 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 t# out[0] [7:0] $end -$var wire 8 u# out[1] [7:0] $end -$upscope $end -$scope module i_sub2 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 6" P1 [31:0] $end -$var wire 8 v# out[0] [7:0] $end -$var wire 8 w# out[1] [7:0] $end -$upscope $end -$scope module i_sub3 $end -$var parameter 32 5" P0 [31:0] $end -$var parameter 32 =" P1 [31:0] $end -$var wire 8 x# out[0] [7:0] $end -$var wire 8 y# out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 z# i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 {# j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 |# exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 }# i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 ~# j [31:0] $end -$scope module unnamedblk3 $end -$var byte 8 !$ exp [7:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module top.t.i_sub3.i_sub4_0.i_sub5 $end -$var wire 1 "$ clk $end -$var wire 128 #$ in[0][0] [127:0] $end -$var wire 128 $$ in[0][1] [127:0] $end -$var wire 128 %$ in[0][2] [127:0] $end -$var wire 128 &$ in[1][0] [127:0] $end -$var wire 128 '$ in[1][1] [127:0] $end -$var wire 128 ($ in[1][2] [127:0] $end -$var wire 8 )$ out[0][0] [7:0] $end -$var wire 8 *$ out[0][1] [7:0] $end -$var wire 8 +$ out[0][2] [7:0] $end -$var wire 8 ,$ out[1][0] [7:0] $end -$var wire 8 -$ out[1][1] [7:0] $end -$var wire 8 .$ out[1][2] [7:0] $end -$scope module sub5 $end -$var wire 1 "$ clk $end -$var wire 128 /$ in[0][0] [127:0] $end -$var wire 128 0$ in[0][1] [127:0] $end -$var wire 128 1$ in[0][2] [127:0] $end -$var wire 128 2$ in[1][0] [127:0] $end -$var wire 128 3$ in[1][1] [127:0] $end -$var wire 128 4$ in[1][2] [127:0] $end -$var wire 8 5$ out[0][0] [7:0] $end -$var wire 8 6$ out[0][1] [7:0] $end -$var wire 8 7$ out[0][2] [7:0] $end -$var wire 8 8$ out[1][0] [7:0] $end -$var wire 8 9$ out[1][1] [7:0] $end -$var wire 8 :$ out[1][2] [7:0] $end -$var int 32 ;$ count [31:0] $end -$var wire 8 <$ val0[0] [7:0] $end -$var wire 8 =$ val0[1] [7:0] $end -$var wire 8 >$ val1[0] [7:0] $end -$var wire 8 ?$ val1[1] [7:0] $end -$var wire 8 @$ val2[0] [7:0] $end -$var wire 8 A$ val2[1] [7:0] $end -$var wire 8 B$ val3[0] [7:0] $end -$var wire 8 C$ val3[1] [7:0] $end -$scope module i_sub0 $end -$var parameter 32 D$ P0 [31:0] $end -$var parameter 32 E$ P1 [31:0] $end -$var wire 8 F$ out[0] [7:0] $end -$var wire 8 G$ out[1] [7:0] $end -$upscope $end -$scope module i_sub1 $end -$var parameter 32 D$ P0 [31:0] $end -$var parameter 32 E$ P1 [31:0] $end -$var wire 8 H$ out[0] [7:0] $end -$var wire 8 I$ out[1] [7:0] $end -$upscope $end -$scope module i_sub2 $end -$var parameter 32 D$ P0 [31:0] $end -$var parameter 32 E$ P1 [31:0] $end -$var wire 8 J$ out[0] [7:0] $end -$var wire 8 K$ out[1] [7:0] $end -$upscope $end -$scope module i_sub3 $end -$var parameter 32 D$ P0 [31:0] $end -$var parameter 32 L$ P1 [31:0] $end -$var wire 8 M$ out[0] [7:0] $end -$var wire 8 N$ out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 O$ i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 P$ j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 Q$ exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module top.t.i_sub3.i_sub4_1.i_sub5 $end $var wire 1 R$ clk $end $var wire 128 S$ in[0][0] [127:0] $end $var wire 128 T$ in[0][1] [127:0] $end @@ -864,203 +771,39 @@ $var wire 8 [$ out[0][2] [7:0] $end $var wire 8 \$ out[1][0] [7:0] $end $var wire 8 ]$ out[1][1] [7:0] $end $var wire 8 ^$ out[1][2] [7:0] $end -$scope module sub5 $end -$var wire 1 R$ clk $end -$var wire 128 _$ in[0][0] [127:0] $end -$var wire 128 `$ in[0][1] [127:0] $end -$var wire 128 a$ in[0][2] [127:0] $end -$var wire 128 b$ in[1][0] [127:0] $end -$var wire 128 c$ in[1][1] [127:0] $end -$var wire 128 d$ in[1][2] [127:0] $end -$var wire 8 e$ out[0][0] [7:0] $end -$var wire 8 f$ out[0][1] [7:0] $end -$var wire 8 g$ out[0][2] [7:0] $end -$var wire 8 h$ out[1][0] [7:0] $end -$var wire 8 i$ out[1][1] [7:0] $end -$var wire 8 j$ out[1][2] [7:0] $end -$var int 32 k$ count [31:0] $end -$var wire 8 l$ val0[0] [7:0] $end -$var wire 8 m$ val0[1] [7:0] $end -$var wire 8 n$ val1[0] [7:0] $end -$var wire 8 o$ val1[1] [7:0] $end -$var wire 8 p$ val2[0] [7:0] $end -$var wire 8 q$ val2[1] [7:0] $end -$var wire 8 r$ val3[0] [7:0] $end -$var wire 8 s$ val3[1] [7:0] $end +$var int 32 _$ count [31:0] $end +$var wire 8 `$ val0[0] [7:0] $end +$var wire 8 a$ val0[1] [7:0] $end +$var wire 8 b$ val1[0] [7:0] $end +$var wire 8 c$ val1[1] [7:0] $end +$var wire 8 d$ val2[0] [7:0] $end +$var wire 8 e$ val2[1] [7:0] $end +$var wire 8 f$ val3[0] [7:0] $end +$var wire 8 g$ val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 t$ P0 [31:0] $end -$var parameter 32 u$ P1 [31:0] $end -$var wire 8 v$ out[0] [7:0] $end -$var wire 8 w$ out[1] [7:0] $end +$var parameter 32 h$ P0 [31:0] $end +$var parameter 32 i$ P1 [31:0] $end +$var wire 8 j$ out[0] [7:0] $end +$var wire 8 k$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 t$ P0 [31:0] $end -$var parameter 32 u$ P1 [31:0] $end -$var wire 8 x$ out[0] [7:0] $end -$var wire 8 y$ out[1] [7:0] $end +$var parameter 32 h$ P0 [31:0] $end +$var parameter 32 i$ P1 [31:0] $end +$var wire 8 l$ out[0] [7:0] $end +$var wire 8 m$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 t$ P0 [31:0] $end -$var parameter 32 u$ P1 [31:0] $end -$var wire 8 z$ out[0] [7:0] $end -$var wire 8 {$ out[1] [7:0] $end +$var parameter 32 h$ P0 [31:0] $end +$var parameter 32 i$ P1 [31:0] $end +$var wire 8 n$ out[0] [7:0] $end +$var wire 8 o$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var parameter 32 t$ P0 [31:0] $end -$var parameter 32 |$ P1 [31:0] $end -$var wire 8 }$ out[0] [7:0] $end -$var wire 8 ~$ out[1] [7:0] $end +$var parameter 32 h$ P0 [31:0] $end +$var parameter 32 p$ P1 [31:0] $end +$var wire 8 q$ out[0] [7:0] $end +$var wire 8 r$ out[1] [7:0] $end $upscope $end -$scope module unnamedblk1 $end -$var int 32 !% i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 "% j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 #% exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module top.t.i_sub3_2.i_sub4_0.i_sub5 $end -$var wire 1 $% clk $end -$var wire 128 %% in[0][0] [127:0] $end -$var wire 128 &% in[0][1] [127:0] $end -$var wire 128 '% in[0][2] [127:0] $end -$var wire 128 (% in[1][0] [127:0] $end -$var wire 128 )% in[1][1] [127:0] $end -$var wire 128 *% in[1][2] [127:0] $end -$var wire 8 +% out[0][0] [7:0] $end -$var wire 8 ,% out[0][1] [7:0] $end -$var wire 8 -% out[0][2] [7:0] $end -$var wire 8 .% out[1][0] [7:0] $end -$var wire 8 /% out[1][1] [7:0] $end -$var wire 8 0% out[1][2] [7:0] $end -$scope module sub5 $end -$var wire 1 $% clk $end -$var wire 128 1% in[0][0] [127:0] $end -$var wire 128 2% in[0][1] [127:0] $end -$var wire 128 3% in[0][2] [127:0] $end -$var wire 128 4% in[1][0] [127:0] $end -$var wire 128 5% in[1][1] [127:0] $end -$var wire 128 6% in[1][2] [127:0] $end -$var wire 8 7% out[0][0] [7:0] $end -$var wire 8 8% out[0][1] [7:0] $end -$var wire 8 9% out[0][2] [7:0] $end -$var wire 8 :% out[1][0] [7:0] $end -$var wire 8 ;% out[1][1] [7:0] $end -$var wire 8 <% out[1][2] [7:0] $end -$var int 32 =% count [31:0] $end -$var wire 8 >% val0[0] [7:0] $end -$var wire 8 ?% val0[1] [7:0] $end -$var wire 8 @% val1[0] [7:0] $end -$var wire 8 A% val1[1] [7:0] $end -$var wire 8 B% val2[0] [7:0] $end -$var wire 8 C% val2[1] [7:0] $end -$var wire 8 D% val3[0] [7:0] $end -$var wire 8 E% val3[1] [7:0] $end -$scope module i_sub0 $end -$var parameter 32 F% P0 [31:0] $end -$var parameter 32 G% P1 [31:0] $end -$var wire 8 H% out[0] [7:0] $end -$var wire 8 I% out[1] [7:0] $end -$upscope $end -$scope module i_sub1 $end -$var parameter 32 F% P0 [31:0] $end -$var parameter 32 G% P1 [31:0] $end -$var wire 8 J% out[0] [7:0] $end -$var wire 8 K% out[1] [7:0] $end -$upscope $end -$scope module i_sub2 $end -$var parameter 32 F% P0 [31:0] $end -$var parameter 32 G% P1 [31:0] $end -$var wire 8 L% out[0] [7:0] $end -$var wire 8 M% out[1] [7:0] $end -$upscope $end -$scope module i_sub3 $end -$var parameter 32 F% P0 [31:0] $end -$var parameter 32 N% P1 [31:0] $end -$var wire 8 O% out[0] [7:0] $end -$var wire 8 P% out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 Q% i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 R% j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 S% exp [127:0] $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$upscope $end -$scope module top.t.i_sub3_2.i_sub4_1.i_sub5 $end -$var wire 1 T% clk $end -$var wire 128 U% in[0][0] [127:0] $end -$var wire 128 V% in[0][1] [127:0] $end -$var wire 128 W% in[0][2] [127:0] $end -$var wire 128 X% in[1][0] [127:0] $end -$var wire 128 Y% in[1][1] [127:0] $end -$var wire 128 Z% in[1][2] [127:0] $end -$var wire 8 [% out[0][0] [7:0] $end -$var wire 8 \% out[0][1] [7:0] $end -$var wire 8 ]% out[0][2] [7:0] $end -$var wire 8 ^% out[1][0] [7:0] $end -$var wire 8 _% out[1][1] [7:0] $end -$var wire 8 `% out[1][2] [7:0] $end -$scope module sub5 $end -$var wire 1 T% clk $end -$var wire 128 a% in[0][0] [127:0] $end -$var wire 128 b% in[0][1] [127:0] $end -$var wire 128 c% in[0][2] [127:0] $end -$var wire 128 d% in[1][0] [127:0] $end -$var wire 128 e% in[1][1] [127:0] $end -$var wire 128 f% in[1][2] [127:0] $end -$var wire 8 g% out[0][0] [7:0] $end -$var wire 8 h% out[0][1] [7:0] $end -$var wire 8 i% out[0][2] [7:0] $end -$var wire 8 j% out[1][0] [7:0] $end -$var wire 8 k% out[1][1] [7:0] $end -$var wire 8 l% out[1][2] [7:0] $end -$var int 32 m% count [31:0] $end -$var wire 8 n% val0[0] [7:0] $end -$var wire 8 o% val0[1] [7:0] $end -$var wire 8 p% val1[0] [7:0] $end -$var wire 8 q% val1[1] [7:0] $end -$var wire 8 r% val2[0] [7:0] $end -$var wire 8 s% val2[1] [7:0] $end -$var wire 8 t% val3[0] [7:0] $end -$var wire 8 u% val3[1] [7:0] $end -$scope module i_sub0 $end -$var parameter 32 v% P0 [31:0] $end -$var parameter 32 w% P1 [31:0] $end -$var wire 8 x% out[0] [7:0] $end -$var wire 8 y% out[1] [7:0] $end -$upscope $end -$scope module i_sub1 $end -$var parameter 32 v% P0 [31:0] $end -$var parameter 32 w% P1 [31:0] $end -$var wire 8 z% out[0] [7:0] $end -$var wire 8 {% out[1] [7:0] $end -$upscope $end -$scope module i_sub2 $end -$var parameter 32 v% P0 [31:0] $end -$var parameter 32 w% P1 [31:0] $end -$var wire 8 |% out[0] [7:0] $end -$var wire 8 }% out[1] [7:0] $end -$upscope $end -$scope module i_sub3 $end -$var parameter 32 v% P0 [31:0] $end -$var parameter 32 ~% P1 [31:0] $end -$var wire 8 !& out[0] [7:0] $end -$var wire 8 "& out[1] [7:0] $end -$upscope $end -$scope module unnamedblk1 $end -$var int 32 #& i [31:0] $end -$scope module unnamedblk2 $end -$var int 32 $& j [31:0] $end -$scope module unnamedblk3 $end -$var bit 128 %& exp [127:0] $end $upscope $end $upscope $end $upscope $end @@ -1069,137 +812,26 @@ $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 %& -b00000000000000000000000000000000 $& -b00000000000000000000000000000000 #& -b00000011 "& -b00000001 !& -b00000000000000000000000000000011 ~% -b00000010 }% -b00000001 |% -b00000010 {% -b00000001 z% -b00000010 y% -b00000001 x% -b00000000000000000000000000000010 w% -b00000000000000000000000000000001 v% -b00000011 u% -b00000001 t% -b00000010 s% -b00000001 r% -b00000010 q% -b00000001 p% -b00000010 o% -b00000001 n% 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N [31:0] $end + $var wire 32 g! WIDTH [31:0] $end + $var wire 1 c! clk $end + $var wire 8 >! in [7:0] $end + $var wire 8 ' out [7:0] $end + $var wire 8 * tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end - $var wire 32 !# N [31:0] $end - $var wire 32 ~" WIDTH [31:0] $end - $var wire 1 z" clk $end - $var wire 8 + in [7:0] $end - $var wire 8 ( out [7:0] $end - $var wire 8 ( tmp [7:0] $end + $var wire 32 h! N [31:0] $end + $var wire 32 g! WIDTH [31:0] $end + $var wire 1 c! clk $end + $var wire 8 * in [7:0] $end + $var wire 8 ' out [7:0] $end + $var wire 8 ' tmp [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_delay1 $end - $var wire 32 "# N [31:0] $end - $var wire 32 ~" WIDTH [31:0] $end - $var wire 1 z" clk $end - $var wire 8 ( in [7:0] $end - $var wire 8 ) out [7:0] $end - $var wire 8 , tmp [7:0] $end + $var wire 32 i! N [31:0] $end + $var wire 32 g! WIDTH [31:0] $end + $var wire 1 c! clk $end + $var wire 8 ' in [7:0] $end + $var wire 8 ( out [7:0] $end + $var wire 8 + tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end - $var wire 32 }" N [31:0] $end - $var wire 32 ~" WIDTH [31:0] $end - $var wire 1 z" clk $end - $var wire 8 , in [7:0] $end - $var wire 8 ) out [7:0] $end - $var wire 8 - tmp [7:0] $end + $var wire 32 f! N [31:0] $end + $var wire 32 g! WIDTH [31:0] $end + $var wire 1 c! clk $end + $var wire 8 + in [7:0] $end + $var wire 8 ( out [7:0] $end + $var wire 8 , tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end - $var wire 32 !# N [31:0] $end - $var wire 32 ~" WIDTH [31:0] $end - $var wire 1 z" clk $end - $var wire 8 - in [7:0] $end - $var wire 8 ) out [7:0] $end - $var wire 8 ) tmp [7:0] $end + $var wire 32 h! N [31:0] $end + $var wire 32 g! WIDTH [31:0] $end + $var wire 1 c! clk $end + $var wire 8 , in [7:0] $end + $var wire 8 ( out [7:0] $end + $var wire 8 ( tmp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub0 $end - $var wire 1 z" clk $end - $var wire 8 C! in [7:0] $end - $var wire 8 G" out [7:0] $end + $var wire 1 c! clk $end + $var wire 8 >! in [7:0] $end + $var wire 8 H! out [7:0] $end $scope module i_sub0 $end - $var wire 1 z" clk $end - $var wire 8 C! in [7:0] $end - $var wire 8 G" out [7:0] $end + $var wire 1 y! clk $end + $var wire 8 z! in [7:0] $end + $var wire 8 {! out [7:0] $end + $var wire 8 |! ff [7:0] $end $upscope $end $upscope $end $scope module i_sub1 $end - $var wire 1 z" clk $end - $var wire 8 G" in [11:4] $end - $var wire 8 H" out [7:0] $end + $var wire 1 }! clk $end + $var wire 8 ~! in [11:4] $end + $var wire 8 !" out [7:0] $end + $var wire 8 "" ff [7:0] $end + $var wire 2 #" enum_v [1:0] $end $upscope $end $scope module i_sub2 $end - $var wire 1 z" clk $end - $var wire 8 H" in [7:0] $end - $var wire 8 I" out [7:0] $end + $var wire 1 ^% clk $end + $var wire 8 _% in [7:0] $end + $var wire 8 `% out [7:0] $end + $var wire 8 h" ff [7:0] $end + $var wire 2 i" alt_enum_v [1:0] $end + $scope module i_sub3 $end + $var wire 8 h" in_wire [7:0] $end + $var wire 8 j" out_1 [7:0] $end + $var wire 8 k" out_2 [7:0] $end + $scope module i_sub3 $end + $var wire 8 a% P0 [7:0] $end + $var wire 32 b% UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 c% UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 d% UNUSED [15:0] $end + $var wire 2 e% ENUM [1:0] $end + $var wire 1 ^% clk $end + $var wire 8 h" in [7:0] $end + $var wire 8 j" out [7:0] $end + $var wire 1 l" ff[0] $end + $var wire 1 m" ff[1] $end + $var wire 1 n" ff[2] $end + $var wire 1 o" ff[3] $end + $var wire 1 p" ff[4] $end + $var wire 1 q" ff[5] $end + $var wire 1 r" ff[6] $end + $var wire 1 s" ff[7] $end + $var wire 8 j" out4 [7:0] $end + $var wire 8 t" out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 32 f% P0 [31:0] $end + $var real 64 g% P1 $end + $var real 64 i% P3 $end + $var wire 1 ^% clk $end + $var wire 8 u" in [7:0] $end + $var wire 8 j" out [7:0] $end + $var wire 8 j" ff [7:0] $end + $var wire 128 v" sub5_in[0][0] [127:0] $end + $var wire 128 z" sub5_in[0][1] [127:0] $end + $var wire 128 ~" sub5_in[0][2] [127:0] $end + $var wire 128 $# sub5_in[1][0] [127:0] $end + $var wire 128 (# sub5_in[1][1] [127:0] $end + $var wire 128 ,# sub5_in[1][2] [127:0] $end + $var wire 8 0# sub5_out[0][0] [7:0] $end + $var wire 8 1# sub5_out[0][1] [7:0] $end + $var wire 8 2# sub5_out[0][2] [7:0] $end + $var wire 8 3# sub5_out[1][0] [7:0] $end + $var wire 8 4# sub5_out[1][1] [7:0] $end + $var wire 8 5# sub5_out[1][2] [7:0] $end + $var wire 32 6# count [31:0] $end + $var wire 32 $" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 g% P1 $end + $var wire 32 $" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 ^% clk $end + $var wire 128 7# in[0][0] [127:0] $end + $var wire 128 ;# in[0][1] [127:0] $end + $var wire 128 ?# in[0][2] [127:0] $end + $var wire 128 C# in[1][0] [127:0] $end + $var wire 128 G# in[1][1] [127:0] $end + $var wire 128 K# in[1][2] [127:0] $end + $var wire 8 O# out[0][0] [7:0] $end + $var wire 8 P# out[0][1] [7:0] $end + $var wire 8 Q# out[0][2] [7:0] $end + $var wire 8 R# out[1][0] [7:0] $end + $var wire 8 S# out[1][1] [7:0] $end + $var wire 8 T# out[1][2] [7:0] $end + $var wire 32 U# count [31:0] $end + $var wire 8 %" val0[0] [7:0] $end + $var wire 8 &" val0[1] [7:0] $end + $var wire 8 '" val1[0] [7:0] $end + $var wire 8 (" val1[1] [7:0] $end + $var wire 8 )" val2[0] [7:0] $end + $var wire 8 *" val2[1] [7:0] $end + $var wire 8 +" val3[0] [7:0] $end + $var wire 8 ," val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 -" out[0] [7:0] $end + $var wire 8 ." out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 /" out[0] [7:0] $end + $var wire 8 0" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 1" out[0] [7:0] $end + $var wire 8 2" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 m% P1 [31:0] $end + $var wire 8 3" out[0] [7:0] $end + $var wire 8 4" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 32 f% P0 [31:0] $end + $var real 64 g% P1 $end + $var real 64 n% P3 $end + $var wire 1 ^% clk $end + $var wire 8 u" in [7:0] $end + $var wire 8 t" out [7:0] $end + $var wire 8 t" ff [7:0] $end + $var wire 128 V# sub5_in[0][0] [127:0] $end + $var wire 128 Z# sub5_in[0][1] [127:0] $end + $var wire 128 ^# sub5_in[0][2] [127:0] $end + $var wire 128 b# sub5_in[1][0] [127:0] $end + $var wire 128 f# sub5_in[1][1] [127:0] $end + $var wire 128 j# sub5_in[1][2] [127:0] $end + $var wire 8 n# sub5_out[0][0] [7:0] $end + $var wire 8 o# sub5_out[0][1] [7:0] $end + $var wire 8 p# sub5_out[0][2] [7:0] $end + $var wire 8 q# sub5_out[1][0] [7:0] $end + $var wire 8 r# sub5_out[1][1] [7:0] $end + $var wire 8 s# sub5_out[1][2] [7:0] $end + $var wire 32 t# count [31:0] $end + $var wire 32 5" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 g% P1 $end + $var wire 32 5" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 ^% clk $end + $var wire 128 u# in[0][0] [127:0] $end + $var wire 128 y# in[0][1] [127:0] $end + $var wire 128 }# in[0][2] [127:0] $end + $var wire 128 #$ in[1][0] [127:0] $end + $var wire 128 '$ in[1][1] [127:0] $end + $var wire 128 +$ in[1][2] [127:0] $end + $var wire 8 /$ out[0][0] [7:0] $end + $var wire 8 0$ out[0][1] [7:0] $end + $var wire 8 1$ out[0][2] [7:0] $end + $var wire 8 2$ out[1][0] [7:0] $end + $var wire 8 3$ out[1][1] [7:0] $end + $var wire 8 4$ out[1][2] [7:0] $end + $var wire 32 5$ count [31:0] $end + $var wire 8 6" val0[0] [7:0] $end + $var wire 8 7" val0[1] [7:0] $end + $var wire 8 8" val1[0] [7:0] $end + $var wire 8 9" val1[1] [7:0] $end + $var wire 8 :" val2[0] [7:0] $end + $var wire 8 ;" val2[1] [7:0] $end + $var wire 8 <" val3[0] [7:0] $end + $var wire 8 =" val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 >" out[0] [7:0] $end + $var wire 8 ?" out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 @" out[0] [7:0] $end + $var wire 8 A" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 B" out[0] [7:0] $end + $var wire 8 C" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 m% P1 [31:0] $end + $var wire 8 D" out[0] [7:0] $end + $var wire 8 E" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub3_2 $end + $var wire 8 a% P0 [7:0] $end + $var wire 32 p% UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 q% UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 d% UNUSED [15:0] $end + $var wire 2 e% ENUM [1:0] $end + $var wire 1 ^% clk $end + $var wire 8 h" in [7:0] $end + $var wire 8 k" out [7:0] $end + $var wire 1 6$ ff[0] $end + $var wire 1 7$ ff[1] $end + $var wire 1 8$ ff[2] $end + $var wire 1 9$ ff[3] $end + $var wire 1 :$ ff[4] $end + $var wire 1 ;$ ff[5] $end + $var wire 1 <$ ff[6] $end + $var wire 1 =$ ff[7] $end + $var wire 8 k" out4 [7:0] $end + $var wire 8 >$ out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 32 f% P0 [31:0] $end + $var real 64 g% P1 $end + $var real 64 i% P3 $end + $var wire 1 ^% clk $end + $var wire 8 ?$ in [7:0] $end + $var wire 8 k" out [7:0] $end + $var wire 8 k" ff [7:0] $end + $var wire 128 @$ sub5_in[0][0] [127:0] $end + $var wire 128 D$ sub5_in[0][1] [127:0] $end + $var wire 128 H$ sub5_in[0][2] [127:0] $end + $var wire 128 L$ sub5_in[1][0] [127:0] $end + $var wire 128 P$ sub5_in[1][1] [127:0] $end + $var wire 128 T$ sub5_in[1][2] [127:0] $end + $var wire 8 X$ sub5_out[0][0] [7:0] $end + $var wire 8 Y$ sub5_out[0][1] [7:0] $end + $var wire 8 Z$ sub5_out[0][2] [7:0] $end + $var wire 8 [$ sub5_out[1][0] [7:0] $end + $var wire 8 \$ sub5_out[1][1] [7:0] $end + $var wire 8 ]$ sub5_out[1][2] [7:0] $end + $var wire 32 ^$ count [31:0] $end + $var wire 32 F" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 g% P1 $end + $var wire 32 F" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 ^% clk $end + $var wire 128 _$ in[0][0] [127:0] $end + $var wire 128 c$ in[0][1] [127:0] $end + $var wire 128 g$ in[0][2] [127:0] $end + $var wire 128 k$ in[1][0] [127:0] $end + $var wire 128 o$ in[1][1] [127:0] $end + $var wire 128 s$ in[1][2] [127:0] $end + $var wire 8 w$ out[0][0] [7:0] $end + $var wire 8 x$ out[0][1] [7:0] $end + $var wire 8 y$ out[0][2] [7:0] $end + $var wire 8 z$ out[1][0] [7:0] $end + $var wire 8 {$ out[1][1] [7:0] $end + $var wire 8 |$ out[1][2] [7:0] $end + $var wire 32 }$ count [31:0] $end + $var wire 8 G" val0[0] [7:0] $end + $var wire 8 H" val0[1] [7:0] $end + $var wire 8 I" val1[0] [7:0] $end + $var wire 8 J" val1[1] [7:0] $end + $var wire 8 K" val2[0] [7:0] $end + $var wire 8 L" val2[1] [7:0] $end + $var wire 8 M" val3[0] [7:0] $end + $var wire 8 N" val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 O" out[0] [7:0] $end + $var wire 8 P" out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 Q" out[0] [7:0] $end + $var wire 8 R" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 S" out[0] [7:0] $end + $var wire 8 T" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 m% P1 [31:0] $end + $var wire 8 U" out[0] [7:0] $end + $var wire 8 V" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 32 f% P0 [31:0] $end + $var real 64 g% P1 $end + $var real 64 n% P3 $end + $var wire 1 ^% clk $end + $var wire 8 ?$ in [7:0] $end + $var wire 8 >$ out [7:0] $end + $var wire 8 >$ ff [7:0] $end + $var wire 128 ~$ sub5_in[0][0] [127:0] $end + $var wire 128 $% sub5_in[0][1] [127:0] $end + $var wire 128 (% sub5_in[0][2] [127:0] $end + $var wire 128 ,% sub5_in[1][0] [127:0] $end + $var wire 128 0% sub5_in[1][1] [127:0] $end + $var wire 128 4% sub5_in[1][2] [127:0] $end + $var wire 8 8% sub5_out[0][0] [7:0] $end + $var wire 8 9% sub5_out[0][1] [7:0] $end + $var wire 8 :% sub5_out[0][2] [7:0] $end + $var wire 8 ;% sub5_out[1][0] [7:0] $end + $var wire 8 <% sub5_out[1][1] [7:0] $end + $var wire 8 =% sub5_out[1][2] [7:0] $end + $var wire 32 >% count [31:0] $end + $var wire 32 W" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 g% P1 $end + $var wire 32 W" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 ^% clk $end + $var wire 128 ?% in[0][0] [127:0] $end + $var wire 128 C% in[0][1] [127:0] $end + $var wire 128 G% in[0][2] [127:0] $end + $var wire 128 K% in[1][0] [127:0] $end + $var wire 128 O% in[1][1] [127:0] $end + $var wire 128 S% in[1][2] [127:0] $end + $var wire 8 W% out[0][0] [7:0] $end + $var wire 8 X% out[0][1] [7:0] $end + $var wire 8 Y% out[0][2] [7:0] $end + $var wire 8 Z% out[1][0] [7:0] $end + $var wire 8 [% out[1][1] [7:0] $end + $var wire 8 \% out[1][2] [7:0] $end + $var wire 32 ]% count [31:0] $end + $var wire 8 X" val0[0] [7:0] $end + $var wire 8 Y" val0[1] [7:0] $end + $var wire 8 Z" val1[0] [7:0] $end + $var wire 8 [" val1[1] [7:0] $end + $var wire 8 \" val2[0] [7:0] $end + $var wire 8 ]" val2[1] [7:0] $end + $var wire 8 ^" val3[0] [7:0] $end + $var wire 8 _" val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 `" out[0] [7:0] $end + $var wire 8 a" out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 b" out[0] [7:0] $end + $var wire 8 c" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 l% P1 [31:0] $end + $var wire 8 d" out[0] [7:0] $end + $var wire 8 e" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 k% P0 [31:0] $end + $var wire 32 m% P1 [31:0] $end + $var wire 8 f" out[0] [7:0] $end + $var wire 8 g" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module in $end + $var wire 1 ^% clk $end + $var wire 8 h" data [7:0] $end + $upscope $end + $scope module out $end + $var wire 1 ^% clk $end + $var wire 8 j" data [7:0] $end + $upscope $end + $upscope $end + $scope module in_ifs $end + $var wire 1 ^% clk $end + $var wire 8 h" data [7:0] $end + $upscope $end + $scope module out_ifs $end + $var wire 1 ^% clk $end + $var wire 8 j" data [7:0] $end + $upscope $end $upscope $end $scope module i_sub3 $end - $var wire 8 ## P0 [7:0] $end - $var wire 32 $# UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 %# UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 &# UNUSED [15:0] $end - $var wire 2 '# ENUM [1:0] $end - $var wire 1 z" clk $end - $var wire 8 I" in [7:0] $end - $var wire 8 C! out [7:0] $end - $var wire 8 D! ff [7:0] $end - $var wire 8 C! out4 [7:0] $end - $var wire 8 . out4_2 [7:0] $end + $var wire 8 j! P0 [7:0] $end + $var wire 32 k! UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 l! UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 m! UNUSED [15:0] $end + $var wire 2 n! ENUM [1:0] $end + $var wire 1 c! clk $end + $var wire 8 J! in [7:0] $end + $var wire 8 >! out [7:0] $end + $var wire 1 ?! ff[0] $end + $var wire 1 @! ff[1] $end + $var wire 1 A! ff[2] $end + $var wire 1 B! ff[3] $end + $var wire 1 C! ff[4] $end + $var wire 1 D! ff[5] $end + $var wire 1 E! ff[6] $end + $var wire 1 F! ff[7] $end + $var wire 8 >! out4 [7:0] $end + $var wire 8 - out4_2 [7:0] $end $scope module i_sub4_0 $end - $var wire 32 (# P0 [31:0] $end - $var real 64 )# P1 $end - $var real 64 +# P3 $end - $var wire 1 z" clk $end - $var wire 8 D! in [7:0] $end - $var wire 8 C! out [7:0] $end - $var wire 8 C! ff [7:0] $end - $var wire 128 / sub5_in[0][0] [127:0] $end - $var wire 128 3 sub5_in[0][1] [127:0] $end - $var wire 128 7 sub5_in[0][2] [127:0] $end - $var wire 128 ; sub5_in[1][0] [127:0] $end - $var wire 128 ? sub5_in[1][1] [127:0] $end - $var wire 128 C sub5_in[1][2] [127:0] $end - $var wire 8 J" sub5_out[0][0] [7:0] $end - $var wire 8 K" sub5_out[0][1] [7:0] $end - $var wire 8 L" sub5_out[0][2] [7:0] $end - $var wire 8 M" sub5_out[1][0] [7:0] $end - $var wire 8 N" sub5_out[1][1] [7:0] $end - $var wire 8 O" sub5_out[1][2] [7:0] $end - $var wire 32 G count [31:0] $end - $var wire 32 # driven_from_bind [31:0] $end + $var wire 32 o! P0 [31:0] $end + $var real 64 p! P1 $end + $var real 64 r! P3 $end + $var wire 1 c! clk $end + $var wire 8 G! in [7:0] $end + $var wire 8 >! out [7:0] $end + $var wire 8 >! ff [7:0] $end + $var wire 128 . sub5_in[0][0] [127:0] $end + $var wire 128 2 sub5_in[0][1] [127:0] $end + $var wire 128 6 sub5_in[0][2] [127:0] $end + $var wire 128 : sub5_in[1][0] [127:0] $end + $var wire 128 > sub5_in[1][1] [127:0] $end + $var wire 128 B sub5_in[1][2] [127:0] $end + $var wire 8 K! sub5_out[0][0] [7:0] $end + $var wire 8 L! sub5_out[0][1] [7:0] $end + $var wire 8 M! sub5_out[0][2] [7:0] $end + $var wire 8 N! sub5_out[1][0] [7:0] $end + $var wire 8 O! sub5_out[1][1] [7:0] $end + $var wire 8 P! sub5_out[1][2] [7:0] $end + $var wire 32 F count [31:0] $end + $var wire 32 " driven_from_bind [31:0] $end $scope module i_sub4_bound $end - $var real 64 )# P1 $end - $var wire 32 # driven_from_bind [31:0] $end + $var real 64 p! P1 $end + $var wire 32 " driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end - $var wire 1 z" clk $end - $var wire 128 E! in[0][0] [127:0] $end - $var wire 128 I! in[0][1] [127:0] $end - $var wire 128 M! in[0][2] [127:0] $end - $var wire 128 Q! in[1][0] [127:0] $end - $var wire 128 U! in[1][1] [127:0] $end - $var wire 128 Y! in[1][2] [127:0] $end - $var wire 8 P" out[0][0] [7:0] $end - $var wire 8 Q" out[0][1] [7:0] $end - $var wire 8 R" out[0][2] [7:0] $end - $var wire 8 S" out[1][0] [7:0] $end - $var wire 8 T" out[1][1] [7:0] $end - $var wire 8 U" out[1][2] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 H i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 I j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 J exp [7:0] $end - $upscope $end + $var wire 1 C& clk $end + $var wire 128 $& in[0][0] [127:0] $end + $var wire 128 (& in[0][1] [127:0] $end + $var wire 128 ,& in[0][2] [127:0] $end + $var wire 128 0& in[1][0] [127:0] $end + $var wire 128 4& in[1][1] [127:0] $end + $var wire 128 8& in[1][2] [127:0] $end + $var wire 8 <& out[0][0] [7:0] $end + $var wire 8 =& out[0][1] [7:0] $end + $var wire 8 >& out[0][2] [7:0] $end + $var wire 8 ?& out[1][0] [7:0] $end + $var wire 8 @& out[1][1] [7:0] $end + $var wire 8 A& out[1][2] [7:0] $end + $var wire 32 B& count [31:0] $end + $var wire 8 r% val0[0] [7:0] $end + $var wire 8 s% val0[1] [7:0] $end + $var wire 8 t% val1[0] [7:0] $end + $var wire 8 u% val1[1] [7:0] $end + $var wire 8 v% val2[0] [7:0] $end + $var wire 8 w% val2[1] [7:0] $end + $var wire 8 x% val3[0] [7:0] $end + $var wire 8 y% val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 D& P0 [31:0] $end + $var wire 32 E& P1 [31:0] $end + $var wire 8 z% out[0] [7:0] $end + $var wire 8 {% out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 D& P0 [31:0] $end + $var wire 32 E& P1 [31:0] $end + $var wire 8 |% out[0] [7:0] $end + $var wire 8 }% out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 D& P0 [31:0] $end + $var wire 32 E& P1 [31:0] $end + $var wire 8 ~% out[0] [7:0] $end + $var wire 8 !& out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 D& P0 [31:0] $end + $var wire 32 F& P1 [31:0] $end + $var wire 8 "& out[0] [7:0] $end + $var wire 8 #& out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end - $var wire 32 (# P0 [31:0] $end - $var real 64 )# P1 $end - $var real 64 -# P3 $end - $var wire 1 z" clk $end - $var wire 8 D! in [7:0] $end - $var wire 8 . out [7:0] $end - $var wire 8 . ff [7:0] $end - $var wire 128 K sub5_in[0][0] [127:0] $end - $var wire 128 O sub5_in[0][1] [127:0] $end - $var wire 128 S sub5_in[0][2] [127:0] $end - $var wire 128 W sub5_in[1][0] [127:0] $end - $var wire 128 [ sub5_in[1][1] [127:0] $end - $var wire 128 _ sub5_in[1][2] [127:0] $end - $var wire 8 V" sub5_out[0][0] [7:0] $end - $var wire 8 W" sub5_out[0][1] [7:0] $end - $var wire 8 X" sub5_out[0][2] [7:0] $end - $var wire 8 Y" sub5_out[1][0] [7:0] $end - $var wire 8 Z" sub5_out[1][1] [7:0] $end - $var wire 8 [" sub5_out[1][2] [7:0] $end - $var wire 32 c count [31:0] $end - $var wire 32 $ driven_from_bind [31:0] $end + $var wire 32 o! P0 [31:0] $end + $var real 64 p! P1 $end + $var real 64 t! P3 $end + $var wire 1 c! clk $end + $var wire 8 G! in [7:0] $end + $var wire 8 - out [7:0] $end + $var wire 8 - ff [7:0] $end + $var wire 128 G sub5_in[0][0] [127:0] $end + $var wire 128 K sub5_in[0][1] [127:0] $end + $var wire 128 O sub5_in[0][2] [127:0] $end + $var wire 128 S sub5_in[1][0] [127:0] $end + $var wire 128 W sub5_in[1][1] [127:0] $end + $var wire 128 [ sub5_in[1][2] [127:0] $end + $var wire 8 Q! sub5_out[0][0] [7:0] $end + $var wire 8 R! sub5_out[0][1] [7:0] $end + $var wire 8 S! sub5_out[0][2] [7:0] $end + $var wire 8 T! sub5_out[1][0] [7:0] $end + $var wire 8 U! sub5_out[1][1] [7:0] $end + $var wire 8 V! sub5_out[1][2] [7:0] $end + $var wire 32 _ count [31:0] $end + $var wire 32 # driven_from_bind [31:0] $end $scope module i_sub4_bound $end - $var real 64 )# P1 $end - $var wire 32 $ driven_from_bind [31:0] $end + $var real 64 p! P1 $end + $var wire 32 # driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end - $var wire 1 z" clk $end - $var wire 128 ]! in[0][0] [127:0] $end - $var wire 128 a! in[0][1] [127:0] $end - $var wire 128 e! in[0][2] [127:0] $end - $var wire 128 i! in[1][0] [127:0] $end - $var wire 128 m! in[1][1] [127:0] $end - $var wire 128 q! in[1][2] [127:0] $end - $var wire 8 \" out[0][0] [7:0] $end - $var wire 8 ]" out[0][1] [7:0] $end - $var wire 8 ^" out[0][2] [7:0] $end - $var wire 8 _" out[1][0] [7:0] $end - $var wire 8 `" out[1][1] [7:0] $end - $var wire 8 a" out[1][2] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 d i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 e j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 f exp [7:0] $end - $upscope $end + $var wire 1 v& clk $end + $var wire 128 W& in[0][0] [127:0] $end + $var wire 128 [& in[0][1] [127:0] $end + $var wire 128 _& in[0][2] [127:0] $end + $var wire 128 c& in[1][0] [127:0] $end + $var wire 128 g& in[1][1] [127:0] $end + $var wire 128 k& in[1][2] [127:0] $end + $var wire 8 o& out[0][0] [7:0] $end + $var wire 8 p& out[0][1] [7:0] $end + $var wire 8 q& out[0][2] [7:0] $end + $var wire 8 r& out[1][0] [7:0] $end + $var wire 8 s& out[1][1] [7:0] $end + $var wire 8 t& out[1][2] [7:0] $end + $var wire 32 u& count [31:0] $end + $var wire 8 G& val0[0] [7:0] $end + $var wire 8 H& val0[1] [7:0] $end + $var wire 8 I& val1[0] [7:0] $end + $var wire 8 J& val1[1] [7:0] $end + $var wire 8 K& val2[0] [7:0] $end + $var wire 8 L& val2[1] [7:0] $end + $var wire 8 M& val3[0] [7:0] $end + $var wire 8 N& val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 w& P0 [31:0] $end + $var wire 32 x& P1 [31:0] $end + $var wire 8 O& out[0] [7:0] $end + $var wire 8 P& out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 w& P0 [31:0] $end + $var wire 32 x& P1 [31:0] $end + $var wire 8 Q& out[0] [7:0] $end + $var wire 8 R& out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 w& P0 [31:0] $end + $var wire 32 x& P1 [31:0] $end + $var wire 8 S& out[0] [7:0] $end + $var wire 8 T& out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 w& P0 [31:0] $end + $var wire 32 y& P1 [31:0] $end + $var wire 8 U& out[0] [7:0] $end + $var wire 8 V& out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module i_sub3_2 $end - $var wire 8 ## P0 [7:0] $end - $var wire 32 /# UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 0# UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 &# UNUSED [15:0] $end - $var wire 2 '# ENUM [1:0] $end - $var wire 1 z" clk $end - $var wire 8 I" in [7:0] $end - $var wire 8 ' out [7:0] $end - $var wire 8 g ff [7:0] $end - $var wire 8 ' out4 [7:0] $end + $var wire 8 j! P0 [7:0] $end + $var wire 32 v! UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 w! UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 m! UNUSED [15:0] $end + $var wire 2 n! ENUM [1:0] $end + $var wire 1 c! clk $end + $var wire 8 J! in [7:0] $end + $var wire 8 & out [7:0] $end + $var wire 1 ` ff[0] $end + $var wire 1 a ff[1] $end + $var wire 1 b ff[2] $end + $var wire 1 c ff[3] $end + $var wire 1 d ff[4] $end + $var wire 1 e ff[5] $end + $var wire 1 f ff[6] $end + $var wire 1 g ff[7] $end + $var wire 8 & out4 [7:0] $end $var wire 8 h out4_2 [7:0] $end $scope module i_sub4_0 $end - $var wire 32 (# P0 [31:0] $end - $var real 64 )# P1 $end - $var real 64 +# P3 $end - $var wire 1 z" clk $end - $var wire 8 g in [7:0] $end - $var wire 8 ' out [7:0] $end - $var wire 8 ' ff [7:0] $end - $var wire 128 i sub5_in[0][0] [127:0] $end - $var wire 128 m sub5_in[0][1] [127:0] $end - $var wire 128 q sub5_in[0][2] [127:0] $end - $var wire 128 u sub5_in[1][0] [127:0] $end - $var wire 128 y sub5_in[1][1] [127:0] $end - $var wire 128 } sub5_in[1][2] [127:0] $end - $var wire 8 b" sub5_out[0][0] [7:0] $end - $var wire 8 c" sub5_out[0][1] [7:0] $end - $var wire 8 d" sub5_out[0][2] [7:0] $end - $var wire 8 e" sub5_out[1][0] [7:0] $end - $var wire 8 f" sub5_out[1][1] [7:0] $end - $var wire 8 g" sub5_out[1][2] [7:0] $end - $var wire 32 #! count [31:0] $end - $var wire 32 % driven_from_bind [31:0] $end + $var wire 32 o! P0 [31:0] $end + $var real 64 p! P1 $end + $var real 64 r! P3 $end + $var wire 1 c! clk $end + $var wire 8 i in [7:0] $end + $var wire 8 & out [7:0] $end + $var wire 8 & ff [7:0] $end + $var wire 128 j sub5_in[0][0] [127:0] $end + $var wire 128 n sub5_in[0][1] [127:0] $end + $var wire 128 r sub5_in[0][2] [127:0] $end + $var wire 128 v sub5_in[1][0] [127:0] $end + $var wire 128 z sub5_in[1][1] [127:0] $end + $var wire 128 ~ sub5_in[1][2] [127:0] $end + $var wire 8 W! sub5_out[0][0] [7:0] $end + $var wire 8 X! sub5_out[0][1] [7:0] $end + $var wire 8 Y! sub5_out[0][2] [7:0] $end + $var wire 8 Z! sub5_out[1][0] [7:0] $end + $var wire 8 [! sub5_out[1][1] [7:0] $end + $var wire 8 \! sub5_out[1][2] [7:0] $end + $var wire 32 $! count [31:0] $end + $var wire 32 $ driven_from_bind [31:0] $end $scope module i_sub4_bound $end - $var real 64 )# P1 $end - $var wire 32 % driven_from_bind [31:0] $end + $var real 64 p! P1 $end + $var wire 32 $ driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end - $var wire 1 z" clk $end - $var wire 128 u! in[0][0] [127:0] $end - $var wire 128 y! in[0][1] [127:0] $end - $var wire 128 }! in[0][2] [127:0] $end - $var wire 128 #" in[1][0] [127:0] $end - $var wire 128 '" in[1][1] [127:0] $end - $var wire 128 +" in[1][2] [127:0] $end - $var wire 8 h" out[0][0] [7:0] $end - $var wire 8 i" out[0][1] [7:0] $end - $var wire 8 j" out[0][2] [7:0] $end - $var wire 8 k" out[1][0] [7:0] $end - $var wire 8 l" out[1][1] [7:0] $end - $var wire 8 m" out[1][2] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 $! i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 %! j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 &! exp [7:0] $end - $upscope $end + $var wire 1 K' clk $end + $var wire 128 ,' in[0][0] [127:0] $end + $var wire 128 0' in[0][1] [127:0] $end + $var wire 128 4' in[0][2] [127:0] $end + $var wire 128 8' in[1][0] [127:0] $end + $var wire 128 <' in[1][1] [127:0] $end + $var wire 128 @' in[1][2] [127:0] $end + $var wire 8 D' out[0][0] [7:0] $end + $var wire 8 E' out[0][1] [7:0] $end + $var wire 8 F' out[0][2] [7:0] $end + $var wire 8 G' out[1][0] [7:0] $end + $var wire 8 H' out[1][1] [7:0] $end + $var wire 8 I' out[1][2] [7:0] $end + $var wire 32 J' count [31:0] $end + $var wire 8 z& val0[0] [7:0] $end + $var wire 8 {& val0[1] [7:0] $end + $var wire 8 |& val1[0] [7:0] $end + $var wire 8 }& val1[1] [7:0] $end + $var wire 8 ~& val2[0] [7:0] $end + $var wire 8 !' val2[1] [7:0] $end + $var wire 8 "' val3[0] [7:0] $end + $var wire 8 #' val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 L' P0 [31:0] $end + $var wire 32 M' P1 [31:0] $end + $var wire 8 $' out[0] [7:0] $end + $var wire 8 %' out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 L' P0 [31:0] $end + $var wire 32 M' P1 [31:0] $end + $var wire 8 &' out[0] [7:0] $end + $var wire 8 '' out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 L' P0 [31:0] $end + $var wire 32 M' P1 [31:0] $end + $var wire 8 (' out[0] [7:0] $end + $var wire 8 )' out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 L' P0 [31:0] $end + $var wire 32 N' P1 [31:0] $end + $var wire 8 *' out[0] [7:0] $end + $var wire 8 +' out[1] [7:0] $end $upscope $end $upscope $end $upscope $end $scope module i_sub4_1 $end - $var wire 32 (# P0 [31:0] $end - $var real 64 )# P1 $end - $var real 64 -# P3 $end - $var wire 1 z" clk $end - $var wire 8 g in [7:0] $end + $var wire 32 o! P0 [31:0] $end + $var real 64 p! P1 $end + $var real 64 t! P3 $end + $var wire 1 c! clk $end + $var wire 8 i in [7:0] $end $var wire 8 h out [7:0] $end $var wire 8 h ff [7:0] $end - $var wire 128 '! sub5_in[0][0] [127:0] $end - $var wire 128 +! sub5_in[0][1] [127:0] $end - $var wire 128 /! sub5_in[0][2] [127:0] $end - $var wire 128 3! sub5_in[1][0] [127:0] $end - $var wire 128 7! sub5_in[1][1] [127:0] $end - $var wire 128 ;! sub5_in[1][2] [127:0] $end - $var wire 8 n" sub5_out[0][0] [7:0] $end - $var wire 8 o" sub5_out[0][1] [7:0] $end - $var wire 8 p" sub5_out[0][2] [7:0] $end - $var wire 8 q" sub5_out[1][0] [7:0] $end - $var wire 8 r" sub5_out[1][1] [7:0] $end - $var wire 8 s" sub5_out[1][2] [7:0] $end - $var wire 32 ?! count [31:0] $end - $var wire 32 & driven_from_bind [31:0] $end + $var wire 128 %! sub5_in[0][0] [127:0] $end + $var wire 128 )! sub5_in[0][1] [127:0] $end + $var wire 128 -! sub5_in[0][2] [127:0] $end + $var wire 128 1! sub5_in[1][0] [127:0] $end + $var wire 128 5! sub5_in[1][1] [127:0] $end + $var wire 128 9! sub5_in[1][2] [127:0] $end + $var wire 8 ]! sub5_out[0][0] [7:0] $end + $var wire 8 ^! sub5_out[0][1] [7:0] $end + $var wire 8 _! sub5_out[0][2] [7:0] $end + $var wire 8 `! sub5_out[1][0] [7:0] $end + $var wire 8 a! sub5_out[1][1] [7:0] $end + $var wire 8 b! sub5_out[1][2] [7:0] $end + $var wire 32 =! count [31:0] $end + $var wire 32 % driven_from_bind [31:0] $end $scope module i_sub4_bound $end - $var real 64 )# P1 $end - $var wire 32 & driven_from_bind [31:0] $end + $var real 64 p! P1 $end + $var wire 32 % driven_from_bind [31:0] $end $upscope $end $scope module i_sub5 $end - $var wire 1 z" clk $end - $var wire 128 /" in[0][0] [127:0] $end - $var wire 128 3" in[0][1] [127:0] $end - $var wire 128 7" in[0][2] [127:0] $end - $var wire 128 ;" in[1][0] [127:0] $end - $var wire 128 ?" in[1][1] [127:0] $end - $var wire 128 C" in[1][2] [127:0] $end - $var wire 8 t" out[0][0] [7:0] $end - $var wire 8 u" out[0][1] [7:0] $end - $var wire 8 v" out[0][2] [7:0] $end - $var wire 8 w" out[1][0] [7:0] $end - $var wire 8 x" out[1][1] [7:0] $end - $var wire 8 y" out[1][2] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 @! i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 A! j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 B! exp [7:0] $end - $upscope $end + $var wire 1 ~' clk $end + $var wire 128 _' in[0][0] [127:0] $end + $var wire 128 c' in[0][1] [127:0] $end + $var wire 128 g' in[0][2] [127:0] $end + $var wire 128 k' in[1][0] [127:0] $end + $var wire 128 o' in[1][1] [127:0] $end + $var wire 128 s' in[1][2] [127:0] $end + $var wire 8 w' out[0][0] [7:0] $end + $var wire 8 x' out[0][1] [7:0] $end + $var wire 8 y' out[0][2] [7:0] $end + $var wire 8 z' out[1][0] [7:0] $end + $var wire 8 {' out[1][1] [7:0] $end + $var wire 8 |' out[1][2] [7:0] $end + $var wire 32 }' count [31:0] $end + $var wire 8 O' val0[0] [7:0] $end + $var wire 8 P' val0[1] [7:0] $end + $var wire 8 Q' val1[0] [7:0] $end + $var wire 8 R' val1[1] [7:0] $end + $var wire 8 S' val2[0] [7:0] $end + $var wire 8 T' val2[1] [7:0] $end + $var wire 8 U' val3[0] [7:0] $end + $var wire 8 V' val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 !( P0 [31:0] $end + $var wire 32 "( P1 [31:0] $end + $var wire 8 W' out[0] [7:0] $end + $var wire 8 X' out[1] [7:0] $end $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.i_sub0.i_sub0 $end - $var wire 1 2# clk $end - $var wire 8 3# in [7:0] $end - $var wire 8 4# out [7:0] $end - $scope module sub0 $end - $var wire 1 2# clk $end - $var wire 8 3# in [7:0] $end - $var wire 8 4# out [7:0] $end - $var wire 8 5# ff [7:0] $end - $upscope $end - $upscope $end - $scope module top.t.i_sub1 $end - $var wire 1 7# clk $end - $var wire 8 8# in [11:4] $end - $var wire 8 9# out [7:0] $end - $scope module sub1 $end - $var wire 1 7# clk $end - $var wire 8 8# in [11:4] $end - $var wire 8 9# out [7:0] $end - $var wire 8 :# ff [7:0] $end - $upscope $end - $upscope $end - $scope module top.t.i_sub2 $end - $var wire 1 +' clk $end - $var wire 8 ,' in [7:0] $end - $var wire 8 -' out [7:0] $end - $scope module sub2 $end - $var wire 1 +' clk $end - $var wire 8 ,' in [7:0] $end - $var wire 8 -' out [7:0] $end - $var wire 8 "$ ff [7:0] $end - $scope module in_ifs $end - $var wire 1 +' clk $end - $var wire 8 "$ data [7:0] $end - $upscope $end - $scope module out_ifs $end - $var wire 1 +' clk $end - $var wire 8 #$ data [7:0] $end - $upscope $end - $scope module i_sub3 $end - $scope module in $end - $var wire 1 +' clk $end - $var wire 8 "$ data [7:0] $end - $upscope $end - $scope module out $end - $var wire 1 +' clk $end - $var wire 8 #$ data [7:0] $end - $upscope $end - $var wire 8 "$ in_wire [7:0] $end - $var wire 8 #$ out_1 [7:0] $end - $var wire 8 $$ out_2 [7:0] $end - $scope module i_sub3 $end - $var wire 8 .' P0 [7:0] $end - $var wire 32 /' UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 0' UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 1' UNUSED [15:0] $end - $var wire 2 2' ENUM [1:0] $end - $var wire 1 +' clk $end - $var wire 8 "$ in [7:0] $end - $var wire 8 #$ out [7:0] $end - $var wire 8 %$ ff [7:0] $end - $var wire 8 #$ out4 [7:0] $end - $var wire 8 &$ out4_2 [7:0] $end - $scope module i_sub4_0 $end - $var wire 32 3' P0 [31:0] $end - $var real 64 4' P1 $end - $var real 64 6' P3 $end - $var wire 1 +' clk $end - $var wire 8 %$ in [7:0] $end - $var wire 8 #$ out [7:0] $end - $var wire 8 #$ ff [7:0] $end - $var wire 128 '$ sub5_in[0][0] [127:0] $end - $var wire 128 +$ sub5_in[0][1] [127:0] $end - $var wire 128 /$ sub5_in[0][2] [127:0] $end - $var wire 128 3$ sub5_in[1][0] [127:0] $end - $var wire 128 7$ sub5_in[1][1] [127:0] $end - $var wire 128 ;$ sub5_in[1][2] [127:0] $end - $var wire 8 ?$ sub5_out[0][0] [7:0] $end - $var wire 8 @$ sub5_out[0][1] [7:0] $end - $var wire 8 A$ sub5_out[0][2] [7:0] $end - $var wire 8 B$ sub5_out[1][0] [7:0] $end - $var wire 8 C$ sub5_out[1][1] [7:0] $end - $var wire 8 D$ sub5_out[1][2] [7:0] $end - $var wire 32 E$ count [31:0] $end - $var wire 32 <# driven_from_bind [31:0] $end - $scope module i_sub4_bound $end - $var real 64 4' P1 $end - $var wire 32 <# driven_from_bind [31:0] $end + $scope module i_sub1 $end + $var wire 32 !( P0 [31:0] $end + $var wire 32 "( P1 [31:0] $end + $var wire 8 Y' out[0] [7:0] $end + $var wire 8 Z' out[1] [7:0] $end $upscope $end - $scope module i_sub5 $end - $var wire 1 +' clk $end - $var wire 128 F$ in[0][0] [127:0] $end - $var wire 128 J$ in[0][1] [127:0] $end - $var wire 128 N$ in[0][2] [127:0] $end - $var wire 128 R$ in[1][0] [127:0] $end - $var wire 128 V$ in[1][1] [127:0] $end - $var wire 128 Z$ in[1][2] [127:0] $end - $var wire 8 ^$ out[0][0] [7:0] $end - $var wire 8 _$ out[0][1] [7:0] $end - $var wire 8 `$ out[0][2] [7:0] $end - $var wire 8 a$ out[1][0] [7:0] $end - $var wire 8 b$ out[1][1] [7:0] $end - $var wire 8 c$ out[1][2] [7:0] $end - $var wire 32 d$ count [31:0] $end - $var wire 8 =# val0[0] [7:0] $end - $var wire 8 ># val0[1] [7:0] $end - $var wire 8 ?# val1[0] [7:0] $end - $var wire 8 @# val1[1] [7:0] $end - $var wire 8 A# val2[0] [7:0] $end - $var wire 8 B# val2[1] [7:0] $end - $var wire 8 C# val3[0] [7:0] $end - $var wire 8 D# val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 E# out[0] [7:0] $end - $var wire 8 F# out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 G# out[0] [7:0] $end - $var wire 8 H# out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 I# out[0] [7:0] $end - $var wire 8 J# out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 :' P1 [31:0] $end - $var wire 8 K# out[0] [7:0] $end - $var wire 8 L# out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 e$ i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 f$ j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 g$ exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end + $scope module i_sub2 $end + $var wire 32 !( P0 [31:0] $end + $var wire 32 "( P1 [31:0] $end + $var wire 8 [' out[0] [7:0] $end + $var wire 8 \' out[1] [7:0] $end $upscope $end - $scope module unnamedblk1 $end - $var wire 32 k$ i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 l$ j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 m$ exp [7:0] $end - $upscope $end - $upscope $end + $scope module i_sub3 $end + $var wire 32 !( P0 [31:0] $end + $var wire 32 #( P1 [31:0] $end + $var wire 8 ]' out[0] [7:0] $end + $var wire 8 ^' out[1] [7:0] $end $upscope $end $upscope $end - $scope module i_sub4_1 $end - $var wire 32 3' P0 [31:0] $end - $var real 64 4' P1 $end - $var real 64 ;' P3 $end - $var wire 1 +' clk $end - $var wire 8 %$ in [7:0] $end - $var wire 8 &$ out [7:0] $end - $var wire 8 &$ ff [7:0] $end - $var wire 128 n$ sub5_in[0][0] [127:0] $end - $var wire 128 r$ sub5_in[0][1] [127:0] $end - $var wire 128 v$ sub5_in[0][2] [127:0] $end - $var wire 128 z$ sub5_in[1][0] [127:0] $end - $var wire 128 ~$ sub5_in[1][1] [127:0] $end - $var wire 128 $% sub5_in[1][2] [127:0] $end - $var wire 8 (% sub5_out[0][0] [7:0] $end - $var wire 8 )% sub5_out[0][1] [7:0] $end - $var wire 8 *% sub5_out[0][2] [7:0] $end - $var wire 8 +% sub5_out[1][0] [7:0] $end - $var wire 8 ,% sub5_out[1][1] [7:0] $end - $var wire 8 -% sub5_out[1][2] [7:0] $end - $var wire 32 .% count [31:0] $end - $var wire 32 M# driven_from_bind [31:0] $end - $scope module i_sub4_bound $end - $var real 64 4' P1 $end - $var wire 32 M# driven_from_bind [31:0] $end - $upscope $end - $scope module i_sub5 $end - $var wire 1 +' clk $end - $var wire 128 /% in[0][0] [127:0] $end - $var wire 128 3% in[0][1] [127:0] $end - $var wire 128 7% in[0][2] [127:0] $end - $var wire 128 ;% in[1][0] [127:0] $end - $var wire 128 ?% in[1][1] [127:0] $end - $var wire 128 C% in[1][2] [127:0] $end - $var wire 8 G% out[0][0] [7:0] $end - $var wire 8 H% out[0][1] [7:0] $end - $var wire 8 I% out[0][2] [7:0] $end - $var wire 8 J% out[1][0] [7:0] $end - $var wire 8 K% out[1][1] [7:0] $end - $var wire 8 L% out[1][2] [7:0] $end - $var wire 32 M% count [31:0] $end - $var wire 8 N# val0[0] [7:0] $end - $var wire 8 O# val0[1] [7:0] $end - $var wire 8 P# val1[0] [7:0] $end - $var wire 8 Q# val1[1] [7:0] $end - $var wire 8 R# val2[0] [7:0] $end - $var wire 8 S# val2[1] [7:0] $end - $var wire 8 T# val3[0] [7:0] $end - $var wire 8 U# val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 V# out[0] [7:0] $end - $var wire 8 W# out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 X# out[0] [7:0] $end - $var wire 8 Y# out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 Z# out[0] [7:0] $end - $var wire 8 [# out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 :' P1 [31:0] $end - $var wire 8 \# out[0] [7:0] $end - $var wire 8 ]# out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 N% i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 O% j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 P% exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 T% i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 U% j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 V% exp [7:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module i_sub3_2 $end - $var wire 8 .' P0 [7:0] $end - $var wire 32 =' UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 >' UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 1' UNUSED [15:0] $end - $var wire 2 2' ENUM [1:0] $end - $var wire 1 +' clk $end - $var wire 8 "$ in [7:0] $end - $var wire 8 $$ out [7:0] $end - $var wire 8 W% ff [7:0] $end - $var wire 8 $$ out4 [7:0] $end - $var wire 8 X% out4_2 [7:0] $end - $scope module i_sub4_0 $end - $var wire 32 3' P0 [31:0] $end - $var real 64 4' P1 $end - $var real 64 6' P3 $end - $var wire 1 +' clk $end - $var wire 8 W% in [7:0] $end - $var wire 8 $$ out [7:0] $end - $var wire 8 $$ ff [7:0] $end - $var wire 128 Y% sub5_in[0][0] [127:0] $end - $var wire 128 ]% sub5_in[0][1] [127:0] $end - $var wire 128 a% sub5_in[0][2] [127:0] $end - $var wire 128 e% sub5_in[1][0] [127:0] $end - $var wire 128 i% sub5_in[1][1] [127:0] $end - $var wire 128 m% sub5_in[1][2] [127:0] $end - $var wire 8 q% sub5_out[0][0] [7:0] $end - $var wire 8 r% sub5_out[0][1] [7:0] $end - $var wire 8 s% sub5_out[0][2] [7:0] $end - $var wire 8 t% sub5_out[1][0] [7:0] $end - $var wire 8 u% sub5_out[1][1] [7:0] $end - $var wire 8 v% sub5_out[1][2] [7:0] $end - $var wire 32 w% count [31:0] $end - $var wire 32 ^# driven_from_bind [31:0] $end - $scope module i_sub4_bound $end - $var real 64 4' P1 $end - $var wire 32 ^# driven_from_bind [31:0] $end - $upscope $end - $scope module i_sub5 $end - $var wire 1 +' clk $end - $var wire 128 x% in[0][0] [127:0] $end - $var wire 128 |% in[0][1] [127:0] $end - $var wire 128 "& in[0][2] [127:0] $end - $var wire 128 && in[1][0] [127:0] $end - $var wire 128 *& in[1][1] [127:0] $end - $var wire 128 .& in[1][2] [127:0] $end - $var wire 8 2& out[0][0] [7:0] $end - $var wire 8 3& out[0][1] [7:0] $end - $var wire 8 4& out[0][2] [7:0] $end - $var wire 8 5& out[1][0] [7:0] $end - $var wire 8 6& out[1][1] [7:0] $end - $var wire 8 7& out[1][2] [7:0] $end - $var wire 32 8& count [31:0] $end - $var wire 8 _# val0[0] [7:0] $end - $var wire 8 `# val0[1] [7:0] $end - $var wire 8 a# val1[0] [7:0] $end - $var wire 8 b# val1[1] [7:0] $end - $var wire 8 c# val2[0] [7:0] $end - $var wire 8 d# val2[1] [7:0] $end - $var wire 8 e# val3[0] [7:0] $end - $var wire 8 f# val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 g# out[0] [7:0] $end - $var wire 8 h# out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 i# out[0] [7:0] $end - $var wire 8 j# out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 k# out[0] [7:0] $end - $var wire 8 l# out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 :' P1 [31:0] $end - $var wire 8 m# out[0] [7:0] $end - $var wire 8 n# out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 9& i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 :& j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 ;& exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 ?& i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 @& j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 A& exp [7:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module i_sub4_1 $end - $var wire 32 3' P0 [31:0] $end - $var real 64 4' P1 $end - $var real 64 ;' P3 $end - $var wire 1 +' clk $end - $var wire 8 W% in [7:0] $end - $var wire 8 X% out [7:0] $end - $var wire 8 X% ff [7:0] $end - $var wire 128 B& sub5_in[0][0] [127:0] $end - $var wire 128 F& sub5_in[0][1] [127:0] $end - $var wire 128 J& sub5_in[0][2] [127:0] $end - $var wire 128 N& sub5_in[1][0] [127:0] $end - $var wire 128 R& sub5_in[1][1] [127:0] $end - $var wire 128 V& sub5_in[1][2] [127:0] $end - $var wire 8 Z& sub5_out[0][0] [7:0] $end - $var wire 8 [& sub5_out[0][1] [7:0] $end - $var wire 8 \& sub5_out[0][2] [7:0] $end - $var wire 8 ]& sub5_out[1][0] [7:0] $end - $var wire 8 ^& sub5_out[1][1] [7:0] $end - $var wire 8 _& sub5_out[1][2] [7:0] $end - $var wire 32 `& count [31:0] $end - $var wire 32 o# driven_from_bind [31:0] $end - $scope module i_sub4_bound $end - $var real 64 4' P1 $end - $var wire 32 o# driven_from_bind [31:0] $end - $upscope $end - $scope module i_sub5 $end - $var wire 1 +' clk $end - $var wire 128 a& in[0][0] [127:0] $end - $var wire 128 e& in[0][1] [127:0] $end - $var wire 128 i& in[0][2] [127:0] $end - $var wire 128 m& in[1][0] [127:0] $end - $var wire 128 q& in[1][1] [127:0] $end - $var wire 128 u& in[1][2] [127:0] $end - $var wire 8 y& out[0][0] [7:0] $end - $var wire 8 z& out[0][1] [7:0] $end - $var wire 8 {& out[0][2] [7:0] $end - $var wire 8 |& out[1][0] [7:0] $end - $var wire 8 }& out[1][1] [7:0] $end - $var wire 8 ~& out[1][2] [7:0] $end - $var wire 32 !' count [31:0] $end - $var wire 8 p# val0[0] [7:0] $end - $var wire 8 q# val0[1] [7:0] $end - $var wire 8 r# val1[0] [7:0] $end - $var wire 8 s# val1[1] [7:0] $end - $var wire 8 t# val2[0] [7:0] $end - $var wire 8 u# val2[1] [7:0] $end - $var wire 8 v# val3[0] [7:0] $end - $var wire 8 w# val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 x# out[0] [7:0] $end - $var wire 8 y# out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 z# out[0] [7:0] $end - $var wire 8 {# out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 9' P1 [31:0] $end - $var wire 8 |# out[0] [7:0] $end - $var wire 8 }# out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 8' P0 [31:0] $end - $var wire 32 :' P1 [31:0] $end - $var wire 8 ~# out[0] [7:0] $end - $var wire 8 !$ out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 "' i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 #' j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 $' exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 (' i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 )' j [31:0] $end - $scope module unnamedblk3 $end - $var wire 8 *' exp [7:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.i_sub3.i_sub4_0.i_sub5 $end - $var wire 1 u' clk $end - $var wire 128 v' in[0][0] [127:0] $end - $var wire 128 z' in[0][1] [127:0] $end - $var wire 128 ~' in[0][2] [127:0] $end - $var wire 128 $( in[1][0] [127:0] $end - $var wire 128 (( in[1][1] [127:0] $end - $var wire 128 ,( in[1][2] [127:0] $end - $var wire 8 0( out[0][0] [7:0] $end - $var wire 8 1( out[0][1] [7:0] $end - $var wire 8 2( out[0][2] [7:0] $end - $var wire 8 3( out[1][0] [7:0] $end - $var wire 8 4( out[1][1] [7:0] $end - $var wire 8 5( out[1][2] [7:0] $end - $scope module sub5 $end - $var wire 1 u' clk $end - $var wire 128 P' in[0][0] [127:0] $end - $var wire 128 T' in[0][1] [127:0] $end - $var wire 128 X' in[0][2] [127:0] $end - $var wire 128 \' in[1][0] [127:0] $end - $var wire 128 `' in[1][1] [127:0] $end - $var wire 128 d' in[1][2] [127:0] $end - $var wire 8 h' out[0][0] [7:0] $end - $var wire 8 i' out[0][1] [7:0] $end - $var wire 8 j' out[0][2] [7:0] $end - $var wire 8 k' out[1][0] [7:0] $end - $var wire 8 l' out[1][1] [7:0] $end - $var wire 8 m' out[1][2] [7:0] $end - $var wire 32 n' count [31:0] $end - $var wire 8 @' val0[0] [7:0] $end - $var wire 8 A' val0[1] [7:0] $end - $var wire 8 B' val1[0] [7:0] $end - $var wire 8 C' val1[1] [7:0] $end - $var wire 8 D' val2[0] [7:0] $end - $var wire 8 E' val2[1] [7:0] $end - $var wire 8 F' val3[0] [7:0] $end - $var wire 8 G' val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 6( P0 [31:0] $end - $var wire 32 7( P1 [31:0] $end - $var wire 8 H' out[0] [7:0] $end - $var wire 8 I' out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 6( P0 [31:0] $end - $var wire 32 7( P1 [31:0] $end - $var wire 8 J' out[0] [7:0] $end - $var wire 8 K' out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 6( P0 [31:0] $end - $var wire 32 7( P1 [31:0] $end - $var wire 8 L' out[0] [7:0] $end - $var wire 8 M' out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 6( P0 [31:0] $end - $var wire 32 8( P1 [31:0] $end - $var wire 8 N' out[0] [7:0] $end - $var wire 8 O' out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 o' i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 p' j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 q' exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.i_sub3.i_sub4_1.i_sub5 $end - $var wire 1 o( clk $end - $var wire 128 p( in[0][0] [127:0] $end - $var wire 128 t( in[0][1] [127:0] $end - $var wire 128 x( in[0][2] [127:0] $end - $var wire 128 |( in[1][0] [127:0] $end - $var wire 128 ") in[1][1] [127:0] $end - $var wire 128 &) in[1][2] [127:0] $end - $var wire 8 *) out[0][0] [7:0] $end - $var wire 8 +) out[0][1] [7:0] $end - $var wire 8 ,) out[0][2] [7:0] $end - $var wire 8 -) out[1][0] [7:0] $end - $var wire 8 .) out[1][1] [7:0] $end - $var wire 8 /) out[1][2] [7:0] $end - $scope module sub5 $end - $var wire 1 o( clk $end - $var wire 128 J( in[0][0] [127:0] $end - $var wire 128 N( in[0][1] [127:0] $end - $var wire 128 R( in[0][2] [127:0] $end - $var wire 128 V( in[1][0] [127:0] $end - $var wire 128 Z( in[1][1] [127:0] $end - $var wire 128 ^( in[1][2] [127:0] $end - $var wire 8 b( out[0][0] [7:0] $end - $var wire 8 c( out[0][1] [7:0] $end - $var wire 8 d( out[0][2] [7:0] $end - $var wire 8 e( out[1][0] [7:0] $end - $var wire 8 f( out[1][1] [7:0] $end - $var wire 8 g( out[1][2] [7:0] $end - $var wire 32 h( count [31:0] $end - $var wire 8 :( val0[0] [7:0] $end - $var wire 8 ;( val0[1] [7:0] $end - $var wire 8 <( val1[0] [7:0] $end - $var wire 8 =( val1[1] [7:0] $end - $var wire 8 >( val2[0] [7:0] $end - $var wire 8 ?( val2[1] [7:0] $end - $var wire 8 @( val3[0] [7:0] $end - $var wire 8 A( val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 0) P0 [31:0] $end - $var wire 32 1) P1 [31:0] $end - $var wire 8 B( out[0] [7:0] $end - $var wire 8 C( out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 0) P0 [31:0] $end - $var wire 32 1) P1 [31:0] $end - $var wire 8 D( out[0] [7:0] $end - $var wire 8 E( out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 0) P0 [31:0] $end - $var wire 32 1) P1 [31:0] $end - $var wire 8 F( out[0] [7:0] $end - $var wire 8 G( out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 0) P0 [31:0] $end - $var wire 32 2) P1 [31:0] $end - $var wire 8 H( out[0] [7:0] $end - $var wire 8 I( out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 i( i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 j( j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 k( exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.i_sub3_2.i_sub4_0.i_sub5 $end - $var wire 1 i) clk $end - $var wire 128 j) in[0][0] [127:0] $end - $var wire 128 n) in[0][1] [127:0] $end - $var wire 128 r) in[0][2] [127:0] $end - $var wire 128 v) in[1][0] [127:0] $end - $var wire 128 z) in[1][1] [127:0] $end - $var wire 128 ~) in[1][2] [127:0] $end - $var wire 8 $* out[0][0] [7:0] $end - $var wire 8 %* out[0][1] [7:0] $end - $var wire 8 &* out[0][2] [7:0] $end - $var wire 8 '* out[1][0] [7:0] $end - $var wire 8 (* out[1][1] [7:0] $end - $var wire 8 )* out[1][2] [7:0] $end - $scope module sub5 $end - $var wire 1 i) clk $end - $var wire 128 D) in[0][0] [127:0] $end - $var wire 128 H) in[0][1] [127:0] $end - $var wire 128 L) in[0][2] [127:0] $end - $var wire 128 P) in[1][0] [127:0] $end - $var wire 128 T) in[1][1] [127:0] $end - $var wire 128 X) in[1][2] [127:0] $end - $var wire 8 \) out[0][0] [7:0] $end - $var wire 8 ]) out[0][1] [7:0] $end - $var wire 8 ^) out[0][2] [7:0] $end - $var wire 8 _) out[1][0] [7:0] $end - $var wire 8 `) out[1][1] [7:0] $end - $var wire 8 a) out[1][2] [7:0] $end - $var wire 32 b) count [31:0] $end - $var wire 8 4) val0[0] [7:0] $end - $var wire 8 5) val0[1] [7:0] $end - $var wire 8 6) val1[0] [7:0] $end - $var wire 8 7) val1[1] [7:0] $end - $var wire 8 8) val2[0] [7:0] $end - $var wire 8 9) val2[1] [7:0] $end - $var wire 8 :) val3[0] [7:0] $end - $var wire 8 ;) val3[1] [7:0] $end - $scope module i_sub0 $end - $var wire 32 ** P0 [31:0] $end - $var wire 32 +* P1 [31:0] $end - $var wire 8 <) out[0] [7:0] $end - $var wire 8 =) out[1] [7:0] $end - $upscope $end - $scope module i_sub1 $end - $var wire 32 ** P0 [31:0] $end - $var wire 32 +* P1 [31:0] $end - $var wire 8 >) out[0] [7:0] $end - $var wire 8 ?) out[1] [7:0] $end - $upscope $end - $scope module i_sub2 $end - $var wire 32 ** P0 [31:0] $end - $var wire 32 +* P1 [31:0] $end - $var wire 8 @) out[0] [7:0] $end - $var wire 8 A) out[1] [7:0] $end - $upscope $end - $scope module i_sub3 $end - $var wire 32 ** P0 [31:0] $end - $var wire 32 ,* P1 [31:0] $end - $var wire 8 B) out[0] [7:0] $end - $var wire 8 C) out[1] [7:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 c) i [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 d) j [31:0] $end - $scope module unnamedblk3 $end - $var wire 128 e) exp [127:0] $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.i_sub3_2.i_sub4_1.i_sub5 $end - $var wire 1 c* clk $end - $var wire 128 d* in[0][0] [127:0] $end - $var wire 128 h* in[0][1] [127:0] $end - $var wire 128 l* in[0][2] [127:0] $end - $var wire 128 p* in[1][0] [127:0] $end - $var wire 128 t* in[1][1] [127:0] $end - $var wire 128 x* in[1][2] [127:0] $end - $var wire 8 |* out[0][0] [7:0] $end - $var wire 8 }* out[0][1] [7:0] $end - $var wire 8 ~* out[0][2] [7:0] $end - $var wire 8 !+ out[1][0] [7:0] $end - $var wire 8 "+ out[1][1] [7:0] $end - $var wire 8 #+ out[1][2] [7:0] $end - $scope module sub5 $end - $var wire 1 c* clk $end - $var wire 128 >* in[0][0] [127:0] $end - $var wire 128 B* in[0][1] [127:0] $end - $var wire 128 F* in[0][2] [127:0] $end - $var wire 128 J* in[1][0] [127:0] $end - $var wire 128 N* in[1][1] [127:0] $end - $var wire 128 R* in[1][2] [127:0] $end - $var wire 8 V* out[0][0] [7:0] $end - $var wire 8 W* out[0][1] [7:0] $end - $var wire 8 X* out[0][2] [7:0] $end - $var wire 8 Y* out[1][0] [7:0] $end - $var wire 8 Z* out[1][1] [7:0] $end - $var wire 8 [* out[1][2] [7:0] $end - $var wire 32 \* count [31:0] $end - $var wire 8 .* val0[0] [7:0] $end - $var wire 8 /* val0[1] [7:0] $end - $var wire 8 0* val1[0] [7:0] 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+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 k' +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 o' +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 s' +b00000000 w' +b00000000 x' +b00000000 y' +b00000000 z' +b00000000 {' +b00000000 |' +b00000000000000000000000000010001 }' +1~' diff --git a/test_regress/t/t_hier_block_trace_vcd.py b/test_regress/t/t_hier_block_trace_vcd.py index 6e06e809d..2d0a09733 100755 --- a/test_regress/t/t_hier_block_trace_vcd.py +++ b/test_regress/t/t_hier_block_trace_vcd.py @@ -1,34 +1,73 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap -test.priority(30) +import re + +noinline = "noinl" in test.name +if not noinline: + test.priority(30) test.scenarios('vlt_all') test.top_filename = "t/t_hier_block.v" -# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. -# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. -# So use 6 threads here though it's not optimal in performance, but ok. +verilator_common_flags = [ + 't/t_hier_block.cpp', + '--Wno-TIMESCALEMOD', + '--trace-vcd', + '--trace-underscore', # Should not trace handle + "--trace-max-width", + "0", + "--trace-max-array", + "0", + "--trace-structs", +] -test.compile( - v_flags2=['t/t_hier_block.cpp'], - verilator_flags2=[ - '--hierarchical', - '--Wno-TIMESCALEMOD', - '--trace-vcd', - '--no-trace-underscore', # To avoid handle mismatches - ], - threads=(6 if test.vltmt else 1)) +verilator_hier_flags = verilator_common_flags + ['--hierarchical'] +if noinline: + verilator_hier_flags.extend(["+define+NO_INLINE"]) -test.execute() +# Compile hierarchically +test.vm_prefix = "Vhier" +test.main_filename = test.obj_dir + "/Vhier__main.cpp" +test.compile(verilator_flags2=verilator_hier_flags) -test.vcd_identical(test.trace_filename, test.golden_filename) +# Compile non hierarchically +test.vm_prefix = "Vnonh" +test.main_filename = test.obj_dir + "/Vnonh__main.cpp" +test.compile(verilator_flags2=verilator_common_flags) + +trace_hier = test.trace_filename.replace("simx", "hier") +trace_nonh = test.trace_filename.replace("simx", "nonh") + +# Run the hierarchical model +test.execute(executable=test.obj_dir + "/Vhier") +test.run(cmd=["mv", test.trace_filename, trace_hier]) +# Run the non hierarchical model +test.execute(executable=test.obj_dir + "/Vnonh") +test.run(cmd=["mv", test.trace_filename, trace_nonh]) + +# Scope structure must match exactly +with open(trace_nonh, 'r', encoding='utf8') as fnonh, open(trace_hier, 'r', + encoding='utf8') as fhier: + for la, lb in zip(fnonh, fhier): + la = re.sub(r'^(\s*\$var\s+\S+\s+\S+\s+)\S+(.*)$', r'\1CODE\2', la) + lb = re.sub(r'^(\s*\$var\s+\S+\s+\S+\s+)\S+(.*)$', r'\1CODE\2', lb) + if la != lb: + test.error_keep_going("VCD header mismatch: '{}' !~ '{}'".format( + la.strip(), lb.strip())) + if "enddefinitions" in la: + break + +# The two models must match +test.vcd_identical(trace_hier, trace_nonh) +# The hierarchical must match the reference +test.vcd_identical(trace_hier, test.golden_filename.replace("_noinl", "")) test.passes() diff --git a/test_regress/t/t_hier_block_trace_vcd_noinl.py b/test_regress/t/t_hier_block_trace_vcd_noinl.py new file mode 100755 index 000000000..8b05cc089 --- /dev/null +++ b/test_regress/t/t_hier_block_trace_vcd_noinl.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +import runpy + +test.priority(30) +test.scenarios('vlt_all') + +runpy.run_path("t/t_hier_block_trace_vcd.py", globals()) diff --git a/test_regress/t/t_hier_block_trace_vcd_statful_pkg.out b/test_regress/t/t_hier_block_trace_vcd_statful_pkg.out new file mode 100644 index 000000000..360cddbd0 --- /dev/null +++ b/test_regress/t/t_hier_block_trace_vcd_statful_pkg.out @@ -0,0 +1,5361 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module top $end + $var wire 1 d! clk $end + $scope module $unit $end + $var wire 1 >! global_flag $end + $upscope $end + $scope module stateless_pkg $end + $var wire 32 y! ONE [31:0] $end + $upscope $end + $scope module t $end + $var wire 32 e! PARAM_A [31:0] $end + $var wire 32 f! PARAM_B [31:0] $end + $var wire 1 d! clk $end + $var wire 8 I! out0 [7:0] $end + $var wire 8 J! out1 [7:0] $end + $var wire 8 K! out2 [7:0] $end + $var wire 8 ?! out3 [7:0] $end + $var wire 8 & out3_2 [7:0] $end + $var wire 8 ' out5 [7:0] $end + $var wire 8 ( out6 [7:0] $end + $var wire 32 ) count [31:0] $end + $scope module i_delay0 $end + $var wire 32 g! N [31:0] $end + $var wire 32 h! WIDTH [31:0] $end + $var wire 1 d! clk $end + $var wire 8 ?! in [7:0] $end + $var wire 8 ' out [7:0] $end + $var wire 8 * tmp [7:0] $end + $scope module genblk1 $end + $scope module i_delay $end + $var wire 32 i! N [31:0] $end + $var wire 32 h! WIDTH [31:0] $end + $var wire 1 d! clk $end + $var wire 8 * in [7:0] $end + $var wire 8 ' out [7:0] $end + $var wire 8 ' tmp [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_delay1 $end + $var wire 32 j! N [31:0] $end + $var wire 32 h! WIDTH [31:0] $end + $var wire 1 d! clk $end + $var wire 8 ' in [7:0] $end + $var wire 8 ( out [7:0] $end + $var wire 8 + tmp [7:0] $end + $scope module genblk1 $end + $scope module i_delay $end + $var wire 32 g! N [31:0] $end + $var wire 32 h! WIDTH [31:0] $end + $var wire 1 d! clk $end + $var wire 8 + in [7:0] $end + $var wire 8 ( out [7:0] $end + $var wire 8 , tmp [7:0] $end + $scope module genblk1 $end + $scope module i_delay $end + $var wire 32 i! N [31:0] $end + $var wire 32 h! WIDTH [31:0] $end + $var wire 1 d! clk $end + $var wire 8 , in [7:0] $end + $var wire 8 ( out [7:0] $end + $var wire 8 ( tmp [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub0 $end + $var wire 1 d! clk $end + $var wire 8 ?! in [7:0] $end + $var wire 8 I! out [7:0] $end + $scope module i_sub0 $end + $var wire 1 z! clk $end + $var wire 8 {! in [7:0] $end + $var wire 8 |! out [7:0] $end + $var wire 8 }! ff [7:0] $end + $scope module $libroot $end + $var wire 1 ~! global_flag $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub1 $end + $var wire 1 !" clk $end + $var wire 8 "" in [11:4] $end + $var wire 8 #" out [7:0] $end + $var wire 8 $" ff [7:0] $end + $var wire 2 %" enum_v [1:0] $end + $scope module $libroot $end + $var wire 1 &" global_flag $end + $upscope $end + $upscope $end + $scope module i_sub2 $end + $var wire 1 a% clk $end + $var wire 8 b% in [7:0] $end + $var wire 8 c% out [7:0] $end + $var wire 8 k" ff [7:0] $end + $var wire 2 l" alt_enum_v [1:0] $end + $scope module $libroot $end + $var wire 1 u% global_flag $end + $upscope $end + $scope module i_sub3 $end + $var wire 8 k" in_wire [7:0] $end + $var wire 8 m" out_1 [7:0] $end + $var wire 8 n" out_2 [7:0] $end + $scope module i_sub3 $end + $var wire 8 d% P0 [7:0] $end + $var wire 32 e% UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 f% UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 g% UNUSED [15:0] $end + $var wire 2 h% ENUM [1:0] $end + $var wire 1 a% clk $end + $var wire 8 k" in [7:0] $end + $var wire 8 m" out [7:0] $end + $var wire 1 o" ff[0] $end + $var wire 1 p" ff[1] $end + $var wire 1 q" ff[2] $end + $var wire 1 r" ff[3] $end + $var wire 1 s" ff[4] $end + $var wire 1 t" ff[5] $end + $var wire 1 u" ff[6] $end + $var wire 1 v" ff[7] $end + $var wire 8 m" out4 [7:0] $end + $var wire 8 w" out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 32 i% P0 [31:0] $end + $var real 64 j% P1 $end + $var real 64 l% P3 $end + $var wire 1 a% clk $end + $var wire 8 x" in [7:0] $end + $var wire 8 m" out [7:0] $end + $var wire 8 m" ff [7:0] $end + $var wire 128 y" sub5_in[0][0] [127:0] $end + $var wire 128 }" sub5_in[0][1] [127:0] $end + $var wire 128 ## sub5_in[0][2] [127:0] $end + $var wire 128 '# sub5_in[1][0] [127:0] $end + $var wire 128 +# sub5_in[1][1] [127:0] $end + $var wire 128 /# sub5_in[1][2] [127:0] $end + $var wire 8 3# sub5_out[0][0] [7:0] $end + $var wire 8 4# sub5_out[0][1] [7:0] $end + $var wire 8 5# sub5_out[0][2] [7:0] $end + $var wire 8 6# sub5_out[1][0] [7:0] $end + $var wire 8 7# sub5_out[1][1] [7:0] $end + $var wire 8 8# sub5_out[1][2] [7:0] $end + $var wire 32 9# count [31:0] $end + $var wire 32 '" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 j% P1 $end + $var wire 32 '" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 a% clk $end + $var wire 128 :# in[0][0] [127:0] $end + $var wire 128 ># in[0][1] [127:0] $end + $var wire 128 B# in[0][2] [127:0] $end + $var wire 128 F# in[1][0] [127:0] $end + $var wire 128 J# in[1][1] [127:0] $end + $var wire 128 N# in[1][2] [127:0] $end + $var wire 8 R# out[0][0] [7:0] $end + $var wire 8 S# out[0][1] [7:0] $end + $var wire 8 T# out[0][2] [7:0] $end + $var wire 8 U# out[1][0] [7:0] $end + $var wire 8 V# out[1][1] [7:0] $end + $var wire 8 W# out[1][2] [7:0] $end + $var wire 32 X# count [31:0] $end + $var wire 8 (" val0[0] [7:0] $end + $var wire 8 )" val0[1] [7:0] $end + $var wire 8 *" val1[0] [7:0] $end + $var wire 8 +" val1[1] [7:0] $end + $var wire 8 ," val2[0] [7:0] $end + $var wire 8 -" val2[1] [7:0] $end + $var wire 8 ." val3[0] [7:0] $end + $var wire 8 /" val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 0" out[0] [7:0] $end + $var wire 8 1" out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 2" out[0] [7:0] $end + $var wire 8 3" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 4" out[0] [7:0] $end + $var wire 8 5" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 p% P1 [31:0] $end + $var wire 8 6" out[0] [7:0] $end + $var wire 8 7" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 32 i% P0 [31:0] $end + $var real 64 j% P1 $end + $var real 64 q% P3 $end + $var wire 1 a% clk $end + $var wire 8 x" in [7:0] $end + $var wire 8 w" out [7:0] $end + $var wire 8 w" ff [7:0] $end + $var wire 128 Y# sub5_in[0][0] [127:0] $end + $var wire 128 ]# sub5_in[0][1] [127:0] $end + $var wire 128 a# sub5_in[0][2] [127:0] $end + $var wire 128 e# sub5_in[1][0] [127:0] $end + $var wire 128 i# sub5_in[1][1] [127:0] $end + $var wire 128 m# sub5_in[1][2] [127:0] $end + $var wire 8 q# sub5_out[0][0] [7:0] $end + $var wire 8 r# sub5_out[0][1] [7:0] $end + $var wire 8 s# sub5_out[0][2] [7:0] $end + $var wire 8 t# sub5_out[1][0] [7:0] $end + $var wire 8 u# sub5_out[1][1] [7:0] $end + $var wire 8 v# sub5_out[1][2] [7:0] $end + $var wire 32 w# count [31:0] $end + $var wire 32 8" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 j% P1 $end + $var wire 32 8" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 a% clk $end + $var wire 128 x# in[0][0] [127:0] $end + $var wire 128 |# in[0][1] [127:0] $end + $var wire 128 "$ in[0][2] [127:0] $end + $var wire 128 &$ in[1][0] [127:0] $end + $var wire 128 *$ in[1][1] [127:0] $end + $var wire 128 .$ in[1][2] [127:0] $end + $var wire 8 2$ out[0][0] [7:0] $end + $var wire 8 3$ out[0][1] [7:0] $end + $var wire 8 4$ out[0][2] [7:0] $end + $var wire 8 5$ out[1][0] [7:0] $end + $var wire 8 6$ out[1][1] [7:0] $end + $var wire 8 7$ out[1][2] [7:0] $end + $var wire 32 8$ count [31:0] $end + $var wire 8 9" val0[0] [7:0] $end + $var wire 8 :" val0[1] [7:0] $end + $var wire 8 ;" val1[0] [7:0] $end + $var wire 8 <" val1[1] [7:0] $end + $var wire 8 =" val2[0] [7:0] $end + $var wire 8 >" val2[1] [7:0] $end + $var wire 8 ?" val3[0] [7:0] $end + $var wire 8 @" val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 A" out[0] [7:0] $end + $var wire 8 B" out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 C" out[0] [7:0] $end + $var wire 8 D" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 E" out[0] [7:0] $end + $var wire 8 F" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 p% P1 [31:0] $end + $var wire 8 G" out[0] [7:0] $end + $var wire 8 H" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub3_2 $end + $var wire 8 d% P0 [7:0] $end + $var wire 32 s% UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 t% UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 g% UNUSED [15:0] $end + $var wire 2 h% ENUM [1:0] $end + $var wire 1 a% clk $end + $var wire 8 k" in [7:0] $end + $var wire 8 n" out [7:0] $end + $var wire 1 9$ ff[0] $end + $var wire 1 :$ ff[1] $end + $var wire 1 ;$ ff[2] $end + $var wire 1 <$ ff[3] $end + $var wire 1 =$ ff[4] $end + $var wire 1 >$ ff[5] $end + $var wire 1 ?$ ff[6] $end + $var wire 1 @$ ff[7] $end + $var wire 8 n" out4 [7:0] $end + $var wire 8 A$ out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 32 i% P0 [31:0] $end + $var real 64 j% P1 $end + $var real 64 l% P3 $end + $var wire 1 a% clk $end + $var wire 8 B$ in [7:0] $end + $var wire 8 n" out [7:0] $end + $var wire 8 n" ff [7:0] $end + $var wire 128 C$ sub5_in[0][0] [127:0] $end + $var wire 128 G$ sub5_in[0][1] [127:0] $end + $var wire 128 K$ sub5_in[0][2] [127:0] $end + $var wire 128 O$ sub5_in[1][0] [127:0] $end + $var wire 128 S$ sub5_in[1][1] [127:0] $end + $var wire 128 W$ sub5_in[1][2] [127:0] $end + $var wire 8 [$ sub5_out[0][0] [7:0] $end + $var wire 8 \$ sub5_out[0][1] [7:0] $end + $var wire 8 ]$ sub5_out[0][2] [7:0] $end + $var wire 8 ^$ sub5_out[1][0] [7:0] $end + $var wire 8 _$ sub5_out[1][1] [7:0] $end + $var wire 8 `$ sub5_out[1][2] [7:0] $end + $var wire 32 a$ count [31:0] $end + $var wire 32 I" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 j% P1 $end + $var wire 32 I" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 a% clk $end + $var wire 128 b$ in[0][0] [127:0] $end + $var wire 128 f$ in[0][1] [127:0] $end + $var wire 128 j$ in[0][2] [127:0] $end + $var wire 128 n$ in[1][0] [127:0] $end + $var wire 128 r$ in[1][1] [127:0] $end + $var wire 128 v$ in[1][2] [127:0] $end + $var wire 8 z$ out[0][0] [7:0] $end + $var wire 8 {$ out[0][1] [7:0] $end + $var wire 8 |$ out[0][2] [7:0] $end + $var wire 8 }$ out[1][0] [7:0] $end + $var wire 8 ~$ out[1][1] [7:0] $end + $var wire 8 !% out[1][2] [7:0] $end + $var wire 32 "% count [31:0] $end + $var wire 8 J" val0[0] [7:0] $end + $var wire 8 K" val0[1] [7:0] $end + $var wire 8 L" val1[0] [7:0] $end + $var wire 8 M" val1[1] [7:0] $end + $var wire 8 N" val2[0] [7:0] $end + $var wire 8 O" val2[1] [7:0] $end + $var wire 8 P" val3[0] [7:0] $end + $var wire 8 Q" val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 R" out[0] [7:0] $end + $var wire 8 S" out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 T" out[0] [7:0] $end + $var wire 8 U" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 V" out[0] [7:0] $end + $var wire 8 W" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 p% P1 [31:0] $end + $var wire 8 X" out[0] [7:0] $end + $var wire 8 Y" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 32 i% P0 [31:0] $end + $var real 64 j% P1 $end + $var real 64 q% P3 $end + $var wire 1 a% clk $end + $var wire 8 B$ in [7:0] $end + $var wire 8 A$ out [7:0] $end + $var wire 8 A$ ff [7:0] $end + $var wire 128 #% sub5_in[0][0] [127:0] $end + $var wire 128 '% sub5_in[0][1] [127:0] $end + $var wire 128 +% sub5_in[0][2] [127:0] $end + $var wire 128 /% sub5_in[1][0] [127:0] $end + $var wire 128 3% sub5_in[1][1] [127:0] $end + $var wire 128 7% sub5_in[1][2] [127:0] $end + $var wire 8 ;% sub5_out[0][0] [7:0] $end + $var wire 8 <% sub5_out[0][1] [7:0] $end + $var wire 8 =% sub5_out[0][2] [7:0] $end + $var wire 8 >% sub5_out[1][0] [7:0] $end + $var wire 8 ?% sub5_out[1][1] [7:0] $end + $var wire 8 @% sub5_out[1][2] [7:0] $end + $var wire 32 A% count [31:0] $end + $var wire 32 Z" driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 j% P1 $end + $var wire 32 Z" driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 a% clk $end + $var wire 128 B% in[0][0] [127:0] $end + $var wire 128 F% in[0][1] [127:0] $end + $var wire 128 J% in[0][2] [127:0] $end + $var wire 128 N% in[1][0] [127:0] $end + $var wire 128 R% in[1][1] [127:0] $end + $var wire 128 V% in[1][2] [127:0] $end + $var wire 8 Z% out[0][0] [7:0] $end + $var wire 8 [% out[0][1] [7:0] $end + $var wire 8 \% out[0][2] [7:0] $end + $var wire 8 ]% out[1][0] [7:0] $end + $var wire 8 ^% out[1][1] [7:0] $end + $var wire 8 _% out[1][2] [7:0] $end + $var wire 32 `% count [31:0] $end + $var wire 8 [" val0[0] [7:0] $end + $var wire 8 \" val0[1] [7:0] $end + $var wire 8 ]" val1[0] [7:0] $end + $var wire 8 ^" val1[1] [7:0] $end + $var wire 8 _" val2[0] [7:0] $end + $var wire 8 `" val2[1] [7:0] $end + $var wire 8 a" val3[0] [7:0] $end + $var wire 8 b" val3[1] [7:0] $end + $scope module i_sub0 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 c" out[0] [7:0] $end + $var wire 8 d" out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 e" out[0] [7:0] $end + $var wire 8 f" out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 o% P1 [31:0] $end + $var wire 8 g" out[0] [7:0] $end + $var wire 8 h" out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 n% P0 [31:0] $end + $var wire 32 p% P1 [31:0] $end + $var wire 8 i" out[0] [7:0] $end + $var wire 8 j" out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module in $end + $var wire 1 a% clk $end + $var wire 8 k" data [7:0] $end + $upscope $end + $scope module out $end + $var wire 1 a% clk $end + $var wire 8 m" data [7:0] $end + $upscope $end + $upscope $end + $scope module in_ifs $end + $var wire 1 a% clk $end + $var wire 8 k" data [7:0] $end + $upscope $end + $scope module out_ifs $end + $var wire 1 a% clk $end + $var wire 8 m" data [7:0] $end + $upscope $end + $upscope $end + $scope module i_sub3 $end + $var wire 8 k! P0 [7:0] $end + $var wire 32 l! UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 m! UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 n! UNUSED [15:0] $end + $var wire 2 o! ENUM [1:0] $end + $var wire 1 d! clk $end + $var wire 8 K! in [7:0] $end + $var wire 8 ?! out [7:0] $end + $var wire 1 @! ff[0] $end + $var wire 1 A! ff[1] $end + $var wire 1 B! ff[2] $end + $var wire 1 C! ff[3] $end + $var wire 1 D! ff[4] $end + $var wire 1 E! ff[5] $end + $var wire 1 F! ff[6] $end + $var wire 1 G! ff[7] $end + $var wire 8 ?! out4 [7:0] $end + $var wire 8 - out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 32 p! P0 [31:0] $end + $var real 64 q! P1 $end + $var real 64 s! P3 $end + $var wire 1 d! clk $end + $var wire 8 H! in [7:0] $end + $var wire 8 ?! out [7:0] $end + $var wire 8 ?! ff [7:0] $end + $var wire 128 . sub5_in[0][0] [127:0] $end + $var wire 128 2 sub5_in[0][1] [127:0] $end + $var wire 128 6 sub5_in[0][2] [127:0] $end + $var wire 128 : sub5_in[1][0] [127:0] $end + $var wire 128 > sub5_in[1][1] [127:0] $end + $var wire 128 B sub5_in[1][2] [127:0] $end + $var wire 8 L! sub5_out[0][0] [7:0] $end + $var wire 8 M! sub5_out[0][1] [7:0] $end + $var wire 8 N! sub5_out[0][2] [7:0] $end + $var wire 8 O! sub5_out[1][0] [7:0] $end + $var wire 8 P! sub5_out[1][1] [7:0] $end + $var wire 8 Q! sub5_out[1][2] [7:0] $end + $var wire 32 F count [31:0] $end + $var wire 32 " driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 q! P1 $end + $var wire 32 " driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 G& clk $end + $var wire 128 (& in[0][0] [127:0] $end + $var wire 128 ,& in[0][1] [127:0] $end + $var wire 128 0& in[0][2] [127:0] $end + $var wire 128 4& in[1][0] [127:0] $end + $var wire 128 8& in[1][1] [127:0] $end + $var wire 128 <& in[1][2] [127:0] $end + $var wire 8 @& out[0][0] [7:0] $end + $var wire 8 A& out[0][1] [7:0] $end + $var wire 8 B& out[0][2] [7:0] $end + $var wire 8 C& out[1][0] [7:0] $end + $var wire 8 D& out[1][1] [7:0] $end + $var wire 8 E& out[1][2] [7:0] $end + $var wire 32 F& count [31:0] $end + $var wire 8 v% val0[0] [7:0] $end + $var wire 8 w% val0[1] [7:0] $end + $var wire 8 x% val1[0] [7:0] $end + $var wire 8 y% val1[1] [7:0] $end + $var wire 8 z% val2[0] [7:0] $end + $var wire 8 {% val2[1] [7:0] $end + $var wire 8 |% val3[0] [7:0] $end + $var wire 8 }% val3[1] [7:0] $end + $scope module $libroot $end + $var wire 1 K& global_flag $end + $upscope $end + $scope module i_sub0 $end + $var wire 32 H& P0 [31:0] $end + $var wire 32 I& P1 [31:0] $end + $var wire 8 ~% out[0] [7:0] $end + $var wire 8 !& out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 H& P0 [31:0] $end + $var wire 32 I& P1 [31:0] $end + $var wire 8 "& out[0] [7:0] $end + $var wire 8 #& out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 H& P0 [31:0] $end + $var wire 32 I& P1 [31:0] $end + $var wire 8 $& out[0] [7:0] $end + $var wire 8 %& out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 H& P0 [31:0] $end + $var wire 32 J& P1 [31:0] $end + $var wire 8 && out[0] [7:0] $end + $var wire 8 '& out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 32 p! P0 [31:0] $end + $var real 64 q! P1 $end + $var real 64 u! P3 $end + $var wire 1 d! clk $end + $var wire 8 H! in [7:0] $end + $var wire 8 - out [7:0] $end + $var wire 8 - ff [7:0] $end + $var wire 128 G sub5_in[0][0] [127:0] $end + $var wire 128 K sub5_in[0][1] [127:0] $end + $var wire 128 O sub5_in[0][2] [127:0] $end + $var wire 128 S sub5_in[1][0] [127:0] $end + $var wire 128 W sub5_in[1][1] [127:0] $end + $var wire 128 [ sub5_in[1][2] [127:0] $end + $var wire 8 R! sub5_out[0][0] [7:0] $end + $var wire 8 S! sub5_out[0][1] [7:0] $end + $var wire 8 T! sub5_out[0][2] [7:0] $end + $var wire 8 U! sub5_out[1][0] [7:0] $end + $var wire 8 V! sub5_out[1][1] [7:0] $end + $var wire 8 W! sub5_out[1][2] [7:0] $end + $var wire 32 _ count [31:0] $end + $var wire 32 # driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 q! P1 $end + $var wire 32 # driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 {& clk $end + $var wire 128 \& in[0][0] [127:0] $end + $var wire 128 `& in[0][1] [127:0] $end + $var wire 128 d& in[0][2] [127:0] $end + $var wire 128 h& in[1][0] [127:0] $end + $var wire 128 l& in[1][1] [127:0] $end + $var wire 128 p& in[1][2] [127:0] $end + $var wire 8 t& out[0][0] [7:0] $end + $var wire 8 u& out[0][1] [7:0] $end + $var wire 8 v& out[0][2] [7:0] $end + $var wire 8 w& out[1][0] [7:0] $end + $var wire 8 x& out[1][1] [7:0] $end + $var wire 8 y& out[1][2] [7:0] $end + $var wire 32 z& count [31:0] $end + $var wire 8 L& val0[0] [7:0] $end + $var wire 8 M& val0[1] [7:0] $end + $var wire 8 N& val1[0] [7:0] $end + $var wire 8 O& val1[1] [7:0] $end + $var wire 8 P& val2[0] [7:0] $end + $var wire 8 Q& val2[1] [7:0] $end + $var wire 8 R& val3[0] [7:0] $end + $var wire 8 S& val3[1] [7:0] $end + $scope module $libroot $end + $var wire 1 !' global_flag $end + $upscope $end + $scope module i_sub0 $end + $var wire 32 |& P0 [31:0] $end + $var wire 32 }& P1 [31:0] $end + $var wire 8 T& out[0] [7:0] $end + $var wire 8 U& out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 |& P0 [31:0] $end + $var wire 32 }& P1 [31:0] $end + $var wire 8 V& out[0] [7:0] $end + $var wire 8 W& out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 |& P0 [31:0] $end + $var wire 32 }& P1 [31:0] $end + $var wire 8 X& out[0] [7:0] $end + $var wire 8 Y& out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 |& P0 [31:0] $end + $var wire 32 ~& P1 [31:0] $end + $var wire 8 Z& out[0] [7:0] $end + $var wire 8 [& out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub3_2 $end + $var wire 8 k! P0 [7:0] $end + $var wire 32 w! UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 x! UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 n! UNUSED [15:0] $end + $var wire 2 o! ENUM [1:0] $end + $var wire 1 d! clk $end + $var wire 8 K! in [7:0] $end + $var wire 8 & out [7:0] $end + $var wire 1 ` ff[0] $end + $var wire 1 a ff[1] $end + $var wire 1 b ff[2] $end + $var wire 1 c ff[3] $end + $var wire 1 d ff[4] $end + $var wire 1 e ff[5] $end + $var wire 1 f ff[6] $end + $var wire 1 g ff[7] $end + $var wire 8 & out4 [7:0] $end + $var wire 8 h out4_2 [7:0] $end + $scope module i_sub4_0 $end + $var wire 32 p! P0 [31:0] $end + $var real 64 q! P1 $end + $var real 64 s! P3 $end + $var wire 1 d! clk $end + $var wire 8 i in [7:0] $end + $var wire 8 & out [7:0] $end + $var wire 8 & ff [7:0] $end + $var wire 128 j sub5_in[0][0] [127:0] $end + $var wire 128 n sub5_in[0][1] [127:0] $end + $var wire 128 r sub5_in[0][2] [127:0] $end + $var wire 128 v sub5_in[1][0] [127:0] $end + $var wire 128 z sub5_in[1][1] [127:0] $end + $var wire 128 ~ sub5_in[1][2] [127:0] $end + $var wire 8 X! sub5_out[0][0] [7:0] $end + $var wire 8 Y! sub5_out[0][1] [7:0] $end + $var wire 8 Z! sub5_out[0][2] [7:0] $end + $var wire 8 [! sub5_out[1][0] [7:0] $end + $var wire 8 \! sub5_out[1][1] [7:0] $end + $var wire 8 ]! sub5_out[1][2] [7:0] $end + $var wire 32 $! count [31:0] $end + $var wire 32 $ driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 q! P1 $end + $var wire 32 $ driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 Q' clk $end + $var wire 128 2' in[0][0] [127:0] $end + $var wire 128 6' in[0][1] [127:0] $end + $var wire 128 :' in[0][2] [127:0] $end + $var wire 128 >' in[1][0] [127:0] $end + $var wire 128 B' in[1][1] [127:0] $end + $var wire 128 F' in[1][2] [127:0] $end + $var wire 8 J' out[0][0] [7:0] $end + $var wire 8 K' out[0][1] [7:0] $end + $var wire 8 L' out[0][2] [7:0] $end + $var wire 8 M' out[1][0] [7:0] $end + $var wire 8 N' out[1][1] [7:0] $end + $var wire 8 O' out[1][2] [7:0] $end + $var wire 32 P' count [31:0] $end + $var wire 8 "' val0[0] [7:0] $end + $var wire 8 #' val0[1] [7:0] $end + $var wire 8 $' val1[0] [7:0] $end + $var wire 8 %' val1[1] [7:0] $end + $var wire 8 &' val2[0] [7:0] $end + $var wire 8 '' val2[1] [7:0] $end + $var wire 8 (' val3[0] [7:0] $end + $var wire 8 )' val3[1] [7:0] $end + $scope module $libroot $end + $var wire 1 U' global_flag $end + $upscope $end + $scope module i_sub0 $end + $var wire 32 R' P0 [31:0] $end + $var wire 32 S' P1 [31:0] $end + $var wire 8 *' out[0] [7:0] $end + $var wire 8 +' out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 R' P0 [31:0] $end + $var wire 32 S' P1 [31:0] $end + $var wire 8 ,' out[0] [7:0] $end + $var wire 8 -' out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 R' P0 [31:0] $end + $var wire 32 S' P1 [31:0] $end + $var wire 8 .' out[0] [7:0] $end + $var wire 8 /' out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 R' P0 [31:0] $end + $var wire 32 T' P1 [31:0] $end + $var wire 8 0' out[0] [7:0] $end + $var wire 8 1' out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module i_sub4_1 $end + $var wire 32 p! P0 [31:0] $end + $var real 64 q! P1 $end + $var real 64 u! P3 $end + $var wire 1 d! clk $end + $var wire 8 i in [7:0] $end + $var wire 8 h out [7:0] $end + $var wire 8 h ff [7:0] $end + $var wire 128 %! sub5_in[0][0] [127:0] $end + $var wire 128 )! sub5_in[0][1] [127:0] $end + $var wire 128 -! sub5_in[0][2] [127:0] $end + $var wire 128 1! sub5_in[1][0] [127:0] $end + $var wire 128 5! sub5_in[1][1] [127:0] $end + $var wire 128 9! sub5_in[1][2] [127:0] $end + $var wire 8 ^! sub5_out[0][0] [7:0] $end + $var wire 8 _! sub5_out[0][1] [7:0] $end + $var wire 8 `! sub5_out[0][2] [7:0] $end + $var wire 8 a! sub5_out[1][0] [7:0] $end + $var wire 8 b! sub5_out[1][1] [7:0] $end + $var wire 8 c! sub5_out[1][2] [7:0] $end + $var wire 32 =! count [31:0] $end + $var wire 32 % driven_from_bind [31:0] $end + $scope module i_sub4_bound $end + $var real 64 q! P1 $end + $var wire 32 % driven_from_bind [31:0] $end + $upscope $end + $scope module i_sub5 $end + $var wire 1 '( clk $end + $var wire 128 f' in[0][0] [127:0] $end + $var wire 128 j' in[0][1] [127:0] $end + $var wire 128 n' in[0][2] [127:0] $end + $var wire 128 r' in[1][0] [127:0] $end + $var wire 128 v' in[1][1] [127:0] $end + $var wire 128 z' in[1][2] [127:0] $end + $var wire 8 ~' out[0][0] [7:0] $end + $var wire 8 !( out[0][1] [7:0] $end + $var wire 8 "( out[0][2] [7:0] $end + $var wire 8 #( out[1][0] [7:0] $end + $var wire 8 $( out[1][1] [7:0] $end + $var wire 8 %( out[1][2] [7:0] $end + $var wire 32 &( count [31:0] $end + $var wire 8 V' val0[0] [7:0] $end + $var wire 8 W' val0[1] [7:0] $end + $var wire 8 X' val1[0] [7:0] $end + $var wire 8 Y' val1[1] [7:0] $end + $var wire 8 Z' val2[0] [7:0] $end + $var wire 8 [' val2[1] [7:0] $end + $var wire 8 \' val3[0] [7:0] $end + $var wire 8 ]' val3[1] [7:0] $end + $scope module $libroot $end + $var wire 1 +( global_flag $end + $upscope $end + $scope module i_sub0 $end + $var wire 32 (( P0 [31:0] $end + $var wire 32 )( P1 [31:0] $end + $var wire 8 ^' out[0] [7:0] $end + $var wire 8 _' out[1] [7:0] $end + $upscope $end + $scope module i_sub1 $end + $var wire 32 (( P0 [31:0] $end + $var wire 32 )( P1 [31:0] $end + $var wire 8 `' out[0] [7:0] $end + $var wire 8 a' out[1] [7:0] $end + $upscope $end + $scope module i_sub2 $end + $var wire 32 (( P0 [31:0] $end + $var wire 32 )( P1 [31:0] $end + $var wire 8 b' out[0] [7:0] $end + $var wire 8 c' out[1] [7:0] $end + $upscope $end + $scope module i_sub3 $end + $var wire 32 (( P0 [31:0] $end + $var wire 32 *( P1 [31:0] $end + $var wire 8 d' out[0] [7:0] $end + $var wire 8 e' out[1] [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000110 " +b00000000000000000000000000000110 # +b00000000000000000000000000000110 $ +b00000000000000000000000000000110 % +b00000000 & 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SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.priority(30) +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +test.compile(verilator_flags2=[ + 't/t_hier_block.cpp', '--Wno-TIMESCALEMOD', '--trace-vcd', '--trace-underscore', + "--trace-max-width", "0", "--trace-max-array", "0", "--trace-structs", "--hierarchical", + "+define+STATEFUL_PKG" +]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_hier_block_type_param.py b/test_regress/t/t_hier_block_type_param.py index 96ef0646c..1032275a2 100755 --- a/test_regress/t/t_hier_block_type_param.py +++ b/test_regress/t/t_hier_block_type_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_type_param.v b/test_regress/t/t_hier_block_type_param.v index 4daffc406..4ccebbd46 100644 --- a/test_regress/t/t_hier_block_type_param.v +++ b/test_regress/t/t_hier_block_type_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t( diff --git a/test_regress/t/t_hier_block_type_param_multiple.py b/test_regress/t/t_hier_block_type_param_multiple.py index a5474d2ec..7db19f9cc 100755 --- a/test_regress/t/t_hier_block_type_param_multiple.py +++ b/test_regress/t/t_hier_block_type_param_multiple.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_type_param_multiple.v b/test_regress/t/t_hier_block_type_param_multiple.v index ca4a82481..70dd8ce43 100644 --- a/test_regress/t/t_hier_block_type_param_multiple.v +++ b/test_regress/t/t_hier_block_type_param_multiple.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t( diff --git a/test_regress/t/t_hier_block_type_param_multiple_instances.py b/test_regress/t/t_hier_block_type_param_multiple_instances.py index a5474d2ec..7db19f9cc 100755 --- a/test_regress/t/t_hier_block_type_param_multiple_instances.py +++ b/test_regress/t/t_hier_block_type_param_multiple_instances.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_type_param_multiple_instances.v b/test_regress/t/t_hier_block_type_param_multiple_instances.v index 0cd6db393..0339769fb 100644 --- a/test_regress/t/t_hier_block_type_param_multiple_instances.v +++ b/test_regress/t/t_hier_block_type_param_multiple_instances.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t( diff --git a/test_regress/t/t_hier_block_type_param_nested.py b/test_regress/t/t_hier_block_type_param_nested.py index a5474d2ec..7db19f9cc 100755 --- a/test_regress/t/t_hier_block_type_param_nested.py +++ b/test_regress/t/t_hier_block_type_param_nested.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_type_param_nested.v b/test_regress/t/t_hier_block_type_param_nested.v index bd8cd0b8b..5d9bbe23c 100644 --- a/test_regress/t/t_hier_block_type_param_nested.v +++ b/test_regress/t/t_hier_block_type_param_nested.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t( diff --git a/test_regress/t/t_hier_block_type_param_notfound_bad.py b/test_regress/t/t_hier_block_type_param_notfound_bad.py index 7eae3e24a..111841bf4 100755 --- a/test_regress/t/t_hier_block_type_param_notfound_bad.py +++ b/test_regress/t/t_hier_block_type_param_notfound_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_type_param_typedef.v b/test_regress/t/t_hier_block_type_param_typedef.v index b956f4c0d..bd43276d2 100644 --- a/test_regress/t/t_hier_block_type_param_typedef.v +++ b/test_regress/t/t_hier_block_type_param_typedef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t( diff --git a/test_regress/t/t_hier_block_typedef_param.py b/test_regress/t/t_hier_block_typedef_param.py index 43ec2591b..234927d29 100755 --- a/test_regress/t/t_hier_block_typedef_param.py +++ b/test_regress/t/t_hier_block_typedef_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_vlt.py b/test_regress/t/t_hier_block_vlt.py index 0d1643704..90f2fdacd 100755 --- a/test_regress/t/t_hier_block_vlt.py +++ b/test_regress/t/t_hier_block_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_block_vlt.vlt b/test_regress/t/t_hier_block_vlt.vlt index 81317810c..54b3167eb 100644 --- a/test_regress/t/t_hier_block_vlt.vlt +++ b/test_regress/t/t_hier_block_vlt.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Yutetsu TAKATSUKASA +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense `verilator_config diff --git a/test_regress/t/t_hier_bynum.py b/test_regress/t/t_hier_bynum.py index c2db19e11..e470c0d7d 100755 --- a/test_regress/t/t_hier_bynum.py +++ b/test_regress/t/t_hier_bynum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_bynum.v b/test_regress/t/t_hier_bynum.v index 78307d98b..aae47ed40 100644 --- a/test_regress/t/t_hier_bynum.v +++ b/test_regress/t/t_hier_bynum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: Unlicense module flop (q, d, clk); diff --git a/test_regress/t/t_hier_parm_under.py b/test_regress/t/t_hier_parm_under.py index 470caf710..e9ae8f7df 100755 --- a/test_regress/t/t_hier_parm_under.py +++ b/test_regress/t/t_hier_parm_under.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_parm_under.v b/test_regress/t/t_hier_parm_under.v index 4d36d0dfb..1a00f844d 100644 --- a/test_regress/t/t_hier_parm_under.v +++ b/test_regress/t/t_hier_parm_under.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub; diff --git a/test_regress/t/t_hier_task.py b/test_regress/t/t_hier_task.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_hier_task.py +++ b/test_regress/t/t_hier_task.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_task.v b/test_regress/t/t_hier_task.v index ec20d1d63..d8a34281d 100644 --- a/test_regress/t/t_hier_task.v +++ b/test_regress/t/t_hier_task.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test for issue #2267 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by James Pallister. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 James Pallister // SPDX-License-Identifier: CC0-1.0 module mod_a; diff --git a/test_regress/t/t_hier_trace.out b/test_regress/t/t_hier_trace.out index 1bb69f35d..8b3e7571f 100644 --- a/test_regress/t/t_hier_trace.out +++ b/test_regress/t/t_hier_trace.out @@ -1,268 +1,124 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end - $var wire 1 # clk $end - $var wire 1 $ reset_l $end + $var wire 1 " clk $end + $var wire 1 # reset_l $end $scope module t $end - $var wire 1 # clk $end - $var wire 1 $ reset_l $end + $var wire 1 " clk $end + $var wire 1 # reset_l $end $scope module u0_sub_top $end - $var wire 1 # clk $end - $var wire 1 $ reset_l $end + $var wire 1 $ clk $end + $var wire 1 % reset_l $end + $scope module u0 $end + $var wire 1 & clk $end + $var wire 1 ' reset_l $end + $upscope $end + $scope module u1 $end + $var wire 1 ( clk $end + $var wire 1 ) reset_l $end + $upscope $end + $scope module u2 $end + $var wire 1 * clk $end + $var wire 1 + reset_l $end + $upscope $end + $scope module u3 $end + $var wire 1 , clk $end + $var wire 1 - reset_l $end + $upscope $end + $scope module u4 $end + $var wire 1 . clk $end + $var wire 1 / reset_l $end + $upscope $end + $scope module u5 $end + $var wire 1 0 clk $end + $var wire 1 1 reset_l $end + $upscope $end + $scope module u6 $end + $var wire 1 2 clk $end + $var wire 1 3 reset_l $end + $upscope $end + $scope module u7 $end + $var wire 1 4 clk $end + $var wire 1 5 reset_l $end + $upscope $end $upscope $end $scope module u1_sub_top $end - $var wire 1 # clk $end - $var wire 1 $ reset_l $end + $var wire 1 6 clk $end + $var wire 1 7 reset_l $end + $scope module u0 $end + $var wire 1 8 clk $end + $var wire 1 9 reset_l $end + $upscope $end + $scope module u1 $end + $var wire 1 : clk $end + $var wire 1 ; reset_l $end + $upscope $end + $scope module u2 $end + $var wire 1 < clk $end + $var wire 1 = reset_l $end + $upscope $end + $scope module u3 $end + $var wire 1 > clk $end + $var wire 1 ? reset_l $end + $upscope $end + $scope module u4 $end + $var wire 1 @ clk $end + $var wire 1 A reset_l $end + $upscope $end + $scope module u5 $end + $var wire 1 B clk $end + $var wire 1 C reset_l $end + $upscope $end + $scope module u6 $end + $var wire 1 D clk $end + $var wire 1 E reset_l $end + $upscope $end + $scope module u7 $end + $var wire 1 F clk $end + $var wire 1 G reset_l $end + $upscope $end $upscope $end $upscope $end $upscope $end - $scope module top.t.u0_sub_top $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $scope module sub_top $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $scope module u0 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u1 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u2 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u3 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u4 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u5 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u6 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u7 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $scope module sub_top $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $scope module u0 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u1 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u2 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u3 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u4 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u5 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u6 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u7 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u0 $end - $var wire 1 , clk $end - $var wire 1 - reset_l $end - $scope module detail_code $end - $var wire 1 , clk $end - $var wire 1 - reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u1 $end - $var wire 1 / clk $end - $var wire 1 0 reset_l $end - $scope module detail_code $end - $var wire 1 / clk $end - $var wire 1 0 reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u2 $end - $var wire 1 2 clk $end - $var wire 1 3 reset_l $end - $scope module detail_code $end - $var wire 1 2 clk $end - $var wire 1 3 reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u3 $end - $var wire 1 5 clk $end - $var wire 1 6 reset_l $end - $scope module detail_code $end - $var wire 1 5 clk $end - $var wire 1 6 reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u4 $end - $var wire 1 8 clk $end - $var wire 1 9 reset_l $end - $scope module detail_code $end - $var wire 1 8 clk $end - $var wire 1 9 reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u5 $end - $var wire 1 ; clk $end - $var wire 1 < reset_l $end - $scope module detail_code $end - $var wire 1 ; clk $end - $var wire 1 < reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u6 $end - $var wire 1 > clk $end - $var wire 1 ? reset_l $end - $scope module detail_code $end - $var wire 1 > clk $end - $var wire 1 ? reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u7 $end - $var wire 1 A clk $end - $var wire 1 B reset_l $end - $scope module detail_code $end - $var wire 1 A clk $end - $var wire 1 B reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u0 $end - $var wire 1 D clk $end - $var wire 1 E reset_l $end - $scope module detail_code $end - $var wire 1 D clk $end - $var wire 1 E reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u1 $end - $var wire 1 G clk $end - $var wire 1 H reset_l $end - $scope module detail_code $end - $var wire 1 G clk $end - $var wire 1 H reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u2 $end - $var wire 1 J clk $end - $var wire 1 K reset_l $end - $scope module detail_code $end - $var wire 1 J clk $end - $var wire 1 K reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u3 $end - $var wire 1 M clk $end - $var wire 1 N reset_l $end - $scope module detail_code $end - $var wire 1 M clk $end - $var wire 1 N reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u4 $end - $var wire 1 P clk $end - $var wire 1 Q reset_l $end - $scope module detail_code $end - $var wire 1 P clk $end - $var wire 1 Q reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u5 $end - $var wire 1 S clk $end - $var wire 1 T reset_l $end - $scope module detail_code $end - $var wire 1 S clk $end - $var wire 1 T reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u6 $end - $var wire 1 V clk $end - $var wire 1 W reset_l $end - $scope module detail_code $end - $var wire 1 V clk $end - $var wire 1 W reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u7 $end - $var wire 1 Y clk $end - $var wire 1 Z reset_l $end - $scope module detail_code $end - $var wire 1 Y clk $end - $var wire 1 Z reset_l $end - $upscope $end - $upscope $end $enddefinitions $end #0 +0" 0# 0$ +0% +06 +07 0& 0' +0( 0) 0* +0+ 0, 0- +0. 0/ 00 +01 02 03 +04 05 -06 08 09 +0: 0; 0< +0= 0> 0? +0@ 0A 0B +0C 0D 0E +0F 0G -0H -0J -0K -0M -0N -0P -0Q -0S -0T -0V -0W -0Y -0Z diff --git a/test_regress/t/t_hier_trace.py b/test_regress/t/t_hier_trace.py index 9f6d83866..a8d887dae 100755 --- a/test_regress/t/t_hier_trace.py +++ b/test_regress/t/t_hier_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_trace.v b/test_regress/t/t_hier_trace.v index d8d492912..0c67b41a3 100644 --- a/test_regress/t/t_hier_trace.v +++ b/test_regress/t/t_hier_trace.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t( diff --git a/test_regress/t/t_hier_trace_noinl.out b/test_regress/t/t_hier_trace_noinl.out index 1bb69f35d..8b3e7571f 100644 --- a/test_regress/t/t_hier_trace_noinl.out +++ b/test_regress/t/t_hier_trace_noinl.out @@ -1,268 +1,124 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end - $var wire 1 # clk $end - $var wire 1 $ reset_l $end + $var wire 1 " clk $end + $var wire 1 # reset_l $end $scope module t $end - $var wire 1 # clk $end - $var wire 1 $ reset_l $end + $var wire 1 " clk $end + $var wire 1 # reset_l $end $scope module u0_sub_top $end - $var wire 1 # clk $end - $var wire 1 $ reset_l $end + $var wire 1 $ clk $end + $var wire 1 % reset_l $end + $scope module u0 $end + $var wire 1 & clk $end + $var wire 1 ' reset_l $end + $upscope $end + $scope module u1 $end + $var wire 1 ( clk $end + $var wire 1 ) reset_l $end + $upscope $end + $scope module u2 $end + $var wire 1 * clk $end + $var wire 1 + reset_l $end + $upscope $end + $scope module u3 $end + $var wire 1 , clk $end + $var wire 1 - reset_l $end + $upscope $end + $scope module u4 $end + $var wire 1 . clk $end + $var wire 1 / reset_l $end + $upscope $end + $scope module u5 $end + $var wire 1 0 clk $end + $var wire 1 1 reset_l $end + $upscope $end + $scope module u6 $end + $var wire 1 2 clk $end + $var wire 1 3 reset_l $end + $upscope $end + $scope module u7 $end + $var wire 1 4 clk $end + $var wire 1 5 reset_l $end + $upscope $end $upscope $end $scope module u1_sub_top $end - $var wire 1 # clk $end - $var wire 1 $ reset_l $end + $var wire 1 6 clk $end + $var wire 1 7 reset_l $end + $scope module u0 $end + $var wire 1 8 clk $end + $var wire 1 9 reset_l $end + $upscope $end + $scope module u1 $end + $var wire 1 : clk $end + $var wire 1 ; reset_l $end + $upscope $end + $scope module u2 $end + $var wire 1 < clk $end + $var wire 1 = reset_l $end + $upscope $end + $scope module u3 $end + $var wire 1 > clk $end + $var wire 1 ? reset_l $end + $upscope $end + $scope module u4 $end + $var wire 1 @ clk $end + $var wire 1 A reset_l $end + $upscope $end + $scope module u5 $end + $var wire 1 B clk $end + $var wire 1 C reset_l $end + $upscope $end + $scope module u6 $end + $var wire 1 D clk $end + $var wire 1 E reset_l $end + $upscope $end + $scope module u7 $end + $var wire 1 F clk $end + $var wire 1 G reset_l $end + $upscope $end $upscope $end $upscope $end $upscope $end - $scope module top.t.u0_sub_top $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $scope module sub_top $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $scope module u0 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u1 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u2 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u3 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u4 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u5 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u6 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $scope module u7 $end - $var wire 1 & clk $end - $var wire 1 ' reset_l $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $scope module sub_top $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $scope module u0 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u1 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u2 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u3 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u4 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u5 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u6 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $scope module u7 $end - $var wire 1 ) clk $end - $var wire 1 * reset_l $end - $upscope $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u0 $end - $var wire 1 , clk $end - $var wire 1 - reset_l $end - $scope module detail_code $end - $var wire 1 , clk $end - $var wire 1 - reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u1 $end - $var wire 1 / clk $end - $var wire 1 0 reset_l $end - $scope module detail_code $end - $var wire 1 / clk $end - $var wire 1 0 reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u2 $end - $var wire 1 2 clk $end - $var wire 1 3 reset_l $end - $scope module detail_code $end - $var wire 1 2 clk $end - $var wire 1 3 reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u3 $end - $var wire 1 5 clk $end - $var wire 1 6 reset_l $end - $scope module detail_code $end - $var wire 1 5 clk $end - $var wire 1 6 reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u4 $end - $var wire 1 8 clk $end - $var wire 1 9 reset_l $end - $scope module detail_code $end - $var wire 1 8 clk $end - $var wire 1 9 reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u5 $end - $var wire 1 ; clk $end - $var wire 1 < reset_l $end - $scope module detail_code $end - $var wire 1 ; clk $end - $var wire 1 < reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u6 $end - $var wire 1 > clk $end - $var wire 1 ? reset_l $end - $scope module detail_code $end - $var wire 1 > clk $end - $var wire 1 ? reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u0_sub_top.sub_top.u7 $end - $var wire 1 A clk $end - $var wire 1 B reset_l $end - $scope module detail_code $end - $var wire 1 A clk $end - $var wire 1 B reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u0 $end - $var wire 1 D clk $end - $var wire 1 E reset_l $end - $scope module detail_code $end - $var wire 1 D clk $end - $var wire 1 E reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u1 $end - $var wire 1 G clk $end - $var wire 1 H reset_l $end - $scope module detail_code $end - $var wire 1 G clk $end - $var wire 1 H reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u2 $end - $var wire 1 J clk $end - $var wire 1 K reset_l $end - $scope module detail_code $end - $var wire 1 J clk $end - $var wire 1 K reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u3 $end - $var wire 1 M clk $end - $var wire 1 N reset_l $end - $scope module detail_code $end - $var wire 1 M clk $end - $var wire 1 N reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u4 $end - $var wire 1 P clk $end - $var wire 1 Q reset_l $end - $scope module detail_code $end - $var wire 1 P clk $end - $var wire 1 Q reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u5 $end - $var wire 1 S clk $end - $var wire 1 T reset_l $end - $scope module detail_code $end - $var wire 1 S clk $end - $var wire 1 T reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u6 $end - $var wire 1 V clk $end - $var wire 1 W reset_l $end - $scope module detail_code $end - $var wire 1 V clk $end - $var wire 1 W reset_l $end - $upscope $end - $upscope $end - $scope module top.t.u1_sub_top.sub_top.u7 $end - $var wire 1 Y clk $end - $var wire 1 Z reset_l $end - $scope module detail_code $end - $var wire 1 Y clk $end - $var wire 1 Z reset_l $end - $upscope $end - $upscope $end $enddefinitions $end #0 +0" 0# 0$ +0% +06 +07 0& 0' +0( 0) 0* +0+ 0, 0- +0. 0/ 00 +01 02 03 +04 05 -06 08 09 +0: 0; 0< +0= 0> 0? +0@ 0A 0B +0C 0D 0E +0F 0G -0H -0J -0K -0M -0N -0P -0Q -0S -0T -0V -0W -0Y -0Z diff --git a/test_regress/t/t_hier_trace_noinl.py b/test_regress/t/t_hier_trace_noinl.py index 2a1b1b27b..eb440b805 100755 --- a/test_regress/t/t_hier_trace_noinl.py +++ b/test_regress/t/t_hier_trace_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hier_trace_sub/sub.vc b/test_regress/t/t_hier_trace_sub/sub.vc index ec34d8efe..59df44421 100644 --- a/test_regress/t/t_hier_trace_sub/sub.vc +++ b/test_regress/t/t_hier_trace_sub/sub.vc @@ -1,7 +1,7 @@ -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 t_hier_trace_sub.v diff --git a/test_regress/t/t_hier_trace_sub/t_hier_trace.vlt b/test_regress/t/t_hier_trace_sub/t_hier_trace.vlt index bfd0e7a0d..4aa047d33 100644 --- a/test_regress/t/t_hier_trace_sub/t_hier_trace.vlt +++ b/test_regress/t/t_hier_trace_sub/t_hier_trace.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_hier_trace_sub/t_hier_trace_sub.v b/test_regress/t/t_hier_trace_sub/t_hier_trace_sub.v index 564e375d7..a73317bcc 100644 --- a/test_regress/t/t_hier_trace_sub/t_hier_trace_sub.v +++ b/test_regress/t/t_hier_trace_sub/t_hier_trace_sub.v @@ -1,48 +1,50 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module detail_code( +module detail_code ( input clk, - input reset_l); + input reset_l +); endmodule -module sub_top( +module sub_top ( input clk, - input reset_l); + input reset_l +); - detail_code u0( - .clk(clk), - .reset_l(reset_l) - ); - detail_code u1( - .clk(clk), - .reset_l(reset_l) - ); - detail_code u2( - .clk(clk), - .reset_l(reset_l) - ); - detail_code u3( - .clk(clk), - .reset_l(reset_l) - ); - detail_code u4( - .clk(clk), - .reset_l(reset_l) - ); - detail_code u5( - .clk(clk), - .reset_l(reset_l) - ); - detail_code u6( - .clk(clk), - .reset_l(reset_l) - ); - detail_code u7( - .clk(clk), - .reset_l(reset_l) - ); + detail_code u0 ( + .clk(clk), + .reset_l(reset_l) + ); + detail_code u1 ( + .clk(clk), + .reset_l(reset_l) + ); + detail_code u2 ( + .clk(clk), + .reset_l(reset_l) + ); + detail_code u3 ( + .clk(clk), + .reset_l(reset_l) + ); + detail_code u4 ( + .clk(clk), + .reset_l(reset_l) + ); + detail_code u5 ( + .clk(clk), + .reset_l(reset_l) + ); + detail_code u6 ( + .clk(clk), + .reset_l(reset_l) + ); + detail_code u7 ( + .clk(clk), + .reset_l(reset_l) + ); endmodule diff --git a/test_regress/t/t_hier_trace_sub/top.vc b/test_regress/t/t_hier_trace_sub/top.vc index 022e6f949..a42f30e65 100644 --- a/test_regress/t/t_hier_trace_sub/top.vc +++ b/test_regress/t/t_hier_trace_sub/top.vc @@ -1,7 +1,7 @@ -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -F sub.vc diff --git a/test_regress/t/t_hierarchy_identifier.py b/test_regress/t/t_hierarchy_identifier.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_hierarchy_identifier.py +++ b/test_regress/t/t_hierarchy_identifier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hierarchy_identifier.v b/test_regress/t/t_hierarchy_identifier.v index 88586661c..6c65f48a0 100644 --- a/test_regress/t/t_hierarchy_identifier.v +++ b/test_regress/t/t_hierarchy_identifier.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_hierarchy_identifier_bad.py b/test_regress/t/t_hierarchy_identifier_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_hierarchy_identifier_bad.py +++ b/test_regress/t/t_hierarchy_identifier_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hierarchy_identifier_bad.v b/test_regress/t/t_hierarchy_identifier_bad.v index c94d393e3..a92a70a28 100644 --- a/test_regress/t/t_hierarchy_identifier_bad.v +++ b/test_regress/t/t_hierarchy_identifier_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_hierarchy_unnamed.py b/test_regress/t/t_hierarchy_unnamed.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_hierarchy_unnamed.py +++ b/test_regress/t/t_hierarchy_unnamed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_hierarchy_unnamed.v b/test_regress/t/t_hierarchy_unnamed.v index a4c82b403..e4540759f 100644 --- a/test_regress/t/t_hierarchy_unnamed.v +++ b/test_regress/t/t_hierarchy_unnamed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Chandan Egbert. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Chandan Egbert // SPDX-License-Identifier: CC0-1.0 module sub(); diff --git a/test_regress/t/t_if_deep.py b/test_regress/t/t_if_deep.py index 539f320b1..84c09a3bb 100755 --- a/test_regress/t/t_if_deep.py +++ b/test_regress/t/t_if_deep.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_if_deep.v b/test_regress/t/t_if_deep.v index 26c8a4641..9276b73d0 100644 --- a/test_regress/t/t_if_deep.v +++ b/test_regress/t/t_if_deep.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_if_same_bad.py b/test_regress/t/t_if_same_bad.py index f206d9126..5fc1c82aa 100755 --- a/test_regress/t/t_if_same_bad.py +++ b/test_regress/t/t_if_same_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_if_same_bad.v b/test_regress/t/t_if_same_bad.v index 276664e07..0f04bbf3f 100644 --- a/test_regress/t/t_if_same_bad.v +++ b/test_regress/t/t_if_same_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug3806 diff --git a/test_regress/t/t_if_swap.py b/test_regress/t/t_if_swap.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_if_swap.py +++ b/test_regress/t/t_if_swap.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_if_swap.v b/test_regress/t/t_if_swap.v index 2dc1ef29d..a70708911 100644 --- a/test_regress/t/t_if_swap.v +++ b/test_regress/t/t_if_swap.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_iface_param_class_typedef.py b/test_regress/t/t_iface_param_class_typedef.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_iface_param_class_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_iface_param_class_typedef.v b/test_regress/t/t_iface_param_class_typedef.v new file mode 100644 index 000000000..da30b0b1e --- /dev/null +++ b/test_regress/t/t_iface_param_class_typedef.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// Test that parameterized class typedefs work as interface type parameters +// See issue #6983 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +class flux_st #( + parameter int WIDTH = 32 +); + typedef struct packed {logic [WIDTH-1:0] data;} pld_t; +endclass + +interface flux_if #( + parameter type PLD_T = logic +); + logic rdy; + logic vld; + PLD_T pld; + modport drive(input rdy, output vld, output pld); + modport sink(output rdy, input vld, input pld); +endinterface + +module t; + // Test using parameterized class typedef as interface type parameter + flux_if #(flux_st #(64)::pld_t) w_flux_st (); + + initial begin + `checkd($bits(w_flux_st.pld), 64); + w_flux_st.pld.data = 64'hDEADBEEF_CAFEBABE; + `checkd(w_flux_st.pld.data, 64'hDEADBEEF_CAFEBABE); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_iff.py b/test_regress/t/t_iff.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_iff.py +++ b/test_regress/t/t_iff.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_iff.v b/test_regress/t/t_iff.v index f7c72197c..4beb3f525 100644 --- a/test_regress/t/t_iff.v +++ b/test_regress/t/t_iff.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_implements.py b/test_regress/t/t_implements.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_implements.py +++ b/test_regress/t/t_implements.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements.v b/test_regress/t/t_implements.v index f4f07c56d..1aef26518 100644 --- a/test_regress/t/t_implements.v +++ b/test_regress/t/t_implements.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface class Icempty; diff --git a/test_regress/t/t_implements_collision.py b/test_regress/t/t_implements_collision.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_implements_collision.py +++ b/test_regress/t/t_implements_collision.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_collision.v b/test_regress/t/t_implements_collision.v index b8929a2ce..df5ca2c92 100644 --- a/test_regress/t/t_implements_collision.v +++ b/test_regress/t/t_implements_collision.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface class Icls1; diff --git a/test_regress/t/t_implements_collision_bad.py b/test_regress/t/t_implements_collision_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_implements_collision_bad.py +++ b/test_regress/t/t_implements_collision_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_collision_bad.v b/test_regress/t/t_implements_collision_bad.v index c45f9967c..488095e10 100644 --- a/test_regress/t/t_implements_collision_bad.v +++ b/test_regress/t/t_implements_collision_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface class Icls1; diff --git a/test_regress/t/t_implements_contents_bad.py b/test_regress/t/t_implements_contents_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_implements_contents_bad.py +++ b/test_regress/t/t_implements_contents_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_contents_bad.v b/test_regress/t/t_implements_contents_bad.v index 3931423e8..5f8531096 100644 --- a/test_regress/t/t_implements_contents_bad.v +++ b/test_regress/t/t_implements_contents_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface class Icls; diff --git a/test_regress/t/t_implements_missing_bad.py b/test_regress/t/t_implements_missing_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_implements_missing_bad.py +++ b/test_regress/t/t_implements_missing_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_missing_bad.v b/test_regress/t/t_implements_missing_bad.v index b15e4ba9f..0ee7e3e18 100644 --- a/test_regress/t/t_implements_missing_bad.v +++ b/test_regress/t/t_implements_missing_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface class Icls1; diff --git a/test_regress/t/t_implements_nested.py b/test_regress/t/t_implements_nested.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_implements_nested.py +++ b/test_regress/t/t_implements_nested.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_nested.v b/test_regress/t/t_implements_nested.v index b02b2684f..21934507c 100644 --- a/test_regress/t/t_implements_nested.v +++ b/test_regress/t/t_implements_nested.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 Antmicro. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_implements_nested_bad.py b/test_regress/t/t_implements_nested_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_implements_nested_bad.py +++ b/test_regress/t/t_implements_nested_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_nested_bad.v b/test_regress/t/t_implements_nested_bad.v index b2ee8ef0f..d82713e4e 100644 --- a/test_regress/t/t_implements_nested_bad.v +++ b/test_regress/t/t_implements_nested_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_implements_new_bad.py b/test_regress/t/t_implements_new_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_implements_new_bad.py +++ b/test_regress/t/t_implements_new_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_new_bad.v b/test_regress/t/t_implements_new_bad.v index 00c1a22a6..e98806a88 100644 --- a/test_regress/t/t_implements_new_bad.v +++ b/test_regress/t/t_implements_new_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface class Icls; diff --git a/test_regress/t/t_implements_noinherit_bad.py b/test_regress/t/t_implements_noinherit_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_implements_noinherit_bad.py +++ b/test_regress/t/t_implements_noinherit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_noinherit_bad.v b/test_regress/t/t_implements_noinherit_bad.v index 2ab770043..8142b021c 100644 --- a/test_regress/t/t_implements_noinherit_bad.v +++ b/test_regress/t/t_implements_noinherit_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface class Icls; diff --git a/test_regress/t/t_implements_noninterface_bad.py b/test_regress/t/t_implements_noninterface_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_implements_noninterface_bad.py +++ b/test_regress/t/t_implements_noninterface_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_noninterface_bad.v b/test_regress/t/t_implements_noninterface_bad.v index 72a37e765..ca4753d6b 100644 --- a/test_regress/t/t_implements_noninterface_bad.v +++ b/test_regress/t/t_implements_noninterface_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class NotIcls; diff --git a/test_regress/t/t_implements_not_nested.py b/test_regress/t/t_implements_not_nested.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_implements_not_nested.py +++ b/test_regress/t/t_implements_not_nested.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_not_nested.v b/test_regress/t/t_implements_not_nested.v index c4089662b..1e5f1826a 100644 --- a/test_regress/t/t_implements_not_nested.v +++ b/test_regress/t/t_implements_not_nested.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package ipkg; diff --git a/test_regress/t/t_implements_notfound_bad.py b/test_regress/t/t_implements_notfound_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_implements_notfound_bad.py +++ b/test_regress/t/t_implements_notfound_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_notfound_bad.v b/test_regress/t/t_implements_notfound_bad.v index 605a8db5d..668934c31 100644 --- a/test_regress/t/t_implements_notfound_bad.v +++ b/test_regress/t/t_implements_notfound_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class ClsI implements Inotfound; diff --git a/test_regress/t/t_implements_typed.py b/test_regress/t/t_implements_typed.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_implements_typed.py +++ b/test_regress/t/t_implements_typed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_implements_typed.v b/test_regress/t/t_implements_typed.v index ce733d0fc..70bff2b88 100644 --- a/test_regress/t/t_implements_typed.v +++ b/test_regress/t/t_implements_typed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface class Icls; diff --git a/test_regress/t/t_impure_cond_empty_if.py b/test_regress/t/t_impure_cond_empty_if.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_impure_cond_empty_if.py +++ b/test_regress/t/t_impure_cond_empty_if.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_impure_cond_empty_if.v b/test_regress/t/t_impure_cond_empty_if.v index 6cf409ea6..2569422ba 100644 --- a/test_regress/t/t_impure_cond_empty_if.v +++ b/test_regress/t/t_impure_cond_empty_if.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class uvm_component; diff --git a/test_regress/t/t_inc_relink.py b/test_regress/t/t_inc_relink.py index 754bdeefc..0655dc089 100755 --- a/test_regress/t/t_inc_relink.py +++ b/test_regress/t/t_inc_relink.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inc_relink.v b/test_regress/t/t_inc_relink.v index 089f1cf34..8089b1049 100644 --- a/test_regress/t/t_inc_relink.v +++ b/test_regress/t/t_inc_relink.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 // Test if temporary vars are relinked if not used directly under FTASK. diff --git a/test_regress/t/t_incorrect_multi_driven.py b/test_regress/t/t_incorrect_multi_driven.py index f51428711..0d2c50fcf 100755 --- a/test_regress/t/t_incorrect_multi_driven.py +++ b/test_regress/t/t_incorrect_multi_driven.py @@ -2,10 +2,10 @@ # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_incorrect_multi_driven.v b/test_regress/t/t_incorrect_multi_driven.v index 3020398db..4efd5b0ab 100644 --- a/test_regress/t/t_incorrect_multi_driven.v +++ b/test_regress/t/t_incorrect_multi_driven.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Adrien Le Masle. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Adrien Le Masle // SPDX-License-Identifier: CC0-1.0 interface test_if #(parameter int AA = 2, BB=5); diff --git a/test_regress/t/t_incr_void.py b/test_regress/t/t_incr_void.py index 487255781..c6cfafd7b 100755 --- a/test_regress/t/t_incr_void.py +++ b/test_regress/t/t_incr_void.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_incr_void.v b/test_regress/t/t_incr_void.v index 75284fcd7..bc58fdd41 100644 --- a/test_regress/t/t_incr_void.v +++ b/test_regress/t/t_incr_void.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Drew Ranck. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Drew Ranck // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_increment_bad.py b/test_regress/t/t_increment_bad.py index 07fc79e8e..3160d0589 100755 --- a/test_regress/t/t_increment_bad.py +++ b/test_regress/t/t_increment_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_increment_bad.v b/test_regress/t/t_increment_bad.v index 11c031177..d0006a4a1 100644 --- a/test_regress/t/t_increment_bad.v +++ b/test_regress/t/t_increment_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_infinite_recursion.py b/test_regress/t/t_infinite_recursion.py index d789a829e..30b3e1786 100755 --- a/test_regress/t/t_infinite_recursion.py +++ b/test_regress/t/t_infinite_recursion.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_infinite_recursion.v b/test_regress/t/t_infinite_recursion.v index 9bacc5bd2..377b5e1d9 100644 --- a/test_regress/t/t_infinite_recursion.v +++ b/test_regress/t/t_infinite_recursion.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class cls; diff --git a/test_regress/t/t_init_array_bad.out b/test_regress/t/t_init_array_bad.out new file mode 100644 index 000000000..539750145 --- /dev/null +++ b/test_regress/t/t_init_array_bad.out @@ -0,0 +1,5 @@ +%Error: t/t_init_array_bad.v:8:33: Array initialization has too few elements, need element 2 + 8 | bit [7:0] r[3] = {{8'h1, 8'h2}, 8'h5}; + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_init_array_bad.py b/test_regress/t/t_init_array_bad.py new file mode 100755 index 000000000..dd0d7c389 --- /dev/null +++ b/test_regress/t/t_init_array_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, v_flags2=['-Wno-WIDTHTRUNC'], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_init_array_bad.v b/test_regress/t/t_init_array_bad.v new file mode 100644 index 000000000..71ded6bfe --- /dev/null +++ b/test_regress/t/t_init_array_bad.v @@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + bit [7:0] r[3] = {{8'h1, 8'h2}, 8'h5}; + initial $finish; +endmodule diff --git a/test_regress/t/t_init_concat.py b/test_regress/t/t_init_concat.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_init_concat.py +++ b/test_regress/t/t_init_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_init_concat.v b/test_regress/t/t_init_concat.v index 163502fb8..9672a1c3b 100644 --- a/test_regress/t/t_init_concat.v +++ b/test_regress/t/t_init_concat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_initarray_nonarray.py b/test_regress/t/t_initarray_nonarray.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_initarray_nonarray.py +++ b/test_regress/t/t_initarray_nonarray.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_initarray_nonarray.v b/test_regress/t/t_initarray_nonarray.v index 71da30cfc..799a881c0 100644 --- a/test_regress/t/t_initarray_nonarray.v +++ b/test_regress/t/t_initarray_nonarray.v @@ -3,8 +3,8 @@ // The code here is used to trigger Verilator internal error // "InitArray on non-array" // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Jie Xu // SPDX-License-Identifier: CC0-1.0 typedef logic [7:0] mask_t [7:0]; diff --git a/test_regress/t/t_initial.py b/test_regress/t/t_initial.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_initial.py +++ b/test_regress/t/t_initial.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_initial.v b/test_regress/t/t_initial.v index 203ed4503..a5cdf46ab 100644 --- a/test_regress/t/t_initial.v +++ b/test_regress/t/t_initial.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_initial_assign_sformatf.py b/test_regress/t/t_initial_assign_sformatf.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_initial_assign_sformatf.py +++ b/test_regress/t/t_initial_assign_sformatf.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_initial_assign_sformatf.v b/test_regress/t/t_initial_assign_sformatf.v index 7ff94eaba..2a66dfc71 100644 --- a/test_regress/t/t_initial_assign_sformatf.v +++ b/test_regress/t/t_initial_assign_sformatf.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog interface test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 interface intf(); diff --git a/test_regress/t/t_initial_assign_sformatf_debug.py b/test_regress/t/t_initial_assign_sformatf_debug.py index 4679bcd8c..6070a7a0e 100755 --- a/test_regress/t/t_initial_assign_sformatf_debug.py +++ b/test_regress/t/t_initial_assign_sformatf_debug.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_initial_delay_assign.py b/test_regress/t/t_initial_delay_assign.py new file mode 100755 index 000000000..b7cce95a7 --- /dev/null +++ b/test_regress/t/t_initial_delay_assign.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios("simulator_st") + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +test.execute(all_run_flags=["+verilator+rand+reset+0"]) +test.execute(all_run_flags=["+verilator+rand+reset+1"]) +for seed in range(1, 5): + test.execute(all_run_flags=["+verilator+rand+reset+2", f"+verilator+seed+{seed}"]) + +test.passes() diff --git a/test_regress/t/t_initial_delay_assign.v b/test_regress/t/t_initial_delay_assign.v new file mode 100644 index 000000000..a5eaec7e6 --- /dev/null +++ b/test_regress/t/t_initial_delay_assign.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +`define DELAY_INIT_CHECK(foo, bar) \ + assign #1 bar = foo; \ +\ + always @(foo, bar) begin \ + $display("%d foo %x, bar %x", $time, foo, bar); \ + end \ +\ + initial begin \ + #5; \ + if (bar != foo) $stop; \ + #5 foo = ~foo; \ + #5; \ + if (bar != foo) $stop; \ + #5 foo = ~foo; \ + #5; \ + if (bar != foo) $stop; \ + end \ + + +module t (); + reg foo1; + wire bar1; + initial foo1 = '0; + `DELAY_INIT_CHECK(foo1, bar1) + + reg foo2 = '0; + wire bar2; + `DELAY_INIT_CHECK(foo2, bar2) + + reg foo3 = '0; + reg bar3 = '1; + `DELAY_INIT_CHECK(foo3, bar3) + + initial begin + #30; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_initial_dlyass.py b/test_regress/t/t_initial_dlyass.py index 49c67d3a1..99d3b795b 100755 --- a/test_regress/t/t_initial_dlyass.py +++ b/test_regress/t/t_initial_dlyass.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_initial_dlyass.v b/test_regress/t/t_initial_dlyass.v index 5e86b628c..d5cd6d36d 100644 --- a/test_regress/t/t_initial_dlyass.v +++ b/test_regress/t/t_initial_dlyass.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_initial_dlyass_bad.py b/test_regress/t/t_initial_dlyass_bad.py index 883aebe62..f8feb4a77 100755 --- a/test_regress/t/t_initial_dlyass_bad.py +++ b/test_regress/t/t_initial_dlyass_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_initial_edge.py b/test_regress/t/t_initial_edge.py index 989bc8776..8f376addf 100755 --- a/test_regress/t/t_initial_edge.py +++ b/test_regress/t/t_initial_edge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_initial_edge.v b/test_regress/t/t_initial_edge.v index 954ac7240..4c755755a 100644 --- a/test_regress/t/t_initial_edge.v +++ b/test_regress/t/t_initial_edge.v @@ -19,8 +19,8 @@ // thus matching the behaviour of a 4-state simulator. This is reportedly also // the behaviour of commercial cycle accurate modelling tools as well. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns diff --git a/test_regress/t/t_initial_edge_bad.py b/test_regress/t/t_initial_edge_bad.py index 2182cc77c..b929b7b19 100755 --- a/test_regress/t/t_initial_edge_bad.py +++ b/test_regress/t/t_initial_edge_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This works with other vlt_alls, we we don't run it for them. It should diff --git a/test_regress/t/t_initial_inc.vh b/test_regress/t/t_initial_inc.vh index 503776881..3e52492c1 100644 --- a/test_regress/t/t_initial_inc.vh +++ b/test_regress/t/t_initial_inc.vh @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define foo bar diff --git a/test_regress/t/t_initialstatic_circ.py b/test_regress/t/t_initialstatic_circ.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_initialstatic_circ.py +++ b/test_regress/t/t_initialstatic_circ.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_initialstatic_circ.v b/test_regress/t/t_initialstatic_circ.v index 31325cad5..62d07401c 100644 --- a/test_regress/t/t_initialstatic_circ.v +++ b/test_regress/t/t_initialstatic_circ.v @@ -1,7 +1,7 @@ // DESCRIPTION::Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_inline_varxref_inlineddots.py b/test_regress/t/t_inline_varxref_inlineddots.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_inline_varxref_inlineddots.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inline_varxref_inlineddots.v b/test_regress/t/t_inline_varxref_inlineddots.v new file mode 100644 index 000000000..425cb5d08 --- /dev/null +++ b/test_regress/t/t_inline_varxref_inlineddots.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: VarXRef inlinedDots propagation regression +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +module src #( + parameter [3:0] VAL = 4'h0 +) ( + output logic [3:0] val +); + /*verilator no_inline_module*/ + assign val = VAL; +endmodule + +module inner ( + input logic [3:0] in, + output logic [3:0] out +); + /*verilator inline_module*/ + assign out = in; +endmodule + +module outer #( + parameter [3:0] VAL = 4'h0 +) ( + output logic [3:0] out +); + /*verilator inline_module*/ + logic [3:0] s_val; + src #(.VAL(VAL)) s (.val(s_val)); + // Use hierarchical ref s.val (not s_val) to test inlinedDots propagation + inner u ( + .in(s.val), + .out(out) + ); +endmodule + +module t; + logic [3:0] out0; + logic [3:0] out1; + logic [3:0] unused; + + // Top-level instance with the same name as the inlined one. + src #(.VAL(4'hF)) s (.val(unused)); + + outer #(.VAL(4'h1)) o0 (.out(out0)); + outer #(.VAL(4'h2)) o1 (.out(out1)); + + initial begin + if (out0 !== 4'h1) $stop; + if (out1 !== 4'h2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_inside.py b/test_regress/t/t_inside.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inside.py +++ b/test_regress/t/t_inside.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside.v b/test_regress/t/t_inside.v index a832823d5..669e8b4d2 100644 --- a/test_regress/t/t_inside.v +++ b/test_regress/t/t_inside.v @@ -1,7 +1,7 @@ // DESCRIPTION::Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_inside2.py b/test_regress/t/t_inside2.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_inside2.py +++ b/test_regress/t/t_inside2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside2.v b/test_regress/t/t_inside2.v index 4cea304f6..0dfb5935e 100644 --- a/test_regress/t/t_inside2.v +++ b/test_regress/t/t_inside2.v @@ -1,7 +1,7 @@ // DESCRIPTION::Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_inside3.py b/test_regress/t/t_inside3.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_inside3.py +++ b/test_regress/t/t_inside3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside3.v b/test_regress/t/t_inside3.v index c90662d3b..0629c8bb1 100644 --- a/test_regress/t/t_inside3.v +++ b/test_regress/t/t_inside3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_inside_assoc_unsup.py b/test_regress/t/t_inside_assoc_unsup.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inside_assoc_unsup.py +++ b/test_regress/t/t_inside_assoc_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside_assoc_unsup.v b/test_regress/t/t_inside_assoc_unsup.v index 2b85a11f5..3df80d6ee 100644 --- a/test_regress/t/t_inside_assoc_unsup.v +++ b/test_regress/t/t_inside_assoc_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inside_dyn.py b/test_regress/t/t_inside_dyn.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inside_dyn.py +++ b/test_regress/t/t_inside_dyn.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside_dyn.v b/test_regress/t/t_inside_dyn.v index cf0a0d9c2..7d64598ca 100644 --- a/test_regress/t/t_inside_dyn.v +++ b/test_regress/t/t_inside_dyn.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inside_extend.py b/test_regress/t/t_inside_extend.py index 78d425f95..35bc0fd0e 100755 --- a/test_regress/t/t_inside_extend.py +++ b/test_regress/t/t_inside_extend.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside_extend.v b/test_regress/t/t_inside_extend.v index df754b3fc..4b80e1654 100644 --- a/test_regress/t/t_inside_extend.v +++ b/test_regress/t/t_inside_extend.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 typedef enum bit [4:0] {V0 = 1} my_enum; @@ -10,12 +10,13 @@ class Cls; endclass module t; - initial begin - Cls c = new; - int i = 0; - if (i inside {c.sp}) $stop; + initial begin + Cls c; + int i; + c = new; + if (i inside {c.sp}) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_inside_impure_unsized.py b/test_regress/t/t_inside_impure_unsized.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_inside_impure_unsized.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inside_impure_unsized.v b/test_regress/t/t_inside_impure_unsized.v new file mode 100644 index 000000000..dfaa27593 --- /dev/null +++ b/test_regress/t/t_inside_impure_unsized.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +module t; + bit [7:0] str_arr[string]; + string str_key; + + bit [7:0] int_arr[int]; + int int_key; + + int counter = 0; + function bit [7:0] get_val(); + counter++; + return 25; + endfunction + + initial begin + str_arr["test"] = 25; + str_key = "test"; + if (!(str_arr[str_key] inside {[10 : 50]})) $stop; + if (str_arr[str_key] inside {[100 : 200]}) $stop; + + int_arr[0] = 25; + int_key = 0; + if (!(int_arr[int_key] inside {[10 : 50]})) $stop; + if (int_arr[int_key] inside {[100 : 200]}) $stop; + + if (!(get_val() inside {[10 : 50]})) $stop; + if (get_val() inside {[100 : 200]}) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_inside_nonint.py b/test_regress/t/t_inside_nonint.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inside_nonint.py +++ b/test_regress/t/t_inside_nonint.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside_nonint.v b/test_regress/t/t_inside_nonint.v index 90f5cecce..b37e7675a 100644 --- a/test_regress/t/t_inside_nonint.v +++ b/test_regress/t/t_inside_nonint.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 function bit check_string(string s); diff --git a/test_regress/t/t_inside_queue_elem.py b/test_regress/t/t_inside_queue_elem.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inside_queue_elem.py +++ b/test_regress/t/t_inside_queue_elem.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside_queue_elem.v b/test_regress/t/t_inside_queue_elem.v index 782514ee1..c0fcad54b 100644 --- a/test_regress/t/t_inside_queue_elem.v +++ b/test_regress/t/t_inside_queue_elem.v @@ -1,13 +1,14 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; initial begin - int q[$] = {1, 2}; + automatic int q[$] = {1, 2}; + if (!(1 inside {q[0], q[1]})) $stop; if (3 inside {q[0], q[1]}) $stop; diff --git a/test_regress/t/t_inside_tolerance_unsup.py b/test_regress/t/t_inside_tolerance_unsup.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inside_tolerance_unsup.py +++ b/test_regress/t/t_inside_tolerance_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside_tolerance_unsup.v b/test_regress/t/t_inside_tolerance_unsup.v index 60cdf5b97..e0e853412 100644 --- a/test_regress/t/t_inside_tolerance_unsup.v +++ b/test_regress/t/t_inside_tolerance_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_inside_unbounded.py b/test_regress/t/t_inside_unbounded.py new file mode 100755 index 000000000..4aff8b3e0 --- /dev/null +++ b/test_regress/t/t_inside_unbounded.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() +test.execute() +test.passes() diff --git a/test_regress/t/t_inside_unbounded.v b/test_regress/t/t_inside_unbounded.v new file mode 100644 index 000000000..1357f9dee --- /dev/null +++ b/test_regress/t/t_inside_unbounded.v @@ -0,0 +1,80 @@ +// DESCRIPTION: Verilator: Test for unbounded '$' in inside range +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wei-Lun Chiu +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + int value; + + // Test [$:100] - should match minimum to 100 + value = 50; + if (!(value inside {[$ : 100]})) $stop; + + value = 100; + if (!(value inside {[$ : 100]})) $stop; + + value = 101; + if (value inside {[$ : 100]}) $stop; // Should NOT match + + // Test [0:$] - should match 0 to maximum + value = 50; + if (!(value inside {[0 : $]})) $stop; + + value = 0; + if (!(value inside {[0 : $]})) $stop; + + // Test [100:$] - should match 100 to maximum + value = 100; + if (!(value inside {[100 : $]})) $stop; + + value = 200; + if (!(value inside {[100 : $]})) $stop; + + value = 50; + if (value inside {[100 : $]}) $stop; // Should NOT match + + // Test mixed with other ranges + value = 5; + if (!(value inside {[$ : 10], [90 : $]})) $stop; + + value = 95; + if (!(value inside {[$ : 10], [90 : $]})) $stop; + + value = 50; + if (value inside {[$ : 10], [90 : $]}) $stop; // Should NOT match + + // Test with function + if (!(get_value(50) inside {[$ : 100]})) $stop; + if (!(get_value(50) inside {[0 : $]})) $stop; + if (get_value(50) inside {[100 : $]}) $stop; // Should NOT match + + // Test with increment + value = 49; + if (!(++value inside {[$ : 100]})) $stop; // value becomes 50 + if (value != 50) $stop; + + value = -1; + if (!(++value inside {[0 : $]})) $stop; // value becomes 0 + if (value != 0) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + + function int get_value(int v); + return v; + endfunction + + // Use volatile-like behavior to prevent compile-time optimization + int runtime_val; + function int get_runtime_value(int v); +`ifdef VERILATOR + runtime_val = $c32(v); +`else + runtime_val = v; +`endif + return runtime_val; + endfunction +endmodule diff --git a/test_regress/t/t_inside_unbounded_both.py b/test_regress/t/t_inside_unbounded_both.py new file mode 100755 index 000000000..ae5c2b502 --- /dev/null +++ b/test_regress/t/t_inside_unbounded_both.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=['-Wno-INSIDETRUE']) +test.execute() +test.passes() diff --git a/test_regress/t/t_inside_unbounded_both.v b/test_regress/t/t_inside_unbounded_both.v new file mode 100644 index 000000000..b50e9ed60 --- /dev/null +++ b/test_regress/t/t_inside_unbounded_both.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Test for [$:$] with warning suppressed +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + int value; + value = 50; + // [$:$] is always true - warning suppressed with -Wno-INSIDETRUE + if (!(value inside {[$ : $]})) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_inside_unbounded_both_bad.out b/test_regress/t/t_inside_unbounded_both_bad.out new file mode 100644 index 000000000..17e45e396 --- /dev/null +++ b/test_regress/t/t_inside_unbounded_both_bad.out @@ -0,0 +1,6 @@ +%Warning-INSIDETRUE: t/t_inside_unbounded_both.v:12:25: Unbounded on both sides of inside range [$:$] is always true + 12 | if (!(value inside {[$ : $]})) $stop; + | ^ + ... For warning description see https://verilator.org/warn/INSIDETRUE?v=latest + ... Use "/* verilator lint_off INSIDETRUE */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_inside_unbounded_both_bad.py b/test_regress/t/t_inside_unbounded_both_bad.py new file mode 100755 index 000000000..5d8273f11 --- /dev/null +++ b/test_regress/t/t_inside_unbounded_both_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = 't/t_inside_unbounded_both.v' + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inside_unpacked.py b/test_regress/t/t_inside_unpacked.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inside_unpacked.py +++ b/test_regress/t/t_inside_unpacked.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside_unpacked.v b/test_regress/t/t_inside_unpacked.v index a3d203674..9b44fa588 100644 --- a/test_regress/t/t_inside_unpacked.v +++ b/test_regress/t/t_inside_unpacked.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_inside_unpacked_param.py b/test_regress/t/t_inside_unpacked_param.py index 966dc53da..20b96a7d7 100755 --- a/test_regress/t/t_inside_unpacked_param.py +++ b/test_regress/t/t_inside_unpacked_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside_unpacked_param.v b/test_regress/t/t_inside_unpacked_param.v index 10f227af8..2c159825c 100644 --- a/test_regress/t/t_inside_unpacked_param.v +++ b/test_regress/t/t_inside_unpacked_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inside_wild.py b/test_regress/t/t_inside_wild.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inside_wild.py +++ b/test_regress/t/t_inside_wild.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inside_wild.v b/test_regress/t/t_inside_wild.v index 86b9cc060..49ebd4cc3 100644 --- a/test_regress/t/t_inside_wild.v +++ b/test_regress/t/t_inside_wild.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_2star_bad.py b/test_regress/t/t_inst_2star_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_2star_bad.py +++ b/test_regress/t/t_inst_2star_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_2star_bad.v b/test_regress/t/t_inst_2star_bad.v index ccf3e4990..60ab2694c 100644 --- a/test_regress/t/t_inst_2star_bad.v +++ b/test_regress/t/t_inst_2star_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_array.v b/test_regress/t/t_inst_array.v index 130970ba3..f4f363b25 100644 --- a/test_regress/t/t_inst_array.v +++ b/test_regress/t/t_inst_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_array_bad.py b/test_regress/t/t_inst_array_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_array_bad.py +++ b/test_regress/t/t_inst_array_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_array_bad.v b/test_regress/t/t_inst_array_bad.v index f156c68bf..86d3b223d 100644 --- a/test_regress/t/t_inst_array_bad.v +++ b/test_regress/t/t_inst_array_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_array_connect.py b/test_regress/t/t_inst_array_connect.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_array_connect.py +++ b/test_regress/t/t_inst_array_connect.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_array_connect.v b/test_regress/t/t_inst_array_connect.v index af08f7c30..644eca973 100644 --- a/test_regress/t/t_inst_array_connect.v +++ b/test_regress/t/t_inst_array_connect.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for Issue#1631 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Julien Margetts. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Julien Margetts // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_array_inl0.py b/test_regress/t/t_inst_array_inl0.py index 38c939c11..85188349b 100755 --- a/test_regress/t/t_inst_array_inl0.py +++ b/test_regress/t/t_inst_array_inl0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_array_inl1.py b/test_regress/t/t_inst_array_inl1.py index 588df37a9..ba989a59a 100755 --- a/test_regress/t/t_inst_array_inl1.py +++ b/test_regress/t/t_inst_array_inl1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_array_partial.py b/test_regress/t/t_inst_array_partial.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_array_partial.py +++ b/test_regress/t/t_inst_array_partial.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_array_partial.v b/test_regress/t/t_inst_array_partial.v index 2470c714c..e8b3d8a3b 100644 --- a/test_regress/t/t_inst_array_partial.v +++ b/test_regress/t/t_inst_array_partial.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_array_slice.py b/test_regress/t/t_inst_array_slice.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_inst_array_slice.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_inst_array_slice.v b/test_regress/t/t_inst_array_slice.v new file mode 100644 index 000000000..6dfbf7d3d --- /dev/null +++ b/test_regress/t/t_inst_array_slice.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t; + localparam int unsigned LARGE_ARRAY[5] = '{1, 2, 3, 4, 5}; + localparam int unsigned SMALL_ARRAY[2] = LARGE_ARRAY[1+:2]; + sub #(.VAL(SMALL_ARRAY)) u_sub (); +endmodule + +module sub #( + parameter int unsigned VAL[2] = '{1, 2} +) (); + initial begin + `checkd(VAL[0], 2); + `checkd(VAL[1], 3); + $finish; + end +endmodule diff --git a/test_regress/t/t_inst_array_struct.py b/test_regress/t/t_inst_array_struct.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_array_struct.py +++ b/test_regress/t/t_inst_array_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_array_struct.v b/test_regress/t/t_inst_array_struct.v index 35831162e..ca3713a9d 100644 --- a/test_regress/t/t_inst_array_struct.v +++ b/test_regress/t/t_inst_array_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_inst_ccall.py b/test_regress/t/t_inst_ccall.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_ccall.py +++ b/test_regress/t/t_inst_ccall.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_ccall.v b/test_regress/t/t_inst_ccall.v index 63c48d8c9..7fa14463f 100644 --- a/test_regress/t/t_inst_ccall.v +++ b/test_regress/t/t_inst_ccall.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_comma.v b/test_regress/t/t_inst_comma.v index 974bbff71..62d9bede4 100644 --- a/test_regress/t/t_inst_comma.v +++ b/test_regress/t/t_inst_comma.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_comma_inl0.py b/test_regress/t/t_inst_comma_inl0.py index 03cf930d4..1f7b491cc 100755 --- a/test_regress/t/t_inst_comma_inl0.py +++ b/test_regress/t/t_inst_comma_inl0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_comma_inl1.py b/test_regress/t/t_inst_comma_inl1.py index 02a41e5a1..f60677020 100755 --- a/test_regress/t/t_inst_comma_inl1.py +++ b/test_regress/t/t_inst_comma_inl1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_darray.py b/test_regress/t/t_inst_darray.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_darray.py +++ b/test_regress/t/t_inst_darray.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_darray.v b/test_regress/t/t_inst_darray.v index 11e46dfe4..a9ff0dc52 100644 --- a/test_regress/t/t_inst_darray.v +++ b/test_regress/t/t_inst_darray.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by John Stevenson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 John Stevenson // SPDX-License-Identifier: CC0-1.0 typedef logic [63:0] uid_t; diff --git a/test_regress/t/t_inst_dearray_slice.py b/test_regress/t/t_inst_dearray_slice.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_dearray_slice.py +++ b/test_regress/t/t_inst_dearray_slice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dearray_slice.v b/test_regress/t/t_inst_dearray_slice.v index 1cc17c8cb..eea55deb1 100644 --- a/test_regress/t/t_inst_dearray_slice.v +++ b/test_regress/t/t_inst_dearray_slice.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by engr248. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2020 engr248 // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_inst_dff.py b/test_regress/t/t_inst_dff.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_dff.py +++ b/test_regress/t/t_inst_dff.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dff.v b/test_regress/t/t_inst_dff.v index 028a55fdb..31b11af42 100644 --- a/test_regress/t/t_inst_dff.v +++ b/test_regress/t/t_inst_dff.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_dtree.v b/test_regress/t/t_inst_dtree.v index 8870c6a66..09b6eec73 100644 --- a/test_regress/t/t_inst_dtree.v +++ b/test_regress/t/t_inst_dtree.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_dtree_inla.py b/test_regress/t/t_inst_dtree_inla.py index 0c74e5b29..0fefe30b4 100755 --- a/test_regress/t/t_inst_dtree_inla.py +++ b/test_regress/t/t_inst_dtree_inla.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dtree_inlab.py b/test_regress/t/t_inst_dtree_inlab.py index 2e47b5491..f8bf9dd65 100755 --- a/test_regress/t/t_inst_dtree_inlab.py +++ b/test_regress/t/t_inst_dtree_inlab.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dtree_inlac.py b/test_regress/t/t_inst_dtree_inlac.py index af4e087f5..e2fb8968e 100755 --- a/test_regress/t/t_inst_dtree_inlac.py +++ b/test_regress/t/t_inst_dtree_inlac.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dtree_inlad.py b/test_regress/t/t_inst_dtree_inlad.py index f8d8a945a..8d971d735 100755 --- a/test_regress/t/t_inst_dtree_inlad.py +++ b/test_regress/t/t_inst_dtree_inlad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dtree_inlb.py b/test_regress/t/t_inst_dtree_inlb.py index ff392eb7a..17a89f51a 100755 --- a/test_regress/t/t_inst_dtree_inlb.py +++ b/test_regress/t/t_inst_dtree_inlb.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dtree_inlbc.py b/test_regress/t/t_inst_dtree_inlbc.py index 2bf440d42..ca5ef6efd 100755 --- a/test_regress/t/t_inst_dtree_inlbc.py +++ b/test_regress/t/t_inst_dtree_inlbc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dtree_inlbd.py b/test_regress/t/t_inst_dtree_inlbd.py index 9b9abcd5c..62fd8abca 100755 --- a/test_regress/t/t_inst_dtree_inlbd.py +++ b/test_regress/t/t_inst_dtree_inlbd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dtree_inlc.py b/test_regress/t/t_inst_dtree_inlc.py index 3310eff69..7855e8c2c 100755 --- a/test_regress/t/t_inst_dtree_inlc.py +++ b/test_regress/t/t_inst_dtree_inlc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dtree_inlcd.py b/test_regress/t/t_inst_dtree_inlcd.py index 2ba7663b0..412add88d 100755 --- a/test_regress/t/t_inst_dtree_inlcd.py +++ b/test_regress/t/t_inst_dtree_inlcd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_dtree_inld.py b/test_regress/t/t_inst_dtree_inld.py index 304292305..4671a1bf7 100755 --- a/test_regress/t/t_inst_dtree_inld.py +++ b/test_regress/t/t_inst_dtree_inld.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_first.py b/test_regress/t/t_inst_first.py index a06492309..c996a862c 100755 --- a/test_regress/t/t_inst_first.py +++ b/test_regress/t/t_inst_first.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_first.v b/test_regress/t/t_inst_first.v index 05b876188..668e52ab7 100644 --- a/test_regress/t/t_inst_first.v +++ b/test_regress/t/t_inst_first.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_first_a.v b/test_regress/t/t_inst_first_a.v index f347aff35..61ccda166 100644 --- a/test_regress/t/t_inst_first_a.v +++ b/test_regress/t/t_inst_first_a.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_inst_first_a (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_first_b.v b/test_regress/t/t_inst_first_b.v index ce2515ee0..eaf5be6f1 100644 --- a/test_regress/t/t_inst_first_b.v +++ b/test_regress/t/t_inst_first_b.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_inst_first_b (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_implicit.py b/test_regress/t/t_inst_implicit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_implicit.py +++ b/test_regress/t/t_inst_implicit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_implicit.v b/test_regress/t/t_inst_implicit.v index 53c205fad..9357b9953 100644 --- a/test_regress/t/t_inst_implicit.v +++ b/test_regress/t/t_inst_implicit.v @@ -1,7 +1,7 @@ // DESCRIPTION:tor:ilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_long.py b/test_regress/t/t_inst_long.py index a34888c88..1718b115c 100755 --- a/test_regress/t/t_inst_long.py +++ b/test_regress/t/t_inst_long.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_long_bad.py b/test_regress/t/t_inst_long_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_long_bad.py +++ b/test_regress/t/t_inst_long_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_long_bad.v b/test_regress/t/t_inst_long_bad.v index 5340a983a..e956762cc 100644 --- a/test_regress/t/t_inst_long_bad.v +++ b/test_regress/t/t_inst_long_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_misarray2_bad.py b/test_regress/t/t_inst_misarray2_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_misarray2_bad.py +++ b/test_regress/t/t_inst_misarray2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_misarray2_bad.v b/test_regress/t/t_inst_misarray2_bad.v index 863762523..a7c608085 100644 --- a/test_regress/t/t_inst_misarray2_bad.v +++ b/test_regress/t/t_inst_misarray2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_misarray_bad.py b/test_regress/t/t_inst_misarray_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_misarray_bad.py +++ b/test_regress/t/t_inst_misarray_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_misarray_bad.v b/test_regress/t/t_inst_misarray_bad.v index ab99ad05b..83a5f3696 100644 --- a/test_regress/t/t_inst_misarray_bad.v +++ b/test_regress/t/t_inst_misarray_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_mism.py b/test_regress/t/t_inst_mism.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_mism.py +++ b/test_regress/t/t_inst_mism.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_mism.v b/test_regress/t/t_inst_mism.v index 03c98e56d..b6dadb322 100644 --- a/test_regress/t/t_inst_mism.v +++ b/test_regress/t/t_inst_mism.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Alex Solomatnikov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 //bug595 diff --git a/test_regress/t/t_inst_missing.py b/test_regress/t/t_inst_missing.py index 7fd4e37fd..ece1a4910 100755 --- a/test_regress/t/t_inst_missing.py +++ b/test_regress/t/t_inst_missing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_missing.v b/test_regress/t/t_inst_missing.v index fcd25cd16..690094f73 100644 --- a/test_regress/t/t_inst_missing.v +++ b/test_regress/t/t_inst_missing.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_missing_bad.py b/test_regress/t/t_inst_missing_bad.py index 8641f823f..b11fa7cea 100755 --- a/test_regress/t/t_inst_missing_bad.py +++ b/test_regress/t/t_inst_missing_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_missing_bad.v b/test_regress/t/t_inst_missing_bad.v index 91408c57f..c41d7acc7 100644 --- a/test_regress/t/t_inst_missing_bad.v +++ b/test_regress/t/t_inst_missing_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_missing_dot_bad.py b/test_regress/t/t_inst_missing_dot_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_missing_dot_bad.py +++ b/test_regress/t/t_inst_missing_dot_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_missing_dot_bad.v b/test_regress/t/t_inst_missing_dot_bad.v index e2570bd5f..e6c026735 100644 --- a/test_regress/t/t_inst_missing_dot_bad.v +++ b/test_regress/t/t_inst_missing_dot_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_mnpipe.py b/test_regress/t/t_inst_mnpipe.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_mnpipe.py +++ b/test_regress/t/t_inst_mnpipe.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_mnpipe.v b/test_regress/t/t_inst_mnpipe.v index e97c4e9fd..290bbc7ff 100644 --- a/test_regress/t/t_inst_mnpipe.v +++ b/test_regress/t/t_inst_mnpipe.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_name_long.py b/test_regress/t/t_inst_name_long.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_inst_name_long.py +++ b/test_regress/t/t_inst_name_long.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_name_long.v b/test_regress/t/t_inst_name_long.v index 964ca30dd..5d1595cc5 100644 --- a/test_regress/t/t_inst_name_long.v +++ b/test_regress/t/t_inst_name_long.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off PINMISSING diff --git a/test_regress/t/t_inst_nansi.py b/test_regress/t/t_inst_nansi.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_inst_nansi.py +++ b/test_regress/t/t_inst_nansi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_nansi.v b/test_regress/t/t_inst_nansi.v index 370d31894..f5937318c 100644 --- a/test_regress/t/t_inst_nansi.v +++ b/test_regress/t/t_inst_nansi.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(b, si, i, li, w3, w4); diff --git a/test_regress/t/t_inst_nansi_dup_bad.py b/test_regress/t/t_inst_nansi_dup_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_inst_nansi_dup_bad.py +++ b/test_regress/t/t_inst_nansi_dup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_nansi_dup_bad.v b/test_regress/t/t_inst_nansi_dup_bad.v index 386b23154..fe0161f26 100644 --- a/test_regress/t/t_inst_nansi_dup_bad.v +++ b/test_regress/t/t_inst_nansi_dup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef int T; diff --git a/test_regress/t/t_inst_nansi_mism_bad.py b/test_regress/t/t_inst_nansi_mism_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_inst_nansi_mism_bad.py +++ b/test_regress/t/t_inst_nansi_mism_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_nansi_mism_bad.v b/test_regress/t/t_inst_nansi_mism_bad.v index d5fbb4f8f..38f8d8895 100644 --- a/test_regress/t/t_inst_nansi_mism_bad.v +++ b/test_regress/t/t_inst_nansi_mism_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef int T; diff --git a/test_regress/t/t_inst_nansi_param.py b/test_regress/t/t_inst_nansi_param.py index f2f5d0201..fab28cddd 100755 --- a/test_regress/t/t_inst_nansi_param.py +++ b/test_regress/t/t_inst_nansi_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_nansi_param.v b/test_regress/t/t_inst_nansi_param.v index 52cf4c164..c1b28d41f 100644 --- a/test_regress/t/t_inst_nansi_param.v +++ b/test_regress/t/t_inst_nansi_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub ( diff --git a/test_regress/t/t_inst_noname_bad.py b/test_regress/t/t_inst_noname_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_noname_bad.py +++ b/test_regress/t/t_inst_noname_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_noname_bad.v b/test_regress/t/t_inst_noname_bad.v index ca179b788..58a88b137 100644 --- a/test_regress/t/t_inst_noname_bad.v +++ b/test_regress/t/t_inst_noname_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_notunsized.py b/test_regress/t/t_inst_notunsized.py index 46c86aaf4..762a53022 100755 --- a/test_regress/t/t_inst_notunsized.py +++ b/test_regress/t/t_inst_notunsized.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_notunsized.v b/test_regress/t/t_inst_notunsized.v index ced84654d..781f63914 100644 --- a/test_regress/t/t_inst_notunsized.v +++ b/test_regress/t/t_inst_notunsized.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_overwide.py b/test_regress/t/t_inst_overwide.py index 9acf5a62b..018361beb 100755 --- a/test_regress/t/t_inst_overwide.py +++ b/test_regress/t/t_inst_overwide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_overwide.v b/test_regress/t/t_inst_overwide.v index 5c5d365f3..accae8d68 100644 --- a/test_regress/t/t_inst_overwide.v +++ b/test_regress/t/t_inst_overwide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_overwide_bad.py b/test_regress/t/t_inst_overwide_bad.py index 3133e885c..56722b4f7 100755 --- a/test_regress/t/t_inst_overwide_bad.py +++ b/test_regress/t/t_inst_overwide_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_param_comma_bad.py b/test_regress/t/t_inst_param_comma_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_param_comma_bad.py +++ b/test_regress/t/t_inst_param_comma_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_param_comma_bad.v b/test_regress/t/t_inst_param_comma_bad.v index 08bb665b0..3adb791d7 100644 --- a/test_regress/t/t_inst_param_comma_bad.v +++ b/test_regress/t/t_inst_param_comma_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module M #( diff --git a/test_regress/t/t_inst_param_override_bad.py b/test_regress/t/t_inst_param_override_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_param_override_bad.py +++ b/test_regress/t/t_inst_param_override_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_param_override_bad.v b/test_regress/t/t_inst_param_override_bad.v index 8ac842b23..1ecc33c89 100644 --- a/test_regress/t/t_inst_param_override_bad.v +++ b/test_regress/t/t_inst_param_override_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 module sub(); diff --git a/test_regress/t/t_inst_paren_bad.py b/test_regress/t/t_inst_paren_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_paren_bad.py +++ b/test_regress/t/t_inst_paren_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_paren_bad.v b/test_regress/t/t_inst_paren_bad.v index 86e5b6181..f3974d5e3 100644 --- a/test_regress/t/t_inst_paren_bad.v +++ b/test_regress/t/t_inst_paren_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub; diff --git a/test_regress/t/t_inst_pin_place_bad.py b/test_regress/t/t_inst_pin_place_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_pin_place_bad.py +++ b/test_regress/t/t_inst_pin_place_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_pin_place_bad.v b/test_regress/t/t_inst_pin_place_bad.v index cac3e4f4c..a93d2202b 100644 --- a/test_regress/t/t_inst_pin_place_bad.v +++ b/test_regress/t/t_inst_pin_place_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 module sub # ( diff --git a/test_regress/t/t_inst_pin_realnreal.py b/test_regress/t/t_inst_pin_realnreal.py index 966dc53da..20b96a7d7 100755 --- a/test_regress/t/t_inst_pin_realnreal.py +++ b/test_regress/t/t_inst_pin_realnreal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_pin_realnreal.v b/test_regress/t/t_inst_pin_realnreal.v index 5c5539661..84a9df30f 100644 --- a/test_regress/t/t_inst_pin_realnreal.v +++ b/test_regress/t/t_inst_pin_realnreal.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Peter Monsson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Peter Monsson // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_port_array.py b/test_regress/t/t_inst_port_array.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_port_array.py +++ b/test_regress/t/t_inst_port_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_port_array.v b/test_regress/t/t_inst_port_array.v index ef5071f58..a4d2b7f7e 100644 --- a/test_regress/t/t_inst_port_array.v +++ b/test_regress/t/t_inst_port_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Alex Solomatnikov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_port_complex_unsup.out b/test_regress/t/t_inst_port_complex_unsup.out new file mode 100644 index 000000000..e2f245c5f --- /dev/null +++ b/test_regress/t/t_inst_port_complex_unsup.out @@ -0,0 +1,47 @@ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:9:9: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 9 | input .ai_rename(ai), .bi_rename(b), + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:9:26: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 9 | input .ai_rename(ai), .bi_rename(b), + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:10:15: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 10 | output wire .ao_rename(ao), .bo_rename(bo) + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:10:32: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 10 | output wire .ao_rename(ao), .bo_rename(bo) + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:17:3: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 17 | .ai_rename(ai), .bi_rename(bi), + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:17:19: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 17 | .ai_rename(ai), .bi_rename(bi), + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:18:3: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 18 | .ao_rename(ao), .bo_rename(bo) + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:18:19: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 18 | .ao_rename(ao), .bo_rename(bo) + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:30:9: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 30 | input .ci_30(ci[3:0]), .ci_74(ci[7:4]), + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:30:26: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 30 | input .ci_30(ci[3:0]), .ci_74(ci[7:4]), + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:31:15: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 31 | output wire .co_30(co[3:0]), .co_74(co[7:4]) + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:31:33: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 31 | output wire .co_30(co[3:0]), .co_74(co[7:4]) + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:56:3: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 56 | .abi({ai, bi}), + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:57:3: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 57 | .abo({ao, bo}) + | ^ +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:70:30: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) + 70 | module nansi_mixed_direction(.aio({ai, ao})); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_inst_port_complex_unsup.py b/test_regress/t/t_inst_port_complex_unsup.py new file mode 100755 index 000000000..344a4e20a --- /dev/null +++ b/test_regress/t/t_inst_port_complex_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_inst_port_complex_unsup.v b/test_regress/t/t_inst_port_complex_unsup.v new file mode 100644 index 000000000..d1b2ed754 --- /dev/null +++ b/test_regress/t/t_inst_port_complex_unsup.v @@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// No simulator supporting this was found +module ansi_rename ( + input .ai_rename(ai), .bi_rename(b), + output wire .ao_rename(ao), .bo_rename(bo) +); + assign ao = ai; + assign bo = bi; +endmodule + +module nansi_rename ( + .ai_rename(ai), .bi_rename(bi), + .ao_rename(ao), .bo_rename(bo) +); + input ai; + input bi; + output ao; + output bo; + assign ao = ai; + assign bo = bi; +endmodule + +// No simulator supporting this was found +module ansi_split ( + input .ci_30(ci[3:0]), .ci_74(ci[7:4]), + output wire .co_30(co[3:0]), .co_74(co[7:4]) +); + assign co = ci; +endmodule + +module nansi_split ( + ci[3:0], ci[7:4], + co[3:0], co[7:4] +); + input [7:0] ci; + output [7:0] co; + assign co = ci; +endmodule + +module nansi_concat ( + {ai, bi}, + {ao, bo} +); + input [1:0] ai, bi; + output [1:0] ao, bo; + assign ao = ai; + assign bo = bi; +endmodule + +module nansi_concat_named ( + .abi({ai, bi}), + .abo({ao, bo}) +); + input [1:0] ai, bi; + output [1:0] ao, bo; + assign ao = ai; + assign bo = bi; +endmodule + +module nansi_same_input(aa, aa); + input aa; +endmodule + +// Some simulators don't support aggregated ports with different directions +module nansi_mixed_direction(.aio({ai, ao})); + input ai; + output ao; +endmodule + +module t; + // TODO make self checking + initial $finish; +endmodule diff --git a/test_regress/t/t_inst_prepost.py b/test_regress/t/t_inst_prepost.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_inst_prepost.py +++ b/test_regress/t/t_inst_prepost.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_prepost.v b/test_regress/t/t_inst_prepost.v index 2d50acb37..4eb33ec17 100644 --- a/test_regress/t/t_inst_prepost.v +++ b/test_regress/t/t_inst_prepost.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_public.py b/test_regress/t/t_inst_public.py index c4062aa79..17e8338f3 100755 --- a/test_regress/t/t_inst_public.py +++ b/test_regress/t/t_inst_public.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_public.v b/test_regress/t/t_inst_public.v index 7dec1c060..f426e170b 100644 --- a/test_regress/t/t_inst_public.v +++ b/test_regress/t/t_inst_public.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_recurse2_bad.py b/test_regress/t/t_inst_recurse2_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_recurse2_bad.py +++ b/test_regress/t/t_inst_recurse2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_recurse2_bad.v b/test_regress/t/t_inst_recurse2_bad.v index abf4dbf8f..5e1725f7d 100644 --- a/test_regress/t/t_inst_recurse2_bad.v +++ b/test_regress/t/t_inst_recurse2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_recurse_bad.py b/test_regress/t/t_inst_recurse_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_inst_recurse_bad.py +++ b/test_regress/t/t_inst_recurse_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_recurse_bad.v b/test_regress/t/t_inst_recurse_bad.v index 400bb1be9..d963cfb3b 100644 --- a/test_regress/t/t_inst_recurse_bad.v +++ b/test_regress/t/t_inst_recurse_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inst_signed.py b/test_regress/t/t_inst_signed.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_signed.py +++ b/test_regress/t/t_inst_signed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_signed.v b/test_regress/t/t_inst_signed.v index 8fbdc0adc..b79b1542f 100644 --- a/test_regress/t/t_inst_signed.v +++ b/test_regress/t/t_inst_signed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_signed1.py b/test_regress/t/t_inst_signed1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_signed1.py +++ b/test_regress/t/t_inst_signed1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_signed1.v b/test_regress/t/t_inst_signed1.v index 34cdaf2fc..27a9b5393 100644 --- a/test_regress/t/t_inst_signed1.v +++ b/test_regress/t/t_inst_signed1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_slice.py b/test_regress/t/t_inst_slice.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_slice.py +++ b/test_regress/t/t_inst_slice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_slice.v b/test_regress/t/t_inst_slice.v index 2ce445b74..3391b870d 100644 --- a/test_regress/t/t_inst_slice.v +++ b/test_regress/t/t_inst_slice.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Varun Koyyalagunta. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 // bug1015 diff --git a/test_regress/t/t_inst_slice_noinl.py b/test_regress/t/t_inst_slice_noinl.py index bd7bcdff5..88ff3e6f7 100755 --- a/test_regress/t/t_inst_slice_noinl.py +++ b/test_regress/t/t_inst_slice_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_slice_part_select.py b/test_regress/t/t_inst_slice_part_select.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_slice_part_select.py +++ b/test_regress/t/t_inst_slice_part_select.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_slice_part_select.v b/test_regress/t/t_inst_slice_part_select.v index 3c837e0df..827561026 100644 --- a/test_regress/t/t_inst_slice_part_select.v +++ b/test_regress/t/t_inst_slice_part_select.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by engr248. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2020 engr248 // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_inst_sv.py b/test_regress/t/t_inst_sv.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_inst_sv.py +++ b/test_regress/t/t_inst_sv.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_sv.v b/test_regress/t/t_inst_sv.v index d412b21a6..e2cfeb46d 100644 --- a/test_regress/t/t_inst_sv.v +++ b/test_regress/t/t_inst_sv.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_tree.v b/test_regress/t/t_inst_tree.v index 092ff2c17..6a0a211f6 100644 --- a/test_regress/t/t_inst_tree.v +++ b/test_regress/t/t_inst_tree.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_tree_inl0_pub0.py b/test_regress/t/t_inst_tree_inl0_pub0.py index e55e72830..a5bc9523b 100755 --- a/test_regress/t/t_inst_tree_inl0_pub0.py +++ b/test_regress/t/t_inst_tree_inl0_pub0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_tree_inl0_pub0.vlt b/test_regress/t/t_inst_tree_inl0_pub0.vlt index 4743c1224..7b928414f 100644 --- a/test_regress/t/t_inst_tree_inl0_pub0.vlt +++ b/test_regress/t/t_inst_tree_inl0_pub0.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_inst_tree_inl0_pub1.py b/test_regress/t/t_inst_tree_inl0_pub1.py index a8a063375..31d27a095 100755 --- a/test_regress/t/t_inst_tree_inl0_pub1.py +++ b/test_regress/t/t_inst_tree_inl0_pub1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_tree_inl0_pub1.vlt b/test_regress/t/t_inst_tree_inl0_pub1.vlt index 26d803b7d..3e01feebf 100644 --- a/test_regress/t/t_inst_tree_inl0_pub1.vlt +++ b/test_regress/t/t_inst_tree_inl0_pub1.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_inst_tree_inl1_pub0.py b/test_regress/t/t_inst_tree_inl1_pub0.py index 437358a66..488ba092e 100755 --- a/test_regress/t/t_inst_tree_inl1_pub0.py +++ b/test_regress/t/t_inst_tree_inl1_pub0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_tree_inl1_pub0.vlt b/test_regress/t/t_inst_tree_inl1_pub0.vlt index b27dcbff4..328e18b7b 100644 --- a/test_regress/t/t_inst_tree_inl1_pub0.vlt +++ b/test_regress/t/t_inst_tree_inl1_pub0.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_inst_tree_inl1_pub1.py b/test_regress/t/t_inst_tree_inl1_pub1.py index 2a4f5c98b..463aaa038 100755 --- a/test_regress/t/t_inst_tree_inl1_pub1.py +++ b/test_regress/t/t_inst_tree_inl1_pub1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_tree_inl1_pub1.vlt b/test_regress/t/t_inst_tree_inl1_pub1.vlt index fda247a74..2dc063070 100644 --- a/test_regress/t/t_inst_tree_inl1_pub1.vlt +++ b/test_regress/t/t_inst_tree_inl1_pub1.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_inst_v2k.py b/test_regress/t/t_inst_v2k.py index a791c097a..1ec3b0e4a 100755 --- a/test_regress/t/t_inst_v2k.py +++ b/test_regress/t/t_inst_v2k.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_v2k.v b/test_regress/t/t_inst_v2k.v index 4e9e524b6..d8a3af367 100644 --- a/test_regress/t/t_inst_v2k.v +++ b/test_regress/t/t_inst_v2k.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_v2k__sub.vi b/test_regress/t/t_inst_v2k__sub.vi index ee4ee74b1..28c2490bb 100644 --- a/test_regress/t/t_inst_v2k__sub.vi +++ b/test_regress/t/t_inst_v2k__sub.vi @@ -1,8 +1,8 @@ // -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // This file is named .vi to test +libext+ flags. diff --git a/test_regress/t/t_inst_wideconst.py b/test_regress/t/t_inst_wideconst.py index 54297fbe0..b18ae571f 100755 --- a/test_regress/t/t_inst_wideconst.py +++ b/test_regress/t/t_inst_wideconst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_inst_wideconst.v b/test_regress/t/t_inst_wideconst.v index b4cc2ec2d..39c86f763 100644 --- a/test_regress/t/t_inst_wideconst.v +++ b/test_regress/t/t_inst_wideconst.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_interconnect.py b/test_regress/t/t_interconnect.py index 341c8bf04..6676c437d 100755 --- a/test_regress/t/t_interconnect.py +++ b/test_regress/t/t_interconnect.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interconnect.v b/test_regress/t/t_interconnect.v index 0196adab1..a4d327863 100644 --- a/test_regress/t/t_interconnect.v +++ b/test_regress/t/t_interconnect.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Note: Other simulator's support for interconnect seems rare, the below might diff --git a/test_regress/t/t_interconnect_bad.py b/test_regress/t/t_interconnect_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interconnect_bad.py +++ b/test_regress/t/t_interconnect_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interconnect_bad.v b/test_regress/t/t_interconnect_bad.v index c709239e7..961792fe5 100644 --- a/test_regress/t/t_interconnect_bad.v +++ b/test_regress/t/t_interconnect_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_interface.py b/test_regress/t/t_interface.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface.py +++ b/test_regress/t/t_interface.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface.v b/test_regress/t/t_interface.v index 608d3e443..9f09df9f2 100644 --- a/test_regress/t/t_interface.v +++ b/test_regress/t/t_interface.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog interface test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_interface1.py b/test_regress/t/t_interface1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface1.py +++ b/test_regress/t/t_interface1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface1.v b/test_regress/t/t_interface1.v index 9d87f3a4c..be074184e 100644 --- a/test_regress/t/t_interface1.v +++ b/test_regress/t/t_interface1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing diff --git a/test_regress/t/t_interface1_modport.py b/test_regress/t/t_interface1_modport.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface1_modport.py +++ b/test_regress/t/t_interface1_modport.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface1_modport.v b/test_regress/t/t_interface1_modport.v index d2359b44e..ab64c2854 100644 --- a/test_regress/t/t_interface1_modport.v +++ b/test_regress/t/t_interface1_modport.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing diff --git a/test_regress/t/t_interface1_modport_nansi.py b/test_regress/t/t_interface1_modport_nansi.py index 83abc3d48..7f2c0bde5 100755 --- a/test_regress/t/t_interface1_modport_nansi.py +++ b/test_regress/t/t_interface1_modport_nansi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface1_modport_noinl.py b/test_regress/t/t_interface1_modport_noinl.py index 39ec887e7..1aec8386a 100755 --- a/test_regress/t/t_interface1_modport_noinl.py +++ b/test_regress/t/t_interface1_modport_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface1_modport_trace.py b/test_regress/t/t_interface1_modport_trace.py index e8d6f2272..e291222e0 100755 --- a/test_regress/t/t_interface1_modport_trace.py +++ b/test_regress/t/t_interface1_modport_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface1_noinl.py b/test_regress/t/t_interface1_noinl.py index f38117e8e..e25d72676 100755 --- a/test_regress/t/t_interface1_noinl.py +++ b/test_regress/t/t_interface1_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface2.py b/test_regress/t/t_interface2.py index fd9bd7244..305e2bb0b 100755 --- a/test_regress/t/t_interface2.py +++ b/test_regress/t/t_interface2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface2.v b/test_regress/t/t_interface2.v index 2c3df5550..872550823 100644 --- a/test_regress/t/t_interface2.v +++ b/test_regress/t/t_interface2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_interface2_noinl.py b/test_regress/t/t_interface2_noinl.py index b231b4c73..bd529e930 100755 --- a/test_regress/t/t_interface2_noinl.py +++ b/test_regress/t/t_interface2_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_and_struct_pattern.py b/test_regress/t/t_interface_and_struct_pattern.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_and_struct_pattern.py +++ b/test_regress/t/t_interface_and_struct_pattern.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_and_struct_pattern.v b/test_regress/t/t_interface_and_struct_pattern.v index 2b75dca53..39109a3b9 100644 --- a/test_regress/t/t_interface_and_struct_pattern.v +++ b/test_regress/t/t_interface_and_struct_pattern.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog interface test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 package Package_pkg; diff --git a/test_regress/t/t_interface_ar2a.py b/test_regress/t/t_interface_ar2a.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_interface_ar2a.py +++ b/test_regress/t/t_interface_ar2a.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ar2a.v b/test_regress/t/t_interface_ar2a.v index f0c406843..e2102953b 100644 --- a/test_regress/t/t_interface_ar2a.v +++ b/test_regress/t/t_interface_ar2a.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog interface test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Thierry Tambe. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Thierry Tambe // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_interface_ar2b.py b/test_regress/t/t_interface_ar2b.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_interface_ar2b.py +++ b/test_regress/t/t_interface_ar2b.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ar2b.v b/test_regress/t/t_interface_ar2b.v index b14ae8cbc..6e8766ff9 100644 --- a/test_regress/t/t_interface_ar2b.v +++ b/test_regress/t/t_interface_ar2b.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog interface test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Thierry Tambe. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Thierry Tambe // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_interface_ar3.py b/test_regress/t/t_interface_ar3.py index b0a6b1891..b9952dbf2 100755 --- a/test_regress/t/t_interface_ar3.py +++ b/test_regress/t/t_interface_ar3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ar3.v b/test_regress/t/t_interface_ar3.v index 74416a300..8ea3beb1d 100644 --- a/test_regress/t/t_interface_ar3.v +++ b/test_regress/t/t_interface_ar3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog interface test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Thierry Tambe. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Thierry Tambe // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_interface_array.py b/test_regress/t/t_interface_array.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_array.py +++ b/test_regress/t/t_interface_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array.v b/test_regress/t/t_interface_array.v index 6f302e012..1609aad05 100644 --- a/test_regress/t/t_interface_array.v +++ b/test_regress/t/t_interface_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 interface foo_intf; diff --git a/test_regress/t/t_interface_array2.py b/test_regress/t/t_interface_array2.py index d30a25fe8..9e69cbd92 100755 --- a/test_regress/t/t_interface_array2.py +++ b/test_regress/t/t_interface_array2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array2.v b/test_regress/t/t_interface_array2.v index db5433194..f2b7190e8 100644 --- a/test_regress/t/t_interface_array2.v +++ b/test_regress/t/t_interface_array2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Johan Bjork. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Johan Bjork // SPDX-License-Identifier: CC0-1.0 interface intf; diff --git a/test_regress/t/t_interface_array2_coverage.py b/test_regress/t/t_interface_array2_coverage.py index c0c4569f2..70f8d1678 100755 --- a/test_regress/t/t_interface_array2_coverage.py +++ b/test_regress/t/t_interface_array2_coverage.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array2_noinl.py b/test_regress/t/t_interface_array2_noinl.py index 4e3a93da0..4de8eeb5d 100755 --- a/test_regress/t/t_interface_array2_noinl.py +++ b/test_regress/t/t_interface_array2_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array3.py b/test_regress/t/t_interface_array3.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_interface_array3.py +++ b/test_regress/t/t_interface_array3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array3.v b/test_regress/t/t_interface_array3.v index da93b3cf3..e98b1e18a 100644 --- a/test_regress/t/t_interface_array3.v +++ b/test_regress/t/t_interface_array3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface my_ifc (); diff --git a/test_regress/t/t_interface_array4.py b/test_regress/t/t_interface_array4.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_interface_array4.py +++ b/test_regress/t/t_interface_array4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array4.v b/test_regress/t/t_interface_array4.v index afb4f45c5..1a48b2dee 100644 --- a/test_regress/t/t_interface_array4.v +++ b/test_regress/t/t_interface_array4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface Ifc; diff --git a/test_regress/t/t_interface_array_bad.py b/test_regress/t/t_interface_array_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_array_bad.py +++ b/test_regress/t/t_interface_array_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array_bad.v b/test_regress/t/t_interface_array_bad.v index adac88196..9806c54f7 100644 --- a/test_regress/t/t_interface_array_bad.v +++ b/test_regress/t/t_interface_array_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Demonstrate deferred linking error messages // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 interface foo_intf; diff --git a/test_regress/t/t_interface_array_loop.py b/test_regress/t/t_interface_array_loop.py new file mode 100755 index 000000000..d376ab1f0 --- /dev/null +++ b/test_regress/t/t_interface_array_loop.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Test interface array access with loop variables +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True) + +test.passes() diff --git a/test_regress/t/t_interface_array_loop.v b/test_regress/t/t_interface_array_loop.v new file mode 100644 index 000000000..5898f6981 --- /dev/null +++ b/test_regress/t/t_interface_array_loop.v @@ -0,0 +1,393 @@ +// DESCRIPTION: Verilator: Test interface array access with loop variables +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +interface simple_if; + logic data; + logic [7:0] value; + + modport source(output data, output value); + modport sink(input data, input value); +endinterface + +// Test 6: Submodule with interface array as sink modport port +module sub_sink ( + simple_if.sink ifaces[3:0], + output logic [7:0] sum_out +); + always_comb begin + sum_out = 8'b0; + for (int i = 0; i < 4; i++) begin + sum_out = sum_out + ifaces[i].value; + end + end +endmodule + +// Test 7: Submodule with interface array as source modport port +module sub_source ( + simple_if.source ifaces[3:0] +); + always_comb begin + for (int i = 0; i < 4; i++) begin + ifaces[i].data = 1'b1; + ifaces[i].value = 8'(i + 100); + end + end +endmodule + +// Test 8: Submodule with interface array without modport +module sub_generic ( + simple_if ifaces[3:0] +); + always_comb begin + for (int i = 0; i < 4; i++) begin + ifaces[i].data = 1'b0; + ifaces[i].value = 8'(i + 50); + end + end +endmodule + +// Test 11: Parameterized submodule with interface array size from parameter +module l1_param_sub #( + parameter NUM_IFACES = 4 +) ( + simple_if.sink l0_ifaces[NUM_IFACES-1:0], + output logic [7:0] l0_sum +); + always_comb begin + l0_sum = 8'b0; + for (int i = 0; i < NUM_IFACES; i++) begin + l0_sum = l0_sum + l0_ifaces[i].value; + end + end +endmodule + +module t ( /*AUTOARG*/ + // Inputs + clk +); + + input clk; + + localparam N = 4; + + simple_if ifaces[N-1:0] (); + + // Test 1: Simple for loop writing to interface array + always_comb begin + for (int i = 0; i < N; i++) begin + ifaces[i].data = '0; + end + end + + // Test 2: For loop reading from interface array + logic [N-1:0] read_data; + always_comb begin + for (int j = 0; j < N; j++) begin + read_data[j] = ifaces[j].data; + end + end + + // Test 3: For loop with expression in body + always_comb begin + for (int k = 0; k < N - 1; k++) begin + // Use k to index, accessing different member + ifaces[k].value = 8'(k); + end + ifaces[N-1].value = 8'hFF; + end + + // Test 4: Descending loop with >= comparison + logic [N-1:0] desc_data; + always_comb begin + for (int p = N - 1; p >= 0; p--) begin + desc_data[p] = ifaces[p].data; + end + end + + // Test 4b: Ascending loop with <= comparison + logic [N-1:0] lte_data; + always_comb begin + for (int m = 0; m <= N - 1; m++) begin + lte_data[m] = ifaces[m].data; + end + end + + // Test 4c: Descending loop with > comparison + simple_if gt_ifaces[N-1:0] (); + always_comb begin + for (int n = N; n > 0; n--) begin + gt_ifaces[n-1].data = 1'b1; + gt_ifaces[n-1].value = 8'(n); + end + end + + // Test 5: Multiple interface arrays in same loop + simple_if other_ifaces[N-1:0] (); + always_comb begin + for (int q = 0; q < N; q++) begin + other_ifaces[q].data = ifaces[q].data; + other_ifaces[q].value = ifaces[q].value; + end + end + + // Test 6: Interface array as sink modport port (read from ports in loop) + logic [7:0] sink_sum; + sub_sink u_sub_sink ( + .ifaces(ifaces), + .sum_out(sink_sum) + ); + + // Test 7: Interface array as source modport port (write to ports in loop) + simple_if source_ifaces[N-1:0] (); + sub_source u_sub_source (.ifaces(source_ifaces)); + + // Test 8: Interface array without modport (read/write in loop) + simple_if generic_ifaces[N-1:0] (); + sub_generic u_sub_generic (.ifaces(generic_ifaces)); + + // Test 9: Ascending loop with step of 2 + simple_if step2_ifaces[7:0] (); + always_comb begin + for (int i = 0; i < 8; i += 2) begin + step2_ifaces[i].data = 1'b1; + step2_ifaces[i].value = 8'(i); + end + for (int i = 1; i < 8; i += 2) begin + step2_ifaces[i].data = 1'b0; + step2_ifaces[i].value = 8'hAA; + end + end + + // Test 10: Descending loop with step of -2 + simple_if step2d_ifaces[7:0] (); + always_comb begin + for (int i = 6; i >= 0; i -= 2) begin + step2d_ifaces[i].data = 1'b1; + step2d_ifaces[i].value = 8'(i); + end + for (int i = 7; i >= 1; i -= 2) begin + step2d_ifaces[i].data = 1'b0; + step2d_ifaces[i].value = 8'hBB; + end + end + + // Test 11: Parameterized submodule with interface array size from parameter + // Override NUM_IFACES from default 4 to 6 to test that pre-unroll + // uses the overridden parameter value (not the default) + simple_if l0_param_ifaces[5:0] (); + always_comb begin + for (int i = 0; i < 6; i++) begin + l0_param_ifaces[i].data = 1'b1; + l0_param_ifaces[i].value = 8'(i * 10); + end + end + logic [7:0] l0_param_sum; + l1_param_sub #( + .NUM_IFACES(6) + ) u_l1_param ( + .l0_ifaces(l0_param_ifaces), + .l0_sum(l0_param_sum) + ); + + // Test 12: Complex index expression (N-1-i) - reversed assignment + simple_if rev_ifaces[N-1:0] (); + always_comb begin + for (int i = 0; i < N; i++) begin + rev_ifaces[N-1-i].data = 1'b1; + rev_ifaces[N-1-i].value = 8'(i); + end + end + + // Test 13: Non-zero-based interface array range [2:5] + simple_if nzb_ifaces[2:5] (); + always_comb begin + for (int i = 2; i <= 5; i++) begin + nzb_ifaces[i].data = 1'b1; + nzb_ifaces[i].value = 8'(i); + end + end + + // Verification + int cycle; + initial cycle = 0; + + always @(posedge clk) begin + cycle <= cycle + 1; + + // Check that interfaces were properly accessed + if (cycle == 1) begin + // After initialization, data should be 0 + for (int i = 0; i < N; i++) begin + if (ifaces[i].data !== 1'b0) begin + $display("%%Error: ifaces[%0d].data should be 0, got %b", i, ifaces[i].data); + $stop; + end + end + + // Check values + for (int i = 0; i < N - 1; i++) begin + if (ifaces[i].value !== 8'(i)) begin + $display("%%Error: ifaces[%0d].value should be %0d, got %0d", i, i, ifaces[i].value); + $stop; + end + end + if (ifaces[N-1].value !== 8'hFF) begin + $display("%%Error: ifaces[%0d].value should be 0xFF, got %0d", N - 1, ifaces[N-1].value); + $stop; + end + + // Test 4b: Check lte_data (uses <= comparison) + for (int i = 0; i < N; i++) begin + if (lte_data[i] !== 1'b0) begin + $display("%%Error: lte_data[%0d] should be 0, got %b", i, lte_data[i]); + $stop; + end + end + + // Test 4c: Check gt_ifaces (uses > comparison, values are 1,2,3,4) + for (int i = 0; i < N; i++) begin + if (gt_ifaces[i].data !== 1'b1) begin + $display("%%Error: gt_ifaces[%0d].data should be 1, got %b", i, gt_ifaces[i].data); + $stop; + end + if (gt_ifaces[i].value !== 8'(i + 1)) begin + $display("%%Error: gt_ifaces[%0d].value should be %0d, got %0d", i, i + 1, + gt_ifaces[i].value); + $stop; + end + end + + // Test 6: Check sink_sum (sum of ifaces[0..3].value = 0+1+2+255 = 258 = 0x02) + if (sink_sum !== 8'h02) begin + $display("%%Error: sink_sum should be 0x02, got 0x%02x", sink_sum); + $stop; + end + + // Test 7: Check source_ifaces (written by sub_source with i+100) + for (int i = 0; i < N; i++) begin + if (source_ifaces[i].data !== 1'b1) begin + $display("%%Error: source_ifaces[%0d].data should be 1, got %b", i, + source_ifaces[i].data); + $stop; + end + if (source_ifaces[i].value !== 8'(i + 100)) begin + $display("%%Error: source_ifaces[%0d].value should be %0d, got %0d", i, i + 100, + source_ifaces[i].value); + $stop; + end + end + + // Test 8: Check generic_ifaces (written by sub_generic with i+50) + for (int i = 0; i < N; i++) begin + if (generic_ifaces[i].data !== 1'b0) begin + $display("%%Error: generic_ifaces[%0d].data should be 0, got %b", i, + generic_ifaces[i].data); + $stop; + end + if (generic_ifaces[i].value !== 8'(i + 50)) begin + $display("%%Error: generic_ifaces[%0d].value should be %0d, got %0d", i, i + 50, + generic_ifaces[i].value); + $stop; + end + end + + // Test 9: Check step2_ifaces (even indices have i, odd have 0xAA) + for (int i = 0; i < 8; i++) begin + if (i % 2 == 0) begin + if (step2_ifaces[i].data !== 1'b1) begin + $display("%%Error: step2_ifaces[%0d].data should be 1, got %b", i, + step2_ifaces[i].data); + $stop; + end + if (step2_ifaces[i].value !== 8'(i)) begin + $display("%%Error: step2_ifaces[%0d].value should be %0d, got %0d", i, i, + step2_ifaces[i].value); + $stop; + end + end + else begin + if (step2_ifaces[i].data !== 1'b0) begin + $display("%%Error: step2_ifaces[%0d].data should be 0, got %b", i, + step2_ifaces[i].data); + $stop; + end + if (step2_ifaces[i].value !== 8'hAA) begin + $display("%%Error: step2_ifaces[%0d].value should be 0xAA, got 0x%02x", i, + step2_ifaces[i].value); + $stop; + end + end + end + + // Test 10: Check step2d_ifaces (even indices descending, odd indices 0xBB) + for (int i = 0; i < 8; i++) begin + if (i % 2 == 0) begin + if (step2d_ifaces[i].data !== 1'b1) begin + $display("%%Error: step2d_ifaces[%0d].data should be 1, got %b", i, + step2d_ifaces[i].data); + $stop; + end + if (step2d_ifaces[i].value !== 8'(i)) begin + $display("%%Error: step2d_ifaces[%0d].value should be %0d, got %0d", i, i, + step2d_ifaces[i].value); + $stop; + end + end + else begin + if (step2d_ifaces[i].data !== 1'b0) begin + $display("%%Error: step2d_ifaces[%0d].data should be 0, got %b", i, + step2d_ifaces[i].data); + $stop; + end + if (step2d_ifaces[i].value !== 8'hBB) begin + $display("%%Error: step2d_ifaces[%0d].value should be 0xBB, got 0x%02x", i, + step2d_ifaces[i].value); + $stop; + end + end + end + + // Test 11: Check l0_param_sum (0*10 + 1*10 + 2*10 + 3*10 + 4*10 + 5*10 = 150) + if (l0_param_sum !== 8'd150) begin + $display("%%Error: l0_param_sum should be 150, got %0d", l0_param_sum); + $stop; + end + + // Test 12: Check rev_ifaces (reversed: rev_ifaces[N-1-i].value = i) + // So rev_ifaces[3].value=0, rev_ifaces[2].value=1, rev_ifaces[1].value=2, rev_ifaces[0].value=3 + for (int i = 0; i < N; i++) begin + if (rev_ifaces[i].data !== 1'b1) begin + $display("%%Error: rev_ifaces[%0d].data should be 1, got %b", i, rev_ifaces[i].data); + $stop; + end + if (rev_ifaces[i].value !== 8'(N - 1 - i)) begin + $display("%%Error: rev_ifaces[%0d].value should be %0d, got %0d", i, N - 1 - i, + rev_ifaces[i].value); + $stop; + end + end + + // Test 13: Check nzb_ifaces (non-zero-based [2:5], nzb_ifaces[i].value = i) + for (int i = 2; i <= 5; i++) begin + if (nzb_ifaces[i].data !== 1'b1) begin + $display("%%Error: nzb_ifaces[%0d].data should be 1, got %b", i, nzb_ifaces[i].data); + $stop; + end + if (nzb_ifaces[i].value !== 8'(i)) begin + $display("%%Error: nzb_ifaces[%0d].value should be %0d, got %0d", i, i, + nzb_ifaces[i].value); + $stop; + end + end + end + + if (cycle == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_interface_array_loop_bad.out b/test_regress/t/t_interface_array_loop_bad.out new file mode 100644 index 000000000..a0b24d9c7 --- /dev/null +++ b/test_regress/t/t_interface_array_loop_bad.out @@ -0,0 +1,10 @@ +%Error: t/t_interface_array_loop_bad.v:27:14: Expecting expression to be constant, but variable isn't const: 'i' + : ... note: In instance 't' + 27 | ifaces[i].value = 8'(i); + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_interface_array_loop_bad.v:27:13: Could not expand constant selection inside dotted reference: 'i' + : ... note: In instance 't' + 27 | ifaces[i].value = 8'(i); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_interface_array_loop_bad.py b/test_regress/t/t_interface_array_loop_bad.py new file mode 100755 index 000000000..1584aa3de --- /dev/null +++ b/test_regress/t/t_interface_array_loop_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Test non-constant interface array loop index error +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_array_loop_bad.v b/test_regress/t/t_interface_array_loop_bad.v new file mode 100644 index 000000000..7299b4ad5 --- /dev/null +++ b/test_regress/t/t_interface_array_loop_bad.v @@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Test non-constant interface array loop index error +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +interface simple_bad_if; + logic [7:0] value; +endinterface + +module t ( /*AUTOARG*/ + // Inputs + clk +); + + input clk; + + localparam N = 4; + + simple_bad_if ifaces[N-1:0] (); + + // BAD: Loop with runtime-variable bound - not unrollable, so the + // interface array index cannot be resolved to a constant. + logic [7:0] limit; + always_comb begin + for (int i = 0; i < limit; i++) begin + ifaces[i].value = 8'(i); + end + end + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_interface_array_loop_noinl.py b/test_regress/t/t_interface_array_loop_noinl.py new file mode 100755 index 000000000..bb8c4d193 --- /dev/null +++ b/test_regress/t/t_interface_array_loop_noinl.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Test interface array access with loop variables (no inline) +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_interface_array_loop.v" + +test.compile(fails=True, v_flags2=["-fno-inline"]) + +test.passes() diff --git a/test_regress/t/t_interface_array_modport.py b/test_regress/t/t_interface_array_modport.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_array_modport.py +++ b/test_regress/t/t_interface_array_modport.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array_modport.v b/test_regress/t/t_interface_array_modport.v index c3317b5e3..883bec0f4 100644 --- a/test_regress/t/t_interface_array_modport.v +++ b/test_regress/t/t_interface_array_modport.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Connecting an interface array slice to a module's portmap // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 interface foo_intf; diff --git a/test_regress/t/t_interface_array_nocolon.py b/test_regress/t/t_interface_array_nocolon.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_array_nocolon.py +++ b/test_regress/t/t_interface_array_nocolon.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array_nocolon.v b/test_regress/t/t_interface_array_nocolon.v index 370ca35fd..5ef95ea2b 100644 --- a/test_regress/t/t_interface_array_nocolon.v +++ b/test_regress/t/t_interface_array_nocolon.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Mike Popoloski. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Mike Popoloski // SPDX-License-Identifier: CC0-1.0 interface foo_intf diff --git a/test_regress/t/t_interface_array_nocolon_bad.py b/test_regress/t/t_interface_array_nocolon_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_interface_array_nocolon_bad.py +++ b/test_regress/t/t_interface_array_nocolon_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array_nocolon_bad.v b/test_regress/t/t_interface_array_nocolon_bad.v index 088f38ef1..79c6c570d 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.v +++ b/test_regress/t/t_interface_array_nocolon_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Mike Popoloski. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Mike Popoloski // SPDX-License-Identifier: CC0-1.0 interface foo_intf diff --git a/test_regress/t/t_interface_array_noinl.py b/test_regress/t/t_interface_array_noinl.py index e4b1e7a2d..1749f03fd 100755 --- a/test_regress/t/t_interface_array_noinl.py +++ b/test_regress/t/t_interface_array_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array_parameter_access.py b/test_regress/t/t_interface_array_parameter_access.py index dbdaf4551..1a93d5310 100755 --- a/test_regress/t/t_interface_array_parameter_access.py +++ b/test_regress/t/t_interface_array_parameter_access.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_array_parameter_access.v b/test_regress/t/t_interface_array_parameter_access.v index 7b95cb7fe..489efbf8b 100644 --- a/test_regress/t/t_interface_array_parameter_access.v +++ b/test_regress/t/t_interface_array_parameter_access.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Get parameter from array of interfaces // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Todd Strader +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Todd Strader // SPDX-License-Identifier: CC0-1.0 interface intf diff --git a/test_regress/t/t_interface_array_parameter_aggregate.py b/test_regress/t/t_interface_array_parameter_aggregate.py new file mode 100755 index 000000000..df81265b7 --- /dev/null +++ b/test_regress/t/t_interface_array_parameter_aggregate.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile(fails=True) + +#test.execute(fails=True) + +test.passes() diff --git a/test_regress/t/t_interface_array_parameter_aggregate.v b/test_regress/t/t_interface_array_parameter_aggregate.v new file mode 100644 index 000000000..fd8745a46 --- /dev/null +++ b/test_regress/t/t_interface_array_parameter_aggregate.v @@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Todd Strader +// SPDX-License-Identifier: CC0-1.0 + +typedef struct { + int BAR_INT; + bit BAR_BIT; + byte BAR_ARRAY[0:3]; +} foo_t; + +interface intf #( + parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}} +) ( + input wire clk, + input wire rst +); + modport modp(input clk, rst); +endinterface + +module sub ( + intf.modp the_intf_port[4], + intf.modp single_intf_port +); + localparam foo_t intf_foo = the_intf_port[0].FOO; + localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; + localparam bit intf_foo_bar_bit = the_intf_port[0].FOO.BAR_BIT; + localparam byte intf_foo_bar_byte = the_intf_port[0].FOO.BAR_ARRAY[3]; + localparam foo_t single_foo = single_intf_port.FOO; + localparam int single_foo_bar_int = single_intf_port.FOO.BAR_INT; + localparam bit single_foo_bar_bit = single_intf_port.FOO.BAR_BIT; + localparam byte single_foo_bar_byte = single_intf_port.FOO.BAR_ARRAY[3]; + + initial begin + if (intf_foo != foo_t'{4, 1'b1, '{1, 2, 4, 8}}) $stop; + if (intf_foo_bar_int != 4) $stop; + if (intf_foo_bar_bit != 1'b1) $stop; + if (intf_foo_bar_byte != 8'd8) $stop; + if (single_foo != foo_t'{4, 1'b1, '{1, 2, 4, 8}}) $stop; + if (single_foo_bar_int != 4) $stop; + if (single_foo_bar_bit != 1'b1) $stop; + if (single_foo_bar_byte != 8'd8) $stop; + end +endmodule + +module t ( + clk +); + logic rst; + input clk; + + intf the_intf[4] (.*); + intf single_intf (.*); + + sub the_sub ( + .the_intf_port(the_intf), + .single_intf_port(single_intf) + ); + + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_arraymux.py b/test_regress/t/t_interface_arraymux.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_interface_arraymux.py +++ b/test_regress/t/t_interface_arraymux.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_arraymux.v b/test_regress/t/t_interface_arraymux.v index 382045fd3..06e970d71 100644 --- a/test_regress/t/t_interface_arraymux.v +++ b/test_regress/t/t_interface_arraymux.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by John Stevenson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 John Stevenson // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_interface_asvar_bad.py b/test_regress/t/t_interface_asvar_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_asvar_bad.py +++ b/test_regress/t/t_interface_asvar_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_asvar_bad.v b/test_regress/t/t_interface_asvar_bad.v index d0dea01a0..868905f34 100644 --- a/test_regress/t/t_interface_asvar_bad.v +++ b/test_regress/t/t_interface_asvar_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_interface_bind_public.py b/test_regress/t/t_interface_bind_public.py index 54297fbe0..b18ae571f 100755 --- a/test_regress/t/t_interface_bind_public.py +++ b/test_regress/t/t_interface_bind_public.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_bind_public.v b/test_regress/t/t_interface_bind_public.v index 2f5cc16a4..1312a477d 100644 --- a/test_regress/t/t_interface_bind_public.v +++ b/test_regress/t/t_interface_bind_public.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Alex Solomatnikov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 interface hex2ram_if diff --git a/test_regress/t/t_interface_colon_bad.py b/test_regress/t/t_interface_colon_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_colon_bad.py +++ b/test_regress/t/t_interface_colon_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_colon_bad.v b/test_regress/t/t_interface_colon_bad.v index 904468bca..a202e8574 100644 --- a/test_regress/t/t_interface_colon_bad.v +++ b/test_regress/t/t_interface_colon_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface iface; diff --git a/test_regress/t/t_interface_dearray.py b/test_regress/t/t_interface_dearray.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_interface_dearray.py +++ b/test_regress/t/t_interface_dearray.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_dearray.v b/test_regress/t/t_interface_dearray.v index a8bee53b2..88f355664 100644 --- a/test_regress/t/t_interface_dearray.v +++ b/test_regress/t/t_interface_dearray.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface A; @@ -31,7 +31,7 @@ module tb_top(); initial begin static a_t aa = a[0]; - B b = new(a[0]); + automatic B b = new(a[0]); c = new(); c.vif = a; diff --git a/test_regress/t/t_interface_dearray_bad.py b/test_regress/t/t_interface_dearray_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_dearray_bad.py +++ b/test_regress/t/t_interface_dearray_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_dearray_bad.v b/test_regress/t/t_interface_dearray_bad.v index cde795595..93e2f20fc 100644 --- a/test_regress/t/t_interface_dearray_bad.v +++ b/test_regress/t/t_interface_dearray_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface A; diff --git a/test_regress/t/t_interface_derived_type.py b/test_regress/t/t_interface_derived_type.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_derived_type.py +++ b/test_regress/t/t_interface_derived_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_derived_type.v b/test_regress/t/t_interface_derived_type.v index cee8559bc..7732ab714 100644 --- a/test_regress/t/t_interface_derived_type.v +++ b/test_regress/t/t_interface_derived_type.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: SystemVerilog interface test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 interface intf #( diff --git a/test_regress/t/t_interface_down.py b/test_regress/t/t_interface_down.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_down.py +++ b/test_regress/t/t_interface_down.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down.v b/test_regress/t/t_interface_down.v index e37037367..da941c14b 100644 --- a/test_regress/t/t_interface_down.v +++ b/test_regress/t/t_interface_down.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface ifc; diff --git a/test_regress/t/t_interface_down_inla.py b/test_regress/t/t_interface_down_inla.py index 1782f7d1b..f46b354c9 100755 --- a/test_regress/t/t_interface_down_inla.py +++ b/test_regress/t/t_interface_down_inla.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down_inlab.py b/test_regress/t/t_interface_down_inlab.py index d65a7085d..bd0f14aaf 100755 --- a/test_regress/t/t_interface_down_inlab.py +++ b/test_regress/t/t_interface_down_inlab.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down_inlac.py b/test_regress/t/t_interface_down_inlac.py index 6cc094f25..a6b39fff7 100755 --- a/test_regress/t/t_interface_down_inlac.py +++ b/test_regress/t/t_interface_down_inlac.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down_inlad.py b/test_regress/t/t_interface_down_inlad.py index d7d413259..b61190907 100755 --- a/test_regress/t/t_interface_down_inlad.py +++ b/test_regress/t/t_interface_down_inlad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down_inlb.py b/test_regress/t/t_interface_down_inlb.py index daf398a11..60cb0da85 100755 --- a/test_regress/t/t_interface_down_inlb.py +++ b/test_regress/t/t_interface_down_inlb.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down_inlbc.py b/test_regress/t/t_interface_down_inlbc.py index 5a4620498..7a10c3417 100755 --- a/test_regress/t/t_interface_down_inlbc.py +++ b/test_regress/t/t_interface_down_inlbc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down_inlbd.py b/test_regress/t/t_interface_down_inlbd.py index 7b3bdf8c9..424369759 100755 --- a/test_regress/t/t_interface_down_inlbd.py +++ b/test_regress/t/t_interface_down_inlbd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down_inlc.py b/test_regress/t/t_interface_down_inlc.py index f0d83ee04..176f53229 100755 --- a/test_regress/t/t_interface_down_inlc.py +++ b/test_regress/t/t_interface_down_inlc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down_inlcd.py b/test_regress/t/t_interface_down_inlcd.py index bc2c3a4ff..6aab477a6 100755 --- a/test_regress/t/t_interface_down_inlcd.py +++ b/test_regress/t/t_interface_down_inlcd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down_inld.py b/test_regress/t/t_interface_down_inld.py index aa706ba17..1d3e2e157 100755 --- a/test_regress/t/t_interface_down_inld.py +++ b/test_regress/t/t_interface_down_inld.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_down_noinl.py b/test_regress/t/t_interface_down_noinl.py index d1aa7ab2b..6fdb3819b 100755 --- a/test_regress/t/t_interface_down_noinl.py +++ b/test_regress/t/t_interface_down_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_dups.py b/test_regress/t/t_interface_dups.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_dups.py +++ b/test_regress/t/t_interface_dups.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_dups.v b/test_regress/t/t_interface_dups.v index 6a6925b7c..dfa2897f8 100644 --- a/test_regress/t/t_interface_dups.v +++ b/test_regress/t/t_interface_dups.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_interface_find.py b/test_regress/t/t_interface_find.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_find.py +++ b/test_regress/t/t_interface_find.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_find.v b/test_regress/t/t_interface_find.v index 6566a7381..284b31e4f 100644 --- a/test_regress/t/t_interface_find.v +++ b/test_regress/t/t_interface_find.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Auto-resolved by t_interface_find_ifc.v diff --git a/test_regress/t/t_interface_find_ifc.v b/test_regress/t/t_interface_find_ifc.v index 2866d850b..ddf1ec395 100644 --- a/test_regress/t/t_interface_find_ifc.v +++ b/test_regress/t/t_interface_find_ifc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface t_interface_find_ifc; diff --git a/test_regress/t/t_interface_gen.py b/test_regress/t/t_interface_gen.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen.py +++ b/test_regress/t/t_interface_gen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen.v b/test_regress/t/t_interface_gen.v index e4dbedad5..2c3d61772 100644 --- a/test_regress/t/t_interface_gen.v +++ b/test_regress/t/t_interface_gen.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing diff --git a/test_regress/t/t_interface_gen10.py b/test_regress/t/t_interface_gen10.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen10.py +++ b/test_regress/t/t_interface_gen10.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen10.v b/test_regress/t/t_interface_gen10.v index 2e64f700f..0e00daee2 100644 --- a/test_regress/t/t_interface_gen10.v +++ b/test_regress/t/t_interface_gen10.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen10_noinl.py b/test_regress/t/t_interface_gen10_noinl.py index b75c3971f..25a8067b4 100755 --- a/test_regress/t/t_interface_gen10_noinl.py +++ b/test_regress/t/t_interface_gen10_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen11.py b/test_regress/t/t_interface_gen11.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen11.py +++ b/test_regress/t/t_interface_gen11.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen11.v b/test_regress/t/t_interface_gen11.v index 62acbbba7..6ae54e8da 100644 --- a/test_regress/t/t_interface_gen11.v +++ b/test_regress/t/t_interface_gen11.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen11_noinl.py b/test_regress/t/t_interface_gen11_noinl.py index 0c8f41ceb..fc1383eb0 100755 --- a/test_regress/t/t_interface_gen11_noinl.py +++ b/test_regress/t/t_interface_gen11_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen12.py b/test_regress/t/t_interface_gen12.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen12.py +++ b/test_regress/t/t_interface_gen12.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen12.v b/test_regress/t/t_interface_gen12.v index aec45a9c0..636645f21 100644 --- a/test_regress/t/t_interface_gen12.v +++ b/test_regress/t/t_interface_gen12.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug1005 diff --git a/test_regress/t/t_interface_gen12_noinl.py b/test_regress/t/t_interface_gen12_noinl.py index 343c709d0..cf3565baf 100755 --- a/test_regress/t/t_interface_gen12_noinl.py +++ b/test_regress/t/t_interface_gen12_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen13.py b/test_regress/t/t_interface_gen13.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen13.py +++ b/test_regress/t/t_interface_gen13.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen13.v b/test_regress/t/t_interface_gen13.v index 0435dda0e..9eabdde8c 100644 --- a/test_regress/t/t_interface_gen13.v +++ b/test_regress/t/t_interface_gen13.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen14.py b/test_regress/t/t_interface_gen14.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_interface_gen14.py +++ b/test_regress/t/t_interface_gen14.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen14.v b/test_regress/t/t_interface_gen14.v index 0803cc0cd..52bdcc768 100644 --- a/test_regress/t/t_interface_gen14.v +++ b/test_regress/t/t_interface_gen14.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_interface_gen2.py b/test_regress/t/t_interface_gen2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen2.py +++ b/test_regress/t/t_interface_gen2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen2.v b/test_regress/t/t_interface_gen2.v index 9ce2de2e1..ab6c5b401 100644 --- a/test_regress/t/t_interface_gen2.v +++ b/test_regress/t/t_interface_gen2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing diff --git a/test_regress/t/t_interface_gen2_collision.py b/test_regress/t/t_interface_gen2_collision.py index 132e5efc8..78a1e96e1 100755 --- a/test_regress/t/t_interface_gen2_collision.py +++ b/test_regress/t/t_interface_gen2_collision.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen2_noinl.py b/test_regress/t/t_interface_gen2_noinl.py index a58e9c947..f0ea8f993 100755 --- a/test_regress/t/t_interface_gen2_noinl.py +++ b/test_regress/t/t_interface_gen2_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen3.py b/test_regress/t/t_interface_gen3.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen3.py +++ b/test_regress/t/t_interface_gen3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen3.v b/test_regress/t/t_interface_gen3.v index 11f43c907..1e8f6756b 100644 --- a/test_regress/t/t_interface_gen3.v +++ b/test_regress/t/t_interface_gen3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing diff --git a/test_regress/t/t_interface_gen3_collision.py b/test_regress/t/t_interface_gen3_collision.py index 90c0230e2..4483913c3 100755 --- a/test_regress/t/t_interface_gen3_collision.py +++ b/test_regress/t/t_interface_gen3_collision.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen3_noinl.py b/test_regress/t/t_interface_gen3_noinl.py index a3c907564..ff08a6a4f 100755 --- a/test_regress/t/t_interface_gen3_noinl.py +++ b/test_regress/t/t_interface_gen3_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen4.py b/test_regress/t/t_interface_gen4.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen4.py +++ b/test_regress/t/t_interface_gen4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen4.v b/test_regress/t/t_interface_gen4.v index c8a1efe86..10b574206 100644 --- a/test_regress/t/t_interface_gen4.v +++ b/test_regress/t/t_interface_gen4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug789 generates diff --git a/test_regress/t/t_interface_gen4_noinl.py b/test_regress/t/t_interface_gen4_noinl.py index 4309bc821..d37bf8dc5 100755 --- a/test_regress/t/t_interface_gen4_noinl.py +++ b/test_regress/t/t_interface_gen4_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen5.py b/test_regress/t/t_interface_gen5.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen5.py +++ b/test_regress/t/t_interface_gen5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen5.v b/test_regress/t/t_interface_gen5.v index 584db2bff..db58f6764 100644 --- a/test_regress/t/t_interface_gen5.v +++ b/test_regress/t/t_interface_gen5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen5_noinl.py b/test_regress/t/t_interface_gen5_noinl.py index 6408c8ce9..049edc2b6 100755 --- a/test_regress/t/t_interface_gen5_noinl.py +++ b/test_regress/t/t_interface_gen5_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen6.py b/test_regress/t/t_interface_gen6.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen6.py +++ b/test_regress/t/t_interface_gen6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen6.v b/test_regress/t/t_interface_gen6.v index e6f41bc5e..b3a9e5620 100644 --- a/test_regress/t/t_interface_gen6.v +++ b/test_regress/t/t_interface_gen6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 // bug1001 diff --git a/test_regress/t/t_interface_gen6_noinl.py b/test_regress/t/t_interface_gen6_noinl.py index 1130f060e..c662f8969 100755 --- a/test_regress/t/t_interface_gen6_noinl.py +++ b/test_regress/t/t_interface_gen6_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen7.py b/test_regress/t/t_interface_gen7.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen7.py +++ b/test_regress/t/t_interface_gen7.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen7.v b/test_regress/t/t_interface_gen7.v index 5ffb79c37..fb457286e 100644 --- a/test_regress/t/t_interface_gen7.v +++ b/test_regress/t/t_interface_gen7.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen7_noinl.py b/test_regress/t/t_interface_gen7_noinl.py index 5f3047e6d..154b76464 100755 --- a/test_regress/t/t_interface_gen7_noinl.py +++ b/test_regress/t/t_interface_gen7_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen8.py b/test_regress/t/t_interface_gen8.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen8.py +++ b/test_regress/t/t_interface_gen8.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen8.v b/test_regress/t/t_interface_gen8.v index 10b7373a8..f3f464fbd 100644 --- a/test_regress/t/t_interface_gen8.v +++ b/test_regress/t/t_interface_gen8.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen8_noinl.py b/test_regress/t/t_interface_gen8_noinl.py index a436079e9..7184c52df 100755 --- a/test_regress/t/t_interface_gen8_noinl.py +++ b/test_regress/t/t_interface_gen8_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen9.py b/test_regress/t/t_interface_gen9.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_gen9.py +++ b/test_regress/t/t_interface_gen9.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen9.v b/test_regress/t/t_interface_gen9.v index 89d75adfb..4f8d6bd59 100644 --- a/test_regress/t/t_interface_gen9.v +++ b/test_regress/t/t_interface_gen9.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen9_noinl.py b/test_regress/t/t_interface_gen9_noinl.py index a4c47ac50..24ea30b07 100755 --- a/test_regress/t/t_interface_gen9_noinl.py +++ b/test_regress/t/t_interface_gen9_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_gen_noinl.py b/test_regress/t/t_interface_gen_noinl.py index 510c52a8b..c3c20b2fe 100755 --- a/test_regress/t/t_interface_gen_noinl.py +++ b/test_regress/t/t_interface_gen_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic.py b/test_regress/t/t_interface_generic.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic.py +++ b/test_regress/t/t_interface_generic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic.v b/test_regress/t/t_interface_generic.v index 729beebcd..2ea8f4256 100644 --- a/test_regress/t/t_interface_generic.v +++ b/test_regress/t/t_interface_generic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic2.py b/test_regress/t/t_interface_generic2.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic2.py +++ b/test_regress/t/t_interface_generic2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic2.v b/test_regress/t/t_interface_generic2.v index ee3ad0997..15eb2c048 100644 --- a/test_regress/t/t_interface_generic2.v +++ b/test_regress/t/t_interface_generic2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_array.py b/test_regress/t/t_interface_generic_array.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_array.py +++ b/test_regress/t/t_interface_generic_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_array.v b/test_regress/t/t_interface_generic_array.v index cce0e00fd..d732f6a43 100644 --- a/test_regress/t/t_interface_generic_array.v +++ b/test_regress/t/t_interface_generic_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_bad.out b/test_regress/t/t_interface_generic_bad.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_interface_generic_bad.py b/test_regress/t/t_interface_generic_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_bad.py +++ b/test_regress/t/t_interface_generic_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_bad.v b/test_regress/t/t_interface_generic_bad.v index d9d9a49be..e949e8e51 100644 --- a/test_regress/t/t_interface_generic_bad.v +++ b/test_regress/t/t_interface_generic_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_bad2.out b/test_regress/t/t_interface_generic_bad2.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_interface_generic_bad2.py b/test_regress/t/t_interface_generic_bad2.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_bad2.py +++ b/test_regress/t/t_interface_generic_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_bad2.v b/test_regress/t/t_interface_generic_bad2.v index aefcecb1d..51d5d339c 100644 --- a/test_regress/t/t_interface_generic_bad2.v +++ b/test_regress/t/t_interface_generic_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class inf; diff --git a/test_regress/t/t_interface_generic_bad3.out b/test_regress/t/t_interface_generic_bad3.out index 1d6b83f9a..dd5629397 100644 --- a/test_regress/t/t_interface_generic_bad3.out +++ b/test_regress/t/t_interface_generic_bad3.out @@ -5,5 +5,8 @@ %Error-PINNOTFOUND: t/t_interface_generic_bad3.v:21:42: Pin not found: '__pinNumber2' 21 | GenericModule genericModule (inf_inst, inf_inst); | ^~~~~~~~ + : ... Location of instance's module declaration + 11 | module GenericModule (interface a); + | ^~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_interface_generic_bad3.py b/test_regress/t/t_interface_generic_bad3.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_bad3.py +++ b/test_regress/t/t_interface_generic_bad3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_bad3.v b/test_regress/t/t_interface_generic_bad3.v index 98e7e755c..bc5c445b9 100644 --- a/test_regress/t/t_interface_generic_bad3.v +++ b/test_regress/t/t_interface_generic_bad3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_bad4.py b/test_regress/t/t_interface_generic_bad4.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_bad4.py +++ b/test_regress/t/t_interface_generic_bad4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_bad4.v b/test_regress/t/t_interface_generic_bad4.v index 392357c9c..f3dcbe934 100644 --- a/test_regress/t/t_interface_generic_bad4.v +++ b/test_regress/t/t_interface_generic_bad4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_function.py b/test_regress/t/t_interface_generic_function.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_function.py +++ b/test_regress/t/t_interface_generic_function.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_function.v b/test_regress/t/t_interface_generic_function.v index 4f52378a3..2d8dbad6b 100644 --- a/test_regress/t/t_interface_generic_function.v +++ b/test_regress/t/t_interface_generic_function.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_function_bad.out b/test_regress/t/t_interface_generic_function_bad.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_interface_generic_function_bad.py b/test_regress/t/t_interface_generic_function_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_function_bad.py +++ b/test_regress/t/t_interface_generic_function_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_function_bad.v b/test_regress/t/t_interface_generic_function_bad.v index 63bbc8b25..48592e5f7 100644 --- a/test_regress/t/t_interface_generic_function_bad.v +++ b/test_regress/t/t_interface_generic_function_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_iface_param.py b/test_regress/t/t_interface_generic_iface_param.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_iface_param.py +++ b/test_regress/t/t_interface_generic_iface_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_iface_param.v b/test_regress/t/t_interface_generic_iface_param.v index 6bdbe0022..9cbe4370a 100644 --- a/test_regress/t/t_interface_generic_iface_param.v +++ b/test_regress/t/t_interface_generic_iface_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf #(PARAM); diff --git a/test_regress/t/t_interface_generic_mod_param.py b/test_regress/t/t_interface_generic_mod_param.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_mod_param.py +++ b/test_regress/t/t_interface_generic_mod_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_mod_param.v b/test_regress/t/t_interface_generic_mod_param.v index b41481c7a..119a394d6 100644 --- a/test_regress/t/t_interface_generic_mod_param.v +++ b/test_regress/t/t_interface_generic_mod_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport.py b/test_regress/t/t_interface_generic_modport.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_modport.py +++ b/test_regress/t/t_interface_generic_modport.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport.v b/test_regress/t/t_interface_generic_modport.v index d4e58dbd8..407574f7e 100644 --- a/test_regress/t/t_interface_generic_modport.v +++ b/test_regress/t/t_interface_generic_modport.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport2.py b/test_regress/t/t_interface_generic_modport2.py index fda93f1f5..05f4c1c48 100755 --- a/test_regress/t/t_interface_generic_modport2.py +++ b/test_regress/t/t_interface_generic_modport2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport2.v b/test_regress/t/t_interface_generic_modport2.v index 59a32c0a2..988520f57 100644 --- a/test_regress/t/t_interface_generic_modport2.v +++ b/test_regress/t/t_interface_generic_modport2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport_bad.out b/test_regress/t/t_interface_generic_modport_bad.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_interface_generic_modport_bad.py b/test_regress/t/t_interface_generic_modport_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_modport_bad.py +++ b/test_regress/t/t_interface_generic_modport_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport_bad.v b/test_regress/t/t_interface_generic_modport_bad.v index 3fe1212a5..d6dff8c81 100644 --- a/test_regress/t/t_interface_generic_modport_bad.v +++ b/test_regress/t/t_interface_generic_modport_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport_bad2.out b/test_regress/t/t_interface_generic_modport_bad2.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_interface_generic_modport_bad2.py b/test_regress/t/t_interface_generic_modport_bad2.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_modport_bad2.py +++ b/test_regress/t/t_interface_generic_modport_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport_bad2.v b/test_regress/t/t_interface_generic_modport_bad2.v index c52c012cb..1a05b15e6 100644 --- a/test_regress/t/t_interface_generic_modport_bad2.v +++ b/test_regress/t/t_interface_generic_modport_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport_bad3.out b/test_regress/t/t_interface_generic_modport_bad3.out old mode 100755 new mode 100644 index a822cf676..3a09a3cf8 --- a/test_regress/t/t_interface_generic_modport_bad3.out +++ b/test_regress/t/t_interface_generic_modport_bad3.out @@ -1,7 +1,7 @@ -%Error: t/t_interface_generic_modport_bad3.v:18:11: Can't find definition of 'v' in dotted signal: 'a.v' +%Error: t/t_interface_generic_modport_bad3.v:18:11: Can't find definition of 'v' in dotted variable/method: 'a.v' : ... note: In instance 't.genericModule' 18 | if (a.v != 7) $stop; | ^ - ... Known scopes under 'v': + ... Known scopes under 'a': ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_generic_modport_bad3.py b/test_regress/t/t_interface_generic_modport_bad3.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_modport_bad3.py +++ b/test_regress/t/t_interface_generic_modport_bad3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport_bad3.v b/test_regress/t/t_interface_generic_modport_bad3.v index f43f1bc3e..f560e9b86 100644 --- a/test_regress/t/t_interface_generic_modport_bad3.v +++ b/test_regress/t/t_interface_generic_modport_bad3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport_function.py b/test_regress/t/t_interface_generic_modport_function.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_modport_function.py +++ b/test_regress/t/t_interface_generic_modport_function.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport_function.v b/test_regress/t/t_interface_generic_modport_function.v index ccf4c889b..d1100642f 100644 --- a/test_regress/t/t_interface_generic_modport_function.v +++ b/test_regress/t/t_interface_generic_modport_function.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport_function2.py b/test_regress/t/t_interface_generic_modport_function2.py index fda93f1f5..05f4c1c48 100755 --- a/test_regress/t/t_interface_generic_modport_function2.py +++ b/test_regress/t/t_interface_generic_modport_function2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport_function2.v b/test_regress/t/t_interface_generic_modport_function2.v index 27c33b0db..e56818082 100644 --- a/test_regress/t/t_interface_generic_modport_function2.v +++ b/test_regress/t/t_interface_generic_modport_function2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport_function_bad.out b/test_regress/t/t_interface_generic_modport_function_bad.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_interface_generic_modport_function_bad.py b/test_regress/t/t_interface_generic_modport_function_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_modport_function_bad.py +++ b/test_regress/t/t_interface_generic_modport_function_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport_function_bad.v b/test_regress/t/t_interface_generic_modport_function_bad.v index 8ad2d2061..5d38bf185 100644 --- a/test_regress/t/t_interface_generic_modport_function_bad.v +++ b/test_regress/t/t_interface_generic_modport_function_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport_param.py b/test_regress/t/t_interface_generic_modport_param.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_modport_param.py +++ b/test_regress/t/t_interface_generic_modport_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport_param.v b/test_regress/t/t_interface_generic_modport_param.v index e3c9ebc52..e43292ec1 100644 --- a/test_regress/t/t_interface_generic_modport_param.v +++ b/test_regress/t/t_interface_generic_modport_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport_task.py b/test_regress/t/t_interface_generic_modport_task.py index fda93f1f5..05f4c1c48 100755 --- a/test_regress/t/t_interface_generic_modport_task.py +++ b/test_regress/t/t_interface_generic_modport_task.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport_task.v b/test_regress/t/t_interface_generic_modport_task.v index 36b5b54fb..132ccbc2f 100644 --- a/test_regress/t/t_interface_generic_modport_task.v +++ b/test_regress/t/t_interface_generic_modport_task.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport_task2.py b/test_regress/t/t_interface_generic_modport_task2.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_modport_task2.py +++ b/test_regress/t/t_interface_generic_modport_task2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport_task2.v b/test_regress/t/t_interface_generic_modport_task2.v index 958c7fb66..3e6da039b 100644 --- a/test_regress/t/t_interface_generic_modport_task2.v +++ b/test_regress/t/t_interface_generic_modport_task2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_modport_task_bad.out b/test_regress/t/t_interface_generic_modport_task_bad.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_interface_generic_modport_task_bad.py b/test_regress/t/t_interface_generic_modport_task_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_modport_task_bad.py +++ b/test_regress/t/t_interface_generic_modport_task_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_modport_task_bad.v b/test_regress/t/t_interface_generic_modport_task_bad.v index c0b82d74c..aac1d53c5 100644 --- a/test_regress/t/t_interface_generic_modport_task_bad.v +++ b/test_regress/t/t_interface_generic_modport_task_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_normal.py b/test_regress/t/t_interface_generic_normal.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_normal.py +++ b/test_regress/t/t_interface_generic_normal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_normal.v b/test_regress/t/t_interface_generic_normal.v index f6e3f9a61..1678e2074 100644 --- a/test_regress/t/t_interface_generic_normal.v +++ b/test_regress/t/t_interface_generic_normal.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_positional.py b/test_regress/t/t_interface_generic_positional.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_positional.py +++ b/test_regress/t/t_interface_generic_positional.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_positional.v b/test_regress/t/t_interface_generic_positional.v index caf1c4a87..a2726cfb0 100644 --- a/test_regress/t/t_interface_generic_positional.v +++ b/test_regress/t/t_interface_generic_positional.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_submod_param.py b/test_regress/t/t_interface_generic_submod_param.py index fda93f1f5..05f4c1c48 100755 --- a/test_regress/t/t_interface_generic_submod_param.py +++ b/test_regress/t/t_interface_generic_submod_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_submod_param.v b/test_regress/t/t_interface_generic_submod_param.v index 729bcd19d..f9614bb10 100644 --- a/test_regress/t/t_interface_generic_submod_param.v +++ b/test_regress/t/t_interface_generic_submod_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module sub #(parameter P); diff --git a/test_regress/t/t_interface_generic_task.py b/test_regress/t/t_interface_generic_task.py index fda93f1f5..05f4c1c48 100755 --- a/test_regress/t/t_interface_generic_task.py +++ b/test_regress/t/t_interface_generic_task.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_task.v b/test_regress/t/t_interface_generic_task.v index b75c8f164..7e31fcea3 100644 --- a/test_regress/t/t_interface_generic_task.v +++ b/test_regress/t/t_interface_generic_task.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_task2.py b/test_regress/t/t_interface_generic_task2.py index 5b1a2f8cc..a8d4caabb 100755 --- a/test_regress/t/t_interface_generic_task2.py +++ b/test_regress/t/t_interface_generic_task2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_task2.v b/test_regress/t/t_interface_generic_task2.v index 3400e7a4b..3895fa70a 100644 --- a/test_regress/t/t_interface_generic_task2.v +++ b/test_regress/t/t_interface_generic_task2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_generic_task_bad.out b/test_regress/t/t_interface_generic_task_bad.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_interface_generic_task_bad.py b/test_regress/t/t_interface_generic_task_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_generic_task_bad.py +++ b/test_regress/t/t_interface_generic_task_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_generic_task_bad.v b/test_regress/t/t_interface_generic_task_bad.v index 2b5b9ad81..8a23ec5b2 100644 --- a/test_regress/t/t_interface_generic_task_bad.v +++ b/test_regress/t/t_interface_generic_task_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface inf; diff --git a/test_regress/t/t_interface_hidden.py b/test_regress/t/t_interface_hidden.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_hidden.py +++ b/test_regress/t/t_interface_hidden.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_hidden.v b/test_regress/t/t_interface_hidden.v index 04b460d92..bda43b19a 100644 --- a/test_regress/t/t_interface_hidden.v +++ b/test_regress/t/t_interface_hidden.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_interface_import_param.py b/test_regress/t/t_interface_import_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_import_param.py +++ b/test_regress/t/t_interface_import_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_import_param.v b/test_regress/t/t_interface_import_param.v index 4e6860b45..aec218dde 100644 --- a/test_regress/t/t_interface_import_param.v +++ b/test_regress/t/t_interface_import_param.v @@ -3,8 +3,8 @@ // A test that a package import declaration can precede a parameter port list // in an interface declaration. See IEEE 1800-2023 25.3. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 package bus_pkg; diff --git a/test_regress/t/t_interface_initial.py b/test_regress/t/t_interface_initial.py index ada0954ca..affe6d704 100755 --- a/test_regress/t/t_interface_initial.py +++ b/test_regress/t/t_interface_initial.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_initial.v b/test_regress/t/t_interface_initial.v index d1028e3c5..1e7d0e3c7 100644 --- a/test_regress/t/t_interface_initial.v +++ b/test_regress/t/t_interface_initial.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test interface with multiple initial blocks // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Test that interfaces with multiple initial blocks don't cause diff --git a/test_regress/t/t_interface_inl.py b/test_regress/t/t_interface_inl.py index e5a851161..65ab2e2cf 100755 --- a/test_regress/t/t_interface_inl.py +++ b/test_regress/t/t_interface_inl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_localparam.py b/test_regress/t/t_interface_localparam.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_localparam.py +++ b/test_regress/t/t_interface_localparam.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_localparam.v b/test_regress/t/t_interface_localparam.v index e7ba1810c..5957fc49c 100644 --- a/test_regress/t/t_interface_localparam.v +++ b/test_regress/t/t_interface_localparam.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Justin Thiel. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Justin Thiel // SPDX-License-Identifier: CC0-1.0 interface SimpleIntf diff --git a/test_regress/t/t_interface_mismodport_bad.out b/test_regress/t/t_interface_mismodport_bad.out index a8b307c1f..598cdd3df 100644 --- a/test_regress/t/t_interface_mismodport_bad.out +++ b/test_regress/t/t_interface_mismodport_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_interface_mismodport_bad.v:32:12: Can't find definition of 'bad' in dotted signal: 'isub.bad' +%Error: t/t_interface_mismodport_bad.v:32:12: Can't find definition of 'bad' in dotted variable/method: 'isub.bad' 32 | isub.bad = i_value; | ^~~ - ... Known scopes under 'bad': + ... Known scopes under 'isub': ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_interface_mismodport_bad.py b/test_regress/t/t_interface_mismodport_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_mismodport_bad.py +++ b/test_regress/t/t_interface_mismodport_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_mismodport_bad.v b/test_regress/t/t_interface_mismodport_bad.v index f0b6994bd..39747a7bf 100644 --- a/test_regress/t/t_interface_mismodport_bad.v +++ b/test_regress/t/t_interface_mismodport_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface ifc; diff --git a/test_regress/t/t_interface_missing_bad.py b/test_regress/t/t_interface_missing_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_missing_bad.py +++ b/test_regress/t/t_interface_missing_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_missing_bad.v b/test_regress/t/t_interface_missing_bad.v index 062d6f459..e546e14b1 100644 --- a/test_regress/t/t_interface_missing_bad.v +++ b/test_regress/t/t_interface_missing_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Missing interface test // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 // Interface intentionally not defined diff --git a/test_regress/t/t_interface_modport.py b/test_regress/t/t_interface_modport.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_modport.py +++ b/test_regress/t/t_interface_modport.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modport.v b/test_regress/t/t_interface_modport.v index a5cf58414..c4a6580b5 100644 --- a/test_regress/t/t_interface_modport.v +++ b/test_regress/t/t_interface_modport.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface counter_if; diff --git a/test_regress/t/t_interface_modport_bad.py b/test_regress/t/t_interface_modport_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_modport_bad.py +++ b/test_regress/t/t_interface_modport_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modport_bad.v b/test_regress/t/t_interface_modport_bad.v index 3f9c52fcb..b846827ea 100644 --- a/test_regress/t/t_interface_modport_bad.v +++ b/test_regress/t/t_interface_modport_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface ifc; diff --git a/test_regress/t/t_interface_modport_coverage.py b/test_regress/t/t_interface_modport_coverage.py index 76d179c19..b473cbb28 100755 --- a/test_regress/t/t_interface_modport_coverage.py +++ b/test_regress/t/t_interface_modport_coverage.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modport_dir_bad.py b/test_regress/t/t_interface_modport_dir_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_modport_dir_bad.py +++ b/test_regress/t/t_interface_modport_dir_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modport_dir_bad.v b/test_regress/t/t_interface_modport_dir_bad.v index 477215312..c682802b3 100644 --- a/test_regress/t/t_interface_modport_dir_bad.v +++ b/test_regress/t/t_interface_modport_dir_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 interface validData diff --git a/test_regress/t/t_interface_modport_export.py b/test_regress/t/t_interface_modport_export.py index 966dc53da..20b96a7d7 100755 --- a/test_regress/t/t_interface_modport_export.py +++ b/test_regress/t/t_interface_modport_export.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modport_export.v b/test_regress/t/t_interface_modport_export.v index 1369556b7..313b4feaa 100644 --- a/test_regress/t/t_interface_modport_export.v +++ b/test_regress/t/t_interface_modport_export.v @@ -2,8 +2,8 @@ // // A test of the export parameter used with modport // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 interface test_if; diff --git a/test_regress/t/t_interface_modport_expr.out b/test_regress/t/t_interface_modport_expr.out deleted file mode 100644 index 277926b00..000000000 --- a/test_regress/t/t_interface_modport_expr.out +++ /dev/null @@ -1,39 +0,0 @@ -%Error-UNSUPPORTED: t/t_interface_modport_expr.v:15:22: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) - 15 | modport mp1(input .a(sig_a), output .b(sig_b)); - | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_interface_modport_expr.v:15:22: Modport item not found: 'a' - 15 | modport mp1(input .a(sig_a), output .b(sig_b)); - | ^ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_interface_modport_expr.v:15:40: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) - 15 | modport mp1(input .a(sig_a), output .b(sig_b)); - | ^ -%Error: t/t_interface_modport_expr.v:15:40: Modport item not found: 'b' - 15 | modport mp1(input .a(sig_a), output .b(sig_b)); - | ^ -%Error-UNSUPPORTED: t/t_interface_modport_expr.v:16:22: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) - 16 | modport mp2(input .a(sig_c), output .b(sig_d)); - | ^ -%Error: t/t_interface_modport_expr.v:16:22: Modport item not found: 'a' - 16 | modport mp2(input .a(sig_c), output .b(sig_d)); - | ^ -%Error-UNSUPPORTED: t/t_interface_modport_expr.v:16:40: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) - 16 | modport mp2(input .a(sig_c), output .b(sig_d)); - | ^ -%Error: t/t_interface_modport_expr.v:16:40: Modport item not found: 'b' - 16 | modport mp2(input .a(sig_c), output .b(sig_d)); - | ^ -%Error: t/t_interface_modport_expr.v:28:18: Can't find definition of 'a' in dotted variable/method: 'i.a' - 28 | assign i.b = i.a; - | ^ -%Error: t/t_interface_modport_expr.v:28:12: Can't find definition of 'b' in dotted variable/method: 'i.b' - 28 | assign i.b = i.a; - | ^ -%Error: t/t_interface_modport_expr.v:22:18: Can't find definition of 'a' in dotted variable/method: 'i.a' - 22 | assign i.b = i.a; - | ^ -%Error: t/t_interface_modport_expr.v:22:12: Can't find definition of 'b' in dotted variable/method: 'i.b' - 22 | assign i.b = i.a; - | ^ -%Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_expr.py b/test_regress/t/t_interface_modport_expr.py index 7a0f86f5e..6fe7d000c 100755 --- a/test_regress/t/t_interface_modport_expr.py +++ b/test_regress/t/t_interface_modport_expr.py @@ -1,21 +1,18 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') -test.compile(fails=test.vlt_all, - expect_filename=test.golden_filename, - verilator_flags2=["--binary"]) +test.compile(verilator_flags2=["--binary"]) -if not test.vlt_all: - test.execute() +test.execute() test.passes() diff --git a/test_regress/t/t_interface_modport_expr.v b/test_regress/t/t_interface_modport_expr.v index 9c69ed8c8..3e2f39689 100644 --- a/test_regress/t/t_interface_modport_expr.v +++ b/test_regress/t/t_interface_modport_expr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off @@ -9,11 +9,18 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); // verilog_format: on -interface my_if; - logic sig_a, sig_b, sig_c, sig_d; +interface my_if #(parameter WIDTH = 1); + logic [WIDTH-1:0] sig_a, sig_b, sig_c, sig_d; + logic [WIDTH-1:0] sig_e, sig_f; + // Multiple expressions same direction + logic [WIDTH-1:0] m1, m2, m3; modport mp1(input .a(sig_a), output .b(sig_b)); modport mp2(input .a(sig_c), output .b(sig_d)); + // Mixed regular and expression items + modport mp3(input sig_e, output .f(sig_f)); + // Multiple expressions with same direction + modport mp4(input .in1(m1), input .in2(m2), output .out(m3)); endinterface module mod1 ( @@ -28,17 +35,35 @@ module mod2 ( assign i.b = i.a; endmodule -module top (); - my_if myIf (); - assign myIf.sig_a = 1'b1, myIf.sig_c = 1'b1; +module mod3 ( + my_if.mp3 i +); + assign i.f = i.sig_e; // sig_e is regular, f is expression +endmodule - mod1 mod1Instance (myIf); - mod2 mod2Instance (myIf); +module mod4 ( + my_if.mp4 i +); + assign i.out = i.in1 ^ i.in2; +endmodule + +module top (); + my_if #(.WIDTH(8)) myIf (); + assign myIf.sig_a = 8'h42, myIf.sig_c = 8'hAB; + assign myIf.sig_e = 8'hCD; + assign myIf.m1 = 8'hF0, myIf.m2 = 8'h0F; + + mod1 mod1i (myIf.mp1); + mod2 mod2i (myIf.mp2); + mod3 mod3i (myIf.mp3); + mod4 mod4i (myIf.mp4); initial begin #1; - `checkh(myIf.sig_a, myIf.sig_b); - `checkh(myIf.sig_c, myIf.sig_d); + `checkh(myIf.sig_b, 8'h42); // mp1: b = a + `checkh(myIf.sig_d, 8'hAB); // mp2: b = a + `checkh(myIf.sig_f, 8'hCD); // mp3: f = sig_e + `checkh(myIf.m3, 8'hFF); // mp4: out = in1 ^ in2 #1; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_interface_modport_expr_array.out b/test_regress/t/t_interface_modport_expr_array.out new file mode 100644 index 000000000..f258f18f5 --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_array.out @@ -0,0 +1,43 @@ +%Error-UNSUPPORTED: t/t_interface_modport_expr_array.v:26:15: Unsupported: Modport expression with part select (IEEE 1800-2023 25.5.4) + 26 | output .ch0_wr(ch[0].wr), + | ^~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: t/t_interface_modport_expr_array.v:26:15: Modport item not found: 'ch0_wr' + 26 | output .ch0_wr(ch[0].wr), + | ^~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error-UNSUPPORTED: t/t_interface_modport_expr_array.v:27:14: Unsupported: Modport expression with part select (IEEE 1800-2023 25.5.4) + 27 | input .ch0_rd(ch[0].rd), + | ^~~~~~ +%Error: t/t_interface_modport_expr_array.v:27:14: Modport item not found: 'ch0_rd' + 27 | input .ch0_rd(ch[0].rd), + | ^~~~~~ +%Error-UNSUPPORTED: t/t_interface_modport_expr_array.v:28:15: Unsupported: Modport expression with part select (IEEE 1800-2023 25.5.4) + 28 | output .ch1_wr(ch[1].wr), + | ^~~~~~ +%Error: t/t_interface_modport_expr_array.v:28:15: Modport item not found: 'ch1_wr' + 28 | output .ch1_wr(ch[1].wr), + | ^~~~~~ +%Error-UNSUPPORTED: t/t_interface_modport_expr_array.v:29:14: Unsupported: Modport expression with part select (IEEE 1800-2023 25.5.4) + 29 | input .ch1_rd(ch[1].rd) + | ^~~~~~ +%Error: t/t_interface_modport_expr_array.v:29:14: Modport item not found: 'ch1_rd' + 29 | input .ch1_rd(ch[1].rd) + | ^~~~~~ +%Error: t/t_interface_modport_expr_array.v:37:29: Can't find definition of 'ch0_wr' in dotted variable/method: 'port.ch0_wr' + 37 | assign port.ch0_rd = port.ch0_wr + 8'h10; + | ^~~~~~ + ... Known scopes under 'port': +%Error: t/t_interface_modport_expr_array.v:37:15: Can't find definition of 'ch0_rd' in dotted variable/method: 'port.ch0_rd' + 37 | assign port.ch0_rd = port.ch0_wr + 8'h10; + | ^~~~~~ + ... Known scopes under 'port': +%Error: t/t_interface_modport_expr_array.v:38:29: Can't find definition of 'ch1_wr' in dotted variable/method: 'port.ch1_wr' + 38 | assign port.ch1_rd = port.ch1_wr + 8'h20; + | ^~~~~~ + ... Known scopes under 'port': +%Error: t/t_interface_modport_expr_array.v:38:15: Can't find definition of 'ch1_rd' in dotted variable/method: 'port.ch1_rd' + 38 | assign port.ch1_rd = port.ch1_wr + 8'h20; + | ^~~~~~ + ... Known scopes under 'port': +%Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_expr_array.py b/test_regress/t/t_interface_modport_expr_array.py new file mode 100755 index 000000000..3bacbbfc8 --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_array.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, + expect_filename=test.golden_filename, + verilator_flags2=["--binary"]) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_expr_array.v b/test_regress/t/t_interface_modport_expr_array.v new file mode 100644 index 000000000..30cca12db --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_array.v @@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +// Test modport expressions with arrayed interface instances (unsupported) + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface base_if; + logic [7:0] wr; + logic [7:0] rd; + modport host(output wr, input rd); + modport dev(input wr, output rd); +endinterface + +interface container_if; + base_if ch[2] (); + + // Modport expressions accessing arrayed interface instances + modport mp( + output .ch0_wr(ch[0].wr), + input .ch0_rd(ch[0].rd), + output .ch1_wr(ch[1].wr), + input .ch1_rd(ch[1].rd) + ); +endinterface + +module consumer ( + container_if.mp port +); + // Access through modport expression virtual ports + assign port.ch0_rd = port.ch0_wr + 8'h10; + assign port.ch1_rd = port.ch1_wr + 8'h20; +endmodule + +module top; + container_if cont (); + + consumer m_cons (.port(cont)); + + initial begin + cont.ch[0].wr = 8'hA0; + cont.ch[1].wr = 8'hB0; + #1; + `checkh(cont.ch[0].rd, 8'hB0); + `checkh(cont.ch[1].rd, 8'hD0); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_modport_expr_bad.out b/test_regress/t/t_interface_modport_expr_bad.out new file mode 100644 index 000000000..2754d3ad8 --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_bad.out @@ -0,0 +1,18 @@ +%Error: t/t_interface_modport_expr_bad.v:10:22: Can't find modport expression target: 'nonexist.sig' + 10 | modport mp1(input .in(nonexist.sig)); + | ^~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_interface_modport_expr_bad.v:10:22: Modport item not found: 'in' + 10 | modport mp1(input .in(nonexist.sig)); + | ^~ +%Error-UNSUPPORTED: t/t_interface_modport_expr_bad.v:12:22: Unsupported: Complex modport expression (IEEE 1800-2023 25.5.4) + 12 | modport mp2(input .in(~a)); + | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: t/t_interface_modport_expr_bad.v:12:22: Modport item not found: 'in' + 12 | modport mp2(input .in(~a)); + | ^~ +%Error: t/t_interface_modport_expr_bad.v:10:25: Can't find definition of scope/variable: 'nonexist' + 10 | modport mp1(input .in(nonexist.sig)); + | ^~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_expr_bad.py b/test_regress/t/t_interface_modport_expr_bad.py new file mode 100755 index 000000000..3bacbbfc8 --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_bad.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, + expect_filename=test.golden_filename, + verilator_flags2=["--binary"]) + +if not test.vlt_all: + test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_expr_bad.v b/test_regress/t/t_interface_modport_expr_bad.v new file mode 100644 index 000000000..2f9c2b26f --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_bad.v @@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +interface iface; + logic a, b; + // Dotted path to non-existent signal + modport mp1(input .in(nonexist.sig)); + // Complex expression not supported as modport expression + modport mp2(input .in(~a)); +endinterface + +module t; + iface intf (); +endmodule diff --git a/test_regress/t/t_interface_modport_expr_hier.py b/test_regress/t/t_interface_modport_expr_hier.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_hier.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_expr_hier.v b/test_regress/t/t_interface_modport_expr_hier.v new file mode 100644 index 000000000..cfe7e8be4 --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_hier.v @@ -0,0 +1,160 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +// Test modport expressions with hierarchical module instantiation + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +// ============================================================ +// Scenario A: Single-level hierarchy + expression modport +// ============================================================ + +interface if_a; + logic [7:0] raw_in; + logic [7:0] raw_out; + modport mp(input .data_in(raw_in), output .data_out(raw_out)); +endinterface + +// Leaf module: uses modport expression virtual ports +module a_leaf ( + if_a.mp port +); + assign port.data_out = port.data_in + 8'h10; +endmodule + +// Mid-level module: passes interface down +module a_mid ( + if_a.mp port +); + a_leaf u_leaf (.port(port)); +endmodule + +// ============================================================ +// Scenario B: 2-level deep hierarchy +// ============================================================ + +interface if_b; + logic [15:0] x; + logic [15:0] y; + modport mp(input .alpha(x), output .beta(y)); +endinterface + +module b_leaf ( + if_b.mp port +); + assign port.beta = port.alpha ^ 16'hFFFF; +endmodule + +module b_mid ( + if_b.mp port +); + b_leaf u_leaf (.port(port)); +endmodule + +module b_top_wrap ( + if_b.mp port +); + b_mid u_mid (.port(port)); +endmodule + +// ============================================================ +// Scenario C: Nested interface + expression modport + hierarchy +// ============================================================ + +interface if_c_inner; + logic [7:0] val; +endinterface + +interface if_c_outer; + if_c_inner inner (); + modport mp(output .w(inner.val), input .r(inner.val)); +endinterface + +module c_leaf ( + if_c_outer.mp port +); + assign port.w = 8'hBE; + wire [7:0] c_read = port.r; +endmodule + +module c_mid ( + if_c_outer.mp port +); + c_leaf u_leaf (.port(port)); +endmodule + +// ============================================================ +// Scenario D: Multiple instances of same wrapper (no cross-talk) +// ============================================================ + +interface if_d; + logic [7:0] din; + logic [7:0] dout; + modport mp(input .vi(din), output .vo(dout)); +endinterface + +module d_leaf ( + if_d.mp port +); + assign port.vo = port.vi + 8'h01; +endmodule + +module d_mid ( + if_d.mp port +); + d_leaf u_leaf (.port(port)); +endmodule + +// ============================================================ +// Top module +// ============================================================ + +module top; + + // --- Scenario A --- + if_a ifa (); + a_mid u_a (.port(ifa)); + + // --- Scenario B --- + if_b ifb (); + b_top_wrap u_b (.port(ifb)); + + // --- Scenario C --- + if_c_outer ifc (); + c_mid u_c (.port(ifc)); + + // --- Scenario D --- + if_d ifd (); + d_mid u_d (.port(ifd)); + + initial begin + // Scenario A: single-level hierarchy + ifa.raw_in = 8'h20; + #1; + `checkh(ifa.raw_out, 8'h30); + + // Scenario B: 2-level deep hierarchy + ifb.x = 16'h1234; + #1; + `checkh(ifb.y, 16'hEDCB); + + // Scenario C: nested interface + hierarchy + #1; + `checkh(ifc.inner.val, 8'hBE); + `checkh(u_c.u_leaf.c_read, 8'hBE); + + // Scenario D: single instance through hierarchy + ifd.din = 8'h10; + #1; + `checkh(ifd.dout, 8'h11); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_modport_expr_hier_noinl.py b/test_regress/t/t_interface_modport_expr_hier_noinl.py new file mode 100755 index 000000000..092cc4a23 --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_hier_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport_expr_hier.v" + +test.compile(verilator_flags2=["--binary", "-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_expr_nested.py b/test_regress/t/t_interface_modport_expr_nested.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_nested.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_expr_nested.v b/test_regress/t/t_interface_modport_expr_nested.v new file mode 100644 index 000000000..a81a9d0ca --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_nested.v @@ -0,0 +1,132 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +// Test modport expressions with nested interfaces + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface base_reg_if; + logic [7:0] wr; + logic [7:0] rd; + modport host(output wr, input rd); + modport dev(input wr, output rd); +endinterface + +interface example_reg_if; + logic [15:0] wr; + logic [15:0] rd; + modport host(output wr, input rd); + modport dev(input wr, output rd); +endinterface + +interface app_reg_if; + base_reg_if base (); + example_reg_if example (); + + // Use modport expressions to expose nested interface signals + modport host( + output .base_wr(base.wr), + input .base_rd(base.rd), + output .example_wr(example.wr), + input .example_rd(example.rd) + ); + modport dev( + input .base_wr(base.wr), + output .base_rd(base.rd), + input .example_wr(example.wr), + output .example_rd(example.rd) + ); +endinterface + +// Deep nesting test (3 levels) +interface inner_if; + logic [7:0] data; + modport producer(output data); + modport consumer(input data); +endinterface + +interface middle_if; + inner_if inner (); +endinterface + +interface outer_if; + middle_if middle (); + + // 3-level deep modport expression + modport mp(output .deep_out(middle.inner.data), input .deep_in(middle.inner.data)); +endinterface + +module deep_consumer ( + outer_if.mp port +); + assign port.deep_out = 8'hDE; + // Verify reading through deep_in virtual port + wire [7:0] deep_in_val = port.deep_in; +endmodule + +// 4-level deep nesting test +interface level1_if; + logic [7:0] val; +endinterface + +interface level2_if; + level1_if l1 (); +endinterface + +interface level3_if; + level2_if l2 (); +endinterface + +interface level4_if; + level3_if l3 (); + + // 4-level deep modport expression + modport mp(output .deep4_w(l3.l2.l1.val), input .deep4_r(l3.l2.l1.val)); +endinterface + +module deep4_consumer ( + level4_if.mp port +); + assign port.deep4_w = 8'h4D; + wire [7:0] deep4_read = port.deep4_r; +endmodule + +module app_consumer ( + app_reg_if.dev i_app_regs +); + // Access through modport expression virtual ports + assign i_app_regs.base_rd = i_app_regs.base_wr + 8'h1; + assign i_app_regs.example_rd = i_app_regs.example_wr + 16'h1; +endmodule + +module top; + app_reg_if app_regs (); + outer_if outer (); + level4_if lev4 (); + + app_consumer m_app (.i_app_regs(app_regs)); + deep_consumer m_deep (.port(outer)); + deep4_consumer m_deep4 (.port(lev4)); + + initial begin + app_regs.base.wr = 8'hAB; + app_regs.example.wr = 16'hCDEF; + #1; + `checkh(app_regs.base.rd, 8'hAC); + `checkh(app_regs.example.rd, 16'hCDF0); + // Verify 3-level deep nesting + `checkh(outer.middle.inner.data, 8'hDE); + `checkh(m_deep.deep_in_val, 8'hDE); + // Verify 4-level deep nesting + `checkh(lev4.l3.l2.l1.val, 8'h4D); + `checkh(m_deep4.deep4_read, 8'h4D); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_modport_expr_nested_noinl.py b/test_regress/t/t_interface_modport_expr_nested_noinl.py new file mode 100755 index 000000000..c8b950dc5 --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_nested_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport_expr_nested.v" + +test.compile(verilator_flags2=["--binary", "-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_expr_noinl.py b/test_regress/t/t_interface_modport_expr_noinl.py new file mode 100755 index 000000000..63982213e --- /dev/null +++ b/test_regress/t/t_interface_modport_expr_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport_expr.v" + +test.compile(verilator_flags2=["--binary", "-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_expr_partsel.out b/test_regress/t/t_interface_modport_expr_partsel.out index deb4ee46c..8ebfe6774 100644 --- a/test_regress/t/t_interface_modport_expr_partsel.out +++ b/test_regress/t/t_interface_modport_expr_partsel.out @@ -1,4 +1,4 @@ -%Error-UNSUPPORTED: t/t_interface_modport_expr_partsel.v:16:22: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) +%Error-UNSUPPORTED: t/t_interface_modport_expr_partsel.v:16:22: Unsupported: Modport expression with part select (IEEE 1800-2023 25.5.4) 16 | modport mp1(input .in(a[7:0]), output .out(b)); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest @@ -6,34 +6,18 @@ 16 | modport mp1(input .in(a[7:0]), output .out(b)); | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_interface_modport_expr_partsel.v:16:42: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) - 16 | modport mp1(input .in(a[7:0]), output .out(b)); - | ^~~ -%Error: t/t_interface_modport_expr_partsel.v:16:42: Modport item not found: 'out' - 16 | modport mp1(input .in(a[7:0]), output .out(b)); - | ^~~ -%Error-UNSUPPORTED: t/t_interface_modport_expr_partsel.v:17:22: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) +%Error-UNSUPPORTED: t/t_interface_modport_expr_partsel.v:17:22: Unsupported: Modport expression with part select (IEEE 1800-2023 25.5.4) 17 | modport mp2(input .in(a[15:8]), output .out(c)); | ^~ %Error: t/t_interface_modport_expr_partsel.v:17:22: Modport item not found: 'in' 17 | modport mp2(input .in(a[15:8]), output .out(c)); | ^~ -%Error-UNSUPPORTED: t/t_interface_modport_expr_partsel.v:17:43: Unsupported: Modport expressions (IEEE 1800-2023 25.5.4) - 17 | modport mp2(input .in(a[15:8]), output .out(c)); - | ^~~ -%Error: t/t_interface_modport_expr_partsel.v:17:43: Modport item not found: 'out' - 17 | modport mp2(input .in(a[15:8]), output .out(c)); - | ^~~ %Error: t/t_interface_modport_expr_partsel.v:29:21: Can't find definition of 'in' in dotted variable/method: 'i.in' 29 | assign i.out = ~i.in; | ^~ -%Error: t/t_interface_modport_expr_partsel.v:29:12: Can't find definition of 'out' in dotted variable/method: 'i.out' - 29 | assign i.out = ~i.in; - | ^~~ + ... Known scopes under 'i': %Error: t/t_interface_modport_expr_partsel.v:23:20: Can't find definition of 'in' in dotted variable/method: 'i.in' 23 | assign i.out = i.in; | ^~ -%Error: t/t_interface_modport_expr_partsel.v:23:12: Can't find definition of 'out' in dotted variable/method: 'i.out' - 23 | assign i.out = i.in; - | ^~~ + ... Known scopes under 'i': %Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_expr_partsel.py b/test_regress/t/t_interface_modport_expr_partsel.py index 7a0f86f5e..3bacbbfc8 100755 --- a/test_regress/t/t_interface_modport_expr_partsel.py +++ b/test_regress/t/t_interface_modport_expr_partsel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modport_expr_partsel.v b/test_regress/t/t_interface_modport_expr_partsel.v index b8b8f7f70..832b2c697 100644 --- a/test_regress/t/t_interface_modport_expr_partsel.v +++ b/test_regress/t/t_interface_modport_expr_partsel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_interface_modport_hier.py b/test_regress/t/t_interface_modport_hier.py new file mode 100755 index 000000000..3fb25347f --- /dev/null +++ b/test_regress/t/t_interface_modport_hier.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +# Test hierarchical access through modport interface ports +# Related to Issue #5941 and #2656 + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_hier.v b/test_regress/t/t_interface_modport_hier.v new file mode 100644 index 000000000..ed68f6d10 --- /dev/null +++ b/test_regress/t/t_interface_modport_hier.v @@ -0,0 +1,146 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +// Test for Issue #5941 and #2656: Modport interface field access via hierarchy +// Tests: +// - Single-level and deep hierarchical access +// - Multiple interface instances (same modport type, different data) +// - Interface arrays + +interface bus_if ( + input logic clk +); + logic [7:0] data; + modport slave(output data, input clk); +endinterface + +// l1 module with the actual logic +module l1_mod ( + bus_if.slave bus +); + always_ff @(posedge bus.clk) bus.data <= 8'h5A; +endmodule + +// l0 module wrapping l1 module +module l0_mod ( + bus_if.slave bus +); + l1_mod l1_inst (bus); +endmodule + +// Modules for testing multiple instances with same modport +module mod_aa ( + bus_if.slave bus +); + assign bus.data = 8'hAA; +endmodule + +module mod_bb ( + bus_if.slave bus +); + assign bus.data = 8'hBB; +endmodule + +// Module for testing interface arrays +module array_mod ( + bus_if.slave bus[2] +); + always_ff @(posedge bus[0].clk) begin + bus[0].data <= 8'hA0; + bus[1].data <= 8'hA1; + end +endmodule + +module t ( + input clk +); + + integer cyc = 0; + + // Deep hierarchy test + bus_if bus (clk); + l0_mod l0_inst (bus); + + // Multiple instances test + bus_if bus_a (clk); + bus_if bus_b (clk); + mod_aa inst_aa (bus_a); + mod_bb inst_bb (bus_b); + + // Array test + bus_if bus_arr[2] (clk); + array_mod array_inst (bus_arr); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + // === Deep hierarchy tests === + $display("bus.data = %h (direct)", bus.data); + $display("l0_inst.bus.data = %h (single-level)", l0_inst.bus.data); + $display("l0_inst.l1_inst.bus.data = %h (deep)", l0_inst.l1_inst.bus.data); + + if (bus.data !== 8'h5A) begin + $display("%%Error: bus.data = %h, expected 5A", bus.data); + $stop; + end + if (l0_inst.bus.data !== 8'h5A) begin + $display("%%Error: l0_inst.bus.data = %h, expected 5A", l0_inst.bus.data); + $stop; + end + if (l0_inst.l1_inst.bus.data !== 8'h5A) begin + $display("%%Error: l0_inst.l1_inst.bus.data = %h, expected 5A", l0_inst.l1_inst.bus.data); + $stop; + end + if (l0_inst.bus.clk !== clk) begin + $display("%%Error: l0_inst.bus.clk mismatch"); + $stop; + end + if (l0_inst.l1_inst.bus.clk !== clk) begin + $display("%%Error: l0_inst.l1_inst.bus.clk mismatch"); + $stop; + end + + // === Multiple instances tests (bug #2656) === + $display("inst_aa.bus.data = %h", inst_aa.bus.data); + $display("inst_bb.bus.data = %h", inst_bb.bus.data); + + if (inst_aa.bus.data !== 8'hAA) begin + $display("%%Error: inst_aa.bus.data = %h, expected AA", inst_aa.bus.data); + $stop; + end + if (inst_bb.bus.data !== 8'hBB) begin + $display("%%Error: inst_bb.bus.data = %h, expected BB", inst_bb.bus.data); + $stop; + end + + // === Interface array tests (bug #2656) === + $display("bus_arr[0].data = %h (direct)", bus_arr[0].data); + $display("bus_arr[1].data = %h (direct)", bus_arr[1].data); + $display("array_inst.bus[0].data = %h (hierarchical)", array_inst.bus[0].data); + $display("array_inst.bus[1].data = %h (hierarchical)", array_inst.bus[1].data); + + if (bus_arr[0].data !== 8'hA0) begin + $display("%%Error: bus_arr[0].data = %h, expected A0", bus_arr[0].data); + $stop; + end + if (bus_arr[1].data !== 8'hA1) begin + $display("%%Error: bus_arr[1].data = %h, expected A1", bus_arr[1].data); + $stop; + end + if (array_inst.bus[0].data !== 8'hA0) begin + $display("%%Error: array_inst.bus[0].data = %h, expected A0", array_inst.bus[0].data); + $stop; + end + if (array_inst.bus[1].data !== 8'hA1) begin + $display("%%Error: array_inst.bus[1].data = %h, expected A1", array_inst.bus[1].data); + $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_interface_modport_hier_noinl.py b/test_regress/t/t_interface_modport_hier_noinl.py new file mode 100755 index 000000000..0950605f0 --- /dev/null +++ b/test_regress/t/t_interface_modport_hier_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_modport_hier.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_modport_import.py b/test_regress/t/t_interface_modport_import.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_modport_import.py +++ b/test_regress/t/t_interface_modport_import.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modport_import.v b/test_regress/t/t_interface_modport_import.v index 6fed88a03..681513633 100644 --- a/test_regress/t/t_interface_modport_import.v +++ b/test_regress/t/t_interface_modport_import.v @@ -2,8 +2,8 @@ // // A test of the import parameter used with modport // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 interface test_if; diff --git a/test_regress/t/t_interface_modport_import_export_list.py b/test_regress/t/t_interface_modport_import_export_list.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_interface_modport_import_export_list.py +++ b/test_regress/t/t_interface_modport_import_export_list.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modport_import_export_list.v b/test_regress/t/t_interface_modport_import_export_list.v index a44673327..398896f5e 100644 --- a/test_regress/t/t_interface_modport_import_export_list.v +++ b/test_regress/t/t_interface_modport_import_export_list.v @@ -2,8 +2,8 @@ // // Modport import export list test // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Goekce Aydos. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Goekce Aydos // SPDX-License-Identifier: CC0-1.0 interface intf; diff --git a/test_regress/t/t_interface_modport_import_noinl.py b/test_regress/t/t_interface_modport_import_noinl.py index 799af8f28..83452502c 100755 --- a/test_regress/t/t_interface_modport_import_noinl.py +++ b/test_regress/t/t_interface_modport_import_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modport_inl.py b/test_regress/t/t_interface_modport_inl.py index 06444df8c..664b9c9a1 100755 --- a/test_regress/t/t_interface_modport_inl.py +++ b/test_regress/t/t_interface_modport_inl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modport_noinl.py b/test_regress/t/t_interface_modport_noinl.py index cd95c2a08..1c56d9b01 100755 --- a/test_regress/t/t_interface_modport_noinl.py +++ b/test_regress/t/t_interface_modport_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modportlist.py b/test_regress/t/t_interface_modportlist.py index 69ecdb152..1d54c793f 100755 --- a/test_regress/t/t_interface_modportlist.py +++ b/test_regress/t/t_interface_modportlist.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_modportlist.v b/test_regress/t/t_interface_modportlist.v index 7391bfcb0..dcab0b03b 100644 --- a/test_regress/t/t_interface_modportlist.v +++ b/test_regress/t/t_interface_modportlist.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Adrian Wise. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Adrian Wise // SPDX-License-Identifier: CC0-1.0 //bug1246 diff --git a/test_regress/t/t_interface_mp_func.py b/test_regress/t/t_interface_mp_func.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_mp_func.py +++ b/test_regress/t/t_interface_mp_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_mp_func.v b/test_regress/t/t_interface_mp_func.v index 5148b46a1..be8089001 100644 --- a/test_regress/t/t_interface_mp_func.v +++ b/test_regress/t/t_interface_mp_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface pads_if(); diff --git a/test_regress/t/t_interface_mp_func_noinl.py b/test_regress/t/t_interface_mp_func_noinl.py index eaddfaae9..1e22253e7 100755 --- a/test_regress/t/t_interface_mp_func_noinl.py +++ b/test_regress/t/t_interface_mp_func_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_nansi.py b/test_regress/t/t_interface_nansi.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_nansi.py +++ b/test_regress/t/t_interface_nansi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_nansi.v b/test_regress/t/t_interface_nansi.v index ef9d2d418..251b9af62 100644 --- a/test_regress/t/t_interface_nansi.v +++ b/test_regress/t/t_interface_nansi.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 interface iface(input logic clk); diff --git a/test_regress/t/t_interface_ndup_member.py b/test_regress/t/t_interface_ndup_member.py index cca4c9e73..d6d35e7fd 100755 --- a/test_regress/t/t_interface_ndup_member.py +++ b/test_regress/t/t_interface_ndup_member.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ndup_member.v b/test_regress/t/t_interface_ndup_member.v index 05371c9a9..c5b07ab3b 100644 --- a/test_regress/t/t_interface_ndup_member.v +++ b/test_regress/t/t_interface_ndup_member.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface backdoor_if; diff --git a/test_regress/t/t_interface_nest.py b/test_regress/t/t_interface_nest.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_nest.py +++ b/test_regress/t/t_interface_nest.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_nest.v b/test_regress/t/t_interface_nest.v index f4eb0d643..176bb5b45 100644 --- a/test_regress/t/t_interface_nest.v +++ b/test_regress/t/t_interface_nest.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2017 // SPDX-License-Identifier: CC0-1.0 interface if1; diff --git a/test_regress/t/t_interface_nest_noinl.py b/test_regress/t/t_interface_nest_noinl.py index bd3c559ac..8105695d5 100755 --- a/test_regress/t/t_interface_nest_noinl.py +++ b/test_regress/t/t_interface_nest_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_nested_port.py b/test_regress/t/t_interface_nested_port.py new file mode 100755 index 000000000..46d1fe4c0 --- /dev/null +++ b/test_regress/t/t_interface_nested_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_nested_port.v b/test_regress/t/t_interface_nested_port.v new file mode 100644 index 000000000..37696caee --- /dev/null +++ b/test_regress/t/t_interface_nested_port.v @@ -0,0 +1,372 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +// Issue #5066 - Combined test for nested interface ports with parameters +// +// Tests all parameter patterns in a 5-deep hierarchy: +// - Derived: W doubles at each level (L3=L4*2, L2A=L3*2, L1=L2*2) +// - Hard-coded: L2B.W=8 regardless of parent +// - Passthrough: L0A_W flows unchanged from top to L0A +// - Default: L0B uses default W=8 +// +// With TOP_W=4, L0A_W=16: +// L4(W=4) -> L3(W=8) -> L2A(W=16) -> L1(W=32) -> L0A(W=16), L0B(W=8) +// -> L2B(W=8) -> L1(W=16) -> L0A(W=16), L0B(W=8) + +interface l0_if #( + parameter int W = 8 +); + logic [W-1:0] tb_in; + logic [W-1:0] dut_out; +endinterface + +interface l1_if #( + parameter int W = 8, + parameter int L0A_W = 8 +); + logic [W-1:0] tb_in; + logic [W-1:0] dut_out; + l0_if #(L0A_W) l0a (); // passthrough + l0_if l0b (); // default +endinterface + +interface l2_if #( + parameter int W = 8, + parameter int L0A_W = 8 +); + logic [W-1:0] tb_in; + logic [W-1:0] dut_out; + l1_if #(W * 2, L0A_W) l1 (); // derived +endinterface + +interface l3_if #( + parameter int W = 8, + parameter int L0A_W = 8 +); + logic [W-1:0] tb_in; + logic [W-1:0] dut_out; + l2_if #(W * 2, L0A_W) l2a (); // derived + l2_if #(8, L0A_W) l2b (); // hard-coded +endinterface + +interface l4_if #( + parameter int W = 8, + parameter int L0A_W = 8 +); + logic [W-1:0] tb_in; + logic [W-1:0] dut_out; + l3_if #(W * 2, L0A_W) l3 (); // derived +endinterface + +// Handlers use unparameterized interface ports with parameterized output widths + +module l0_handler #( + parameter int W = 8 +) ( + input logic clk, + l0_if l0, + output logic [W-1:0] dout +); + always_ff @(posedge clk) l0.dut_out <= l0.tb_in ^ W'('1); + assign dout = l0.dut_out; +endmodule + +module l1_reader #( + parameter int W = 8 +) ( + l1_if l1, + output logic [W-1:0] dout +); + assign dout = l1.dut_out; +endmodule + +module l1_driver #( + parameter int W = 8 +) ( + input logic clk, + l1_if l1 +); + always_ff @(posedge clk) l1.dut_out <= l1.tb_in ^ W'('1); +endmodule + +module l1_handler #( + parameter int W = 8, + parameter int L0A_W = 8 +) ( + input logic clk, + l1_if l1, + output logic [W-1:0] l1_dout, + output logic [L0A_W-1:0] l0a_dout, + output logic [7:0] l0b_dout +); + // Use reader/driver submodules instead of direct access + l1_reader #(W) m_rdr ( + .l1(l1), + .dout(l1_dout) + ); + l1_driver #(W) m_drv ( + .clk(clk), + .l1(l1) + ); + + // Still instantiate l0_handlers for nested ports + l0_handler #(L0A_W) m_l0a ( + .clk(clk), + .l0(l1.l0a), + .dout(l0a_dout) + ); + l0_handler #(8) m_l0b ( + .clk(clk), + .l0(l1.l0b), + .dout(l0b_dout) + ); +endmodule + +module l2_handler #( + parameter int W = 8, + parameter int L0A_W = 8 +) ( + input logic clk, + l2_if l2, + output logic [W-1:0] l2_dout, + output logic [W*2-1:0] l1_dout, + output logic [L0A_W-1:0] l0a_dout, + output logic [7:0] l0b_dout +); + always_ff @(posedge clk) l2.dut_out <= l2.tb_in ^ W'('1); + assign l2_dout = l2.dut_out; + l1_handler #(W * 2, L0A_W) m_l1 ( + .clk(clk), + .l1(l2.l1), + .l1_dout(l1_dout), + .l0a_dout(l0a_dout), + .l0b_dout(l0b_dout) + ); +endmodule + +module l3_reader #( + parameter int W = 8 +) ( + l3_if l3, + output logic [W-1:0] dout +); + assign dout = l3.dut_out; +endmodule + +module l3_driver #( + parameter int W = 8 +) ( + input logic clk, + l3_if l3 +); + always_ff @(posedge clk) l3.dut_out <= l3.tb_in ^ W'('1); +endmodule + +module l3_handler #( + parameter int W = 8, + parameter int L0A_W = 8 +) ( + input logic clk, + l3_if l3, + output logic [W-1:0] l3_dout, + output logic [W*2-1:0] l2a_dout, + output logic [W*4-1:0] l1_2a_dout, + output logic [L0A_W-1:0] l0a_2a_dout, + output logic [7:0] l0b_2a_dout, + output logic [7:0] l2b_dout, + output logic [15:0] l1_2b_dout, + output logic [L0A_W-1:0] l0a_2b_dout, + output logic [7:0] l0b_2b_dout +); + // Use reader/driver submodules instead of direct access + l3_reader #(W) m_rdr ( + .l3(l3), + .dout(l3_dout) + ); + l3_driver #(W) m_drv ( + .clk(clk), + .l3(l3) + ); + + // Still instantiate l2_handlers for nested ports + l2_handler #(W * 2, L0A_W) m_l2a ( + .clk(clk), + .l2(l3.l2a), + .l2_dout(l2a_dout), + .l1_dout(l1_2a_dout), + .l0a_dout(l0a_2a_dout), + .l0b_dout(l0b_2a_dout) + ); + l2_handler #(8, L0A_W) m_l2b ( + .clk(clk), + .l2(l3.l2b), + .l2_dout(l2b_dout), + .l1_dout(l1_2b_dout), + .l0a_dout(l0a_2b_dout), + .l0b_dout(l0b_2b_dout) + ); +endmodule + +module l4_handler #( + parameter int W = 8, + parameter int L0A_W = 8 +) ( + input logic clk, + l4_if l4, + output logic [W-1:0] l4_dout, + output logic [W*2-1:0] l3_dout, + output logic [W*4-1:0] l2a_dout, + output logic [W*8-1:0] l1_2a_dout, + output logic [L0A_W-1:0] l0a_2a_dout, + output logic [7:0] l0b_2a_dout, + output logic [7:0] l2b_dout, + output logic [15:0] l1_2b_dout, + output logic [L0A_W-1:0] l0a_2b_dout, + output logic [7:0] l0b_2b_dout +); + always_ff @(posedge clk) l4.dut_out <= l4.tb_in ^ W'('1); + assign l4_dout = l4.dut_out; + l3_handler #(W * 2, L0A_W) m_l3 ( + .clk(clk), + .l3(l4.l3), + .l3_dout(l3_dout), + .l2a_dout(l2a_dout), + .l1_2a_dout(l1_2a_dout), + .l0a_2a_dout(l0a_2a_dout), + .l0b_2a_dout(l0b_2a_dout), + .l2b_dout(l2b_dout), + .l1_2b_dout(l1_2b_dout), + .l0a_2b_dout(l0a_2b_dout), + .l0b_2b_dout(l0b_2b_dout) + ); +endmodule + +module t; + logic clk = 0; + int cyc = 0; + + localparam int TOP_W = 4; + localparam int L0A_W = 16; + + l4_if #(TOP_W, L0A_W) inst (); + + logic [TOP_W-1:0] l4_dout; + logic [TOP_W*2-1:0] l3_dout; + logic [TOP_W*4-1:0] l2a_dout; + logic [TOP_W*8-1:0] l1_2a_dout; + logic [L0A_W-1:0] l0a_2a_dout; + logic [7:0] l0b_2a_dout; + logic [7:0] l2b_dout; + logic [15:0] l1_2b_dout; + logic [L0A_W-1:0] l0a_2b_dout; + logic [7:0] l0b_2b_dout; + + l4_handler #(TOP_W, L0A_W) m_l4 ( + .clk(clk), + .l4(inst), + .l4_dout(l4_dout), + .l3_dout(l3_dout), + .l2a_dout(l2a_dout), + .l1_2a_dout(l1_2a_dout), + .l0a_2a_dout(l0a_2a_dout), + .l0b_2a_dout(l0b_2a_dout), + .l2b_dout(l2b_dout), + .l1_2b_dout(l1_2b_dout), + .l0a_2b_dout(l0a_2b_dout), + .l0b_2b_dout(l0b_2b_dout) + ); + + always #5 clk = ~clk; + + always_ff @(posedge clk) begin + inst.tb_in <= cyc[TOP_W-1:0]; + inst.l3.tb_in <= cyc[TOP_W*2-1:0] + (TOP_W * 2)'(1); + inst.l3.l2a.tb_in <= cyc[TOP_W*4-1:0] + (TOP_W * 4)'(2); + inst.l3.l2a.l1.tb_in <= cyc[TOP_W*8-1:0] + (TOP_W * 8)'(3); + inst.l3.l2a.l1.l0a.tb_in <= cyc[L0A_W-1:0] + L0A_W'(4); + inst.l3.l2a.l1.l0b.tb_in <= cyc[7:0] + 8'd5; + inst.l3.l2b.tb_in <= cyc[7:0] + 8'd6; + inst.l3.l2b.l1.tb_in <= cyc[15:0] + 16'd7; + inst.l3.l2b.l1.l0a.tb_in <= cyc[L0A_W-1:0] + L0A_W'(8); + inst.l3.l2b.l1.l0b.tb_in <= cyc[7:0] + 8'd9; + end + + logic [TOP_W-1:0] exp_l4; + logic [TOP_W*2-1:0] exp_l3; + logic [TOP_W*4-1:0] exp_l2a; + logic [TOP_W*8-1:0] exp_l1_2a; + logic [L0A_W-1:0] exp_l0a_2a; + logic [7:0] exp_l0b_2a; + logic [7:0] exp_l2b; + logic [15:0] exp_l1_2b; + logic [L0A_W-1:0] exp_l0a_2b; + logic [7:0] exp_l0b_2b; + + always_ff @(posedge clk) begin + exp_l4 <= inst.tb_in ^ TOP_W'('1); + exp_l3 <= inst.l3.tb_in ^ (TOP_W * 2)'('1); + exp_l2a <= inst.l3.l2a.tb_in ^ (TOP_W * 4)'('1); + exp_l1_2a <= inst.l3.l2a.l1.tb_in ^ (TOP_W * 8)'('1); + exp_l0a_2a <= inst.l3.l2a.l1.l0a.tb_in ^ L0A_W'('1); + exp_l0b_2a <= inst.l3.l2a.l1.l0b.tb_in ^ 8'hFF; + exp_l2b <= inst.l3.l2b.tb_in ^ 8'hFF; + exp_l1_2b <= inst.l3.l2b.l1.tb_in ^ 16'hFFFF; + exp_l0a_2b <= inst.l3.l2b.l1.l0a.tb_in ^ L0A_W'('1); + exp_l0b_2b <= inst.l3.l2b.l1.l0b.tb_in ^ 8'hFF; + end + + always @(posedge clk) begin + cyc <= cyc + 1; + + if (cyc > 3) begin + if (l4_dout !== exp_l4) begin + $display("FAIL cyc=%0d: l4_dout=%h expected %h", cyc, l4_dout, exp_l4); + $stop; + end + if (l3_dout !== exp_l3) begin + $display("FAIL cyc=%0d: l3_dout=%h expected %h", cyc, l3_dout, exp_l3); + $stop; + end + if (l2a_dout !== exp_l2a) begin + $display("FAIL cyc=%0d: l2a_dout=%h expected %h", cyc, l2a_dout, exp_l2a); + $stop; + end + if (l1_2a_dout !== exp_l1_2a) begin + $display("FAIL cyc=%0d: l1_2a_dout=%h expected %h", cyc, l1_2a_dout, exp_l1_2a); + $stop; + end + if (l0a_2a_dout !== exp_l0a_2a) begin + $display("FAIL cyc=%0d: l0a_2a_dout=%h expected %h", cyc, l0a_2a_dout, exp_l0a_2a); + $stop; + end + if (l0b_2a_dout !== exp_l0b_2a) begin + $display("FAIL cyc=%0d: l0b_2a_dout=%h expected %h", cyc, l0b_2a_dout, exp_l0b_2a); + $stop; + end + if (l2b_dout !== exp_l2b) begin + $display("FAIL cyc=%0d: l2b_dout=%h expected %h", cyc, l2b_dout, exp_l2b); + $stop; + end + if (l1_2b_dout !== exp_l1_2b) begin + $display("FAIL cyc=%0d: l1_2b_dout=%h expected %h", cyc, l1_2b_dout, exp_l1_2b); + $stop; + end + if (l0a_2b_dout !== exp_l0a_2b) begin + $display("FAIL cyc=%0d: l0a_2b_dout=%h expected %h", cyc, l0a_2b_dout, exp_l0a_2b); + $stop; + end + if (l0b_2b_dout !== exp_l0b_2b) begin + $display("FAIL cyc=%0d: l0b_2b_dout=%h expected %h", cyc, l0b_2b_dout, exp_l0b_2b); + $stop; + end + end + + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_interface_nested_port_array.out b/test_regress/t/t_interface_nested_port_array.out new file mode 100644 index 000000000..a2f56f9b1 --- /dev/null +++ b/test_regress/t/t_interface_nested_port_array.out @@ -0,0 +1,24 @@ +%Error: t/t_interface_nested_port_array.v:160:5: Interface 'l3_if' not connected as parent's interface not connected + : ... note: In instance 't.m_l3' + : ... Perhaps caused by another error on the parent interface that needs resolving + : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? + 160 | l3_if#(W, L0A_W) l3, + | ^~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_interface_nested_port_array.v:123:5: Interface 'l2_if' not connected as parent's interface not connected + : ... note: In instance 't.m_l3.m_l2' + : ... Perhaps caused by another error on the parent interface that needs resolving + : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? + 123 | l2_if#(W, L0A_W) l2s[1:0], + | ^~~~~ +%Error: t/t_interface_nested_port_array.v:91:5: Interface 'l2_if' not connected as parent's interface not connected + : ... note: In instance 't.m_l3.m_l2.m_l2b' + : ... Perhaps caused by another error on the parent interface that needs resolving + : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? + 91 | l2_if#(W, L0A_W) l2, + | ^~~~~ +%Error: Internal Error: t/t_interface_nested_port_array.v:27:11: ../V3LinkDot.cpp:#: Module/etc never assigned a symbol entry? + : ... note: In instance 't.m_l3.m_l2.m_l2b.m_l1_1' + 27 | interface l2_if #( + | ^~~~~ + ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_interface_nested_port_array.py b/test_regress/t/t_interface_nested_port_array.py new file mode 100755 index 000000000..e30519452 --- /dev/null +++ b/test_regress/t/t_interface_nested_port_array.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +# Issue #5066: Nested interface ports through interface arrays +# (e.g., l2.l1[0] where l1 is an interface array inside interface l2). +# V3Param internal errors have been fixed, but V3LinkDot interface +# connection resolution for array element selections is not yet implemented. +# This test documents the current behavior and should be updated when +# full support is added. +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_nested_port_array.v b/test_regress/t/t_interface_nested_port_array.v new file mode 100644 index 000000000..65e1a204e --- /dev/null +++ b/test_regress/t/t_interface_nested_port_array.v @@ -0,0 +1,338 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +// Issue #5066 - Nested interface ports through interface arrays +// Similar structure to t_interface_nested_port.v, but with interface arrays. + +interface l0_if #( + parameter int W = 8 +); + logic [W-1:0] tb_in; + logic [W-1:0] dut_out; +endinterface + +interface l1_if #( + parameter int W = 8, + parameter int L0A_W = 8 +); + logic [W-1:0] tb_in; + logic [W-1:0] dut_out; + l0_if #(L0A_W) l0a[1:0] (); // arrayed passthrough + l0_if l0b (); // default +endinterface + +interface l2_if #( + parameter int W = 8, + parameter int L0A_W = 8 +); + logic [W-1:0] tb_in; + logic [W-1:0] dut_out; + l1_if #(W * 2, L0A_W) l1[1:0] (); // derived +endinterface + +interface l3_if #( + parameter int W = 8, + parameter int L0A_W = 8 +); + logic [W-1:0] tb_in; + logic [W-1:0] dut_out; + l2_if #(W * 2, L0A_W) l2[1:0] (); // arrayed +endinterface + +module l0_handler #( + parameter int W = 8 +) ( + input logic clk, + l0_if#(W) l0, + output logic [W-1:0] dout +); + always_ff @(posedge clk) l0.dut_out <= l0.tb_in ^ W'('1); + assign dout = l0.dut_out; +endmodule + +module l1_handler #( + parameter int W = 8, + parameter int L0A_W = 8 +) ( + input logic clk, + l1_if#(W, L0A_W) l1, + output logic [W-1:0] l1_dout, + output logic [L0A_W-1:0] l0a0_dout, + output logic [L0A_W-1:0] l0a1_dout, + output logic [7:0] l0b_dout +); + always_ff @(posedge clk) l1.dut_out <= l1.tb_in ^ W'('1); + assign l1_dout = l1.dut_out; + l0_handler #(L0A_W) m_l0a0 ( + .clk(clk), + .l0(l1.l0a[0]), + .dout(l0a0_dout) + ); + l0_handler #(L0A_W) m_l0a1 ( + .clk(clk), + .l0(l1.l0a[1]), + .dout(l0a1_dout) + ); + l0_handler #(8) m_l0b ( + .clk(clk), + .l0(l1.l0b), + .dout(l0b_dout) + ); +endmodule + +module l2_handler #( + parameter int W = 8, + parameter int L0A_W = 8 +) ( + input logic clk, + l2_if#(W, L0A_W) l2, + output logic [W-1:0] l2_dout, + output logic [W*2-1:0] l1_0_dout, + output logic [L0A_W-1:0] l0a0_0_dout, + output logic [L0A_W-1:0] l0a1_1_dout, + output logic [7:0] l0b_1_dout +); + always_ff @(posedge clk) l2.dut_out <= l2.tb_in ^ W'('1); + assign l2_dout = l2.dut_out; + l1_handler #(W * 2, L0A_W) m_l1_0 ( + .clk(clk), + .l1(l2.l1[0]), + .l1_dout(l1_0_dout), + .l0a0_dout(l0a0_0_dout), + .l0a1_dout(), + .l0b_dout() + ); + l1_handler #(W * 2, L0A_W) m_l1_1 ( + .clk(clk), + .l1(l2.l1[1]), + .l1_dout(), + .l0a0_dout(), + .l0a1_dout(l0a1_1_dout), + .l0b_dout(l0b_1_dout) + ); +endmodule + +module l2_array_handler #( + parameter int W = 8, + parameter int L0A_W = 8 +) ( + input logic clk, + l2_if#(W, L0A_W) l2s[1:0], + output logic [W-1:0] l2a_dout, + output logic [W*2-1:0] l2a_l1_0_dout, + output logic [L0A_W-1:0] l2a_l0a0_0_dout, + output logic [L0A_W-1:0] l2a_l0a1_1_dout, + output logic [7:0] l2a_l0b_1_dout, + output logic [W-1:0] l2b_dout, + output logic [W*2-1:0] l2b_l1_0_dout, + output logic [L0A_W-1:0] l2b_l0a0_0_dout, + output logic [L0A_W-1:0] l2b_l0a1_1_dout, + output logic [7:0] l2b_l0b_1_dout +); + l2_handler #(W, L0A_W) m_l2a ( + .clk(clk), + .l2(l2s[0]), + .l2_dout(l2a_dout), + .l1_0_dout(l2a_l1_0_dout), + .l0a0_0_dout(l2a_l0a0_0_dout), + .l0a1_1_dout(l2a_l0a1_1_dout), + .l0b_1_dout(l2a_l0b_1_dout) + ); + l2_handler #(W, L0A_W) m_l2b ( + .clk(clk), + .l2(l2s[1]), + .l2_dout(l2b_dout), + .l1_0_dout(l2b_l1_0_dout), + .l0a0_0_dout(l2b_l0a0_0_dout), + .l0a1_1_dout(l2b_l0a1_1_dout), + .l0b_1_dout(l2b_l0b_1_dout) + ); +endmodule + +module l3_handler #( + parameter int W = 8, + parameter int L0A_W = 8 +) ( + input logic clk, + l3_if#(W, L0A_W) l3, + output logic [W-1:0] l3_dout, + output logic [W*2-1:0] l2a_dout, + output logic [W*4-1:0] l2a_l1_0_dout, + output logic [L0A_W-1:0] l2a_l0a0_0_dout, + output logic [L0A_W-1:0] l2a_l0a1_1_dout, + output logic [7:0] l2a_l0b_1_dout, + output logic [W*2-1:0] l2b_dout, + output logic [W*4-1:0] l2b_l1_0_dout, + output logic [L0A_W-1:0] l2b_l0a0_0_dout, + output logic [L0A_W-1:0] l2b_l0a1_1_dout, + output logic [7:0] l2b_l0b_1_dout +); + always_ff @(posedge clk) l3.dut_out <= l3.tb_in ^ W'('1); + assign l3_dout = l3.dut_out; + l2_array_handler #(W * 2, L0A_W) m_l2 ( + .clk(clk), + .l2s(l3.l2), + .l2a_dout(l2a_dout), + .l2a_l1_0_dout(l2a_l1_0_dout), + .l2a_l0a0_0_dout(l2a_l0a0_0_dout), + .l2a_l0a1_1_dout(l2a_l0a1_1_dout), + .l2a_l0b_1_dout(l2a_l0b_1_dout), + .l2b_dout(l2b_dout), + .l2b_l1_0_dout(l2b_l1_0_dout), + .l2b_l0a0_0_dout(l2b_l0a0_0_dout), + .l2b_l0a1_1_dout(l2b_l0a1_1_dout), + .l2b_l0b_1_dout(l2b_l0b_1_dout) + ); +endmodule + +module t; + logic clk = 0; + int cyc = 0; + + localparam int TOP_W = 4; + localparam int L0A_W = 12; + + l3_if #(TOP_W, L0A_W) inst (); + + logic [TOP_W-1:0] l3_dout; + logic [TOP_W*2-1:0] l2a_dout; + logic [TOP_W*4-1:0] l2a_l1_0_dout; + logic [L0A_W-1:0] l2a_l0a0_0_dout; + logic [L0A_W-1:0] l2a_l0a1_1_dout; + logic [7:0] l2a_l0b_1_dout; + logic [TOP_W*2-1:0] l2b_dout; + logic [TOP_W*4-1:0] l2b_l1_0_dout; + logic [L0A_W-1:0] l2b_l0a0_0_dout; + logic [L0A_W-1:0] l2b_l0a1_1_dout; + logic [7:0] l2b_l0b_1_dout; + + l3_handler #(TOP_W, L0A_W) m_l3 ( + .clk(clk), + .l3(inst), + .l3_dout(l3_dout), + .l2a_dout(l2a_dout), + .l2a_l1_0_dout(l2a_l1_0_dout), + .l2a_l0a0_0_dout(l2a_l0a0_0_dout), + .l2a_l0a1_1_dout(l2a_l0a1_1_dout), + .l2a_l0b_1_dout(l2a_l0b_1_dout), + .l2b_dout(l2b_dout), + .l2b_l1_0_dout(l2b_l1_0_dout), + .l2b_l0a0_0_dout(l2b_l0a0_0_dout), + .l2b_l0a1_1_dout(l2b_l0a1_1_dout), + .l2b_l0b_1_dout(l2b_l0b_1_dout) + ); + + always #5 clk = ~clk; + + always_ff @(posedge clk) begin + inst.tb_in <= cyc[TOP_W-1:0]; + + inst.l2[0].tb_in <= cyc[TOP_W*2-1:0] + (TOP_W * 2)'(1); + inst.l2[0].l1[0].tb_in <= cyc[TOP_W*4-1:0] + (TOP_W * 4)'(2); + inst.l2[0].l1[0].l0a[0].tb_in <= cyc[L0A_W-1:0] + L0A_W'(3); + inst.l2[0].l1[1].l0a[1].tb_in <= cyc[L0A_W-1:0] + L0A_W'(4); + inst.l2[0].l1[1].l0b.tb_in <= cyc[7:0] + 8'd5; + + inst.l2[1].tb_in <= cyc[TOP_W*2-1:0] + (TOP_W * 2)'(6); + inst.l2[1].l1[0].tb_in <= cyc[TOP_W*4-1:0] + (TOP_W * 4)'(7); + inst.l2[1].l1[0].l0a[0].tb_in <= cyc[L0A_W-1:0] + L0A_W'(8); + inst.l2[1].l1[1].l0a[1].tb_in <= cyc[L0A_W-1:0] + L0A_W'(9); + inst.l2[1].l1[1].l0b.tb_in <= cyc[7:0] + 8'd10; + end + + logic [TOP_W-1:0] exp_l3_dout; + logic [TOP_W*2-1:0] exp_l2a_dout; + logic [TOP_W*4-1:0] exp_l2a_l1_0_dout; + logic [L0A_W-1:0] exp_l2a_l0a0_0_dout; + logic [L0A_W-1:0] exp_l2a_l0a1_1_dout; + logic [7:0] exp_l2a_l0b_1_dout; + logic [TOP_W*2-1:0] exp_l2b_dout; + logic [TOP_W*4-1:0] exp_l2b_l1_0_dout; + logic [L0A_W-1:0] exp_l2b_l0a0_0_dout; + logic [L0A_W-1:0] exp_l2b_l0a1_1_dout; + logic [7:0] exp_l2b_l0b_1_dout; + + always_ff @(posedge clk) begin + exp_l3_dout <= inst.tb_in ^ TOP_W'('1); + + exp_l2a_dout <= inst.l2[0].tb_in ^ (TOP_W * 2)'('1); + exp_l2a_l1_0_dout <= inst.l2[0].l1[0].tb_in ^ (TOP_W * 4)'('1); + exp_l2a_l0a0_0_dout <= inst.l2[0].l1[0].l0a[0].tb_in ^ L0A_W'('1); + exp_l2a_l0a1_1_dout <= inst.l2[0].l1[1].l0a[1].tb_in ^ L0A_W'('1); + exp_l2a_l0b_1_dout <= inst.l2[0].l1[1].l0b.tb_in ^ 8'hFF; + + exp_l2b_dout <= inst.l2[1].tb_in ^ (TOP_W * 2)'('1); + exp_l2b_l1_0_dout <= inst.l2[1].l1[0].tb_in ^ (TOP_W * 4)'('1); + exp_l2b_l0a0_0_dout <= inst.l2[1].l1[0].l0a[0].tb_in ^ L0A_W'('1); + exp_l2b_l0a1_1_dout <= inst.l2[1].l1[1].l0a[1].tb_in ^ L0A_W'('1); + exp_l2b_l0b_1_dout <= inst.l2[1].l1[1].l0b.tb_in ^ 8'hFF; + end + + always @(posedge clk) begin + cyc <= cyc + 1; + + if (cyc > 3) begin + if (l3_dout !== exp_l3_dout) begin + $display("FAIL cyc=%0d: l3_dout=%h expected %h", cyc, l3_dout, exp_l3_dout); + $stop; + end + if (l2a_dout !== exp_l2a_dout) begin + $display("FAIL cyc=%0d: l2a_dout=%h expected %h", cyc, l2a_dout, exp_l2a_dout); + $stop; + end + if (l2a_l1_0_dout !== exp_l2a_l1_0_dout) begin + $display("FAIL cyc=%0d: l2a_l1_0_dout=%h expected %h", cyc, l2a_l1_0_dout, + exp_l2a_l1_0_dout); + $stop; + end + if (l2a_l0a0_0_dout !== exp_l2a_l0a0_0_dout) begin + $display("FAIL cyc=%0d: l2a_l0a0_0_dout=%h expected %h", cyc, l2a_l0a0_0_dout, + exp_l2a_l0a0_0_dout); + $stop; + end + if (l2a_l0a1_1_dout !== exp_l2a_l0a1_1_dout) begin + $display("FAIL cyc=%0d: l2a_l0a1_1_dout=%h expected %h", cyc, l2a_l0a1_1_dout, + exp_l2a_l0a1_1_dout); + $stop; + end + if (l2a_l0b_1_dout !== exp_l2a_l0b_1_dout) begin + $display("FAIL cyc=%0d: l2a_l0b_1_dout=%h expected %h", cyc, l2a_l0b_1_dout, + exp_l2a_l0b_1_dout); + $stop; + end + + if (l2b_dout !== exp_l2b_dout) begin + $display("FAIL cyc=%0d: l2b_dout=%h expected %h", cyc, l2b_dout, exp_l2b_dout); + $stop; + end + if (l2b_l1_0_dout !== exp_l2b_l1_0_dout) begin + $display("FAIL cyc=%0d: l2b_l1_0_dout=%h expected %h", cyc, l2b_l1_0_dout, + exp_l2b_l1_0_dout); + $stop; + end + if (l2b_l0a0_0_dout !== exp_l2b_l0a0_0_dout) begin + $display("FAIL cyc=%0d: l2b_l0a0_0_dout=%h expected %h", cyc, l2b_l0a0_0_dout, + exp_l2b_l0a0_0_dout); + $stop; + end + if (l2b_l0a1_1_dout !== exp_l2b_l0a1_1_dout) begin + $display("FAIL cyc=%0d: l2b_l0a1_1_dout=%h expected %h", cyc, l2b_l0a1_1_dout, + exp_l2b_l0a1_1_dout); + $stop; + end + if (l2b_l0b_1_dout !== exp_l2b_l0b_1_dout) begin + $display("FAIL cyc=%0d: l2b_l0b_1_dout=%h expected %h", cyc, l2b_l0b_1_dout, + exp_l2b_l0b_1_dout); + $stop; + end + end + + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_interface_nested_port_array_noinl.out b/test_regress/t/t_interface_nested_port_array_noinl.out new file mode 100644 index 000000000..a2f56f9b1 --- /dev/null +++ b/test_regress/t/t_interface_nested_port_array_noinl.out @@ -0,0 +1,24 @@ +%Error: t/t_interface_nested_port_array.v:160:5: Interface 'l3_if' not connected as parent's interface not connected + : ... note: In instance 't.m_l3' + : ... Perhaps caused by another error on the parent interface that needs resolving + : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? + 160 | l3_if#(W, L0A_W) l3, + | ^~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_interface_nested_port_array.v:123:5: Interface 'l2_if' not connected as parent's interface not connected + : ... note: In instance 't.m_l3.m_l2' + : ... Perhaps caused by another error on the parent interface that needs resolving + : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? + 123 | l2_if#(W, L0A_W) l2s[1:0], + | ^~~~~ +%Error: t/t_interface_nested_port_array.v:91:5: Interface 'l2_if' not connected as parent's interface not connected + : ... note: In instance 't.m_l3.m_l2.m_l2b' + : ... Perhaps caused by another error on the parent interface that needs resolving + : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? + 91 | l2_if#(W, L0A_W) l2, + | ^~~~~ +%Error: Internal Error: t/t_interface_nested_port_array.v:27:11: ../V3LinkDot.cpp:#: Module/etc never assigned a symbol entry? + : ... note: In instance 't.m_l3.m_l2.m_l2b.m_l1_1' + 27 | interface l2_if #( + | ^~~~~ + ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_interface_nested_port_array_noinl.py b/test_regress/t/t_interface_nested_port_array_noinl.py new file mode 100755 index 000000000..d0884ad33 --- /dev/null +++ b/test_regress/t/t_interface_nested_port_array_noinl.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_interface_nested_port_array.v" + +# Issue #5066: Nested interface ports through interface arrays +# (e.g., l2.l1[0] where l1 is an interface array inside interface l2). +# V3Param internal errors have been fixed, but V3LinkDot interface +# connection resolution for array element selections is not yet implemented. +# This test documents the current behavior and should be updated when +# full support is added. +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_interface_nested_port_noinl.py b/test_regress/t/t_interface_nested_port_noinl.py new file mode 100755 index 000000000..50db1bfbd --- /dev/null +++ b/test_regress/t/t_interface_nested_port_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_nested_port.v" + +test.compile(verilator_flags2=['--binary', '-fno-inline']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_nested_port_type.py b/test_regress/t/t_interface_nested_port_type.py new file mode 100755 index 000000000..46d1fe4c0 --- /dev/null +++ b/test_regress/t/t_interface_nested_port_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_nested_port_type.v b/test_regress/t/t_interface_nested_port_type.v new file mode 100644 index 000000000..dad56d9b1 --- /dev/null +++ b/test_regress/t/t_interface_nested_port_type.v @@ -0,0 +1,414 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Leela Pakanati +// SPDX-License-Identifier: CC0-1.0 + +// Issue #5066 - Test nested interface ports with type parameters +// +// Tests all parameter patterns in a 5-deep hierarchy using types: +// - Derived: Type width doubles at each level (L3=bits(T)*2, etc.) +// - Hard-coded: L2B.T=logic[7:0] regardless of parent +// - Passthrough: L0A_T flows unchanged from top to L0A +// - Default: L0B uses default T=logic[7:0] +// +// With TOP_T=logic[3:0], L0A_T=logic[15:0]: +// L4(T=4b) -> L3(T=8b) -> L2A(T=16b) -> L1(T=32b) -> L0A(T=16b), L0B(T=8b) +// -> L2B(T=8b) -> L1(T=16b) -> L0A(T=16b), L0B(T=8b) + +interface l0_if #( + parameter type T = logic [7:0] +); + T tb_in; + T dut_out; +endinterface + +interface l1_if #( + parameter type T = logic, + parameter type L0A_T = logic +); + T tb_in; + T dut_out; + l0_if #(.T(L0A_T)) l0a (); // passthrough + l0_if l0b (); // default +endinterface + +interface l2_if #( + parameter type T = logic, + parameter type L0A_T = logic +); + T tb_in; + T dut_out; + l1_if #( + .T(logic [$bits(T)*2-1:0]), + .L0A_T(L0A_T) + ) l1 (); // derived +endinterface + +interface l3_if #( + parameter type T = logic, + parameter type L0A_T = logic +); + T tb_in; + T dut_out; + l2_if #( + .T(logic [$bits(T)*2-1:0]), + .L0A_T(L0A_T) + ) l2a (); // derived + l2_if #( + .T(logic [7:0]), + .L0A_T(L0A_T) + ) l2b (); // hard-coded +endinterface + +interface l4_if #( + parameter type T = logic, + parameter type L0A_T = logic +); + T tb_in; + T dut_out; + l3_if #( + .T(logic [$bits(T)*2-1:0]), + .L0A_T(L0A_T) + ) l3 (); // derived +endinterface + +// Handlers use type parameters with derived output types + +module l0_handler #( + parameter type T = logic [7:0] +) ( + input logic clk, + l0_if l0, + output T dout +); + always_ff @(posedge clk) l0.dut_out <= l0.tb_in ^ T'('1); + assign dout = l0.dut_out; +endmodule + +module l1_reader #( + parameter type T = logic +) ( + l1_if l1, + output T dout +); + assign dout = l1.dut_out; +endmodule + +module l1_driver #( + parameter type T = logic +) ( + input logic clk, + l1_if l1 +); + always_ff @(posedge clk) l1.dut_out <= l1.tb_in ^ T'('1); +endmodule + +module l1_handler #( + parameter type T = logic, + parameter type L0A_T = logic +) ( + input logic clk, + l1_if l1, + output T l1_dout, + output L0A_T l0a_dout, + output logic [7:0] l0b_dout +); + // Use reader/driver submodules instead of direct access + l1_reader #( + .T(T) + ) m_rdr ( + .l1(l1), + .dout(l1_dout) + ); + l1_driver #( + .T(T) + ) m_drv ( + .clk(clk), + .l1(l1) + ); + + // Still instantiate l0_handlers for nested ports + l0_handler #( + .T(L0A_T) + ) m_l0a ( + .clk(clk), + .l0(l1.l0a), + .dout(l0a_dout) + ); + l0_handler #( + .T(logic [7:0]) + ) m_l0b ( + .clk(clk), + .l0(l1.l0b), + .dout(l0b_dout) + ); +endmodule + +module l2_handler #( + parameter type T = logic, + parameter type L0A_T = logic +) ( + input logic clk, + l2_if l2, + output T l2_dout, + output logic [$bits(T)*2-1:0] l1_dout, + output L0A_T l0a_dout, + output logic [7:0] l0b_dout +); + always_ff @(posedge clk) l2.dut_out <= l2.tb_in ^ T'('1); + assign l2_dout = l2.dut_out; + l1_handler #( + .T(logic [$bits(T)*2-1:0]), + .L0A_T(L0A_T) + ) m_l1 ( + .clk(clk), + .l1(l2.l1), + .l1_dout(l1_dout), + .l0a_dout(l0a_dout), + .l0b_dout(l0b_dout) + ); +endmodule + +module l3_reader #( + parameter type T = logic +) ( + l3_if l3, + output T dout +); + assign dout = l3.dut_out; +endmodule + +module l3_driver #( + parameter type T = logic +) ( + input logic clk, + l3_if l3 +); + always_ff @(posedge clk) l3.dut_out <= l3.tb_in ^ T'('1); +endmodule + +module l3_handler #( + parameter type T = logic, + parameter type L0A_T = logic +) ( + input logic clk, + l3_if l3, + output T l3_dout, + output logic [$bits(T)*2-1:0] l2a_dout, + output logic [$bits(T)*4-1:0] l1_2a_dout, + output L0A_T l0a_2a_dout, + output logic [7:0] l0b_2a_dout, + output logic [7:0] l2b_dout, + output logic [15:0] l1_2b_dout, + output L0A_T l0a_2b_dout, + output logic [7:0] l0b_2b_dout +); + // Use reader/driver submodules instead of direct access + l3_reader #( + .T(T) + ) m_rdr ( + .l3(l3), + .dout(l3_dout) + ); + l3_driver #( + .T(T) + ) m_drv ( + .clk(clk), + .l3(l3) + ); + + // Still instantiate l2_handlers for nested ports + l2_handler #( + .T(logic [$bits(T)*2-1:0]), + .L0A_T(L0A_T) + ) m_l2a ( + .clk(clk), + .l2(l3.l2a), + .l2_dout(l2a_dout), + .l1_dout(l1_2a_dout), + .l0a_dout(l0a_2a_dout), + .l0b_dout(l0b_2a_dout) + ); + l2_handler #( + .T(logic [7:0]), + .L0A_T(L0A_T) + ) m_l2b ( + .clk(clk), + .l2(l3.l2b), + .l2_dout(l2b_dout), + .l1_dout(l1_2b_dout), + .l0a_dout(l0a_2b_dout), + .l0b_dout(l0b_2b_dout) + ); +endmodule + +module l4_handler #( + parameter type T = logic, + parameter type L0A_T = logic +) ( + input logic clk, + l4_if l4, + output T l4_dout, + output logic [$bits(T)*2-1:0] l3_dout, + output logic [$bits(T)*4-1:0] l2a_dout, + output logic [$bits(T)*8-1:0] l1_2a_dout, + output L0A_T l0a_2a_dout, + output logic [7:0] l0b_2a_dout, + output logic [7:0] l2b_dout, + output logic [15:0] l1_2b_dout, + output L0A_T l0a_2b_dout, + output logic [7:0] l0b_2b_dout +); + always_ff @(posedge clk) l4.dut_out <= l4.tb_in ^ T'('1); + assign l4_dout = l4.dut_out; + l3_handler #( + .T(logic [$bits(T)*2-1:0]), + .L0A_T(L0A_T) + ) m_l3 ( + .clk(clk), + .l3(l4.l3), + .l3_dout(l3_dout), + .l2a_dout(l2a_dout), + .l1_2a_dout(l1_2a_dout), + .l0a_2a_dout(l0a_2a_dout), + .l0b_2a_dout(l0b_2a_dout), + .l2b_dout(l2b_dout), + .l1_2b_dout(l1_2b_dout), + .l0a_2b_dout(l0a_2b_dout), + .l0b_2b_dout(l0b_2b_dout) + ); +endmodule + +module t; + logic clk = 0; + int cyc = 0; + + localparam type TOP_T = logic [3:0]; + localparam type L0A_T = logic [15:0]; + + l4_if #( + .T(TOP_T), + .L0A_T(L0A_T) + ) inst (); + + logic [3:0] l4_dout; + logic [7:0] l3_dout; + logic [15:0] l2a_dout; + logic [31:0] l1_2a_dout; + logic [15:0] l0a_2a_dout; + logic [7:0] l0b_2a_dout; + logic [7:0] l2b_dout; + logic [15:0] l1_2b_dout; + logic [15:0] l0a_2b_dout; + logic [7:0] l0b_2b_dout; + + l4_handler #( + .T(TOP_T), + .L0A_T(L0A_T) + ) m_l4 ( + .clk(clk), + .l4(inst), + .l4_dout(l4_dout), + .l3_dout(l3_dout), + .l2a_dout(l2a_dout), + .l1_2a_dout(l1_2a_dout), + .l0a_2a_dout(l0a_2a_dout), + .l0b_2a_dout(l0b_2a_dout), + .l2b_dout(l2b_dout), + .l1_2b_dout(l1_2b_dout), + .l0a_2b_dout(l0a_2b_dout), + .l0b_2b_dout(l0b_2b_dout) + ); + + always #5 clk = ~clk; + + always_ff @(posedge clk) begin + inst.tb_in <= cyc[3:0]; + inst.l3.tb_in <= cyc[7:0] + 8'd1; + inst.l3.l2a.tb_in <= cyc[15:0] + 16'd2; + inst.l3.l2a.l1.tb_in <= cyc[31:0] + 32'd3; + inst.l3.l2a.l1.l0a.tb_in <= cyc[15:0] + 16'd4; + inst.l3.l2a.l1.l0b.tb_in <= cyc[7:0] + 8'd5; + inst.l3.l2b.tb_in <= cyc[7:0] + 8'd6; + inst.l3.l2b.l1.tb_in <= cyc[15:0] + 16'd7; + inst.l3.l2b.l1.l0a.tb_in <= cyc[15:0] + 16'd8; + inst.l3.l2b.l1.l0b.tb_in <= cyc[7:0] + 8'd9; + end + + logic [3:0] exp_l4; + logic [7:0] exp_l3; + logic [15:0] exp_l2a; + logic [31:0] exp_l1_2a; + logic [15:0] exp_l0a_2a; + logic [7:0] exp_l0b_2a; + logic [7:0] exp_l2b; + logic [15:0] exp_l1_2b; + logic [15:0] exp_l0a_2b; + logic [7:0] exp_l0b_2b; + + always_ff @(posedge clk) begin + exp_l4 <= inst.tb_in ^ 4'hF; + exp_l3 <= inst.l3.tb_in ^ 8'hFF; + exp_l2a <= inst.l3.l2a.tb_in ^ 16'hFFFF; + exp_l1_2a <= inst.l3.l2a.l1.tb_in ^ 32'hFFFFFFFF; + exp_l0a_2a <= inst.l3.l2a.l1.l0a.tb_in ^ 16'hFFFF; + exp_l0b_2a <= inst.l3.l2a.l1.l0b.tb_in ^ 8'hFF; + exp_l2b <= inst.l3.l2b.tb_in ^ 8'hFF; + exp_l1_2b <= inst.l3.l2b.l1.tb_in ^ 16'hFFFF; + exp_l0a_2b <= inst.l3.l2b.l1.l0a.tb_in ^ 16'hFFFF; + exp_l0b_2b <= inst.l3.l2b.l1.l0b.tb_in ^ 8'hFF; + end + + always @(posedge clk) begin + cyc <= cyc + 1; + + if (cyc > 3) begin + if (l4_dout !== exp_l4) begin + $display("FAIL cyc=%0d: l4_dout=%h expected %h", cyc, l4_dout, exp_l4); + $stop; + end + if (l3_dout !== exp_l3) begin + $display("FAIL cyc=%0d: l3_dout=%h expected %h", cyc, l3_dout, exp_l3); + $stop; + end + if (l2a_dout !== exp_l2a) begin + $display("FAIL cyc=%0d: l2a_dout=%h expected %h", cyc, l2a_dout, exp_l2a); + $stop; + end + if (l1_2a_dout !== exp_l1_2a) begin + $display("FAIL cyc=%0d: l1_2a_dout=%h expected %h", cyc, l1_2a_dout, exp_l1_2a); + $stop; + end + if (l0a_2a_dout !== exp_l0a_2a) begin + $display("FAIL cyc=%0d: l0a_2a_dout=%h expected %h", cyc, l0a_2a_dout, exp_l0a_2a); + $stop; + end + if (l0b_2a_dout !== exp_l0b_2a) begin + $display("FAIL cyc=%0d: l0b_2a_dout=%h expected %h", cyc, l0b_2a_dout, exp_l0b_2a); + $stop; + end + if (l2b_dout !== exp_l2b) begin + $display("FAIL cyc=%0d: l2b_dout=%h expected %h", cyc, l2b_dout, exp_l2b); + $stop; + end + if (l1_2b_dout !== exp_l1_2b) begin + $display("FAIL cyc=%0d: l1_2b_dout=%h expected %h", cyc, l1_2b_dout, exp_l1_2b); + $stop; + end + if (l0a_2b_dout !== exp_l0a_2b) begin + $display("FAIL cyc=%0d: l0a_2b_dout=%h expected %h", cyc, l0a_2b_dout, exp_l0a_2b); + $stop; + end + if (l0b_2b_dout !== exp_l0b_2b) begin + $display("FAIL cyc=%0d: l0b_2b_dout=%h expected %h", cyc, l0b_2b_dout, exp_l0b_2b); + $stop; + end + end + + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_interface_nested_port_type_noinl.py b/test_regress/t/t_interface_nested_port_type_noinl.py new file mode 100755 index 000000000..21954d583 --- /dev/null +++ b/test_regress/t/t_interface_nested_port_type_noinl.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface_nested_port_type.v" + +# Type parameters in nested interfaces (no-inline mode) +test.compile(verilator_flags2=['--binary', '-fno-inline']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_noinl.py b/test_regress/t/t_interface_noinl.py index 626af0d7c..f67e05814 100755 --- a/test_regress/t/t_interface_noinl.py +++ b/test_regress/t/t_interface_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_notpublic.py b/test_regress/t/t_interface_notpublic.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_notpublic.py +++ b/test_regress/t/t_interface_notpublic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_notpublic.v b/test_regress/t/t_interface_notpublic.v index 7619519e8..83859db21 100644 --- a/test_regress/t/t_interface_notpublic.v +++ b/test_regress/t/t_interface_notpublic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 interface intf diff --git a/test_regress/t/t_interface_param1.py b/test_regress/t/t_interface_param1.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_interface_param1.py +++ b/test_regress/t/t_interface_param1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_param1.v b/test_regress/t/t_interface_param1.v index 0128f1ba7..d11e21b63 100644 --- a/test_regress/t/t_interface_param1.v +++ b/test_regress/t/t_interface_param1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Jie Xu // SPDX-License-Identifier: CC0-1.0 //bug692 diff --git a/test_regress/t/t_interface_param2.py b/test_regress/t/t_interface_param2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_param2.py +++ b/test_regress/t/t_interface_param2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_param2.v b/test_regress/t/t_interface_param2.v index 324514a94..ae08d1427 100644 --- a/test_regress/t/t_interface_param2.v +++ b/test_regress/t/t_interface_param2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Adrian Wise. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Adrian Wise // SPDX-License-Identifier: CC0-1.0 //bug1104 diff --git a/test_regress/t/t_interface_param_another_bad.py b/test_regress/t/t_interface_param_another_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_param_another_bad.py +++ b/test_regress/t/t_interface_param_another_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_param_another_bad.v b/test_regress/t/t_interface_param_another_bad.v index e432a507c..25e66288e 100644 --- a/test_regress/t/t_interface_param_another_bad.v +++ b/test_regress/t/t_interface_param_another_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Johan Bjork. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Johan Bjork // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_interface_param_dependency.py b/test_regress/t/t_interface_param_dependency.py index daf5a778c..597ea5463 100755 --- a/test_regress/t/t_interface_param_dependency.py +++ b/test_regress/t/t_interface_param_dependency.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Test interface parameter dependency resolution # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_param_dependency.v b/test_regress/t/t_interface_param_dependency.v index 94c8af207..c17892fe6 100644 --- a/test_regress/t/t_interface_param_dependency.v +++ b/test_regress/t/t_interface_param_dependency.v @@ -3,8 +3,8 @@ // Test that interface/modport parameters can be accessed when the // interface/modport is an IO port of the module. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Paul Swirhun +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Paul Swirhun // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_interface_param_genblk.py b/test_regress/t/t_interface_param_genblk.py index ccec64024..33149e225 100755 --- a/test_regress/t/t_interface_param_genblk.py +++ b/test_regress/t/t_interface_param_genblk.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_param_genblk.v b/test_regress/t/t_interface_param_genblk.v index 2a84ad5bb..9597e2034 100644 --- a/test_regress/t/t_interface_param_genblk.v +++ b/test_regress/t/t_interface_param_genblk.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 // See #4664 diff --git a/test_regress/t/t_interface_param_local_access.py b/test_regress/t/t_interface_param_local_access.py index c283ba235..4a1a78384 100755 --- a/test_regress/t/t_interface_param_local_access.py +++ b/test_regress/t/t_interface_param_local_access.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_param_local_access.v b/test_regress/t/t_interface_param_local_access.v index 18ab6bd09..26b7ded47 100644 --- a/test_regress/t/t_interface_param_local_access.v +++ b/test_regress/t/t_interface_param_local_access.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface intf #( diff --git a/test_regress/t/t_interface_parameter_access.py b/test_regress/t/t_interface_parameter_access.py index dbdaf4551..1a93d5310 100755 --- a/test_regress/t/t_interface_parameter_access.py +++ b/test_regress/t/t_interface_parameter_access.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_parameter_access.v b/test_regress/t/t_interface_parameter_access.v index c7dd80d4b..3adf7a20c 100644 --- a/test_regress/t/t_interface_parameter_access.v +++ b/test_regress/t/t_interface_parameter_access.v @@ -2,8 +2,8 @@ // // A test of the import parameter used with modport // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 interface test_if #(parameter integer FOO = 1); diff --git a/test_regress/t/t_interface_paren_missing_bad.py b/test_regress/t/t_interface_paren_missing_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_interface_paren_missing_bad.py +++ b/test_regress/t/t_interface_paren_missing_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_paren_missing_bad.v b/test_regress/t/t_interface_paren_missing_bad.v index 5a02d2ae1..07da0d1b1 100644 --- a/test_regress/t/t_interface_paren_missing_bad.v +++ b/test_regress/t/t_interface_paren_missing_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Goekce Aydos. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Goekce Aydos // SPDX-License-Identifier: CC0-1.0 // Interface instantiation without parenthesis diff --git a/test_regress/t/t_interface_parent_scope.py b/test_regress/t/t_interface_parent_scope.py index 96a59e345..a09d6d38a 100755 --- a/test_regress/t/t_interface_parent_scope.py +++ b/test_regress/t/t_interface_parent_scope.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_parent_scope.v b/test_regress/t/t_interface_parent_scope.v index a3329dfe7..b539c8530 100644 --- a/test_regress/t/t_interface_parent_scope.v +++ b/test_regress/t/t_interface_parent_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 interface Foo; diff --git a/test_regress/t/t_interface_ref_trace.py b/test_regress/t/t_interface_ref_trace.py index b9b76c6e4..9653f752c 100755 --- a/test_regress/t/t_interface_ref_trace.py +++ b/test_regress/t/t_interface_ref_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ref_trace.v b/test_regress/t/t_interface_ref_trace.v index 13540e5c9..211c2dbed 100644 --- a/test_regress/t/t_interface_ref_trace.v +++ b/test_regress/t/t_interface_ref_trace.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Todd Strader // SPDX-License-Identifier: CC0-1.0 // Test for trace file interface aliasing diff --git a/test_regress/t/t_interface_ref_trace_fst.py b/test_regress/t/t_interface_ref_trace_fst.py index fef2fad52..6010b9ac7 100755 --- a/test_regress/t/t_interface_ref_trace_fst.py +++ b/test_regress/t/t_interface_ref_trace_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.py b/test_regress/t/t_interface_ref_trace_fst_sc.py index a45926d74..66033f639 100755 --- a/test_regress/t/t_interface_ref_trace_fst_sc.py +++ b/test_regress/t/t_interface_ref_trace_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ref_trace_inla.py b/test_regress/t/t_interface_ref_trace_inla.py index 0ef92f346..0dea85d0d 100755 --- a/test_regress/t/t_interface_ref_trace_inla.py +++ b/test_regress/t/t_interface_ref_trace_inla.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ref_trace_inlab.py b/test_regress/t/t_interface_ref_trace_inlab.py index e9db453ac..99bf3ce29 100755 --- a/test_regress/t/t_interface_ref_trace_inlab.py +++ b/test_regress/t/t_interface_ref_trace_inlab.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ref_trace_inlb.py b/test_regress/t/t_interface_ref_trace_inlb.py index 48d3a1ba3..cf60c2d4f 100755 --- a/test_regress/t/t_interface_ref_trace_inlb.py +++ b/test_regress/t/t_interface_ref_trace_inlb.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ref_trace_noinl.py b/test_regress/t/t_interface_ref_trace_noinl.py index 81fca1242..537d3408e 100755 --- a/test_regress/t/t_interface_ref_trace_noinl.py +++ b/test_regress/t/t_interface_ref_trace_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ref_trace_noinl_notrace.py b/test_regress/t/t_interface_ref_trace_noinl_notrace.py index d646cb61b..9e768b778 100755 --- a/test_regress/t/t_interface_ref_trace_noinl_notrace.py +++ b/test_regress/t/t_interface_ref_trace_noinl_notrace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_ref_trace_saif.py b/test_regress/t/t_interface_ref_trace_saif.py index c5179ceed..8ed547ac1 100755 --- a/test_regress/t/t_interface_ref_trace_saif.py +++ b/test_regress/t/t_interface_ref_trace_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_size_bad.py b/test_regress/t/t_interface_size_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_size_bad.py +++ b/test_regress/t/t_interface_size_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_size_bad.v b/test_regress/t/t_interface_size_bad.v index e7ea7b153..b02af2043 100644 --- a/test_regress/t/t_interface_size_bad.v +++ b/test_regress/t/t_interface_size_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Demonstrate deferred linking error messages // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Johan Bjork. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Johan Bjork // SPDX-License-Identifier: CC0-1.0 interface foo_intf; diff --git a/test_regress/t/t_interface_star.py b/test_regress/t/t_interface_star.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_star.py +++ b/test_regress/t/t_interface_star.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_star.v b/test_regress/t/t_interface_star.v index 76ef1ea20..0f540d3a4 100644 --- a/test_regress/t/t_interface_star.v +++ b/test_regress/t/t_interface_star.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_interface_top_bad.py b/test_regress/t/t_interface_top_bad.py index 3def97587..71ef8b6c0 100755 --- a/test_regress/t/t_interface_top_bad.py +++ b/test_regress/t/t_interface_top_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_top_bad.v b/test_regress/t/t_interface_top_bad.v index 0de35cbc5..d7c74e7b8 100644 --- a/test_regress/t/t_interface_top_bad.v +++ b/test_regress/t/t_interface_top_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface ifc; diff --git a/test_regress/t/t_interface_twod.py b/test_regress/t/t_interface_twod.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_twod.py +++ b/test_regress/t/t_interface_twod.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_twod.v b/test_regress/t/t_interface_twod.v index b41b3435c..95032d9d2 100644 --- a/test_regress/t/t_interface_twod.v +++ b/test_regress/t/t_interface_twod.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface ifc; diff --git a/test_regress/t/t_interface_twod_noinl.py b/test_regress/t/t_interface_twod_noinl.py index 2c5b11cf0..6ba3e743e 100755 --- a/test_regress/t/t_interface_twod_noinl.py +++ b/test_regress/t/t_interface_twod_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_type_ref_internal.py b/test_regress/t/t_interface_type_ref_internal.py new file mode 100755 index 000000000..84b274f68 --- /dev/null +++ b/test_regress/t/t_interface_type_ref_internal.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_type_ref_internal.v b/test_regress/t/t_interface_type_ref_internal.v new file mode 100644 index 000000000..e8e38966c --- /dev/null +++ b/test_regress/t/t_interface_type_ref_internal.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +interface ifc #( + parameter int width +) ( + input logic [width-1:0] b +); + logic [width-1:0] a; + typedef logic [width-1:0] type_t; + always_comb a = type_t'(b); +endinterface + +module t; + logic [15:0] x; + ifc #(.width(16)) x_ifc (x); + logic [7:0] y; + ifc #(.width(8)) y_ifc (y); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_typedef.py b/test_regress/t/t_interface_typedef.py index 62c547843..a87f14d38 100755 --- a/test_regress/t/t_interface_typedef.py +++ b/test_regress/t/t_interface_typedef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_typedef.v b/test_regress/t/t_interface_typedef.v index 2085e38bc..abb21d448 100644 --- a/test_regress/t/t_interface_typedef.v +++ b/test_regress/t/t_interface_typedef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_interface_typedef2.py b/test_regress/t/t_interface_typedef2.py index 62c547843..a87f14d38 100755 --- a/test_regress/t/t_interface_typedef2.py +++ b/test_regress/t/t_interface_typedef2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_typedef2.v b/test_regress/t/t_interface_typedef2.v index b54aa9dbc..479c14d7d 100644 --- a/test_regress/t/t_interface_typedef2.v +++ b/test_regress/t/t_interface_typedef2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface common_intf #( diff --git a/test_regress/t/t_interface_typedef3.py b/test_regress/t/t_interface_typedef3.py index da7d64435..96005884d 100755 --- a/test_regress/t/t_interface_typedef3.py +++ b/test_regress/t/t_interface_typedef3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_typedef3.v b/test_regress/t/t_interface_typedef3.v index f77507742..9d653344e 100644 --- a/test_regress/t/t_interface_typedef3.v +++ b/test_regress/t/t_interface_typedef3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_interface_typedef_bad.py b/test_regress/t/t_interface_typedef_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_interface_typedef_bad.py +++ b/test_regress/t/t_interface_typedef_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_typedef_bad.v b/test_regress/t/t_interface_typedef_bad.v index e71a0bcc3..e72b45942 100644 --- a/test_regress/t/t_interface_typedef_bad.v +++ b/test_regress/t/t_interface_typedef_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface ifc; diff --git a/test_regress/t/t_interface_typo_bad.py b/test_regress/t/t_interface_typo_bad.py index 9047bac40..0d823a55a 100755 --- a/test_regress/t/t_interface_typo_bad.py +++ b/test_regress/t/t_interface_typo_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_typo_bad.v b/test_regress/t/t_interface_typo_bad.v index 73c08f3fc..f7da3da16 100644 --- a/test_regress/t/t_interface_typo_bad.v +++ b/test_regress/t/t_interface_typo_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Todd Strader // SPDX-License-Identifier: CC0-1.0 //bug1097 diff --git a/test_regress/t/t_interface_virtual.py b/test_regress/t/t_interface_virtual.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_interface_virtual.py +++ b/test_regress/t/t_interface_virtual.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual.v b/test_regress/t/t_interface_virtual.v index 7a034b7ab..bbd93b75c 100644 --- a/test_regress/t/t_interface_virtual.v +++ b/test_regress/t/t_interface_virtual.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Arkadiusz Kozdra. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Arkadiusz Kozdra // SPDX-License-Identifier: CC0-1.0 // See also t_interface_virtual_bad.v diff --git a/test_regress/t/t_interface_virtual_bad.py b/test_regress/t/t_interface_virtual_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_virtual_bad.py +++ b/test_regress/t/t_interface_virtual_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_bad.v b/test_regress/t/t_interface_virtual_bad.v index ebd0449d9..923a4352f 100644 --- a/test_regress/t/t_interface_virtual_bad.v +++ b/test_regress/t/t_interface_virtual_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Arkadiusz Kozdra. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Arkadiusz Kozdra // SPDX-License-Identifier: CC0-1.0 // See also t_interface_virtual.v diff --git a/test_regress/t/t_interface_virtual_cond.py b/test_regress/t/t_interface_virtual_cond.py index 055e14291..514786060 100755 --- a/test_regress/t/t_interface_virtual_cond.py +++ b/test_regress/t/t_interface_virtual_cond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_cond.v b/test_regress/t/t_interface_virtual_cond.v index e0f74d1d0..5d9af886c 100644 --- a/test_regress/t/t_interface_virtual_cond.v +++ b/test_regress/t/t_interface_virtual_cond.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface Bus; diff --git a/test_regress/t/t_interface_virtual_controlflow.py b/test_regress/t/t_interface_virtual_controlflow.py index 65da60c84..ab012d5ce 100755 --- a/test_regress/t/t_interface_virtual_controlflow.py +++ b/test_regress/t/t_interface_virtual_controlflow.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_controlflow.v b/test_regress/t/t_interface_virtual_controlflow.v index f8d03dc8e..8a9423728 100644 --- a/test_regress/t/t_interface_virtual_controlflow.v +++ b/test_regress/t/t_interface_virtual_controlflow.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 interface Bus1; diff --git a/test_regress/t/t_interface_virtual_do_while.py b/test_regress/t/t_interface_virtual_do_while.py new file mode 100755 index 000000000..b6e5d043a --- /dev/null +++ b/test_regress/t/t_interface_virtual_do_while.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary", "--unroll-stmts", "0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_do_while.v b/test_regress/t/t_interface_virtual_do_while.v new file mode 100644 index 000000000..5137fe530 --- /dev/null +++ b/test_regress/t/t_interface_virtual_do_while.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' +// +// Alias type check error test. +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +interface Bus; + bit data; +endinterface + +module t; + Bus intf (); + virtual Bus vif = intf; + bit ok = 0; + + function logic write_data(output bit data); + data = ~data; + return data; + endfunction + + initial @(posedge vif.data) ok = 1; + + initial begin + static bit first = 1; + #1; + do begin + if (!first) $stop; + first = 0; + end while (!write_data( + vif.data + )); + #1; + if (ok != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_virtual_for.py b/test_regress/t/t_interface_virtual_for.py new file mode 100755 index 000000000..b6e5d043a --- /dev/null +++ b/test_regress/t/t_interface_virtual_for.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary", "--unroll-stmts", "0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_for.v b/test_regress/t/t_interface_virtual_for.v new file mode 100644 index 000000000..2a5dba181 --- /dev/null +++ b/test_regress/t/t_interface_virtual_for.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' +// +// Alias type check error test. +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +interface Bus; + bit data; +endinterface + +module t; + Bus intf (); + virtual Bus vif = intf; + bit ok = 0; + + function logic write_data(output bit data); + data = ~data; + return data; + endfunction + + initial @(posedge vif.data) ok = 1; + + initial begin + #1; + for (int i = 0; !write_data(vif.data); i++) $stop; + #1 if (ok != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_virtual_if.py b/test_regress/t/t_interface_virtual_if.py new file mode 100755 index 000000000..7ded63f3a --- /dev/null +++ b/test_regress/t/t_interface_virtual_if.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_if.v b/test_regress/t/t_interface_virtual_if.v new file mode 100644 index 000000000..a242c609e --- /dev/null +++ b/test_regress/t/t_interface_virtual_if.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' +// +// Alias type check error test. +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +interface Bus; + bit data; +endinterface + +module t; + Bus intf (); + virtual Bus vif = intf; + bit ok = 0; + + function logic write_data(output bit data); + data = ~data; + return data; + endfunction + + initial @(posedge vif.data) ok = 1; + + initial begin + #1; + if (!write_data(vif.data)) $stop; + #1 if (ok != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_virtual_inl.py b/test_regress/t/t_interface_virtual_inl.py index 0276a9140..3d30f0a27 100755 --- a/test_regress/t/t_interface_virtual_inl.py +++ b/test_regress/t/t_interface_virtual_inl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_missing_bad.py b/test_regress/t/t_interface_virtual_missing_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_interface_virtual_missing_bad.py +++ b/test_regress/t/t_interface_virtual_missing_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_missing_bad.v b/test_regress/t/t_interface_virtual_missing_bad.v index 9fee9bcb2..2196f25ff 100644 --- a/test_regress/t/t_interface_virtual_missing_bad.v +++ b/test_regress/t/t_interface_virtual_missing_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_interface_virtual_nocell.py b/test_regress/t/t_interface_virtual_nocell.py new file mode 100755 index 000000000..84b274f68 --- /dev/null +++ b/test_regress/t/t_interface_virtual_nocell.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_nocell.v b/test_regress/t/t_interface_virtual_nocell.v new file mode 100644 index 000000000..2b3fd7fd7 --- /dev/null +++ b/test_regress/t/t_interface_virtual_nocell.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +interface mem_if #( + int unsigned ADDR_SIZE = 16 +); +endinterface + +module t; + class Cls #( + type T = int + ); + endclass + + // Note the referred-to virtual class is only used here, not instantiated + typedef Cls#(virtual mem_if #(8)) cls_mem_if_t; + typedef Cls#(virtual mem_if #()) cls_def_if_t; + + initial begin + cls_mem_if_t c; + cls_def_if_t d; + c = new; + d = new; + $finish; + end + +endmodule diff --git a/test_regress/t/t_interface_virtual_opt.py b/test_regress/t/t_interface_virtual_opt.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_virtual_opt.py +++ b/test_regress/t/t_interface_virtual_opt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_opt.v b/test_regress/t/t_interface_virtual_opt.v index d538fc009..c9e1a85f4 100644 --- a/test_regress/t/t_interface_virtual_opt.v +++ b/test_regress/t/t_interface_virtual_opt.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 interface Bus; diff --git a/test_regress/t/t_interface_virtual_param.py b/test_regress/t/t_interface_virtual_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_virtual_param.py +++ b/test_regress/t/t_interface_virtual_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_param.v b/test_regress/t/t_interface_virtual_param.v index a1596b4ff..27eb0b0b5 100644 --- a/test_regress/t/t_interface_virtual_param.v +++ b/test_regress/t/t_interface_virtual_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 interface Bus #(parameter int W = 1, X = 2); diff --git a/test_regress/t/t_interface_virtual_sched_act.py b/test_regress/t/t_interface_virtual_sched_act.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_interface_virtual_sched_act.py +++ b/test_regress/t/t_interface_virtual_sched_act.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_sched_act.v b/test_regress/t/t_interface_virtual_sched_act.v index 7f37b8a37..603c677f8 100644 --- a/test_regress/t/t_interface_virtual_sched_act.v +++ b/test_regress/t/t_interface_virtual_sched_act.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 interface Bus; diff --git a/test_regress/t/t_interface_virtual_sched_ico.py b/test_regress/t/t_interface_virtual_sched_ico.py index 79de66837..7a2535255 100755 --- a/test_regress/t/t_interface_virtual_sched_ico.py +++ b/test_regress/t/t_interface_virtual_sched_ico.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_sched_ico.v b/test_regress/t/t_interface_virtual_sched_ico.v index 3e1b8e280..50e21d59a 100644 --- a/test_regress/t/t_interface_virtual_sched_ico.v +++ b/test_regress/t/t_interface_virtual_sched_ico.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 interface If; diff --git a/test_regress/t/t_interface_virtual_sched_nba.py b/test_regress/t/t_interface_virtual_sched_nba.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_interface_virtual_sched_nba.py +++ b/test_regress/t/t_interface_virtual_sched_nba.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_sched_nba.v b/test_regress/t/t_interface_virtual_sched_nba.v index 3a22fd5c9..1f79571ac 100644 --- a/test_regress/t/t_interface_virtual_sched_nba.v +++ b/test_regress/t/t_interface_virtual_sched_nba.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 interface Bus1; diff --git a/test_regress/t/t_interface_virtual_timing.py b/test_regress/t/t_interface_virtual_timing.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_interface_virtual_timing.py +++ b/test_regress/t/t_interface_virtual_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_timing.v b/test_regress/t/t_interface_virtual_timing.v index 6d6d285d7..738e64b2f 100644 --- a/test_regress/t/t_interface_virtual_timing.v +++ b/test_regress/t/t_interface_virtual_timing.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 interface Bus; diff --git a/test_regress/t/t_interface_virtual_unsup.out b/test_regress/t/t_interface_virtual_unsup.out deleted file mode 100644 index e4a69ebac..000000000 --- a/test_regress/t/t_interface_virtual_unsup.out +++ /dev/null @@ -1,11 +0,0 @@ -%Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:24:22: Unsupported: Write to virtual interface in if condition - 24 | if (write_data(vif.data)) $write("dummy op"); - | ^~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:25:25: Unsupported: Write to virtual interface in loop condition - 25 | while (write_data(vif.data)); - | ^~~ -%Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:26:30: Unsupported: Write to virtual interface in loop condition - 26 | do ; while (write_data(vif.data)); - | ^~~ -%Error: Exiting due to diff --git a/test_regress/t/t_interface_virtual_unsup.v b/test_regress/t/t_interface_virtual_unsup.v deleted file mode 100644 index dd1f83774..000000000 --- a/test_regress/t/t_interface_virtual_unsup.v +++ /dev/null @@ -1,30 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -// NOTE: Once this is supported, t_interface_virtual_cond is no longer needed - -interface Bus; - logic [15:0] data; -endinterface - -module t; - Bus intf(); - virtual Bus vif = intf; - - function logic write_data(output logic[15:0] data); - data = 'hdead; - return 1; - endfunction - - // verilator lint_off INFINITELOOP - initial begin - if (write_data(vif.data)) $write("dummy op"); - while (write_data(vif.data)); - do ; while (write_data(vif.data)); - for (int i = 0; write_data(vif.data++); i++); - end - -endmodule diff --git a/test_regress/t/t_interface_virtual_unused.py b/test_regress/t/t_interface_virtual_unused.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_interface_virtual_unused.py +++ b/test_regress/t/t_interface_virtual_unused.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_unused.v b/test_regress/t/t_interface_virtual_unused.v index 225514872..ed3343e02 100644 --- a/test_regress/t/t_interface_virtual_unused.v +++ b/test_regress/t/t_interface_virtual_unused.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Arkadiusz Kozdra. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Arkadiusz Kozdra // SPDX-License-Identifier: CC0-1.0 // See also t_interface_virtual.v diff --git a/test_regress/t/t_interface_virtual_unused2.py b/test_regress/t/t_interface_virtual_unused2.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_interface_virtual_unused2.py +++ b/test_regress/t/t_interface_virtual_unused2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_unused2.v b/test_regress/t/t_interface_virtual_unused2.v index 7feb732ce..d9ea25eba 100644 --- a/test_regress/t/t_interface_virtual_unused2.v +++ b/test_regress/t/t_interface_virtual_unused2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface QBus(input logic k); diff --git a/test_regress/t/t_interface_virtual_unused3.py b/test_regress/t/t_interface_virtual_unused3.py index 147fe6faf..0379f0dd0 100755 --- a/test_regress/t/t_interface_virtual_unused3.py +++ b/test_regress/t/t_interface_virtual_unused3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_virtual_unused3.v b/test_regress/t/t_interface_virtual_unused3.v index fbac6d425..79946aade 100644 --- a/test_regress/t/t_interface_virtual_unused3.v +++ b/test_regress/t/t_interface_virtual_unused3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface stream_ifc #( diff --git a/test_regress/t/t_interface_virtual_while.py b/test_regress/t/t_interface_virtual_while.py new file mode 100755 index 000000000..b6e5d043a --- /dev/null +++ b/test_regress/t/t_interface_virtual_while.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary", "--unroll-stmts", "0"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_virtual_while.v b/test_regress/t/t_interface_virtual_while.v new file mode 100644 index 000000000..0bda2b17f --- /dev/null +++ b/test_regress/t/t_interface_virtual_while.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' +// +// Alias type check error test. +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +interface Bus; + bit data; +endinterface + +module t; + Bus intf (); + virtual Bus vif = intf; + bit ok = 0; + + function logic write_data(output bit data); + data = ~data; + return data; + endfunction + + initial @(posedge vif.data) ok = 1; + + initial begin + #1; + while (!write_data(vif.data)) $stop; + #1 if (ok != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_wire_bad.py b/test_regress/t/t_interface_wire_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_wire_bad.py +++ b/test_regress/t/t_interface_wire_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_wire_bad.v b/test_regress/t/t_interface_wire_bad.v index d4401b6e1..f6d8067f6 100644 --- a/test_regress/t/t_interface_wire_bad.v +++ b/test_regress/t/t_interface_wire_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface Ifc; diff --git a/test_regress/t/t_interface_wire_bad_param.py b/test_regress/t/t_interface_wire_bad_param.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_wire_bad_param.py +++ b/test_regress/t/t_interface_wire_bad_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_wire_bad_param.v b/test_regress/t/t_interface_wire_bad_param.v index 5399bbd9a..e1660f0cc 100644 --- a/test_regress/t/t_interface_wire_bad_param.v +++ b/test_regress/t/t_interface_wire_bad_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface Ifc; diff --git a/test_regress/t/t_interface_wrong_bad.py b/test_regress/t/t_interface_wrong_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_interface_wrong_bad.py +++ b/test_regress/t/t_interface_wrong_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_interface_wrong_bad.v b/test_regress/t/t_interface_wrong_bad.v index 63ed412a4..58c455662 100644 --- a/test_regress/t/t_interface_wrong_bad.v +++ b/test_regress/t/t_interface_wrong_bad.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Using the wrong kind of interface in a portmap // should cause an error // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Todd Strader // SPDX-License-Identifier: CC0-1.0 interface foo_intf; diff --git a/test_regress/t/t_json_only_begin_hier.out b/test_regress/t/t_json_only_begin_hier.out index ccc21a73e..3a0e1aa16 100644 --- a/test_regress/t/t_json_only_begin_hier.out +++ b/test_regress/t/t_json_only_begin_hier.out @@ -1,42 +1,42 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"test","addr":"(E)","loc":"d,22:8,22:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"test","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"test","addr":"(E)","loc":"d,22:8,22:12","origName":"test","verilogName":"test","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"N","addr":"(F)","loc":"d,24:12,24:13","dtypep":"(G)","origName":"N","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":true,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"GENVAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"GENBLOCK","name":"FOR_GENERATE","addr":"(H)","loc":"d,25:14,25:17","implied":true,"unnamed":false,"genforp": [],"itemsp": []}, - {"type":"GENBLOCK","name":"FOR_GENERATE[0]","addr":"(I)","loc":"d,27:21,27:31","implied":false,"unnamed":false,"genforp": [], + {"type":"VAR","name":"N","addr":"(F)","loc":"d,24:12,24:13","dtypep":"(G)","origName":"N","verilogName":"N","direction":"NONE","isUsedLoopIdx":true,"lifetime":"VSTATICI","varType":"GENVAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"GENBLOCK","name":"FOR_GENERATE","addr":"(H)","loc":"d,25:14,25:17","implied":true,"genforp": [],"itemsp": []}, + {"type":"GENBLOCK","name":"FOR_GENERATE[0]","addr":"(I)","loc":"d,27:21,27:31","genforp": [], "itemsp": [ - {"type":"CELL","name":"submod_for","addr":"(J)","loc":"d,27:21,27:31","origName":"submod_for","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"GENBLOCK","name":"genblk1","addr":"(L)","loc":"d,28:19,28:24","implied":false,"unnamed":true,"genforp": [], + {"type":"CELL","name":"submod_for","addr":"(J)","loc":"d,27:21,27:31","origName":"submod_for","verilogName":"submod_for","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, + {"type":"GENBLOCK","name":"genblk1","addr":"(L)","loc":"d,28:19,28:24","unnamed":true,"genforp": [], "itemsp": [ - {"type":"CELL","name":"submod_2","addr":"(M)","loc":"d,29:25,29:33","origName":"submod_2","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_2","addr":"(M)","loc":"d,29:25,29:33","origName":"submod_2","verilogName":"submod_2","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"CELL","name":"submod_3","addr":"(N)","loc":"d,31:21,31:29","origName":"submod_3","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_3","addr":"(N)","loc":"d,31:21,31:29","origName":"submod_3","verilogName":"submod_3","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"GENBLOCK","name":"FOR_GENERATE[1]","addr":"(O)","loc":"d,27:21,27:31","implied":false,"unnamed":false,"genforp": [], + {"type":"GENBLOCK","name":"FOR_GENERATE[1]","addr":"(O)","loc":"d,27:21,27:31","genforp": [], "itemsp": [ - {"type":"CELL","name":"submod_for","addr":"(P)","loc":"d,27:21,27:31","origName":"submod_for","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"GENBLOCK","name":"genblk1","addr":"(Q)","loc":"d,28:19,28:24","implied":false,"unnamed":true,"genforp": [], + {"type":"CELL","name":"submod_for","addr":"(P)","loc":"d,27:21,27:31","origName":"submod_for","verilogName":"submod_for","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, + {"type":"GENBLOCK","name":"genblk1","addr":"(Q)","loc":"d,28:19,28:24","unnamed":true,"genforp": [], "itemsp": [ - {"type":"CELL","name":"submod_2","addr":"(R)","loc":"d,29:25,29:33","origName":"submod_2","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_2","addr":"(R)","loc":"d,29:25,29:33","origName":"submod_2","verilogName":"submod_2","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"CELL","name":"submod_3","addr":"(S)","loc":"d,31:21,31:29","origName":"submod_3","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_3","addr":"(S)","loc":"d,31:21,31:29","origName":"submod_3","verilogName":"submod_3","modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]} ]}, - {"type":"MODULE","name":"submod","addr":"(K)","loc":"d,10:8,10:14","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"submod","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"submod","addr":"(K)","loc":"d,10:8,10:14","origName":"submod","verilogName":"submod","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"GENBLOCK","name":"submod_gen","addr":"(T)","loc":"d,12:19,12:29","implied":false,"unnamed":false,"genforp": [], + {"type":"GENBLOCK","name":"submod_gen","addr":"(T)","loc":"d,12:19,12:29","genforp": [], "itemsp": [ - {"type":"VAR","name":"l1_sig","addr":"(U)","loc":"d,13:14,13:20","dtypep":"(V)","origName":"l1_sig","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"GENBLOCK","name":"nested_gen","addr":"(W)","loc":"d,14:23,14:33","implied":false,"unnamed":false,"genforp": [], + {"type":"VAR","name":"l1_sig","addr":"(U)","loc":"d,13:14,13:20","dtypep":"(V)","origName":"l1_sig","verilogName":"l1_sig","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"GENBLOCK","name":"nested_gen","addr":"(W)","loc":"d,14:23,14:33","genforp": [], "itemsp": [ - {"type":"CELL","name":"submod_nested","addr":"(X)","loc":"d,15:21,15:34","origName":"submod_nested","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_nested","addr":"(X)","loc":"d,15:21,15:34","origName":"submod_nested","verilogName":"submod_nested","modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"CELL","name":"submod_l1","addr":"(Z)","loc":"d,17:17,17:26","origName":"submod_l1","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_l1","addr":"(Z)","loc":"d,17:17,17:26","origName":"submod_l1","verilogName":"submod_l1","modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"CELL","name":"submod_l0","addr":"(AB)","loc":"d,19:13,19:22","origName":"submod_l0","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + {"type":"CELL","name":"submod_l0","addr":"(AB)","loc":"d,19:13,19:22","origName":"submod_l0","verilogName":"submod_l0","modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"MODULE","name":"submod2","addr":"(Y)","loc":"d,7:8,7:15","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"submod2","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],"stmtsp": []} + {"type":"MODULE","name":"submod2","addr":"(Y)","loc":"d,7:8,7:15","origName":"submod2","verilogName":"submod2","level":3,"timeunit":"1ps","inlinesp": [],"stmtsp": []} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", @@ -46,7 +46,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(BB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(BB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(CB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(BB)","varsp": [],"blocksp": [],"inlinesp": []} ]} diff --git a/test_regress/t/t_json_only_begin_hier.py b/test_regress/t/t_json_only_begin_hier.py index 5fa0ddc00..2c764bd51 100755 --- a/test_regress/t/t_json_only_begin_hier.py +++ b/test_regress/t/t_json_only_begin_hier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_json_only_begin_hier.v b/test_regress/t/t_json_only_begin_hier.v index 1e29f0133..dd0ed0c91 100644 --- a/test_regress/t/t_json_only_begin_hier.v +++ b/test_regress/t/t_json_only_begin_hier.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Risto Pejasinovic. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Risto Pejasinovic // SPDX-License-Identifier: CC0-1.0 module submod2 (); diff --git a/test_regress/t/t_json_only_debugcheck.out b/test_regress/t/t_json_only_debugcheck.out index bd6608cac..b360d118a 100644 --- a/test_regress/t/t_json_only_debugcheck.out +++ b/test_regress/t/t_json_only_debugcheck.out @@ -1,142 +1,144 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"UNLINKED","evalp":"(F)","evalNbap":"(G)","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(H)", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"UNLINKED","evalp":"(F)","evalNbap":"(G)","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(H)","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"$root","addr":"(I)","loc":"d,11:8,11:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"$root","addr":"(I)","loc":"d,11:8,11:9","origName":"$root","verilogName":"$root","level":1,"modPublic":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk","addr":"(J)","loc":"d,15:10,15:13","dtypep":"(K)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - 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{"type":"CCAST","name":"","addr":"(FF)","loc":"d,41:15,41:16","dtypep":"(CC)","size":32, + {"type":"CCAST","name":"","addr":"(IF)","loc":"d,41:15,41:16","dtypep":"(FC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(GF)","loc":"d,41:15,41:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(JF)","loc":"d,41:15,41:16","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -305,43 +307,43 @@ ]} ], "thensp": [ - {"type":"DISPLAY","name":"","addr":"(HF)","loc":"d,41:59,41:65", + {"type":"DISPLAY","name":"","addr":"(KF)","loc":"d,41:59,41:65", "fmtp": [ - {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:41: got='h%x exp='h3\\n","addr":"(IF)","loc":"d,41:59,41:65","dtypep":"(PB)", + {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:41: got='h%x exp='h3\\n","addr":"(LF)","loc":"d,41:59,41:65","dtypep":"(SB)", "exprsp": [ - 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{"type":"AND","name":"","addr":"(TF)","loc":"d,41:138,41:139","dtypep":"(CC)", + {"type":"AND","name":"","addr":"(WF)","loc":"d,41:138,41:139","dtypep":"(FC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(UF)","loc":"d,41:138,41:139","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(XF)","loc":"d,41:138,41:139","dtypep":"(HC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(VF)","loc":"d,41:138,41:139","dtypep":"(CC)","size":32, + {"type":"CCAST","name":"","addr":"(YF)","loc":"d,41:138,41:139","dtypep":"(FC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(WF)","loc":"d,41:138,41:139","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(ZF)","loc":"d,41:138,41:139","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -351,48 +353,48 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(XF)","loc":"d,41:174,41:179","isFatal":false} + {"type":"STOP","name":"","addr":"(AG)","loc":"d,41:174,41:179"} ],"elsesp": []}, - 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{"type":"CONST","name":"32'h7","addr":"(IG)","loc":"d,42:15,42:16","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(LG)","loc":"d,42:15,42:16","dtypep":"(HC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(JG)","loc":"d,42:15,42:16","dtypep":"(CC)", + {"type":"ARRAYSEL","name":"","addr":"(MG)","loc":"d,42:15,42:16","dtypep":"(FC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KG)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(NG)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(LG)","loc":"d,42:15,42:16","dtypep":"(CC)", + {"type":"AND","name":"","addr":"(OG)","loc":"d,42:15,42:16","dtypep":"(FC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(MG)","loc":"d,42:15,42:16","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(PG)","loc":"d,42:15,42:16","dtypep":"(HC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(NG)","loc":"d,42:15,42:16","dtypep":"(CC)","size":32, + {"type":"CCAST","name":"","addr":"(QG)","loc":"d,42:15,42:16","dtypep":"(FC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(OG)","loc":"d,42:15,42:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(RG)","loc":"d,42:15,42:16","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -403,43 +405,43 @@ ]} ], "thensp": [ - {"type":"DISPLAY","name":"","addr":"(PG)","loc":"d,42:51,42:57", + {"type":"DISPLAY","name":"","addr":"(SG)","loc":"d,42:51,42:57", "fmtp": [ - {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:42: got='h%x exp='h3\\n","addr":"(QG)","loc":"d,42:51,42:57","dtypep":"(PB)", + {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:42: got='h%x exp='h3\\n","addr":"(TG)","loc":"d,42:51,42:57","dtypep":"(SB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(RG)","loc":"d,42:130,42:131","dtypep":"(RB)", + {"type":"ARRAYSEL","name":"","addr":"(UG)","loc":"d,42:130,42:131","dtypep":"(UB)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(SG)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(VG)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(TG)","loc":"d,42:130,42:131","dtypep":"(CC)", + {"type":"AND","name":"","addr":"(WG)","loc":"d,42:130,42:131","dtypep":"(FC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(UG)","loc":"d,42:130,42:131","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(XG)","loc":"d,42:130,42:131","dtypep":"(HC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(VG)","loc":"d,42:130,42:131","dtypep":"(CC)", + {"type":"ARRAYSEL","name":"","addr":"(YG)","loc":"d,42:130,42:131","dtypep":"(FC)", "fromp": [ - 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{"type":"AND","name":"","addr":"(BH)","loc":"d,42:130,42:131","dtypep":"(CC)", + {"type":"AND","name":"","addr":"(EH)","loc":"d,42:130,42:131","dtypep":"(FC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(CH)","loc":"d,42:130,42:131","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(FH)","loc":"d,42:130,42:131","dtypep":"(HC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(DH)","loc":"d,42:130,42:131","dtypep":"(CC)","size":32, + {"type":"CCAST","name":"","addr":"(GH)","loc":"d,42:130,42:131","dtypep":"(FC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(EH)","loc":"d,42:130,42:131","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(HH)","loc":"d,42:130,42:131","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -449,48 +451,48 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(FH)","loc":"d,42:158,42:163","isFatal":false} + {"type":"STOP","name":"","addr":"(IH)","loc":"d,42:158,42:163"} ],"elsesp": []}, - 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{"type":"CONST","name":"32'h7","addr":"(QH)","loc":"d,43:15,43:16","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(TH)","loc":"d,43:15,43:16","dtypep":"(HC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(RH)","loc":"d,43:15,43:16","dtypep":"(CC)", + {"type":"ARRAYSEL","name":"","addr":"(UH)","loc":"d,43:15,43:16","dtypep":"(FC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(SH)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(VH)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(TH)","loc":"d,43:15,43:16","dtypep":"(CC)", + {"type":"AND","name":"","addr":"(WH)","loc":"d,43:15,43:16","dtypep":"(FC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(UH)","loc":"d,43:15,43:16","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(XH)","loc":"d,43:15,43:16","dtypep":"(HC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(VH)","loc":"d,43:15,43:16","dtypep":"(CC)","size":32, + {"type":"CCAST","name":"","addr":"(YH)","loc":"d,43:15,43:16","dtypep":"(FC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(WH)","loc":"d,43:15,43:16","dtypep":"(CC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(ZH)","loc":"d,43:15,43:16","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -501,43 +503,43 @@ ]} ], "thensp": [ - {"type":"DISPLAY","name":"","addr":"(XH)","loc":"d,43:47,43:53", + {"type":"DISPLAY","name":"","addr":"(AI)","loc":"d,43:47,43:53", "fmtp": [ - {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:43: got='h%x exp='h3\\n","addr":"(YH)","loc":"d,43:47,43:53","dtypep":"(PB)", + {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:43: got='h%x exp='h3\\n","addr":"(BI)","loc":"d,43:47,43:53","dtypep":"(SB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(ZH)","loc":"d,43:126,43:127","dtypep":"(RB)", + {"type":"ARRAYSEL","name":"","addr":"(CI)","loc":"d,43:126,43:127","dtypep":"(UB)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(AI)","loc":"d,17:12,17:16","dtypep":"(ZB)","access":"RD","varp":"(AC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(DI)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(BI)","loc":"d,43:126,43:127","dtypep":"(CC)", + {"type":"AND","name":"","addr":"(EI)","loc":"d,43:126,43:127","dtypep":"(FC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(CI)","loc":"d,43:126,43:127","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(FI)","loc":"d,43:126,43:127","dtypep":"(HC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(DI)","loc":"d,43:126,43:127","dtypep":"(CC)", + {"type":"ARRAYSEL","name":"","addr":"(GI)","loc":"d,43:126,43:127","dtypep":"(FC)", "fromp": [ - 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{"type":"ENUMITEM","name":"E01","addr":"(NRB)","loc":"d,18:24,18:27","dtypep":"(RB)","rangep": [], + {"type":"ENUMITEM","name":"E01","addr":"(JSB)","loc":"d,18:24,18:27","dtypep":"(UB)","rangep": [], "valuep": [ - {"type":"CONST","name":"4'h1","addr":"(ORB)","loc":"d,18:30,18:31","dtypep":"(RB)"} + {"type":"CONST","name":"4'h1","addr":"(KSB)","loc":"d,18:30,18:31","dtypep":"(UB)"} ]}, - {"type":"ENUMITEM","name":"E03","addr":"(PRB)","loc":"d,19:24,19:27","dtypep":"(RB)","rangep": [], + {"type":"ENUMITEM","name":"E03","addr":"(LSB)","loc":"d,19:24,19:27","dtypep":"(UB)","rangep": [], "valuep": [ - {"type":"CONST","name":"4'h3","addr":"(QRB)","loc":"d,19:30,19:31","dtypep":"(RB)"} + {"type":"CONST","name":"4'h3","addr":"(MSB)","loc":"d,19:30,19:31","dtypep":"(UB)"} ]}, - {"type":"ENUMITEM","name":"E04","addr":"(RRB)","loc":"d,20:24,20:27","dtypep":"(RB)","rangep": [], + {"type":"ENUMITEM","name":"E04","addr":"(NSB)","loc":"d,20:24,20:27","dtypep":"(UB)","rangep": [], "valuep": [ - {"type":"CONST","name":"4'h4","addr":"(SRB)","loc":"d,20:30,20:31","dtypep":"(RB)"} + {"type":"CONST","name":"4'h4","addr":"(OSB)","loc":"d,20:30,20:31","dtypep":"(UB)"} ]} ]}, - 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{"type":"RANGE","name":"","addr":"(TRB)","loc":"d,17:12,17:16","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(PSB)","loc":"d,17:12,17:16", "leftp": [ - {"type":"CONST","name":"32'h7","addr":"(URB)","loc":"d,17:12,17:16","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(QSB)","loc":"d,17:12,17:16","dtypep":"(HC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(VRB)","loc":"d,17:12,17:16","dtypep":"(EC)"} + {"type":"CONST","name":"32'h0","addr":"(RSB)","loc":"d,17:12,17:16","dtypep":"(HC)"} ]} ]}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(TI)","loc":"d,17:12,17:16","dtypep":"(TI)","isCompound":false,"declRange":"[7:0]","generic":false,"refDTypep":"(MRB)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(WI)","loc":"d,17:12,17:16","dtypep":"(WI)","declRange":"[7:0]","refDTypep":"(ISB)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(WRB)","loc":"d,17:12,17:16","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(SSB)","loc":"d,17:12,17:16", "leftp": [ - {"type":"CONST","name":"32'h7","addr":"(XRB)","loc":"d,17:12,17:16","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(TSB)","loc":"d,17:12,17:16","dtypep":"(HC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(YRB)","loc":"d,17:12,17:16","dtypep":"(EC)"} + {"type":"CONST","name":"32'h0","addr":"(USB)","loc":"d,17:12,17:16","dtypep":"(HC)"} ]} ]}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(FM)","loc":"d,17:12,17:16","dtypep":"(FM)","isCompound":true,"declRange":"[7:0]","generic":false,"refDTypep":"(PB)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(IM)","loc":"d,17:12,17:16","dtypep":"(IM)","isCompound":true,"declRange":"[7:0]","refDTypep":"(SB)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(ZRB)","loc":"d,17:12,17:16","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(VSB)","loc":"d,17:12,17:16", "leftp": [ - {"type":"CONST","name":"32'h7","addr":"(ASB)","loc":"d,17:12,17:16","dtypep":"(EC)"} + {"type":"CONST","name":"32'h7","addr":"(WSB)","loc":"d,17:12,17:16","dtypep":"(HC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(BSB)","loc":"d,17:12,17:16","dtypep":"(EC)"} + {"type":"CONST","name":"32'h0","addr":"(XSB)","loc":"d,17:12,17:16","dtypep":"(HC)"} ]} ]}, - {"type":"BASICDTYPE","name":"logic","addr":"(IB)","loc":"d,23:23,23:24","dtypep":"(IB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"VOIDDTYPE","name":"","addr":"(AB)","loc":"a,0:0,0:0","dtypep":"(AB)","generic":false}, - {"type":"BASICDTYPE","name":"bit","addr":"(EN)","loc":"a,0:0,0:0","dtypep":"(EN)","keyword":"bit","range":"63:0","generic":true,"rangep": []}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(T)","loc":"d,11:8,11:9","dtypep":"(T)","isCompound":false,"declRange":"[0:0]","generic":false,"refDTypep":"(EN)","childDTypep": [], + {"type":"BASICDTYPE","name":"logic","addr":"(LB)","loc":"d,23:23,23:24","dtypep":"(LB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"VOIDDTYPE","name":"","addr":"(DB)","loc":"a,0:0,0:0","dtypep":"(DB)"}, + {"type":"BASICDTYPE","name":"bit","addr":"(HN)","loc":"a,0:0,0:0","dtypep":"(HN)","keyword":"bit","range":"63:0","generic":true,"rangep": []}, + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(W)","loc":"d,11:8,11:9","dtypep":"(W)","declRange":"[0:0]","refDTypep":"(HN)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(CSB)","loc":"d,11:8,11:9","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(YSB)","loc":"d,11:8,11:9", "leftp": [ - {"type":"CONST","name":"32'h0","addr":"(DSB)","loc":"d,11:8,11:9","dtypep":"(EC)"} + {"type":"CONST","name":"32'h0","addr":"(ZSB)","loc":"d,11:8,11:9","dtypep":"(HC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(ESB)","loc":"d,11:8,11:9","dtypep":"(EC)"} + {"type":"CONST","name":"32'h0","addr":"(ATB)","loc":"d,11:8,11:9","dtypep":"(HC)"} ]} ]}, - {"type":"BASICDTYPE","name":"IData","addr":"(LP)","loc":"a,0:0,0:0","dtypep":"(LP)","keyword":"IData","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(GN)","loc":"d,63:14,63:21","dtypep":"(GN)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"bit","addr":"(KMB)","loc":"d,11:8,11:9","dtypep":"(KMB)","keyword":"bit","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"bit","addr":"(R)","loc":"d,11:8,11:9","dtypep":"(R)","keyword":"bit","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(DB)","loc":"d,63:22,63:25","dtypep":"(DB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,32:11,32:14","dtypep":"(RB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(CC)","loc":"d,38:15,38:16","dtypep":"(CC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(CPB)","loc":"d,15:10,15:13","dtypep":"(CPB)","keyword":"logic","range":"7:0","generic":true,"rangep": []} + {"type":"BASICDTYPE","name":"IData","addr":"(IP)","loc":"a,0:0,0:0","dtypep":"(IP)","keyword":"IData","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(JN)","loc":"d,63:14,63:21","dtypep":"(JN)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"bit","addr":"(P)","loc":"d,11:8,11:9","dtypep":"(P)","keyword":"bit","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"bit","addr":"(U)","loc":"d,11:8,11:9","dtypep":"(U)","keyword":"bit","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(GB)","loc":"d,63:22,63:25","dtypep":"(GB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(UB)","loc":"d,32:11,32:14","dtypep":"(UB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(FC)","loc":"d,38:15,38:16","dtypep":"(FC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(SPB)","loc":"d,15:10,15:13","dtypep":"(SPB)","keyword":"logic","range":"7:0","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(FSB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(BTB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ - {"type":"SCOPE","name":"TOP","addr":"(GSB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(FSB)","varsp": [],"blocksp": [],"inlinesp": []} + {"type":"SCOPE","name":"TOP","addr":"(CTB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(BTB)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} diff --git a/test_regress/t/t_json_only_debugcheck.py b/test_regress/t/t_json_only_debugcheck.py index 5b6b6a7c5..97ce5867d 100755 --- a/test_regress/t/t_json_only_debugcheck.py +++ b/test_regress/t/t_json_only_debugcheck.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_json_only_first.out b/test_regress/t/t_json_only_first.out index 876052c83..9fc577f6f 100644 --- a/test_regress/t/t_json_only_first.out +++ b/test_regress/t/t_json_only_first.out @@ -1,48 +1,48 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"t","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","origName":"t","verilogName":"t","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"q","addr":"(F)","loc":"d,15:22,15:23","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"clk","addr":"(H)","loc":"d,13:10,13:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(J)","loc":"d,14:16,14:17","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"between","addr":"(K)","loc":"d,17:22,17:29","dtypep":"(G)","origName":"between","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"CELL","name":"cell1","addr":"(L)","loc":"d,20:4,20:9","origName":"cell1","recursive":false,"modp":"(M)", + {"type":"VAR","name":"q","addr":"(F)","loc":"d,15:22,15:23","dtypep":"(G)","origName":"q","verilogName":"q","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"clk","addr":"(H)","loc":"d,13:10,13:13","dtypep":"(I)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(J)","loc":"d,14:16,14:17","dtypep":"(G)","origName":"d","verilogName":"d","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"between","addr":"(K)","loc":"d,17:22,17:29","dtypep":"(G)","origName":"between","verilogName":"between","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"CELL","name":"cell1","addr":"(L)","loc":"d,20:4,20:9","origName":"cell1","verilogName":"cell1","modp":"(M)", "pinsp": [ - {"type":"PIN","name":"q","addr":"(N)","loc":"d,20:12,20:13","svDotName":true,"svImplicit":false,"modVarp":"(O)","modPTypep":"UNLINKED", + {"type":"PIN","name":"q","addr":"(N)","loc":"d,20:12,20:13","svDotName":true,"modVarp":"(O)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"between","addr":"(P)","loc":"d,20:14,20:21","dtypep":"(G)","access":"WR","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"clk","addr":"(Q)","loc":"d,21:12,21:15","svDotName":true,"svImplicit":false,"modVarp":"(R)","modPTypep":"UNLINKED", + {"type":"PIN","name":"clk","addr":"(Q)","loc":"d,21:12,21:15","svDotName":true,"modVarp":"(R)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"clk","addr":"(S)","loc":"d,21:42,21:45","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"d","addr":"(T)","loc":"d,22:12,22:13","svDotName":true,"svImplicit":false,"modVarp":"(U)","modPTypep":"UNLINKED", + {"type":"PIN","name":"d","addr":"(T)","loc":"d,22:12,22:13","svDotName":true,"modVarp":"(U)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"d","addr":"(V)","loc":"d,22:42,22:43","dtypep":"(G)","access":"RD","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"CELL","name":"cell2","addr":"(W)","loc":"d,25:6,25:11","origName":"cell2","recursive":false,"modp":"(X)", + {"type":"CELL","name":"cell2","addr":"(W)","loc":"d,25:6,25:11","origName":"cell2","verilogName":"cell2","modp":"(X)", "pinsp": [ - {"type":"PIN","name":"d","addr":"(Y)","loc":"d,25:14,25:15","svDotName":true,"svImplicit":false,"modVarp":"(Z)","modPTypep":"UNLINKED", + {"type":"PIN","name":"d","addr":"(Y)","loc":"d,25:14,25:15","svDotName":true,"modVarp":"(Z)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"between","addr":"(AB)","loc":"d,25:16,25:23","dtypep":"(G)","access":"RD","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"q","addr":"(BB)","loc":"d,26:14,26:15","svDotName":true,"svImplicit":false,"modVarp":"(CB)","modPTypep":"UNLINKED", + {"type":"PIN","name":"q","addr":"(BB)","loc":"d,26:14,26:15","svDotName":true,"modVarp":"(CB)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"q","addr":"(DB)","loc":"d,26:42,26:43","dtypep":"(G)","access":"WR","varp":"(F)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"clk","addr":"(EB)","loc":"d,27:14,27:17","svDotName":true,"svImplicit":false,"modVarp":"(FB)","modPTypep":"UNLINKED", + {"type":"PIN","name":"clk","addr":"(EB)","loc":"d,27:14,27:17","svDotName":true,"modVarp":"(FB)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"clk","addr":"(GB)","loc":"d,27:42,27:45","dtypep":"(I)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"paramsp": [],"rangep": [],"intfRefsp": []} ]}, - {"type":"MODULE","name":"mod2","addr":"(X)","loc":"d,46:8,46:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mod2","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"mod2","addr":"(X)","loc":"d,46:8,46:12","origName":"mod2","verilogName":"mod2","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk","addr":"(FB)","loc":"d,48:10,48:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(Z)","loc":"d,49:16,49:17","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"q","addr":"(CB)","loc":"d,50:22,50:23","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(HB)","loc":"d,53:13,53:14","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"VAR","name":"clk","addr":"(FB)","loc":"d,48:10,48:13","dtypep":"(I)","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(Z)","loc":"d,49:16,49:17","dtypep":"(G)","origName":"d","verilogName":"d","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"q","addr":"(CB)","loc":"d,50:22,50:23","dtypep":"(G)","origName":"q","verilogName":"q","direction":"OUTPUT","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"ALWAYS","name":"","addr":"(HB)","loc":"d,53:13,53:14","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(IB)","loc":"d,53:13,53:14","dtypep":"(G)", "rhsp": [ @@ -53,22 +53,22 @@ ],"timingControlp": [],"strengthSpecp": []} ]} ]}, - {"type":"MODULE","name":"mod1__W4","addr":"(M)","loc":"d,31:8,31:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mod1","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"mod1__W4","addr":"(M)","loc":"d,31:8,31:12","origName":"mod1","verilogName":"mod1","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"WIDTH","addr":"(LB)","loc":"d,32:15,32:20","dtypep":"(MB)","origName":"WIDTH","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":true,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"WIDTH","addr":"(LB)","loc":"d,32:15,32:20","dtypep":"(MB)","origName":"WIDTH","verilogName":"WIDTH","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"GPARAM","dtypeName":"logic","isGParam":true,"isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh4","addr":"(NB)","loc":"d,19:18,19:19","dtypep":"(MB)"} ],"attrsp": []}, - {"type":"VAR","name":"clk","addr":"(R)","loc":"d,34:24,34:27","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(U)","loc":"d,35:30,35:31","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"q","addr":"(O)","loc":"d,36:30,36:31","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"IGNORED","addr":"(OB)","loc":"d,39:15,39:22","dtypep":"(MB)","origName":"IGNORED","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"clk","addr":"(R)","loc":"d,34:24,34:27","dtypep":"(I)","origName":"clk","verilogName":"clk","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"d","addr":"(U)","loc":"d,35:30,35:31","dtypep":"(G)","origName":"d","verilogName":"d","direction":"INPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"q","addr":"(O)","loc":"d,36:30,36:31","dtypep":"(G)","origName":"q","verilogName":"q","direction":"OUTPUT","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"IGNORED","addr":"(OB)","loc":"d,39:15,39:22","dtypep":"(MB)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh1","addr":"(PB)","loc":"d,39:25,39:26","dtypep":"(MB)"} ],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(QB)","loc":"d,41:4,41:10","keyword":"always","isSuspendable":false,"needProcess":false, + {"type":"ALWAYS","name":"","addr":"(QB)","loc":"d,41:4,41:10","keyword":"always", "sentreep": [ - {"type":"SENTREE","name":"","addr":"(RB)","loc":"d,41:11,41:12","isMulti":false, + {"type":"SENTREE","name":"","addr":"(RB)","loc":"d,41:11,41:12", "sensesp": [ {"type":"SENITEM","name":"","addr":"(SB)","loc":"d,41:13,41:20","edgeType":"POS", "sensp": [ @@ -93,11 +93,11 @@ {"type":"BASICDTYPE","name":"logic","addr":"(I)","loc":"d,34:24,34:27","dtypep":"(I)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,15:16,15:17","dtypep":"(G)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(MB)","loc":"d,19:18,19:19","dtypep":"(MB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"VOIDDTYPE","name":"","addr":"(XB)","loc":"a,0:0,0:0","dtypep":"(XB)","generic":false} + {"type":"VOIDDTYPE","name":"","addr":"(XB)","loc":"a,0:0,0:0","dtypep":"(XB)"} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(YB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(YB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(ZB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(YB)","varsp": [],"blocksp": [],"inlinesp": []} ]} diff --git a/test_regress/t/t_json_only_first.py b/test_regress/t/t_json_only_first.py index 5fa0ddc00..2c764bd51 100755 --- a/test_regress/t/t_json_only_first.py +++ b/test_regress/t/t_json_only_first.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_json_only_first.v b/test_regress/t/t_json_only_first.v index 7e594036d..634c08889 100644 --- a/test_regress/t/t_json_only_first.v +++ b/test_regress/t/t_json_only_first.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_json_only_flat.out b/test_regress/t/t_json_only_flat.out index 284efe8f4..2bf01765b 100644 --- a/test_regress/t/t_json_only_flat.out +++ b/test_regress/t/t_json_only_flat.out @@ -1,28 +1,28 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)","stlFirstIterationp":"UNLINKED", "modulesp": [ - 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{"type":"VAR","name":"clk","addr":"(I)","loc":"d,13:10,13:13","dtypep":"(J)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"d","addr":"(K)","loc":"d,14:16,14:17","dtypep":"(H)","origName":"d","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - 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{"type":"VAR","name":"t.d","addr":"(N)","loc":"d,14:16,14:17","dtypep":"(H)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.between","addr":"(O)","loc":"d,17:22,17:29","dtypep":"(H)","origName":"between","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - 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{"type":"VAR","name":"t.cell1.q","addr":"(U)","loc":"d,36:30,36:31","dtypep":"(H)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"t.cell1.IGNORED","addr":"(V)","loc":"d,39:15,39:22","dtypep":"(Q)","origName":"IGNORED","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], + {"type":"VAR","name":"t.cell1.clk","addr":"(S)","loc":"d,34:24,34:27","dtypep":"(J)","origName":"clk","verilogName":"clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.d","addr":"(T)","loc":"d,35:30,35:31","dtypep":"(H)","origName":"d","verilogName":"d","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.q","addr":"(U)","loc":"d,36:30,36:31","dtypep":"(H)","origName":"q","verilogName":"q","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"t.cell1.IGNORED","addr":"(V)","loc":"d,39:15,39:22","dtypep":"(Q)","origName":"IGNORED","verilogName":"IGNORED","direction":"NONE","isConst":true,"lifetime":"VSTATICI","varType":"LPARAM","dtypeName":"logic","isParam":true,"hasUserInit":true,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ {"type":"CONST","name":"32'sh1","addr":"(W)","loc":"d,39:25,39:26","dtypep":"(Q)"} ],"attrsp": []}, - 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{"type":"ALWAYS","name":"","addr":"(FB)","loc":"d,15:22,15:23","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(FB)","loc":"d,15:22,15:23","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(GB)","loc":"d,15:22,15:23","dtypep":"(H)", "rhsp": [ @@ -42,7 +42,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.clk","addr":"(JB)","loc":"d,13:10,13:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(M)"}, - {"type":"ALWAYS","name":"","addr":"(KB)","loc":"d,13:10,13:13","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(KB)","loc":"d,13:10,13:13","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(LB)","loc":"d,13:10,13:13","dtypep":"(J)", "rhsp": [ @@ -53,7 +53,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.d","addr":"(OB)","loc":"d,14:16,14:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(N)"}, - {"type":"ALWAYS","name":"","addr":"(PB)","loc":"d,14:16,14:17","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(PB)","loc":"d,14:16,14:17","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(QB)","loc":"d,14:16,14:17","dtypep":"(H)", "rhsp": [ @@ -66,7 +66,7 @@ {"type":"VARSCOPE","name":"t.between","addr":"(TB)","loc":"d,17:22,17:29","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(O)"}, {"type":"VARSCOPE","name":"t.cell1.WIDTH","addr":"(UB)","loc":"d,32:15,32:20","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(P)"}, {"type":"VARSCOPE","name":"t.cell1.clk","addr":"(VB)","loc":"d,34:24,34:27","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(S)"}, - {"type":"ALWAYS","name":"","addr":"(WB)","loc":"d,34:24,34:27","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(WB)","loc":"d,34:24,34:27","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(XB)","loc":"d,34:24,34:27","dtypep":"(J)", "rhsp": [ @@ -77,7 +77,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.cell1.d","addr":"(AC)","loc":"d,35:30,35:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(T)"}, - {"type":"ALWAYS","name":"","addr":"(BC)","loc":"d,35:30,35:31","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(BC)","loc":"d,35:30,35:31","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(CC)","loc":"d,35:30,35:31","dtypep":"(H)", "rhsp": [ @@ -88,7 +88,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.cell1.q","addr":"(FC)","loc":"d,36:30,36:31","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(U)"}, - {"type":"ALWAYS","name":"","addr":"(GC)","loc":"d,36:30,36:31","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(GC)","loc":"d,36:30,36:31","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(HC)","loc":"d,36:30,36:31","dtypep":"(H)", "rhsp": [ @@ -100,7 +100,7 @@ ]}, {"type":"VARSCOPE","name":"t.cell1.IGNORED","addr":"(KC)","loc":"d,39:15,39:22","dtypep":"(Q)","isTrace":true,"scopep":"(AB)","varp":"(V)"}, {"type":"VARSCOPE","name":"t.cell2.clk","addr":"(LC)","loc":"d,48:10,48:13","dtypep":"(J)","isTrace":true,"scopep":"(AB)","varp":"(X)"}, - {"type":"ALWAYS","name":"","addr":"(MC)","loc":"d,48:10,48:13","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(MC)","loc":"d,48:10,48:13","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(NC)","loc":"d,48:10,48:13","dtypep":"(J)", "rhsp": [ @@ -111,7 +111,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.cell2.d","addr":"(QC)","loc":"d,49:16,49:17","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Y)"}, - {"type":"ALWAYS","name":"","addr":"(RC)","loc":"d,49:16,49:17","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(RC)","loc":"d,49:16,49:17","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(SC)","loc":"d,49:16,49:17","dtypep":"(H)", "rhsp": [ @@ -122,7 +122,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"t.cell2.q","addr":"(VC)","loc":"d,50:22,50:23","dtypep":"(H)","isTrace":true,"scopep":"(AB)","varp":"(Z)"}, - {"type":"ALWAYS","name":"","addr":"(WC)","loc":"d,50:22,50:23","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(WC)","loc":"d,50:22,50:23","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(XC)","loc":"d,50:22,50:23","dtypep":"(H)", "rhsp": [ @@ -134,9 +134,9 @@ ]} ], "blocksp": [ - {"type":"ALWAYS","name":"","addr":"(AD)","loc":"d,41:4,41:10","keyword":"always","isSuspendable":false,"needProcess":false, + {"type":"ALWAYS","name":"","addr":"(AD)","loc":"d,41:4,41:10","keyword":"always", "sentreep": [ - {"type":"SENTREE","name":"","addr":"(BD)","loc":"d,41:11,41:12","isMulti":false, + {"type":"SENTREE","name":"","addr":"(BD)","loc":"d,41:11,41:12", "sensesp": [ {"type":"SENITEM","name":"","addr":"(CD)","loc":"d,41:13,41:20","edgeType":"POS", "sensp": [ @@ -153,7 +153,7 @@ {"type":"VARREF","name":"t.between","addr":"(GD)","loc":"d,42:6,42:7","dtypep":"(H)","access":"WR","varp":"(O)","varScopep":"(TB)","classOrPackagep":"UNLINKED"} ],"timingControlp": []} ]}, - {"type":"ALWAYS","name":"","addr":"(HD)","loc":"d,53:13,53:14","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(HD)","loc":"d,53:13,53:14","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(ID)","loc":"d,53:13,53:14","dtypep":"(H)", "rhsp": [ @@ -173,11 +173,11 @@ {"type":"BASICDTYPE","name":"logic","addr":"(J)","loc":"d,34:24,34:27","dtypep":"(J)","keyword":"logic","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(H)","loc":"d,15:16,15:17","dtypep":"(H)","keyword":"logic","range":"3:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(Q)","loc":"d,19:18,19:19","dtypep":"(Q)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"VOIDDTYPE","name":"","addr":"(LD)","loc":"a,0:0,0:0","dtypep":"(LD)","generic":false} + {"type":"VOIDDTYPE","name":"","addr":"(LD)","loc":"a,0:0,0:0","dtypep":"(LD)"} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(MD)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(MD)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(ND)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(MD)","varsp": [],"blocksp": [],"inlinesp": []} ]} diff --git a/test_regress/t/t_json_only_flat.py b/test_regress/t/t_json_only_flat.py index 0c8fa3240..a60a658b6 100755 --- a/test_regress/t/t_json_only_flat.py +++ b/test_regress/t/t_json_only_flat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.out b/test_regress/t/t_json_only_flat_no_inline_mod.out index 9d57129d5..19a74937a 100644 --- a/test_regress/t/t_json_only_flat_no_inline_mod.out +++ b/test_regress/t/t_json_only_flat_no_inline_mod.out @@ -1,17 +1,17 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","origName":"$root","verilogName":"$root","level":1,"modPublic":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,11:8,11:11","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(K)","loc":"d,11:8,11:11","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)", "varsp": [ {"type":"VARSCOPE","name":"i_clk","addr":"(L)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(G)"}, {"type":"VARSCOPE","name":"top.i_clk","addr":"(M)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(I)"}, - {"type":"ALWAYS","name":"","addr":"(N)","loc":"d,11:24,11:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(N)","loc":"d,11:24,11:29","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)", "rhsp": [ @@ -22,7 +22,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"top.f.i_clk","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"}, - {"type":"ALWAYS","name":"","addr":"(S)","loc":"d,7:24,7:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(S)","loc":"d,7:24,7:29","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)", "rhsp": [ @@ -43,7 +43,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(W)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(W)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(X)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(W)","varsp": [],"blocksp": [],"inlinesp": []} ]} diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.py b/test_regress/t/t_json_only_flat_no_inline_mod.py index 9903be780..d6779da1e 100755 --- a/test_regress/t/t_json_only_flat_no_inline_mod.py +++ b/test_regress/t/t_json_only_flat_no_inline_mod.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.v b/test_regress/t/t_json_only_flat_no_inline_mod.v index cf87b71a0..447a40afc 100644 --- a/test_regress/t/t_json_only_flat_no_inline_mod.v +++ b/test_regress/t/t_json_only_flat_no_inline_mod.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module foo(input logic i_clk); /* verilator no_inline_module */ diff --git a/test_regress/t/t_json_only_flat_pub_mod.out b/test_regress/t/t_json_only_flat_pub_mod.out index 9d57129d5..19a74937a 100644 --- a/test_regress/t/t_json_only_flat_pub_mod.out +++ b/test_regress/t/t_json_only_flat_pub_mod.out @@ -1,17 +1,17 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","origName":"$root","verilogName":"$root","level":1,"modPublic":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"top.f.i_clk","addr":"(J)","loc":"d,7:24,7:29","dtypep":"(H)","origName":"i_clk","verilogName":"i_clk","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,11:8,11:11","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(K)","loc":"d,11:8,11:11","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)", "varsp": [ {"type":"VARSCOPE","name":"i_clk","addr":"(L)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(G)"}, {"type":"VARSCOPE","name":"top.i_clk","addr":"(M)","loc":"d,11:24,11:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(I)"}, - {"type":"ALWAYS","name":"","addr":"(N)","loc":"d,11:24,11:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(N)","loc":"d,11:24,11:29","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(O)","loc":"d,11:24,11:29","dtypep":"(H)", "rhsp": [ @@ -22,7 +22,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"top.f.i_clk","addr":"(R)","loc":"d,7:24,7:29","dtypep":"(H)","isTrace":true,"scopep":"(K)","varp":"(J)"}, - {"type":"ALWAYS","name":"","addr":"(S)","loc":"d,7:24,7:29","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(S)","loc":"d,7:24,7:29","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(T)","loc":"d,7:24,7:29","dtypep":"(H)", "rhsp": [ @@ -43,7 +43,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(W)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(W)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(X)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(W)","varsp": [],"blocksp": [],"inlinesp": []} ]} diff --git a/test_regress/t/t_json_only_flat_pub_mod.py b/test_regress/t/t_json_only_flat_pub_mod.py index 9903be780..d6779da1e 100755 --- a/test_regress/t/t_json_only_flat_pub_mod.py +++ b/test_regress/t/t_json_only_flat_pub_mod.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_json_only_flat_pub_mod.v b/test_regress/t/t_json_only_flat_pub_mod.v index 4fa40e587..9c4f97759 100644 --- a/test_regress/t/t_json_only_flat_pub_mod.v +++ b/test_regress/t/t_json_only_flat_pub_mod.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module foo(input logic i_clk); /* verilator public_module */ diff --git a/test_regress/t/t_json_only_flat_vlvbound.out b/test_regress/t/t_json_only_flat_vlvbound.out index 1f7009569..e0c3a714a 100644 --- a/test_regress/t/t_json_only_flat_vlvbound.out +++ b/test_regress/t/t_json_only_flat_vlvbound.out @@ -1,15 +1,15 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:21","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:21","origName":"$root","verilogName":"$root","level":1,"modPublic":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"i_a","addr":"(G)","loc":"d,9:25,9:28","dtypep":"(H)","origName":"i_a","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"i_b","addr":"(I)","loc":"d,10:25,10:28","dtypep":"(H)","origName":"i_b","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"o_a","addr":"(J)","loc":"d,11:25,11:28","dtypep":"(K)","origName":"o_a","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"o_b","addr":"(L)","loc":"d,12:25,12:28","dtypep":"(K)","origName":"o_b","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"vlvbound_test.i_a","addr":"(M)","loc":"d,9:25,9:28","dtypep":"(H)","origName":"i_a","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"vlvbound_test.i_b","addr":"(N)","loc":"d,10:25,10:28","dtypep":"(H)","origName":"i_b","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"vlvbound_test.o_a","addr":"(O)","loc":"d,11:25,11:28","dtypep":"(K)","origName":"o_a","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"vlvbound_test.o_b","addr":"(P)","loc":"d,12:25,12:28","dtypep":"(K)","origName":"o_b","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"i_a","addr":"(G)","loc":"d,9:25,9:28","dtypep":"(H)","origName":"i_a","verilogName":"i_a","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"i_b","addr":"(I)","loc":"d,10:25,10:28","dtypep":"(H)","origName":"i_b","verilogName":"i_b","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"o_a","addr":"(J)","loc":"d,11:25,11:28","dtypep":"(K)","origName":"o_a","verilogName":"o_a","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"o_b","addr":"(L)","loc":"d,12:25,12:28","dtypep":"(K)","origName":"o_b","verilogName":"o_b","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"vlvbound_test.i_a","addr":"(M)","loc":"d,9:25,9:28","dtypep":"(H)","origName":"i_a","verilogName":"i_a","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"vlvbound_test.i_b","addr":"(N)","loc":"d,10:25,10:28","dtypep":"(H)","origName":"i_b","verilogName":"i_b","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"vlvbound_test.o_a","addr":"(O)","loc":"d,11:25,11:28","dtypep":"(K)","origName":"o_a","verilogName":"o_a","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"vlvbound_test.o_b","addr":"(P)","loc":"d,12:25,12:28","dtypep":"(K)","origName":"o_b","verilogName":"o_b","direction":"NONE","lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"TOPSCOPE","name":"","addr":"(E)","loc":"d,7:8,7:21","senTreesp": [], "scopep": [ {"type":"SCOPE","name":"TOP","addr":"(Q)","loc":"d,7:8,7:21","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(F)", @@ -19,7 +19,7 @@ {"type":"VARSCOPE","name":"o_a","addr":"(T)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(J)"}, {"type":"VARSCOPE","name":"o_b","addr":"(U)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(L)"}, {"type":"VARSCOPE","name":"vlvbound_test.i_a","addr":"(V)","loc":"d,9:25,9:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(M)"}, - {"type":"ALWAYS","name":"","addr":"(W)","loc":"d,9:25,9:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(W)","loc":"d,9:25,9:28","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(X)","loc":"d,9:25,9:28","dtypep":"(H)", "rhsp": [ @@ -30,7 +30,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"vlvbound_test.i_b","addr":"(AB)","loc":"d,10:25,10:28","dtypep":"(H)","isTrace":true,"scopep":"(Q)","varp":"(N)"}, - {"type":"ALWAYS","name":"","addr":"(BB)","loc":"d,10:25,10:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(BB)","loc":"d,10:25,10:28","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(CB)","loc":"d,10:25,10:28","dtypep":"(H)", "rhsp": [ @@ -41,7 +41,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"vlvbound_test.o_a","addr":"(FB)","loc":"d,11:25,11:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(O)"}, - {"type":"ALWAYS","name":"","addr":"(GB)","loc":"d,11:25,11:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(GB)","loc":"d,11:25,11:28","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(HB)","loc":"d,11:25,11:28","dtypep":"(K)", "rhsp": [ @@ -52,7 +52,7 @@ ],"timingControlp": [],"strengthSpecp": []} ]}, {"type":"VARSCOPE","name":"vlvbound_test.o_b","addr":"(KB)","loc":"d,12:25,12:28","dtypep":"(K)","isTrace":true,"scopep":"(Q)","varp":"(P)"}, - {"type":"ALWAYS","name":"","addr":"(LB)","loc":"d,12:25,12:28","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(LB)","loc":"d,12:25,12:28","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(MB)","loc":"d,12:25,12:28","dtypep":"(K)", "rhsp": [ @@ -72,7 +72,7 @@ {"type":"VARSCOPE","name":"__Vfunc_vlvbound_test.foo__1__i","addr":"(EC)","loc":"d,17:13,17:14","dtypep":"(WB)","isTrace":true,"scopep":"(Q)","varp":"(FC)"} ], "blocksp": [ - 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{"type":"BASICDTYPE","name":"logic","addr":"(PD)","loc":"d,19:10,19:11","dtypep":"(PD)","keyword":"logic","range":"2:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(LD)","loc":"d,19:11,19:12","dtypep":"(LD)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(GD)","loc":"d,19:20,19:21","dtypep":"(GD)","keyword":"logic","range":"3:0","generic":true,"signed":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(RC)","loc":"d,18:12,18:13","dtypep":"(RC)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, - {"type":"VOIDDTYPE","name":"","addr":"(UF)","loc":"a,0:0,0:0","dtypep":"(UF)","generic":false} + {"type":"BASICDTYPE","name":"logic","addr":"(UD)","loc":"d,19:10,19:11","dtypep":"(UD)","keyword":"logic","range":"2:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(QD)","loc":"d,19:11,19:12","dtypep":"(QD)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(LD)","loc":"d,19:20,19:21","dtypep":"(LD)","keyword":"logic","range":"3:0","generic":true,"signed":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(WC)","loc":"d,18:12,18:13","dtypep":"(WC)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, + {"type":"VOIDDTYPE","name":"","addr":"(EG)","loc":"a,0:0,0:0","dtypep":"(EG)"} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(VF)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(FG)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ - {"type":"SCOPE","name":"@CONST-POOL@","addr":"(WF)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(VF)","varsp": [],"blocksp": [],"inlinesp": []} + {"type":"SCOPE","name":"@CONST-POOL@","addr":"(GG)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(FG)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} diff --git a/test_regress/t/t_json_only_flat_vlvbound.py b/test_regress/t/t_json_only_flat_vlvbound.py index 9903be780..d6779da1e 100755 --- a/test_regress/t/t_json_only_flat_vlvbound.py +++ b/test_regress/t/t_json_only_flat_vlvbound.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_json_only_flat_vlvbound.v b/test_regress/t/t_json_only_flat_vlvbound.v index 9ed0db0cf..89fc2b29b 100644 --- a/test_regress/t/t_json_only_flat_vlvbound.v +++ b/test_regress/t/t_json_only_flat_vlvbound.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module vlvbound_test diff --git a/test_regress/t/t_json_only_output.out b/test_regress/t/t_json_only_output.out index a20d03af0..3433a85fb 100644 --- a/test_regress/t/t_json_only_output.out +++ b/test_regress/t/t_json_only_output.out @@ -1,8 +1,8 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"m","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","origName":"m","verilogName":"m","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:10,8:13","dtypep":"(G)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:10,8:13","dtypep":"(G)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]} ],"filesp": [], "miscsp": [ @@ -12,7 +12,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(H)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(H)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(I)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(H)","varsp": [],"blocksp": [],"inlinesp": []} ]} diff --git a/test_regress/t/t_json_only_output.py b/test_regress/t/t_json_only_output.py index 8f6c3b581..34ae1c875 100755 --- a/test_regress/t/t_json_only_output.py +++ b/test_regress/t/t_json_only_output.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_json_only_output.v b/test_regress/t/t_json_only_output.v index ccde3378d..d636ebb75 100644 --- a/test_regress/t/t_json_only_output.v +++ b/test_regress/t/t_json_only_output.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m diff --git a/test_regress/t/t_json_only_primary_io.out b/test_regress/t/t_json_only_primary_io.out index 7ea175a86..0533de594 100644 --- a/test_regress/t/t_json_only_primary_io.out +++ b/test_regress/t/t_json_only_primary_io.out @@ -1,28 +1,28 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"top","addr":"(E)","loc":"d,7:8,7:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"top","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"top","addr":"(E)","loc":"d,7:8,7:11","origName":"top","verilogName":"top","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk","addr":"(F)","loc":"d,13:9,13:12","dtypep":"(G)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"a1","addr":"(H)","loc":"d,14:9,14:11","dtypep":"(G)","origName":"a1","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"a2","addr":"(I)","loc":"d,15:9,15:11","dtypep":"(G)","origName":"a2","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"ready","addr":"(J)","loc":"d,16:10,16:15","dtypep":"(G)","origName":"ready","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"ready_reg","addr":"(K)","loc":"d,18:8,18:17","dtypep":"(G)","origName":"ready_reg","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"CELL","name":"and_cell","addr":"(L)","loc":"d,20:11,20:19","origName":"and_cell","recursive":false,"modp":"(M)", + {"type":"VAR","name":"clk","addr":"(F)","loc":"d,13:9,13:12","dtypep":"(G)","origName":"clk","verilogName":"clk","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a1","addr":"(H)","loc":"d,14:9,14:11","dtypep":"(G)","origName":"a1","verilogName":"a1","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a2","addr":"(I)","loc":"d,15:9,15:11","dtypep":"(G)","origName":"a2","verilogName":"a2","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"ready","addr":"(J)","loc":"d,16:10,16:15","dtypep":"(G)","origName":"ready","verilogName":"ready","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"ready_reg","addr":"(K)","loc":"d,18:8,18:17","dtypep":"(G)","origName":"ready_reg","verilogName":"ready_reg","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"CELL","name":"and_cell","addr":"(L)","loc":"d,20:11,20:19","origName":"and_cell","verilogName":"and_cell","modp":"(M)", "pinsp": [ - {"type":"PIN","name":"a1","addr":"(N)","loc":"d,21:8,21:10","svDotName":true,"svImplicit":false,"modVarp":"(O)","modPTypep":"UNLINKED", + {"type":"PIN","name":"a1","addr":"(N)","loc":"d,21:8,21:10","svDotName":true,"modVarp":"(O)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"a1","addr":"(P)","loc":"d,21:11,21:13","dtypep":"(G)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"a2","addr":"(Q)","loc":"d,22:8,22:10","svDotName":true,"svImplicit":false,"modVarp":"(R)","modPTypep":"UNLINKED", + {"type":"PIN","name":"a2","addr":"(Q)","loc":"d,22:8,22:10","svDotName":true,"modVarp":"(R)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"a2","addr":"(S)","loc":"d,22:11,22:13","dtypep":"(G)","access":"RD","varp":"(I)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]}, - {"type":"PIN","name":"zn","addr":"(T)","loc":"d,23:8,23:10","svDotName":true,"svImplicit":false,"modVarp":"(U)","modPTypep":"UNLINKED", + {"type":"PIN","name":"zn","addr":"(T)","loc":"d,23:8,23:10","svDotName":true,"modVarp":"(U)","modPTypep":"UNLINKED", "exprp": [ {"type":"VARREF","name":"ready_reg","addr":"(V)","loc":"d,23:11,23:20","dtypep":"(G)","access":"WR","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"ALWAYS","name":"","addr":"(W)","loc":"d,26:16,26:17","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"ALWAYS","name":"","addr":"(W)","loc":"d,26:16,26:17","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(X)","loc":"d,26:16,26:17","dtypep":"(G)", "rhsp": [ @@ -33,12 +33,12 @@ ],"timingControlp": [],"strengthSpecp": []} ]} ]}, - {"type":"MODULE","name":"and2_x1","addr":"(M)","loc":"d,29:8,29:15","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"and2_x1","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"and2_x1","addr":"(M)","loc":"d,29:8,29:15","origName":"and2_x1","verilogName":"and2_x1","level":2,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"a1","addr":"(O)","loc":"d,30:16,30:18","dtypep":"(G)","origName":"a1","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"a2","addr":"(R)","loc":"d,31:16,31:18","dtypep":"(G)","origName":"a2","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"zn","addr":"(U)","loc":"d,32:17,32:19","dtypep":"(G)","origName":"zn","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(AB)","loc":"d,34:13,34:14","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"VAR","name":"a1","addr":"(O)","loc":"d,30:16,30:18","dtypep":"(G)","origName":"a1","verilogName":"a1","direction":"INPUT","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"a2","addr":"(R)","loc":"d,31:16,31:18","dtypep":"(G)","origName":"a2","verilogName":"a2","direction":"INPUT","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"zn","addr":"(U)","loc":"d,32:17,32:19","dtypep":"(G)","origName":"zn","verilogName":"zn","direction":"OUTPUT","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"ALWAYS","name":"","addr":"(AB)","loc":"d,34:13,34:14","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(BB)","loc":"d,34:13,34:14","dtypep":"(G)", "rhsp": [ @@ -60,11 +60,11 @@ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(GB)", "typesp": [ {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,30:16,30:18","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}, - {"type":"VOIDDTYPE","name":"","addr":"(GB)","loc":"a,0:0,0:0","dtypep":"(GB)","generic":false} + {"type":"VOIDDTYPE","name":"","addr":"(GB)","loc":"a,0:0,0:0","dtypep":"(GB)"} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(HB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(HB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(IB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(HB)","varsp": [],"blocksp": [],"inlinesp": []} ]} diff --git a/test_regress/t/t_json_only_primary_io.py b/test_regress/t/t_json_only_primary_io.py index b2fa66aeb..245a9011f 100755 --- a/test_regress/t/t_json_only_primary_io.py +++ b/test_regress/t/t_json_only_primary_io.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_json_only_primary_io.v b/test_regress/t/t_json_only_primary_io.v index 578897780..c9ab406c2 100644 --- a/test_regress/t/t_json_only_primary_io.v +++ b/test_regress/t/t_json_only_primary_io.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module top ( diff --git a/test_regress/t/t_json_only_tag.out b/test_regress/t/t_json_only_tag.out index 8a8395be3..16f5bba1f 100644 --- a/test_regress/t/t_json_only_tag.out +++ b/test_regress/t/t_json_only_tag.out @@ -1,28 +1,28 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"m","addr":"(E)","loc":"d,12:8,12:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"m","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"m","addr":"(E)","loc":"d,12:8,12:9","origName":"m","verilogName":"m","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"clk_ip","addr":"(F)","loc":"d,14:11,14:17","dtypep":"(G)","origName":"clk_ip","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"rst_ip","addr":"(H)","loc":"d,15:11,15:17","dtypep":"(G)","origName":"rst_ip","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"foo_op","addr":"(I)","loc":"d,16:11,16:17","dtypep":"(G)","origName":"foo_op","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"TYPEDEF","name":"my_struct","addr":"(J)","loc":"d,25:6,25:15","dtypep":"(K)","attrPublic":false,"isUnderClass":false,"childDTypep": [],"attrsp": []}, - {"type":"CELL","name":"itop","addr":"(L)","loc":"d,29:8,29:12","origName":"itop","recursive":false,"modp":"(M)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, - {"type":"VAR","name":"itop","addr":"(N)","loc":"d,29:8,29:12","dtypep":"(O)","origName":"itop__Viftop","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"IFACEREF","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"this_struct","addr":"(P)","loc":"d,31:14,31:25","dtypep":"(Q)","origName":"this_struct","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"dotted","addr":"(R)","loc":"d,33:16,33:22","dtypep":"(S)","origName":"dotted","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"ALWAYS","name":"","addr":"(T)","loc":"d,33:23,33:24","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [], + {"type":"VAR","name":"clk_ip","addr":"(F)","loc":"d,14:11,14:17","dtypep":"(G)","origName":"clk_ip","verilogName":"clk_ip","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"rst_ip","addr":"(H)","loc":"d,15:11,15:17","dtypep":"(G)","origName":"rst_ip","verilogName":"rst_ip","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"foo_op","addr":"(I)","loc":"d,16:11,16:17","dtypep":"(G)","origName":"foo_op","verilogName":"foo_op","isPrimaryIO":true,"direction":"OUTPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"TYPEDEF","name":"my_struct","addr":"(J)","loc":"d,25:6,25:15","dtypep":"(K)","childDTypep": [],"attrsp": []}, + {"type":"CELL","name":"itop","addr":"(L)","loc":"d,29:8,29:12","origName":"itop","verilogName":"itop","modp":"(M)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, + {"type":"VAR","name":"itop","addr":"(N)","loc":"d,29:8,29:12","dtypep":"(O)","origName":"itop__Viftop","verilogName":"itop__Viftop","direction":"NONE","lifetime":"VSTATICI","varType":"IFACEREF","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"this_struct","addr":"(P)","loc":"d,31:14,31:25","dtypep":"(Q)","origName":"this_struct","verilogName":"this_struct","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"dotted","addr":"(R)","loc":"d,33:16,33:22","dtypep":"(S)","origName":"dotted","verilogName":"dotted","direction":"NONE","lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"ALWAYS","name":"","addr":"(T)","loc":"d,33:23,33:24","keyword":"cont_assign","sentreep": [], "stmtsp": [ {"type":"ASSIGNW","name":"","addr":"(U)","loc":"d,33:23,33:24","dtypep":"(S)", "rhsp": [ - {"type":"VARXREF","name":"value","addr":"(V)","loc":"d,33:30,33:35","dtypep":"(W)","containsGenBlock":false,"dotted":"itop","inlinedDots":"","access":"RD","varp":"(X)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARXREF","name":"value","addr":"(V)","loc":"d,33:30,33:35","dtypep":"(W)","dotted":"itop","inlinedDots":"","access":"RD","varp":"(X)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "lhsp": [ {"type":"VARREF","name":"dotted","addr":"(Y)","loc":"d,33:16,33:22","dtypep":"(S)","access":"WR","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ]}, - {"type":"TASK","name":"f","addr":"(Z)","loc":"d,35:18,35:19","method":false,"dpiExport":false,"dpiImport":false,"dpiOpenChild":false,"dpiOpenParent":false,"isExternDef":false,"isExternProto":false,"prototype":false,"recursive":false,"taskPublic":false,"cname":"f","fvarp": [],"classOrPackagep": [], + {"type":"TASK","name":"f","addr":"(Z)","loc":"d,35:18,35:19","cname":"f","fvarp": [],"classOrPackagep": [], "stmtsp": [ - {"type":"VAR","name":"m","addr":"(AB)","loc":"d,35:33,35:34","dtypep":"(BB)","origName":"m","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":true,"isStdRandomizeArg":false,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"m","addr":"(AB)","loc":"d,35:33,35:34","dtypep":"(BB)","origName":"m","verilogName":"m","direction":"INPUT","isFuncLocal":true,"lifetime":"VAUTOMI","varType":"PORT","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"DISPLAY","name":"","addr":"(CB)","loc":"d,36:7,36:15", "fmtp": [ {"type":"SFORMATF","name":"%@","addr":"(DB)","loc":"d,36:7,36:15","dtypep":"(BB)", @@ -31,26 +31,26 @@ ],"scopeNamep": []} ],"filep": []} ],"scopeNamep": []}, - {"type":"INITIAL","name":"","addr":"(FB)","loc":"d,39:4,39:11","isSuspendable":false,"needProcess":false, + {"type":"INITIAL","name":"","addr":"(FB)","loc":"d,39:4,39:11", "stmtsp": [ - {"type":"BEGIN","name":"","addr":"(GB)","loc":"d,39:12,39:17","implied":false,"needProcess":false,"unnamed":true,"declsp": [], + {"type":"BEGIN","name":"","addr":"(GB)","loc":"d,39:12,39:17","unnamed":true,"declsp": [], "stmtsp": [ {"type":"STMTEXPR","name":"","addr":"(HB)","loc":"d,41:7,41:8", "exprp": [ - {"type":"TASKREF","name":"f","addr":"(IB)","loc":"d,41:7,41:8","dtypep":"(JB)","dotted":"","taskp":"(Z)","classOrPackagep":"UNLINKED","namep": [], - "pinsp": [ + {"type":"TASKREF","name":"f","addr":"(IB)","loc":"d,41:7,41:8","dtypep":"(JB)","dotted":"","taskp":"(Z)","classOrPackagep":"UNLINKED", + "argsp": [ {"type":"ARG","name":"","addr":"(KB)","loc":"d,41:9,41:736", "exprp": [ {"type":"CONST","name":"\\\"\\001\\002\\003\\004\\005\\006\\007\\010\\t\\n\\013\\014\\r\\016\\017\\020\\021\\022\\023\\024\\025\\026\\027\\030\\031\\032\\033\\034\\035\\036\\037 !\\\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\\177\\200\\201\\202\\203\\204\\205\\206\\207\\210\\211\\212\\213\\214\\215\\216\\217\\220\\221\\222\\223\\224\\225\\226\\227\\230\\231\\232\\233\\234\\235\\236\\237\\240\\241\\242\\243\\244\\245\\246\\247\\250\\251\\252\\253\\254\\255\\256\\257\\260\\261\\262\\263\\264\\265\\266\\267\\270\\271\\272\\273\\274\\275\\276\\277\\300\\301\\302\\303\\304\\305\\306\\307\\310\\311\\312\\313\\314\\315\\316\\317\\320\\321\\322\\323\\324\\325\\326\\327\\330\\331\\332\\333\\334\\335\\336\\337\\340\\341\\342\\343\\344\\345\\346\\347\\350\\351\\352\\353\\354\\355\\356\\357\\360\\361\\362\\363\\364\\365\\366\\367\\370\\371\\372\\373\\374\\375\\376\\377\\\"","addr":"(LB)","loc":"d,41:9,41:736","dtypep":"(BB)"} ]} - ],"scopeNamep": []} + ],"withp": [],"scopeNamep": []} ]} ]} ]} ]}, - {"type":"IFACE","name":"ifc","addr":"(M)","loc":"d,7:11,7:14","origName":"ifc","level":2,"modPublic":false,"inLibrary":true,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"IFACE","name":"ifc","addr":"(M)","loc":"d,7:11,7:14","origName":"ifc","verilogName":"ifc","level":2,"inLibrary":true,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"value","addr":"(X)","loc":"d,8:12,8:17","dtypep":"(W)","origName":"value","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"value","addr":"(X)","loc":"d,8:12,8:17","dtypep":"(W)","origName":"value","verilogName":"value","direction":"NONE","lifetime":"VSTATICI","varType":"VAR","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"MODPORT","name":"out_modport","addr":"(MB)","loc":"d,9:12,9:23", "varsp": [ {"type":"MODPORTVARREF","name":"value","addr":"(NB)","loc":"d,9:32,9:37","direction":"OUTPUT","varp":"(X)","exprp": []} @@ -60,24 +60,24 @@ "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(JB)", "typesp": [ - {"type":"VOIDDTYPE","name":"","addr":"(JB)","loc":"d,41:7,41:8","dtypep":"(JB)","generic":false}, + {"type":"VOIDDTYPE","name":"","addr":"(JB)","loc":"d,41:7,41:8","dtypep":"(JB)"}, {"type":"BASICDTYPE","name":"integer","addr":"(W)","loc":"d,8:4,8:11","dtypep":"(W)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,14:11,14:17","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,21:7,21:12","dtypep":"(OB)","keyword":"logic","generic":false,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(PB)","loc":"d,22:7,22:12","dtypep":"(PB)","keyword":"logic","generic":false,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(QB)","loc":"d,23:7,23:12","dtypep":"(QB)","keyword":"logic","generic":false,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,24:7,24:12","dtypep":"(RB)","keyword":"logic","generic":false,"rangep": []}, - {"type":"STRUCTDTYPE","name":"m.my_struct","addr":"(K)","loc":"d,20:12,20:18","dtypep":"(K)","packed":true,"isFourstate":true,"generic":false,"classOrPackagep":"UNLINKED", + {"type":"BASICDTYPE","name":"logic","addr":"(OB)","loc":"d,21:7,21:12","dtypep":"(OB)","keyword":"logic","rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(PB)","loc":"d,22:7,22:12","dtypep":"(PB)","keyword":"logic","rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(QB)","loc":"d,23:7,23:12","dtypep":"(QB)","keyword":"logic","rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,24:7,24:12","dtypep":"(RB)","keyword":"logic","rangep": []}, + {"type":"STRUCTDTYPE","name":"m.my_struct","addr":"(K)","loc":"d,20:12,20:18","dtypep":"(K)","packed":true,"isFourstate":true,"classOrPackagep":"UNLINKED", "membersp": [ - {"type":"MEMBERDTYPE","name":"clk","addr":"(SB)","loc":"d,21:19,21:22","dtypep":"(OB)","isConstrainedRand":false,"name":"clk","tag":"this is clk","generic":false,"refDTypep":"(OB)","childDTypep": [],"valuep": []}, - {"type":"MEMBERDTYPE","name":"k","addr":"(TB)","loc":"d,22:19,22:20","dtypep":"(PB)","isConstrainedRand":false,"name":"k","tag":"","generic":false,"refDTypep":"(PB)","childDTypep": [],"valuep": []}, - {"type":"MEMBERDTYPE","name":"enable","addr":"(UB)","loc":"d,23:19,23:25","dtypep":"(QB)","isConstrainedRand":false,"name":"enable","tag":"enable","generic":false,"refDTypep":"(QB)","childDTypep": [],"valuep": []}, - {"type":"MEMBERDTYPE","name":"data","addr":"(VB)","loc":"d,24:19,24:23","dtypep":"(RB)","isConstrainedRand":false,"name":"data","tag":"data","generic":false,"refDTypep":"(RB)","childDTypep": [],"valuep": []} + {"type":"MEMBERDTYPE","name":"clk","addr":"(SB)","loc":"d,21:19,21:22","dtypep":"(OB)","name":"clk","tag":"this is clk","refDTypep":"(OB)","childDTypep": [],"valuep": []}, + {"type":"MEMBERDTYPE","name":"k","addr":"(TB)","loc":"d,22:19,22:20","dtypep":"(PB)","name":"k","tag":"","refDTypep":"(PB)","childDTypep": [],"valuep": []}, + {"type":"MEMBERDTYPE","name":"enable","addr":"(UB)","loc":"d,23:19,23:25","dtypep":"(QB)","name":"enable","tag":"enable","refDTypep":"(QB)","childDTypep": [],"valuep": []}, + {"type":"MEMBERDTYPE","name":"data","addr":"(VB)","loc":"d,24:19,24:23","dtypep":"(RB)","name":"data","tag":"data","refDTypep":"(RB)","childDTypep": [],"valuep": []} ]}, - {"type":"IFACEREFDTYPE","name":"","addr":"(O)","loc":"d,29:8,29:12","dtypep":"(O)","isPortDecl":false,"isVirtual":false,"cellName":"itop","ifaceName":"ifc","modportName":"","generic":false,"ifacep":"UNLINKED","cellp":"(L)","modportp":"UNLINKED","paramsp": []}, + {"type":"IFACEREFDTYPE","name":"","addr":"(O)","loc":"d,29:8,29:12","dtypep":"(O)","cellName":"itop","ifaceName":"ifc","modportName":"","ifacep":"UNLINKED","cellp":"(L)","modportp":"UNLINKED","paramsp": []}, {"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"d,31:27,31:28","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"REFDTYPE","name":"my_struct","addr":"(WB)","loc":"d,31:4,31:13","dtypep":"(K)","generic":false,"typedefp":"UNLINKED","refDTypep":"(K)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Q)","loc":"d,31:26,31:27","dtypep":"(Q)","isCompound":false,"declRange":"[0:1]","generic":false,"refDTypep":"(WB)","childDTypep": [], + {"type":"REFDTYPE","name":"my_struct","addr":"(WB)","loc":"d,31:4,31:13","dtypep":"(K)","typedefp":"UNLINKED","refDTypep":"(K)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(Q)","loc":"d,31:26,31:27","dtypep":"(Q)","declRange":"[0:1]","refDTypep":"(WB)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(XB)","loc":"d,31:26,31:27","ascending":true,"fromBracket":true, "leftp": [ @@ -91,7 +91,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(BC)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(AC)","varsp": [],"blocksp": [],"inlinesp": []} ]} diff --git a/test_regress/t/t_json_only_tag.py b/test_regress/t/t_json_only_tag.py index 5fa0ddc00..2c764bd51 100755 --- a/test_regress/t/t_json_only_tag.py +++ b/test_regress/t/t_json_only_tag.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_json_only_tag.v b/test_regress/t/t_json_only_tag.v index a47cd18d7..9bfd517d6 100644 --- a/test_regress/t/t_json_only_tag.v +++ b/test_regress/t/t_json_only_tag.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Chris Randall. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Chris Randall // SPDX-License-Identifier: CC0-1.0 interface ifc; diff --git a/test_regress/t/t_jumps_uninit_destructor_call.py b/test_regress/t/t_jumps_uninit_destructor_call.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_jumps_uninit_destructor_call.py +++ b/test_regress/t/t_jumps_uninit_destructor_call.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_jumps_uninit_destructor_call.v b/test_regress/t/t_jumps_uninit_destructor_call.v index 9354f989e..ddcdce134 100644 --- a/test_regress/t/t_jumps_uninit_destructor_call.v +++ b/test_regress/t/t_jumps_uninit_destructor_call.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; string arra[2]; diff --git a/test_regress/t/t_langext_1.py b/test_regress/t/t_langext_1.py index e87ec43cc..f24fb336a 100755 --- a/test_regress/t/t_langext_1.py +++ b/test_regress/t/t_langext_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_1.v b/test_regress/t/t_langext_1.v index dfbef20de..c2d68eff0 100644 --- a/test_regress/t/t_langext_1.v +++ b/test_regress/t/t_langext_1.v @@ -8,8 +8,8 @@ // // Compile only test, so no need for "All Finished" output. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_langext_1_bad.py b/test_regress/t/t_langext_1_bad.py index 4882e6577..9fda6098f 100755 --- a/test_regress/t/t_langext_1_bad.py +++ b/test_regress/t/t_langext_1_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_1d.py b/test_regress/t/t_langext_1d.py index 6b8d4bc93..3ba6d1701 100755 --- a/test_regress/t/t_langext_1d.py +++ b/test_regress/t/t_langext_1d.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_1d_bad.py b/test_regress/t/t_langext_1d_bad.py index 3eee193cc..f0aff9bf7 100755 --- a/test_regress/t/t_langext_1d_bad.py +++ b/test_regress/t/t_langext_1d_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_2.py b/test_regress/t/t_langext_2.py index 76841dd5e..24a67d2a8 100755 --- a/test_regress/t/t_langext_2.py +++ b/test_regress/t/t_langext_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_2.v b/test_regress/t/t_langext_2.v index 30aa8b428..7d2e895c4 100644 --- a/test_regress/t/t_langext_2.v +++ b/test_regress/t/t_langext_2.v @@ -8,8 +8,8 @@ // // Compile only test, so no need for "All Finished" output. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_langext_2012ext.py b/test_regress/t/t_langext_2012ext.py index bdc9b832b..6e3f4f41f 100755 --- a/test_regress/t/t_langext_2012ext.py +++ b/test_regress/t/t_langext_2012ext.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_2017ext.py b/test_regress/t/t_langext_2017ext.py index 0c7fffebf..e7e5ebc1e 100755 --- a/test_regress/t/t_langext_2017ext.py +++ b/test_regress/t/t_langext_2017ext.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_2023ext.py b/test_regress/t/t_langext_2023ext.py index 2fb9f6909..c11e3ca37 100755 --- a/test_regress/t/t_langext_2023ext.py +++ b/test_regress/t/t_langext_2023ext.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_2_bad.py b/test_regress/t/t_langext_2_bad.py index 7722ecdf5..b5bbc8428 100755 --- a/test_regress/t/t_langext_2_bad.py +++ b/test_regress/t/t_langext_2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_3.py b/test_regress/t/t_langext_3.py index d2e142d8b..f3a83706b 100755 --- a/test_regress/t/t_langext_3.py +++ b/test_regress/t/t_langext_3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_3.v b/test_regress/t/t_langext_3.v index 8efa0085d..60488ea3d 100644 --- a/test_regress/t/t_langext_3.v +++ b/test_regress/t/t_langext_3.v @@ -7,8 +7,8 @@ // // Compile only test, so no need for "All Finished" output. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_langext_3_bad.py b/test_regress/t/t_langext_3_bad.py index 179695a06..104a9c279 100755 --- a/test_regress/t/t_langext_3_bad.py +++ b/test_regress/t/t_langext_3_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_4.py b/test_regress/t/t_langext_4.py index 829a07706..5b1ea1068 100755 --- a/test_regress/t/t_langext_4.py +++ b/test_regress/t/t_langext_4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_4_bad.py b/test_regress/t/t_langext_4_bad.py index 0ea1b6771..d73eb6d98 100755 --- a/test_regress/t/t_langext_4_bad.py +++ b/test_regress/t/t_langext_4_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_order.py b/test_regress/t/t_langext_order.py index d2e142d8b..f3a83706b 100755 --- a/test_regress/t/t_langext_order.py +++ b/test_regress/t/t_langext_order.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_langext_order.v b/test_regress/t/t_langext_order.v index a40880794..083bc67c3 100644 --- a/test_regress/t/t_langext_order.v +++ b/test_regress/t/t_langext_order.v @@ -2,8 +2,8 @@ // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD diff --git a/test_regress/t/t_langext_order_sub.v b/test_regress/t/t_langext_order_sub.v index 3c6d48b5b..bf4ee6df4 100644 --- a/test_regress/t/t_langext_order_sub.v +++ b/test_regress/t/t_langext_order_sub.v @@ -2,8 +2,8 @@ // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD diff --git a/test_regress/t/t_leak.cpp b/test_regress/t/t_leak.cpp index 1d52d27f5..203214f47 100644 --- a/test_regress/t/t_leak.cpp +++ b/test_regress/t/t_leak.cpp @@ -2,10 +2,10 @@ // // DESCRIPTION: Verilator: Verilog Test driver/expect definition // -// Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #include diff --git a/test_regress/t/t_leak.py b/test_regress/t/t_leak.py index cd84c8163..8f3b6df05 100755 --- a/test_regress/t/t_leak.py +++ b/test_regress/t/t_leak.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_leak.v b/test_regress/t/t_leak.v index cca64710b..624801ae7 100644 --- a/test_regress/t/t_leak.v +++ b/test_regress/t/t_leak.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_let.py b/test_regress/t/t_let.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_let.py +++ b/test_regress/t/t_let.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_let.v b/test_regress/t/t_let.v index 9406912ba..3bc4b49b2 100644 --- a/test_regress/t/t_let.v +++ b/test_regress/t/t_let.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg; diff --git a/test_regress/t/t_let_arg_bad.py b/test_regress/t/t_let_arg_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_let_arg_bad.py +++ b/test_regress/t/t_let_arg_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_let_arg_bad.v b/test_regress/t/t_let_arg_bad.v index 5a21b803a..801d29cd2 100644 --- a/test_regress/t/t_let_arg_bad.v +++ b/test_regress/t/t_let_arg_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_let_recurse_bad.py b/test_regress/t/t_let_recurse_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_let_recurse_bad.py +++ b/test_regress/t/t_let_recurse_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_let_recurse_bad.v b/test_regress/t/t_let_recurse_bad.v index d1bd712e6..1114cc110 100644 --- a/test_regress/t/t_let_recurse_bad.v +++ b/test_regress/t/t_let_recurse_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_let_stmt_bad.py b/test_regress/t/t_let_stmt_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_let_stmt_bad.py +++ b/test_regress/t/t_let_stmt_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_let_stmt_bad.v b/test_regress/t/t_let_stmt_bad.v index ca0e67010..0bb6c8751 100644 --- a/test_regress/t/t_let_stmt_bad.v +++ b/test_regress/t/t_let_stmt_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_let_unsup.py b/test_regress/t/t_let_unsup.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_let_unsup.py +++ b/test_regress/t/t_let_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_let_unsup.v b/test_regress/t/t_let_unsup.v index c4e1f0d27..69ccd680b 100644 --- a/test_regress/t/t_let_unsup.v +++ b/test_regress/t/t_let_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lib.py b/test_regress/t/t_lib.py index ddd055e11..05ad77f62 100755 --- a/test_regress/t/t_lib.py +++ b/test_regress/t/t_lib.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_clk_vec.py b/test_regress/t/t_lib_clk_vec.py index 24eea89ec..45b37b72d 100755 --- a/test_regress/t/t_lib_clk_vec.py +++ b/test_regress/t/t_lib_clk_vec.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_clk_vec.v b/test_regress/t/t_lib_clk_vec.v index 5309766af..eacd68dd0 100644 --- a/test_regress/t/t_lib_clk_vec.v +++ b/test_regress/t/t_lib_clk_vec.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // The number of clocks in the clock vector @@ -55,7 +55,7 @@ module top; // Conclude when all counters reach 10 begin - static bit done = 1'b1; + automatic bit done = 1'b1; for (int i = 0; i < N; ++i) begin if (cnt[i] != 10) done = 1'b0; end diff --git a/test_regress/t/t_lib_nolib.py b/test_regress/t/t_lib_nolib.py index 3c4e861ab..e0d740a76 100755 --- a/test_regress/t/t_lib_nolib.py +++ b/test_regress/t/t_lib_nolib.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_prof_exec.py b/test_regress/t/t_lib_prof_exec.py index fd3f5a86c..8ac00b186 100755 --- a/test_regress/t/t_lib_prof_exec.py +++ b/test_regress/t/t_lib_prof_exec.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_prot.py b/test_regress/t/t_lib_prot.py index fdec419c3..127bab7ec 100755 --- a/test_regress/t/t_lib_prot.py +++ b/test_regress/t/t_lib_prot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_prot.v b/test_regress/t/t_lib_prot.v index cdc4c009c..25c1d7894 100644 --- a/test_regress/t/t_lib_prot.v +++ b/test_regress/t/t_lib_prot.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Todd Strader // SPDX-License-Identifier: CC0-1.0 `define DRIVE(sig) \ diff --git a/test_regress/t/t_lib_prot_clk_gated.py b/test_regress/t/t_lib_prot_clk_gated.py index c7e7c897f..0abc2bf38 100755 --- a/test_regress/t/t_lib_prot_clk_gated.py +++ b/test_regress/t/t_lib_prot_clk_gated.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_prot_comb.py b/test_regress/t/t_lib_prot_comb.py index 4a314fcbd..30391c0f9 100755 --- a/test_regress/t/t_lib_prot_comb.py +++ b/test_regress/t/t_lib_prot_comb.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_prot_comb.v b/test_regress/t/t_lib_prot_comb.v index b4716efa0..31f6fdf6b 100644 --- a/test_regress/t/t_lib_prot_comb.v +++ b/test_regress/t/t_lib_prot_comb.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Yutetsu TAKATSUKASA. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 `ifdef PROCESS_TOP diff --git a/test_regress/t/t_lib_prot_delay_bad.py b/test_regress/t/t_lib_prot_delay_bad.py index edbc0bdc5..16a0842b4 100755 --- a/test_regress/t/t_lib_prot_delay_bad.py +++ b/test_regress/t/t_lib_prot_delay_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_prot_delay_bad.v b/test_regress/t/t_lib_prot_delay_bad.v index 832e60f2e..090249c20 100644 --- a/test_regress/t/t_lib_prot_delay_bad.v +++ b/test_regress/t/t_lib_prot_delay_bad.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Todd Strader // SPDX-License-Identifier: CC0-1.0 module secret_impl; diff --git a/test_regress/t/t_lib_prot_exe_bad.py b/test_regress/t/t_lib_prot_exe_bad.py index 236b2a27a..c51bdabb6 100755 --- a/test_regress/t/t_lib_prot_exe_bad.py +++ b/test_regress/t/t_lib_prot_exe_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_prot_inout_bad.py b/test_regress/t/t_lib_prot_inout_bad.py index 4ca020c38..d05b26b02 100755 --- a/test_regress/t/t_lib_prot_inout_bad.py +++ b/test_regress/t/t_lib_prot_inout_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_prot_inout_bad.v b/test_regress/t/t_lib_prot_inout_bad.v index 5fbd371f0..bf946a116 100644 --- a/test_regress/t/t_lib_prot_inout_bad.v +++ b/test_regress/t/t_lib_prot_inout_bad.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Todd Strader // SPDX-License-Identifier: CC0-1.0 module secret_impl ( diff --git a/test_regress/t/t_lib_prot_secret.py b/test_regress/t/t_lib_prot_secret.py index d0e834c5a..1dbf65877 100755 --- a/test_regress/t/t_lib_prot_secret.py +++ b/test_regress/t/t_lib_prot_secret.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lib_prot_secret.v b/test_regress/t/t_lib_prot_secret.v index 4009edb78..5e1be331a 100644 --- a/test_regress/t/t_lib_prot_secret.v +++ b/test_regress/t/t_lib_prot_secret.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Todd Strader // SPDX-License-Identifier: CC0-1.0 module secret #(parameter GATED_CLK = 0) diff --git a/test_regress/t/t_lib_prot_shared.py b/test_regress/t/t_lib_prot_shared.py index 17f750203..8705dc539 100755 --- a/test_regress/t/t_lib_prot_shared.py +++ b/test_regress/t/t_lib_prot_shared.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_always_comb_automatic.py b/test_regress/t/t_lint_always_comb_automatic.py index cca4c9e73..d6d35e7fd 100755 --- a/test_regress/t/t_lint_always_comb_automatic.py +++ b/test_regress/t/t_lint_always_comb_automatic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_always_comb_automatic.v b/test_regress/t/t_lint_always_comb_automatic.v index 7b0c4af70..916427415 100644 --- a/test_regress/t/t_lint_always_comb_automatic.v +++ b/test_regress/t/t_lint_always_comb_automatic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_always_comb_bad.py b/test_regress/t/t_lint_always_comb_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_always_comb_bad.py +++ b/test_regress/t/t_lint_always_comb_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_always_comb_bad.v b/test_regress/t/t_lint_always_comb_bad.v index 1cb2cf2d1..f89b5da51 100644 --- a/test_regress/t/t_lint_always_comb_bad.v +++ b/test_regress/t/t_lint_always_comb_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_always_comb_iface.py b/test_regress/t/t_lint_always_comb_iface.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_lint_always_comb_iface.py +++ b/test_regress/t/t_lint_always_comb_iface.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_always_comb_iface.v b/test_regress/t/t_lint_always_comb_iface.v index a51bc354f..56c06940d 100644 --- a/test_regress/t/t_lint_always_comb_iface.v +++ b/test_regress/t/t_lint_always_comb_iface.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Josh Redford. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 interface my_if; diff --git a/test_regress/t/t_lint_always_comb_multidriven_bad.py b/test_regress/t/t_lint_always_comb_multidriven_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_always_comb_multidriven_bad.py +++ b/test_regress/t/t_lint_always_comb_multidriven_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_always_comb_multidriven_bad.v b/test_regress/t/t_lint_always_comb_multidriven_bad.v index a243bbd59..f8d0e4879 100644 --- a/test_regress/t/t_lint_always_comb_multidriven_bad.v +++ b/test_regress/t/t_lint_always_comb_multidriven_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.out b/test_regress/t/t_lint_always_comb_multidriven_public_bad.out similarity index 100% rename from test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.out rename to test_regress/t/t_lint_always_comb_multidriven_public_bad.out diff --git a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.py b/test_regress/t/t_lint_always_comb_multidriven_public_bad.py similarity index 60% rename from test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.py rename to test_regress/t/t_lint_always_comb_multidriven_public_bad.py index 951c00f44..bba2bd225 100755 --- a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.py +++ b/test_regress/t/t_lint_always_comb_multidriven_public_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_assigneqexpr.py b/test_regress/t/t_lint_assigneqexpr.py index 3844c944c..d24e41475 100755 --- a/test_regress/t/t_lint_assigneqexpr.py +++ b/test_regress/t/t_lint_assigneqexpr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_assigneqexpr.v b/test_regress/t/t_lint_assigneqexpr.v index da3fa3f33..59420699e 100644 --- a/test_regress/t/t_lint_assigneqexpr.v +++ b/test_regress/t/t_lint_assigneqexpr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_assigneqexpr_bad.py b/test_regress/t/t_lint_assigneqexpr_bad.py index f6a8acb6f..7f3535d78 100755 --- a/test_regress/t/t_lint_assigneqexpr_bad.py +++ b/test_regress/t/t_lint_assigneqexpr_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_badvltpragma_bad.py b/test_regress/t/t_lint_badvltpragma_bad.py index 144609fba..cedbfdfcd 100755 --- a/test_regress/t/t_lint_badvltpragma_bad.py +++ b/test_regress/t/t_lint_badvltpragma_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_badvltpragma_bad.v b/test_regress/t/t_lint_badvltpragma_bad.v index 11181c92c..8e9e63305 100644 --- a/test_regress/t/t_lint_badvltpragma_bad.v +++ b/test_regress/t/t_lint_badvltpragma_bad.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_blkseq_bad.py b/test_regress/t/t_lint_blkseq_bad.py index 4adc6df42..71d1e489b 100755 --- a/test_regress/t/t_lint_blkseq_bad.py +++ b/test_regress/t/t_lint_blkseq_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_blkseq_bad.v b/test_regress/t/t_lint_blkseq_bad.v index 380176e1a..e67004882 100644 --- a/test_regress/t/t_lint_blkseq_bad.v +++ b/test_regress/t/t_lint_blkseq_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_blkseq_loop.py b/test_regress/t/t_lint_blkseq_loop.py index ebbf08d1f..c8f5704cf 100755 --- a/test_regress/t/t_lint_blkseq_loop.py +++ b/test_regress/t/t_lint_blkseq_loop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_blkseq_loop.v b/test_regress/t/t_lint_blkseq_loop.v index 1d112dfb0..57e90af27 100644 --- a/test_regress/t/t_lint_blkseq_loop.v +++ b/test_regress/t/t_lint_blkseq_loop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_blkseq_noedge.py b/test_regress/t/t_lint_blkseq_noedge.py index bd8bc88e5..e66c9b81f 100755 --- a/test_regress/t/t_lint_blkseq_noedge.py +++ b/test_regress/t/t_lint_blkseq_noedge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_blkseq_noedge.v b/test_regress/t/t_lint_blkseq_noedge.v index 53ac820aa..87c9199d4 100644 --- a/test_regress/t/t_lint_blkseq_noedge.v +++ b/test_regress/t/t_lint_blkseq_noedge.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_block_redecl_bad.py b/test_regress/t/t_lint_block_redecl_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_block_redecl_bad.py +++ b/test_regress/t/t_lint_block_redecl_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_block_redecl_bad.v b/test_regress/t/t_lint_block_redecl_bad.v index 11e5df1f6..f31ab48d8 100644 --- a/test_regress/t/t_lint_block_redecl_bad.v +++ b/test_regress/t/t_lint_block_redecl_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug485, but see t_gen_forif.v for an OK example. diff --git a/test_regress/t/t_lint_bsspace_bad.py b/test_regress/t/t_lint_bsspace_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_bsspace_bad.py +++ b/test_regress/t/t_lint_bsspace_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_bsspace_bad.v b/test_regress/t/t_lint_bsspace_bad.v index 5ff67f178..ef8a5945a 100644 --- a/test_regress/t/t_lint_bsspace_bad.v +++ b/test_regress/t/t_lint_bsspace_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Fake binary character here '', so is treated as binary and diff --git a/test_regress/t/t_lint_caseincomplete_bad.py b/test_regress/t/t_lint_caseincomplete_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_caseincomplete_bad.py +++ b/test_regress/t/t_lint_caseincomplete_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_caseincomplete_bad.v b/test_regress/t/t_lint_caseincomplete_bad.v index c2b25973f..9ff262bc6 100644 --- a/test_regress/t/t_lint_caseincomplete_bad.v +++ b/test_regress/t/t_lint_caseincomplete_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_cmpconst_bad.py b/test_regress/t/t_lint_cmpconst_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_cmpconst_bad.py +++ b/test_regress/t/t_lint_cmpconst_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_cmpconst_bad.v b/test_regress/t/t_lint_cmpconst_bad.v index 6ee64837f..34d6cdc00 100644 --- a/test_regress/t/t_lint_cmpconst_bad.v +++ b/test_regress/t/t_lint_cmpconst_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_colonplus_bad.py b/test_regress/t/t_lint_colonplus_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_colonplus_bad.py +++ b/test_regress/t/t_lint_colonplus_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_colonplus_bad.v b/test_regress/t/t_lint_colonplus_bad.v index 85dba1403..49b2af74b 100644 --- a/test_regress/t/t_lint_colonplus_bad.v +++ b/test_regress/t/t_lint_colonplus_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_comb_bad.py b/test_regress/t/t_lint_comb_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_comb_bad.py +++ b/test_regress/t/t_lint_comb_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_comb_bad.v b/test_regress/t/t_lint_comb_bad.v index 53abf5f14..5e6cfb34b 100644 --- a/test_regress/t/t_lint_comb_bad.v +++ b/test_regress/t/t_lint_comb_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_comb_use.py b/test_regress/t/t_lint_comb_use.py index ca24d5b16..53bc310a0 100755 --- a/test_regress/t/t_lint_comb_use.py +++ b/test_regress/t/t_lint_comb_use.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_comb_use.v b/test_regress/t/t_lint_comb_use.v index e2d274c3c..def83e983 100644 --- a/test_regress/t/t_lint_comb_use.v +++ b/test_regress/t/t_lint_comb_use.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_const_func_dpi_bad.py b/test_regress/t/t_lint_const_func_dpi_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_const_func_dpi_bad.py +++ b/test_regress/t/t_lint_const_func_dpi_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_const_func_dpi_bad.v b/test_regress/t/t_lint_const_func_dpi_bad.v index 84632841b..6647afd4b 100644 --- a/test_regress/t/t_lint_const_func_dpi_bad.v +++ b/test_regress/t/t_lint_const_func_dpi_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Donald Owen. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Donald Owen // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_const_func_gen_bad.py b/test_regress/t/t_lint_const_func_gen_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_const_func_gen_bad.py +++ b/test_regress/t/t_lint_const_func_gen_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_const_func_gen_bad.v b/test_regress/t/t_lint_const_func_gen_bad.v index 1dda64d9c..95dd6abe0 100644 --- a/test_regress/t/t_lint_const_func_gen_bad.v +++ b/test_regress/t/t_lint_const_func_gen_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Donald Owen. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Donald Owen // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_contassreg_bad.py b/test_regress/t/t_lint_contassreg_bad.py index 129a49d56..ef8868fcc 100755 --- a/test_regress/t/t_lint_contassreg_bad.py +++ b/test_regress/t/t_lint_contassreg_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_contassreg_bad.v b/test_regress/t/t_lint_contassreg_bad.v index 585c37c0d..b102e8243 100644 --- a/test_regress/t/t_lint_contassreg_bad.v +++ b/test_regress/t/t_lint_contassreg_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_lint_declfilename.py b/test_regress/t/t_lint_declfilename.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_declfilename.py +++ b/test_regress/t/t_lint_declfilename.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_declfilename.v b/test_regress/t/t_lint_declfilename.v index b3922ab7e..fe1b63720 100644 --- a/test_regress/t/t_lint_declfilename.v +++ b/test_regress/t/t_lint_declfilename.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_declfilename_bad.py b/test_regress/t/t_lint_declfilename_bad.py index 96e0bed25..bc2e4253e 100755 --- a/test_regress/t/t_lint_declfilename_bad.py +++ b/test_regress/t/t_lint_declfilename_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_declfilename_bbox.py b/test_regress/t/t_lint_declfilename_bbox.py index e037f35c6..5d30b0472 100755 --- a/test_regress/t/t_lint_declfilename_bbox.py +++ b/test_regress/t/t_lint_declfilename_bbox.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_declfilename_bbox.v b/test_regress/t/t_lint_declfilename_bbox.v index 5809d71df..76799025f 100644 --- a/test_regress/t/t_lint_declfilename_bbox.v +++ b/test_regress/t/t_lint_declfilename_bbox.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_lint_declfilename_bbox (); diff --git a/test_regress/t/t_lint_defparam.py b/test_regress/t/t_lint_defparam.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_defparam.py +++ b/test_regress/t/t_lint_defparam.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_defparam.v b/test_regress/t/t_lint_defparam.v index a2b70f76e..fc32e74a7 100644 --- a/test_regress/t/t_lint_defparam.v +++ b/test_regress/t/t_lint_defparam.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_defparam_bad.py b/test_regress/t/t_lint_defparam_bad.py index c25ef765a..4b4fe7c23 100755 --- a/test_regress/t/t_lint_defparam_bad.py +++ b/test_regress/t/t_lint_defparam_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_didnotconverge_bad.out b/test_regress/t/t_lint_didnotconverge_bad.out index 5133d97c7..9f57e12a5 100644 --- a/test_regress/t/t_lint_didnotconverge_bad.out +++ b/test_regress/t/t_lint_didnotconverge_bad.out @@ -1,3 +1,3 @@ -V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] a) -%Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries +%Error-DIDNOTCONVERGE: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after '--converge-limit' of 100 tries Aborting... diff --git a/test_regress/t/t_lint_didnotconverge_bad.py b/test_regress/t/t_lint_didnotconverge_bad.py index 0d6c4e194..a14f87817 100755 --- a/test_regress/t/t_lint_didnotconverge_bad.py +++ b/test_regress/t/t_lint_didnotconverge_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_didnotconverge_bad.v b/test_regress/t/t_lint_didnotconverge_bad.v index 3c3d87801..dec11311e 100644 --- a/test_regress/t/t_lint_didnotconverge_bad.v +++ b/test_regress/t/t_lint_didnotconverge_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_lint_didnotconverge_nodbg_bad.out b/test_regress/t/t_lint_didnotconverge_nodbg_bad.out index 3eb3339bd..24eded329 100644 --- a/test_regress/t/t_lint_didnotconverge_nodbg_bad.out +++ b/test_regress/t/t_lint_didnotconverge_nodbg_bad.out @@ -1,2 +1,2 @@ -%Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after 100 tries +%Error-DIDNOTCONVERGE: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge after '--converge-limit' of 100 tries Aborting... diff --git a/test_regress/t/t_lint_didnotconverge_nodbg_bad.py b/test_regress/t/t_lint_didnotconverge_nodbg_bad.py index abd364a14..f66e7a981 100755 --- a/test_regress/t/t_lint_didnotconverge_nodbg_bad.py +++ b/test_regress/t/t_lint_didnotconverge_nodbg_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_dtype_compare.py b/test_regress/t/t_lint_dtype_compare.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_lint_dtype_compare.py +++ b/test_regress/t/t_lint_dtype_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_dtype_compare.v b/test_regress/t/t_lint_dtype_compare.v index 0962af834..ea54c8705 100644 --- a/test_regress/t/t_lint_dtype_compare.v +++ b/test_regress/t/t_lint_dtype_compare.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; @@ -14,42 +14,42 @@ module t; initial begin // Scalar - int a = 1, b = 1; + automatic int a = 1, b = 1; // Unpacked array - int u1[2] = '{1, 2}; - int u2[2] = '{1, 2}; + automatic int u1[2] = '{1, 2}; + automatic int u2[2] = '{1, 2}; - int m1[2][2] = '{{1, 2}, {3, 4}}; - int m2[2][2] = '{{1, 2}, {3, 4}}; + automatic int m1[2][2] = '{{1, 2}, {3, 4}}; + automatic int m2[2][2] = '{{1, 2}, {3, 4}}; // Dynamic array - int d1[] = new[2]; - int d2[] = new[2]; + automatic int d1[] = new[2]; + automatic int d2[] = new[2]; // Queue - int q1[$] = '{10, 20}; - int q2[$] = '{10, 20}; + automatic int q1[$] = '{10, 20}; + automatic int q2[$] = '{10, 20}; // Associative array - int aa1[string]; - int aa2[string]; + automatic int aa1[string]; + automatic int aa2[string]; // Typedef array - myint_t t1[2] = '{1, 2}; - myint2_t t2[2] = '{1, 2}; + automatic myint_t t1[2] = '{1, 2}; + automatic myint2_t t2[2] = '{1, 2}; // Typedef queue - myq_t tq1 = '{1, 2}; - int tq2[$] = '{1, 2}; + automatic myq_t tq1 = '{1, 2}; + automatic int tq2[$] = '{1, 2}; // Typedef associative array - myval_t aa_typedef1[mykey_t]; - int aa_typedef2[string]; + automatic myval_t aa_typedef1[mykey_t]; + automatic int aa_typedef2[string]; // Typedef scalar - bit signed [31:0] b1 = 1; - int i1 = 1; + automatic bit signed [31:0] b1 = 1; + automatic int i1 = 1; d1[0] = 5; d1[1] = 6; d2[0] = 5; d2[1] = 6; diff --git a/test_regress/t/t_lint_dtype_compare_bad.py b/test_regress/t/t_lint_dtype_compare_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_lint_dtype_compare_bad.py +++ b/test_regress/t/t_lint_dtype_compare_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_dtype_compare_bad.v b/test_regress/t/t_lint_dtype_compare_bad.v index 3079ba052..13be87d02 100644 --- a/test_regress/t/t_lint_dtype_compare_bad.v +++ b/test_regress/t/t_lint_dtype_compare_bad.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // DESCRIPTION: Verilator: Invalid aggregate dtype comparisons // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Shou-Li Hsu. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Shou-Li Hsu // SPDX-License-Identifier: CC0-1.0 module t; @@ -18,33 +18,33 @@ module t; typedef logic [31:0] mylogic_t; initial begin - int queue_var[$] = '{1, 2, 3}; - int q1[$] = '{1, 2}; - bit q2[$] = '{1'b1, 1'b0}; + automatic int queue_var[$] = '{1, 2, 3}; + automatic int q1[$] = '{1, 2}; + automatic bit q2[$] = '{1'b1, 1'b0}; - int d1[] = new[2]; - bit d2[] = new[2]; + automatic int d1[] = new[2]; + automatic bit d2[] = new[2]; - int u1[2] = '{1, 2}; - int u2[2][1] = '{{1}, {2}}; + automatic int u1[2] = '{1, 2}; + automatic int u2[2][1] = '{{1}, {2}}; - int a1[2] = '{1, 2}; - int a2[3] = '{1, 2, 3}; + automatic int a1[2] = '{1, 2}; + automatic int a2[3] = '{1, 2, 3}; - int aa1[string]; - int aa2[int]; + automatic int aa1[string]; + automatic int aa2[int]; - int aa3[string]; - logic [3:0] aa4[string]; + automatic int aa3[string]; + automatic logic [3:0] aa4[string]; - myint_t bad1[2] = '{1, 2}; - mybit_t bad2[2] = '{1, 0}; + automatic myint_t bad1[2] = '{1, 2}; + automatic mybit_t bad2[2] = '{1, 0}; - myval_t val1[mystr_t] = '{"foo": 123}; - mylogic_t val2[string] = '{"foo": 32'h12345678}; + automatic myval_t val1[mystr_t] = '{"foo": 123}; + automatic mylogic_t val2[string] = '{"foo": 32'h12345678}; - myint_t aa5[string]; - myint_t aa6[int]; + automatic myint_t aa5[string]; + automatic myint_t aa6[int]; aa5["a"] = 1; aa6[1] = 1; diff --git a/test_regress/t/t_lint_edge_real_bad.py b/test_regress/t/t_lint_edge_real_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_edge_real_bad.py +++ b/test_regress/t/t_lint_edge_real_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_edge_real_bad.v b/test_regress/t/t_lint_edge_real_bad.v index 4db3ae293..83d4ad16b 100644 --- a/test_regress/t/t_lint_edge_real_bad.v +++ b/test_regress/t/t_lint_edge_real_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_eofnewline.py b/test_regress/t/t_lint_eofnewline.py index 64dde988b..cc2766a36 100755 --- a/test_regress/t/t_lint_eofnewline.py +++ b/test_regress/t/t_lint_eofnewline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_eofnewline_bad.py b/test_regress/t/t_lint_eofnewline_bad.py index 86acef286..51fb0c244 100755 --- a/test_regress/t/t_lint_eofnewline_bad.py +++ b/test_regress/t/t_lint_eofnewline_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_eofnewline_vlt.py b/test_regress/t/t_lint_eofnewline_vlt.py index 852be2ccd..507fe38a1 100755 --- a/test_regress/t/t_lint_eofnewline_vlt.py +++ b/test_regress/t/t_lint_eofnewline_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_eofnewline_vlt.vlt b/test_regress/t/t_lint_eofnewline_vlt.vlt index 016032dea..80aa002e6 100644 --- a/test_regress/t/t_lint_eofnewline_vlt.vlt +++ b/test_regress/t/t_lint_eofnewline_vlt.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_lint_ftask_output_assign_bad.py b/test_regress/t/t_lint_ftask_output_assign_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_ftask_output_assign_bad.py +++ b/test_regress/t/t_lint_ftask_output_assign_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_ftask_output_assign_bad.v b/test_regress/t/t_lint_ftask_output_assign_bad.v index ac8b0c7aa..1799de830 100644 --- a/test_regress/t/t_lint_ftask_output_assign_bad.v +++ b/test_regress/t/t_lint_ftask_output_assign_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_functimectl_bad.py b/test_regress/t/t_lint_functimectl_bad.py index 7c467d6b1..d213ff0d9 100755 --- a/test_regress/t/t_lint_functimectl_bad.py +++ b/test_regress/t/t_lint_functimectl_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_functimectl_bad.v b/test_regress/t/t_lint_functimectl_bad.v index 90bbeb1e9..072da37f0 100644 --- a/test_regress/t/t_lint_functimectl_bad.v +++ b/test_regress/t/t_lint_functimectl_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_genunnamed_bad.py b/test_regress/t/t_lint_genunnamed_bad.py index 946e0710c..83517505a 100755 --- a/test_regress/t/t_lint_genunnamed_bad.py +++ b/test_regress/t/t_lint_genunnamed_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_genunnamed_bad.v b/test_regress/t/t_lint_genunnamed_bad.v index ad7d7da85..c39ac02e5 100644 --- a/test_regress/t/t_lint_genunnamed_bad.v +++ b/test_regress/t/t_lint_genunnamed_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_historical.py b/test_regress/t/t_lint_historical.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_historical.py +++ b/test_regress/t/t_lint_historical.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_historical.v b/test_regress/t/t_lint_historical.v index d261102db..573c429cf 100644 --- a/test_regress/t/t_lint_historical.v +++ b/test_regress/t/t_lint_historical.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; @@ -56,6 +56,7 @@ module t; // verilator lint_off INFINITELOOP // verilator lint_off INITIALDLY // verilator lint_off INSECURE + // verilator lint_off INSIDETRUE // verilator lint_off LATCH // verilator lint_off LITENDIAN // verilator lint_off MINTYPMAXDLY @@ -103,6 +104,7 @@ module t; // verilator lint_off UNOPTFLAT // verilator lint_off UNOPTTHREADS // verilator lint_off UNPACKED + // verilator lint_off UNSATCONSTR // verilator lint_off UNSIGNED // verilator lint_off UNUSED // verilator lint_off UNUSEDGENVAR diff --git a/test_regress/t/t_lint_iface_array_topmodule1.py b/test_regress/t/t_lint_iface_array_topmodule1.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_lint_iface_array_topmodule1.py +++ b/test_regress/t/t_lint_iface_array_topmodule1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_iface_array_topmodule1.v b/test_regress/t/t_lint_iface_array_topmodule1.v index de19c13a2..5e55cd37c 100644 --- a/test_regress/t/t_lint_iface_array_topmodule1.v +++ b/test_regress/t/t_lint_iface_array_topmodule1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Josh Redford. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 interface my_if; diff --git a/test_regress/t/t_lint_iface_array_topmodule2.py b/test_regress/t/t_lint_iface_array_topmodule2.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_lint_iface_array_topmodule2.py +++ b/test_regress/t/t_lint_iface_array_topmodule2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_iface_array_topmodule2.v b/test_regress/t/t_lint_iface_array_topmodule2.v index 078fb4495..7507ddbcd 100644 --- a/test_regress/t/t_lint_iface_array_topmodule2.v +++ b/test_regress/t/t_lint_iface_array_topmodule2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Josh Redford. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 interface my_if #( diff --git a/test_regress/t/t_lint_iface_array_topmodule3.py b/test_regress/t/t_lint_iface_array_topmodule3.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_lint_iface_array_topmodule3.py +++ b/test_regress/t/t_lint_iface_array_topmodule3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_iface_array_topmodule3.v b/test_regress/t/t_lint_iface_array_topmodule3.v index 50dae10f2..dcaea4940 100644 --- a/test_regress/t/t_lint_iface_array_topmodule3.v +++ b/test_regress/t/t_lint_iface_array_topmodule3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Josh Redford. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 interface my_if #( parameter integer DW = 8 ) (input clk); diff --git a/test_regress/t/t_lint_iface_array_topmodule_bad.py b/test_regress/t/t_lint_iface_array_topmodule_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_iface_array_topmodule_bad.py +++ b/test_regress/t/t_lint_iface_array_topmodule_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_iface_array_topmodule_bad.v b/test_regress/t/t_lint_iface_array_topmodule_bad.v index 55b060591..398c9ef6e 100644 --- a/test_regress/t/t_lint_iface_array_topmodule_bad.v +++ b/test_regress/t/t_lint_iface_array_topmodule_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Josh Redford. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 interface my_if #( diff --git a/test_regress/t/t_lint_iface_topmodule1.py b/test_regress/t/t_lint_iface_topmodule1.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_lint_iface_topmodule1.py +++ b/test_regress/t/t_lint_iface_topmodule1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_iface_topmodule1.v b/test_regress/t/t_lint_iface_topmodule1.v index 4c4fa5b1f..0fce52ec9 100644 --- a/test_regress/t/t_lint_iface_topmodule1.v +++ b/test_regress/t/t_lint_iface_topmodule1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Josh Redford. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 interface my_if; diff --git a/test_regress/t/t_lint_iface_topmodule2.py b/test_regress/t/t_lint_iface_topmodule2.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_lint_iface_topmodule2.py +++ b/test_regress/t/t_lint_iface_topmodule2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_iface_topmodule2.v b/test_regress/t/t_lint_iface_topmodule2.v index ec836205a..e06c6f30f 100644 --- a/test_regress/t/t_lint_iface_topmodule2.v +++ b/test_regress/t/t_lint_iface_topmodule2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Josh Redford. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 interface my_if #( diff --git a/test_regress/t/t_lint_iface_topmodule3.py b/test_regress/t/t_lint_iface_topmodule3.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_lint_iface_topmodule3.py +++ b/test_regress/t/t_lint_iface_topmodule3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_iface_topmodule3.v b/test_regress/t/t_lint_iface_topmodule3.v index a6084207b..712fdce13 100644 --- a/test_regress/t/t_lint_iface_topmodule3.v +++ b/test_regress/t/t_lint_iface_topmodule3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Josh Redford. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 interface my_if #( parameter integer DW = 8 ) (input clk); diff --git a/test_regress/t/t_lint_iface_topmodule_bad.py b/test_regress/t/t_lint_iface_topmodule_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_iface_topmodule_bad.py +++ b/test_regress/t/t_lint_iface_topmodule_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_iface_topmodule_bad.v b/test_regress/t/t_lint_iface_topmodule_bad.v index 04e51f7c3..41cf70dac 100644 --- a/test_regress/t/t_lint_iface_topmodule_bad.v +++ b/test_regress/t/t_lint_iface_topmodule_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Josh Redford. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Josh Redford // SPDX-License-Identifier: CC0-1.0 interface my_if #( diff --git a/test_regress/t/t_lint_ifdepth_bad.py b/test_regress/t/t_lint_ifdepth_bad.py index 036372ce1..de5d894a5 100755 --- a/test_regress/t/t_lint_ifdepth_bad.py +++ b/test_regress/t/t_lint_ifdepth_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_ifdepth_bad.v b/test_regress/t/t_lint_ifdepth_bad.v index 84873848f..9eb6ac4a8 100644 --- a/test_regress/t/t_lint_ifdepth_bad.v +++ b/test_regress/t/t_lint_ifdepth_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_implicit.py b/test_regress/t/t_lint_implicit.py index 837cc7107..b4c5575c7 100755 --- a/test_regress/t/t_lint_implicit.py +++ b/test_regress/t/t_lint_implicit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_implicit.v b/test_regress/t/t_lint_implicit.v index 58961b897..34d04a194 100644 --- a/test_regress/t/t_lint_implicit.v +++ b/test_regress/t/t_lint_implicit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (a,z); diff --git a/test_regress/t/t_lint_implicit_bad.py b/test_regress/t/t_lint_implicit_bad.py index fcdd3f4e7..33d06f6b5 100755 --- a/test_regress/t/t_lint_implicit_bad.py +++ b/test_regress/t/t_lint_implicit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_implicit_def_bad.py b/test_regress/t/t_lint_implicit_def_bad.py index 0db29c160..d323cd7c4 100755 --- a/test_regress/t/t_lint_implicit_def_bad.py +++ b/test_regress/t/t_lint_implicit_def_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_implicit_def_bad.v b/test_regress/t/t_lint_implicit_def_bad.v index 0cb1bcc55..34f8563ad 100644 --- a/test_regress/t/t_lint_implicit_def_bad.v +++ b/test_regress/t/t_lint_implicit_def_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (a,z); diff --git a/test_regress/t/t_lint_implicit_func_bad.py b/test_regress/t/t_lint_implicit_func_bad.py index 0db29c160..d323cd7c4 100755 --- a/test_regress/t/t_lint_implicit_func_bad.py +++ b/test_regress/t/t_lint_implicit_func_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_implicit_func_bad.v b/test_regress/t/t_lint_implicit_func_bad.v index 2d3dbe2fb..0e79e153c 100644 --- a/test_regress/t/t_lint_implicit_func_bad.v +++ b/test_regress/t/t_lint_implicit_func_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_implicit_port.py b/test_regress/t/t_lint_implicit_port.py index 837cc7107..b4c5575c7 100755 --- a/test_regress/t/t_lint_implicit_port.py +++ b/test_regress/t/t_lint_implicit_port.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_implicit_port.v b/test_regress/t/t_lint_implicit_port.v index a55ddbc50..c57b8c5b2 100644 --- a/test_regress/t/t_lint_implicit_port.v +++ b/test_regress/t/t_lint_implicit_port.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_implicit_type_bad.py b/test_regress/t/t_lint_implicit_type_bad.py index 383be3ece..3f3f0f925 100755 --- a/test_regress/t/t_lint_implicit_type_bad.py +++ b/test_regress/t/t_lint_implicit_type_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_implicit_type_bad.v b/test_regress/t/t_lint_implicit_type_bad.v index 3262dd6d4..4a878b3ae 100644 --- a/test_regress/t/t_lint_implicit_type_bad.v +++ b/test_regress/t/t_lint_implicit_type_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class imp_Cls_conflict; diff --git a/test_regress/t/t_lint_implicitstatic_bad.out b/test_regress/t/t_lint_implicitstatic_bad.out index 2af9e2775..0b3de4362 100644 --- a/test_regress/t/t_lint_implicitstatic_bad.out +++ b/test_regress/t/t_lint_implicitstatic_bad.out @@ -1,31 +1,29 @@ -%Warning-IMPLICITSTATIC: t/t_lint_implicitstatic_bad.v:16:9: Variable's lifetime implicitly set to static +%Warning-IMPLICITSTATIC: t/t_lint_implicitstatic_bad.v:20:9: Variable's lifetime implicitly set to static (IEEE 1800-2023 6.21) : ... The initializer value will only be set once : ... Suggest use 'static' before variable declaration' - 16 | int implicit_warn = 1; + 20 | int implicit_warn = 1; | ^~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/IMPLICITSTATIC?v=latest ... Use "/* verilator lint_off IMPLICITSTATIC */" and lint_on around source to disable this message. -%Warning-IMPLICITSTATIC: t/t_lint_implicitstatic_bad.v:20:16: Function/task's lifetime implicitly set to static - : ... Suggest use 'function automatic' or 'function static' - 20 | function int f_implicit_static(); - | ^~~~~~~~~~~~~~~~~ - t/t_lint_implicitstatic_bad.v:21:9: ... Location of implicit static variable - : ... The initializer value will only be set once - 21 | int cnt = 0; - | ^~~ -%Warning-IMPLICITSTATIC: t/t_lint_implicitstatic_bad.v:25:8: Function/task's lifetime implicitly set to static +%Warning-IMPLICITSTATIC: t/t_lint_implicitstatic_bad.v:24:8: Function/task's lifetime implicitly set to static; variables made static (IEEE 1800-2023 6.21) : ... Suggest use 'task automatic' or 'task static' - 25 | task f_implicit_static(); + 24 | task t_implicit_static(); | ^~~~~~~~~~~~~~~~~ - t/t_lint_implicitstatic_bad.v:26:9: ... Location of implicit static variable + t/t_lint_implicitstatic_bad.v:25:9: ... Location of implicit static variable : ... The initializer value will only be set once - 26 | int cnt = 0; - | ^~~ -%Error: t/t_lint_implicitstatic_bad.v:25:8: Unsupported in C: Task has the same name as function: 'f_implicit_static' - 25 | task f_implicit_static(); - | ^~~~~~~~~~~~~~~~~ - t/t_lint_implicitstatic_bad.v:20:16: ... Location of original declaration - 20 | function int f_implicit_static(); + 25 | int t_no_has_init = 1; + | ^~~~~~~~~~~~~ +%Warning-IMPLICITSTATIC: t/t_lint_implicitstatic_bad.v:32:16: Function/task's lifetime implicitly set to static; variables made static (IEEE 1800-2023 6.21) + : ... Suggest use 'function automatic' or 'function static' + 32 | function int f_implicit_static(); | ^~~~~~~~~~~~~~~~~ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. + t/t_lint_implicitstatic_bad.v:33:9: ... Location of implicit static variable + : ... The initializer value will only be set once + 33 | int f_no_has_init = 1; + | ^~~~~~~~~~~~~ +%Warning-IMPLICITSTATIC: t/t_lint_implicitstatic_bad.v:42:9: Variable's lifetime implicitly set to static (IEEE 1800-2023 6.21) + : ... The initializer value will only be set once + : ... Suggest use 'static' before variable declaration' + 42 | int i_no_has_init = 1; + | ^~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicitstatic_bad.py b/test_regress/t/t_lint_implicitstatic_bad.py index 966dc53da..71ef8b6c0 100755 --- a/test_regress/t/t_lint_implicitstatic_bad.py +++ b/test_regress/t/t_lint_implicitstatic_bad.py @@ -1,19 +1,16 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('vlt') -test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) - -if not test.vlt_all: - test.execute() +test.compile(fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_lint_implicitstatic_bad.v b/test_regress/t/t_lint_implicitstatic_bad.v index c766749f7..6b3fc9d11 100644 --- a/test_regress/t/t_lint_implicitstatic_bad.v +++ b/test_regress/t/t_lint_implicitstatic_bad.v @@ -1,39 +1,48 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( input clk ); - initial begin - int static_ok = 1; // Obvious as is in initial - end + class C; + task t; + int c_no_has_init = 1; // Ok + automatic int c_automatic_has_init = 1; // Ok + static int c_static_has_init = 1; // Ok + endtask + endclass always @(posedge clk) begin int implicit_warn = 1; // <--- Warning: IMPLICITSTATIC - localparam int NO_WARN = 2; // No warning here + localparam int OK = 2; // Ok end - function int f_implicit_static(); - int cnt = 0; // <--- Warning: IMPLICIT STATIC - return ++cnt; - endfunction - - task f_implicit_static(); - int cnt = 0; // <--- Warning: IMPLICIT STATIC - ++cnt; + task t_implicit_static(); + int t_no_has_init = 1; // <--- Warning: IMPLICIT STATIC + automatic int t_automatic_has_init = 1; // Ok + static int t_static_has_init = 1; // Ok + localparam int ONE = 1; // Ok + ++t_no_has_init; endtask - function int f_no_implicit_static(); - localparam int ONE = 1; // No warning here + function int f_implicit_static(); + int f_no_has_init = 1; // <--- Warning: IMPLICIT STATIC + automatic int f_automatic_has_init = 1; // Ok + static int f_static_has_init = 1; // Ok + localparam int ONE = 1; // Ok + ++f_no_has_init; return ONE; endfunction - task t_no_implicit_static(); - localparam TWO = 2; // No warning here - endtask + initial begin + int i_no_has_init = 1; // <--- Warning: IMPLICIT STATIC + automatic int i_automatic_has_init = 1; // Ok + static int i_static_has_init = 1; // Ok + $finish; + end endmodule diff --git a/test_regress/t/t_lint_import_name2_bad.py b/test_regress/t/t_lint_import_name2_bad.py index 0db29c160..d323cd7c4 100755 --- a/test_regress/t/t_lint_import_name2_bad.py +++ b/test_regress/t/t_lint_import_name2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_import_name2_bad.v b/test_regress/t/t_lint_import_name2_bad.v index 62b8845c8..839c51069 100644 --- a/test_regress/t/t_lint_import_name2_bad.v +++ b/test_regress/t/t_lint_import_name2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 import missing::sigs; diff --git a/test_regress/t/t_lint_import_name_bad.py b/test_regress/t/t_lint_import_name_bad.py index 0db29c160..d323cd7c4 100755 --- a/test_regress/t/t_lint_import_name_bad.py +++ b/test_regress/t/t_lint_import_name_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_import_name_bad.v b/test_regress/t/t_lint_import_name_bad.v index 0c5d0c17a..b1852bd1b 100644 --- a/test_regress/t/t_lint_import_name_bad.v +++ b/test_regress/t/t_lint_import_name_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package defs; diff --git a/test_regress/t/t_lint_importstar_bad.out b/test_regress/t/t_lint_importstar_bad.out index 7b8e68e91..d3b522660 100644 --- a/test_regress/t/t_lint_importstar_bad.out +++ b/test_regress/t/t_lint_importstar_bad.out @@ -3,4 +3,10 @@ | ^~~~ ... For warning description see https://verilator.org/warn/IMPORTSTAR?v=latest ... Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message. +%Warning-UNUSEDPARAM: t/t_lint_importstar_bad.v:8:15: Parameter is not used: 'PAR' + : ... note: In instance 't' + 8 | localparam PAR = 1; + | ^~~ + ... For warning description see https://verilator.org/warn/UNUSEDPARAM?v=latest + ... Use "/* verilator lint_off UNUSEDPARAM */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_importstar_bad.py b/test_regress/t/t_lint_importstar_bad.py index 0db29c160..d323cd7c4 100755 --- a/test_regress/t/t_lint_importstar_bad.py +++ b/test_regress/t/t_lint_importstar_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_importstar_bad.v b/test_regress/t/t_lint_importstar_bad.v index 752d64a64..4dc7f6818 100644 --- a/test_regress/t/t_lint_importstar_bad.v +++ b/test_regress/t/t_lint_importstar_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package defs; diff --git a/test_regress/t/t_lint_in_inc_bad.py b/test_regress/t/t_lint_in_inc_bad.py index 6307c426b..1d7fe1a84 100755 --- a/test_regress/t/t_lint_in_inc_bad.py +++ b/test_regress/t/t_lint_in_inc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_in_inc_bad.v b/test_regress/t/t_lint_in_inc_bad.v index c2fdd72b6..3e40cbe87 100644 --- a/test_regress/t/t_lint_in_inc_bad.v +++ b/test_regress/t/t_lint_in_inc_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "t_lint_in_inc_bad_1.vh" diff --git a/test_regress/t/t_lint_in_inc_bad_1.vh b/test_regress/t/t_lint_in_inc_bad_1.vh index 976417f23..d733874bc 100644 --- a/test_regress/t/t_lint_in_inc_bad_1.vh +++ b/test_regress/t/t_lint_in_inc_bad_1.vh @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "t_lint_in_inc_bad_2.vh" diff --git a/test_regress/t/t_lint_in_inc_bad_2.vh b/test_regress/t/t_lint_in_inc_bad_2.vh index 2921bd853..cfcc5be74 100644 --- a/test_regress/t/t_lint_in_inc_bad_2.vh +++ b/test_regress/t/t_lint_in_inc_bad_2.vh @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module x; diff --git a/test_regress/t/t_lint_incabspath.py b/test_regress/t/t_lint_incabspath.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_incabspath.py +++ b/test_regress/t/t_lint_incabspath.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_incabspath.v b/test_regress/t/t_lint_incabspath.v index 2148dc776..6094afe94 100644 --- a/test_regress/t/t_lint_incabspath.v +++ b/test_regress/t/t_lint_incabspath.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "/dev/null" diff --git a/test_regress/t/t_lint_incabspath_bad.py b/test_regress/t/t_lint_incabspath_bad.py index bed07adeb..136bb4087 100755 --- a/test_regress/t/t_lint_incabspath_bad.py +++ b/test_regress/t/t_lint_incabspath_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_infinite.py b/test_regress/t/t_lint_infinite.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_lint_infinite.py +++ b/test_regress/t/t_lint_infinite.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_infinite.v b/test_regress/t/t_lint_infinite.v index 305cd1e2d..62a8667e3 100644 --- a/test_regress/t/t_lint_infinite.v +++ b/test_regress/t/t_lint_infinite.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_infinite_bad.py b/test_regress/t/t_lint_infinite_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_infinite_bad.py +++ b/test_regress/t/t_lint_infinite_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_infinite_bad.v b/test_regress/t/t_lint_infinite_bad.v index c3cc1cc1b..8e11c11f4 100644 --- a/test_regress/t/t_lint_infinite_bad.v +++ b/test_regress/t/t_lint_infinite_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_inherit.py b/test_regress/t/t_lint_inherit.py index 5484b6a2d..9fd13a76c 100755 --- a/test_regress/t/t_lint_inherit.py +++ b/test_regress/t/t_lint_inherit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_inherit.v b/test_regress/t/t_lint_inherit.v index eb2982c1f..4a8ccac95 100644 --- a/test_regress/t/t_lint_inherit.v +++ b/test_regress/t/t_lint_inherit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_input_eq_good.py b/test_regress/t/t_lint_input_eq_good.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_input_eq_good.py +++ b/test_regress/t/t_lint_input_eq_good.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_input_eq_good.v b/test_regress/t/t_lint_input_eq_good.v index 547fb6f69..6e7600492 100644 --- a/test_regress/t/t_lint_input_eq_good.v +++ b/test_regress/t/t_lint_input_eq_good.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_lint_latch_1.py b/test_regress/t/t_lint_latch_1.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_latch_1.py +++ b/test_regress/t/t_lint_latch_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_1.v b/test_regress/t/t_lint_latch_1.v index a6a5640e1..a7a802c4e 100644 --- a/test_regress/t/t_lint_latch_1.v +++ b/test_regress/t/t_lint_latch_1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #1609 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Julien Margetts. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Julien Margetts // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ a, b, o); diff --git a/test_regress/t/t_lint_latch_2.py b/test_regress/t/t_lint_latch_2.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_latch_2.py +++ b/test_regress/t/t_lint_latch_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_2.v b/test_regress/t/t_lint_latch_2.v index e447f3216..c4e12e201 100644 --- a/test_regress/t/t_lint_latch_2.v +++ b/test_regress/t/t_lint_latch_2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #1609 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Julien Margetts. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Julien Margetts // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ i, o); diff --git a/test_regress/t/t_lint_latch_3.py b/test_regress/t/t_lint_latch_3.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_latch_3.py +++ b/test_regress/t/t_lint_latch_3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_3.v b/test_regress/t/t_lint_latch_3.v index cfc3461c9..840054b93 100644 --- a/test_regress/t/t_lint_latch_3.v +++ b/test_regress/t/t_lint_latch_3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #1609 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Julien Margetts. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Julien Margetts // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ out, out2, in ); diff --git a/test_regress/t/t_lint_latch_4.py b/test_regress/t/t_lint_latch_4.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_latch_4.py +++ b/test_regress/t/t_lint_latch_4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_4.v b/test_regress/t/t_lint_latch_4.v index c91093ea1..2c954d9e4 100644 --- a/test_regress/t/t_lint_latch_4.v +++ b/test_regress/t/t_lint_latch_4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #2938 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Julien Margetts (Originally provided by YanJiun) +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Julien Margetts (Originally provided by YanJiun) // SPDX-License-Identifier: Unlicense module test ( diff --git a/test_regress/t/t_lint_latch_5.py b/test_regress/t/t_lint_latch_5.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_latch_5.py +++ b/test_regress/t/t_lint_latch_5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_5.v b/test_regress/t/t_lint_latch_5.v index e1d276789..a0a6482b5 100644 --- a/test_regress/t/t_lint_latch_5.v +++ b/test_regress/t/t_lint_latch_5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #2863 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Julien Margetts (Originally provided by Thomas Sailer) +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Julien Margetts (Originally provided by Thomas Sailer) // SPDX-License-Identifier: Unlicense module test diff --git a/test_regress/t/t_lint_latch_6.py b/test_regress/t/t_lint_latch_6.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_latch_6.py +++ b/test_regress/t/t_lint_latch_6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_6.v b/test_regress/t/t_lint_latch_6.v index 9383231ff..19e6bcde9 100644 --- a/test_regress/t/t_lint_latch_6.v +++ b/test_regress/t/t_lint_latch_6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #221 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Julien Margetts (Originally provided by Adrien Le Masle) +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Julien Margetts (Originally provided by Adrien Le Masle) // SPDX-License-Identifier: Unlicense module verilator_latch diff --git a/test_regress/t/t_lint_latch_7.py b/test_regress/t/t_lint_latch_7.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_latch_7.py +++ b/test_regress/t/t_lint_latch_7.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_7.v b/test_regress/t/t_lint_latch_7.v index d8fbbc1c6..3367ad606 100644 --- a/test_regress/t/t_lint_latch_7.v +++ b/test_regress/t/t_lint_latch_7.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for Issue#xxxx // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Julien Margetts +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Julien Margetts // SPDX-License-Identifier: Unlicense module test #(parameter W = 65) diff --git a/test_regress/t/t_lint_latch_8.py b/test_regress/t/t_lint_latch_8.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_latch_8.py +++ b/test_regress/t/t_lint_latch_8.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_8.v b/test_regress/t/t_lint_latch_8.v index c000117aa..3a4fe75a2 100644 --- a/test_regress/t/t_lint_latch_8.v +++ b/test_regress/t/t_lint_latch_8.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Yutetsu TAKATSUKASA +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Yutetsu TAKATSUKASA // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t(input wire clk); diff --git a/test_regress/t/t_lint_latch_bad.py b/test_regress/t/t_lint_latch_bad.py index d3baf9587..4f2949426 100755 --- a/test_regress/t/t_lint_latch_bad.py +++ b/test_regress/t/t_lint_latch_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_bad.v b/test_regress/t/t_lint_latch_bad.v index 74d7224a4..34415dbfd 100644 --- a/test_regress/t/t_lint_latch_bad.v +++ b/test_regress/t/t_lint_latch_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_latch_bad_2.py b/test_regress/t/t_lint_latch_bad_2.py index dece38f4e..c7d9b21a5 100755 --- a/test_regress/t/t_lint_latch_bad_2.py +++ b/test_regress/t/t_lint_latch_bad_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_bad_2.v b/test_regress/t/t_lint_latch_bad_2.v index 75ef49a6d..5469957f9 100644 --- a/test_regress/t/t_lint_latch_bad_2.v +++ b/test_regress/t/t_lint_latch_bad_2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #1609 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Julien Margetts. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Julien Margetts // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ a, b, o); diff --git a/test_regress/t/t_lint_latch_bad_3.py b/test_regress/t/t_lint_latch_bad_3.py index dece38f4e..c7d9b21a5 100755 --- a/test_regress/t/t_lint_latch_bad_3.py +++ b/test_regress/t/t_lint_latch_bad_3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_bad_3.v b/test_regress/t/t_lint_latch_bad_3.v index 386a9d460..04a91581e 100644 --- a/test_regress/t/t_lint_latch_bad_3.v +++ b/test_regress/t/t_lint_latch_bad_3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #1609 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Julien Margetts. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Julien Margetts // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ reset, a, b, c, en, o1, o2, o3, o4, o5); diff --git a/test_regress/t/t_lint_latch_casei_bad.py b/test_regress/t/t_lint_latch_casei_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_lint_latch_casei_bad.py +++ b/test_regress/t/t_lint_latch_casei_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_latch_casei_bad.v b/test_regress/t/t_lint_latch_casei_bad.v index 001813cd2..cbb2331b5 100644 --- a/test_regress/t/t_lint_latch_casei_bad.v +++ b/test_regress/t/t_lint_latch_casei_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for Issue#1609 // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_lint_bad.py b/test_regress/t/t_lint_lint_bad.py index 343c375b5..cf3c65504 100755 --- a/test_regress/t/t_lint_lint_bad.py +++ b/test_regress/t/t_lint_lint_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_lint_bad.v b/test_regress/t/t_lint_lint_bad.v index 4fdbcc574..d06b6b0b5 100644 --- a/test_regress/t/t_lint_lint_bad.v +++ b/test_regress/t/t_lint_lint_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_lint_no.py b/test_regress/t/t_lint_lint_no.py index 1a4025a8e..6ae80f83b 100755 --- a/test_regress/t/t_lint_lint_no.py +++ b/test_regress/t/t_lint_lint_no.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_literal_bad.py b/test_regress/t/t_lint_literal_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_literal_bad.py +++ b/test_regress/t/t_lint_literal_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_literal_bad.v b/test_regress/t/t_lint_literal_bad.v index 456feed9b..ca1682e32 100644 --- a/test_regress/t/t_lint_literal_bad.v +++ b/test_regress/t/t_lint_literal_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Todd Strader // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_misindent_bad.py b/test_regress/t/t_lint_misindent_bad.py index 946e0710c..83517505a 100755 --- a/test_regress/t/t_lint_misindent_bad.py +++ b/test_regress/t/t_lint_misindent_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_misindent_bad.v b/test_regress/t/t_lint_misindent_bad.v index 7cc2752f8..876f1971c 100644 --- a/test_regress/t/t_lint_misindent_bad.v +++ b/test_regress/t/t_lint_misindent_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Do not reindent - spaces are critical to this test diff --git a/test_regress/t/t_lint_mod_paren_bad.py b/test_regress/t/t_lint_mod_paren_bad.py index 215c97d4b..a7ec689ac 100755 --- a/test_regress/t/t_lint_mod_paren_bad.py +++ b/test_regress/t/t_lint_mod_paren_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_mod_paren_bad.v b/test_regress/t/t_lint_mod_paren_bad.v index 6f01fb8ab..62113f29f 100644 --- a/test_regress/t/t_lint_mod_paren_bad.v +++ b/test_regress/t/t_lint_mod_paren_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Should have been: diff --git a/test_regress/t/t_lint_modmissing.py b/test_regress/t/t_lint_modmissing.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_modmissing.py +++ b/test_regress/t/t_lint_modmissing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_modmissing.v b/test_regress/t/t_lint_modmissing.v index 9798cf4e6..7cfa890cc 100644 --- a/test_regress/t/t_lint_modmissing.v +++ b/test_regress/t/t_lint_modmissing.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_modport_dir_bad.py b/test_regress/t/t_lint_modport_dir_bad.py index ae0961bea..d31c48bf5 100755 --- a/test_regress/t/t_lint_modport_dir_bad.py +++ b/test_regress/t/t_lint_modport_dir_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_modport_dir_bad.v b/test_regress/t/t_lint_modport_dir_bad.v index 708b920f9..31c056dda 100644 --- a/test_regress/t/t_lint_modport_dir_bad.v +++ b/test_regress/t/t_lint_modport_dir_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface dummy_if (); diff --git a/test_regress/t/t_lint_multidriven_bad.py b/test_regress/t/t_lint_multidriven_bad.py index 5f9429530..b265fb71a 100755 --- a/test_regress/t/t_lint_multidriven_bad.py +++ b/test_regress/t/t_lint_multidriven_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_multidriven_bad.v b/test_regress/t/t_lint_multidriven_bad.v index 0b3ff7bff..dff9f4010 100644 --- a/test_regress/t/t_lint_multidriven_bad.v +++ b/test_regress/t/t_lint_multidriven_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_lint_multidriven_taskcall_bad.out b/test_regress/t/t_lint_multidriven_taskcall_bad.out new file mode 100644 index 000000000..1d1278b14 --- /dev/null +++ b/test_regress/t/t_lint_multidriven_taskcall_bad.out @@ -0,0 +1,11 @@ +%Warning-MULTIDRIVEN: t/t_lint_multidriven_taskcall_bad.v:28:15: Variable written to in always_comb also written by other process (IEEE 1800-2023 9.2.2.2): 'out' + : ... note: In instance 't' + t/t_lint_multidriven_taskcall_bad.v:28:15: + 28 | if (sel2) out = 1'b1; + | ^~~ + t/t_lint_multidriven_taskcall_bad.v:20:5: ... Location of other write + 20 | out = 1'b0; + | ^~~ + ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest + ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_lint_multidriven_taskcall_bad.py b/test_regress/t/t_lint_multidriven_taskcall_bad.py new file mode 100755 index 000000000..c7d9b21a5 --- /dev/null +++ b/test_regress/t/t_lint_multidriven_taskcall_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_multidriven_taskcall_bad.v b/test_regress/t/t_lint_multidriven_taskcall_bad.v new file mode 100644 index 000000000..f5e60812d --- /dev/null +++ b/test_regress/t/t_lint_multidriven_taskcall_bad.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain. +// SPDX-FileCopyrightText: 2026 em2machine +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input logic sel, + input logic sel2, + input logic d, + output logic out +); + + task automatic do_stuff(input logic din); + out = din; + endtask + + // Driver #1 (via task call) + always_comb begin + out = 1'b0; + if (sel) do_stuff(d); + end + + // Driver #2 (separate process) + // I only want the MULTIDRIVEN. + /* verilator lint_off LATCH */ + always_comb begin + if (sel2) out = 1'b1; + end + /* verilator lint_on LATCH */ + +endmodule diff --git a/test_regress/t/t_lint_multiple_msgs.py b/test_regress/t/t_lint_multiple_msgs.py index a2176db03..c5db92dbb 100755 --- a/test_regress/t/t_lint_multiple_msgs.py +++ b/test_regress/t/t_lint_multiple_msgs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_multiple_msgs.v b/test_regress/t/t_lint_multiple_msgs.v index e7ddd5bec..4432f0db5 100644 --- a/test_regress/t/t_lint_multiple_msgs.v +++ b/test_regress/t/t_lint_multiple_msgs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_nolatch_bad.py b/test_regress/t/t_lint_nolatch_bad.py index dece38f4e..c7d9b21a5 100755 --- a/test_regress/t/t_lint_nolatch_bad.py +++ b/test_regress/t/t_lint_nolatch_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_nolatch_bad.v b/test_regress/t/t_lint_nolatch_bad.v index 715c5884b..aba7bba5a 100644 --- a/test_regress/t/t_lint_nolatch_bad.v +++ b/test_regress/t/t_lint_nolatch_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for issue #1609 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Julien Margetts. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Julien Margetts // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ a, b, o); diff --git a/test_regress/t/t_lint_noreturn.py b/test_regress/t/t_lint_noreturn.py index 506c4f8b2..609a0c821 100755 --- a/test_regress/t/t_lint_noreturn.py +++ b/test_regress/t/t_lint_noreturn.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_noreturn.v b/test_regress/t/t_lint_noreturn.v index 62d2d02fa..55e08a7cc 100644 --- a/test_regress/t/t_lint_noreturn.v +++ b/test_regress/t/t_lint_noreturn.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_noreturn_bad.py b/test_regress/t/t_lint_noreturn_bad.py index cd6a0720b..eb5d76356 100755 --- a/test_regress/t/t_lint_noreturn_bad.py +++ b/test_regress/t/t_lint_noreturn_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_noreturn_param.py b/test_regress/t/t_lint_noreturn_param.py index 506c4f8b2..609a0c821 100755 --- a/test_regress/t/t_lint_noreturn_param.py +++ b/test_regress/t/t_lint_noreturn_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_noreturn_param.v b/test_regress/t/t_lint_noreturn_param.v index f8855f158..c2d3fd607 100644 --- a/test_regress/t/t_lint_noreturn_param.v +++ b/test_regress/t/t_lint_noreturn_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_noreturn_param_bad.py b/test_regress/t/t_lint_noreturn_param_bad.py index 5f286b96d..e2f975414 100755 --- a/test_regress/t/t_lint_noreturn_param_bad.py +++ b/test_regress/t/t_lint_noreturn_param_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_noreturn_param_bad.v b/test_regress/t/t_lint_noreturn_param_bad.v index b6e217d10..449759ff8 100644 --- a/test_regress/t/t_lint_noreturn_param_bad.v +++ b/test_regress/t/t_lint_noreturn_param_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_nullport_bad.py b/test_regress/t/t_lint_nullport_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_nullport_bad.py +++ b/test_regress/t/t_lint_nullport_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_nullport_bad.v b/test_regress/t/t_lint_nullport_bad.v index 5b42dc176..1f729cd0a 100644 --- a/test_regress/t/t_lint_nullport_bad.v +++ b/test_regress/t/t_lint_nullport_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Udi Finkelstein. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Udi Finkelstein // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off MULTITOP */ diff --git a/test_regress/t/t_lint_numwidth.py b/test_regress/t/t_lint_numwidth.py index 9f7577b1b..395428d5b 100755 --- a/test_regress/t/t_lint_numwidth.py +++ b/test_regress/t/t_lint_numwidth.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_numwidth.v b/test_regress/t/t_lint_numwidth.v index 52ec94895..f215768b2 100644 --- a/test_regress/t/t_lint_numwidth.v +++ b/test_regress/t/t_lint_numwidth.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 logic [65535:0] a = 65536'd1; diff --git a/test_regress/t/t_lint_once_bad.py b/test_regress/t/t_lint_once_bad.py index fcc71dff4..a75ac133d 100755 --- a/test_regress/t/t_lint_once_bad.py +++ b/test_regress/t/t_lint_once_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_once_bad.v b/test_regress/t/t_lint_once_bad.v index 099f6d99d..a148e5510 100644 --- a/test_regress/t/t_lint_once_bad.v +++ b/test_regress/t/t_lint_once_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Check that we report warnings only once on parameterized modules diff --git a/test_regress/t/t_lint_only.py b/test_regress/t/t_lint_only.py index 6bd600182..b0d3d6d2e 100755 --- a/test_regress/t/t_lint_only.py +++ b/test_regress/t/t_lint_only.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_only.v b/test_regress/t/t_lint_only.v index 123bfbcb0..e0ab4d0df 100644 --- a/test_regress/t/t_lint_only.v +++ b/test_regress/t/t_lint_only.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_paramnodefault.py b/test_regress/t/t_lint_paramnodefault.py index bedf95356..2e4afb178 100755 --- a/test_regress/t/t_lint_paramnodefault.py +++ b/test_regress/t/t_lint_paramnodefault.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_paramnodefault.v b/test_regress/t/t_lint_paramnodefault.v index dcc4e23fa..aef5d515c 100644 --- a/test_regress/t/t_lint_paramnodefault.v +++ b/test_regress/t/t_lint_paramnodefault.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub; diff --git a/test_regress/t/t_lint_paramnodefault_bad.py b/test_regress/t/t_lint_paramnodefault_bad.py index a7e39a6c8..14dd88dbb 100755 --- a/test_regress/t/t_lint_paramnodefault_bad.py +++ b/test_regress/t/t_lint_paramnodefault_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_pindup_bad.out b/test_regress/t/t_lint_pindup_bad.out index ef1bb3d7f..976e5f7e3 100644 --- a/test_regress/t/t_lint_pindup_bad.out +++ b/test_regress/t/t_lint_pindup_bad.out @@ -17,11 +17,17 @@ : ... Suggested alternative: 'exists' 21 | .nexist(i2) | ^~~~~~ + : ... Location of instance's module declaration + 26 | module sub + | ^~~ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error-PINNOTFOUND: t/t_lint_pindup_bad.v:15:9: Parameter not found: 'NEXIST' : ... Suggested alternative: 'EXIST' 15 | #(.NEXIST(1), | ^~~~~~ + : ... Location of instance's module declaration + 26 | module sub + | ^~~ %Error: t/t_lint_pindup_bad.v:17:9: Duplicate parameter connection: 'P' 17 | .P(3)) | ^ diff --git a/test_regress/t/t_lint_pindup_bad.py b/test_regress/t/t_lint_pindup_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_pindup_bad.py +++ b/test_regress/t/t_lint_pindup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_pindup_bad.v b/test_regress/t/t_lint_pindup_bad.v index f98163b7f..ae92719d5 100644 --- a/test_regress/t/t_lint_pindup_bad.v +++ b/test_regress/t/t_lint_pindup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_lint_pinmissing_bad.py b/test_regress/t/t_lint_pinmissing_bad.py index 83b37efab..5ec2083e0 100755 --- a/test_regress/t/t_lint_pinmissing_bad.py +++ b/test_regress/t/t_lint_pinmissing_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_pinmissing_bad.v b/test_regress/t/t_lint_pinmissing_bad.v index ef1de6b05..a14735654 100644 --- a/test_regress/t/t_lint_pinmissing_bad.v +++ b/test_regress/t/t_lint_pinmissing_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_pinnotfound.py b/test_regress/t/t_lint_pinnotfound.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_pinnotfound.py +++ b/test_regress/t/t_lint_pinnotfound.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_pinnotfound.v b/test_regress/t/t_lint_pinnotfound.v index 63f611b10..b45b7859a 100644 --- a/test_regress/t/t_lint_pinnotfound.v +++ b/test_regress/t/t_lint_pinnotfound.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off PINNOTFOUND */ diff --git a/test_regress/t/t_lint_pinnotfound_bad.out b/test_regress/t/t_lint_pinnotfound_bad.out index 6aded1ba0..3753eb3bf 100644 --- a/test_regress/t/t_lint_pinnotfound_bad.out +++ b/test_regress/t/t_lint_pinnotfound_bad.out @@ -1,8 +1,14 @@ %Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:12:13: Pin not found: 'x' 12 | b b_inst1 (.x(1'b0)); | ^ + : ... Location of instance's module declaration + 18 | module b; + | ^ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:13:6: Parameter not found: 'PX' 13 | b #(.PX(1'b0)) b_inst2 (); | ^~ + : ... Location of instance's module declaration + 18 | module b; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_pinnotfound_bad.py b/test_regress/t/t_lint_pinnotfound_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_pinnotfound_bad.py +++ b/test_regress/t/t_lint_pinnotfound_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_pinnotfound_bad.v b/test_regress/t/t_lint_pinnotfound_bad.v index c7128a41a..9810cdf04 100644 --- a/test_regress/t/t_lint_pinnotfound_bad.v +++ b/test_regress/t/t_lint_pinnotfound_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module a; diff --git a/test_regress/t/t_lint_pkg_colon_bad.py b/test_regress/t/t_lint_pkg_colon_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_pkg_colon_bad.py +++ b/test_regress/t/t_lint_pkg_colon_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_pkg_colon_bad.v b/test_regress/t/t_lint_pkg_colon_bad.v index ece082d5b..0a1c9a429 100644 --- a/test_regress/t/t_lint_pkg_colon_bad.v +++ b/test_regress/t/t_lint_pkg_colon_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (input mispkg::foo_t a); diff --git a/test_regress/t/t_lint_pragma_protected.py b/test_regress/t/t_lint_pragma_protected.py index 3b4ab2b45..9a7de48b6 100755 --- a/test_regress/t/t_lint_pragma_protected.py +++ b/test_regress/t/t_lint_pragma_protected.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_pragma_protected.v b/test_regress/t/t_lint_pragma_protected.v index 5525477b2..1d5250340 100644 --- a/test_regress/t/t_lint_pragma_protected.v +++ b/test_regress/t/t_lint_pragma_protected.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // This part should pass OK diff --git a/test_regress/t/t_lint_pragma_protected_bad.py b/test_regress/t/t_lint_pragma_protected_bad.py index e1346660f..147dce6d6 100755 --- a/test_regress/t/t_lint_pragma_protected_bad.py +++ b/test_regress/t/t_lint_pragma_protected_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_pragma_protected_bad.v b/test_regress/t/t_lint_pragma_protected_bad.v index c2488b2b7..3634481f4 100644 --- a/test_regress/t/t_lint_pragma_protected_bad.v +++ b/test_regress/t/t_lint_pragma_protected_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_lint_pragma_protected_err; diff --git a/test_regress/t/t_lint_procassinit_bad.py b/test_regress/t/t_lint_procassinit_bad.py index c95232256..731735002 100755 --- a/test_regress/t/t_lint_procassinit_bad.py +++ b/test_regress/t/t_lint_procassinit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_procassinit_bad.v b/test_regress/t/t_lint_procassinit_bad.v index c358fcf0b..6ed6a30a1 100644 --- a/test_regress/t/t_lint_procassinit_bad.v +++ b/test_regress/t/t_lint_procassinit_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_lint_range_negative_bad.py b/test_regress/t/t_lint_range_negative_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_lint_range_negative_bad.py +++ b/test_regress/t/t_lint_range_negative_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_range_negative_bad.v b/test_regress/t/t_lint_range_negative_bad.v index f1a578184..daf4c6951 100644 --- a/test_regress/t/t_lint_range_negative_bad.v +++ b/test_regress/t/t_lint_range_negative_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_realcvt_bad.py b/test_regress/t/t_lint_realcvt_bad.py index f1cb99e8a..8e8b79bd3 100755 --- a/test_regress/t/t_lint_realcvt_bad.py +++ b/test_regress/t/t_lint_realcvt_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_realcvt_bad.v b/test_regress/t/t_lint_realcvt_bad.v index 819f218ab..f6da7945c 100644 --- a/test_regress/t/t_lint_realcvt_bad.v +++ b/test_regress/t/t_lint_realcvt_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps diff --git a/test_regress/t/t_lint_repeat_bad.py b/test_regress/t/t_lint_repeat_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_repeat_bad.py +++ b/test_regress/t/t_lint_repeat_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_repeat_bad.v b/test_regress/t/t_lint_repeat_bad.v index 18dac4075..747c3b6b0 100644 --- a/test_regress/t/t_lint_repeat_bad.v +++ b/test_regress/t/t_lint_repeat_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_restore_bad.py b/test_regress/t/t_lint_restore_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_restore_bad.py +++ b/test_regress/t/t_lint_restore_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_restore_bad.v b/test_regress/t/t_lint_restore_bad.v index 6ab896dbb..8566a9650 100644 --- a/test_regress/t/t_lint_restore_bad.v +++ b/test_regress/t/t_lint_restore_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_restore_prag_bad.py b/test_regress/t/t_lint_restore_prag_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_restore_prag_bad.py +++ b/test_regress/t/t_lint_restore_prag_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_restore_prag_bad.v b/test_regress/t/t_lint_restore_prag_bad.v index 643b001d5..71a05c912 100644 --- a/test_regress/t/t_lint_restore_prag_bad.v +++ b/test_regress/t/t_lint_restore_prag_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_setout_bad.py b/test_regress/t/t_lint_setout_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_setout_bad.py +++ b/test_regress/t/t_lint_setout_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_setout_bad.v b/test_regress/t/t_lint_setout_bad.v index 23a4339ba..c23a3d127 100644 --- a/test_regress/t/t_lint_setout_bad.v +++ b/test_regress/t/t_lint_setout_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_lint_setout_bad_noinl.py b/test_regress/t/t_lint_setout_bad_noinl.py index 829e79ef1..8e646961a 100755 --- a/test_regress/t/t_lint_setout_bad_noinl.py +++ b/test_regress/t/t_lint_setout_bad_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_sideeffect_bad.py b/test_regress/t/t_lint_sideeffect_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_sideeffect_bad.py +++ b/test_regress/t/t_lint_sideeffect_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_sideeffect_bad.v b/test_regress/t/t_lint_sideeffect_bad.v index 09e258028..951150aec 100644 --- a/test_regress/t/t_lint_sideeffect_bad.v +++ b/test_regress/t/t_lint_sideeffect_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 Krzysztof Boronski. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Krzysztof Boronski // SPDX-License-Identifier: CC0-1.0 int i = 0; @@ -12,7 +12,7 @@ endfunction module t; initial begin - int arr [3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}}; + automatic int arr [3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}}; i = 0; arr[postincrement_i()][postincrement_i()]++; $display("Value: %d", i); diff --git a/test_regress/t/t_lint_stmtdly_bad.py b/test_regress/t/t_lint_stmtdly_bad.py index 35944aa6d..7ad9ec5d1 100755 --- a/test_regress/t/t_lint_stmtdly_bad.py +++ b/test_regress/t/t_lint_stmtdly_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_stmtdly_bad.v b/test_regress/t/t_lint_stmtdly_bad.v index 47ecd9c71..b812c6169 100644 --- a/test_regress/t/t_lint_stmtdly_bad.v +++ b/test_regress/t/t_lint_stmtdly_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_style_bad.out b/test_regress/t/t_lint_style_bad.out index 7de1ed0bc..0bdd6124a 100644 --- a/test_regress/t/t_lint_style_bad.out +++ b/test_regress/t/t_lint_style_bad.out @@ -23,7 +23,7 @@ | ^~~ ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. -%Warning-UNDRIVEN: t/t_lint_style_bad.v:12:14: Signal is not driven: 'top' +%Warning-UNDRIVEN: t/t_lint_style_bad.v:12:14: Function variable is not driven: 'top' : ... note: In instance 't' 12 | output top; | ^~~ diff --git a/test_regress/t/t_lint_style_bad.py b/test_regress/t/t_lint_style_bad.py index 308d8264d..91f2ce8c4 100755 --- a/test_regress/t/t_lint_style_bad.py +++ b/test_regress/t/t_lint_style_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_style_bad.v b/test_regress/t/t_lint_style_bad.v index 8fbf2ed69..74ff5eace 100644 --- a/test_regress/t/t_lint_style_bad.v +++ b/test_regress/t/t_lint_style_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_style_no.py b/test_regress/t/t_lint_style_no.py index e53007ac0..1f408562a 100755 --- a/test_regress/t/t_lint_style_no.py +++ b/test_regress/t/t_lint_style_no.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_subout_bad.py b/test_regress/t/t_lint_subout_bad.py index 8ddea4fed..7e2db3ed9 100755 --- a/test_regress/t/t_lint_subout_bad.py +++ b/test_regress/t/t_lint_subout_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_subout_bad.v b/test_regress/t/t_lint_subout_bad.v index 703d59a1c..52f2da80a 100644 --- a/test_regress/t/t_lint_subout_bad.v +++ b/test_regress/t/t_lint_subout_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNDRIVEN diff --git a/test_regress/t/t_lint_syncasyncnet_bad.py b/test_regress/t/t_lint_syncasyncnet_bad.py index 3753ea9a5..d95ff8477 100755 --- a/test_regress/t/t_lint_syncasyncnet_bad.py +++ b/test_regress/t/t_lint_syncasyncnet_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_syncasyncnet_bad.v b/test_regress/t/t_lint_syncasyncnet_bad.v index 9db96f3fe..572ab35e2 100644 --- a/test_regress/t/t_lint_syncasyncnet_bad.v +++ b/test_regress/t/t_lint_syncasyncnet_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_top_bad.py b/test_regress/t/t_lint_top_bad.py index 161c81983..15fe13439 100755 --- a/test_regress/t/t_lint_top_bad.py +++ b/test_regress/t/t_lint_top_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_top_bad.v b/test_regress/t/t_lint_top_bad.v index 22980818f..7986feed2 100644 --- a/test_regress/t/t_lint_top_bad.v +++ b/test_regress/t/t_lint_top_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub(input wire clk, cpu_reset); diff --git a/test_regress/t/t_lint_unsigned_bad.py b/test_regress/t/t_lint_unsigned_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_unsigned_bad.py +++ b/test_regress/t/t_lint_unsigned_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unsigned_bad.v b/test_regress/t/t_lint_unsigned_bad.v index 8b7cb0c48..9ede747a6 100644 --- a/test_regress/t/t_lint_unsigned_bad.v +++ b/test_regress/t/t_lint_unsigned_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_unsup_deassign.py b/test_regress/t/t_lint_unsup_deassign.py index 4dd72181f..3afe39002 100755 --- a/test_regress/t/t_lint_unsup_deassign.py +++ b/test_regress/t/t_lint_unsup_deassign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unsup_deassign.v b/test_regress/t/t_lint_unsup_deassign.v index 77c1f2f1d..b89a5a40b 100644 --- a/test_regress/t/t_lint_unsup_deassign.v +++ b/test_regress/t/t_lint_unsup_deassign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_lint_unsup_deassign_bad.out b/test_regress/t/t_lint_unsup_deassign_bad.out new file mode 100644 index 000000000..3128fa94a --- /dev/null +++ b/test_regress/t/t_lint_unsup_deassign_bad.out @@ -0,0 +1,5 @@ +%Error-UNSUPPORTED: t/t_lint_unsup_deassign.v:19:8: Unsupported: Verilog 1995 deassign + 19 | deassign q; + | ^~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_lint_unsup_deassign_bad.py b/test_regress/t/t_lint_unsup_deassign_bad.py new file mode 100755 index 000000000..971993c3a --- /dev/null +++ b/test_regress/t/t_lint_unsup_deassign_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') +test.top_filename = "t/t_lint_unsup_deassign.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lint_unsup_mixed.py b/test_regress/t/t_lint_unsup_mixed.py index 4dd72181f..3afe39002 100755 --- a/test_regress/t/t_lint_unsup_mixed.py +++ b/test_regress/t/t_lint_unsup_mixed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unsup_mixed.v b/test_regress/t/t_lint_unsup_mixed.v index 3681f56b3..6e74f217f 100644 --- a/test_regress/t/t_lint_unsup_mixed.v +++ b/test_regress/t/t_lint_unsup_mixed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_lint_unused.py b/test_regress/t/t_lint_unused.py index 9e9a93a06..907f60370 100755 --- a/test_regress/t/t_lint_unused.py +++ b/test_regress/t/t_lint_unused.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unused.v b/test_regress/t/t_lint_unused.v index 697706563..e384b98de 100644 --- a/test_regress/t/t_lint_unused.v +++ b/test_regress/t/t_lint_unused.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_lint_unused_bad.py b/test_regress/t/t_lint_unused_bad.py index 4108fcca7..311bc8a6d 100755 --- a/test_regress/t/t_lint_unused_bad.py +++ b/test_regress/t/t_lint_unused_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unused_bad.v b/test_regress/t/t_lint_unused_bad.v index 47a8d7804..eedde21d8 100644 --- a/test_regress/t/t_lint_unused_bad.v +++ b/test_regress/t/t_lint_unused_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_unused_func_bad.out b/test_regress/t/t_lint_unused_func_bad.out new file mode 100644 index 000000000..e85551431 --- /dev/null +++ b/test_regress/t/t_lint_unused_func_bad.out @@ -0,0 +1,29 @@ +%Warning-UNUSEDSIGNAL: t/t_lint_unused_func_bad.v:15:7: Function variable is not used: 'not_used' + : ... note: In instance 't' + 15 | int not_used); + | ^~~~~~~~ + ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest + ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message. +%Warning-UNDRIVEN: t/t_lint_unused_func_bad.v:21:7: Function variable is not driven: 'not_driven' + : ... note: In instance 't' + 21 | int not_driven; + | ^~~~~~~~~~ + ... For warning description see https://verilator.org/warn/UNDRIVEN?v=latest + ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. +%Warning-UNDRIVEN: t/t_lint_unused_func_bad.v:26:7: Function variable is not driven: 'undriven_result' + : ... note: In instance 't' + 26 | int undriven_result; + | ^~~~~~~~~~~~~~~ +%Warning-UNDRIVEN: t/t_lint_unused_func_bad.v:36:14: Function variable is not driven: 'undriven_out_param' + : ... note: In instance 't' + 36 | output int undriven_out_param); + | ^~~~~~~~~~~~~~~~~~ +%Warning-UNUSEDSIGNAL: t/t_lint_unused_func_bad.v:40:13: Function variable is not driven, nor used: 'untouched_inout_param' + : ... note: In instance 't' + 40 | inout int untouched_inout_param); + | ^~~~~~~~~~~~~~~~~~~~~ +%Warning-UNUSEDSIGNAL: t/t_lint_unused_func_bad.v:44:13: Function variable is not driven, nor used: 'untouched_inout_unused_func_param' + : ... note: In instance 't' + 44 | inout int untouched_inout_unused_func_param); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_lint_unused_func_bad.py b/test_regress/t/t_lint_unused_func_bad.py new file mode 100755 index 000000000..a67184f6e --- /dev/null +++ b/test_regress/t/t_lint_unused_func_bad.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios("linter") + +test.lint( + verilator_flags2=["--lint-only -Wall -Wno-DECLFILENAME --unused-regexp blargh"], + fails=True, + expect_filename=test.golden_filename, +) + +test.passes() diff --git a/test_regress/t/t_lint_unused_func_bad.v b/test_regress/t/t_lint_unused_func_bad.v new file mode 100644 index 000000000..1eb130dd2 --- /dev/null +++ b/test_regress/t/t_lint_unused_func_bad.v @@ -0,0 +1,63 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +function automatic int ok_unused_func(real val); + int result = $rtoi(val); + bit huh = result[0]; + return result + huh; +endfunction + +// Unused parameter +function automatic int unused_input_unused_func( + int not_used); // <-- Warning: UNUSED not_used + return 5; +endfunction + +// Undriven variable +function automatic int undriven_var_unused_func(int some_val); + int not_driven; // <--- Warning: UNDRIVEN not_driven + return some_val + not_driven; +endfunction + +function automatic int undriven_var(); + int undriven_result; // <--- Warning: UNDRIVEN undriven_result + return undriven_result; +endfunction + +function automatic int driven_var(); + int driven_result = 3; // Ok + return driven_result; +endfunction + +function automatic void undriven_output( // + output int undriven_out_param); // <-- Warning: UNDRIVEN +endfunction + +function automatic void untouched_inout( // + inout int untouched_inout_param); // <--- Warning: UNUSED +endfunction + +function automatic void untouched_inout_unused_func( // + inout int untouched_inout_unused_func_param); // <--- Warning: UNUSED +endfunction + +function automatic void driven_inout_unused_func(inout int driven_inout_unused_func_param); + driven_inout_unused_func_param = 7; +endfunction + +function automatic void used_inout_unused_func(inout int used_inout_unused_func_param); + $display(used_inout_unused_func_param); +endfunction + +module t; + int result; + initial begin + result = undriven_var(); + undriven_output(result); + untouched_inout(result); + $display(result); + end +endmodule diff --git a/test_regress/t/t_lint_unused_iface.py b/test_regress/t/t_lint_unused_iface.py index dabf243d0..1a4c2178b 100755 --- a/test_regress/t/t_lint_unused_iface.py +++ b/test_regress/t/t_lint_unused_iface.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unused_iface.v b/test_regress/t/t_lint_unused_iface.v index 3b8f61fcb..ea480fdcb 100644 --- a/test_regress/t/t_lint_unused_iface.v +++ b/test_regress/t/t_lint_unused_iface.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface dummy_if (); diff --git a/test_regress/t/t_lint_unused_iface_bad.py b/test_regress/t/t_lint_unused_iface_bad.py index ad1a5882d..ee4d17cb3 100755 --- a/test_regress/t/t_lint_unused_iface_bad.py +++ b/test_regress/t/t_lint_unused_iface_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unused_iface_bad.v b/test_regress/t/t_lint_unused_iface_bad.v index 5331ab7e6..fc30aaba6 100644 --- a/test_regress/t/t_lint_unused_iface_bad.v +++ b/test_regress/t/t_lint_unused_iface_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface dummy_if (); diff --git a/test_regress/t/t_lint_unused_tri.py b/test_regress/t/t_lint_unused_tri.py index dabf243d0..1a4c2178b 100755 --- a/test_regress/t/t_lint_unused_tri.py +++ b/test_regress/t/t_lint_unused_tri.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unused_tri.v b/test_regress/t/t_lint_unused_tri.v index 4d2646a00..fc6a0e846 100644 --- a/test_regress/t/t_lint_unused_tri.v +++ b/test_regress/t/t_lint_unused_tri.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module Receiver(in); diff --git a/test_regress/t/t_lint_unused_vlt.py b/test_regress/t/t_lint_unused_vlt.py index d2529e95b..ae9990a7e 100755 --- a/test_regress/t/t_lint_unused_vlt.py +++ b/test_regress/t/t_lint_unused_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unused_vlt.vlt b/test_regress/t/t_lint_unused_vlt.vlt index 8a23ae023..3aebb572b 100644 --- a/test_regress/t/t_lint_unused_vlt.vlt +++ b/test_regress/t/t_lint_unused_vlt.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_lint_unused_werror_bad.py b/test_regress/t/t_lint_unused_werror_bad.py index cb1332bd6..7543f684e 100755 --- a/test_regress/t/t_lint_unused_werror_bad.py +++ b/test_regress/t/t_lint_unused_werror_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unusedloop_removed_bad.py b/test_regress/t/t_lint_unusedloop_removed_bad.py index 61e258882..d7d105625 100755 --- a/test_regress/t/t_lint_unusedloop_removed_bad.py +++ b/test_regress/t/t_lint_unusedloop_removed_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_unusedloop_removed_bad.v b/test_regress/t/t_lint_unusedloop_removed_bad.v index 60462603c..ccf2bcade 100644 --- a/test_regress/t/t_lint_unusedloop_removed_bad.v +++ b/test_regress/t/t_lint_unusedloop_removed_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilator lint_off BLKSEQ @@ -226,21 +226,21 @@ module if_with_param; initial begin if (ZERO_PARAM) begin // loop under false parameterized if - no warning - int prints = 0; + int prints; while(prints < 5) begin prints++; end $write("Prints %d\n", prints); end else if (!ONE_PARAM) begin // loop under false parameterized if - no warning - int prints = 0; + int prints; while(prints < 5) begin prints++; end $write("Prints %d\n", prints); end else begin // loop under true parameterized if - no warning - int prints = 0; + int prints; while(prints < 5) begin prints++; end diff --git a/test_regress/t/t_lint_vcmarker_bad.py b/test_regress/t/t_lint_vcmarker_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_vcmarker_bad.py +++ b/test_regress/t/t_lint_vcmarker_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_vcmarker_bad.v b/test_regress/t/t_lint_vcmarker_bad.v index be2bf8ecf..217a9d6aa 100644 --- a/test_regress/t/t_lint_vcmarker_bad.v +++ b/test_regress/t/t_lint_vcmarker_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_waitconst_bad.py b/test_regress/t/t_lint_waitconst_bad.py index 42ea5c8aa..51f19853e 100755 --- a/test_regress/t/t_lint_waitconst_bad.py +++ b/test_regress/t/t_lint_waitconst_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_warn_incfile2_bad.py b/test_regress/t/t_lint_warn_incfile2_bad.py index 1add606d3..a65555478 100755 --- a/test_regress/t/t_lint_warn_incfile2_bad.py +++ b/test_regress/t/t_lint_warn_incfile2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_warn_incfile2_bad.v b/test_regress/t/t_lint_warn_incfile2_bad.v index 0d821dcd8..20c0136f5 100644 --- a/test_regress/t/t_lint_warn_incfile2_bad.v +++ b/test_regress/t/t_lint_warn_incfile2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Check that lint_off doesn't propagate from include, for post-preprocessor warnings diff --git a/test_regress/t/t_lint_warn_incfile2_bad_b.vh b/test_regress/t/t_lint_warn_incfile2_bad_b.vh index aae34e35c..bc6ffde2f 100644 --- a/test_regress/t/t_lint_warn_incfile2_bad_b.vh +++ b/test_regress/t/t_lint_warn_incfile2_bad_b.vh @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub; diff --git a/test_regress/t/t_lint_warn_line_bad.py b/test_regress/t/t_lint_warn_line_bad.py index 1add606d3..a65555478 100755 --- a/test_regress/t/t_lint_warn_line_bad.py +++ b/test_regress/t/t_lint_warn_line_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_warn_line_bad.v b/test_regress/t/t_lint_warn_line_bad.v index 0c219e8a7..8a0bee3be 100644 --- a/test_regress/t/t_lint_warn_line_bad.v +++ b/test_regress/t/t_lint_warn_line_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Check that `line `__LINE__ still shows proper warning context diff --git a/test_regress/t/t_lint_width.py b/test_regress/t/t_lint_width.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_lint_width.py +++ b/test_regress/t/t_lint_width.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_width.v b/test_regress/t/t_lint_width.v index 0931dd1b2..ff2c55d58 100644 --- a/test_regress/t/t_lint_width.v +++ b/test_regress/t/t_lint_width.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); @@ -16,6 +16,14 @@ module t (); wire [4:0] neg5 = - five; wire [5:0] neg6 = - five; + wire inc = 1'b1; + wire dec = 1'b1; + wire [4:0] sumd = inc + five; + wire [4:0] sume = five + inc; + wire [4:0] nege = five - dec; + wire [4:0] nsume = five + inc - dec; + wire [4:0] nsumf = five - dec + inc; + // Relatively harmless < or <= compared with something less wide localparam [1:0] THREE = 3; int a; diff --git a/test_regress/t/t_lint_width_arraydecl.py b/test_regress/t/t_lint_width_arraydecl.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_lint_width_arraydecl.py +++ b/test_regress/t/t_lint_width_arraydecl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_width_arraydecl.v b/test_regress/t/t_lint_width_arraydecl.v index 7a6438621..e11d737df 100644 --- a/test_regress/t/t_lint_width_arraydecl.v +++ b/test_regress/t/t_lint_width_arraydecl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 localparam UADDR_WIDTH = 4'd10; diff --git a/test_regress/t/t_lint_width_bad.py b/test_regress/t/t_lint_width_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_width_bad.py +++ b/test_regress/t/t_lint_width_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_width_bad.v b/test_regress/t/t_lint_width_bad.v index 4e6affbc7..9c004f754 100644 --- a/test_regress/t/t_lint_width_bad.v +++ b/test_regress/t/t_lint_width_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_width_cast.py b/test_regress/t/t_lint_width_cast.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_lint_width_cast.py +++ b/test_regress/t/t_lint_width_cast.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_width_cast.v b/test_regress/t/t_lint_width_cast.v index d05151cda..15883ea97 100644 --- a/test_regress/t/t_lint_width_cast.v +++ b/test_regress/t/t_lint_width_cast.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_lint_width_genfor.py b/test_regress/t/t_lint_width_genfor.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_lint_width_genfor.py +++ b/test_regress/t/t_lint_width_genfor.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_width_genfor.v b/test_regress/t/t_lint_width_genfor.v index 92241350d..3ba744748 100644 --- a/test_regress/t/t_lint_width_genfor.v +++ b/test_regress/t/t_lint_width_genfor.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_width_genfor_bad.py b/test_regress/t/t_lint_width_genfor_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_lint_width_genfor_bad.py +++ b/test_regress/t/t_lint_width_genfor_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_width_genfor_bad.v b/test_regress/t/t_lint_width_genfor_bad.v index 4463ccf71..b0aa12ec5 100644 --- a/test_regress/t/t_lint_width_genfor_bad.v +++ b/test_regress/t/t_lint_width_genfor_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_lint_width_shift_bad.py b/test_regress/t/t_lint_width_shift_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_lint_width_shift_bad.py +++ b/test_regress/t/t_lint_width_shift_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_width_shift_bad.v b/test_regress/t/t_lint_width_shift_bad.v index 7cb1bfbfb..007ac282d 100644 --- a/test_regress/t/t_lint_width_shift_bad.v +++ b/test_regress/t/t_lint_width_shift_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_lint_widthexpand_docs_bad.py b/test_regress/t/t_lint_widthexpand_docs_bad.py index 3c604cd18..9af3b8485 100755 --- a/test_regress/t/t_lint_widthexpand_docs_bad.py +++ b/test_regress/t/t_lint_widthexpand_docs_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lint_widthexpand_docs_bad.v b/test_regress/t/t_lint_widthexpand_docs_bad.v index 896a6d389..f370a7d78 100644 --- a/test_regress/t/t_lint_widthexpand_docs_bad.v +++ b/test_regress/t/t_lint_widthexpand_docs_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lparam_assign_iface_array_typedef.py b/test_regress/t/t_lparam_assign_iface_array_typedef.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_array_typedef.py +++ b/test_regress/t/t_lparam_assign_iface_array_typedef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_array_typedef.v b/test_regress/t/t_lparam_assign_iface_array_typedef.v index 1a8722e92..aa4c8750d 100644 --- a/test_regress/t/t_lparam_assign_iface_array_typedef.v +++ b/test_regress/t/t_lparam_assign_iface_array_typedef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_lparam_assign_iface_array_typedef2.py b/test_regress/t/t_lparam_assign_iface_array_typedef2.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_array_typedef2.py +++ b/test_regress/t/t_lparam_assign_iface_array_typedef2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_array_typedef2.v b/test_regress/t/t_lparam_assign_iface_array_typedef2.v index 0eafeb872..4c53af06a 100644 --- a/test_regress/t/t_lparam_assign_iface_array_typedef2.v +++ b/test_regress/t/t_lparam_assign_iface_array_typedef2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_lparam_assign_iface_typedef.py b/test_regress/t/t_lparam_assign_iface_typedef.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef.py +++ b/test_regress/t/t_lparam_assign_iface_typedef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef.v b/test_regress/t/t_lparam_assign_iface_typedef.v index 169bdbaff..eb527f398 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef.v +++ b/test_regress/t/t_lparam_assign_iface_typedef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting diff --git a/test_regress/t/t_lparam_assign_iface_typedef2.py b/test_regress/t/t_lparam_assign_iface_typedef2.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef2.py +++ b/test_regress/t/t_lparam_assign_iface_typedef2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef2.v b/test_regress/t/t_lparam_assign_iface_typedef2.v index 7bebb16cc..0973695e8 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // @@ -18,6 +18,7 @@ module top (); localparam type p0_t = if0.rq_t; initial begin + if ($bits(p0_t) != 8) $stop; #1; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_lparam_assign_iface_typedef3.py b/test_regress/t/t_lparam_assign_iface_typedef3.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef3.py +++ b/test_regress/t/t_lparam_assign_iface_typedef3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef3.v b/test_regress/t/t_lparam_assign_iface_typedef3.v index 4f95854b8..da536e3a2 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting diff --git a/test_regress/t/t_lparam_assign_iface_typedef4.py b/test_regress/t/t_lparam_assign_iface_typedef4.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef4.v b/test_regress/t/t_lparam_assign_iface_typedef4.v new file mode 100644 index 000000000..09a112a88 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef4.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 +// + +interface x_if #( + parameter int a_width = 3 +) (); + + typedef struct packed {logic [a_width-1:0] addr;} rq_t; +endinterface + +module top (); + x_if #(.a_width(8)) if0 (); + + localparam type p0_t = if0.rq_t[1:0]; + + initial begin + if ($bits(p0_t) != 16) $stop; + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested.py b/test_regress/t/t_lparam_assign_iface_typedef_nested.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested.v b/test_regress/t/t_lparam_assign_iface_typedef_nested.v index 3fa06a292..65db21dd1 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign localparam from nested interface typedef diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested2.py b/test_regress/t/t_lparam_assign_iface_typedef_nested2.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested2.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested2.v b/test_regress/t/t_lparam_assign_iface_typedef_nested2.v index 3670a3e58..8cc63cd26 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign localparam from nested interface typedef diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested3.py b/test_regress/t/t_lparam_assign_iface_typedef_nested3.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested3.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested3.v b/test_regress/t/t_lparam_assign_iface_typedef_nested3.v index 244901b6e..634282662 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign multiple localparams from interface typedef diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested4.py b/test_regress/t/t_lparam_assign_iface_typedef_nested4.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested4.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested4.v b/test_regress/t/t_lparam_assign_iface_typedef_nested4.v index a5fe6288c..cce59e1c4 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested4.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign multiple localparams from interface typedef diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested5.py b/test_regress/t/t_lparam_assign_iface_typedef_nested5.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested5.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested5.v b/test_regress/t/t_lparam_assign_iface_typedef_nested5.v index cfb0cde7f..7179a0685 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested5.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign multiple localparams from interface typedef diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested6.py b/test_regress/t/t_lparam_assign_iface_typedef_nested6.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested6.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested6.v b/test_regress/t/t_lparam_assign_iface_typedef_nested6.v index c53c5a299..c92042da6 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested6.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign localparam from nested interface typedef diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.v similarity index 91% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules.v rename to test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.v index fea53a1fc..d34a43490 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // localparam assignment from interface typedef with module diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.v similarity index 95% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.v rename to test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.v index d6722ebce..56f0e8b33 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // localparam assignment from interface typedef with module diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules3.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.v similarity index 95% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules3.v rename to test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.v index fe82ad430..403e8587a 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign multiple localparams from interface typedef diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg2.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg2.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg2.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg3.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg3.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg3.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg4.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg4.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg4.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg5.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg5.py deleted file mode 100755 index c6e56559a..000000000 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg5.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--binary"]) - -test.execute() - -test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.v similarity index 95% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.v rename to test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.v index 86fdaaf83..23d299d47 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // localparam assignment from interface typedef with module diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg2.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg2.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg2.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg2.v similarity index 92% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg2.v rename to test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg2.v index 2a8343002..ee2591e07 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // Simplified version of config struct to pass params to module diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg3.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.v similarity index 93% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg3.v rename to test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.v index 7a477a510..9f958eb6c 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // Simplified version of config struct to pass params to module diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg4.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.v similarity index 93% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg4.v rename to test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.v index 3f03f7e9d..e20bd1181 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg4.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg5.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.v similarity index 93% rename from test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg5.v rename to test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.v index 72435789e..8b975ec87 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_modules_pkg5.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v index 23b8c1422..0249ac563 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign multiple localparams from interface typedef diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.v index 8bd1c7c49..fa74452ed 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign multiple localparams from interface typedef diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.py b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.py +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.v index f9536da4a..7082650a1 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // diff --git a/test_regress/t/t_mailbox.py b/test_regress/t/t_mailbox.py index b2249f588..72b5f8d81 100755 --- a/test_regress/t/t_mailbox.py +++ b/test_regress/t/t_mailbox.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mailbox.v b/test_regress/t/t_mailbox.v index 0921acb5b..f6913ca89 100644 --- a/test_regress/t/t_mailbox.v +++ b/test_regress/t/t_mailbox.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: diff --git a/test_regress/t/t_mailbox_array.py b/test_regress/t/t_mailbox_array.py index 4839f3e66..1af568d44 100755 --- a/test_regress/t/t_mailbox_array.py +++ b/test_regress/t/t_mailbox_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mailbox_array.v b/test_regress/t/t_mailbox_array.v index 0917b3cc1..f4d753e82 100644 --- a/test_regress/t/t_mailbox_array.v +++ b/test_regress/t/t_mailbox_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_mailbox_bad.py b/test_regress/t/t_mailbox_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_mailbox_bad.py +++ b/test_regress/t/t_mailbox_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mailbox_bad.v b/test_regress/t/t_mailbox_bad.v index 0f32e04d6..a3166be6c 100644 --- a/test_regress/t/t_mailbox_bad.v +++ b/test_regress/t/t_mailbox_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_mailbox_class.py b/test_regress/t/t_mailbox_class.py index 619878281..e6fe26a20 100755 --- a/test_regress/t/t_mailbox_class.py +++ b/test_regress/t/t_mailbox_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mailbox_class.v b/test_regress/t/t_mailbox_class.v index 31619225c..83ea99d62 100644 --- a/test_regress/t/t_mailbox_class.v +++ b/test_regress/t/t_mailbox_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class mailbox_cls #(type T=int); diff --git a/test_regress/t/t_mailbox_concurrent.py b/test_regress/t/t_mailbox_concurrent.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_mailbox_concurrent.py +++ b/test_regress/t/t_mailbox_concurrent.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mailbox_concurrent.v b/test_regress/t/t_mailbox_concurrent.v index d23f099e5..a719cfaf5 100644 --- a/test_regress/t/t_mailbox_concurrent.v +++ b/test_regress/t/t_mailbox_concurrent.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Liam Braun. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Liam Braun // SPDX-License-Identifier: CC0-1.0 module t(); diff --git a/test_regress/t/t_mailbox_notiming.py b/test_regress/t/t_mailbox_notiming.py index e504226e4..5a1059281 100755 --- a/test_regress/t/t_mailbox_notiming.py +++ b/test_regress/t/t_mailbox_notiming.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mailbox_notiming.v b/test_regress/t/t_mailbox_notiming.v index f081d12d5..a6435eeab 100644 --- a/test_regress/t/t_mailbox_notiming.v +++ b/test_regress/t/t_mailbox_notiming.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: diff --git a/test_regress/t/t_mailbox_std.py b/test_regress/t/t_mailbox_std.py index dd4ee7dba..5bacf05bf 100755 --- a/test_regress/t/t_mailbox_std.py +++ b/test_regress/t/t_mailbox_std.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mailbox_unbounded.py b/test_regress/t/t_mailbox_unbounded.py index b2249f588..72b5f8d81 100755 --- a/test_regress/t/t_mailbox_unbounded.py +++ b/test_regress/t/t_mailbox_unbounded.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mailbox_unbounded.v b/test_regress/t/t_mailbox_unbounded.v index 4168321ae..a7799ad25 100644 --- a/test_regress/t/t_mailbox_unbounded.v +++ b/test_regress/t/t_mailbox_unbounded.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 // verilator lint_off DECLFILENAME diff --git a/test_regress/t/t_math_arith.py b/test_regress/t/t_math_arith.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_arith.py +++ b/test_regress/t/t_math_arith.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_arith.v b/test_regress/t/t_math_arith.v index f27cf7279..ccb474d43 100644 --- a/test_regress/t/t_math_arith.v +++ b/test_regress/t/t_math_arith.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_clog2.py b/test_regress/t/t_math_clog2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_clog2.py +++ b/test_regress/t/t_math_clog2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_clog2.v b/test_regress/t/t_math_clog2.v index 2e41ac317..a2400a719 100644 --- a/test_regress/t/t_math_clog2.v +++ b/test_regress/t/t_math_clog2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef verilator diff --git a/test_regress/t/t_math_cmp.py b/test_regress/t/t_math_cmp.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_cmp.py +++ b/test_regress/t/t_math_cmp.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_cmp.v b/test_regress/t/t_math_cmp.v index a142809d9..19353d964 100644 --- a/test_regress/t/t_math_cmp.v +++ b/test_regress/t/t_math_cmp.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_concat.py b/test_regress/t/t_math_concat.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_concat.py +++ b/test_regress/t/t_math_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_concat.v b/test_regress/t/t_math_concat.v index e452078be..efa13e6f8 100644 --- a/test_regress/t/t_math_concat.v +++ b/test_regress/t/t_math_concat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_concat0.py b/test_regress/t/t_math_concat0.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_concat0.py +++ b/test_regress/t/t_math_concat0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_concat0.v b/test_regress/t/t_math_concat0.v index 0f59bbcf0..5234f74f6 100644 --- a/test_regress/t/t_math_concat0.v +++ b/test_regress/t/t_math_concat0.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_concat64.py b/test_regress/t/t_math_concat64.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_concat64.py +++ b/test_regress/t/t_math_concat64.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_concat64.v b/test_regress/t/t_math_concat64.v index c885567c4..6a38e92ba 100644 --- a/test_regress/t/t_math_concat64.v +++ b/test_regress/t/t_math_concat64.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_cond_clean.py b/test_regress/t/t_math_cond_clean.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_cond_clean.py +++ b/test_regress/t/t_math_cond_clean.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_cond_clean.v b/test_regress/t/t_math_cond_clean.v index 3c05b9dbf..c195ee89b 100644 --- a/test_regress/t/t_math_cond_clean.v +++ b/test_regress/t/t_math_cond_clean.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_cond_huge.py b/test_regress/t/t_math_cond_huge.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_cond_huge.py +++ b/test_regress/t/t_math_cond_huge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_cond_huge.v b/test_regress/t/t_math_cond_huge.v index 4864b982c..6f4c58340 100644 --- a/test_regress/t/t_math_cond_huge.v +++ b/test_regress/t/t_math_cond_huge.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_cond_huge_noexpand.py b/test_regress/t/t_math_cond_huge_noexpand.py index fe079527b..47c1a25c1 100755 --- a/test_regress/t/t_math_cond_huge_noexpand.py +++ b/test_regress/t/t_math_cond_huge_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_const.py b/test_regress/t/t_math_const.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_const.py +++ b/test_regress/t/t_math_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_const.v b/test_regress/t/t_math_const.v index 79b0b65fc..7c35a891c 100644 --- a/test_regress/t/t_math_const.v +++ b/test_regress/t/t_math_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_countbits.py b/test_regress/t/t_math_countbits.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_countbits.py +++ b/test_regress/t/t_math_countbits.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_countbits.v b/test_regress/t/t_math_countbits.v index 04e7a512f..24818ddfa 100644 --- a/test_regress/t/t_math_countbits.v +++ b/test_regress/t/t_math_countbits.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Yossi Nivin. +// SPDX-FileCopyrightText: 2020 Yossi Nivin // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_math_countbits2_bad.py b/test_regress/t/t_math_countbits2_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_math_countbits2_bad.py +++ b/test_regress/t/t_math_countbits2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_countbits2_bad.v b/test_regress/t/t_math_countbits2_bad.v index bbbb2a215..65254bb0e 100644 --- a/test_regress/t/t_math_countbits2_bad.v +++ b/test_regress/t/t_math_countbits2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_countbits_bad.py b/test_regress/t/t_math_countbits_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_math_countbits_bad.py +++ b/test_regress/t/t_math_countbits_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_countbits_bad.v b/test_regress/t/t_math_countbits_bad.v index 0cf10d11b..97237eaed 100644 --- a/test_regress/t/t_math_countbits_bad.v +++ b/test_regress/t/t_math_countbits_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Yossi Nivin. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Yossi Nivin // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_countbits_tri.py b/test_regress/t/t_math_countbits_tri.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_math_countbits_tri.py +++ b/test_regress/t/t_math_countbits_tri.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_countbits_tri.v b/test_regress/t/t_math_countbits_tri.v index 421ce6e5d..79c4a77b4 100644 --- a/test_regress/t/t_math_countbits_tri.v +++ b/test_regress/t/t_math_countbits_tri.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_math_cv_bitop.py b/test_regress/t/t_math_cv_bitop.py index dcb1ff476..4641abd21 100755 --- a/test_regress/t/t_math_cv_bitop.py +++ b/test_regress/t/t_math_cv_bitop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_cv_bitop.v b/test_regress/t/t_math_cv_bitop.v index e5ba80fd4..06ccd2386 100644 --- a/test_regress/t/t_math_cv_bitop.v +++ b/test_regress/t/t_math_cv_bitop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_math_cv_concat.py b/test_regress/t/t_math_cv_concat.py index 4ff66dda6..bf473484c 100755 --- a/test_regress/t/t_math_cv_concat.py +++ b/test_regress/t/t_math_cv_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_cv_concat.v b/test_regress/t/t_math_cv_concat.v index cbecf25f6..60d88be0b 100644 --- a/test_regress/t/t_math_cv_concat.v +++ b/test_regress/t/t_math_cv_concat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_math_cv_format.py b/test_regress/t/t_math_cv_format.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_math_cv_format.py +++ b/test_regress/t/t_math_cv_format.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_cv_format.v b/test_regress/t/t_math_cv_format.v index ddb6661d6..650c6f168 100644 --- a/test_regress/t/t_math_cv_format.v +++ b/test_regress/t/t_math_cv_format.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_math_div.py b/test_regress/t/t_math_div.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_div.py +++ b/test_regress/t/t_math_div.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_div.v b/test_regress/t/t_math_div.v index 644f06939..0656f6db7 100644 --- a/test_regress/t/t_math_div.v +++ b/test_regress/t/t_math_div.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_div0.py b/test_regress/t/t_math_div0.py index 1c1006dc8..2b64bb43a 100755 --- a/test_regress/t/t_math_div0.py +++ b/test_regress/t/t_math_div0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_div0.v b/test_regress/t/t_math_div0.v index 2612c5fb4..22f5a41f9 100644 --- a/test_regress/t/t_math_div0.v +++ b/test_regress/t/t_math_div0.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_math_div_noexpand.py b/test_regress/t/t_math_div_noexpand.py index 59a7dbcac..b7466ff27 100755 --- a/test_regress/t/t_math_div_noexpand.py +++ b/test_regress/t/t_math_div_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_divw.py b/test_regress/t/t_math_divw.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_divw.py +++ b/test_regress/t/t_math_divw.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_divw.v b/test_regress/t/t_math_divw.v index e96b50467..9406748f8 100644 --- a/test_regress/t/t_math_divw.v +++ b/test_regress/t/t_math_divw.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_eq.py b/test_regress/t/t_math_eq.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_eq.py +++ b/test_regress/t/t_math_eq.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_eq.v b/test_regress/t/t_math_eq.v index 018f190c7..fe73d3314 100644 --- a/test_regress/t/t_math_eq.v +++ b/test_regress/t/t_math_eq.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_math_eq_bad.py b/test_regress/t/t_math_eq_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_math_eq_bad.py +++ b/test_regress/t/t_math_eq_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_eq_bad.v b/test_regress/t/t_math_eq_bad.v index 941519a74..095d1dd26 100644 --- a/test_regress/t/t_math_eq_bad.v +++ b/test_regress/t/t_math_eq_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_eq_noexpand.py b/test_regress/t/t_math_eq_noexpand.py index 9ee292fb7..01bfdfdb6 100755 --- a/test_regress/t/t_math_eq_noexpand.py +++ b/test_regress/t/t_math_eq_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_equal.py b/test_regress/t/t_math_equal.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_equal.py +++ b/test_regress/t/t_math_equal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_equal.v b/test_regress/t/t_math_equal.v index dee162e01..3dfa5b579 100644 --- a/test_regress/t/t_math_equal.v +++ b/test_regress/t/t_math_equal.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_imm.py b/test_regress/t/t_math_imm.py index 539f320b1..84c09a3bb 100755 --- a/test_regress/t/t_math_imm.py +++ b/test_regress/t/t_math_imm.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_imm.v b/test_regress/t/t_math_imm.v index d5884e806..0c77528f2 100644 --- a/test_regress/t/t_math_imm.v +++ b/test_regress/t/t_math_imm.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // Example module to create problem. diff --git a/test_regress/t/t_math_imm2.cpp b/test_regress/t/t_math_imm2.cpp index 37cafbf37..ce282fe8d 100644 --- a/test_regress/t/t_math_imm2.cpp +++ b/test_regress/t/t_math_imm2.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_math_imm2.py b/test_regress/t/t_math_imm2.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_math_imm2.py +++ b/test_regress/t/t_math_imm2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_imm2.v b/test_regress/t/t_math_imm2.v index 57476f385..79ff28c2e 100644 --- a/test_regress/t/t_math_imm2.v +++ b/test_regress/t/t_math_imm2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // Example module to create problem. diff --git a/test_regress/t/t_math_insert_bound.py b/test_regress/t/t_math_insert_bound.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_insert_bound.py +++ b/test_regress/t/t_math_insert_bound.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_insert_bound.v b/test_regress/t/t_math_insert_bound.v index 5ddb940d4..3937a3919 100644 --- a/test_regress/t/t_math_insert_bound.v +++ b/test_regress/t/t_math_insert_bound.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Paul Swirhun. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Paul Swirhun // SPDX-License-Identifier: CC0-1.0 // Demonstrates the bug in https://github.com/verilator/verilator/issues/4850 diff --git a/test_regress/t/t_math_mul.py b/test_regress/t/t_math_mul.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_mul.py +++ b/test_regress/t/t_math_mul.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_mul.v b/test_regress/t/t_math_mul.v index 65d92878a..d93eb8950 100644 --- a/test_regress/t/t_math_mul.v +++ b/test_regress/t/t_math_mul.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_pick.py b/test_regress/t/t_math_pick.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_pick.py +++ b/test_regress/t/t_math_pick.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_pick.v b/test_regress/t/t_math_pick.v index 0908ed8a1..697166233 100644 --- a/test_regress/t/t_math_pick.v +++ b/test_regress/t/t_math_pick.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2013 // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_pow.py b/test_regress/t/t_math_pow.py index 774a16957..4b2bfc513 100755 --- a/test_regress/t/t_math_pow.py +++ b/test_regress/t/t_math_pow.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_pow.v b/test_regress/t/t_math_pow.v index e1c4f73eb..0fc280c26 100644 --- a/test_regress/t/t_math_pow.v +++ b/test_regress/t/t_math_pow.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_math_pow2.py b/test_regress/t/t_math_pow2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_pow2.py +++ b/test_regress/t/t_math_pow2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_pow2.v b/test_regress/t/t_math_pow2.v index 7cd74413e..d5315a1da 100644 --- a/test_regress/t/t_math_pow2.v +++ b/test_regress/t/t_math_pow2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_pow3.py b/test_regress/t/t_math_pow3.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_pow3.py +++ b/test_regress/t/t_math_pow3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_pow3.v b/test_regress/t/t_math_pow3.v index aeaba1b0d..db40cc664 100644 --- a/test_regress/t/t_math_pow3.v +++ b/test_regress/t/t_math_pow3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0) diff --git a/test_regress/t/t_math_pow4.py b/test_regress/t/t_math_pow4.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_pow4.py +++ b/test_regress/t/t_math_pow4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_pow4.v b/test_regress/t/t_math_pow4.v index cc3f3bdc2..4052cfb62 100644 --- a/test_regress/t/t_math_pow4.v +++ b/test_regress/t/t_math_pow4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Clifford Wolf. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Clifford Wolf // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_pow5.py b/test_regress/t/t_math_pow5.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_pow5.py +++ b/test_regress/t/t_math_pow5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_pow5.v b/test_regress/t/t_math_pow5.v index f51b99395..861d12176 100644 --- a/test_regress/t/t_math_pow5.v +++ b/test_regress/t/t_math_pow5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_pow6.py b/test_regress/t/t_math_pow6.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_pow6.py +++ b/test_regress/t/t_math_pow6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_pow6.v b/test_regress/t/t_math_pow6.v index af43e5233..37c85e770 100644 --- a/test_regress/t/t_math_pow6.v +++ b/test_regress/t/t_math_pow6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_pow7.cpp b/test_regress/t/t_math_pow7.cpp index 703e10f00..fea8b56d0 100644 --- a/test_regress/t/t_math_pow7.cpp +++ b/test_regress/t/t_math_pow7.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_math_pow7.py b/test_regress/t/t_math_pow7.py index f37ad07c8..b6662862a 100755 --- a/test_regress/t/t_math_pow7.py +++ b/test_regress/t/t_math_pow7.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_pow7.v b/test_regress/t/t_math_pow7.v index 20c2070a2..d94e53835 100644 --- a/test_regress/t/t_math_pow7.v +++ b/test_regress/t/t_math_pow7.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_math_precedence.py b/test_regress/t/t_math_precedence.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_precedence.py +++ b/test_regress/t/t_math_precedence.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_precedence.v b/test_regress/t/t_math_precedence.v index 85d2f48f5..1d0815f15 100644 --- a/test_regress/t/t_math_precedence.v +++ b/test_regress/t/t_math_precedence.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_real.py b/test_regress/t/t_math_real.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_real.py +++ b/test_regress/t/t_math_real.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_real.v b/test_regress/t/t_math_real.v index 6c6ac73e0..39892dbd9 100644 --- a/test_regress/t/t_math_real.v +++ b/test_regress/t/t_math_real.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define stop $stop diff --git a/test_regress/t/t_math_real_private.py b/test_regress/t/t_math_real_private.py index cb7c72226..9bded70c6 100755 --- a/test_regress/t/t_math_real_private.py +++ b/test_regress/t/t_math_real_private.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_real_public.py b/test_regress/t/t_math_real_public.py index d6ccbb8bd..f7e482baa 100755 --- a/test_regress/t/t_math_real_public.py +++ b/test_regress/t/t_math_real_public.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_real_public.v b/test_regress/t/t_math_real_public.v index fec4bdacf..accf2fe02 100644 --- a/test_regress/t/t_math_real_public.v +++ b/test_regress/t/t_math_real_public.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Alex Solomatnikov +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_real_random.py b/test_regress/t/t_math_real_random.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_real_random.py +++ b/test_regress/t/t_math_real_random.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_real_random.v b/test_regress/t/t_math_real_random.v index 46d343054..4e9044a90 100644 --- a/test_regress/t/t_math_real_random.v +++ b/test_regress/t/t_math_real_random.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Wilson Snyder. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_math_real_round.py b/test_regress/t/t_math_real_round.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_real_round.py +++ b/test_regress/t/t_math_real_round.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_real_round.v b/test_regress/t/t_math_real_round.v index 7826fcf9f..1677c0f40 100644 --- a/test_regress/t/t_math_real_round.v +++ b/test_regress/t/t_math_real_round.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) diff --git a/test_regress/t/t_math_red.py b/test_regress/t/t_math_red.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_red.py +++ b/test_regress/t/t_math_red.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_red.v b/test_regress/t/t_math_red.v index c9d9d2b63..a357c471c 100644 --- a/test_regress/t/t_math_red.v +++ b/test_regress/t/t_math_red.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_math_red_noexpand.py b/test_regress/t/t_math_red_noexpand.py index eb44fb046..26f290259 100755 --- a/test_regress/t/t_math_red_noexpand.py +++ b/test_regress/t/t_math_red_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_repl.py b/test_regress/t/t_math_repl.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_repl.py +++ b/test_regress/t/t_math_repl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_repl.v b/test_regress/t/t_math_repl.v index e36b15d49..91c7e1230 100644 --- a/test_regress/t/t_math_repl.v +++ b/test_regress/t/t_math_repl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_repl2_bad.py b/test_regress/t/t_math_repl2_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_math_repl2_bad.py +++ b/test_regress/t/t_math_repl2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_repl2_bad.v b/test_regress/t/t_math_repl2_bad.v index 346dcebde..a1e7048a5 100644 --- a/test_regress/t/t_math_repl2_bad.v +++ b/test_regress/t/t_math_repl2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_math_repl3_bad.py b/test_regress/t/t_math_repl3_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_math_repl3_bad.py +++ b/test_regress/t/t_math_repl3_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_repl3_bad.v b/test_regress/t/t_math_repl3_bad.v index 66192c87e..33c3c8f5a 100644 --- a/test_regress/t/t_math_repl3_bad.v +++ b/test_regress/t/t_math_repl3_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t #( diff --git a/test_regress/t/t_math_repl_bad.py b/test_regress/t/t_math_repl_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_math_repl_bad.py +++ b/test_regress/t/t_math_repl_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_repl_bad.v b/test_regress/t/t_math_repl_bad.v index bb83d9ad5..96ad2981e 100644 --- a/test_regress/t/t_math_repl_bad.v +++ b/test_regress/t/t_math_repl_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_reverse.py b/test_regress/t/t_math_reverse.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_reverse.py +++ b/test_regress/t/t_math_reverse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_reverse.v b/test_regress/t/t_math_reverse.v index 15ee7de62..0cfc3bd1c 100644 --- a/test_regress/t/t_math_reverse.v +++ b/test_regress/t/t_math_reverse.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_shift.py b/test_regress/t/t_math_shift.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_shift.py +++ b/test_regress/t/t_math_shift.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shift.v b/test_regress/t/t_math_shift.v index e8f9379c4..c78333832 100644 --- a/test_regress/t/t_math_shift.v +++ b/test_regress/t/t_math_shift.v @@ -1,12 +1,12 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs - ign, ign2, ign3, ign4, ign4s, + ign, ign2, ign3, c_wright_32, c_wleft_32, ign4, ign4s, // Inputs clk ); @@ -59,6 +59,12 @@ module t (/*AUTOARG*/ reg [63:0] qamt; reg [95:0] wamt; + output reg [95:0] c_wright_32; + output reg [95:0] c_wleft_32; + + reg [63:0] crc = 64'h5aef0c8d_d70a4497; + wire [95:0] rand_96 = {crc[63:32] | crc[31:0], crc}; + assign ign = {31'h0, clk} >>> 4'bx; // bug760 assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174 assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}}, @@ -104,12 +110,16 @@ module t (/*AUTOARG*/ w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt; w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt); w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt; + + c_wright_32 = rand_96 >> 32; + c_wleft_32 = rand_96 << 32; end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; `ifdef TEST_VERBOSE $write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright); `endif @@ -233,6 +243,9 @@ module t (/*AUTOARG*/ if (wleft != w_wleft) $stop; if (wright != w_wright) $stop; if (wrights != w_wrights) $stop; + + if (c_wright_32 << 32 != {rand_96[95:32], 32'd0}) $stop; + if (c_wleft_32 >> 32 != {32'd0, rand_96[63:0]}) $stop; end end end diff --git a/test_regress/t/t_math_shift_extend.py b/test_regress/t/t_math_shift_extend.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_shift_extend.py +++ b/test_regress/t/t_math_shift_extend.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shift_extend.v b/test_regress/t/t_math_shift_extend.v index 787c3afca..43d75aeca 100644 --- a/test_regress/t/t_math_shift_extend.v +++ b/test_regress/t/t_math_shift_extend.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_shift_huge.py b/test_regress/t/t_math_shift_huge.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_math_shift_huge.py +++ b/test_regress/t/t_math_shift_huge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shift_huge.v b/test_regress/t/t_math_shift_huge.v index 900bbc188..51c67da7a 100644 --- a/test_regress/t/t_math_shift_huge.v +++ b/test_regress/t/t_math_shift_huge.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_math_shift_noexpand.py b/test_regress/t/t_math_shift_noexpand.py index 72d3f29af..1e604ddc3 100755 --- a/test_regress/t/t_math_shift_noexpand.py +++ b/test_regress/t/t_math_shift_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shift_rep.py b/test_regress/t/t_math_shift_rep.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_shift_rep.py +++ b/test_regress/t/t_math_shift_rep.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shift_rep.v b/test_regress/t/t_math_shift_rep.v index edfcf059e..5b8921eda 100644 --- a/test_regress/t/t_math_shift_rep.v +++ b/test_regress/t/t_math_shift_rep.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_shift_sel.py b/test_regress/t/t_math_shift_sel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_shift_sel.py +++ b/test_regress/t/t_math_shift_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shift_sel.v b/test_regress/t/t_math_shift_sel.v index 569f3b170..9d6436e9b 100644 --- a/test_regress/t/t_math_shift_sel.v +++ b/test_regress/t/t_math_shift_sel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_shift_side.py b/test_regress/t/t_math_shift_side.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_shift_side.py +++ b/test_regress/t/t_math_shift_side.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shift_side.v b/test_regress/t/t_math_shift_side.v index 46eb2915c..f08c3b414 100644 --- a/test_regress/t/t_math_shift_side.v +++ b/test_regress/t/t_math_shift_side.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_math_shiftls.py b/test_regress/t/t_math_shiftls.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_math_shiftls.py +++ b/test_regress/t/t_math_shiftls.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shiftls.v b/test_regress/t/t_math_shiftls.v index 561a04f6e..eb852e804 100644 --- a/test_regress/t/t_math_shiftls.v +++ b/test_regress/t/t_math_shiftls.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Zhen Yan. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Zhen Yan // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_math_shiftrs.py b/test_regress/t/t_math_shiftrs.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_shiftrs.py +++ b/test_regress/t/t_math_shiftrs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shiftrs.v b/test_regress/t/t_math_shiftrs.v index 1622ebbdb..058e99e5e 100644 --- a/test_regress/t/t_math_shiftrs.v +++ b/test_regress/t/t_math_shiftrs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_shiftrs2.py b/test_regress/t/t_math_shiftrs2.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_math_shiftrs2.py +++ b/test_regress/t/t_math_shiftrs2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shiftrs2.v b/test_regress/t/t_math_shiftrs2.v index 821604679..e239a918c 100644 --- a/test_regress/t/t_math_shiftrs2.v +++ b/test_regress/t/t_math_shiftrs2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_math_shortcircuit_assocsel.py b/test_regress/t/t_math_shortcircuit_assocsel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_shortcircuit_assocsel.py +++ b/test_regress/t/t_math_shortcircuit_assocsel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shortcircuit_assocsel.v b/test_regress/t/t_math_shortcircuit_assocsel.v index c12b80d36..3de494fbb 100644 --- a/test_regress/t/t_math_shortcircuit_assocsel.v +++ b/test_regress/t/t_math_shortcircuit_assocsel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; @@ -24,7 +24,7 @@ module t; return next_nonzero; endfunction initial begin - logic r = f(0); + automatic logic r = f(0); $display(r); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_math_shortcircuit_dynsel.py b/test_regress/t/t_math_shortcircuit_dynsel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_shortcircuit_dynsel.py +++ b/test_regress/t/t_math_shortcircuit_dynsel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shortcircuit_dynsel.v b/test_regress/t/t_math_shortcircuit_dynsel.v index 52b4bf995..164f41e02 100644 --- a/test_regress/t/t_math_shortcircuit_dynsel.v +++ b/test_regress/t/t_math_shortcircuit_dynsel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; @@ -24,7 +24,7 @@ module t; return next_nonzero; endfunction initial begin - logic r = f(0); + automatic logic r = f(0); $display(r); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_math_shortreal.py b/test_regress/t/t_math_shortreal.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_shortreal.py +++ b/test_regress/t/t_math_shortreal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shortreal.v b/test_regress/t/t_math_shortreal.v index faf30f99a..0e525b14d 100644 --- a/test_regress/t/t_math_shortreal.v +++ b/test_regress/t/t_math_shortreal.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) diff --git a/test_regress/t/t_math_shortreal_unsup_bad.py b/test_regress/t/t_math_shortreal_unsup_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_math_shortreal_unsup_bad.py +++ b/test_regress/t/t_math_shortreal_unsup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_shortreal_unsup_bad.v b/test_regress/t/t_math_shortreal_unsup_bad.v index 2e13b26d4..e01f6b63f 100644 --- a/test_regress/t/t_math_shortreal_unsup_bad.v +++ b/test_regress/t/t_math_shortreal_unsup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_sign_extend.py b/test_regress/t/t_math_sign_extend.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_sign_extend.py +++ b/test_regress/t/t_math_sign_extend.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_sign_extend.v b/test_regress/t/t_math_sign_extend.v index fd00fc46b..ddbd5972f 100644 --- a/test_regress/t/t_math_sign_extend.v +++ b/test_regress/t/t_math_sign_extend.v @@ -3,8 +3,8 @@ // This test demonstrates an issue with sign extension. // Assigning to localparms larger than 32 bits broke in 3.862 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Mike Thyer. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Mike Thyer // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_signed.py b/test_regress/t/t_math_signed.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_signed.py +++ b/test_regress/t/t_math_signed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed.v b/test_regress/t/t_math_signed.v index 7adf78026..1b51c6f16 100644 --- a/test_regress/t/t_math_signed.v +++ b/test_regress/t/t_math_signed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_signed2.py b/test_regress/t/t_math_signed2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_signed2.py +++ b/test_regress/t/t_math_signed2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed2.v b/test_regress/t/t_math_signed2.v index edfb02686..560686be1 100644 --- a/test_regress/t/t_math_signed2.v +++ b/test_regress/t/t_math_signed2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Peter Debacker. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Peter Debacker // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_signed3.py b/test_regress/t/t_math_signed3.py index 5579de2ce..8a4d632f3 100755 --- a/test_regress/t/t_math_signed3.py +++ b/test_regress/t/t_math_signed3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed3.v b/test_regress/t/t_math_signed3.v index 98d008aaf..e136f6498 100644 --- a/test_regress/t/t_math_signed3.v +++ b/test_regress/t/t_math_signed3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_math_signed3_noopt.py b/test_regress/t/t_math_signed3_noopt.py index d3177f773..1903e42f5 100755 --- a/test_regress/t/t_math_signed3_noopt.py +++ b/test_regress/t/t_math_signed3_noopt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed4.py b/test_regress/t/t_math_signed4.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_signed4.py +++ b/test_regress/t/t_math_signed4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed4.v b/test_regress/t/t_math_signed4.v index 30e267209..1cf044432 100644 --- a/test_regress/t/t_math_signed4.v +++ b/test_regress/t/t_math_signed4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) diff --git a/test_regress/t/t_math_signed5.py b/test_regress/t/t_math_signed5.py index 46560bc9c..346ef8602 100755 --- a/test_regress/t/t_math_signed5.py +++ b/test_regress/t/t_math_signed5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed5.v b/test_regress/t/t_math_signed5.v index b4c2b9ca0..300ce5e92 100644 --- a/test_regress/t/t_math_signed5.v +++ b/test_regress/t/t_math_signed5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) diff --git a/test_regress/t/t_math_signed5_timing.py b/test_regress/t/t_math_signed5_timing.py index cbfc15a4b..3b2dd3bcc 100755 --- a/test_regress/t/t_math_signed5_timing.py +++ b/test_regress/t/t_math_signed5_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed6.py b/test_regress/t/t_math_signed6.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_signed6.py +++ b/test_regress/t/t_math_signed6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed6.v b/test_regress/t/t_math_signed6.v index 891823838..db22170bf 100644 --- a/test_regress/t/t_math_signed6.v +++ b/test_regress/t/t_math_signed6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_math_signed7.py b/test_regress/t/t_math_signed7.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_signed7.py +++ b/test_regress/t/t_math_signed7.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed7.v b/test_regress/t/t_math_signed7.v index ac31749a5..0752ba9ba 100644 --- a/test_regress/t/t_math_signed7.v +++ b/test_regress/t/t_math_signed7.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_math_signed_calc.py b/test_regress/t/t_math_signed_calc.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_signed_calc.py +++ b/test_regress/t/t_math_signed_calc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed_calc.v b/test_regress/t/t_math_signed_calc.v index e89562a81..44f9329bd 100644 --- a/test_regress/t/t_math_signed_calc.v +++ b/test_regress/t/t_math_signed_calc.v @@ -3,8 +3,8 @@ // This mode performs signed number computations in the case of a particular // interface definition. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Raynard Qiao. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Raynard Qiao // SPDX-License-Identifier: CC0-1.0 // issure 3294 diff --git a/test_regress/t/t_math_signed_noexpand.py b/test_regress/t/t_math_signed_noexpand.py index 52c2b4c7a..c374a73cb 100755 --- a/test_regress/t/t_math_signed_noexpand.py +++ b/test_regress/t/t_math_signed_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed_wire.py b/test_regress/t/t_math_signed_wire.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_signed_wire.py +++ b/test_regress/t/t_math_signed_wire.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_signed_wire.v b/test_regress/t/t_math_signed_wire.v index 806044ddd..a617bd695 100644 --- a/test_regress/t/t_math_signed_wire.v +++ b/test_regress/t/t_math_signed_wire.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug511 diff --git a/test_regress/t/t_math_strwidth.py b/test_regress/t/t_math_strwidth.py index 272dabc9b..5216a1f34 100755 --- a/test_regress/t/t_math_strwidth.py +++ b/test_regress/t/t_math_strwidth.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_strwidth.v b/test_regress/t/t_math_strwidth.v index c03bd9375..17fba34a6 100644 --- a/test_regress/t/t_math_strwidth.v +++ b/test_regress/t/t_math_strwidth.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008-2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008-2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_svl.py b/test_regress/t/t_math_svl.py index f5ff115eb..7c9216f0e 100755 --- a/test_regress/t/t_math_svl.py +++ b/test_regress/t/t_math_svl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_svl.v b/test_regress/t/t_math_svl.v index 260e46a3e..568e94980 100644 --- a/test_regress/t/t_math_svl.v +++ b/test_regress/t/t_math_svl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_svl2.py b/test_regress/t/t_math_svl2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_svl2.py +++ b/test_regress/t/t_math_svl2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_svl2.v b/test_regress/t/t_math_svl2.v index ccd1a1c7a..8159f586e 100644 --- a/test_regress/t/t_math_svl2.v +++ b/test_regress/t/t_math_svl2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_swap.py b/test_regress/t/t_math_swap.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_swap.py +++ b/test_regress/t/t_math_swap.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_swap.v b/test_regress/t/t_math_swap.v index 7a0ab5dee..189ba4c51 100644 --- a/test_regress/t/t_math_swap.v +++ b/test_regress/t/t_math_swap.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_synmul.py b/test_regress/t/t_math_synmul.py index 153317c33..7f09b9e2c 100755 --- a/test_regress/t/t_math_synmul.py +++ b/test_regress/t/t_math_synmul.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_synmul.v b/test_regress/t/t_math_synmul.v index 9d69de9b9..f8d2098a2 100644 --- a/test_regress/t/t_math_synmul.v +++ b/test_regress/t/t_math_synmul.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_math_synmul_mul.v b/test_regress/t/t_math_synmul_mul.v index 1d199fdb2..14a3388fa 100644 --- a/test_regress/t/t_math_synmul_mul.v +++ b/test_regress/t/t_math_synmul_mul.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Mahesh Kumashikar +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Mahesh Kumashikar // SPDX-License-Identifier: CC0-1.0 module t_math_synmul_mul (/*AUTOARG*/ diff --git a/test_regress/t/t_math_tri.py b/test_regress/t/t_math_tri.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_tri.py +++ b/test_regress/t/t_math_tri.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_tri.v b/test_regress/t/t_math_tri.v index 462a430c6..38d20e5fb 100644 --- a/test_regress/t/t_math_tri.v +++ b/test_regress/t/t_math_tri.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_math_trig.py b/test_regress/t/t_math_trig.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_trig.py +++ b/test_regress/t/t_math_trig.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_trig.v b/test_regress/t/t_math_trig.v index 91e9d3066..b94ab5a98 100644 --- a/test_regress/t/t_math_trig.v +++ b/test_regress/t/t_math_trig.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_vgen.py b/test_regress/t/t_math_vgen.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_vgen.py +++ b/test_regress/t/t_math_vgen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_vgen.v b/test_regress/t/t_math_vgen.v index c2b0f7720..783ce5d2f 100644 --- a/test_regress/t/t_math_vgen.v +++ b/test_regress/t/t_math_vgen.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_vliw.py b/test_regress/t/t_math_vliw.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_vliw.py +++ b/test_regress/t/t_math_vliw.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_vliw.v b/test_regress/t/t_math_vliw.v index 4aa2d26e1..316d697f1 100644 --- a/test_regress/t/t_math_vliw.v +++ b/test_regress/t/t_math_vliw.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_vliw_noexpand.py b/test_regress/t/t_math_vliw_noexpand.py index ca6a4fa58..504aca69c 100755 --- a/test_regress/t/t_math_vliw_noexpand.py +++ b/test_regress/t/t_math_vliw_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_wallace.py b/test_regress/t/t_math_wallace.py index f64ff6ad9..c8511382a 100755 --- a/test_regress/t/t_math_wallace.py +++ b/test_regress/t/t_math_wallace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_wallace.v b/test_regress/t/t_math_wallace.v index 31cf9a460..5d809a2fc 100644 --- a/test_regress/t/t_math_wallace.v +++ b/test_regress/t/t_math_wallace.v @@ -1,8 +1,8 @@ // -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_math_wallace_mul.v b/test_regress/t/t_math_wallace_mul.v index 75a67dfc4..f32705ff1 100644 --- a/test_regress/t/t_math_wallace_mul.v +++ b/test_regress/t/t_math_wallace_mul.v @@ -1,8 +1,8 @@ // -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_math_wallace_mul ( /*AUTOARG*/ diff --git a/test_regress/t/t_math_wide_bad.py b/test_regress/t/t_math_wide_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_math_wide_bad.py +++ b/test_regress/t/t_math_wide_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_wide_bad.v b/test_regress/t/t_math_wide_bad.v index 2f54d5456..75892c1a1 100644 --- a/test_regress/t/t_math_wide_bad.v +++ b/test_regress/t/t_math_wide_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_wide_inc.py b/test_regress/t/t_math_wide_inc.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_wide_inc.py +++ b/test_regress/t/t_math_wide_inc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_wide_inc.v b/test_regress/t/t_math_wide_inc.v index 1d62ca03f..c49ba93e5 100644 --- a/test_regress/t/t_math_wide_inc.v +++ b/test_regress/t/t_math_wide_inc.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_width.py b/test_regress/t/t_math_width.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_width.py +++ b/test_regress/t/t_math_width.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_width.v b/test_regress/t/t_math_width.v index a9ba18780..d53ae51eb 100644 --- a/test_regress/t/t_math_width.v +++ b/test_regress/t/t_math_width.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_math_yosys.py b/test_regress/t/t_math_yosys.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_math_yosys.py +++ b/test_regress/t/t_math_yosys.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_math_yosys.v b/test_regress/t/t_math_yosys.v index 9e14a38f6..fd7041417 100644 --- a/test_regress/t/t_math_yosys.v +++ b/test_regress/t/t_math_yosys.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Claire Wolf. +// SPDX-FileCopyrightText: 2020 Claire Wolf // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_mem.py b/test_regress/t/t_mem.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem.py +++ b/test_regress/t/t_mem.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem.v b/test_regress/t/t_mem.v index 5baa226a0..4eb216ac2 100644 --- a/test_regress/t/t_mem.v +++ b/test_regress/t/t_mem.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_banks.py b/test_regress/t/t_mem_banks.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_banks.py +++ b/test_regress/t/t_mem_banks.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_banks.v b/test_regress/t/t_mem_banks.v index cef449442..dafe0c590 100644 --- a/test_regress/t/t_mem_banks.v +++ b/test_regress/t/t_mem_banks.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_mem_big_bad.py b/test_regress/t/t_mem_big_bad.py index dece38f4e..c7d9b21a5 100755 --- a/test_regress/t/t_mem_big_bad.py +++ b/test_regress/t/t_mem_big_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_big_bad.v b/test_regress/t/t_mem_big_bad.v index eadfb3f1e..d17e085ab 100644 --- a/test_regress/t/t_mem_big_bad.v +++ b/test_regress/t/t_mem_big_bad.v @@ -1,7 +1,7 @@ // This test shall generate a warning, but not an internal error. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Zhanglei Wang. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Zhanglei Wang // SPDX-License-Identifier: CC0-1.0 module t_bigmem( input wire clk, diff --git a/test_regress/t/t_mem_bound_bad.py b/test_regress/t/t_mem_bound_bad.py index c038d3707..0b18482f0 100755 --- a/test_regress/t/t_mem_bound_bad.py +++ b/test_regress/t/t_mem_bound_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_bound_bad.v b/test_regress/t/t_mem_bound_bad.v index 61919afbe..06d708ead 100644 --- a/test_regress/t/t_mem_bound_bad.v +++ b/test_regress/t/t_mem_bound_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Jie Xu +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Jie Xu // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_mem_cond.py b/test_regress/t/t_mem_cond.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_cond.py +++ b/test_regress/t/t_mem_cond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_cond.v b/test_regress/t/t_mem_cond.v index b5d6f3f63..0c467f030 100644 --- a/test_regress/t/t_mem_cond.v +++ b/test_regress/t/t_mem_cond.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_fifo.py b/test_regress/t/t_mem_fifo.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_fifo.py +++ b/test_regress/t/t_mem_fifo.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_fifo.v b/test_regress/t/t_mem_fifo.v index ca1e13940..7e8817db1 100644 --- a/test_regress/t/t_mem_fifo.v +++ b/test_regress/t/t_mem_fifo.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_file.py b/test_regress/t/t_mem_file.py index a06492309..c996a862c 100755 --- a/test_regress/t/t_mem_file.py +++ b/test_regress/t/t_mem_file.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_file.v b/test_regress/t/t_mem_file.v index 8d9dacb09..2ca91b96f 100644 --- a/test_regress/t/t_mem_file.v +++ b/test_regress/t/t_mem_file.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_first.py b/test_regress/t/t_mem_first.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_first.py +++ b/test_regress/t/t_mem_first.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_first.v b/test_regress/t/t_mem_first.v index dfda7d9cb..bffd25a3c 100644 --- a/test_regress/t/t_mem_first.v +++ b/test_regress/t/t_mem_first.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_func.py b/test_regress/t/t_mem_func.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_func.py +++ b/test_regress/t/t_mem_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_func.v b/test_regress/t/t_mem_func.v index 86cd1f7b2..6376d6a2f 100644 --- a/test_regress/t/t_mem_func.v +++ b/test_regress/t/t_mem_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_iforder.py b/test_regress/t/t_mem_iforder.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_iforder.py +++ b/test_regress/t/t_mem_iforder.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_iforder.v b/test_regress/t/t_mem_iforder.v index 32b56f4a6..37b974ca9 100644 --- a/test_regress/t/t_mem_iforder.v +++ b/test_regress/t/t_mem_iforder.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_multi_io.py b/test_regress/t/t_mem_multi_io.py index ca839f8e4..598ae0253 100755 --- a/test_regress/t/t_mem_multi_io.py +++ b/test_regress/t/t_mem_multi_io.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_multi_io.v b/test_regress/t/t_mem_multi_io.v index 67641c734..b54ce06b6 100644 --- a/test_regress/t/t_mem_multi_io.v +++ b/test_regress/t/t_mem_multi_io.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_multi_io2.cpp b/test_regress/t/t_mem_multi_io2.cpp index 56d37c58f..bb156ce7a 100644 --- a/test_regress/t/t_mem_multi_io2.cpp +++ b/test_regress/t/t_mem_multi_io2.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_mem_multi_io2.v b/test_regress/t/t_mem_multi_io2.v index d43e65d2f..6075899c0 100644 --- a/test_regress/t/t_mem_multi_io2.v +++ b/test_regress/t/t_mem_multi_io2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_multi_io2_cc.py b/test_regress/t/t_mem_multi_io2_cc.py index de38bbd98..c6c932196 100755 --- a/test_regress/t/t_mem_multi_io2_cc.py +++ b/test_regress/t/t_mem_multi_io2_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_multi_io2_sc.py b/test_regress/t/t_mem_multi_io2_sc.py index 25fa435f5..703f7eb10 100755 --- a/test_regress/t/t_mem_multi_io2_sc.py +++ b/test_regress/t/t_mem_multi_io2_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_multi_io3.cpp b/test_regress/t/t_mem_multi_io3.cpp index 8f2b519d9..945326e4c 100644 --- a/test_regress/t/t_mem_multi_io3.cpp +++ b/test_regress/t/t_mem_multi_io3.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_mem_multi_io3.v b/test_regress/t/t_mem_multi_io3.v index 3a70d6e26..ca37f3b13 100644 --- a/test_regress/t/t_mem_multi_io3.v +++ b/test_regress/t/t_mem_multi_io3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2013 // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_mem_multi_io3_cc.py b/test_regress/t/t_mem_multi_io3_cc.py index 4cd1b4166..dc29bdca4 100755 --- a/test_regress/t/t_mem_multi_io3_cc.py +++ b/test_regress/t/t_mem_multi_io3_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_multi_io3_sc.py b/test_regress/t/t_mem_multi_io3_sc.py index 49c0e89c1..de51ff34a 100755 --- a/test_regress/t/t_mem_multi_io3_sc.py +++ b/test_regress/t/t_mem_multi_io3_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_multi_ref_bad.py b/test_regress/t/t_mem_multi_ref_bad.py index 6e8952fd0..516a28fc4 100755 --- a/test_regress/t/t_mem_multi_ref_bad.py +++ b/test_regress/t/t_mem_multi_ref_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_multi_ref_bad.v b/test_regress/t/t_mem_multi_ref_bad.v index 293aad9ae..b66f7a9c0 100644 --- a/test_regress/t/t_mem_multi_ref_bad.v +++ b/test_regress/t/t_mem_multi_ref_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_mem_multidim.py b/test_regress/t/t_mem_multidim.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_multidim.py +++ b/test_regress/t/t_mem_multidim.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_multidim.v b/test_regress/t/t_mem_multidim.v index ca1307553..9ee30eba0 100644 --- a/test_regress/t/t_mem_multidim.v +++ b/test_regress/t/t_mem_multidim.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_multidim_Ox.py b/test_regress/t/t_mem_multidim_Ox.py index 7b2c5a036..cdb59a71a 100755 --- a/test_regress/t/t_mem_multidim_Ox.py +++ b/test_regress/t/t_mem_multidim_Ox.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_multidim_trace.py b/test_regress/t/t_mem_multidim_trace.py index b59d45ff6..7da947d30 100755 --- a/test_regress/t/t_mem_multidim_trace.py +++ b/test_regress/t/t_mem_multidim_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_multiwire.py b/test_regress/t/t_mem_multiwire.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_multiwire.py +++ b/test_regress/t/t_mem_multiwire.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_multiwire.v b/test_regress/t/t_mem_multiwire.v index 15569e2f7..bb033afa8 100644 --- a/test_regress/t/t_mem_multiwire.v +++ b/test_regress/t/t_mem_multiwire.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_packed.py b/test_regress/t/t_mem_packed.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_packed.py +++ b/test_regress/t/t_mem_packed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_packed.v b/test_regress/t/t_mem_packed.v index eb570fc5a..49412fe83 100644 --- a/test_regress/t/t_mem_packed.v +++ b/test_regress/t/t_mem_packed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_packed_assign.py b/test_regress/t/t_mem_packed_assign.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_packed_assign.py +++ b/test_regress/t/t_mem_packed_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_packed_assign.v b/test_regress/t/t_mem_packed_assign.v index 98e5c9112..b6c85b175 100644 --- a/test_regress/t/t_mem_packed_assign.v +++ b/test_regress/t/t_mem_packed_assign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_packed_bad.py b/test_regress/t/t_mem_packed_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_mem_packed_bad.py +++ b/test_regress/t/t_mem_packed_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_packed_bad.v b/test_regress/t/t_mem_packed_bad.v index 386c671e9..440674eac 100644 --- a/test_regress/t/t_mem_packed_bad.v +++ b/test_regress/t/t_mem_packed_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_packed_noexpand.py b/test_regress/t/t_mem_packed_noexpand.py index 0dcc3d32a..839d9ad10 100755 --- a/test_regress/t/t_mem_packed_noexpand.py +++ b/test_regress/t/t_mem_packed_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_shift.py b/test_regress/t/t_mem_shift.py index 7258ac668..4768655a8 100755 --- a/test_regress/t/t_mem_shift.py +++ b/test_regress/t/t_mem_shift.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_shift.v b/test_regress/t/t_mem_shift.v index af523b4fe..668f88dd0 100644 --- a/test_regress/t/t_mem_shift.v +++ b/test_regress/t/t_mem_shift.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_slice.py b/test_regress/t/t_mem_slice.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_slice.py +++ b/test_regress/t/t_mem_slice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_slice.v b/test_regress/t/t_mem_slice.v index 66aa61509..26c7f8b39 100644 --- a/test_regress/t/t_mem_slice.v +++ b/test_regress/t/t_mem_slice.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_slice_bad.py b/test_regress/t/t_mem_slice_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_mem_slice_bad.py +++ b/test_regress/t/t_mem_slice_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_slice_bad.v b/test_regress/t/t_mem_slice_bad.v index 29aa8aaa9..ca5535af9 100644 --- a/test_regress/t/t_mem_slice_bad.v +++ b/test_regress/t/t_mem_slice_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_slice_conc_bad.py b/test_regress/t/t_mem_slice_conc_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_mem_slice_conc_bad.py +++ b/test_regress/t/t_mem_slice_conc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_slice_conc_bad.v b/test_regress/t/t_mem_slice_conc_bad.v index 07b9bc4c2..f5a2f0c71 100644 --- a/test_regress/t/t_mem_slice_conc_bad.v +++ b/test_regress/t/t_mem_slice_conc_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // bug354 diff --git a/test_regress/t/t_mem_slice_dtype_bad.py b/test_regress/t/t_mem_slice_dtype_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_mem_slice_dtype_bad.py +++ b/test_regress/t/t_mem_slice_dtype_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_slice_dtype_bad.v b/test_regress/t/t_mem_slice_dtype_bad.v index 687b2957c..75a28431d 100644 --- a/test_regress/t/t_mem_slice_dtype_bad.v +++ b/test_regress/t/t_mem_slice_dtype_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Alex Solomatnikov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 typedef logic [$clog2(26+1)-1:0] way_cnt_t; diff --git a/test_regress/t/t_mem_slot.cpp b/test_regress/t/t_mem_slot.cpp index 595c2768b..6a6eba92a 100644 --- a/test_regress/t/t_mem_slot.cpp +++ b/test_regress/t/t_mem_slot.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_mem_slot.py b/test_regress/t/t_mem_slot.py index 7b94250d8..eb8f88301 100755 --- a/test_regress/t/t_mem_slot.py +++ b/test_regress/t/t_mem_slot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_slot.v b/test_regress/t/t_mem_slot.v index 63ce7d137..be3ea9de8 100644 --- a/test_regress/t/t_mem_slot.v +++ b/test_regress/t/t_mem_slot.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define RegDel 1 diff --git a/test_regress/t/t_mem_trace_split.py b/test_regress/t/t_mem_trace_split.py index 14fc22b86..cfdafbaff 100755 --- a/test_regress/t/t_mem_trace_split.py +++ b/test_regress/t/t_mem_trace_split.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_trace_split.v b/test_regress/t/t_mem_trace_split.v index 8554ef831..d83f9ab23 100644 --- a/test_regress/t/t_mem_trace_split.v +++ b/test_regress/t/t_mem_trace_split.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Demonstrate complex user typea problem with --x-assign // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mem_twoedge.py b/test_regress/t/t_mem_twoedge.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mem_twoedge.py +++ b/test_regress/t/t_mem_twoedge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mem_twoedge.v b/test_regress/t/t_mem_twoedge.v index c180efbd4..f4618640f 100644 --- a/test_regress/t/t_mem_twoedge.v +++ b/test_regress/t/t_mem_twoedge.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_metacmt_fargs.py b/test_regress/t/t_metacmt_fargs.py index 06454285a..dfeac128d 100755 --- a/test_regress/t/t_metacmt_fargs.py +++ b/test_regress/t/t_metacmt_fargs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_metacmt_fargs.v b/test_regress/t/t_metacmt_fargs.v index 88fd04bb4..c29860879 100644 --- a/test_regress/t/t_metacmt_fargs.v +++ b/test_regress/t/t_metacmt_fargs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator fargs --binary -Wno-WIDTHEXPAND diff --git a/test_regress/t/t_metacmt_fargs_bad.py b/test_regress/t/t_metacmt_fargs_bad.py index 54eb6c48d..f6ea13fea 100755 --- a/test_regress/t/t_metacmt_fargs_bad.py +++ b/test_regress/t/t_metacmt_fargs_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_metacmt_fargs_bad.v b/test_regress/t/t_metacmt_fargs_bad.v index 93649c65e..ba0e8d41f 100644 --- a/test_regress/t/t_metacmt_fargs_bad.v +++ b/test_regress/t/t_metacmt_fargs_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 /* verilator fargs --cc diff --git a/test_regress/t/t_metacmt_onoff.py b/test_regress/t/t_metacmt_onoff.py index 6585af685..b7449248c 100755 --- a/test_regress/t/t_metacmt_onoff.py +++ b/test_regress/t/t_metacmt_onoff.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_metacmt_onoff.v b/test_regress/t/t_metacmt_onoff.v index 91dc5eeae..80011e19f 100644 --- a/test_regress/t/t_metacmt_onoff.v +++ b/test_regress/t/t_metacmt_onoff.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_mod_automatic.py b/test_regress/t/t_mod_automatic.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mod_automatic.py +++ b/test_regress/t/t_mod_automatic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_automatic.v b/test_regress/t/t_mod_automatic.v index 517216789..d0ad14293 100644 --- a/test_regress/t/t_mod_automatic.v +++ b/test_regress/t/t_mod_automatic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module automatic t; diff --git a/test_regress/t/t_mod_dollar$.py b/test_regress/t/t_mod_dollar$.py index 122e74976..1162efed3 100755 --- a/test_regress/t/t_mod_dollar$.py +++ b/test_regress/t/t_mod_dollar$.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_dollar$.v b/test_regress/t/t_mod_dollar$.v index 3eaadfd6d..f748ff820 100644 --- a/test_regress/t/t_mod_dollar$.v +++ b/test_regress/t/t_mod_dollar$.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by engr248. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2020 engr248 // SPDX-License-Identifier: CC0-1.0 module \foo$bar ; diff --git a/test_regress/t/t_mod_dot.py b/test_regress/t/t_mod_dot.py index c0aa692c8..5fb4c194b 100755 --- a/test_regress/t/t_mod_dot.py +++ b/test_regress/t/t_mod_dot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_dot.v b/test_regress/t/t_mod_dot.v index 411b012b5..d2542d85c 100644 --- a/test_regress/t/t_mod_dot.v +++ b/test_regress/t/t_mod_dot.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by engr248. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2020 engr248 // SPDX-License-Identifier: CC0-1.0 module \foo.bar ; diff --git a/test_regress/t/t_mod_dup_bad.py b/test_regress/t/t_mod_dup_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_mod_dup_bad.py +++ b/test_regress/t/t_mod_dup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_dup_bad.v b/test_regress/t/t_mod_dup_bad.v index ad2b678af..55a20802c 100644 --- a/test_regress/t/t_mod_dup_bad.v +++ b/test_regress/t/t_mod_dup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module a(); diff --git a/test_regress/t/t_mod_dup_bad_lib.py b/test_regress/t/t_mod_dup_bad_lib.py index a19988f61..7cc2a715e 100755 --- a/test_regress/t/t_mod_dup_bad_lib.py +++ b/test_regress/t/t_mod_dup_bad_lib.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_dup_bad_lib.v b/test_regress/t/t_mod_dup_bad_lib.v index ad2b678af..55a20802c 100644 --- a/test_regress/t/t_mod_dup_bad_lib.v +++ b/test_regress/t/t_mod_dup_bad_lib.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module a(); diff --git a/test_regress/t/t_mod_dup_ign.py b/test_regress/t/t_mod_dup_ign.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_mod_dup_ign.py +++ b/test_regress/t/t_mod_dup_ign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_dup_ign.v b/test_regress/t/t_mod_dup_ign.v index 8b06b4457..7e08dee11 100644 --- a/test_regress/t/t_mod_dup_ign.v +++ b/test_regress/t/t_mod_dup_ign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_mod_empty.py b/test_regress/t/t_mod_empty.py index bf552cd4c..1cad9679c 100755 --- a/test_regress/t/t_mod_empty.py +++ b/test_regress/t/t_mod_empty.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_empty.v b/test_regress/t/t_mod_empty.v index e79e0ec68..6bbd6fa5d 100644 --- a/test_regress/t/t_mod_empty.v +++ b/test_regress/t/t_mod_empty.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module emptyModule; diff --git a/test_regress/t/t_mod_interface_array0.py b/test_regress/t/t_mod_interface_array0.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mod_interface_array0.py +++ b/test_regress/t/t_mod_interface_array0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array0.v b/test_regress/t/t_mod_interface_array0.v index b77eaae2d..98c6459f0 100644 --- a/test_regress/t/t_mod_interface_array0.v +++ b/test_regress/t/t_mod_interface_array0.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Johan Bjork. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Johan Bjork // SPDX-License-Identifier: CC0-1.0 parameter N = 4; diff --git a/test_regress/t/t_mod_interface_array0_noinl.py b/test_regress/t/t_mod_interface_array0_noinl.py index d82128883..db670e888 100755 --- a/test_regress/t/t_mod_interface_array0_noinl.py +++ b/test_regress/t/t_mod_interface_array0_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array1.py b/test_regress/t/t_mod_interface_array1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mod_interface_array1.py +++ b/test_regress/t/t_mod_interface_array1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array1.v b/test_regress/t/t_mod_interface_array1.v index 0cd46fe78..b07ff0e99 100644 --- a/test_regress/t/t_mod_interface_array1.v +++ b/test_regress/t/t_mod_interface_array1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Johan Bjork. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Johan Bjork // SPDX-License-Identifier: CC0-1.0 parameter N = 4; diff --git a/test_regress/t/t_mod_interface_array1_noinl.py b/test_regress/t/t_mod_interface_array1_noinl.py index 6d7fc4468..22bd5306c 100755 --- a/test_regress/t/t_mod_interface_array1_noinl.py +++ b/test_regress/t/t_mod_interface_array1_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array2.py b/test_regress/t/t_mod_interface_array2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mod_interface_array2.py +++ b/test_regress/t/t_mod_interface_array2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array2.v b/test_regress/t/t_mod_interface_array2.v index 30ee8ae74..9d2e7af66 100644 --- a/test_regress/t/t_mod_interface_array2.v +++ b/test_regress/t/t_mod_interface_array2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Johan Bjork. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Johan Bjork // SPDX-License-Identifier: CC0-1.0 parameter N = 4; diff --git a/test_regress/t/t_mod_interface_array2_noinl.py b/test_regress/t/t_mod_interface_array2_noinl.py index c0f6c74f7..02ffd87ef 100755 --- a/test_regress/t/t_mod_interface_array2_noinl.py +++ b/test_regress/t/t_mod_interface_array2_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array3.py b/test_regress/t/t_mod_interface_array3.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_mod_interface_array3.py +++ b/test_regress/t/t_mod_interface_array3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array3.v b/test_regress/t/t_mod_interface_array3.v index 3a83a9ce4..8a4b536be 100644 --- a/test_regress/t/t_mod_interface_array3.v +++ b/test_regress/t/t_mod_interface_array3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Johan Bjork. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Johan Bjork // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_mod_interface_array4.py b/test_regress/t/t_mod_interface_array4.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mod_interface_array4.py +++ b/test_regress/t/t_mod_interface_array4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array4.v b/test_regress/t/t_mod_interface_array4.v index 1e8781f82..7ce5e0eda 100644 --- a/test_regress/t/t_mod_interface_array4.v +++ b/test_regress/t/t_mod_interface_array4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_mod_interface_array4_noinl.py b/test_regress/t/t_mod_interface_array4_noinl.py index 5c330f73d..f0fae16bf 100755 --- a/test_regress/t/t_mod_interface_array4_noinl.py +++ b/test_regress/t/t_mod_interface_array4_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array5.py b/test_regress/t/t_mod_interface_array5.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mod_interface_array5.py +++ b/test_regress/t/t_mod_interface_array5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array5.v b/test_regress/t/t_mod_interface_array5.v index ff5d55625..29e0c44a0 100644 --- a/test_regress/t/t_mod_interface_array5.v +++ b/test_regress/t/t_mod_interface_array5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_mod_interface_array6.py b/test_regress/t/t_mod_interface_array6.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mod_interface_array6.py +++ b/test_regress/t/t_mod_interface_array6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_array6.v b/test_regress/t/t_mod_interface_array6.v index bb5fb50a5..d0b412573 100644 --- a/test_regress/t/t_mod_interface_array6.v +++ b/test_regress/t/t_mod_interface_array6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_mod_interface_array6_noinl.py b/test_regress/t/t_mod_interface_array6_noinl.py index 1740bd164..f8d264939 100755 --- a/test_regress/t/t_mod_interface_array6_noinl.py +++ b/test_regress/t/t_mod_interface_array6_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_clocking.py b/test_regress/t/t_mod_interface_clocking.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_mod_interface_clocking.py +++ b/test_regress/t/t_mod_interface_clocking.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_clocking.v b/test_regress/t/t_mod_interface_clocking.v index c59b05702..2073206ec 100644 --- a/test_regress/t/t_mod_interface_clocking.v +++ b/test_regress/t/t_mod_interface_clocking.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface axi_if; diff --git a/test_regress/t/t_mod_interface_clocking_bad.out b/test_regress/t/t_mod_interface_clocking_bad.out index 017459e00..7bc404203 100644 --- a/test_regress/t/t_mod_interface_clocking_bad.out +++ b/test_regress/t/t_mod_interface_clocking_bad.out @@ -5,7 +5,8 @@ %Error: t/t_mod_interface_clocking_bad.v:16:41: Modport item not found: 'cx' 16 | modport mp(input clk, clocking reset, clocking cx); | ^~~~~~~~ -%Error: t/t_mod_interface_clocking_bad.v:25:10: Can't find definition of 'cb' +%Error: t/t_mod_interface_clocking_bad.v:25:7: Can't find definition of 'cb' in dotted scope/variable: 'x.cb' 25 | x.cb.reset <= 1; - | ^~~~~ + | ^~ + ... Known scopes under 'x': %Error: Exiting due to diff --git a/test_regress/t/t_mod_interface_clocking_bad.py b/test_regress/t/t_mod_interface_clocking_bad.py index efe8cc01c..382ad0d44 100755 --- a/test_regress/t/t_mod_interface_clocking_bad.py +++ b/test_regress/t/t_mod_interface_clocking_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_interface_clocking_bad.v b/test_regress/t/t_mod_interface_clocking_bad.v index ee19b389a..e64550fa7 100644 --- a/test_regress/t/t_mod_interface_clocking_bad.v +++ b/test_regress/t/t_mod_interface_clocking_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface mem_if ( diff --git a/test_regress/t/t_mod_longname.py b/test_regress/t/t_mod_longname.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mod_longname.py +++ b/test_regress/t/t_mod_longname.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_longname.v b/test_regress/t/t_mod_longname.v index 777f25193..8ba6c653f 100644 --- a/test_regress/t/t_mod_longname.v +++ b/test_regress/t/t_mod_longname.v @@ -2,8 +2,8 @@ // // The code as shown makes a really big file name with Verilator. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 `define LONG_NAME_MOD modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie diff --git a/test_regress/t/t_mod_macromodule.py b/test_regress/t/t_mod_macromodule.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_mod_macromodule.py +++ b/test_regress/t/t_mod_macromodule.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_macromodule.v b/test_regress/t/t_mod_macromodule.v index 710246901..ed186af3a 100644 --- a/test_regress/t/t_mod_macromodule.v +++ b/test_regress/t/t_mod_macromodule.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 macromodule t; diff --git a/test_regress/t/t_mod_mod.py b/test_regress/t/t_mod_mod.py index 6585af685..b7449248c 100755 --- a/test_regress/t/t_mod_mod.py +++ b/test_regress/t/t_mod_mod.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_mod.v b/test_regress/t/t_mod_mod.v index 8e4465d0f..676280fd3 100644 --- a/test_regress/t/t_mod_mod.v +++ b/test_regress/t/t_mod_mod.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m(); diff --git a/test_regress/t/t_mod_nomod.py b/test_regress/t/t_mod_nomod.py index 3527cdb06..fabbdb10f 100755 --- a/test_regress/t/t_mod_nomod.py +++ b/test_regress/t/t_mod_nomod.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_nomod.v b/test_regress/t/t_mod_nomod.v index 7046313bb..c96c6b418 100644 --- a/test_regress/t/t_mod_nomod.v +++ b/test_regress/t/t_mod_nomod.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See issue #1381 diff --git a/test_regress/t/t_mod_param_class_typedef1.py b/test_regress/t/t_mod_param_class_typedef1.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_mod_param_class_typedef1.py +++ b/test_regress/t/t_mod_param_class_typedef1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_param_class_typedef1.v b/test_regress/t/t_mod_param_class_typedef1.v index 74ff9c26a..c0ff8ec12 100644 --- a/test_regress/t/t_mod_param_class_typedef1.v +++ b/test_regress/t/t_mod_param_class_typedef1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_mod_param_class_typedef2.py b/test_regress/t/t_mod_param_class_typedef2.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_mod_param_class_typedef2.py +++ b/test_regress/t/t_mod_param_class_typedef2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_param_class_typedef2.v b/test_regress/t/t_mod_param_class_typedef2.v index 2c8955cbf..ef8da2d27 100644 --- a/test_regress/t/t_mod_param_class_typedef2.v +++ b/test_regress/t/t_mod_param_class_typedef2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_mod_param_class_typedef3.py b/test_regress/t/t_mod_param_class_typedef3.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_mod_param_class_typedef3.py +++ b/test_regress/t/t_mod_param_class_typedef3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_param_class_typedef3.v b/test_regress/t/t_mod_param_class_typedef3.v index 81e28b61f..d25f8f087 100644 --- a/test_regress/t/t_mod_param_class_typedef3.v +++ b/test_regress/t/t_mod_param_class_typedef3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_mod_param_class_typedef4.py b/test_regress/t/t_mod_param_class_typedef4.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_mod_param_class_typedef4.py +++ b/test_regress/t/t_mod_param_class_typedef4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_param_class_typedef4.v b/test_regress/t/t_mod_param_class_typedef4.v index 555c9b46b..5bd860f78 100644 --- a/test_regress/t/t_mod_param_class_typedef4.v +++ b/test_regress/t/t_mod_param_class_typedef4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_mod_param_class_typedef5.py b/test_regress/t/t_mod_param_class_typedef5.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_mod_param_class_typedef5.py +++ b/test_regress/t/t_mod_param_class_typedef5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_param_class_typedef5.v b/test_regress/t/t_mod_param_class_typedef5.v index d496e5cfa..7a2ddd330 100644 --- a/test_regress/t/t_mod_param_class_typedef5.v +++ b/test_regress/t/t_mod_param_class_typedef5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_mod_param_class_typedef6.py b/test_regress/t/t_mod_param_class_typedef6.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_mod_param_class_typedef6.py +++ b/test_regress/t/t_mod_param_class_typedef6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_param_class_typedef6.v b/test_regress/t/t_mod_param_class_typedef6.v index f8a9aa139..d79167eb4 100644 --- a/test_regress/t/t_mod_param_class_typedef6.v +++ b/test_regress/t/t_mod_param_class_typedef6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_mod_param_class_typedef7.py b/test_regress/t/t_mod_param_class_typedef7.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_mod_param_class_typedef7.py +++ b/test_regress/t/t_mod_param_class_typedef7.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_param_class_typedef7.v b/test_regress/t/t_mod_param_class_typedef7.v index 756bc62b0..320fd8eda 100644 --- a/test_regress/t/t_mod_param_class_typedef7.v +++ b/test_regress/t/t_mod_param_class_typedef7.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_mod_recurse.py b/test_regress/t/t_mod_recurse.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mod_recurse.py +++ b/test_regress/t/t_mod_recurse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_recurse.v b/test_regress/t/t_mod_recurse.v index 7236d83b3..0e7b8d9ba 100644 --- a/test_regress/t/t_mod_recurse.v +++ b/test_regress/t/t_mod_recurse.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Sean Moore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Sean Moore // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_mod_recurse1.py b/test_regress/t/t_mod_recurse1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_mod_recurse1.py +++ b/test_regress/t/t_mod_recurse1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_recurse1.v b/test_regress/t/t_mod_recurse1.v index 423d7eea0..d8a94940b 100644 --- a/test_regress/t/t_mod_recurse1.v +++ b/test_regress/t/t_mod_recurse1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Sean Moore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Sean Moore // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_mod_topmodule.py b/test_regress/t/t_mod_topmodule.py index 2ea7dd9e0..4bd1e1215 100755 --- a/test_regress/t/t_mod_topmodule.py +++ b/test_regress/t/t_mod_topmodule.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_topmodule.v b/test_regress/t/t_mod_topmodule.v index 05d4c3ffa..e14726373 100644 --- a/test_regress/t/t_mod_topmodule.v +++ b/test_regress/t/t_mod_topmodule.v @@ -4,8 +4,8 @@ // is instantiated beneath another module in the compiled source // code. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Dan Petrisko +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Dan Petrisko // SPDX-License-Identifier: CC0-1.0 module top(/*AUTOARG*/ diff --git a/test_regress/t/t_mod_topmodule__underunder.py b/test_regress/t/t_mod_topmodule__underunder.py new file mode 100755 index 000000000..8ee97de25 --- /dev/null +++ b/test_regress/t/t_mod_topmodule__underunder.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--top-module t_mod_topmodule__underunder"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_mod_topmodule__underunder.v b/test_regress/t/t_mod_topmodule__underunder.v new file mode 100644 index 000000000..d736a1f13 --- /dev/null +++ b/test_regress/t/t_mod_topmodule__underunder.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This test verifies that a top-module can be specified which +// is instantiated beneath another module in the compiled source +// code. +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t_mod_topmodule__underunder; + initial $finish; +endmodule + +module faketop; +endmodule diff --git a/test_regress/t/t_mod_topmodule_nest.py b/test_regress/t/t_mod_topmodule_nest.py index 2ea7dd9e0..4bd1e1215 100755 --- a/test_regress/t/t_mod_topmodule_nest.py +++ b/test_regress/t/t_mod_topmodule_nest.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_topmodule_nest.v b/test_regress/t/t_mod_topmodule_nest.v index 53c8c41d7..7ce947d65 100644 --- a/test_regress/t/t_mod_topmodule_nest.v +++ b/test_regress/t/t_mod_topmodule_nest.v @@ -5,8 +5,8 @@ // code, even when that top-module has a module both above and beside // it in the hierarchy. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Dan Petrisko. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Dan Petrisko // SPDX-License-Identifier: CC0-1.0 module top(/*AUTOARG*/ diff --git a/test_regress/t/t_mod_uselib.py b/test_regress/t/t_mod_uselib.py index 0b27c3dc0..46f459325 100755 --- a/test_regress/t/t_mod_uselib.py +++ b/test_regress/t/t_mod_uselib.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_mod_uselib.v b/test_regress/t/t_mod_uselib.v index c761f0a78..1dbad7507 100644 --- a/test_regress/t/t_mod_uselib.v +++ b/test_regress/t/t_mod_uselib.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_module_class_static_method.py b/test_regress/t/t_module_class_static_method.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_module_class_static_method.py +++ b/test_regress/t/t_module_class_static_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_module_class_static_method.v b/test_regress/t/t_module_class_static_method.v index e1e75a1aa..79856e38c 100644 --- a/test_regress/t/t_module_class_static_method.v +++ b/test_regress/t/t_module_class_static_method.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_module_input_default_value.py b/test_regress/t/t_module_input_default_value.py index c5190cc16..d7538fa31 100755 --- a/test_regress/t/t_module_input_default_value.py +++ b/test_regress/t/t_module_input_default_value.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_module_input_default_value.v b/test_regress/t/t_module_input_default_value.v index e14c222f4..23c416b04 100644 --- a/test_regress/t/t_module_input_default_value.v +++ b/test_regress/t/t_module_input_default_value.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Andrew Ranck +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Andrew Ranck // SPDX-License-Identifier: CC0-1.0 // Test for Issue#5358: Support default value on module input. @@ -82,6 +82,12 @@ module t /*.i(),*/ .o(dut0_o_default)); + logic dut0_o_default_b; + dut_default_input0 u_dut0_default_b + (.required_input(1), + /*.i(),*/ + .o(dut0_o_default_b)); + logic dut1_o_default; dut_default_input1 u_dut1_default (/*.i(),*/ @@ -101,6 +107,11 @@ module t (.required_input(1), .i(), // open .o(dut0_o_open)); + logic dut0_o_open_b; + dut_default_input0 u_dut0_open_b + (.required_input(1), + .i(), // open + .o(dut0_o_open_b)); logic dut1_o_open; dut_default_input1 u_dut1_open @@ -122,11 +133,16 @@ module t // 3. DUT instances with overriden values // instance names are u_dut*_overriden // Have u_dut0_overriden get its overriden value from a signal - logic dut0_o_overriden; + logic dut0_o_overriden; dut_default_input0 u_dut0_overriden (.required_input(1), .i(logic1), // from wire .o(dut0_o_overriden)); + logic dut0_o_overriden_b; + dut_default_input0 u_dut0_overriden_b + (.required_input(1), + .i(logic1), // from wire + .o(dut0_o_overriden_b)); // Have u_dut1_overriden get its overriden value from a function. logic dut1_o_overriden; diff --git a/test_regress/t/t_module_input_default_value_1_bad.py b/test_regress/t/t_module_input_default_value_1_bad.py index 3def97587..71ef8b6c0 100755 --- a/test_regress/t/t_module_input_default_value_1_bad.py +++ b/test_regress/t/t_module_input_default_value_1_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_module_input_default_value_1_bad.v b/test_regress/t/t_module_input_default_value_1_bad.v index 494a058b9..6cbd48244 100644 --- a/test_regress/t/t_module_input_default_value_1_bad.v +++ b/test_regress/t/t_module_input_default_value_1_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Andrew Ranck +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Andrew Ranck // SPDX-License-Identifier: CC0-1.0 // Test for Issue#5358: Support default value on module input. diff --git a/test_regress/t/t_module_input_default_value_2_bad.py b/test_regress/t/t_module_input_default_value_2_bad.py index 3def97587..71ef8b6c0 100755 --- a/test_regress/t/t_module_input_default_value_2_bad.py +++ b/test_regress/t/t_module_input_default_value_2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_module_input_default_value_2_bad.v b/test_regress/t/t_module_input_default_value_2_bad.v index a5042af8c..1c34a85ce 100644 --- a/test_regress/t/t_module_input_default_value_2_bad.v +++ b/test_regress/t/t_module_input_default_value_2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Andrew Ranck +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Andrew Ranck // SPDX-License-Identifier: CC0-1.0 // Test for Issue#5358: Support default value on module input. diff --git a/test_regress/t/t_module_input_default_value_3_bad.py b/test_regress/t/t_module_input_default_value_3_bad.py index 3def97587..71ef8b6c0 100755 --- a/test_regress/t/t_module_input_default_value_3_bad.py +++ b/test_regress/t/t_module_input_default_value_3_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_module_input_default_value_3_bad.v b/test_regress/t/t_module_input_default_value_3_bad.v index a31085ce5..63fdf0ebf 100644 --- a/test_regress/t/t_module_input_default_value_3_bad.v +++ b/test_regress/t/t_module_input_default_value_3_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Andrew Ranck +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Andrew Ranck // SPDX-License-Identifier: CC0-1.0 // Test for Issue#5358: Support default value on module input. diff --git a/test_regress/t/t_module_input_default_value_noinl.py b/test_regress/t/t_module_input_default_value_noinl.py index 7858944b8..a105d2781 100755 --- a/test_regress/t/t_module_input_default_value_noinl.py +++ b/test_regress/t/t_module_input_default_value_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_multidriven_class.py b/test_regress/t/t_multidriven_class.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_multidriven_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_class.v b/test_regress/t/t_multidriven_class.v new file mode 100644 index 000000000..087ebf796 --- /dev/null +++ b/test_regress/t/t_multidriven_class.v @@ -0,0 +1,313 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// Consolidated class-based task/function multidriven tests +// (formerly t_multidriven_class{0,1,2,3,4,f0,f1}.v) + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +//---------------------------------------------------------------------- +// class0: class task writes through ref argument (direct assignment + class task in same always_comb) + +class C0; + task automatic set1(ref logic q); + q = 1'b1; + endtask + task automatic set0(ref logic q); + q = 1'b0; + endtask +endclass + +module class0 #( +) ( + input logic sel, + output logic val +); + + logic l0; + C0 c; + + initial c = new; + + always_comb begin + l0 = 1'b0; + if (sel) begin + c.set1(l0); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// class1: class task chain - nested method calls write through ref in same always_comb + +class C1; + task automatic inner(inout logic q); + q = 1'b1; + endtask + task automatic outer(inout logic q); + inner(q); + endtask +endclass + +module class1 #( +) ( + input logic sel, + output logic val +); + + logic l0; + C1 c; + + initial c = new; + + always_comb begin + l0 = 1'b0; + if (sel) begin + c.outer(l0); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// class2: class handle passed through module port - class method writes through ref + +class C2; + task automatic set1(ref logic q); + q = 1'b1; + endtask +endclass + +module class2 #( +) ( + input logic sel, + output logic val, + C2 c +); + + logic l0; + + always_comb begin + l0 = 1'b0; + if (sel) begin + c.set1(l0); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// class3: static class task - call via class scope, writes through ref in same always_comb + +class C3; + static task automatic set1(ref logic q); + q = 1'b1; + endtask +endclass + +module class3 #( +) ( + input logic sel, + output logic val +); + + logic l0; + + always_comb begin + l0 = 1'b0; + if (sel) begin + C3::set1(l0); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// class4: class composition - one class calls another task, ultimately writes through ref + +class C4Inner; + task automatic set1(ref logic q); + q = 1'b1; + endtask +endclass + +class C4Outer; + C4Inner inner; + function new(); + inner = new; + endfunction + task automatic set1(ref logic q); + inner.set1(q); + endtask +endclass + +module class4 #( +) ( + input logic sel, + output logic val +); + + logic l0; + C4Outer c; + + initial c = new; + + always_comb begin + l0 = 1'b0; + if (sel) begin + c.set1(l0); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// classf0: class function returns value - always_comb writes var directly + via class function call + +class Cf0; + function automatic logic ret1(); + return 1'b1; + endfunction +endclass + +module classf0 #( +) ( + input logic sel, + output logic val +); + + logic l0; + Cf0 c; + + initial c = new; + + always_comb begin + l0 = 1'b0; + if (sel) begin + l0 = c.ret1(); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// classf1: static class function returns value - always_comb uses class scope call + +class Cf1; + static function automatic logic ret1(); + return 1'b1; + endfunction +endclass + +module classf1 #( +) ( + input logic sel, + output logic val +); + + logic l0; + + always_comb begin + l0 = 1'b0; + if (sel) begin + l0 = Cf1::ret1(); + end + end + + assign val = l0; + +endmodule + +//---------------------------------------------------------------------- +// Shared TB + +module m_tb #() (); + + logic sel; + + logic val0, val1, val2, val3, val4, valf0, valf1; + + C2 c2; + initial c2 = new; + + class0 u0 ( + .sel(sel), + .val(val0) + ); + class1 u1 ( + .sel(sel), + .val(val1) + ); + class2 u2 ( + .sel(sel), + .val(val2), + .c(c2) + ); + class3 u3 ( + .sel(sel), + .val(val3) + ); + class4 u4 ( + .sel(sel), + .val(val4) + ); + classf0 uf0 ( + .sel(sel), + .val(valf0) + ); + classf1 uf1 ( + .sel(sel), + .val(valf1) + ); + + task automatic check_all(input logic exp); + `checkd(val0, exp); + `checkd(val1, exp); + `checkd(val2, exp); + `checkd(val3, exp); + `checkd(val4, exp); + `checkd(valf0, exp); + `checkd(valf1, exp); + endtask + + initial begin + #1; + sel = 'b0; + #1; + check_all(1'b0); + + sel = 'b1; + #1; + check_all(1'b1); + + sel = 'b0; + #1; + check_all(1'b0); + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_multidriven_funcret0.py b/test_regress/t/t_multidriven_funcret0.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_multidriven_funcret0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_funcret0.v b/test_regress/t/t_multidriven_funcret0.v new file mode 100644 index 000000000..15d5b7b76 --- /dev/null +++ b/test_regress/t/t_multidriven_funcret0.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// MULTIDRIVEN false positive - package function return var +// +// Minimal reproducer for: package function with "return expr" used in always_comb expression. +// The function return variable must not be treated as a side-effect "writeSummary" target. + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package p; + function automatic int num_bytes(input int size); + return 1 << size; + endfunction +endpackage + +module t; + typedef struct packed { + logic [31:0] addr; + logic [2:0] size; + } meta_t; + + meta_t rd_meta_q; + meta_t rd_meta; + + always_comb begin + rd_meta = rd_meta_q; + rd_meta.addr = rd_meta_q.addr + p::num_bytes(int'(rd_meta_q.size)); + end + + initial begin + rd_meta_q.addr = 32'h100; + rd_meta_q.size = 3'd2; // num_bytes = 4 + #1; + `checkd(rd_meta.addr, 32'h104); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_multidriven_iface.py b/test_regress/t/t_multidriven_iface.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_multidriven_iface.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_iface.v b/test_regress/t/t_multidriven_iface.v new file mode 100644 index 000000000..799f7e590 --- /dev/null +++ b/test_regress/t/t_multidriven_iface.v @@ -0,0 +1,280 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// Consolidated interface-based multidriven tests +// (formerly t_multidriven_iface{0,1,2,3,4,5,6}.v) + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +//---------------------------------------------------------------------- +// iface0: direct assignment to interface signal + interface task assign in same process + +interface my_if0; + logic l0; + task set_l0_1(); + l0 = 1'b1; + endtask + task set_l0_0(); + l0 = 1'b0; + endtask +endinterface + +module iface0 #( +) ( + input logic sel, + output logic val +); + my_if0 if0 (); + always_comb begin + if0.l0 = 1'b0; + if (sel) begin + if0.set_l0_1(); + end + end + assign val = if0.l0; +endmodule + +//---------------------------------------------------------------------- +// iface1: interface task chain - nested calls write interface signal in same always_comb + +interface my_if1; + logic l0; + task set_l0_1_inner(); + l0 = 1'b1; + endtask + task set_l0_1_outer(); + set_l0_1_inner(); + endtask +endinterface + +module iface1 #( +) ( + input logic sel, + output logic val +); + my_if1 if0 (); + always_comb begin + if0.l0 = 1'b0; + if (sel) begin + if0.set_l0_1_outer(); + end + end + assign val = if0.l0; +endmodule + +//---------------------------------------------------------------------- +// iface2: interface passed through module port - direct assign + task call in same always_comb + +interface my_if2; + logic l0; + task set_l0_1(); + l0 = 1'b1; + endtask + task set_l0_0(); + l0 = 1'b0; + endtask +endinterface + +module iface2 #( +) ( + input logic sel, + output logic val, + my_if2 ifp +); + always_comb begin + ifp.l0 = 1'b0; + if (sel) begin + ifp.set_l0_1(); + end + end + assign val = ifp.l0; +endmodule + +//---------------------------------------------------------------------- +// iface3: interface modport + task import - write interface signal in same always_comb + +interface my_if3; + logic l0; + task set_l0_1(); + l0 = 1'b1; + endtask + modport mp(output l0, import set_l0_1); +endinterface + +module iface3 #( +) ( + input logic sel, + output logic val, + my_if3.mp ifp +); + always_comb begin + ifp.l0 = 1'b0; + if (sel) begin + ifp.set_l0_1(); + end + end + assign val = ifp.l0; +endmodule + +//---------------------------------------------------------------------- +// iface4: interface task writes through output formal - actual is interface member + +interface my_if4; + logic l0; + task automatic set_any(output logic q); + q = 1'b1; + endtask +endinterface + +module iface4 #( +) ( + input logic sel, + output logic val +); + my_if4 if0 (); + always_comb begin + if0.l0 = 1'b0; + if (sel) begin + if0.set_any(if0.l0); + end + end + assign val = if0.l0; +endmodule + +//---------------------------------------------------------------------- +// iface5: nested interface test - direct assignment + nested interface task call in same always_comb + +interface leaf_if5; + logic l0; + task set1(); + l0 = 1'b1; + endtask +endinterface + +interface top_if5; + leaf_if5 sub (); +endinterface + +module iface5 #( +) ( + input logic sel, + output logic val +); + top_if5 if0 (); + always_comb begin + if0.sub.l0 = 1'b0; + if (sel) begin + if0.sub.set1(); + end + end + assign val = if0.sub.l0; +endmodule + +//---------------------------------------------------------------------- +// iface6: nested interface aggregator - two nested interfaces, only one driven + +interface chan_if6; + logic b0; + task set1(); + b0 = 1'b1; + endtask +endinterface + +interface agg_if6; + chan_if6 tlb (); + chan_if6 ic (); +endinterface + +module iface6 #( +) ( + input logic sel, + output logic val +); + agg_if6 a (); + always_comb begin + a.tlb.b0 = 1'b0; + if (sel) a.tlb.set1(); + end + assign val = a.tlb.b0; +endmodule + +//---------------------------------------------------------------------- +// Shared TB + +module m_tb #() (); + + logic sel; + logic val0, val1, val2, val3, val4, val5, val6; + + my_if2 if2 (); + my_if3 if3 (); + + iface0 u0 ( + .sel(sel), + .val(val0) + ); + iface1 u1 ( + .sel(sel), + .val(val1) + ); + iface2 u2 ( + .sel(sel), + .val(val2), + .ifp(if2) + ); + iface3 u3 ( + .sel(sel), + .val(val3), + .ifp(if3) + ); + iface4 u4 ( + .sel(sel), + .val(val4) + ); + iface5 u5 ( + .sel(sel), + .val(val5) + ); + iface6 u6 ( + .sel(sel), + .val(val6) + ); + + task automatic check_all(input logic exp); + `checkd(val0, exp); + `checkd(val1, exp); + `checkd(val2, exp); + `checkd(val3, exp); + `checkd(val4, exp); + `checkd(val5, exp); + `checkd(val6, exp); + endtask + + initial begin + #1; + sel = 'b0; + #1; + check_all(1'b0); + + sel = 'b1; + #1; + check_all(1'b1); + + sel = 'b0; + #1; + check_all(1'b0); + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_multidriven_simple.py b/test_regress/t/t_multidriven_simple.py new file mode 100755 index 000000000..31b1f0e53 --- /dev/null +++ b/test_regress/t/t_multidriven_simple.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_simple.v b/test_regress/t/t_multidriven_simple.v new file mode 100644 index 000000000..084c68d7b --- /dev/null +++ b/test_regress/t/t_multidriven_simple.v @@ -0,0 +1,158 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +// direct task call +module mod0 #( +) ( + input logic sel, + output logic val +); + logic l0; + task do_stuff(); + l0 = 'b1; + endtask + always_comb begin + l0 = 'b0; + if (sel) begin + do_stuff(); + end + end + assign val = l0; +endmodule + +// nested task call chain +module mod1 #( +) ( + input logic sel, + output logic val +); + logic l0; + task do_inner(); + l0 = 'b1; + endtask + task do_outer(); + do_inner(); + endtask + always_comb begin + l0 = 'b0; + if (sel) do_outer(); + end + assign val = l0; +endmodule + +// task writes through an output arguement +module mod2 #( +) ( + input logic sel, + output logic val +); + logic l0; + task automatic do_stuff(output logic q); + q = 1'b1; + endtask + always_comb begin + l0 = 1'b0; + if (sel) do_stuff(l0); + end + assign val = l0; +endmodule + +// function call that writes +module mod3 #( +) ( + input logic sel, + output logic val +); + logic l0; + function automatic void do_func(); + l0 = 1'b1; + endfunction + always_comb begin + l0 = 1'b0; + if (sel) do_func(); + end + assign val = l0; +endmodule + +// two tasks set0/set1 +module mod4 #( +) ( + input logic sel, + output logic val +); + logic l0; + task automatic set1(); + l0 = 1'b1; + endtask + task automatic set0(); + l0 = 1'b0; + endtask + always_comb begin + set0(); + if (sel) begin + set1(); + end + end + assign val = l0; +endmodule + +module m_tb; + logic sel; + logic v0, v1, v2, v3, v4; + + mod0 u0 ( + .sel(sel), + .val(v0) + ); + mod1 u1 ( + .sel(sel), + .val(v1) + ); + mod2 u2 ( + .sel(sel), + .val(v2) + ); + mod3 u3 ( + .sel(sel), + .val(v3) + ); + mod4 u4 ( + .sel(sel), + .val(v4) + ); + + initial begin + #1; + sel = 0; + `checkd(v0, 0); + `checkd(v1, 0); + `checkd(v2, 0); + `checkd(v3, 0); + `checkd(v4, 0); + #1; + sel = 1; + `checkd(v0, 1); + `checkd(v1, 1); + `checkd(v2, 1); + `checkd(v3, 1); + `checkd(v4, 1); + #1; + sel = 0; + `checkd(v0, 0); + `checkd(v1, 0); + `checkd(v2, 0); + `checkd(v3, 0); + `checkd(v4, 0); + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_multitop1.py b/test_regress/t/t_multitop1.py index 86e5ab5e5..b3095a9c5 100755 --- a/test_regress/t/t_multitop1.py +++ b/test_regress/t/t_multitop1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_multitop1.v b/test_regress/t/t_multitop1.v index a89daf8a9..0ace0f0a6 100644 --- a/test_regress/t/t_multitop1.v +++ b/test_regress/t/t_multitop1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_multitop1s.v b/test_regress/t/t_multitop1s.v index 34282dd67..06e27d6b5 100644 --- a/test_regress/t/t_multitop1s.v +++ b/test_regress/t/t_multitop1s.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_multitop1s; diff --git a/test_regress/t/t_multitop_sig.cpp b/test_regress/t/t_multitop_sig.cpp index 95cc0aa7c..c24f14700 100644 --- a/test_regress/t/t_multitop_sig.cpp +++ b/test_regress/t/t_multitop_sig.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_multitop_sig.py b/test_regress/t/t_multitop_sig.py index b70faf4bc..ee91c179b 100755 --- a/test_regress/t/t_multitop_sig.py +++ b/test_regress/t/t_multitop_sig.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_multitop_sig.v b/test_regress/t/t_multitop_sig.v index 4f1d34338..167a2922c 100644 --- a/test_regress/t/t_multitop_sig.v +++ b/test_regress/t/t_multitop_sig.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module a(in, out); diff --git a/test_regress/t/t_multitop_sig_bad.py b/test_regress/t/t_multitop_sig_bad.py index b76511c6c..d9f4b81e7 100755 --- a/test_regress/t/t_multitop_sig_bad.py +++ b/test_regress/t/t_multitop_sig_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_multitop_xref.py b/test_regress/t/t_multitop_xref.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_multitop_xref.py +++ b/test_regress/t/t_multitop_xref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_multitop_xref.v b/test_regress/t/t_multitop_xref.v index f96eca986..2f493a5dc 100644 --- a/test_regress/t/t_multitop_xref.v +++ b/test_regress/t/t_multitop_xref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_name_collision.py b/test_regress/t/t_name_collision.py index fdaf03625..734512bed 100755 --- a/test_regress/t/t_name_collision.py +++ b/test_regress/t/t_name_collision.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_name_collision.v b/test_regress/t/t_name_collision.v index 6639e9ed5..4f232e0b3 100644 --- a/test_regress/t/t_name_collision.v +++ b/test_regress/t/t_name_collision.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module HasNameParam diff --git a/test_regress/t/t_nba_assign_on_rhs.py b/test_regress/t/t_nba_assign_on_rhs.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_nba_assign_on_rhs.py +++ b/test_regress/t/t_nba_assign_on_rhs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_nba_assign_on_rhs.v b/test_regress/t/t_nba_assign_on_rhs.v index 312ee0366..26a8e3fd8 100644 --- a/test_regress/t/t_nba_assign_on_rhs.v +++ b/test_regress/t/t_nba_assign_on_rhs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_nba_commit_queue.py b/test_regress/t/t_nba_commit_queue.py index f2f141378..0b71cf8b2 100755 --- a/test_regress/t/t_nba_commit_queue.py +++ b/test_regress/t/t_nba_commit_queue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_nba_commit_queue.v b/test_regress/t/t_nba_commit_queue.v index 632762b22..ccda0713c 100644 --- a/test_regress/t/t_nba_commit_queue.v +++ b/test_regress/t/t_nba_commit_queue.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_nba_commit_queue_suspenable.py b/test_regress/t/t_nba_commit_queue_suspenable.py index c27c4ac25..90960f869 100755 --- a/test_regress/t/t_nba_commit_queue_suspenable.py +++ b/test_regress/t/t_nba_commit_queue_suspenable.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_nba_commit_queue_suspenable.v b/test_regress/t/t_nba_commit_queue_suspenable.v index 3ba826ea9..4d94379a2 100644 --- a/test_regress/t/t_nba_commit_queue_suspenable.v +++ b/test_regress/t/t_nba_commit_queue_suspenable.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_nba_hier.py b/test_regress/t/t_nba_hier.py index 5714e793e..adb8e4da8 100755 --- a/test_regress/t/t_nba_hier.py +++ b/test_regress/t/t_nba_hier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_nba_hier.v b/test_regress/t/t_nba_hier.v index 87967b19c..8c83bac56 100644 --- a/test_regress/t/t_nba_hier.v +++ b/test_regress/t/t_nba_hier.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_nba_mixed_update_clocked.py b/test_regress/t/t_nba_mixed_update_clocked.py index 6e944f0f7..f8e05bf18 100755 --- a/test_regress/t/t_nba_mixed_update_clocked.py +++ b/test_regress/t/t_nba_mixed_update_clocked.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_nba_mixed_update_clocked.v b/test_regress/t/t_nba_mixed_update_clocked.v index 20c4e9063..20c4d9631 100644 --- a/test_regress/t/t_nba_mixed_update_clocked.v +++ b/test_regress/t/t_nba_mixed_update_clocked.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_nba_mixed_update_comb.py b/test_regress/t/t_nba_mixed_update_comb.py index 689445088..063b96de3 100755 --- a/test_regress/t/t_nba_mixed_update_comb.py +++ b/test_regress/t/t_nba_mixed_update_comb.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_nba_mixed_update_comb.v b/test_regress/t/t_nba_mixed_update_comb.v index c8c002d87..be73ff82c 100644 --- a/test_regress/t/t_nba_mixed_update_comb.v +++ b/test_regress/t/t_nba_mixed_update_comb.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_nba_shared_flag_reuse.py b/test_regress/t/t_nba_shared_flag_reuse.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_nba_shared_flag_reuse.py +++ b/test_regress/t/t_nba_shared_flag_reuse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_nba_shared_flag_reuse.v b/test_regress/t/t_nba_shared_flag_reuse.v index 2116c45ba..c6a7b9588 100644 --- a/test_regress/t/t_nba_shared_flag_reuse.v +++ b/test_regress/t/t_nba_shared_flag_reuse.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_nba_struct_array.py b/test_regress/t/t_nba_struct_array.py index f64ff6ad9..c8511382a 100755 --- a/test_regress/t/t_nba_struct_array.py +++ b/test_regress/t/t_nba_struct_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_nba_struct_array.v b/test_regress/t/t_nba_struct_array.v index 6233c3cf1..6e64789b9 100644 --- a/test_regress/t/t_nba_struct_array.v +++ b/test_regress/t/t_nba_struct_array.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_net_delay.py b/test_regress/t/t_net_delay.py index 2424f0de5..90c1cf2fd 100755 --- a/test_regress/t/t_net_delay.py +++ b/test_regress/t/t_net_delay.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_net_delay.v b/test_regress/t/t_net_delay.v index 9822f1827..2faa3e0b3 100644 --- a/test_regress/t/t_net_delay.v +++ b/test_regress/t/t_net_delay.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_net_delay_timing.py b/test_regress/t/t_net_delay_timing.py index bc41b20a9..442c015eb 100755 --- a/test_regress/t/t_net_delay_timing.py +++ b/test_regress/t/t_net_delay_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_net_delay_timing_sc.py b/test_regress/t/t_net_delay_timing_sc.py index 9e15c738f..85cb5093b 100755 --- a/test_regress/t/t_net_delay_timing_sc.py +++ b/test_regress/t/t_net_delay_timing_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_net_dtype_bad.py b/test_regress/t/t_net_dtype_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_net_dtype_bad.py +++ b/test_regress/t/t_net_dtype_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_net_dtype_bad.v b/test_regress/t/t_net_dtype_bad.v index f5f3383ea..7b5f4e1eb 100644 --- a/test_regress/t/t_net_dtype_bad.v +++ b/test_regress/t/t_net_dtype_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_nettype.py b/test_regress/t/t_nettype.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_nettype.py +++ b/test_regress/t/t_nettype.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_nettype.v b/test_regress/t/t_nettype.v index 1614c76de..9dd3ce0b4 100644 --- a/test_regress/t/t_nettype.v +++ b/test_regress/t/t_nettype.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg; diff --git a/test_regress/t/t_no_sel_assign_merge_in_cpp.py b/test_regress/t/t_no_sel_assign_merge_in_cpp.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_no_sel_assign_merge_in_cpp.py +++ b/test_regress/t/t_no_sel_assign_merge_in_cpp.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_no_sel_assign_merge_in_cpp.v b/test_regress/t/t_no_sel_assign_merge_in_cpp.v index 6c7f1a62b..cd729985d 100644 --- a/test_regress/t/t_no_sel_assign_merge_in_cpp.v +++ b/test_regress/t/t_no_sel_assign_merge_in_cpp.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_no_sel_assign_merge_in_cpp ( diff --git a/test_regress/t/t_no_std_bad.py b/test_regress/t/t_no_std_bad.py index b0857dbf5..d52e862a6 100755 --- a/test_regress/t/t_no_std_bad.py +++ b/test_regress/t/t_no_std_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_no_std_bad.v b/test_regress/t/t_no_std_bad.v index 9bce31e77..7e5457019 100644 --- a/test_regress/t/t_no_std_bad.v +++ b/test_regress/t/t_no_std_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off DECLFILENAME diff --git a/test_regress/t/t_no_std_pkg_bad.py b/test_regress/t/t_no_std_pkg_bad.py index d8c88252c..d28dfe589 100755 --- a/test_regress/t/t_no_std_pkg_bad.py +++ b/test_regress/t/t_no_std_pkg_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_no_trace_top.cpp b/test_regress/t/t_no_trace_top.cpp index e53cd583d..51091a4de 100644 --- a/test_regress/t/t_no_trace_top.cpp +++ b/test_regress/t/t_no_trace_top.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_no_trace_top.py b/test_regress/t/t_no_trace_top.py index 3a550f86d..83cc873eb 100755 --- a/test_regress/t/t_no_trace_top.py +++ b/test_regress/t/t_no_trace_top.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_noninl_port_type.py b/test_regress/t/t_noninl_port_type.py new file mode 100755 index 000000000..b1a195a9c --- /dev/null +++ b/test_regress/t/t_noninl_port_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_noninl_port_type.v b/test_regress/t/t_noninl_port_type.v new file mode 100644 index 000000000..0ed7b7219 --- /dev/null +++ b/test_regress/t/t_noninl_port_type.v @@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +module top; + + int x, y, z; + int out [3]; + + sub sub_i(x, y, z, out); + + initial begin + x = 2; + y = 1; + z = 3; + #1; + `checkh(out[0], 1); + `checkh(out[1], 2); + `checkh(out[2], 3); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module sub( + input int a, + input int b, + input int c, + output int sorted [3] +); + + /* verilator no_inline_module */ + + always_comb begin + sorted = '{a, b, c}; + sorted.sort; + end + +endmodule diff --git a/test_regress/t/t_notiming.py b/test_regress/t/t_notiming.py index 6f71603b5..d1bad5e3a 100755 --- a/test_regress/t/t_notiming.py +++ b/test_regress/t/t_notiming.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_notiming.v b/test_regress/t/t_notiming.v index ae163d23c..5777f8c66 100644 --- a/test_regress/t/t_notiming.v +++ b/test_regress/t/t_notiming.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_notiming_off.py b/test_regress/t/t_notiming_off.py index a1cb5082f..e5896a33d 100755 --- a/test_regress/t/t_notiming_off.py +++ b/test_regress/t/t_notiming_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_0.py b/test_regress/t/t_opt_0.py index 38bb29595..41535b3cc 100755 --- a/test_regress/t/t_opt_0.py +++ b/test_regress/t/t_opt_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_0.v b/test_regress/t/t_opt_0.v index 55b645c5f..f4e1346f3 100644 --- a/test_regress/t/t_opt_0.v +++ b/test_regress/t/t_opt_0.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_opt_assemble_cellarray.py b/test_regress/t/t_opt_assemble_cellarray.py index 3c81426dd..79e99cda4 100755 --- a/test_regress/t/t_opt_assemble_cellarray.py +++ b/test_regress/t/t_opt_assemble_cellarray.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_assemble_cellarray.v b/test_regress/t/t_opt_assemble_cellarray.v index c7c6e32b9..45dd03a99 100644 --- a/test_regress/t/t_opt_assemble_cellarray.v +++ b/test_regress/t/t_opt_assemble_cellarray.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Jie Xu // SPDX-License-Identifier: CC0-1.0 // change these two parameters to see the speed differences diff --git a/test_regress/t/t_opt_assemble_cellarray_off.py b/test_regress/t/t_opt_assemble_cellarray_off.py index 52d34ad88..ba7ec6d37 100755 --- a/test_regress/t/t_opt_assemble_cellarray_off.py +++ b/test_regress/t/t_opt_assemble_cellarray_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_balance_cats.py b/test_regress/t/t_opt_balance_cats.py index b4c1671aa..cca6c4f1a 100755 --- a/test_regress/t/t_opt_balance_cats.py +++ b/test_regress/t/t_opt_balance_cats.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_balance_cats.v b/test_regress/t/t_opt_balance_cats.v index 7befe35ce..154a9266f 100644 --- a/test_regress/t/t_opt_balance_cats.v +++ b/test_regress/t/t_opt_balance_cats.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(i, o); diff --git a/test_regress/t/t_opt_balance_cats_nofunc.py b/test_regress/t/t_opt_balance_cats_nofunc.py index 153050312..4f19c30eb 100755 --- a/test_regress/t/t_opt_balance_cats_nofunc.py +++ b/test_regress/t/t_opt_balance_cats_nofunc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_balance_cats_sc.py b/test_regress/t/t_opt_balance_cats_sc.py index d9b6693a3..59667fd06 100755 --- a/test_regress/t/t_opt_balance_cats_sc.py +++ b/test_regress/t/t_opt_balance_cats_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const.cpp b/test_regress/t/t_opt_const.cpp index fde57c973..fcb767538 100644 --- a/test_regress/t/t_opt_const.cpp +++ b/test_regress/t/t_opt_const.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_opt_const.py b/test_regress/t/t_opt_const.py index 5cf4b936b..90b3b54f6 100755 --- a/test_regress/t/t_opt_const.py +++ b/test_regress/t/t_opt_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const.v b/test_regress/t/t_opt_const.v index d4982f11c..b2eae6d59 100644 --- a/test_regress/t/t_opt_const.v +++ b/test_regress/t/t_opt_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 Yutetsu TAKATSUKASA. +// SPDX-FileCopyrightText: 2021 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 // This function always returns 0, so safe to take bitwise OR with any value. diff --git a/test_regress/t/t_opt_const_big_or_tree.py b/test_regress/t/t_opt_const_big_or_tree.py index 7fbda1fba..e8b658de6 100755 --- a/test_regress/t/t_opt_const_big_or_tree.py +++ b/test_regress/t/t_opt_const_big_or_tree.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const_big_or_tree.v b/test_regress/t/t_opt_const_big_or_tree.v index f24ecb010..a632b710b 100644 --- a/test_regress/t/t_opt_const_big_or_tree.v +++ b/test_regress/t/t_opt_const_big_or_tree.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_opt_const_cond_redundant.py b/test_regress/t/t_opt_const_cond_redundant.py index 5a1640c4e..ee4352503 100755 --- a/test_regress/t/t_opt_const_cond_redundant.py +++ b/test_regress/t/t_opt_const_cond_redundant.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const_cond_redundant.v b/test_regress/t/t_opt_const_cond_redundant.v index 8dcb36a90..a3ccfdfc1 100644 --- a/test_regress/t/t_opt_const_cond_redundant.v +++ b/test_regress/t/t_opt_const_cond_redundant.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug3806 diff --git a/test_regress/t/t_opt_const_cov.py b/test_regress/t/t_opt_const_cov.py index f1c93b8d2..8cff7b332 100755 --- a/test_regress/t/t_opt_const_cov.py +++ b/test_regress/t/t_opt_const_cov.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const_cov.v b/test_regress/t/t_opt_const_cov.v index 0d3790fed..5d2793197 100644 --- a/test_regress/t/t_opt_const_cov.v +++ b/test_regress/t/t_opt_const_cov.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Wilson Snyder. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_opt_const_dfg.py b/test_regress/t/t_opt_const_dfg.py index 6fd2ea9bc..eb5626311 100755 --- a/test_regress/t/t_opt_const_dfg.py +++ b/test_regress/t/t_opt_const_dfg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const_no_expand.py b/test_regress/t/t_opt_const_no_expand.py index e72a9737f..2ab023f16 100755 --- a/test_regress/t/t_opt_const_no_expand.py +++ b/test_regress/t/t_opt_const_no_expand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const_no_opt.py b/test_regress/t/t_opt_const_no_opt.py index 6633ac18d..2d893a3c6 100755 --- a/test_regress/t/t_opt_const_no_opt.py +++ b/test_regress/t/t_opt_const_no_opt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const_or.py b/test_regress/t/t_opt_const_or.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_opt_const_or.py +++ b/test_regress/t/t_opt_const_or.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const_or.v b/test_regress/t/t_opt_const_or.v index 7ed622dc7..2cd09ec64 100644 --- a/test_regress/t/t_opt_const_or.v +++ b/test_regress/t/t_opt_const_or.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Wilson Snyder. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_opt_const_red.py b/test_regress/t/t_opt_const_red.py index 66ad3d212..11c4ebbff 100755 --- a/test_regress/t/t_opt_const_red.py +++ b/test_regress/t/t_opt_const_red.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const_red.v b/test_regress/t/t_opt_const_red.v index 6405e0c92..589f3b351 100644 --- a/test_regress/t/t_opt_const_red.v +++ b/test_regress/t/t_opt_const_red.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Wilson Snyder. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_opt_const_shortcut.cpp b/test_regress/t/t_opt_const_shortcut.cpp index 44a695a94..cfd94c48e 100644 --- a/test_regress/t/t_opt_const_shortcut.cpp +++ b/test_regress/t/t_opt_const_shortcut.cpp @@ -1,5 +1,5 @@ -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_opt_const_shortcut.py b/test_regress/t/t_opt_const_shortcut.py index 340f595be..bbe1eaf69 100755 --- a/test_regress/t/t_opt_const_shortcut.py +++ b/test_regress/t/t_opt_const_shortcut.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_const_shortcut.v b/test_regress/t/t_opt_const_shortcut.v index 5ad27558e..42a7d4c9a 100644 --- a/test_regress/t/t_opt_const_shortcut.v +++ b/test_regress/t/t_opt_const_shortcut.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 Yutetsu TAKATSUKASA. +// SPDX-FileCopyrightText: 2021 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 import "DPI-C" context function int import_func0(); diff --git a/test_regress/t/t_opt_dead.py b/test_regress/t/t_opt_dead.py index 10b9c67ff..a0de4ce68 100755 --- a/test_regress/t/t_opt_dead.py +++ b/test_regress/t/t_opt_dead.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_dead.v b/test_regress/t/t_opt_dead.v index 4fb804739..09c0a8c08 100644 --- a/test_regress/t/t_opt_dead.v +++ b/test_regress/t/t_opt_dead.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class EmptyClass_Dead; diff --git a/test_regress/t/t_opt_dead_enumpkg.py b/test_regress/t/t_opt_dead_enumpkg.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_opt_dead_enumpkg.py +++ b/test_regress/t/t_opt_dead_enumpkg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_dead_enumpkg.v b/test_regress/t/t_opt_dead_enumpkg.v index 491e1ad5a..11bae4aed 100644 --- a/test_regress/t/t_opt_dead_enumpkg.v +++ b/test_regress/t/t_opt_dead_enumpkg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_opt_dead_noassigns.py b/test_regress/t/t_opt_dead_noassigns.py index c191088d1..d9068708b 100755 --- a/test_regress/t/t_opt_dead_noassigns.py +++ b/test_regress/t/t_opt_dead_noassigns.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_dead_noassigns.v b/test_regress/t/t_opt_dead_noassigns.v index beb41c736..e302db4ab 100644 --- a/test_regress/t/t_opt_dead_noassigns.v +++ b/test_regress/t/t_opt_dead_noassigns.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_dead_nocells.py b/test_regress/t/t_opt_dead_nocells.py index 3637842f4..22ab3ea62 100755 --- a/test_regress/t/t_opt_dead_nocells.py +++ b/test_regress/t/t_opt_dead_nocells.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_dead_nocells.v b/test_regress/t/t_opt_dead_nocells.v index 0ee6431ab..4db59694e 100644 --- a/test_regress/t/t_opt_dead_nocells.v +++ b/test_regress/t/t_opt_dead_nocells.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module Mod_Dead; diff --git a/test_regress/t/t_opt_dead_task.py b/test_regress/t/t_opt_dead_task.py index 84ef5c5e2..93f7d9485 100755 --- a/test_regress/t/t_opt_dead_task.py +++ b/test_regress/t/t_opt_dead_task.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_dead_task.v b/test_regress/t/t_opt_dead_task.v index cf9f77a6d..4cc32ad78 100644 --- a/test_regress/t/t_opt_dead_task.v +++ b/test_regress/t/t_opt_dead_task.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_opt_dedupe_clk_gate.py b/test_regress/t/t_opt_dedupe_clk_gate.py index 29a1ccf68..1125e65e5 100755 --- a/test_regress/t/t_opt_dedupe_clk_gate.py +++ b/test_regress/t/t_opt_dedupe_clk_gate.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_dedupe_clk_gate.v b/test_regress/t/t_opt_dedupe_clk_gate.v index 6ba6ff174..c40a44d5f 100644 --- a/test_regress/t/t_opt_dedupe_clk_gate.v +++ b/test_regress/t/t_opt_dedupe_clk_gate.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Dedupe optimization test. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by Varun Koyyalagunta, Centaur Technology. diff --git a/test_regress/t/t_opt_dedupe_clk_gate_off.py b/test_regress/t/t_opt_dedupe_clk_gate_off.py index e48d085c4..0fccfd799 100755 --- a/test_regress/t/t_opt_dedupe_clk_gate_off.py +++ b/test_regress/t/t_opt_dedupe_clk_gate_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_dedupe_seq_logic.py b/test_regress/t/t_opt_dedupe_seq_logic.py index 32c90c0e9..1a30d0dd9 100755 --- a/test_regress/t/t_opt_dedupe_seq_logic.py +++ b/test_regress/t/t_opt_dedupe_seq_logic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_dedupe_seq_logic.v b/test_regress/t/t_opt_dedupe_seq_logic.v index e9a03f3f8..657cbc939 100644 --- a/test_regress/t/t_opt_dedupe_seq_logic.v +++ b/test_regress/t/t_opt_dedupe_seq_logic.v @@ -1,11 +1,9 @@ // DESCRIPTION: Verilator: Dedupe optimization test. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Varun Koyyalagunta, Centaur Technology // SPDX-License-Identifier: CC0-1.0 -// Contributed 2012 by Varun Koyyalagunta, Centaur Technology. -// // Test consists of the follow logic tree, which has many obvious // places for dedupe: /* diff --git a/test_regress/t/t_opt_expand_keep_widths.py b/test_regress/t/t_opt_expand_keep_widths.py index fa87f0e9d..85a35d675 100755 --- a/test_regress/t/t_opt_expand_keep_widths.py +++ b/test_regress/t/t_opt_expand_keep_widths.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_expand_keep_widths.v b/test_regress/t/t_opt_expand_keep_widths.v index a19565b00..61f6ca22c 100644 --- a/test_regress/t/t_opt_expand_keep_widths.v +++ b/test_regress/t/t_opt_expand_keep_widths.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module gymhnulbvj (in5, clock_10, clock_12, out18); diff --git a/test_regress/t/t_opt_if_array.py b/test_regress/t/t_opt_if_array.py index 0739b468a..9abf44601 100755 --- a/test_regress/t/t_opt_if_array.py +++ b/test_regress/t/t_opt_if_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_if_array.v b/test_regress/t/t_opt_if_array.v index 2004c58eb..9bb49b2fe 100644 --- a/test_regress/t/t_opt_if_array.v +++ b/test_regress/t/t_opt_if_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_ifjumpgo.py b/test_regress/t/t_opt_ifjumpgo.py index 2c0e4f4f6..a96fc4420 100755 --- a/test_regress/t/t_opt_ifjumpgo.py +++ b/test_regress/t/t_opt_ifjumpgo.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_ifjumpgo.v b/test_regress/t/t_opt_ifjumpgo.v index e0fabacaa..69ff06d76 100644 --- a/test_regress/t/t_opt_ifjumpgo.v +++ b/test_regress/t/t_opt_ifjumpgo.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class uvm_object; diff --git a/test_regress/t/t_opt_inline_cfuncs.py b/test_regress/t/t_opt_inline_cfuncs.py index 5e2ad15b3..7981f48c3 100755 --- a/test_regress/t/t_opt_inline_cfuncs.py +++ b/test_regress/t/t_opt_inline_cfuncs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_inline_cfuncs.v b/test_regress/t/t_opt_inline_cfuncs.v index b17dcce8f..514748197 100644 --- a/test_regress/t/t_opt_inline_cfuncs.v +++ b/test_regress/t/t_opt_inline_cfuncs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Test module designed to generate multiple small CFuncs that can be inlined diff --git a/test_regress/t/t_opt_inline_cfuncs_off.py b/test_regress/t/t_opt_inline_cfuncs_off.py index 7caca9631..8b045e8ca 100755 --- a/test_regress/t/t_opt_inline_cfuncs_off.py +++ b/test_regress/t/t_opt_inline_cfuncs_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_inline_cfuncs_threshold.py b/test_regress/t/t_opt_inline_cfuncs_threshold.py index f653728ae..677dee894 100755 --- a/test_regress/t/t_opt_inline_cfuncs_threshold.py +++ b/test_regress/t/t_opt_inline_cfuncs_threshold.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_inline_cfuncs_threshold.v b/test_regress/t/t_opt_inline_cfuncs_threshold.v index 8dd36ccd2..e45e149fb 100644 --- a/test_regress/t/t_opt_inline_cfuncs_threshold.v +++ b/test_regress/t/t_opt_inline_cfuncs_threshold.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Test module to exercise threshold checking in CFunc inlining diff --git a/test_regress/t/t_opt_inline_funcs.py b/test_regress/t/t_opt_inline_funcs.py index 2ef665de4..b644fe663 100755 --- a/test_regress/t/t_opt_inline_funcs.py +++ b/test_regress/t/t_opt_inline_funcs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_inline_funcs.v b/test_regress/t/t_opt_inline_funcs.v index 3d63a636f..56bfeeb51 100644 --- a/test_regress/t/t_opt_inline_funcs.v +++ b/test_regress/t/t_opt_inline_funcs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_opt_inline_funcs_no.py b/test_regress/t/t_opt_inline_funcs_no.py index 4ae9a60d0..88f96ac39 100755 --- a/test_regress/t/t_opt_inline_funcs_no.py +++ b/test_regress/t/t_opt_inline_funcs_no.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_inline_funcs_no_eager.py b/test_regress/t/t_opt_inline_funcs_no_eager.py index a832fe80a..69590605e 100755 --- a/test_regress/t/t_opt_inline_funcs_no_eager.py +++ b/test_regress/t/t_opt_inline_funcs_no_eager.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_life.py b/test_regress/t/t_opt_life.py index 76637c7ee..fa4b9bb88 100755 --- a/test_regress/t/t_opt_life.py +++ b/test_regress/t/t_opt_life.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -14,8 +14,7 @@ test.scenarios('simulator') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: - test.file_grep(test.stats, r'Optimizations, Lifetime assign deletions\s+(\d+)', 4) - test.file_grep(test.stats, r'Optimizations, Lifetime creset deletions\s+(\d+)', 1) + test.file_grep(test.stats, r'Optimizations, Lifetime assign deletions\s+(\d+)', 5) test.file_grep(test.stats, r'Optimizations, Lifetime constant prop\s+(\d+)', 5) test.file_grep(test.stats, r'Optimizations, Lifetime postassign deletions\s+(\d+)', 1) diff --git a/test_regress/t/t_opt_life.v b/test_regress/t/t_opt_life.v index d6aa4e605..7faa743f5 100644 --- a/test_regress/t/t_opt_life.v +++ b/test_regress/t/t_opt_life.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_life_dpi_written.cpp b/test_regress/t/t_opt_life_dpi_written.cpp new file mode 100644 index 000000000..274344eec --- /dev/null +++ b/test_regress/t/t_opt_life_dpi_written.cpp @@ -0,0 +1,21 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026-2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#include "svdpi.h" + +#include + +extern "C" void setDpi(int value); + +extern "C" void setViaDpi(int value) { + std::cout << "setViaDpi " << value << std::endl; + setDpi(value); +} diff --git a/test_regress/t/t_opt_life_dpi_written.py b/test_regress/t/t_opt_life_dpi_written.py new file mode 100755 index 000000000..ea2bf11a3 --- /dev/null +++ b/test_regress/t/t_opt_life_dpi_written.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--binary", "--stats", test.top_filename.replace(".v", ".cpp")]) + +test.execute() + +test.file_grep_not(test.stats, r'Optimizations, Lifetime constant prop') +test.file_grep_not(test.stats, r'Optimizations, Lifetime assign deletions') + +test.passes() diff --git a/test_regress/t/t_opt_life_dpi_written.v b/test_regress/t/t_opt_life_dpi_written.v new file mode 100644 index 000000000..a4bc6e3c0 --- /dev/null +++ b/test_regress/t/t_opt_life_dpi_written.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define check(got,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (got), (exp)); `stop; end while(0) +// verilog_format: on + +module t; + + int dpiSet = 0; + function automatic void setDpi(int value); + dpiSet = value; + endfunction + export "DPI-C" function setDpi; + import "DPI-C" context function void setViaDpi(int value); // calls setDpi(value) + + initial begin + dpiSet = 13; + setViaDpi(14); + `check(dpiSet, 14); + dpiSet = 15; + setViaDpi(16); + `check(dpiSet, 16); + dpiSet = 17; + setViaDpi(18); + `check(dpiSet, 18); + end + +endmodule diff --git a/test_regress/t/t_opt_life_off.py b/test_regress/t/t_opt_life_off.py index 0168042a7..cb69d4615 100755 --- a/test_regress/t/t_opt_life_off.py +++ b/test_regress/t/t_opt_life_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_life_timing_loop.py b/test_regress/t/t_opt_life_timing_loop.py index 19217b264..57ca11af7 100755 --- a/test_regress/t/t_opt_life_timing_loop.py +++ b/test_regress/t/t_opt_life_timing_loop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_life_timing_loop.v b/test_regress/t/t_opt_life_timing_loop.v index c2d1e36bb..478f79bb0 100644 --- a/test_regress/t/t_opt_life_timing_loop.v +++ b/test_regress/t/t_opt_life_timing_loop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_opt_localize_deep.py b/test_regress/t/t_opt_localize_deep.py index 539f320b1..84c09a3bb 100755 --- a/test_regress/t/t_opt_localize_deep.py +++ b/test_regress/t/t_opt_localize_deep.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_localize_deep.v b/test_regress/t/t_opt_localize_deep.v index 9d99620c7..19568bb26 100644 --- a/test_regress/t/t_opt_localize_deep.v +++ b/test_regress/t/t_opt_localize_deep.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 `ifdef verilator diff --git a/test_regress/t/t_opt_localize_max_size.py b/test_regress/t/t_opt_localize_max_size.py index 5e20fde4b..66dc26dc9 100755 --- a/test_regress/t/t_opt_localize_max_size.py +++ b/test_regress/t/t_opt_localize_max_size.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_localize_max_size.v b/test_regress/t/t_opt_localize_max_size.v index 4a8239462..ae2d48d67 100644 --- a/test_regress/t/t_opt_localize_max_size.v +++ b/test_regress/t/t_opt_localize_max_size.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_opt_localize_max_size_1.py b/test_regress/t/t_opt_localize_max_size_1.py index e5b1e38e1..ab5b04e28 100755 --- a/test_regress/t/t_opt_localize_max_size_1.py +++ b/test_regress/t/t_opt_localize_max_size_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_merge_cond.py b/test_regress/t/t_opt_merge_cond.py index 34bb401c0..cd68237be 100755 --- a/test_regress/t/t_opt_merge_cond.py +++ b/test_regress/t/t_opt_merge_cond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_merge_cond.v b/test_regress/t/t_opt_merge_cond.v index ef1b25e3d..61aaa624a 100644 --- a/test_regress/t/t_opt_merge_cond.v +++ b/test_regress/t/t_opt_merge_cond.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_opt_merge_cond_blowup.py b/test_regress/t/t_opt_merge_cond_blowup.py index 9602f04f6..eadc43963 100755 --- a/test_regress/t/t_opt_merge_cond_blowup.py +++ b/test_regress/t/t_opt_merge_cond_blowup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_merge_cond_blowup.v b/test_regress/t/t_opt_merge_cond_blowup.v index aa97f8f26..57927db99 100644 --- a/test_regress/t/t_opt_merge_cond_blowup.v +++ b/test_regress/t/t_opt_merge_cond_blowup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_merge_cond_bug_3409.py b/test_regress/t/t_opt_merge_cond_bug_3409.py index e5bc05874..b352fb2c0 100755 --- a/test_regress/t/t_opt_merge_cond_bug_3409.py +++ b/test_regress/t/t_opt_merge_cond_bug_3409.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_merge_cond_bug_3409.v b/test_regress/t/t_opt_merge_cond_bug_3409.v index 938e1fa9f..f8713e16b 100644 --- a/test_regress/t/t_opt_merge_cond_bug_3409.v +++ b/test_regress/t/t_opt_merge_cond_bug_3409.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Raynard Qiao. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Raynard Qiao // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_opt_merge_cond_motion_branch.py b/test_regress/t/t_opt_merge_cond_motion_branch.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_opt_merge_cond_motion_branch.py +++ b/test_regress/t/t_opt_merge_cond_motion_branch.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_merge_cond_motion_branch.v b/test_regress/t/t_opt_merge_cond_motion_branch.v index 73a538df0..990b4ec07 100644 --- a/test_regress/t/t_opt_merge_cond_motion_branch.v +++ b/test_regress/t/t_opt_merge_cond_motion_branch.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Based on ivtest's pr540.v by Steve Williams. diff --git a/test_regress/t/t_opt_merge_cond_no_extend.py b/test_regress/t/t_opt_merge_cond_no_extend.py index d85958438..5ff16e18e 100755 --- a/test_regress/t/t_opt_merge_cond_no_extend.py +++ b/test_regress/t/t_opt_merge_cond_no_extend.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_merge_cond_no_extend.v b/test_regress/t/t_opt_merge_cond_no_extend.v index ede818af3..bcff66546 100644 --- a/test_regress/t/t_opt_merge_cond_no_extend.v +++ b/test_regress/t/t_opt_merge_cond_no_extend.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_opt_merge_cond_no_merge.py b/test_regress/t/t_opt_merge_cond_no_merge.py index 43bbd8373..400394df9 100755 --- a/test_regress/t/t_opt_merge_cond_no_merge.py +++ b/test_regress/t/t_opt_merge_cond_no_merge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_merge_cond_no_motion.py b/test_regress/t/t_opt_merge_cond_no_motion.py index 39f083624..88b894b75 100755 --- a/test_regress/t/t_opt_merge_cond_no_motion.py +++ b/test_regress/t/t_opt_merge_cond_no_motion.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_redor.py b/test_regress/t/t_opt_redor.py index 0739b468a..9abf44601 100755 --- a/test_regress/t/t_opt_redor.py +++ b/test_regress/t/t_opt_redor.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_redor.v b/test_regress/t/t_opt_redor.v index b902bcdca..c42c90824 100644 --- a/test_regress/t/t_opt_redor.v +++ b/test_regress/t/t_opt_redor.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_slice.py b/test_regress/t/t_opt_slice.py index b5ce94197..b77291069 100755 --- a/test_regress/t/t_opt_slice.py +++ b/test_regress/t/t_opt_slice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_slice.v b/test_regress/t/t_opt_slice.v index 92ac3dd37..4a6c095e0 100644 --- a/test_regress/t/t_opt_slice.v +++ b/test_regress/t/t_opt_slice.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_slice_element_limit.py b/test_regress/t/t_opt_slice_element_limit.py index 65eb02d55..f5dd17ce1 100755 --- a/test_regress/t/t_opt_slice_element_limit.py +++ b/test_regress/t/t_opt_slice_element_limit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_slice_element_limit.v b/test_regress/t/t_opt_slice_element_limit.v index 428dc1eec..b69a3eff3 100644 --- a/test_regress/t/t_opt_slice_element_limit.v +++ b/test_regress/t/t_opt_slice_element_limit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_opt_slice_element_limit_allow_all.py b/test_regress/t/t_opt_slice_element_limit_allow_all.py index 48a349457..037614d4b 100755 --- a/test_regress/t/t_opt_slice_element_limit_allow_all.py +++ b/test_regress/t/t_opt_slice_element_limit_allow_all.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_slice_element_limit_bad.py b/test_regress/t/t_opt_slice_element_limit_bad.py index aad29f286..e64abba0f 100755 --- a/test_regress/t/t_opt_slice_element_limit_bad.py +++ b/test_regress/t/t_opt_slice_element_limit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_slice_element_limit_default.py b/test_regress/t/t_opt_slice_element_limit_default.py index 31df49d90..7d6d1ceee 100755 --- a/test_regress/t/t_opt_slice_element_limit_default.py +++ b/test_regress/t/t_opt_slice_element_limit_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_slice_no.py b/test_regress/t/t_opt_slice_no.py index 3ee92e4e0..4348edaec 100755 --- a/test_regress/t/t_opt_slice_no.py +++ b/test_regress/t/t_opt_slice_no.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_subst.py b/test_regress/t/t_opt_subst.py index 5705e1fad..b013d8319 100755 --- a/test_regress/t/t_opt_subst.py +++ b/test_regress/t/t_opt_subst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -14,7 +14,13 @@ test.scenarios('simulator_st') test.compile(verilator_flags2=["--stats"]) if test.vlt_all: - test.file_grep(test.stats, r'Optimizations, Substituted temps\s+(\d+)', 43) + test.file_grep(test.stats, r'Optimizations, Subst, Constant words reinlined\s+(\d+)', 156) + test.file_grep(test.stats, r'Optimizations, Subst, Substituted temps\s+(\d+)', 225) + test.file_grep(test.stats, r'Optimizations, Subst, Whole variable assignments deleted\s+(\d+)', + 1) + test.file_grep(test.stats, r'Optimizations, Subst, Whole variables substituted\s+(\d+)', 1) + test.file_grep(test.stats, r'Optimizations, Subst, Word assignments deleted\s+(\d+)', 68) + test.file_grep(test.stats, r'Optimizations, Subst, Words substituted\s+(\d+)', 68) test.execute() diff --git a/test_regress/t/t_opt_subst.v b/test_regress/t/t_opt_subst.v index 8fc9c32f9..f2b761190 100644 --- a/test_regress/t/t_opt_subst.v +++ b/test_regress/t/t_opt_subst.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2025 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t ( @@ -12,6 +12,7 @@ module t ( integer i; reg [94:0] w95; + reg [399:0] w400; integer cyc = 0; @@ -24,6 +25,7 @@ module t ( if (cyc == 0) begin // Setup w95 = {95{1'b1}}; + w400 = '1; end else if (cyc == 1) begin if (w95++ != {95{1'b1}}) $stop; @@ -34,6 +36,15 @@ module t ( if (w95 != {95{1'b0}}) $stop; if (--w95 != {95{1'b1}}) $stop; if (w95 != {95{1'b1}}) $stop; + + if (w400++ != {400{1'b1}}) $stop; + if (w400 != {400{1'b0}}) $stop; + if (w400-- != {400{1'b0}}) $stop; + if (w400 != {400{1'b1}}) $stop; + if (++w400 != {400{1'b0}}) $stop; + if (w400 != {400{1'b0}}) $stop; + if (--w400 != {400{1'b1}}) $stop; + if (w400 != {400{1'b1}}) $stop; end else if (cyc == 99) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_opt_subst_off.py b/test_regress/t/t_opt_subst_off.py index 509036fe2..c59b32156 100755 --- a/test_regress/t/t_opt_subst_off.py +++ b/test_regress/t/t_opt_subst_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -15,6 +15,6 @@ test.top_filename = "t/t_opt_life.v" test.compile(verilator_flags2=['--stats', '-fno-subst', '-fno-subst-const']) if test.vlt_all: - test.file_grep_not(test.stats, r'Optimizations, Substituted temps\s+(\d+)') + test.file_grep_not(test.stats, r'Optimizations, Subst,') test.passes() diff --git a/test_regress/t/t_opt_table_display.py b/test_regress/t/t_opt_table_display.py index e8fd08599..000166723 100755 --- a/test_regress/t/t_opt_table_display.py +++ b/test_regress/t/t_opt_table_display.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_display.v b/test_regress/t/t_opt_table_display.v index 19fbe03ad..6c859ca45 100644 --- a/test_regress/t/t_opt_table_display.v +++ b/test_regress/t/t_opt_table_display.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_table_enum.py b/test_regress/t/t_opt_table_enum.py index 912dd4cf8..5908d7cde 100755 --- a/test_regress/t/t_opt_table_enum.py +++ b/test_regress/t/t_opt_table_enum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_enum.v b/test_regress/t/t_opt_table_enum.v index 538cf3bea..7b31a3331 100644 --- a/test_regress/t/t_opt_table_enum.v +++ b/test_regress/t/t_opt_table_enum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_table_fsm.py b/test_regress/t/t_opt_table_fsm.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_opt_table_fsm.py +++ b/test_regress/t/t_opt_table_fsm.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_fsm.v b/test_regress/t/t_opt_table_fsm.v index 79a8a524f..bd9e3d66e 100644 --- a/test_regress/t/t_opt_table_fsm.v +++ b/test_regress/t/t_opt_table_fsm.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_table_packed_array.py b/test_regress/t/t_opt_table_packed_array.py index 912dd4cf8..5908d7cde 100755 --- a/test_regress/t/t_opt_table_packed_array.py +++ b/test_regress/t/t_opt_table_packed_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_packed_array.v b/test_regress/t/t_opt_table_packed_array.v index 9cd2d5508..b06fb0d32 100644 --- a/test_regress/t/t_opt_table_packed_array.v +++ b/test_regress/t/t_opt_table_packed_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_table_real.py b/test_regress/t/t_opt_table_real.py index 912dd4cf8..5908d7cde 100755 --- a/test_regress/t/t_opt_table_real.py +++ b/test_regress/t/t_opt_table_real.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_real.v b/test_regress/t/t_opt_table_real.v index b77c95557..4f7e730bc 100644 --- a/test_regress/t/t_opt_table_real.v +++ b/test_regress/t/t_opt_table_real.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Arthur Rosa // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_opt_table_real_off.py b/test_regress/t/t_opt_table_real_off.py index effecdb53..fbe8fd693 100755 --- a/test_regress/t/t_opt_table_real_off.py +++ b/test_regress/t/t_opt_table_real_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_same.py b/test_regress/t/t_opt_table_same.py index 622bd1b1b..2cee4586a 100755 --- a/test_regress/t/t_opt_table_same.py +++ b/test_regress/t/t_opt_table_same.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_same.v b/test_regress/t/t_opt_table_same.v index c2317dce0..1695187bc 100644 --- a/test_regress/t/t_opt_table_same.v +++ b/test_regress/t/t_opt_table_same.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_table_signed.py b/test_regress/t/t_opt_table_signed.py index 912dd4cf8..5908d7cde 100755 --- a/test_regress/t/t_opt_table_signed.py +++ b/test_regress/t/t_opt_table_signed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_signed.v b/test_regress/t/t_opt_table_signed.v index 8dbd80a98..95108bdd1 100644 --- a/test_regress/t/t_opt_table_signed.v +++ b/test_regress/t/t_opt_table_signed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_table_sparse.py b/test_regress/t/t_opt_table_sparse.py index 9d5ac0261..4563aa80d 100755 --- a/test_regress/t/t_opt_table_sparse.py +++ b/test_regress/t/t_opt_table_sparse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_sparse.v b/test_regress/t/t_opt_table_sparse.v index 3145d3c19..e9647baec 100644 --- a/test_regress/t/t_opt_table_sparse.v +++ b/test_regress/t/t_opt_table_sparse.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_table_sparse_output_split.py b/test_regress/t/t_opt_table_sparse_output_split.py index bc87cb9fc..3205c18ab 100755 --- a/test_regress/t/t_opt_table_sparse_output_split.py +++ b/test_regress/t/t_opt_table_sparse_output_split.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_string.py b/test_regress/t/t_opt_table_string.py index 912dd4cf8..5908d7cde 100755 --- a/test_regress/t/t_opt_table_string.py +++ b/test_regress/t/t_opt_table_string.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_string.v b/test_regress/t/t_opt_table_string.v index 11c6999ea..1b91b0c77 100644 --- a/test_regress/t/t_opt_table_string.v +++ b/test_regress/t/t_opt_table_string.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_opt_table_struct.py b/test_regress/t/t_opt_table_struct.py index 912dd4cf8..5908d7cde 100755 --- a/test_regress/t/t_opt_table_struct.py +++ b/test_regress/t/t_opt_table_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_opt_table_struct.v b/test_regress/t/t_opt_table_struct.v index f27f1eef6..25e1f6072 100644 --- a/test_regress/t/t_opt_table_struct.v +++ b/test_regress/t/t_opt_table_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order.py b/test_regress/t/t_order.py index 77acf6161..de3ece11f 100755 --- a/test_regress/t/t_order.py +++ b/test_regress/t/t_order.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order.v b/test_regress/t/t_order.v index 14276f6ba..04359f5d0 100644 --- a/test_regress/t/t_order.v +++ b/test_regress/t/t_order.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order_2d.py b/test_regress/t/t_order_2d.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_order_2d.py +++ b/test_regress/t/t_order_2d.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_2d.v b/test_regress/t/t_order_2d.v index 4836e969c..773de764b 100644 --- a/test_regress/t/t_order_2d.v +++ b/test_regress/t/t_order_2d.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order_a.v b/test_regress/t/t_order_a.v index 2cad003f6..839c3ace7 100644 --- a/test_regress/t/t_order_a.v +++ b/test_regress/t/t_order_a.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_order_a (/*AUTOARG*/ diff --git a/test_regress/t/t_order_b.v b/test_regress/t/t_order_b.v index b941580ae..1229ad2a9 100644 --- a/test_regress/t/t_order_b.v +++ b/test_regress/t/t_order_b.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_order_b (/*AUTOARG*/ diff --git a/test_regress/t/t_order_blkandnblk_bad.py b/test_regress/t/t_order_blkandnblk_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_order_blkandnblk_bad.py +++ b/test_regress/t/t_order_blkandnblk_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_blkandnblk_bad.v b/test_regress/t/t_order_blkandnblk_bad.v index 32506aca1..b7f19e3bc 100644 --- a/test_regress/t/t_order_blkandnblk_bad.v +++ b/test_regress/t/t_order_blkandnblk_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order_blkloopinit_bad.py b/test_regress/t/t_order_blkloopinit_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_order_blkloopinit_bad.py +++ b/test_regress/t/t_order_blkloopinit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_blkloopinit_bad.v b/test_regress/t/t_order_blkloopinit_bad.v index 74725cbf7..671a78a60 100644 --- a/test_regress/t/t_order_blkloopinit_bad.v +++ b/test_regress/t/t_order_blkloopinit_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTIDRIVEN diff --git a/test_regress/t/t_order_clkinst.py b/test_regress/t/t_order_clkinst.py index 9e12d32c2..0a7133fe3 100755 --- a/test_regress/t/t_order_clkinst.py +++ b/test_regress/t/t_order_clkinst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_clkinst.v b/test_regress/t/t_order_clkinst.v index 2b0bf2509..e58e2479c 100644 --- a/test_regress/t/t_order_clkinst.v +++ b/test_regress/t/t_order_clkinst.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order_comboclkloop.py b/test_regress/t/t_order_comboclkloop.py index dc6cab445..c02254607 100755 --- a/test_regress/t/t_order_comboclkloop.py +++ b/test_regress/t/t_order_comboclkloop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_comboclkloop.v b/test_regress/t/t_order_comboclkloop.v index 52185ca0c..e99f19af3 100644 --- a/test_regress/t/t_order_comboclkloop.v +++ b/test_regress/t/t_order_comboclkloop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order_comboloop.py b/test_regress/t/t_order_comboloop.py index dc6cab445..c02254607 100755 --- a/test_regress/t/t_order_comboloop.py +++ b/test_regress/t/t_order_comboloop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_comboloop.v b/test_regress/t/t_order_comboloop.v index 565597484..f9ce7bca8 100644 --- a/test_regress/t/t_order_comboloop.v +++ b/test_regress/t/t_order_comboloop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order_doubleloop.py b/test_regress/t/t_order_doubleloop.py index dc6cab445..c02254607 100755 --- a/test_regress/t/t_order_doubleloop.py +++ b/test_regress/t/t_order_doubleloop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_doubleloop.v b/test_regress/t/t_order_doubleloop.v index d5ffae5f8..bbd008556 100644 --- a/test_regress/t/t_order_doubleloop.v +++ b/test_regress/t/t_order_doubleloop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order_dpi_export_1.cpp b/test_regress/t/t_order_dpi_export_1.cpp index 2902ae32f..9f2fab1bf 100644 --- a/test_regress/t/t_order_dpi_export_1.cpp +++ b/test_regress/t/t_order_dpi_export_1.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_order_dpi_export_1.py b/test_regress/t/t_order_dpi_export_1.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_order_dpi_export_1.py +++ b/test_regress/t/t_order_dpi_export_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_dpi_export_1.v b/test_regress/t/t_order_dpi_export_1.v index cb608bad3..85edfea8b 100644 --- a/test_regress/t/t_order_dpi_export_1.v +++ b/test_regress/t/t_order_dpi_export_1.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench; diff --git a/test_regress/t/t_order_dpi_export_2.cpp b/test_regress/t/t_order_dpi_export_2.cpp index ca68903cd..c50f725d3 100644 --- a/test_regress/t/t_order_dpi_export_2.cpp +++ b/test_regress/t/t_order_dpi_export_2.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_order_dpi_export_2.py b/test_regress/t/t_order_dpi_export_2.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_order_dpi_export_2.py +++ b/test_regress/t/t_order_dpi_export_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_dpi_export_2.v b/test_regress/t/t_order_dpi_export_2.v index be8af3616..4f2efe691 100644 --- a/test_regress/t/t_order_dpi_export_2.v +++ b/test_regress/t/t_order_dpi_export_2.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( diff --git a/test_regress/t/t_order_dpi_export_3.cpp b/test_regress/t/t_order_dpi_export_3.cpp index 46087bafe..61ef97f38 100644 --- a/test_regress/t/t_order_dpi_export_3.cpp +++ b/test_regress/t/t_order_dpi_export_3.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_order_dpi_export_3.py b/test_regress/t/t_order_dpi_export_3.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_order_dpi_export_3.py +++ b/test_regress/t/t_order_dpi_export_3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_dpi_export_3.v b/test_regress/t/t_order_dpi_export_3.v index 49a41e235..f326e690f 100644 --- a/test_regress/t/t_order_dpi_export_3.v +++ b/test_regress/t/t_order_dpi_export_3.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( diff --git a/test_regress/t/t_order_dpi_export_4.cpp b/test_regress/t/t_order_dpi_export_4.cpp index 370bdb1c5..5f0e16dbe 100644 --- a/test_regress/t/t_order_dpi_export_4.cpp +++ b/test_regress/t/t_order_dpi_export_4.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_order_dpi_export_4.py b/test_regress/t/t_order_dpi_export_4.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_order_dpi_export_4.py +++ b/test_regress/t/t_order_dpi_export_4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_dpi_export_4.v b/test_regress/t/t_order_dpi_export_4.v index f0ad6ae66..808066a7d 100644 --- a/test_regress/t/t_order_dpi_export_4.v +++ b/test_regress/t/t_order_dpi_export_4.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( diff --git a/test_regress/t/t_order_dpi_export_5.cpp b/test_regress/t/t_order_dpi_export_5.cpp index e043b2bd0..2977049f5 100644 --- a/test_regress/t/t_order_dpi_export_5.cpp +++ b/test_regress/t/t_order_dpi_export_5.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_order_dpi_export_5.py b/test_regress/t/t_order_dpi_export_5.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_order_dpi_export_5.py +++ b/test_regress/t/t_order_dpi_export_5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_dpi_export_5.v b/test_regress/t/t_order_dpi_export_5.v index 355a606d7..f498708ab 100644 --- a/test_regress/t/t_order_dpi_export_5.v +++ b/test_regress/t/t_order_dpi_export_5.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2021 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( diff --git a/test_regress/t/t_order_dpi_export_6.cpp b/test_regress/t/t_order_dpi_export_6.cpp index 048447f2c..8e54d032c 100644 --- a/test_regress/t/t_order_dpi_export_6.cpp +++ b/test_regress/t/t_order_dpi_export_6.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_order_dpi_export_6.py b/test_regress/t/t_order_dpi_export_6.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_order_dpi_export_6.py +++ b/test_regress/t/t_order_dpi_export_6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_dpi_export_6.v b/test_regress/t/t_order_dpi_export_6.v index b49c5c879..b9fa2a6fa 100644 --- a/test_regress/t/t_order_dpi_export_6.v +++ b/test_regress/t/t_order_dpi_export_6.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( diff --git a/test_regress/t/t_order_dpi_export_7.cpp b/test_regress/t/t_order_dpi_export_7.cpp index 0649d2e97..73043298b 100644 --- a/test_regress/t/t_order_dpi_export_7.cpp +++ b/test_regress/t/t_order_dpi_export_7.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_order_dpi_export_7.py b/test_regress/t/t_order_dpi_export_7.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_order_dpi_export_7.py +++ b/test_regress/t/t_order_dpi_export_7.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_dpi_export_7.v b/test_regress/t/t_order_dpi_export_7.v index 575b88b50..bc6b5edcf 100644 --- a/test_regress/t/t_order_dpi_export_7.v +++ b/test_regress/t/t_order_dpi_export_7.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench; diff --git a/test_regress/t/t_order_dpi_export_8.cpp b/test_regress/t/t_order_dpi_export_8.cpp index 824aa58bf..28626f656 100644 --- a/test_regress/t/t_order_dpi_export_8.cpp +++ b/test_regress/t/t_order_dpi_export_8.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_order_dpi_export_8.py b/test_regress/t/t_order_dpi_export_8.py index 38f29b4e6..8ef3e1cf8 100755 --- a/test_regress/t/t_order_dpi_export_8.py +++ b/test_regress/t/t_order_dpi_export_8.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_dpi_export_8.v b/test_regress/t/t_order_dpi_export_8.v index 2df1a3e9b..b9493c710 100644 --- a/test_regress/t/t_order_dpi_export_8.v +++ b/test_regress/t/t_order_dpi_export_8.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module testbench( diff --git a/test_regress/t/t_order_first.py b/test_regress/t/t_order_first.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_order_first.py +++ b/test_regress/t/t_order_first.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_first.v b/test_regress/t/t_order_first.v index eaf1403ee..970a9c1dc 100644 --- a/test_regress/t/t_order_first.v +++ b/test_regress/t/t_order_first.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order_loop_bad.py b/test_regress/t/t_order_loop_bad.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_order_loop_bad.py +++ b/test_regress/t/t_order_loop_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_loop_bad.v b/test_regress/t/t_order_loop_bad.v index 2372d90a0..45749302d 100644 --- a/test_regress/t/t_order_loop_bad.v +++ b/test_regress/t/t_order_loop_bad.v @@ -6,8 +6,8 @@ // // This is a regression test against issue #513. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order_multialways.py b/test_regress/t/t_order_multialways.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_order_multialways.py +++ b/test_regress/t/t_order_multialways.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_multialways.v b/test_regress/t/t_order_multialways.v index 46c67d672..3686c1504 100644 --- a/test_regress/t/t_order_multialways.v +++ b/test_regress/t/t_order_multialways.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_order_multidriven.cpp b/test_regress/t/t_order_multidriven.cpp index 284330498..69357e058 100644 --- a/test_regress/t/t_order_multidriven.cpp +++ b/test_regress/t/t_order_multidriven.cpp @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Ted Campbell. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Ted Campbell // SPDX-License-Identifier: CC0-1.0 #include "verilated.h" diff --git a/test_regress/t/t_order_multidriven.py b/test_regress/t/t_order_multidriven.py index 202e6a897..6bff8cd57 100755 --- a/test_regress/t/t_order_multidriven.py +++ b/test_regress/t/t_order_multidriven.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_multidriven.v b/test_regress/t/t_order_multidriven.v index 04ba843e4..e26c5d14e 100644 --- a/test_regress/t/t_order_multidriven.v +++ b/test_regress/t/t_order_multidriven.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Ted Campbell. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Ted Campbell // SPDX-License-Identifier: CC0-1.0 //With MULTI_CLK defined shows bug, without it is hidden diff --git a/test_regress/t/t_order_quad.cpp b/test_regress/t/t_order_quad.cpp index e15584148..61e4bee44 100644 --- a/test_regress/t/t_order_quad.cpp +++ b/test_regress/t/t_order_quad.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_order_quad.py b/test_regress/t/t_order_quad.py index 94dfdc72f..9ec50ba9b 100755 --- a/test_regress/t/t_order_quad.py +++ b/test_regress/t/t_order_quad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_quad.v b/test_regress/t/t_order_quad.v index 8652b8d05..1d23f39ba 100644 --- a/test_regress/t/t_order_quad.v +++ b/test_regress/t/t_order_quad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See issue #762 diff --git a/test_regress/t/t_order_timing.py b/test_regress/t/t_order_timing.py index cee17e347..9131fbe59 100755 --- a/test_regress/t/t_order_timing.py +++ b/test_regress/t/t_order_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_wireloop.py b/test_regress/t/t_order_wireloop.py index a96c62185..033891113 100755 --- a/test_regress/t/t_order_wireloop.py +++ b/test_regress/t/t_order_wireloop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_order_wireloop.v b/test_regress/t/t_order_wireloop.v index a98131e99..2749a4033 100644 --- a/test_regress/t/t_order_wireloop.v +++ b/test_regress/t/t_order_wireloop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_package.py b/test_regress/t/t_package.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_package.py +++ b/test_regress/t/t_package.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package.v b/test_regress/t/t_package.v index db29474f6..99d559c4e 100644 --- a/test_regress/t/t_package.v +++ b/test_regress/t/t_package.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef int unit_type_t; @@ -66,7 +66,7 @@ module t2; package_type_t vp; package2_type_t vp2; initial begin - bit x = realCompare(1.0); + automatic bit x = realCompare(1.0); if (plusone(1) !== 2) $stop; if (plustwo(1) !== 3) $stop; if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value diff --git a/test_regress/t/t_package_abs.py b/test_regress/t/t_package_abs.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_package_abs.py +++ b/test_regress/t/t_package_abs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_abs.v b/test_regress/t/t_package_abs.v index fa63ba7a1..5ea79a8e3 100644 --- a/test_regress/t/t_package_abs.v +++ b/test_regress/t/t_package_abs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // see bug491 diff --git a/test_regress/t/t_package_alone_bad.py b/test_regress/t/t_package_alone_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_package_alone_bad.py +++ b/test_regress/t/t_package_alone_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_alone_bad.v b/test_regress/t/t_package_alone_bad.v index 34adc1b82..c2ba3e5af 100644 --- a/test_regress/t/t_package_alone_bad.v +++ b/test_regress/t/t_package_alone_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 export pkg::something; diff --git a/test_regress/t/t_package_ddecl.py b/test_regress/t/t_package_ddecl.py index 46560bc9c..346ef8602 100755 --- a/test_regress/t/t_package_ddecl.py +++ b/test_regress/t/t_package_ddecl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_ddecl.v b/test_regress/t/t_package_ddecl.v index 57e057c50..03cedbe40 100644 --- a/test_regress/t/t_package_ddecl.v +++ b/test_regress/t/t_package_ddecl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See issue #474 diff --git a/test_regress/t/t_package_ddecl_timing.py b/test_regress/t/t_package_ddecl_timing.py index e1e20eb67..dd5c6535c 100755 --- a/test_regress/t/t_package_ddecl_timing.py +++ b/test_regress/t/t_package_ddecl_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_dimport.py b/test_regress/t/t_package_dimport.py index d474feea7..e45a78e3a 100755 --- a/test_regress/t/t_package_dimport.py +++ b/test_regress/t/t_package_dimport.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_dimport.v b/test_regress/t/t_package_dimport.v index a4dd4fd07..0e3cc60b7 100644 --- a/test_regress/t/t_package_dimport.v +++ b/test_regress/t/t_package_dimport.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package defs; diff --git a/test_regress/t/t_package_dot.py b/test_regress/t/t_package_dot.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_package_dot.py +++ b/test_regress/t/t_package_dot.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_dot.v b/test_regress/t/t_package_dot.v index 39fa6b1a9..61338d899 100644 --- a/test_regress/t/t_package_dot.v +++ b/test_regress/t/t_package_dot.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_package_dup_bad.py b/test_regress/t/t_package_dup_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_package_dup_bad.py +++ b/test_regress/t/t_package_dup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_dup_bad.v b/test_regress/t/t_package_dup_bad.v index 89d9e7edd..aef6858be 100644 --- a/test_regress/t/t_package_dup_bad.v +++ b/test_regress/t/t_package_dup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_package_dup_bad2.py b/test_regress/t/t_package_dup_bad2.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_package_dup_bad2.py +++ b/test_regress/t/t_package_dup_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_dup_bad2.v b/test_regress/t/t_package_dup_bad2.v index 8e265c9e7..32f1e8d27 100644 --- a/test_regress/t/t_package_dup_bad2.v +++ b/test_regress/t/t_package_dup_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg; diff --git a/test_regress/t/t_package_enum.py b/test_regress/t/t_package_enum.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_package_enum.py +++ b/test_regress/t/t_package_enum.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_enum.v b/test_regress/t/t_package_enum.v index 97ddf0255..1e89369e1 100644 --- a/test_regress/t/t_package_enum.v +++ b/test_regress/t/t_package_enum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_package_export.py b/test_regress/t/t_package_export.py index 06f34925c..ec6924ad0 100755 --- a/test_regress/t/t_package_export.py +++ b/test_regress/t/t_package_export.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_export.v b/test_regress/t/t_package_export.v index 342f98eda..99c79f289 100644 --- a/test_regress/t/t_package_export.v +++ b/test_regress/t/t_package_export.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 // See issue #591 diff --git a/test_regress/t/t_package_export_bad.py b/test_regress/t/t_package_export_bad.py index 593de1e5b..b5dce3077 100755 --- a/test_regress/t/t_package_export_bad.py +++ b/test_regress/t/t_package_export_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_export_bad2.py b/test_regress/t/t_package_export_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_package_export_bad2.py +++ b/test_regress/t/t_package_export_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_export_bad2.v b/test_regress/t/t_package_export_bad2.v index ae1ac13fe..7c7a305ea 100644 --- a/test_regress/t/t_package_export_bad2.v +++ b/test_regress/t/t_package_export_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg1; diff --git a/test_regress/t/t_package_identifier_bad.py b/test_regress/t/t_package_identifier_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_package_identifier_bad.py +++ b/test_regress/t/t_package_identifier_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_identifier_bad.v b/test_regress/t/t_package_identifier_bad.v index a3457cee5..d3e1605f3 100644 --- a/test_regress/t/t_package_identifier_bad.v +++ b/test_regress/t/t_package_identifier_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 package Foo; diff --git a/test_regress/t/t_package_import_bad2.py b/test_regress/t/t_package_import_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_package_import_bad2.py +++ b/test_regress/t/t_package_import_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_import_bad2.v b/test_regress/t/t_package_import_bad2.v index b2d4d0c36..e080d0c29 100644 --- a/test_regress/t/t_package_import_bad2.v +++ b/test_regress/t/t_package_import_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg1; diff --git a/test_regress/t/t_package_import_override.py b/test_regress/t/t_package_import_override.py index 6305a4fd8..34380009e 100755 --- a/test_regress/t/t_package_import_override.py +++ b/test_regress/t/t_package_import_override.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_import_override.v b/test_regress/t/t_package_import_override.v index 3c3e5d10c..43bacad17 100644 --- a/test_regress/t/t_package_import_override.v +++ b/test_regress/t/t_package_import_override.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_package_import_param.py b/test_regress/t/t_package_import_param.py index cca4c9e73..d6d35e7fd 100755 --- a/test_regress/t/t_package_import_param.py +++ b/test_regress/t/t_package_import_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_import_param.v b/test_regress/t/t_package_import_param.v index 9822d0e76..3d85e01da 100644 --- a/test_regress/t/t_package_import_param.v +++ b/test_regress/t/t_package_import_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package s_pkg; diff --git a/test_regress/t/t_package_local_bad.py b/test_regress/t/t_package_local_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_package_local_bad.py +++ b/test_regress/t/t_package_local_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_local_bad.v b/test_regress/t/t_package_local_bad.v index 99ff3ede4..24a574858 100644 --- a/test_regress/t/t_package_local_bad.v +++ b/test_regress/t/t_package_local_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_package_param.py b/test_regress/t/t_package_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_package_param.py +++ b/test_regress/t/t_package_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_param.v b/test_regress/t/t_package_param.v index c13eef367..736f58142 100644 --- a/test_regress/t/t_package_param.v +++ b/test_regress/t/t_package_param.v @@ -4,8 +4,8 @@ // definitions in wildcard imported packages (section 26.3). Thus the code // below is valid SystemVerilog. // -// This file ONLY is placed into the Public Domain, for any use, without -// warranty, 2013 by Jie Xu. +// This file ONLY is placed into the Public Domain. +// SPDX-FileCopyrightText: 2013 Jie Xu // SPDX-License-Identifier: CC0-1.0 package defs; diff --git a/test_regress/t/t_package_struct.py b/test_regress/t/t_package_struct.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_package_struct.py +++ b/test_regress/t/t_package_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_struct.v b/test_regress/t/t_package_struct.v index 9e9a93393..aafb2f24d 100644 --- a/test_regress/t/t_package_struct.v +++ b/test_regress/t/t_package_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_package_twodeep.py b/test_regress/t/t_package_twodeep.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_package_twodeep.py +++ b/test_regress/t/t_package_twodeep.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_twodeep.v b/test_regress/t/t_package_twodeep.v index 49dc83568..8218dd4bc 100644 --- a/test_regress/t/t_package_twodeep.v +++ b/test_regress/t/t_package_twodeep.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 // See issue #591 diff --git a/test_regress/t/t_package_using_dollar_unit.py b/test_regress/t/t_package_using_dollar_unit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_package_using_dollar_unit.py +++ b/test_regress/t/t_package_using_dollar_unit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_using_dollar_unit.v b/test_regress/t/t_package_using_dollar_unit.v index 2ccde8879..f7f987aa0 100644 --- a/test_regress/t/t_package_using_dollar_unit.v +++ b/test_regress/t/t_package_using_dollar_unit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_package_verb.py b/test_regress/t/t_package_verb.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_package_verb.py +++ b/test_regress/t/t_package_verb.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_package_verb.v b/test_regress/t/t_package_verb.v index e0fbdb094..63ad0c36b 100644 --- a/test_regress/t/t_package_verb.v +++ b/test_regress/t/t_package_verb.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug474 diff --git a/test_regress/t/t_packed_concat.v b/test_regress/t/t_packed_concat.v index 02b309750..036be30c1 100644 --- a/test_regress/t/t_packed_concat.v +++ b/test_regress/t/t_packed_concat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_packed_concat_bad.py b/test_regress/t/t_packed_concat_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_packed_concat_bad.py +++ b/test_regress/t/t_packed_concat_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_packed_concat_bad.v b/test_regress/t/t_packed_concat_bad.v index 37e2d381b..80e04362b 100644 --- a/test_regress/t/t_packed_concat_bad.v +++ b/test_regress/t/t_packed_concat_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param.py b/test_regress/t/t_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param.py +++ b/test_regress/t/t_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param.v b/test_regress/t/t_param.v index 3d0c68bea..0bb9354b1 100644 --- a/test_regress/t/t_param.v +++ b/test_regress/t/t_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_array.py b/test_regress/t/t_param_array.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_array.py +++ b/test_regress/t/t_param_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_array.v b/test_regress/t/t_param_array.v index f98ad281b..e321928d0 100644 --- a/test_regress/t/t_param_array.v +++ b/test_regress/t/t_param_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_array2.py b/test_regress/t/t_param_array2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_array2.py +++ b/test_regress/t/t_param_array2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_array2.v b/test_regress/t/t_param_array2.v index ee8e97c65..6d5fd05bc 100644 --- a/test_regress/t/t_param_array2.v +++ b/test_regress/t/t_param_array2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_array3.py b/test_regress/t/t_param_array3.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_array3.py +++ b/test_regress/t/t_param_array3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_array3.v b/test_regress/t/t_param_array3.v index 1be55ef14..0071cc5b9 100644 --- a/test_regress/t/t_param_array3.v +++ b/test_regress/t/t_param_array3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_array4.py b/test_regress/t/t_param_array4.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_array4.py +++ b/test_regress/t/t_param_array4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_array4.v b/test_regress/t/t_param_array4.v index 13626edc4..062ca3927 100644 --- a/test_regress/t/t_param_array4.v +++ b/test_regress/t/t_param_array4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_array5.py b/test_regress/t/t_param_array5.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_array5.py +++ b/test_regress/t/t_param_array5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_array5.v b/test_regress/t/t_param_array5.v index 356c051a3..4c4f9f354 100644 --- a/test_regress/t/t_param_array5.v +++ b/test_regress/t/t_param_array5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug1578 diff --git a/test_regress/t/t_param_array6.py b/test_regress/t/t_param_array6.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_array6.py +++ b/test_regress/t/t_param_array6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_array6.v b/test_regress/t/t_param_array6.v index 708935749..a2d24a8bf 100644 --- a/test_regress/t/t_param_array6.v +++ b/test_regress/t/t_param_array6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Anderson Ignacio da Silva. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2020 Anderson Ignacio da Silva // SPDX-License-Identifier: CC0-1.0 package test_pkg; diff --git a/test_regress/t/t_param_array6_noslice.py b/test_regress/t/t_param_array6_noslice.py index 79f955063..4a59ae5c1 100755 --- a/test_regress/t/t_param_array6_noslice.py +++ b/test_regress/t/t_param_array6_noslice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_array7.py b/test_regress/t/t_param_array7.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_array7.py +++ b/test_regress/t/t_param_array7.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_array7.v b/test_regress/t/t_param_array7.v index 821a16adc..be093cbca 100644 --- a/test_regress/t/t_param_array7.v +++ b/test_regress/t/t_param_array7.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: CC0-1.0 typedef struct packed { diff --git a/test_regress/t/t_param_array8.py b/test_regress/t/t_param_array8.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_array8.py +++ b/test_regress/t/t_param_array8.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_array8.v b/test_regress/t/t_param_array8.v index c19d4bba8..4e91b9d29 100644 --- a/test_regress/t/t_param_array8.v +++ b/test_regress/t/t_param_array8.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub diff --git a/test_regress/t/t_param_array9.py b/test_regress/t/t_param_array9.py index 147fe6faf..0379f0dd0 100755 --- a/test_regress/t/t_param_array9.py +++ b/test_regress/t/t_param_array9.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_array9.v b/test_regress/t/t_param_array9.v index 81f7a5ce0..d43b526e6 100644 --- a/test_regress/t/t_param_array9.v +++ b/test_regress/t/t_param_array9.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module p_i_match #( diff --git a/test_regress/t/t_param_avec.py b/test_regress/t/t_param_avec.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_avec.py +++ b/test_regress/t/t_param_avec.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_avec.v b/test_regress/t/t_param_avec.v index 87f70486d..6b00894d4 100644 --- a/test_regress/t/t_param_avec.v +++ b/test_regress/t/t_param_avec.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_param_bit_sel.py b/test_regress/t/t_param_bit_sel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_bit_sel.py +++ b/test_regress/t/t_param_bit_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_bit_sel.v b/test_regress/t/t_param_bit_sel.v index e76c43e44..fb27ce534 100644 --- a/test_regress/t/t_param_bit_sel.v +++ b/test_regress/t/t_param_bit_sel.v @@ -5,8 +5,8 @@ // // Other event drive simulators accept this. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_bracket.py b/test_regress/t/t_param_bracket.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_param_bracket.py +++ b/test_regress/t/t_param_bracket.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_bracket.v b/test_regress/t/t_param_bracket.v index b2890ad9a..1c39515f3 100644 --- a/test_regress/t/t_param_bracket.v +++ b/test_regress/t/t_param_bracket.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder; +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder; // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_param_ceil.py b/test_regress/t/t_param_ceil.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_ceil.py +++ b/test_regress/t/t_param_ceil.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_ceil.v b/test_regress/t/t_param_ceil.v index d6e7766ca..6123603a1 100644 --- a/test_regress/t/t_param_ceil.v +++ b/test_regress/t/t_param_ceil.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_chain.py b/test_regress/t/t_param_chain.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_chain.py +++ b/test_regress/t/t_param_chain.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_chain.v b/test_regress/t/t_param_chain.v index 3b10a889c..480a97377 100644 --- a/test_regress/t/t_param_chain.v +++ b/test_regress/t/t_param_chain.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_circ_bad.py b/test_regress/t/t_param_circ_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_param_circ_bad.py +++ b/test_regress/t/t_param_circ_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_circ_bad.v b/test_regress/t/t_param_circ_bad.v index f56a36a26..86fdcfd71 100644 --- a/test_regress/t/t_param_circ_bad.v +++ b/test_regress/t/t_param_circ_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_concat.py b/test_regress/t/t_param_concat.py index 8ecb93fe4..0f708235b 100755 --- a/test_regress/t/t_param_concat.py +++ b/test_regress/t/t_param_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_concat.v b/test_regress/t/t_param_concat.v index 4d86d79ce..20a660fd8 100644 --- a/test_regress/t/t_param_concat.v +++ b/test_regress/t/t_param_concat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_concat_bad.py b/test_regress/t/t_param_concat_bad.py index 65a84a628..40c495f81 100755 --- a/test_regress/t/t_param_concat_bad.py +++ b/test_regress/t/t_param_concat_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_const_part.py b/test_regress/t/t_param_const_part.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_const_part.py +++ b/test_regress/t/t_param_const_part.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_const_part.v b/test_regress/t/t_param_const_part.v index c4317a6d1..e66373059 100644 --- a/test_regress/t/t_param_const_part.v +++ b/test_regress/t/t_param_const_part.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_ddeep_width.py b/test_regress/t/t_param_ddeep_width.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_param_ddeep_width.py +++ b/test_regress/t/t_param_ddeep_width.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_ddeep_width.v b/test_regress/t/t_param_ddeep_width.v index 379a77e80..625650558 100644 --- a/test_regress/t/t_param_ddeep_width.v +++ b/test_regress/t/t_param_ddeep_width.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug541 diff --git a/test_regress/t/t_param_default.py b/test_regress/t/t_param_default.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_default.py +++ b/test_regress/t/t_param_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_default.v b/test_regress/t/t_param_default.v index 5928e4c49..2f664fd38 100644 --- a/test_regress/t/t_param_default.v +++ b/test_regress/t/t_param_default.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m #(parameter int Foo); diff --git a/test_regress/t/t_param_default_2.py b/test_regress/t/t_param_default_2.py index 6812c4542..b4df26891 100755 --- a/test_regress/t/t_param_default_2.py +++ b/test_regress/t/t_param_default_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_default_2.v b/test_regress/t/t_param_default_2.v index 67e747b4c..d6e89cdfe 100644 --- a/test_regress/t/t_param_default_2.v +++ b/test_regress/t/t_param_default_2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; diff --git a/test_regress/t/t_param_default_bad.py b/test_regress/t/t_param_default_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_param_default_bad.py +++ b/test_regress/t/t_param_default_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_default_bad.v b/test_regress/t/t_param_default_bad.v index 44e40af0a..8c49a0d9c 100644 --- a/test_regress/t/t_param_default_bad.v +++ b/test_regress/t/t_param_default_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module m #(parameter int Foo); diff --git a/test_regress/t/t_param_default_override.py b/test_regress/t/t_param_default_override.py index 116160a1a..6f4204c2e 100755 --- a/test_regress/t/t_param_default_override.py +++ b/test_regress/t/t_param_default_override.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_default_override.v b/test_regress/t/t_param_default_override.v index a618bbb27..65caaa4d4 100644 --- a/test_regress/t/t_param_default_override.v +++ b/test_regress/t/t_param_default_override.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Josse Van Delm. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Josse Van Delm // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH diff --git a/test_regress/t/t_param_default_presv_bad.py b/test_regress/t/t_param_default_presv_bad.py index 4730f0b37..a758dfc7e 100755 --- a/test_regress/t/t_param_default_presv_bad.py +++ b/test_regress/t/t_param_default_presv_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_first.py b/test_regress/t/t_param_first.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_first.py +++ b/test_regress/t/t_param_first.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_first.v b/test_regress/t/t_param_first.v index 2ef817ccb..083531dc6 100644 --- a/test_regress/t/t_param_first.v +++ b/test_regress/t/t_param_first.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_param_first_a.v b/test_regress/t/t_param_first_a.v index accad60bb..4898e07c3 100644 --- a/test_regress/t/t_param_first_a.v +++ b/test_regress/t/t_param_first_a.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_param_first_a (/*AUTOARG*/ diff --git a/test_regress/t/t_param_first_b.v b/test_regress/t/t_param_first_b.v index ab49f7be1..29a865180 100644 --- a/test_regress/t/t_param_first_b.v +++ b/test_regress/t/t_param_first_b.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_param_first_b (/*AUTOARG*/ diff --git a/test_regress/t/t_param_func.py b/test_regress/t/t_param_func.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_param_func.py +++ b/test_regress/t/t_param_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_func.v b/test_regress/t/t_param_func.v index 11b23acba..89c5dea51 100644 --- a/test_regress/t/t_param_func.v +++ b/test_regress/t/t_param_func.v @@ -3,8 +3,8 @@ // This test examines Verilator against paramter definition with functions. // Particularly the function takes in argument which is multi-dimentional. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Roland Kruse and Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Roland Kruse and Jie Xu // SPDX-License-Identifier: CC0-1.0 module test#( diff --git a/test_regress/t/t_param_func2.py b/test_regress/t/t_param_func2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_func2.py +++ b/test_regress/t/t_param_func2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_func2.v b/test_regress/t/t_param_func2.v index 1a4630d77..6893bb9d2 100644 --- a/test_regress/t/t_param_func2.v +++ b/test_regress/t/t_param_func2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_hier_bad.py b/test_regress/t/t_param_hier_bad.py index 14ad3403f..b3e527d04 100755 --- a/test_regress/t/t_param_hier_bad.py +++ b/test_regress/t/t_param_hier_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_hier_bad.v b/test_regress/t/t_param_hier_bad.v index d15aa44e1..1e1220371 100644 --- a/test_regress/t/t_param_hier_bad.v +++ b/test_regress/t/t_param_hier_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_param_if_blk.py b/test_regress/t/t_param_if_blk.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_if_blk.py +++ b/test_regress/t/t_param_if_blk.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_if_blk.v b/test_regress/t/t_param_if_blk.v index 5bacd5eb4..58e9a1d4c 100644 --- a/test_regress/t/t_param_if_blk.v +++ b/test_regress/t/t_param_if_blk.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2013 // SPDX-License-Identifier: CC0-1.0 // bug648 diff --git a/test_regress/t/t_param_implicit_bad.py b/test_regress/t/t_param_implicit_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_param_implicit_bad.py +++ b/test_regress/t/t_param_implicit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_implicit_bad.v b/test_regress/t/t_param_implicit_bad.v index dbbceda09..efb14fd4e 100644 --- a/test_regress/t/t_param_implicit_bad.v +++ b/test_regress/t/t_param_implicit_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // IEEE parameter_port_declaration has data_type but not data_type_or_implicit diff --git a/test_regress/t/t_param_implicit_local_bad.out b/test_regress/t/t_param_implicit_local_bad.out index 159b4f135..947d67592 100644 --- a/test_regress/t/t_param_implicit_local_bad.out +++ b/test_regress/t/t_param_implicit_local_bad.out @@ -5,19 +5,37 @@ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:17:21: Parameter not found: '__paramNumber3' 17 | mod1 # ( 3, 4, 5 ) i_mod1 (); | ^ + : ... Location of instance's module declaration + 26 | module mod1 # ( + | ^~~~ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:15: Parameter not found: '__paramNumber1' 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); | ^ + : ... Location of instance's module declaration + 38 | module mod3 #() (); + | ^~~~ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:18: Parameter not found: '__paramNumber2' 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); | ^~ + : ... Location of instance's module declaration + 38 | module mod3 #() (); + | ^~~~ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:19:22: Parameter not found: '__paramNumber3' 19 | mod3 # ( 7, 24, 25 ) i_mod3 (); | ^~ + : ... Location of instance's module declaration + 38 | module mod3 #() (); + | ^~~~ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:20:22: Parameter not found: '__paramNumber3' 20 | intf1 # ( 8, 15, 17 ) i_intf1 (); | ^~ + : ... Location of instance's interface declaration + 43 | interface intf1 # ( + | ^~~~~ %Error-PINNOTFOUND: t/t_param_implicit_local_bad.v:21:22: Parameter not found: '__paramNumber3' 21 | prgm1 # ( 9, 40, 41 ) i_prgm1 (); | ^~ + : ... Location of instance's program declaration + 50 | program prgm1 # ( + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_implicit_local_bad.py b/test_regress/t/t_param_implicit_local_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_param_implicit_local_bad.py +++ b/test_regress/t/t_param_implicit_local_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_implicit_local_bad.v b/test_regress/t/t_param_implicit_local_bad.v index a6252f77d..da3387e63 100644 --- a/test_regress/t/t_param_implicit_local_bad.v +++ b/test_regress/t/t_param_implicit_local_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_param_implicit_string.py b/test_regress/t/t_param_implicit_string.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_param_implicit_string.py +++ b/test_regress/t/t_param_implicit_string.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_implicit_string.v b/test_regress/t/t_param_implicit_string.v index 43f958bb7..8e59efe44 100644 --- a/test_regress/t/t_param_implicit_string.v +++ b/test_regress/t/t_param_implicit_string.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_param_in_func.py b/test_regress/t/t_param_in_func.py index e636de991..88c27220f 100755 --- a/test_regress/t/t_param_in_func.py +++ b/test_regress/t/t_param_in_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_in_func.v b/test_regress/t/t_param_in_func.v index 7300965b8..5f992e680 100644 --- a/test_regress/t/t_param_in_func.v +++ b/test_regress/t/t_param_in_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_in_func_noinline.py b/test_regress/t/t_param_in_func_noinline.py index 6fe5459f1..716aa43be 100755 --- a/test_regress/t/t_param_in_func_noinline.py +++ b/test_regress/t/t_param_in_func_noinline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_local.py b/test_regress/t/t_param_local.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_local.py +++ b/test_regress/t/t_param_local.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_local.v b/test_regress/t/t_param_local.v index ceb51cab7..374533079 100644 --- a/test_regress/t/t_param_local.v +++ b/test_regress/t/t_param_local.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_long.py b/test_regress/t/t_param_long.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_long.py +++ b/test_regress/t/t_param_long.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_long.v b/test_regress/t/t_param_long.v index fc1fecc10..706da0509 100644 --- a/test_regress/t/t_param_long.v +++ b/test_regress/t/t_param_long.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_mem_attr.py b/test_regress/t/t_param_mem_attr.py index 84ad9365e..15689f8e3 100755 --- a/test_regress/t/t_param_mem_attr.py +++ b/test_regress/t/t_param_mem_attr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_mem_attr.v b/test_regress/t/t_param_mem_attr.v index fcf44bc5a..3ffa00f87 100644 --- a/test_regress/t/t_param_mem_attr.v +++ b/test_regress/t/t_param_mem_attr.v @@ -12,8 +12,8 @@ // terminate called without an active exception // %Error: Verilator aborted. Consider trying --debug --gdbbt // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jie Xu // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_mintypmax.py b/test_regress/t/t_param_mintypmax.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_mintypmax.py +++ b/test_regress/t/t_param_mintypmax.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_mintypmax.v b/test_regress/t/t_param_mintypmax.v index 05fb78d89..3e1dec67a 100644 --- a/test_regress/t/t_param_mintypmax.v +++ b/test_regress/t/t_param_mintypmax.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_module.py b/test_regress/t/t_param_module.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_module.py +++ b/test_regress/t/t_param_module.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_module.v b/test_regress/t/t_param_module.v index c83a8e805..cb329a82d 100644 --- a/test_regress/t/t_param_module.v +++ b/test_regress/t/t_param_module.v @@ -10,8 +10,8 @@ // %Warning-ASCRANGE: t/t_param_module.v:42: Ascending bit range vector: MSB // < LSB of bit range: -17:0 // -// This file ONLY is placed into the Public Domain, for any use, without -// warranty, 2013 by Jie Xu. +// This file ONLY is placed into the Public Domain. +// SPDX-FileCopyrightText: 2013 Jie Xu // SPDX-License-Identifier: CC0-1.0 // bug606 diff --git a/test_regress/t/t_param_named.py b/test_regress/t/t_param_named.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_named.py +++ b/test_regress/t/t_param_named.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_named.v b/test_regress/t/t_param_named.v index 523b65138..f702bc05e 100644 --- a/test_regress/t/t_param_named.v +++ b/test_regress/t/t_param_named.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_named_2.py b/test_regress/t/t_param_named_2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_named_2.py +++ b/test_regress/t/t_param_named_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_named_2.v b/test_regress/t/t_param_named_2.v index d0682db1e..603a3eefc 100644 --- a/test_regress/t/t_param_named_2.v +++ b/test_regress/t/t_param_named_2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_no_parentheses.py b/test_regress/t/t_param_no_parentheses.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_no_parentheses.py +++ b/test_regress/t/t_param_no_parentheses.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_no_parentheses.v b/test_regress/t/t_param_no_parentheses.v index 2b644d4f6..66c3fb904 100644 --- a/test_regress/t/t_param_no_parentheses.v +++ b/test_regress/t/t_param_no_parentheses.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // This is a copy of t_param.v with the parentheses around the module parameters diff --git a/test_regress/t/t_param_noval_bad.py b/test_regress/t/t_param_noval_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_param_noval_bad.py +++ b/test_regress/t/t_param_noval_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_noval_bad.v b/test_regress/t/t_param_noval_bad.v index 61248d8ef..1a78f3561 100644 --- a/test_regress/t/t_param_noval_bad.v +++ b/test_regress/t/t_param_noval_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t #(parameter P, parameter type T); diff --git a/test_regress/t/t_param_package.py b/test_regress/t/t_param_package.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_package.py +++ b/test_regress/t/t_param_package.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_package.v b/test_regress/t/t_param_package.v index a51891452..9931091cc 100644 --- a/test_regress/t/t_param_package.v +++ b/test_regress/t/t_param_package.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_passed_to_port.py b/test_regress/t/t_param_passed_to_port.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_passed_to_port.py +++ b/test_regress/t/t_param_passed_to_port.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_passed_to_port.v b/test_regress/t/t_param_passed_to_port.v index 7b1fb67d5..ff971ed03 100644 --- a/test_regress/t/t_param_passed_to_port.v +++ b/test_regress/t/t_param_passed_to_port.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 parameter int HwDataAttr[1] = '{1}; @@ -10,7 +10,7 @@ module flash_mp_data_region_sel ( input int region_attrs_i[1] ); initial begin - int o = 0; + automatic int o = 0; for (int i = 0; i < 1; i++) begin o = region_attrs_i[i]; end diff --git a/test_regress/t/t_param_pattern.py b/test_regress/t/t_param_pattern.py index 835a031c1..fb0f79543 100755 --- a/test_regress/t/t_param_pattern.py +++ b/test_regress/t/t_param_pattern.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_pattern.v b/test_regress/t/t_param_pattern.v index 43df17942..7eca40b3f 100644 --- a/test_regress/t/t_param_pattern.v +++ b/test_regress/t/t_param_pattern.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Krzysztof Bieganski. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Krzysztof Bieganski // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_param_pattern2.py b/test_regress/t/t_param_pattern2.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_param_pattern2.py +++ b/test_regress/t/t_param_pattern2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_pattern2.v b/test_regress/t/t_param_pattern2.v index 2bd1731c8..64211085b 100644 --- a/test_regress/t/t_param_pattern2.v +++ b/test_regress/t/t_param_pattern2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Ryszard Rozak. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Ryszard Rozak // SPDX-License-Identifier: CC0-1.0 module dut diff --git a/test_regress/t/t_param_pattern3.py b/test_regress/t/t_param_pattern3.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_param_pattern3.py +++ b/test_regress/t/t_param_pattern3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_pattern3.v b/test_regress/t/t_param_pattern3.v index 4ea714c5e..b7c8f4694 100644 --- a/test_regress/t/t_param_pattern3.v +++ b/test_regress/t/t_param_pattern3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_param_pattern_init.py b/test_regress/t/t_param_pattern_init.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_pattern_init.py +++ b/test_regress/t/t_param_pattern_init.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_pattern_init.v b/test_regress/t/t_param_pattern_init.v index 69fefffec..2a40a4134 100644 --- a/test_regress/t/t_param_pattern_init.v +++ b/test_regress/t/t_param_pattern_init.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_param_pattern_init_scope.py b/test_regress/t/t_param_pattern_init_scope.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_param_pattern_init_scope.py +++ b/test_regress/t/t_param_pattern_init_scope.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_pattern_init_scope.v b/test_regress/t/t_param_pattern_init_scope.v index 455133c8a..f4911f88a 100644 --- a/test_regress/t/t_param_pattern_init_scope.v +++ b/test_regress/t/t_param_pattern_init_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_param_public.cpp b/test_regress/t/t_param_public.cpp index 6bed53bd0..61891bb45 100644 --- a/test_regress/t/t_param_public.cpp +++ b/test_regress/t/t_param_public.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_param_public.py b/test_regress/t/t_param_public.py index a5d71a2d5..bdfaedcec 100755 --- a/test_regress/t/t_param_public.py +++ b/test_regress/t/t_param_public.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_public.v b/test_regress/t/t_param_public.v index a2db80ceb..e8d3a8198 100644 --- a/test_regress/t/t_param_public.v +++ b/test_regress/t/t_param_public.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug505 diff --git a/test_regress/t/t_param_real.py b/test_regress/t/t_param_real.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_real.py +++ b/test_regress/t/t_param_real.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_real.v b/test_regress/t/t_param_real.v index 6fc950a82..0190587e5 100644 --- a/test_regress/t/t_param_real.v +++ b/test_regress/t/t_param_real.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Johan Bjork +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Johan Bjork // SPDX-License-Identifier: CC0-1.0 module mod #( diff --git a/test_regress/t/t_param_real2.py b/test_regress/t/t_param_real2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_real2.py +++ b/test_regress/t/t_param_real2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_real2.v b/test_regress/t/t_param_real2.v index f371b5597..ecdca0549 100644 --- a/test_regress/t/t_param_real2.v +++ b/test_regress/t/t_param_real2.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module foo diff --git a/test_regress/t/t_param_real2_collision.py b/test_regress/t/t_param_real2_collision.py index 9d6a5295f..c1150b53d 100755 --- a/test_regress/t/t_param_real2_collision.py +++ b/test_regress/t/t_param_real2_collision.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_repl.py b/test_regress/t/t_param_repl.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_repl.py +++ b/test_regress/t/t_param_repl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_repl.v b/test_regress/t/t_param_repl.v index cc7b04d40..7743ecfd1 100644 --- a/test_regress/t/t_param_repl.v +++ b/test_regress/t/t_param_repl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_resolve_args.py b/test_regress/t/t_param_resolve_args.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_resolve_args.py +++ b/test_regress/t/t_param_resolve_args.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_resolve_args.v b/test_regress/t/t_param_resolve_args.v index 2cd61b175..ec717e2be 100644 --- a/test_regress/t/t_param_resolve_args.v +++ b/test_regress/t/t_param_resolve_args.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_param_scope_bad.py b/test_regress/t/t_param_scope_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_param_scope_bad.py +++ b/test_regress/t/t_param_scope_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_scope_bad.v b/test_regress/t/t_param_scope_bad.v index 0e4c2b117..b154c6ec8 100644 --- a/test_regress/t/t_param_scope_bad.v +++ b/test_regress/t/t_param_scope_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_seg.py b/test_regress/t/t_param_seg.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_seg.py +++ b/test_regress/t/t_param_seg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_seg.v b/test_regress/t/t_param_seg.v index 447c44d5e..fb85ac6e3 100644 --- a/test_regress/t/t_param_seg.v +++ b/test_regress/t/t_param_seg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Mandy Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Mandy Xu // SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH diff --git a/test_regress/t/t_param_sel.py b/test_regress/t/t_param_sel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_sel.py +++ b/test_regress/t/t_param_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_sel.v b/test_regress/t/t_param_sel.v index b87db56e2..446e41a31 100644 --- a/test_regress/t/t_param_sel.v +++ b/test_regress/t/t_param_sel.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_sel_range.py b/test_regress/t/t_param_sel_range.py index 282910f54..3cbc9d76f 100755 --- a/test_regress/t/t_param_sel_range.py +++ b/test_regress/t/t_param_sel_range.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_sel_range.v b/test_regress/t/t_param_sel_range.v index 85ea4a7d8..a4a21ac46 100644 --- a/test_regress/t/t_param_sel_range.v +++ b/test_regress/t/t_param_sel_range.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug477 diff --git a/test_regress/t/t_param_sel_range_bad.py b/test_regress/t/t_param_sel_range_bad.py index 916df8696..50f394103 100755 --- a/test_regress/t/t_param_sel_range_bad.py +++ b/test_regress/t/t_param_sel_range_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_shift.py b/test_regress/t/t_param_shift.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_shift.py +++ b/test_regress/t/t_param_shift.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_shift.v b/test_regress/t/t_param_shift.v index ecc4d51c0..8ef0fc01a 100644 --- a/test_regress/t/t_param_shift.v +++ b/test_regress/t/t_param_shift.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Mandy Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Mandy Xu // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_param_slice.py b/test_regress/t/t_param_slice.py index 25010f779..d55e45178 100755 --- a/test_regress/t/t_param_slice.py +++ b/test_regress/t/t_param_slice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Test constant parameter slicing of unpacked arrays (issue #6257) # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_slice.v b/test_regress/t/t_param_slice.v index 96adbdf0b..358c1edd6 100644 --- a/test_regress/t/t_param_slice.v +++ b/test_regress/t/t_param_slice.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps @@ -21,7 +21,7 @@ module issue_desc #( ) x(); end initial begin - int expected = orig_els - els_p + 1; + automatic int expected = orig_els - els_p + 1; if (val_p[2] !== expected) begin $error("DESC wrong value %0d expected %0d in %m", val_p[2], expected); $finish; @@ -44,7 +44,7 @@ module issue_rev #( ) x(); end initial begin - int expected = orig_els - els_p + 1; + automatic int expected = orig_els - els_p + 1; if (val_p[2] !== expected) begin $error("REV wrong value %0d expected %0d in %m", val_p[2], expected); $finish; diff --git a/test_regress/t/t_param_store_bad.py b/test_regress/t/t_param_store_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_param_store_bad.py +++ b/test_regress/t/t_param_store_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_store_bad.v b/test_regress/t/t_param_store_bad.v index 5f617d9d7..4dff59398 100644 --- a/test_regress/t/t_param_store_bad.v +++ b/test_regress/t/t_param_store_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t #( diff --git a/test_regress/t/t_param_type.py b/test_regress/t/t_param_type.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_type.py +++ b/test_regress/t/t_param_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type.v b/test_regress/t/t_param_type.v index 9fbeaa969..088f387ed 100644 --- a/test_regress/t/t_param_type.v +++ b/test_regress/t/t_param_type.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_param_type2.py b/test_regress/t/t_param_type2.py index 3aafd524c..f8083269e 100755 --- a/test_regress/t/t_param_type2.py +++ b/test_regress/t/t_param_type2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type2.v b/test_regress/t/t_param_type2.v index 8cdd09d70..498e3b9d1 100644 --- a/test_regress/t/t_param_type2.v +++ b/test_regress/t/t_param_type2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 package tt_pkg; diff --git a/test_regress/t/t_param_type3.py b/test_regress/t/t_param_type3.py index 3aafd524c..f8083269e 100755 --- a/test_regress/t/t_param_type3.py +++ b/test_regress/t/t_param_type3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type3.v b/test_regress/t/t_param_type3.v index cbce4c24b..1399798fb 100644 --- a/test_regress/t/t_param_type3.v +++ b/test_regress/t/t_param_type3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 typedef logic T_t; diff --git a/test_regress/t/t_param_type4.py b/test_regress/t/t_param_type4.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_type4.py +++ b/test_regress/t/t_param_type4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type4.v b/test_regress/t/t_param_type4.v index 4fd9604bd..61c515c45 100644 --- a/test_regress/t/t_param_type4.v +++ b/test_regress/t/t_param_type4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_param_type4_collision.py b/test_regress/t/t_param_type4_collision.py index 202e9dda9..a4ae90afb 100755 --- a/test_regress/t/t_param_type4_collision.py +++ b/test_regress/t/t_param_type4_collision.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type5.py b/test_regress/t/t_param_type5.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_type5.py +++ b/test_regress/t/t_param_type5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type5.v b/test_regress/t/t_param_type5.v index 3744262e4..d5abe3ea9 100644 --- a/test_regress/t/t_param_type5.v +++ b/test_regress/t/t_param_type5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class ParamClass #(string P = "ABC", R = "GDF"); diff --git a/test_regress/t/t_param_type6.py b/test_regress/t/t_param_type6.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_type6.py +++ b/test_regress/t/t_param_type6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type6.v b/test_regress/t/t_param_type6.v index 32c173a15..7557e7cb9 100644 --- a/test_regress/t/t_param_type6.v +++ b/test_regress/t/t_param_type6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface intf #( diff --git a/test_regress/t/t_param_type_bad.py b/test_regress/t/t_param_type_bad.py index 45bc705e4..21cff4c51 100755 --- a/test_regress/t/t_param_type_bad.py +++ b/test_regress/t/t_param_type_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type_bad.v b/test_regress/t/t_param_type_bad.v index 45d05240b..b70983e4e 100644 --- a/test_regress/t/t_param_type_bad.v +++ b/test_regress/t/t_param_type_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_type_bad2.py b/test_regress/t/t_param_type_bad2.py index 95efb5b13..eba256d00 100755 --- a/test_regress/t/t_param_type_bad2.py +++ b/test_regress/t/t_param_type_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type_bad2.v b/test_regress/t/t_param_type_bad2.v index b61f9af0d..8a78237e9 100644 --- a/test_regress/t/t_param_type_bad2.v +++ b/test_regress/t/t_param_type_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_type_bad3.py b/test_regress/t/t_param_type_bad3.py index 45bc705e4..21cff4c51 100755 --- a/test_regress/t/t_param_type_bad3.py +++ b/test_regress/t/t_param_type_bad3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type_bad3.v b/test_regress/t/t_param_type_bad3.v index 3848e7c9e..98b91ab2d 100644 --- a/test_regress/t/t_param_type_bad3.v +++ b/test_regress/t/t_param_type_bad3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_type_bit.py b/test_regress/t/t_param_type_bit.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_param_type_bit.py +++ b/test_regress/t/t_param_type_bit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type_bit.v b/test_regress/t/t_param_type_bit.v index 4317ee39d..b5bd12f51 100644 --- a/test_regress/t/t_param_type_bit.v +++ b/test_regress/t/t_param_type_bit.v @@ -3,8 +3,8 @@ // This test examines Verilator against paramter definition with functions. // Particularly the function takes in argument which is multi-dimentional. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_type_chain.py b/test_regress/t/t_param_type_chain.py new file mode 100755 index 000000000..84b274f68 --- /dev/null +++ b/test_regress/t/t_param_type_chain.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type_chain.v b/test_regress/t/t_param_type_chain.v new file mode 100644 index 000000000..c8e9e582b --- /dev/null +++ b/test_regress/t/t_param_type_chain.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk +); + + sub sub_default (); + sub #(.foo_t(logic [7:0])) sub_8 (); + + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module sub #( + parameter type foo_t = logic, + parameter type bar_t = foo_t[1:0] +); + initial begin + $display("%m foo_t = %0d bar_t = %0d", $bits(foo_t), $bits(bar_t)); + if (2 * $bits(foo_t) != $bits(bar_t)) $stop; + end +endmodule diff --git a/test_regress/t/t_param_type_cmp.py b/test_regress/t/t_param_type_cmp.py index 671072f97..93e1f30e1 100755 --- a/test_regress/t/t_param_type_cmp.py +++ b/test_regress/t/t_param_type_cmp.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type_cmp.v b/test_regress/t/t_param_type_cmp.v index 79cbc0e4a..547986c89 100644 --- a/test_regress/t/t_param_type_cmp.v +++ b/test_regress/t/t_param_type_cmp.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_param_type_collision.py b/test_regress/t/t_param_type_collision.py index 9cc944889..787a3afd4 100755 --- a/test_regress/t/t_param_type_collision.py +++ b/test_regress/t/t_param_type_collision.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type_fwd.py b/test_regress/t/t_param_type_fwd.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_param_type_fwd.py +++ b/test_regress/t/t_param_type_fwd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type_fwd.v b/test_regress/t/t_param_type_fwd.v index f84a2d567..4fdab946f 100644 --- a/test_regress/t/t_param_type_fwd.v +++ b/test_regress/t/t_param_type_fwd.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef enum { ONE } e_t; diff --git a/test_regress/t/t_param_type_fwd_bad.py b/test_regress/t/t_param_type_fwd_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_param_type_fwd_bad.py +++ b/test_regress/t/t_param_type_fwd_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type_fwd_bad.v b/test_regress/t/t_param_type_fwd_bad.v index e623b9ca0..f5333afe9 100644 --- a/test_regress/t/t_param_type_fwd_bad.v +++ b/test_regress/t/t_param_type_fwd_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef int int_t; diff --git a/test_regress/t/t_param_type_id_bad.py b/test_regress/t/t_param_type_id_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_param_type_id_bad.py +++ b/test_regress/t/t_param_type_id_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_type_id_bad.v b/test_regress/t/t_param_type_id_bad.v index fd4482a5f..aaf60e5a6 100644 --- a/test_regress/t/t_param_type_id_bad.v +++ b/test_regress/t/t_param_type_id_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 int i; diff --git a/test_regress/t/t_param_typedef.py b/test_regress/t/t_param_typedef.py index cca4c9e73..d6d35e7fd 100755 --- a/test_regress/t/t_param_typedef.py +++ b/test_regress/t/t_param_typedef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_typedef.v b/test_regress/t/t_param_typedef.v index fb843b91a..796d3b9c1 100644 --- a/test_regress/t/t_param_typedef.v +++ b/test_regress/t/t_param_typedef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off IMPLICIT diff --git a/test_regress/t/t_param_typedef2.py b/test_regress/t/t_param_typedef2.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_param_typedef2.py +++ b/test_regress/t/t_param_typedef2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_typedef2.v b/test_regress/t/t_param_typedef2.v index dcf6db506..85f191f9b 100644 --- a/test_regress/t/t_param_typedef2.v +++ b/test_regress/t/t_param_typedef2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo #(type T); diff --git a/test_regress/t/t_param_unreachable.py b/test_regress/t/t_param_unreachable.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_unreachable.py +++ b/test_regress/t/t_param_unreachable.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_unreachable.v b/test_regress/t/t_param_unreachable.v index 856944f5f..67756cce3 100644 --- a/test_regress/t/t_param_unreachable.v +++ b/test_regress/t/t_param_unreachable.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Pierre-Henri Horrein +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2020 Pierre-Henri Horrein // SPDX-License-Identifier: CC0-1.0 module t (input clk); diff --git a/test_regress/t/t_param_up_bad.py b/test_regress/t/t_param_up_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_param_up_bad.py +++ b/test_regress/t/t_param_up_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_up_bad.v b/test_regress/t/t_param_up_bad.v index 1d5ebf566..b0632a1dc 100644 --- a/test_regress/t/t_param_up_bad.v +++ b/test_regress/t/t_param_up_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Ian Thompson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Ian Thompson // SPDX-License-Identifier: CC0-1.0 //bug1099 diff --git a/test_regress/t/t_param_value.py b/test_regress/t/t_param_value.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_value.py +++ b/test_regress/t/t_param_value.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_value.v b/test_regress/t/t_param_value.v index ac745a993..cfedb195c 100644 --- a/test_regress/t/t_param_value.v +++ b/test_regress/t/t_param_value.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2012 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_param_while.py b/test_regress/t/t_param_while.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_while.py +++ b/test_regress/t/t_param_while.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_while.v b/test_regress/t/t_param_while.v index 188bff4d2..8e4bc172c 100644 --- a/test_regress/t/t_param_while.v +++ b/test_regress/t/t_param_while.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug505 diff --git a/test_regress/t/t_param_wide_io.py b/test_regress/t/t_param_wide_io.py index 3aafd524c..f8083269e 100755 --- a/test_regress/t/t_param_wide_io.py +++ b/test_regress/t/t_param_wide_io.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_wide_io.v b/test_regress/t/t_param_wide_io.v index 12fdc58f8..efb140c18 100644 --- a/test_regress/t/t_param_wide_io.v +++ b/test_regress/t/t_param_wide_io.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See issue #1991 diff --git a/test_regress/t/t_param_width.py b/test_regress/t/t_param_width.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_param_width.py +++ b/test_regress/t/t_param_width.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_width.v b/test_regress/t/t_param_width.v index ec0cce8bc..106fd7727 100644 --- a/test_regress/t/t_param_width.v +++ b/test_regress/t/t_param_width.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // See issue #1991 diff --git a/test_regress/t/t_param_width_loc_bad.py b/test_regress/t/t_param_width_loc_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_param_width_loc_bad.py +++ b/test_regress/t/t_param_width_loc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_width_loc_bad.v b/test_regress/t/t_param_width_loc_bad.v index 1f0a65166..4b30df634 100644 --- a/test_regress/t/t_param_width_loc_bad.v +++ b/test_regress/t/t_param_width_loc_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_param_x_unique.py b/test_regress/t/t_param_x_unique.py index b60fcce63..ce00f0a74 100755 --- a/test_regress/t/t_param_x_unique.py +++ b/test_regress/t/t_param_x_unique.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_param_x_unique.v b/test_regress/t/t_param_x_unique.v index feeb4c2c7..02162f3a7 100644 --- a/test_regress/t/t_param_x_unique.v +++ b/test_regress/t/t_param_x_unique.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub #(parameter P = 1'bx); diff --git a/test_regress/t/t_parse_delay.py b/test_regress/t/t_parse_delay.py index 3436d0b33..5e555fc34 100755 --- a/test_regress/t/t_parse_delay.py +++ b/test_regress/t/t_parse_delay.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_parse_delay.v b/test_regress/t/t_parse_delay.v index 32733163a..f78f630b2 100644 --- a/test_regress/t/t_parse_delay.v +++ b/test_regress/t/t_parse_delay.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_parse_delay_timing.py b/test_regress/t/t_parse_delay_timing.py index 3c7ce0c65..af464584a 100755 --- a/test_regress/t/t_parse_delay_timing.py +++ b/test_regress/t/t_parse_delay_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_parse_eof_attr_bad.py b/test_regress/t/t_parse_eof_attr_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_parse_eof_attr_bad.py +++ b/test_regress/t/t_parse_eof_attr_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_parse_eof_attr_bad.v b/test_regress/t/t_parse_eof_attr_bad.v index 58bed87cd..c505f1bb5 100644 --- a/test_regress/t/t_parse_eof_attr_bad.v +++ b/test_regress/t/t_parse_eof_attr_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 (* attr diff --git a/test_regress/t/t_parse_eof_qqq_bad.py b/test_regress/t/t_parse_eof_qqq_bad.py index 6256a5167..27b2b057d 100755 --- a/test_regress/t/t_parse_eof_qqq_bad.py +++ b/test_regress/t/t_parse_eof_qqq_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_parse_eof_qqq_bad.v b/test_regress/t/t_parse_eof_qqq_bad.v index 6f936b832..ff34c5843 100644 --- a/test_regress/t/t_parse_eof_qqq_bad.v +++ b/test_regress/t/t_parse_eof_qqq_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 """str diff --git a/test_regress/t/t_parse_eof_str_bad.py b/test_regress/t/t_parse_eof_str_bad.py index 6256a5167..27b2b057d 100755 --- a/test_regress/t/t_parse_eof_str_bad.py +++ b/test_regress/t/t_parse_eof_str_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_parse_eof_str_bad.v b/test_regress/t/t_parse_eof_str_bad.v index ea3efd4e6..b22296723 100644 --- a/test_regress/t/t_parse_eof_str_bad.v +++ b/test_regress/t/t_parse_eof_str_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 localparam string STR = "str diff --git a/test_regress/t/t_parse_sync_bad.py b/test_regress/t/t_parse_sync_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_parse_sync_bad.py +++ b/test_regress/t/t_parse_sync_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_parse_sync_bad.v b/test_regress/t/t_parse_sync_bad.v index 579db166f..892850503 100644 --- a/test_regress/t/t_parse_sync_bad.v +++ b/test_regress/t/t_parse_sync_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Dan Petrisko. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Dan Petrisko // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_parse_sync_bad2.py b/test_regress/t/t_parse_sync_bad2.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_parse_sync_bad2.py +++ b/test_regress/t/t_parse_sync_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_parse_sync_bad2.v b/test_regress/t/t_parse_sync_bad2.v index eb94043b8..39d53599f 100644 --- a/test_regress/t/t_parse_sync_bad2.v +++ b/test_regress/t/t_parse_sync_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Dan Petrisko. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Dan Petrisko // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_past.py b/test_regress/t/t_past.py index 72a44ba64..538200ca5 100755 --- a/test_regress/t/t_past.py +++ b/test_regress/t/t_past.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_past.v b/test_regress/t/t_past.v index a32858a45..510fe87f5 100644 --- a/test_regress/t/t_past.v +++ b/test_regress/t/t_past.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_past_bad.py b/test_regress/t/t_past_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_past_bad.py +++ b/test_regress/t/t_past_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_past_bad.v b/test_regress/t/t_past_bad.v index ed4462350..70a21e12c 100644 --- a/test_regress/t/t_past_bad.v +++ b/test_regress/t/t_past_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_past_funcs.py b/test_regress/t/t_past_funcs.py index e55d87378..690ae1cbf 100755 --- a/test_regress/t/t_past_funcs.py +++ b/test_regress/t/t_past_funcs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_past_funcs.v b/test_regress/t/t_past_funcs.v index d8e987c96..79bd9e558 100644 --- a/test_regress/t/t_past_funcs.v +++ b/test_regress/t/t_past_funcs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Peter Monsson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Peter Monsson // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ diff --git a/test_regress/t/t_past_strobe.py b/test_regress/t/t_past_strobe.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_past_strobe.py +++ b/test_regress/t/t_past_strobe.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_past_strobe.v b/test_regress/t/t_past_strobe.v index 4ccbce987..8d154cf34 100644 --- a/test_regress/t/t_past_strobe.v +++ b/test_regress/t/t_past_strobe.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_past_unsup.py b/test_regress/t/t_past_unsup.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_past_unsup.py +++ b/test_regress/t/t_past_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_past_unsup.v b/test_regress/t/t_past_unsup.v index 58cbc84c5..ffdac94dd 100644 --- a/test_regress/t/t_past_unsup.v +++ b/test_regress/t/t_past_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_pattern_unsup_xor.out b/test_regress/t/t_pattern_unsup_xor.out new file mode 100644 index 000000000..82871ca73 --- /dev/null +++ b/test_regress/t/t_pattern_unsup_xor.out @@ -0,0 +1,6 @@ +%Error-UNSUPPORTED: t/t_pattern_unsup_xor.v:11:25: Unsupported/Illegal: Assignment pattern member not underneath a supported construct: XOR + : ... note: In instance 't' + 11 | status_t status_reg = '{bit_field: 1'b0} ^ 1'b0; + | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_pattern_unsup_xor.py b/test_regress/t/t_pattern_unsup_xor.py new file mode 100755 index 000000000..c7d9b21a5 --- /dev/null +++ b/test_regress/t/t_pattern_unsup_xor.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pattern_unsup_xor.v b/test_regress/t/t_pattern_unsup_xor.v new file mode 100644 index 000000000..c3dc096d7 --- /dev/null +++ b/test_regress/t/t_pattern_unsup_xor.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// Test for issue where assignment pattern with XOR caused segfault +module t; + typedef struct {logic bit_field;} status_t; + + status_t status_reg = '{bit_field: 1'b0} ^ 1'b0; +endmodule diff --git a/test_regress/t/t_pgo_profoutofdate_bad.py b/test_regress/t/t_pgo_profoutofdate_bad.py index dcb5636b3..6eb37c3ee 100755 --- a/test_regress/t/t_pgo_profoutofdate_bad.py +++ b/test_regress/t/t_pgo_profoutofdate_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pgo_profoutofdate_bad.v b/test_regress/t/t_pgo_profoutofdate_bad.v index 43a2b1b8d..652557f31 100644 --- a/test_regress/t/t_pgo_profoutofdate_bad.v +++ b/test_regress/t/t_pgo_profoutofdate_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_pgo_threads.py b/test_regress/t/t_pgo_threads.py index 9527e06d0..a5864f805 100755 --- a/test_regress/t/t_pgo_threads.py +++ b/test_regress/t/t_pgo_threads.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pgo_threads_hier.py b/test_regress/t/t_pgo_threads_hier.py index 404deb791..f09094b61 100755 --- a/test_regress/t/t_pgo_threads_hier.py +++ b/test_regress/t/t_pgo_threads_hier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pgo_threads_hier.vlt b/test_regress/t/t_pgo_threads_hier.vlt index caa255202..ebecfa826 100644 --- a/test_regress/t/t_pgo_threads_hier.vlt +++ b/test_regress/t/t_pgo_threads_hier.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_pipe_exit_bad.py b/test_regress/t/t_pipe_exit_bad.py index 7e0fef5d9..ee96c93a7 100755 --- a/test_regress/t/t_pipe_exit_bad.py +++ b/test_regress/t/t_pipe_exit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pipe_exit_bad_pf.pf b/test_regress/t/t_pipe_exit_bad_pf.pf index 312b25bc0..55e05bf43 100755 --- a/test_regress/t/t_pipe_exit_bad_pf.pf +++ b/test_regress/t/t_pipe_exit_bad_pf.pf @@ -4,10 +4,10 @@ # # DESCRIPTION: Verilator: Verilog Test example --pipe-filter script # -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2010 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import sys diff --git a/test_regress/t/t_pipe_filter.py b/test_regress/t/t_pipe_filter.py index 0ca83d0d1..7fbe6feb1 100755 --- a/test_regress/t/t_pipe_filter.py +++ b/test_regress/t/t_pipe_filter.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pipe_filter.v b/test_regress/t/t_pipe_filter.v index ce2e441a1..e372e027d 100644 --- a/test_regress/t/t_pipe_filter.v +++ b/test_regress/t/t_pipe_filter.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //=========================================================================== diff --git a/test_regress/t/t_pipe_filter_inc.vh b/test_regress/t/t_pipe_filter_inc.vh index aff08071e..e6d63ec25 100644 --- a/test_regress/t/t_pipe_filter_inc.vh +++ b/test_regress/t/t_pipe_filter_inc.vh @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 inc line 6; diff --git a/test_regress/t/t_pipe_filter_pf.pf b/test_regress/t/t_pipe_filter_pf.pf index 6c25e3042..c44a5e92d 100755 --- a/test_regress/t/t_pipe_filter_pf.pf +++ b/test_regress/t/t_pipe_filter_pf.pf @@ -4,10 +4,10 @@ # # DESCRIPTION: Verilator: Verilog Test example --pipe-filter script # -# Copyright 2010 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2010 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import re diff --git a/test_regress/t/t_pli_bad.py b/test_regress/t/t_pli_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_pli_bad.py +++ b/test_regress/t/t_pli_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pli_bad.v b/test_regress/t/t_pli_bad.v index cd8ba2d87..35e198f64 100644 --- a/test_regress/t/t_pli_bad.v +++ b/test_regress/t/t_pli_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_pli_bbox.py b/test_regress/t/t_pli_bbox.py index 6962d0be1..cfc717aa9 100755 --- a/test_regress/t/t_pli_bbox.py +++ b/test_regress/t/t_pli_bbox.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_circ_subst_bad.py b/test_regress/t/t_pp_circ_subst_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_pp_circ_subst_bad.py +++ b/test_regress/t/t_pp_circ_subst_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_circ_subst_bad.v b/test_regress/t/t_pp_circ_subst_bad.v index a1abbbabb..bf97bd69d 100644 --- a/test_regress/t/t_pp_circ_subst_bad.v +++ b/test_regress/t/t_pp_circ_subst_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define e fun `e diff --git a/test_regress/t/t_pp_circ_subst_bad2.py b/test_regress/t/t_pp_circ_subst_bad2.py index a4770180d..f21959d4b 100755 --- a/test_regress/t/t_pp_circ_subst_bad2.py +++ b/test_regress/t/t_pp_circ_subst_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_circdef_bad.py b/test_regress/t/t_pp_circdef_bad.py index 0478d07b9..f2d5b3d3d 100755 --- a/test_regress/t/t_pp_circdef_bad.py +++ b/test_regress/t/t_pp_circdef_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_circdef_bad.v b/test_regress/t/t_pp_circdef_bad.v index 0b822957b..d062e0bd2 100644 --- a/test_regress/t/t_pp_circdef_bad.v +++ b/test_regress/t/t_pp_circdef_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // bug445 diff --git a/test_regress/t/t_pp_defkwd_bad.py b/test_regress/t/t_pp_defkwd_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_pp_defkwd_bad.py +++ b/test_regress/t/t_pp_defkwd_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_defkwd_bad.v b/test_regress/t/t_pp_defkwd_bad.v index ec5a3c731..0a2fc6b78 100644 --- a/test_regress/t/t_pp_defkwd_bad.v +++ b/test_regress/t/t_pp_defkwd_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define define 1 diff --git a/test_regress/t/t_pp_defnettype_bad.py b/test_regress/t/t_pp_defnettype_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_pp_defnettype_bad.py +++ b/test_regress/t/t_pp_defnettype_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_defnettype_bad.v b/test_regress/t/t_pp_defnettype_bad.v index fc8aa9c1a..ddbfe35d7 100644 --- a/test_regress/t/t_pp_defnettype_bad.v +++ b/test_regress/t/t_pp_defnettype_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `default_nettype bad_none_such diff --git a/test_regress/t/t_pp_defparen_bad.py b/test_regress/t/t_pp_defparen_bad.py index 4cc015636..ac8e3fac3 100755 --- a/test_regress/t/t_pp_defparen_bad.py +++ b/test_regress/t/t_pp_defparen_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_defparen_bad.v b/test_regress/t/t_pp_defparen_bad.v index 558bad346..fa3056129 100644 --- a/test_regress/t/t_pp_defparen_bad.v +++ b/test_regress/t/t_pp_defparen_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define test(a1,a2) ((a1) + (a2)) diff --git a/test_regress/t/t_pp_display.py b/test_regress/t/t_pp_display.py index 97abb660e..c03eaf086 100755 --- a/test_regress/t/t_pp_display.py +++ b/test_regress/t/t_pp_display.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_display.v b/test_regress/t/t_pp_display.v index 4a0fcca0c..28fe82569 100644 --- a/test_regress/t/t_pp_display.v +++ b/test_regress/t/t_pp_display.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_pp_dupdef.py b/test_regress/t/t_pp_dupdef.py index 759a466d9..2f6d1e4f8 100755 --- a/test_regress/t/t_pp_dupdef.py +++ b/test_regress/t/t_pp_dupdef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_dupdef.v b/test_regress/t/t_pp_dupdef.v index 4e2405777..3e1e71b9e 100644 --- a/test_regress/t/t_pp_dupdef.v +++ b/test_regress/t/t_pp_dupdef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_pp_dupdef_bad.py b/test_regress/t/t_pp_dupdef_bad.py index e9153a9f4..49abce3eb 100755 --- a/test_regress/t/t_pp_dupdef_bad.py +++ b/test_regress/t/t_pp_dupdef_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_dupdef_pragma_bad.py b/test_regress/t/t_pp_dupdef_pragma_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_pp_dupdef_pragma_bad.py +++ b/test_regress/t/t_pp_dupdef_pragma_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_dupdef_pragma_bad.v b/test_regress/t/t_pp_dupdef_pragma_bad.v index 3541805eb..a2c811241 100644 --- a/test_regress/t/t_pp_dupdef_pragma_bad.v +++ b/test_regress/t/t_pp_dupdef_pragma_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_pp_lib.py b/test_regress/t/t_pp_lib.py index 1fc2440ba..1a3f535a7 100755 --- a/test_regress/t/t_pp_lib.py +++ b/test_regress/t/t_pp_lib.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_lib.v b/test_regress/t/t_pp_lib.v index ae984a1a1..ff79fa89d 100644 --- a/test_regress/t/t_pp_lib.v +++ b/test_regress/t/t_pp_lib.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "t_pp_lib_inc.vh" diff --git a/test_regress/t/t_pp_lib_inc.vh b/test_regress/t/t_pp_lib_inc.vh index 734024343..0f4540981 100644 --- a/test_regress/t/t_pp_lib_inc.vh +++ b/test_regress/t/t_pp_lib_inc.vh @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define WIDTH 10 diff --git a/test_regress/t/t_pp_lib_library.v b/test_regress/t/t_pp_lib_library.v index 316c8844c..431f73f48 100644 --- a/test_regress/t/t_pp_lib_library.v +++ b/test_regress/t/t_pp_lib_library.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module library_cell(a); diff --git a/test_regress/t/t_pp_line.py b/test_regress/t/t_pp_line.py index ccec64024..33149e225 100755 --- a/test_regress/t/t_pp_line.py +++ b/test_regress/t/t_pp_line.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_line.v b/test_regress/t/t_pp_line.v index efc22d470..4e1c948c1 100644 --- a/test_regress/t/t_pp_line.v +++ b/test_regress/t/t_pp_line.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_pp_line_bad.py b/test_regress/t/t_pp_line_bad.py index 2819d29cf..86977e559 100755 --- a/test_regress/t/t_pp_line_bad.py +++ b/test_regress/t/t_pp_line_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_line_bad.v b/test_regress/t/t_pp_line_bad.v index 0d41247a1..4c08af5dd 100644 --- a/test_regress/t/t_pp_line_bad.v +++ b/test_regress/t/t_pp_line_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `line diff --git a/test_regress/t/t_pp_misdef_bad.py b/test_regress/t/t_pp_misdef_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_pp_misdef_bad.py +++ b/test_regress/t/t_pp_misdef_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_misdef_bad.v b/test_regress/t/t_pp_misdef_bad.v index 6328c26db..bc5c56b8f 100644 --- a/test_regress/t/t_pp_misdef_bad.v +++ b/test_regress/t/t_pp_misdef_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_pp_pragma_bad.py b/test_regress/t/t_pp_pragma_bad.py index e9ac373c2..c3b4dffcd 100755 --- a/test_regress/t/t_pp_pragma_bad.py +++ b/test_regress/t/t_pp_pragma_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_pragma_bad.v b/test_regress/t/t_pp_pragma_bad.v index 82c596225..a5e4e93a7 100644 --- a/test_regress/t/t_pp_pragma_bad.v +++ b/test_regress/t/t_pp_pragma_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `pragma diff --git a/test_regress/t/t_pp_pragmas.py b/test_regress/t/t_pp_pragmas.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_pp_pragmas.py +++ b/test_regress/t/t_pp_pragmas.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_pragmas.v b/test_regress/t/t_pp_pragmas.v index 2da128a39..3b994574a 100644 --- a/test_regress/t/t_pp_pragmas.v +++ b/test_regress/t/t_pp_pragmas.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/10ps diff --git a/test_regress/t/t_pp_recursedef_bad.py b/test_regress/t/t_pp_recursedef_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_pp_recursedef_bad.py +++ b/test_regress/t/t_pp_recursedef_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_recursedef_bad.v b/test_regress/t/t_pp_recursedef_bad.v index 00a2aa78c..57287cfe8 100644 --- a/test_regress/t/t_pp_recursedef_bad.v +++ b/test_regress/t/t_pp_recursedef_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_pp_resetall_bad.py b/test_regress/t/t_pp_resetall_bad.py index 8df222dcf..35d510005 100755 --- a/test_regress/t/t_pp_resetall_bad.py +++ b/test_regress/t/t_pp_resetall_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_resetall_bad.v b/test_regress/t/t_pp_resetall_bad.v index 1d9cc583a..c6f781576 100644 --- a/test_regress/t/t_pp_resetall_bad.v +++ b/test_regress/t/t_pp_resetall_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `resetall // Ok diff --git a/test_regress/t/t_pp_underline.py b/test_regress/t/t_pp_underline.py new file mode 100755 index 000000000..6ea49d226 --- /dev/null +++ b/test_regress/t/t_pp_underline.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.top_filename = "t/t_pp_underline_bad.v" + +test.lint(verilator_flags2=["-Wno-BADVLTPRAGMA"]) + +test.passes() diff --git a/test_regress/t/t_pp_underline_bad.out b/test_regress/t/t_pp_underline_bad.out index 663d52e91..977a7a361 100644 --- a/test_regress/t/t_pp_underline_bad.out +++ b/test_regress/t/t_pp_underline_bad.out @@ -1,12 +1,8 @@ -%Error: t/t_pp_underline_bad.v:8:4: Extra underscore in meta-comment; use /*verilator {...}*/ not /*verilator_{...}*/ +%Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:8:4: Extra underscore in meta-comment, ignoring comment; use /*verilator {...}*/ not /*verilator_{...}*/ 8 | // verilator_no_inline_module | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_pp_underline_bad.v:10:19: Extra underscore in meta-comment; use /*synopsys {...}*/ not /*synopsys_{...}*/ + ... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest +%Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:10:19: Extra underscore in meta-comment, ignoring comment; use /*synopsys {...}*/ not /*synopsys_{...}*/ 10 | case (1'b1) // synopsys_full_case | ^~~~~~~~~~~~~~~~~~~~~ -%Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:8:4: Unknown verilator comment: '/*verilator _no_inline_module*/' - 8 | /*verilator _no_inline_module*/ - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - ... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_pp_underline_bad.py b/test_regress/t/t_pp_underline_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_pp_underline_bad.py +++ b/test_regress/t/t_pp_underline_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_pp_underline_bad.v b/test_regress/t/t_pp_underline_bad.v index 7d1ee1bc9..56a87c969 100644 --- a/test_regress/t/t_pp_underline_bad.v +++ b/test_regress/t/t_pp_underline_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; @@ -9,6 +9,7 @@ module t; initial begin case (1'b1) // synopsys_full_case 1'b0: $stop; + 1'b1: $finish; endcase $stop; // Should have failed end diff --git a/test_regress/t/t_pp_underline_bad_vlt.out b/test_regress/t/t_pp_underline_bad_vlt.out new file mode 100644 index 000000000..89ac5c94b --- /dev/null +++ b/test_regress/t/t_pp_underline_bad_vlt.out @@ -0,0 +1,5 @@ +%Error-BADVLTPRAGMA: t/t_pp_underline_bad.v:8:4: Extra underscore in meta-comment, ignoring comment; use /*verilator {...}*/ not /*verilator_{...}*/ + 8 | // verilator_no_inline_module + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_pp_underline_bad_vlt.py b/test_regress/t/t_pp_underline_bad_vlt.py new file mode 100755 index 000000000..46c7f2a76 --- /dev/null +++ b/test_regress/t/t_pp_underline_bad_vlt.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.top_filename = "t/t_pp_underline_bad.v" + +test.lint(verilator_flags2=["t/t_pp_underline_bad_vlt.vlt"], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_pp_underline_bad_vlt.vlt b/test_regress/t/t_pp_underline_bad_vlt.vlt new file mode 100644 index 000000000..6ac64238f --- /dev/null +++ b/test_regress/t/t_pp_underline_bad_vlt.vlt @@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +`verilator_config + +lint_off -rule BADVLTPRAGMA -file "t/t_pp_underline_bad.v" -lines 10 diff --git a/test_regress/t/t_premit_rw.py b/test_regress/t/t_premit_rw.py index 3aafd524c..f8083269e 100755 --- a/test_regress/t/t_premit_rw.py +++ b/test_regress/t/t_premit_rw.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_premit_rw.v b/test_regress/t/t_premit_rw.v index ba7872a43..f9bb52cc9 100644 --- a/test_regress/t/t_premit_rw.v +++ b/test_regress/t/t_premit_rw.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef struct packed { diff --git a/test_regress/t/t_preproc.py b/test_regress/t/t_preproc.py index 8ccc75e7a..a3f0c1c97 100755 --- a/test_regress/t/t_preproc.py +++ b/test_regress/t/t_preproc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc.v b/test_regress/t/t_preproc.v index ed882d1d9..eac57cc0c 100644 --- a/test_regress/t/t_preproc.v +++ b/test_regress/t/t_preproc.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2000-2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2000-2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // This file intentionally includes some tabs diff --git a/test_regress/t/t_preproc_cmtend_bad.py b/test_regress/t/t_preproc_cmtend_bad.py index 889534217..b4b069353 100755 --- a/test_regress/t/t_preproc_cmtend_bad.py +++ b/test_regress/t/t_preproc_cmtend_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_cmtend_bad.v b/test_regress/t/t_preproc_cmtend_bad.v index d458fe340..ec9f00814 100644 --- a/test_regress/t/t_preproc_cmtend_bad.v +++ b/test_regress/t/t_preproc_cmtend_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 /*Blah diff --git a/test_regress/t/t_preproc_comments.out b/test_regress/t/t_preproc_comments.out index 9054c0fec..06438f836 100644 --- a/test_regress/t/t_preproc_comments.out +++ b/test_regress/t/t_preproc_comments.out @@ -1,7 +1,7 @@ `line 1 "t/t_preproc.v" 1 // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2000-2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2000-2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc.v" 0 @@ -15,8 +15,8 @@ `line 1 "t/t_preproc_inc2.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc2.vh" 0 -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2000-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2000-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 At file "t/t_preproc_inc2.vh" line 5 @@ -25,8 +25,8 @@ At file "t/t_preproc_inc2.vh" line 5 `line 1 "t/t_preproc_inc3.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc3.vh" 0 -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2000-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2000-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc_inc3.vh" 0 @@ -369,8 +369,8 @@ begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 1 "t/t_preproc_inc4.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc4.vh" 0 -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2000-2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2000-2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc_inc4.vh" 0 @@ -703,8 +703,8 @@ hello4hello4hello4hello4 `line 1 "t/t_preproc_inc4.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc4.vh" 0 -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2000-2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2000-2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc_inc4.vh" 0 diff --git a/test_regress/t/t_preproc_comments.py b/test_regress/t/t_preproc_comments.py index 54493536f..5d7d79f1d 100755 --- a/test_regress/t/t_preproc_comments.py +++ b/test_regress/t/t_preproc_comments.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_debugi.py b/test_regress/t/t_preproc_debugi.py index a8df3f568..7616cf6ca 100755 --- a/test_regress/t/t_preproc_debugi.py +++ b/test_regress/t/t_preproc_debugi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_debugi.v b/test_regress/t/t_preproc_debugi.v index 9e9202741..b35208387 100644 --- a/test_regress/t/t_preproc_debugi.v +++ b/test_regress/t/t_preproc_debugi.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define FOO diff --git a/test_regress/t/t_preproc_def09.py b/test_regress/t/t_preproc_def09.py index fe9e90689..f8fd8478c 100755 --- a/test_regress/t/t_preproc_def09.py +++ b/test_regress/t/t_preproc_def09.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_def09.v b/test_regress/t/t_preproc_def09.v index 2106080c2..3163b8254 100644 --- a/test_regress/t/t_preproc_def09.v +++ b/test_regress/t/t_preproc_def09.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `undefineall diff --git a/test_regress/t/t_preproc_defarg_bad.py b/test_regress/t/t_preproc_defarg_bad.py index 8e1a07120..b495acc93 100755 --- a/test_regress/t/t_preproc_defarg_bad.py +++ b/test_regress/t/t_preproc_defarg_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_defarg_bad.v b/test_regress/t/t_preproc_defarg_bad.v index 967c3b44b..bb600a36f 100644 --- a/test_regress/t/t_preproc_defarg_bad.v +++ b/test_regress/t/t_preproc_defarg_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //See bug289 diff --git a/test_regress/t/t_preproc_defines.py b/test_regress/t/t_preproc_defines.py index 8d7631e60..10369de7d 100755 --- a/test_regress/t/t_preproc_defines.py +++ b/test_regress/t/t_preproc_defines.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_dos.py b/test_regress/t/t_preproc_dos.py index ca72b6ab7..f46a2a68b 100755 --- a/test_regress/t/t_preproc_dos.py +++ b/test_regress/t/t_preproc_dos.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_dump_defines.py b/test_regress/t/t_preproc_dump_defines.py index 433946a97..70b8ac8ed 100755 --- a/test_regress/t/t_preproc_dump_defines.py +++ b/test_regress/t/t_preproc_dump_defines.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_elsif_bad.py b/test_regress/t/t_preproc_elsif_bad.py index b16466729..15c9e41a3 100755 --- a/test_regress/t/t_preproc_elsif_bad.py +++ b/test_regress/t/t_preproc_elsif_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_elsif_bad.v b/test_regress/t/t_preproc_elsif_bad.v index 967b9f241..7e19d15f2 100644 --- a/test_regress/t/t_preproc_elsif_bad.v +++ b/test_regress/t/t_preproc_elsif_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //See bug289 diff --git a/test_regress/t/t_preproc_eof1_bad.py b/test_regress/t/t_preproc_eof1_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_preproc_eof1_bad.py +++ b/test_regress/t/t_preproc_eof1_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_eof1_bad.v b/test_regress/t/t_preproc_eof1_bad.v index 84de21a44..83ffc3688 100644 --- a/test_regress/t/t_preproc_eof1_bad.v +++ b/test_regress/t/t_preproc_eof1_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 /* diff --git a/test_regress/t/t_preproc_eof2_bad.py b/test_regress/t/t_preproc_eof2_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_preproc_eof2_bad.py +++ b/test_regress/t/t_preproc_eof2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_eof2_bad.v b/test_regress/t/t_preproc_eof2_bad.v index 4009eed35..bed72ea90 100644 --- a/test_regress/t/t_preproc_eof2_bad.v +++ b/test_regress/t/t_preproc_eof2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define FOO(a, diff --git a/test_regress/t/t_preproc_eof3_bad.py b/test_regress/t/t_preproc_eof3_bad.py index 889534217..b4b069353 100755 --- a/test_regress/t/t_preproc_eof3_bad.py +++ b/test_regress/t/t_preproc_eof3_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_eof3_bad.v b/test_regress/t/t_preproc_eof3_bad.v index 4bfdf63c8..082455d2a 100644 --- a/test_regress/t/t_preproc_eof3_bad.v +++ b/test_regress/t/t_preproc_eof3_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define FOO(a,b) diff --git a/test_regress/t/t_preproc_eof4_bad.py b/test_regress/t/t_preproc_eof4_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_preproc_eof4_bad.py +++ b/test_regress/t/t_preproc_eof4_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_eof4_bad.v b/test_regress/t/t_preproc_eof4_bad.v index 521c65dfa..0ac05f20f 100644 --- a/test_regress/t/t_preproc_eof4_bad.v +++ b/test_regress/t/t_preproc_eof4_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 "blah diff --git a/test_regress/t/t_preproc_eof_qqq_bad.py b/test_regress/t/t_preproc_eof_qqq_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_preproc_eof_qqq_bad.py +++ b/test_regress/t/t_preproc_eof_qqq_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_eof_qqq_bad.v b/test_regress/t/t_preproc_eof_qqq_bad.v index 6f936b832..ff34c5843 100644 --- a/test_regress/t/t_preproc_eof_qqq_bad.v +++ b/test_regress/t/t_preproc_eof_qqq_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 """str diff --git a/test_regress/t/t_preproc_ifdef.py b/test_regress/t/t_preproc_ifdef.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_preproc_ifdef.py +++ b/test_regress/t/t_preproc_ifdef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_ifdef.v b/test_regress/t/t_preproc_ifdef.v index d333a7767..8df3a83ec 100644 --- a/test_regress/t/t_preproc_ifdef.v +++ b/test_regress/t/t_preproc_ifdef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_preproc_ifdefend_bad.py b/test_regress/t/t_preproc_ifdefend_bad.py index 889534217..b4b069353 100755 --- a/test_regress/t/t_preproc_ifdefend_bad.py +++ b/test_regress/t/t_preproc_ifdefend_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_ifdefend_bad.v b/test_regress/t/t_preproc_ifdefend_bad.v index 3effb41d1..5fe28c7e5 100644 --- a/test_regress/t/t_preproc_ifdefend_bad.v +++ b/test_regress/t/t_preproc_ifdefend_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef FOO diff --git a/test_regress/t/t_preproc_ifexpr.py b/test_regress/t/t_preproc_ifexpr.py index 977858180..b615ba94b 100755 --- a/test_regress/t/t_preproc_ifexpr.py +++ b/test_regress/t/t_preproc_ifexpr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_ifexpr.v b/test_regress/t/t_preproc_ifexpr.v index d56963d40..f57827e55 100644 --- a/test_regress/t/t_preproc_ifexpr.v +++ b/test_regress/t/t_preproc_ifexpr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `begin_keywords "1800-2023" diff --git a/test_regress/t/t_preproc_ifexpr_bad.py b/test_regress/t/t_preproc_ifexpr_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_preproc_ifexpr_bad.py +++ b/test_regress/t/t_preproc_ifexpr_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_ifexpr_bad.v b/test_regress/t/t_preproc_ifexpr_bad.v index 208a78528..329a32c76 100644 --- a/test_regress/t/t_preproc_ifexpr_bad.v +++ b/test_regress/t/t_preproc_ifexpr_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `begin_keywords "1800-2023" diff --git a/test_regress/t/t_preproc_inc2.vh b/test_regress/t/t_preproc_inc2.vh index 89ab6d752..5513d5f36 100644 --- a/test_regress/t/t_preproc_inc2.vh +++ b/test_regress/t/t_preproc_inc2.vh @@ -1,6 +1,6 @@ // DESCRIPTION: Verilog::Preproc: Example source code -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2000-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2000-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 At file `__FILE__ line `__LINE__ `define INCFILE diff --git a/test_regress/t/t_preproc_inc3.vh b/test_regress/t/t_preproc_inc3.vh index 9d3d91ac4..f3cd73c9a 100644 --- a/test_regress/t/t_preproc_inc3.vh +++ b/test_regress/t/t_preproc_inc3.vh @@ -1,6 +1,6 @@ // DESCRIPTION: Verilog::Preproc: Example source code -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2000-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2000-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifndef _EXAMPLE_INC2_V_ diff --git a/test_regress/t/t_preproc_inc4.vh b/test_regress/t/t_preproc_inc4.vh index 7f5b187a3..f80e5c874 100644 --- a/test_regress/t/t_preproc_inc4.vh +++ b/test_regress/t/t_preproc_inc4.vh @@ -1,6 +1,6 @@ // DESCRIPTION: Verilog::Preproc: Example source code -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2000-2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2000-2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define T_PREPROC_INC4 diff --git a/test_regress/t/t_preproc_inc_bad.py b/test_regress/t/t_preproc_inc_bad.py index b16466729..15c9e41a3 100755 --- a/test_regress/t/t_preproc_inc_bad.py +++ b/test_regress/t/t_preproc_inc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_inc_bad.v b/test_regress/t/t_preproc_inc_bad.v index a9dd80fc6..b9c6b3d6f 100644 --- a/test_regress/t/t_preproc_inc_bad.v +++ b/test_regress/t/t_preproc_inc_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //See bug289 diff --git a/test_regress/t/t_preproc_inc_fn_bad.py b/test_regress/t/t_preproc_inc_fn_bad.py index b16466729..15c9e41a3 100755 --- a/test_regress/t/t_preproc_inc_fn_bad.py +++ b/test_regress/t/t_preproc_inc_fn_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_inc_fn_bad.v b/test_regress/t/t_preproc_inc_fn_bad.v index 49fd4a1a5..410abbb98 100644 --- a/test_regress/t/t_preproc_inc_fn_bad.v +++ b/test_regress/t/t_preproc_inc_fn_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include `else diff --git a/test_regress/t/t_preproc_inc_inc_bad.vh b/test_regress/t/t_preproc_inc_inc_bad.vh index 83cab6aaf..e854c817a 100644 --- a/test_regress/t/t_preproc_inc_inc_bad.vh +++ b/test_regress/t/t_preproc_inc_inc_bad.vh @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module xx; diff --git a/test_regress/t/t_preproc_inc_notfound_bad.py b/test_regress/t/t_preproc_inc_notfound_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_preproc_inc_notfound_bad.py +++ b/test_regress/t/t_preproc_inc_notfound_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_inc_notfound_bad.v b/test_regress/t/t_preproc_inc_notfound_bad.v index fb4d0cfbd..aa91c7930 100644 --- a/test_regress/t/t_preproc_inc_notfound_bad.v +++ b/test_regress/t/t_preproc_inc_notfound_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "this_file_is_not_found.vh" diff --git a/test_regress/t/t_preproc_inc_recurse_bad.py b/test_regress/t/t_preproc_inc_recurse_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_preproc_inc_recurse_bad.py +++ b/test_regress/t/t_preproc_inc_recurse_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_inc_recurse_bad.v b/test_regress/t/t_preproc_inc_recurse_bad.v index 21497beef..0914b9887 100644 --- a/test_regress/t/t_preproc_inc_recurse_bad.v +++ b/test_regress/t/t_preproc_inc_recurse_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "t_preproc_inc_recurse_bad.v" diff --git a/test_regress/t/t_preproc_kwd.py b/test_regress/t/t_preproc_kwd.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_preproc_kwd.py +++ b/test_regress/t/t_preproc_kwd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v index 6b11486ea..bae08217a 100644 --- a/test_regress/t/t_preproc_kwd.v +++ b/test_regress/t/t_preproc_kwd.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_preproc_kwd_bad.py b/test_regress/t/t_preproc_kwd_bad.py index 291d7509d..8e9369e4c 100755 --- a/test_regress/t/t_preproc_kwd_bad.py +++ b/test_regress/t/t_preproc_kwd_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_kwd_bad.v b/test_regress/t/t_preproc_kwd_bad.v index 16c423b8b..d89d01905 100644 --- a/test_regress/t/t_preproc_kwd_bad.v +++ b/test_regress/t/t_preproc_kwd_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `end_keywords diff --git a/test_regress/t/t_preproc_nodef_bad.py b/test_regress/t/t_preproc_nodef_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_preproc_nodef_bad.py +++ b/test_regress/t/t_preproc_nodef_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_nodef_bad.v b/test_regress/t/t_preproc_nodef_bad.v index 3c0c23d5b..b596bb765 100644 --- a/test_regress/t/t_preproc_nodef_bad.v +++ b/test_regress/t/t_preproc_nodef_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `not_defined diff --git a/test_regress/t/t_preproc_noline.py b/test_regress/t/t_preproc_noline.py index 60dd75a8c..7bf13ade8 100755 --- a/test_regress/t/t_preproc_noline.py +++ b/test_regress/t/t_preproc_noline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_noline.v b/test_regress/t/t_preproc_noline.v index 3f7c72700..9a2360d65 100644 --- a/test_regress/t/t_preproc_noline.v +++ b/test_regress/t/t_preproc_noline.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define CHECK text \ diff --git a/test_regress/t/t_preproc_persist.py b/test_regress/t/t_preproc_persist.py index 1fba47b6f..779e4971e 100755 --- a/test_regress/t/t_preproc_persist.py +++ b/test_regress/t/t_preproc_persist.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_persist.v b/test_regress/t/t_preproc_persist.v index b78e3d90d..0bfd24252 100644 --- a/test_regress/t/t_preproc_persist.v +++ b/test_regress/t/t_preproc_persist.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 Inside `__FILE__. diff --git a/test_regress/t/t_preproc_persist2.v b/test_regress/t/t_preproc_persist2.v index b78e3d90d..0bfd24252 100644 --- a/test_regress/t/t_preproc_persist2.v +++ b/test_regress/t/t_preproc_persist2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 Inside `__FILE__. diff --git a/test_regress/t/t_preproc_persist_inc.v b/test_regress/t/t_preproc_persist_inc.v index d16add4c7..30e3b54aa 100644 --- a/test_regress/t/t_preproc_persist_inc.v +++ b/test_regress/t/t_preproc_persist_inc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifndef COMMON_GUARD diff --git a/test_regress/t/t_preproc_preproczero_bad.py b/test_regress/t/t_preproc_preproczero_bad.py index b213d98c3..fe1d61e40 100755 --- a/test_regress/t/t_preproc_preproczero_bad.py +++ b/test_regress/t/t_preproc_preproczero_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_preproczero_bad.v b/test_regress/t/t_preproc_preproczero_bad.v index b6af66740..9a0130a50 100644 --- a/test_regress/t/t_preproc_preproczero_bad.v +++ b/test_regress/t/t_preproc_preproczero_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `begin_keywords "1800-2023" diff --git a/test_regress/t/t_preproc_resolve.out b/test_regress/t/t_preproc_resolve.out index ca8171e87..6d4a3c27e 100644 --- a/test_regress/t/t_preproc_resolve.out +++ b/test_regress/t/t_preproc_resolve.out @@ -4,28 +4,29 @@ lint_off -rule NONSTD `begin_keywords "1800-2023" `timescale 1ns/1ps module top( - input logic clk, - input logic rst, - output logic top_out + input logic clk, + input logic rst, + output logic top_out ); - submod u_submod ( - .clk (clk), - .rst (rst), - .out_signal(top_out) - ); + submod u_submod ( + .clk (clk), + .rst (rst), + .out_signal(top_out) + ); endmodule `begin_keywords "1800-2023" -`timescale 1ns/1ps -module submod( - input logic clk, - input logic rst, - output logic out_signal +`timescale 1ns / 1ps +module submod ( + input logic clk, + input logic rst, + output logic out_signal ); - always_ff @(posedge clk or posedge rst) begin - if (rst) begin - out_signal <= 1'b0; - end else begin - out_signal <= ~out_signal; - end - end + always_ff @(posedge clk or posedge rst) begin + if (rst) begin + out_signal <= 1'b0; + end + else begin + out_signal <= ~out_signal; + end + end endmodule diff --git a/test_regress/t/t_preproc_resolve.py b/test_regress/t/t_preproc_resolve.py index 8cc950b99..3c3820119 100755 --- a/test_regress/t/t_preproc_resolve.py +++ b/test_regress/t/t_preproc_resolve.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_resolve.v b/test_regress/t/t_preproc_resolve.v index 7d49cd8d0..b31072be1 100644 --- a/test_regress/t/t_preproc_resolve.v +++ b/test_regress/t/t_preproc_resolve.v @@ -1,18 +1,18 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps module top(/*AUTOARG*/ - input logic clk, - input logic rst, - output logic top_out + input logic clk, + input logic rst, + output logic top_out ); - submod u_submod (/*AUTOINST*/ - .clk (clk), - .rst (rst), - .out_signal(top_out) - ); + submod u_submod (/*AUTOINST*/ + .clk (clk), + .rst (rst), + .out_signal(top_out) + ); endmodule diff --git a/test_regress/t/t_preproc_resolve/submod.sv b/test_regress/t/t_preproc_resolve/submod.sv index 701cd7269..505282d05 100644 --- a/test_regress/t/t_preproc_resolve/submod.sv +++ b/test_regress/t/t_preproc_resolve/submod.sv @@ -1,20 +1,21 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -`timescale 1ns/1ps -module submod(/*AUTOARG*/ - input logic clk, - input logic rst, - output logic out_signal +`timescale 1ns / 1ps +module submod ( + input logic clk, + input logic rst, + output logic out_signal ); - always_ff @(posedge clk or posedge rst) begin - if (rst) begin - out_signal <= 1'b0; - end else begin - out_signal <= ~out_signal; - end - end + always_ff @(posedge clk or posedge rst) begin + if (rst) begin + out_signal <= 1'b0; + end + else begin + out_signal <= ~out_signal; + end + end endmodule diff --git a/test_regress/t/t_preproc_resolve_config.vlt b/test_regress/t/t_preproc_resolve_config.vlt index ed2310c9b..a047f3110 100644 --- a/test_regress/t/t_preproc_resolve_config.vlt +++ b/test_regress/t/t_preproc_resolve_config.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_preproc_str_undef.py b/test_regress/t/t_preproc_str_undef.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_preproc_str_undef.py +++ b/test_regress/t/t_preproc_str_undef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_str_undef.v b/test_regress/t/t_preproc_str_undef.v index 1ab629a7f..ef072b9b2 100644 --- a/test_regress/t/t_preproc_str_undef.v +++ b/test_regress/t/t_preproc_str_undef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define PREFIX_ my_prefix_ diff --git a/test_regress/t/t_preproc_strify_join.py b/test_regress/t/t_preproc_strify_join.py index 981d60faf..3f1eac3ae 100755 --- a/test_regress/t/t_preproc_strify_join.py +++ b/test_regress/t/t_preproc_strify_join.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_strify_join.v b/test_regress/t/t_preproc_strify_join.v index 88241fae5..de49f3d8e 100644 --- a/test_regress/t/t_preproc_strify_join.v +++ b/test_regress/t/t_preproc_strify_join.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `define FOO foo diff --git a/test_regress/t/t_preproc_stringend_bad.py b/test_regress/t/t_preproc_stringend_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_preproc_stringend_bad.py +++ b/test_regress/t/t_preproc_stringend_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_stringend_bad.v b/test_regress/t/t_preproc_stringend_bad.v index 6c7f56c2d..4f2024eeb 100644 --- a/test_regress/t/t_preproc_stringend_bad.v +++ b/test_regress/t/t_preproc_stringend_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 "Blah diff --git a/test_regress/t/t_preproc_ttempty.py b/test_regress/t/t_preproc_ttempty.py index 28ad7e4b2..53762f285 100755 --- a/test_regress/t/t_preproc_ttempty.py +++ b/test_regress/t/t_preproc_ttempty.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_ttempty.v b/test_regress/t/t_preproc_ttempty.v index 75fdd9499..3334453a1 100644 --- a/test_regress/t/t_preproc_ttempty.v +++ b/test_regress/t/t_preproc_ttempty.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //`define TARGET_PACKAGE diff --git a/test_regress/t/t_preproc_undefineall.py b/test_regress/t/t_preproc_undefineall.py index 07b8cc53a..0fd661ab7 100755 --- a/test_regress/t/t_preproc_undefineall.py +++ b/test_regress/t/t_preproc_undefineall.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_preproc_undefineall.v b/test_regress/t/t_preproc_undefineall.v index 3c233eb5d..0fb666e3e 100644 --- a/test_regress/t/t_preproc_undefineall.v +++ b/test_regress/t/t_preproc_undefineall.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_priority_case.py b/test_regress/t/t_priority_case.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_priority_case.py +++ b/test_regress/t/t_priority_case.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_priority_case.v b/test_regress/t/t_priority_case.v index 477752748..7a3069ccd 100644 --- a/test_regress/t/t_priority_case.v +++ b/test_regress/t/t_priority_case.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Rupert Swarbrick. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Rupert Swarbrick // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_probdist.py b/test_regress/t/t_probdist.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_probdist.py +++ b/test_regress/t/t_probdist.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_probdist.v b/test_regress/t/t_probdist.v index 3547b3cfc..340455f92 100644 --- a/test_regress/t/t_probdist.v +++ b/test_regress/t/t_probdist.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_probdist_bad.py b/test_regress/t/t_probdist_bad.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_probdist_bad.py +++ b/test_regress/t/t_probdist_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_probdist_bad.v b/test_regress/t/t_probdist_bad.v index 4c1e55881..672412e16 100644 --- a/test_regress/t/t_probdist_bad.v +++ b/test_regress/t/t_probdist_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_probdist_cmake.py b/test_regress/t/t_probdist_cmake.py index db9e11c29..3238eefa8 100755 --- a/test_regress/t/t_probdist_cmake.py +++ b/test_regress/t/t_probdist_cmake.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process.py b/test_regress/t/t_process.py index 299c161ca..a4f6212a5 100755 --- a/test_regress/t/t_process.py +++ b/test_regress/t/t_process.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process.v b/test_regress/t/t_process.v index 81d3f8017..e800d6707 100644 --- a/test_regress/t/t_process.v +++ b/test_regress/t/t_process.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: diff --git a/test_regress/t/t_process_always.py b/test_regress/t/t_process_always.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_process_always.py +++ b/test_regress/t/t_process_always.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_always.v b/test_regress/t/t_process_always.v index f4d49a8f2..82477995a 100644 --- a/test_regress/t/t_process_always.v +++ b/test_regress/t/t_process_always.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_process_bad.py b/test_regress/t/t_process_bad.py index 9536f58b9..24048b079 100755 --- a/test_regress/t/t_process_bad.py +++ b/test_regress/t/t_process_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_bad.v b/test_regress/t/t_process_bad.v index c336e912e..665c7c1d7 100644 --- a/test_regress/t/t_process_bad.v +++ b/test_regress/t/t_process_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_process_compare.py b/test_regress/t/t_process_compare.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_process_compare.py +++ b/test_regress/t/t_process_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_compare.v b/test_regress/t/t_process_compare.v index ab2b7e233..02f7dcc2e 100644 --- a/test_regress/t/t_process_compare.v +++ b/test_regress/t/t_process_compare.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class A; diff --git a/test_regress/t/t_process_copy_constr.py b/test_regress/t/t_process_copy_constr.py index 34b0247e9..c1140f359 100755 --- a/test_regress/t/t_process_copy_constr.py +++ b/test_regress/t/t_process_copy_constr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_copy_constr.v b/test_regress/t/t_process_copy_constr.v index 3bbadf5c2..fa335548a 100644 --- a/test_regress/t/t_process_copy_constr.v +++ b/test_regress/t/t_process_copy_constr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_process_finished.py b/test_regress/t/t_process_finished.py index 34b0247e9..c1140f359 100755 --- a/test_regress/t/t_process_finished.py +++ b/test_regress/t/t_process_finished.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_finished.v b/test_regress/t/t_process_finished.v index df6f6cc28..109acb469 100644 --- a/test_regress/t/t_process_finished.v +++ b/test_regress/t/t_process_finished.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_process_fork.py b/test_regress/t/t_process_fork.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_process_fork.py +++ b/test_regress/t/t_process_fork.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_fork.v b/test_regress/t/t_process_fork.v index 90020c506..854c050ea 100644 --- a/test_regress/t/t_process_fork.v +++ b/test_regress/t/t_process_fork.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_process_fork_block.py b/test_regress/t/t_process_fork_block.py index dcb1ff476..4641abd21 100755 --- a/test_regress/t/t_process_fork_block.py +++ b/test_regress/t/t_process_fork_block.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_fork_block.v b/test_regress/t/t_process_fork_block.v index ab6ed5d59..6bf216615 100644 --- a/test_regress/t/t_process_fork_block.v +++ b/test_regress/t/t_process_fork_block.v @@ -1,26 +1,26 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; - process job; + process job; - initial begin - process p1 = process::self(); - fork - begin - wait(p1.status() != process::RUNNING); - $write("job started\n"); - job = process::self(); - end - join_none - wait (job); - $write("all jobs started\n"); - job.await(); - $write("all jobs finished\n"); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + automatic process p1 = process::self(); + fork + begin + wait (p1.status() != process::RUNNING); + $write("job started\n"); + job = process::self(); + end + join_none + wait (job); + $write("all jobs started\n"); + job.await(); + $write("all jobs finished\n"); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_process_kill.py b/test_regress/t/t_process_kill.py index 34b0247e9..c1140f359 100755 --- a/test_regress/t/t_process_kill.py +++ b/test_regress/t/t_process_kill.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_kill.v b/test_regress/t/t_process_kill.v index a382bfcf4..f5ed09ea1 100644 --- a/test_regress/t/t_process_kill.v +++ b/test_regress/t/t_process_kill.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_process_notiming.py b/test_regress/t/t_process_notiming.py index a4f6917ce..ca5c0f0d5 100755 --- a/test_regress/t/t_process_notiming.py +++ b/test_regress/t/t_process_notiming.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_propagation.py b/test_regress/t/t_process_propagation.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_process_propagation.py +++ b/test_regress/t/t_process_propagation.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_propagation.v b/test_regress/t/t_process_propagation.v index 70973bcba..169649f36 100644 --- a/test_regress/t/t_process_propagation.v +++ b/test_regress/t/t_process_propagation.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 event evt1, evt2; diff --git a/test_regress/t/t_process_rand.py b/test_regress/t/t_process_rand.py index 80206c4ae..36f4378a8 100755 --- a/test_regress/t/t_process_rand.py +++ b/test_regress/t/t_process_rand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_rand.v b/test_regress/t/t_process_rand.v index 20978fc04..2607e4dd3 100644 --- a/test_regress/t/t_process_rand.v +++ b/test_regress/t/t_process_rand.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_process_redecl.py b/test_regress/t/t_process_redecl.py index c8dddaddf..67b896515 100755 --- a/test_regress/t/t_process_redecl.py +++ b/test_regress/t/t_process_redecl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_redecl.v b/test_regress/t/t_process_redecl.v index 0263e5c56..78b46f537 100644 --- a/test_regress/t/t_process_redecl.v +++ b/test_regress/t/t_process_redecl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_process_std.py b/test_regress/t/t_process_std.py index a53e3de39..740e9060f 100755 --- a/test_regress/t/t_process_std.py +++ b/test_regress/t/t_process_std.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_task.py b/test_regress/t/t_process_task.py index 80206c4ae..36f4378a8 100755 --- a/test_regress/t/t_process_task.py +++ b/test_regress/t/t_process_task.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_process_task.v b/test_regress/t/t_process_task.v index 5701b47b3..9e7d41ad3 100644 --- a/test_regress/t/t_process_task.v +++ b/test_regress/t/t_process_task.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t(); diff --git a/test_regress/t/t_prof.py b/test_regress/t/t_prof.py index 429e6a0ac..bd0aafa67 100755 --- a/test_regress/t/t_prof.py +++ b/test_regress/t/t_prof.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_prof.v b/test_regress/t/t_prof.v index 30002a14f..9bce13891 100644 --- a/test_regress/t/t_prof.v +++ b/test_regress/t/t_prof.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t( diff --git a/test_regress/t/t_prof_timing.py b/test_regress/t/t_prof_timing.py index 6f3f7a570..cb9252310 100755 --- a/test_regress/t/t_prof_timing.py +++ b/test_regress/t/t_prof_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_profc.py b/test_regress/t/t_profc.py index a70fca363..506bf751f 100755 --- a/test_regress/t/t_profc.py +++ b/test_regress/t/t_profc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_profcfunc.py b/test_regress/t/t_profcfunc.py index b9523a78b..16540811f 100755 --- a/test_regress/t/t_profcfunc.py +++ b/test_regress/t/t_profcfunc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_program.py b/test_regress/t/t_program.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_program.py +++ b/test_regress/t/t_program.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_program.v b/test_regress/t/t_program.v index d87524c1f..8f12edd40 100644 --- a/test_regress/t/t_program.v +++ b/test_regress/t/t_program.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 program t; diff --git a/test_regress/t/t_program_anonymous.py b/test_regress/t/t_program_anonymous.py index 966dc53da..20b96a7d7 100755 --- a/test_regress/t/t_program_anonymous.py +++ b/test_regress/t/t_program_anonymous.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_program_anonymous.v b/test_regress/t/t_program_anonymous.v index 2fb5ec90d..b16086ffa 100644 --- a/test_regress/t/t_program_anonymous.v +++ b/test_regress/t/t_program_anonymous.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 program; diff --git a/test_regress/t/t_program_extern.out b/test_regress/t/t_program_extern.out deleted file mode 100644 index 13c1988fa..000000000 --- a/test_regress/t/t_program_extern.out +++ /dev/null @@ -1,11 +0,0 @@ -%Error-UNSUPPORTED: t/t_program_extern.v:7:1: Unsupported: extern program - 7 | extern program ex_pgm; - | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_program_extern.v:8:1: Unsupported: extern interface - 8 | extern interface ex_ifc; - | ^~~~~~ -%Error-UNSUPPORTED: t/t_program_extern.v:9:1: Unsupported: extern module - 9 | extern module ex_mod; - | ^~~~~~ -%Error: Exiting due to diff --git a/test_regress/t/t_program_extern.py b/test_regress/t/t_program_extern.py index 966dc53da..cf9cbcb93 100755 --- a/test_regress/t/t_program_extern.py +++ b/test_regress/t/t_program_extern.py @@ -1,19 +1,18 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('simulator_st') -test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) +test.compile() -if not test.vlt_all: - test.execute() +test.execute() test.passes() diff --git a/test_regress/t/t_program_extern.v b/test_regress/t/t_program_extern.v index be637049d..a912f94aa 100644 --- a/test_regress/t/t_program_extern.v +++ b/test_regress/t/t_program_extern.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 extern program ex_pgm; @@ -10,14 +10,23 @@ extern module ex_mod; module t; - ex_pgm u_pgm(); - ex_ifc u_ifc(); - ex_mod u_mod(); + ex_pgm u_pgm(); + ex_ifc u_ifc(); + ex_mod u_mod(); - initial begin - ex_task(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule + +// Could be in another compile run, but we don't support that +program ex_pgm; +endprogram + +interface ex_ifc; +endinterface + +module ex_mod; +endmodule diff --git a/test_regress/t/t_property.py b/test_regress/t/t_property.py index 724621ce6..3c390daaf 100755 --- a/test_regress/t/t_property.py +++ b/test_regress/t/t_property.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property.v b/test_regress/t/t_property.v index f530048b2..b7b196b1f 100644 --- a/test_regress/t/t_property.v +++ b/test_regress/t/t_property.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_property_fail_1.py b/test_regress/t/t_property_fail_1.py index 4caf548d3..261586eee 100755 --- a/test_regress/t/t_property_fail_1.py +++ b/test_regress/t/t_property_fail_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_fail_2_bad.py b/test_regress/t/t_property_fail_2_bad.py index b0a2ba504..37c3a7bb5 100755 --- a/test_regress/t/t_property_fail_2_bad.py +++ b/test_regress/t/t_property_fail_2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_named.py b/test_regress/t/t_property_named.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_property_named.py +++ b/test_regress/t/t_property_named.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_named.v b/test_regress/t/t_property_named.v index ceb2ad90c..85d707eae 100644 --- a/test_regress/t/t_property_named.v +++ b/test_regress/t/t_property_named.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_property_negated.py b/test_regress/t/t_property_negated.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_property_negated.py +++ b/test_regress/t/t_property_negated.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_negated.v b/test_regress/t/t_property_negated.v index 23243c04b..72f4772a0 100644 --- a/test_regress/t/t_property_negated.v +++ b/test_regress/t/t_property_negated.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define MAX 10 diff --git a/test_regress/t/t_property_pexpr.py b/test_regress/t/t_property_pexpr.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_property_pexpr.py +++ b/test_regress/t/t_property_pexpr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_pexpr.v b/test_regress/t/t_property_pexpr.v index 82bd119bc..b09acf263 100644 --- a/test_regress/t/t_property_pexpr.v +++ b/test_regress/t/t_property_pexpr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_property_pexpr_unsup.py b/test_regress/t/t_property_pexpr_unsup.py index 7b40cd490..4805ab926 100755 --- a/test_regress/t/t_property_pexpr_unsup.py +++ b/test_regress/t/t_property_pexpr_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_pexpr_unsup.v b/test_regress/t/t_property_pexpr_unsup.v index e8143e993..464ca558b 100644 --- a/test_regress/t/t_property_pexpr_unsup.v +++ b/test_regress/t/t_property_pexpr_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_property_recursive_unsup.py b/test_regress/t/t_property_recursive_unsup.py index 7e5bcdfe5..b5718946c 100755 --- a/test_regress/t/t_property_recursive_unsup.py +++ b/test_regress/t/t_property_recursive_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_recursive_unsup.v b/test_regress/t/t_property_recursive_unsup.v index b6d91ad47..9acff81ba 100644 --- a/test_regress/t/t_property_recursive_unsup.v +++ b/test_regress/t/t_property_recursive_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_property_sexpr.py b/test_regress/t/t_property_sexpr.py index 786072909..a8d77fc30 100755 --- a/test_regress/t/t_property_sexpr.py +++ b/test_regress/t/t_property_sexpr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_sexpr.v b/test_regress/t/t_property_sexpr.v index 5bbb48f90..a48d6631a 100644 --- a/test_regress/t/t_property_sexpr.v +++ b/test_regress/t/t_property_sexpr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_property_sexpr2_bad.py b/test_regress/t/t_property_sexpr2_bad.py index 5562c90e9..cc0c9c826 100755 --- a/test_regress/t/t_property_sexpr2_bad.py +++ b/test_regress/t/t_property_sexpr2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_sexpr2_bad.v b/test_regress/t/t_property_sexpr2_bad.v index c64745024..c927cc466 100644 --- a/test_regress/t/t_property_sexpr2_bad.v +++ b/test_regress/t/t_property_sexpr2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_property_sexpr_bad.py b/test_regress/t/t_property_sexpr_bad.py index 5562c90e9..cc0c9c826 100755 --- a/test_regress/t/t_property_sexpr_bad.py +++ b/test_regress/t/t_property_sexpr_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_sexpr_bad.v b/test_regress/t/t_property_sexpr_bad.v index d5f82cce3..c05db11c0 100644 --- a/test_regress/t/t_property_sexpr_bad.v +++ b/test_regress/t/t_property_sexpr_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_property_sexpr_cov.py b/test_regress/t/t_property_sexpr_cov.py index 9ca3456b4..c7339ea5e 100755 --- a/test_regress/t/t_property_sexpr_cov.py +++ b/test_regress/t/t_property_sexpr_cov.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_sexpr_cov.v b/test_regress/t/t_property_sexpr_cov.v index a23742ba2..59fa3ddc9 100644 --- a/test_regress/t/t_property_sexpr_cov.v +++ b/test_regress/t/t_property_sexpr_cov.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ diff --git a/test_regress/t/t_property_sexpr_disable.py b/test_regress/t/t_property_sexpr_disable.py new file mode 100755 index 000000000..35e44000c --- /dev/null +++ b/test_regress/t/t_property_sexpr_disable.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(timing_loop=True, verilator_flags2=['--assert', '--timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_property_sexpr_disable.v b/test_regress/t/t_property_sexpr_disable.v new file mode 100644 index 000000000..b2df8471f --- /dev/null +++ b/test_regress/t/t_property_sexpr_disable.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv, + expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%p exp='h%p\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t ( /*AUTOARG*/ + // Inputs + clk +); + + input clk; + + typedef struct { + int fails; + int passs; + } result_t; + + result_t results[int]; + result_t expected[int]; + + localparam MAX = 15; + integer cyc = 0; + + assert property (@(posedge clk) disable iff (cyc == 5 || cyc > MAX) 1 ##1 cyc < 10) + results[1].passs++; + else results[1].fails++; + + assert property (@(posedge clk) disable iff (1) 1 ##1 0) + results[2].passs++; + else results[2].fails++; + + assert property (@(posedge clk) disable iff (0) 1 ##1 0) + results[3].passs++; + else results[3].fails++; + + always @(clk) begin + ++cyc; + if (cyc == MAX) begin + expected[1] = '{2, 3}; + // expected[2] shouldn't be initialized + expected[3] = '{6, 0}; + `checkh(results, expected); + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_property_sexpr_disable_sampled_unsup.out b/test_regress/t/t_property_sexpr_disable_sampled_unsup.out new file mode 100644 index 000000000..9c988bb01 --- /dev/null +++ b/test_regress/t/t_property_sexpr_disable_sampled_unsup.out @@ -0,0 +1,6 @@ +%Error-UNSUPPORTED: t/t_property_sexpr_disable_sampled_unsup.v:23:48: Unsupported: $sampled inside disabled condition of a sequence + : ... note: In instance 't' + 23 | assert property (@(posedge clk) disable iff ($sampled(cyc) == 4) 1 ##1 cyc % 3 == 0) passes++; + | ^~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_property_sexpr_disable_sampled_unsup.py b/test_regress/t/t_property_sexpr_disable_sampled_unsup.py new file mode 100755 index 000000000..504773395 --- /dev/null +++ b/test_regress/t/t_property_sexpr_disable_sampled_unsup.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, + verilator_flags2=['--assert', '--timing', '--error-limit 1000'], + fails=True) + +test.passes() diff --git a/test_regress/t/t_property_sexpr_disable_sampled_unsup.v b/test_regress/t/t_property_sexpr_disable_sampled_unsup.v new file mode 100644 index 000000000..1172b73c1 --- /dev/null +++ b/test_regress/t/t_property_sexpr_disable_sampled_unsup.v @@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv, + expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%p exp='h%p\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t ( /*AUTOARG*/ + // Inputs + clk +); + + input clk; + + localparam MAX = 10; + int cyc = 0; + int passes = 0; + int fails = 0; + + assert property (@(posedge clk) disable iff ($sampled(cyc) == 4) 1 ##1 cyc % 3 == 0) passes++; + else fails++; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == MAX) begin + `checkh(passes, 3); + `checkh(fails, 4); + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_property_sexpr_multi.py b/test_regress/t/t_property_sexpr_multi.py index 722b56945..5de1b48bd 100755 --- a/test_regress/t/t_property_sexpr_multi.py +++ b/test_regress/t/t_property_sexpr_multi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_sexpr_multi.v b/test_regress/t/t_property_sexpr_multi.v index 1ee6e9dce..1de021431 100644 --- a/test_regress/t/t_property_sexpr_multi.v +++ b/test_regress/t/t_property_sexpr_multi.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_property_sexpr_parse_unsup.out b/test_regress/t/t_property_sexpr_parse_unsup.out index 4c017ae88..0449d4338 100644 --- a/test_regress/t/t_property_sexpr_parse_unsup.out +++ b/test_regress/t/t_property_sexpr_parse_unsup.out @@ -1,23 +1,23 @@ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:75:14: Unsupported: sequence match items - 75 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b]; +%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:65:14: Unsupported: sequence match items + 65 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b]; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:75:29: Unsupported: ## range cycle delay range expression - 75 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b]; +%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:65:29: Unsupported: ## range cycle delay range expression + 65 | ($rose(a), l_b = b) |-> ##[3:10] q[l_b]; | ^~ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:74:13: Unsupported: property variable declaration - 74 | integer l_b; +%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:64:13: Unsupported: property variable declaration + 64 | integer l_b; | ^~~ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:92:16: Unsupported: sequence match items - 92 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; +%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:82:16: Unsupported: sequence match items + 82 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; | ^ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:92:51: Unsupported: [-> boolean abbrev expression - 92 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; +%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:82:51: Unsupported: [-> boolean abbrev expression + 82 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; | ^~~ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:92:54: Unsupported: boolean abbrev (in sequence expression) - 92 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; +%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:82:54: Unsupported: boolean abbrev (in sequence expression) + 82 | (count == 0, l_t = $realtime) ##1 (count == 7)[->1] |-> $realtime - l_t < 50.5; | ^ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:90:14: Unsupported: property variable declaration - 90 | realtime l_t; +%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:80:14: Unsupported: property variable declaration + 80 | realtime l_t; | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_property_sexpr_parse_unsup.py b/test_regress/t/t_property_sexpr_parse_unsup.py index 6f175f1ac..b775bd8bc 100755 --- a/test_regress/t/t_property_sexpr_parse_unsup.py +++ b/test_regress/t/t_property_sexpr_parse_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_sexpr_unsup.out b/test_regress/t/t_property_sexpr_unsup.out index 67f822d29..137ce4bfb 100644 --- a/test_regress/t/t_property_sexpr_unsup.out +++ b/test_regress/t/t_property_sexpr_unsup.out @@ -27,24 +27,8 @@ : ... note: In instance 't' 43 | assert property (@(posedge clk) (##1 val) |-> (##1 val)) $display("[%0t] two delays implication stmt, fileline:%d", $time, 43); | ^~~ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:45:52: Unsupported: Disable iff with sequence expression +%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:46:18: Unsupported: Implication with sequence expression : ... note: In instance 't' - 45 | assert property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, 45); - | ^~ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:47:52: Unsupported: Disable iff with sequence expression - : ... note: In instance 't' - 47 | assume property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, 47); - | ^~ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:49:51: Unsupported: Disable iff with sequence expression - : ... note: In instance 't' - 49 | cover property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, 49); - | ^~ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:52:37: Unsupported: Disable iff with sequence expression - : ... note: In instance 't' - 52 | @(posedge clk) disable iff (cyc != 5) ##1 0; - | ^~ -%Error-UNSUPPORTED: t/t_property_sexpr_unsup.v:56:18: Unsupported: Implication with sequence expression - : ... note: In instance 't' - 56 | ##1 cyc == 4 |-> 1; + 46 | ##1 cyc == 4 |-> 1; | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_property_sexpr_unsup.py b/test_regress/t/t_property_sexpr_unsup.py index c8e1cbe53..f17bf6461 100755 --- a/test_regress/t/t_property_sexpr_unsup.py +++ b/test_regress/t/t_property_sexpr_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_sexpr_unsup.v b/test_regress/t/t_property_sexpr_unsup.v index da27da6c0..a424d576d 100644 --- a/test_regress/t/t_property_sexpr_unsup.v +++ b/test_regress/t/t_property_sexpr_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t ( /*AUTOARG*/ @@ -42,16 +42,6 @@ module t ( /*AUTOARG*/ assert property (@(posedge clk) (##1 val) |-> (##1 val)) $display("[%0t] two delays implication stmt, fileline:%d", $time, `__LINE__); - assert property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, `__LINE__); - - assume property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, `__LINE__); - - cover property (@(posedge clk) disable iff (cyc != 5) ##1 0) $display("[%0t] disable iff stmt, fileline:%d", $time, `__LINE__); - - property prop_disableiff; - @(posedge clk) disable iff (cyc != 5) ##1 0; - endproperty - property prop_implication; ##1 cyc == 4 |-> 1; endproperty diff --git a/test_regress/t/t_property_unsup.out b/test_regress/t/t_property_unsup.out index 4a00f5d06..0f5bb8cdc 100644 --- a/test_regress/t/t_property_unsup.out +++ b/test_regress/t/t_property_unsup.out @@ -1,116 +1,116 @@ -%Error-UNSUPPORTED: t/t_property_unsup.v:62:41: Unsupported: eventually[] (in property expression) - 62 | assert property (counter == 1 implies eventually[1: 2] counter == 3); +%Error-UNSUPPORTED: t/t_property_unsup.v:65:41: Unsupported: eventually[] (in property expression) + 65 | assert property (counter == 1 implies eventually[1: 2] counter == 3); | ^~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_property_unsup.v:77:20: Unsupported: eventually[] (in property expression) - 77 | assert property (eventually[0: 2] counter == 3); +%Error-UNSUPPORTED: t/t_property_unsup.v:80:20: Unsupported: eventually[] (in property expression) + 80 | assert property (eventually[0: 2] counter == 3); | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:87:21: Unsupported: always (in property expression) - 87 | assert property ((always a) implies (always a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:90:21: Unsupported: always (in property expression) + 90 | assert property ((always a) implies (always a)); | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:87:40: Unsupported: always (in property expression) - 87 | assert property ((always a) implies (always a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:90:40: Unsupported: always (in property expression) + 90 | assert property ((always a) implies (always a)); | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:89:26: Unsupported: always (in property expression) - 89 | assert property ((a or(always b)) implies (a or(always b))); +%Error-UNSUPPORTED: t/t_property_unsup.v:92:26: Unsupported: always (in property expression) + 92 | assert property ((a or(always b)) implies (a or(always b))); | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:89:23: Unsupported: or (in sequence expression) - 89 | assert property ((a or(always b)) implies (a or(always b))); +%Error-UNSUPPORTED: t/t_property_unsup.v:92:23: Unsupported: or (in sequence expression) + 92 | assert property ((a or(always b)) implies (a or(always b))); | ^~ -%Error-UNSUPPORTED: t/t_property_unsup.v:89:51: Unsupported: always (in property expression) - 89 | assert property ((a or(always b)) implies (a or(always b))); +%Error-UNSUPPORTED: t/t_property_unsup.v:92:51: Unsupported: always (in property expression) + 92 | assert property ((a or(always b)) implies (a or(always b))); | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:89:48: Unsupported: or (in sequence expression) - 89 | assert property ((a or(always b)) implies (a or(always b))); +%Error-UNSUPPORTED: t/t_property_unsup.v:92:48: Unsupported: or (in sequence expression) + 92 | assert property ((a or(always b)) implies (a or(always b))); | ^~ -%Error-UNSUPPORTED: t/t_property_unsup.v:91:21: Unsupported: eventually[] (in property expression) - 91 | assert property ((eventually[0: 1] a) implies (eventually[0: 1] a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:94:21: Unsupported: eventually[] (in property expression) + 94 | assert property ((eventually[0: 1] a) implies (eventually[0: 1] a)); | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:91:50: Unsupported: eventually[] (in property expression) - 91 | assert property ((eventually[0: 1] a) implies (eventually[0: 1] a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:94:50: Unsupported: eventually[] (in property expression) + 94 | assert property ((eventually[0: 1] a) implies (eventually[0: 1] a)); | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:93:21: Unsupported: s_eventually (in property expression) - 93 | assert property ((s_eventually a) implies (s_eventually a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:96:21: Unsupported: s_eventually (in property expression) + 96 | assert property ((s_eventually a) implies (s_eventually a)); | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:93:46: Unsupported: s_eventually (in property expression) - 93 | assert property ((s_eventually a) implies (s_eventually a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:96:46: Unsupported: s_eventually (in property expression) + 96 | assert property ((s_eventually a) implies (s_eventually a)); | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:95:23: Unsupported: until (in property expression) - 95 | assert property ((a until b) implies (a until b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:98:23: Unsupported: until (in property expression) + 98 | assert property ((a until b) implies (a until b)); | ^~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:95:43: Unsupported: until (in property expression) - 95 | assert property ((a until b) implies (a until b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:98:43: Unsupported: until (in property expression) + 98 | assert property ((a until b) implies (a until b)); | ^~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:97:23: Unsupported: s_until (in property expression) - 97 | assert property ((a s_until b) implies (a s_until b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:100:23: Unsupported: s_until (in property expression) + 100 | assert property ((a s_until b) implies (a s_until b)); | ^~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:97:45: Unsupported: s_until (in property expression) - 97 | assert property ((a s_until b) implies (a s_until b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:100:45: Unsupported: s_until (in property expression) + 100 | assert property ((a s_until b) implies (a s_until b)); | ^~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:99:23: Unsupported: until_with (in property expression) - 99 | assert property ((a until_with b) implies (a until_with b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:102:23: Unsupported: until_with (in property expression) + 102 | assert property ((a until_with b) implies (a until_with b)); | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:99:48: Unsupported: until_with (in property expression) - 99 | assert property ((a until_with b) implies (a until_with b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:102:48: Unsupported: until_with (in property expression) + 102 | assert property ((a until_with b) implies (a until_with b)); | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:101:23: Unsupported: s_until_with (in property expression) - 101 | assert property ((a s_until_with b) implies (a s_until_with b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:104:23: Unsupported: s_until_with (in property expression) + 104 | assert property ((a s_until_with b) implies (a s_until_with b)); | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:101:50: Unsupported: s_until_with (in property expression) - 101 | assert property ((a s_until_with b) implies (a s_until_with b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:104:50: Unsupported: s_until_with (in property expression) + 104 | assert property ((a s_until_with b) implies (a s_until_with b)); | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:105:23: Unsupported: #-# (in property expression) - 105 | assert property ((a #-# b) implies (a #-# b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:108:23: Unsupported: #-# (in property expression) + 108 | assert property ((a #-# b) implies (a #-# b)); | ^~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:105:41: Unsupported: #-# (in property expression) - 105 | assert property ((a #-# b) implies (a #-# b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:108:41: Unsupported: #-# (in property expression) + 108 | assert property ((a #-# b) implies (a #-# b)); | ^~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:115:21: Unsupported: always (in property expression) - 115 | assert property ((always a) iff (always a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:118:21: Unsupported: always (in property expression) + 118 | assert property ((always a) iff (always a)); | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:115:36: Unsupported: always (in property expression) - 115 | assert property ((always a) iff (always a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:118:36: Unsupported: always (in property expression) + 118 | assert property ((always a) iff (always a)); | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:117:21: Unsupported: eventually[] (in property expression) - 117 | assert property ((eventually[0: 1] a) iff (eventually[0: 1] a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:120:21: Unsupported: eventually[] (in property expression) + 120 | assert property ((eventually[0: 1] a) iff (eventually[0: 1] a)); | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:117:46: Unsupported: eventually[] (in property expression) - 117 | assert property ((eventually[0: 1] a) iff (eventually[0: 1] a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:120:46: Unsupported: eventually[] (in property expression) + 120 | assert property ((eventually[0: 1] a) iff (eventually[0: 1] a)); | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:119:21: Unsupported: s_eventually (in property expression) - 119 | assert property ((s_eventually a) iff (s_eventually a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:122:21: Unsupported: s_eventually (in property expression) + 122 | assert property ((s_eventually a) iff (s_eventually a)); | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:119:42: Unsupported: s_eventually (in property expression) - 119 | assert property ((s_eventually a) iff (s_eventually a)); +%Error-UNSUPPORTED: t/t_property_unsup.v:122:42: Unsupported: s_eventually (in property expression) + 122 | assert property ((s_eventually a) iff (s_eventually a)); | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:121:23: Unsupported: until (in property expression) - 121 | assert property ((a until b) iff (a until b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:124:23: Unsupported: until (in property expression) + 124 | assert property ((a until b) iff (a until b)); | ^~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:121:39: Unsupported: until (in property expression) - 121 | assert property ((a until b) iff (a until b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:124:39: Unsupported: until (in property expression) + 124 | assert property ((a until b) iff (a until b)); | ^~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:123:23: Unsupported: s_until (in property expression) - 123 | assert property ((a s_until b) iff (a s_until b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:126:23: Unsupported: s_until (in property expression) + 126 | assert property ((a s_until b) iff (a s_until b)); | ^~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:123:41: Unsupported: s_until (in property expression) - 123 | assert property ((a s_until b) iff (a s_until b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:126:41: Unsupported: s_until (in property expression) + 126 | assert property ((a s_until b) iff (a s_until b)); | ^~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:125:23: Unsupported: until_with (in property expression) - 125 | assert property ((a until_with b) iff (a until_with b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:128:23: Unsupported: until_with (in property expression) + 128 | assert property ((a until_with b) iff (a until_with b)); | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:125:44: Unsupported: until_with (in property expression) - 125 | assert property ((a until_with b) iff (a until_with b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:128:44: Unsupported: until_with (in property expression) + 128 | assert property ((a until_with b) iff (a until_with b)); | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:127:23: Unsupported: s_until_with (in property expression) - 127 | assert property ((a s_until_with b) iff (a s_until_with b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:130:23: Unsupported: s_until_with (in property expression) + 130 | assert property ((a s_until_with b) iff (a s_until_with b)); | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:127:46: Unsupported: s_until_with (in property expression) - 127 | assert property ((a s_until_with b) iff (a s_until_with b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:130:46: Unsupported: s_until_with (in property expression) + 130 | assert property ((a s_until_with b) iff (a s_until_with b)); | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:131:23: Unsupported: #-# (in property expression) - 131 | assert property ((a #-# b) iff (a #-# b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:134:23: Unsupported: #-# (in property expression) + 134 | assert property ((a #-# b) iff (a #-# b)); | ^~~ -%Error-UNSUPPORTED: t/t_property_unsup.v:131:37: Unsupported: #-# (in property expression) - 131 | assert property ((a #-# b) iff (a #-# b)); +%Error-UNSUPPORTED: t/t_property_unsup.v:134:37: Unsupported: #-# (in property expression) + 134 | assert property ((a #-# b) iff (a #-# b)); | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_property_unsup.py b/test_regress/t/t_property_unsup.py index 9acc8bd21..5bd92cf7b 100755 --- a/test_regress/t/t_property_unsup.py +++ b/test_regress/t/t_property_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_unsup.v b/test_regress/t/t_property_unsup.v index aaee26c34..49cfbedcd 100644 --- a/test_regress/t/t_property_unsup.v +++ b/test_regress/t/t_property_unsup.v @@ -1,3 +1,6 @@ +// SPDX-FileCopyrightText: 2001-2020 Daniel Kroening, Edmund Clarke +// SPDX-License-Identifier: BSD-3-Clause +// // (C) 2001-2020, Daniel Kroening, Edmund Clarke, // Computer Science Department, University of Oxford // Computer Science Department, Carnegie Mellon University diff --git a/test_regress/t/t_property_untyped.py b/test_regress/t/t_property_untyped.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_property_untyped.py +++ b/test_regress/t/t_property_untyped.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_untyped.v b/test_regress/t/t_property_untyped.v index 15f1bc81c..e13764522 100644 --- a/test_regress/t/t_property_untyped.v +++ b/test_regress/t/t_property_untyped.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_property_untyped_unsup.py b/test_regress/t/t_property_untyped_unsup.py index 7e5bcdfe5..b5718946c 100755 --- a/test_regress/t/t_property_untyped_unsup.py +++ b/test_regress/t/t_property_untyped_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_untyped_unsup.v b/test_regress/t/t_property_untyped_unsup.v index 9784c48fc..9bdb57374 100644 --- a/test_regress/t/t_property_untyped_unsup.v +++ b/test_regress/t/t_property_untyped_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_property_var_unsup.py b/test_regress/t/t_property_var_unsup.py index 25f9960b8..4d0f745d0 100755 --- a/test_regress/t/t_property_var_unsup.py +++ b/test_regress/t/t_property_var_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_property_var_unsup.v b/test_regress/t/t_property_var_unsup.v index 6b9170d09..30091f240 100644 --- a/test_regress/t/t_property_var_unsup.v +++ b/test_regress/t/t_property_var_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_protect_ids.py b/test_regress/t/t_protect_ids.py index 46de898d8..d92181ed2 100755 --- a/test_regress/t/t_protect_ids.py +++ b/test_regress/t/t_protect_ids.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_protect_ids.v b/test_regress/t/t_protect_ids.v index 031f12406..9f2bf7e9f 100644 --- a/test_regress/t/t_protect_ids.v +++ b/test_regress/t/t_protect_ids.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface secret_intf(); diff --git a/test_regress/t/t_protect_ids_bad.py b/test_regress/t/t_protect_ids_bad.py index 934f802f7..1b0a2fbd8 100755 --- a/test_regress/t/t_protect_ids_bad.py +++ b/test_regress/t/t_protect_ids_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_protect_ids_bad.v b/test_regress/t/t_protect_ids_bad.v index b102cb1b8..eb1adc426 100644 --- a/test_regress/t/t_protect_ids_bad.v +++ b/test_regress/t/t_protect_ids_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_protect_ids_c.cpp b/test_regress/t/t_protect_ids_c.cpp index 8c14a7cc8..9a52816b9 100644 --- a/test_regress/t/t_protect_ids_c.cpp +++ b/test_regress/t/t_protect_ids_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_protect_ids_debug.py b/test_regress/t/t_protect_ids_debug.py index 8d66ea5d5..d7f9ecbca 100755 --- a/test_regress/t/t_protect_ids_debug.py +++ b/test_regress/t/t_protect_ids_debug.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_protect_ids_key.py b/test_regress/t/t_protect_ids_key.py index 3cf278fdf..09316d28c 100755 --- a/test_regress/t/t_protect_ids_key.py +++ b/test_regress/t/t_protect_ids_key.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_public_clk.cpp b/test_regress/t/t_public_clk.cpp index 3a76d1d7c..eafc9ef8e 100644 --- a/test_regress/t/t_public_clk.cpp +++ b/test_regress/t/t_public_clk.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Todd Strader // SPDX-License-Identifier: CC0-1.0 // Generated header diff --git a/test_regress/t/t_public_clk.py b/test_regress/t/t_public_clk.py index f37ad07c8..b6662862a 100755 --- a/test_regress/t/t_public_clk.py +++ b/test_regress/t/t_public_clk.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_public_clk.v b/test_regress/t/t_public_clk.v index b5f123f35..bef8056e0 100644 --- a/test_regress/t/t_public_clk.v +++ b/test_regress/t/t_public_clk.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: public clock signal // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Todd Strader +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Todd Strader // SPDX-License-Identifier: CC0-1.0 `ifdef VERILATOR diff --git a/test_regress/t/t_public_seq.cpp b/test_regress/t/t_public_seq.cpp index beda4a7e3..6c5b1761e 100644 --- a/test_regress/t/t_public_seq.cpp +++ b/test_regress/t/t_public_seq.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Todd Strader // SPDX-License-Identifier: CC0-1.0 // Generated header diff --git a/test_regress/t/t_public_seq.py b/test_regress/t/t_public_seq.py index f37ad07c8..b6662862a 100755 --- a/test_regress/t/t_public_seq.py +++ b/test_regress/t/t_public_seq.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_public_seq.v b/test_regress/t/t_public_seq.v index a796e15c2..ce55d349a 100644 --- a/test_regress/t/t_public_seq.v +++ b/test_regress/t/t_public_seq.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: public clock signal // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Todd Strader +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Todd Strader // SPDX-License-Identifier: CC0-1.0 `ifdef VERILATOR diff --git a/test_regress/t/t_public_unpacked_port.py b/test_regress/t/t_public_unpacked_port.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_public_unpacked_port.py +++ b/test_regress/t/t_public_unpacked_port.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_public_unpacked_port.v b/test_regress/t/t_public_unpacked_port.v index 6cdcb6deb..2384f3a4f 100644 --- a/test_regress/t/t_public_unpacked_port.v +++ b/test_regress/t/t_public_unpacked_port.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Todd Strader // SPDX-License-Identifier: CC0-1.0 module sub ( diff --git a/test_regress/t/t_queue.py b/test_regress/t/t_queue.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue.py +++ b/test_regress/t/t_queue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue.v b/test_regress/t/t_queue.v index e54cda217..3cbf98fc4 100644 --- a/test_regress/t/t_queue.v +++ b/test_regress/t/t_queue.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_queue_arg.py b/test_regress/t/t_queue_arg.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_queue_arg.py +++ b/test_regress/t/t_queue_arg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_arg.v b/test_regress/t/t_queue_arg.v index e6e3a9be2..25bd909e8 100644 --- a/test_regress/t/t_queue_arg.v +++ b/test_regress/t/t_queue_arg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_queue_assignment.py b/test_regress/t/t_queue_assignment.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_assignment.py +++ b/test_regress/t/t_queue_assignment.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_assignment.v b/test_regress/t/t_queue_assignment.v index 80f52ca52..cc9bd1c42 100644 --- a/test_regress/t/t_queue_assignment.v +++ b/test_regress/t/t_queue_assignment.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 module t_queue_assignment; diff --git a/test_regress/t/t_queue_back.py b/test_regress/t/t_queue_back.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_back.py +++ b/test_regress/t/t_queue_back.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_back.v b/test_regress/t/t_queue_back.v index 48e60ae22..cb4036361 100644 --- a/test_regress/t/t_queue_back.v +++ b/test_regress/t/t_queue_back.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_queue_bounded.py b/test_regress/t/t_queue_bounded.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_bounded.py +++ b/test_regress/t/t_queue_bounded.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_bounded.v b/test_regress/t/t_queue_bounded.v index 1b1241ec6..004fefb78 100644 --- a/test_regress/t/t_queue_bounded.v +++ b/test_regress/t/t_queue_bounded.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_queue_class.py b/test_regress/t/t_queue_class.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_class.py +++ b/test_regress/t/t_queue_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_class.v b/test_regress/t/t_queue_class.v index efacb958f..ccd721d5e 100644 --- a/test_regress/t/t_queue_class.v +++ b/test_regress/t/t_queue_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_queue_compare.py b/test_regress/t/t_queue_compare.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_compare.py +++ b/test_regress/t/t_queue_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_compare.v b/test_regress/t/t_queue_compare.v index 991a3659a..eeaa1ddfa 100644 --- a/test_regress/t/t_queue_compare.v +++ b/test_regress/t/t_queue_compare.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Check == and != operations performed on queues // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Ilya Barkov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Ilya Barkov // SPDX-License-Identifier: CC0-1.0 `define stop $stop @@ -42,8 +42,8 @@ module t; end begin // classes - Cls a = new; - Cls b = new; + automatic Cls a = new; + automatic Cls b = new; Cls q1[$]; Cls q2[$]; q1.push_back(a); diff --git a/test_regress/t/t_queue_concat_assign.py b/test_regress/t/t_queue_concat_assign.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_concat_assign.py +++ b/test_regress/t/t_queue_concat_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_concat_assign.v b/test_regress/t/t_queue_concat_assign.v index 4422f6164..f6fcc8114 100644 --- a/test_regress/t/t_queue_concat_assign.v +++ b/test_regress/t/t_queue_concat_assign.v @@ -1,17 +1,17 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; initial begin - bit q1[$] = {1'b1}; + automatic bit q1[$] = {1'b1}; bit q2[$]; bit q3[$]; - bit [1:0] d1[$] = {2'b10}; + automatic bit [1:0] d1[$] = {2'b10}; bit [1:0] d2[$]; bit [1:0] d3[$]; diff --git a/test_regress/t/t_queue_empty_bad.py b/test_regress/t/t_queue_empty_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_queue_empty_bad.py +++ b/test_regress/t/t_queue_empty_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_empty_bad.v b/test_regress/t/t_queue_empty_bad.v index a92590a67..f0a356582 100644 --- a/test_regress/t/t_queue_empty_bad.v +++ b/test_regress/t/t_queue_empty_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_queue_empty_pin.py b/test_regress/t/t_queue_empty_pin.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_empty_pin.py +++ b/test_regress/t/t_queue_empty_pin.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_empty_pin.v b/test_regress/t/t_queue_empty_pin.v index 4d7f97e7d..db9c04f0f 100644 --- a/test_regress/t/t_queue_empty_pin.v +++ b/test_regress/t/t_queue_empty_pin.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_queue_init.py b/test_regress/t/t_queue_init.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_init.py +++ b/test_regress/t/t_queue_init.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_init.v b/test_regress/t/t_queue_init.v index 3efd86bcf..b47b674f3 100644 --- a/test_regress/t/t_queue_init.v +++ b/test_regress/t/t_queue_init.v @@ -1,36 +1,52 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - int a1[$] = '{12, 13}; - int a2[$] = {14, 15}; - int a3[$] = '{16}; - int a4[$] = {17}; + int a1[$] = '{12, 13}; + int a2[$] = {14, 15}; + int a3[$] = '{16}; + int a4[$] = {17}; - initial begin - `checkh(a1.size, 2); - `checkh(a1[0], 12); - `checkh(a1[1], 13); + int src[3], dest1[], dest2[]; - `checkh(a2.size, 2); - `checkh(a2[0], 14); - `checkh(a2[1], 15); + initial begin + `checkd(a1.size, 2); + `checkd(a1[0], 12); + `checkd(a1[1], 13); - `checkh(a3.size, 1); - `checkh(a3[0], 16); + `checkd(a2.size, 2); + `checkd(a2[0], 14); + `checkd(a2[1], 15); - `checkh(a4.size, 1); - `checkh(a4[0], 17); + `checkd(a3.size, 1); + `checkd(a3[0], 16); - $write("*-* All Finished *-*\n"); - $finish; - end + `checkd(a4.size, 1); + `checkd(a4[0], 17); + + src = '{2, 3, 4}; + dest1 = new[2] (src); + `checkd(dest1.size, 2); // {2, 3} + `checkd(dest1[0], 2); + `checkd(dest1[1], 3); + dest2 = new[4] (src); + `checkd(dest2.size, 4); // {2, 3, 4, 0}. + `checkd(dest2[0], 2); + `checkd(dest2[1], 3); + `checkd(dest2[2], 4); + `checkd(dest2[3], 0); + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_queue_insert_at_end.py b/test_regress/t/t_queue_insert_at_end.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_insert_at_end.py +++ b/test_regress/t/t_queue_insert_at_end.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_insert_at_end.v b/test_regress/t/t_queue_insert_at_end.v index 6ed3c006f..9e21d4264 100644 --- a/test_regress/t/t_queue_insert_at_end.v +++ b/test_regress/t/t_queue_insert_at_end.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t(); diff --git a/test_regress/t/t_queue_method.py b/test_regress/t/t_queue_method.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_method.py +++ b/test_regress/t/t_queue_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_method.v b/test_regress/t/t_queue_method.v index fb98bb5a7..ae59cfaa0 100644 --- a/test_regress/t/t_queue_method.v +++ b/test_regress/t/t_queue_method.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_queue_method2_bad.py b/test_regress/t/t_queue_method2_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_queue_method2_bad.py +++ b/test_regress/t/t_queue_method2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_method2_bad.v b/test_regress/t/t_queue_method2_bad.v index 3b0b51087..b664a5033 100644 --- a/test_regress/t/t_queue_method2_bad.v +++ b/test_regress/t/t_queue_method2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_queue_method3_bad.py b/test_regress/t/t_queue_method3_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_queue_method3_bad.py +++ b/test_regress/t/t_queue_method3_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_method3_bad.v b/test_regress/t/t_queue_method3_bad.v index cb68fd7e2..d173f0ce8 100644 --- a/test_regress/t/t_queue_method3_bad.v +++ b/test_regress/t/t_queue_method3_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_queue_method_bad.py b/test_regress/t/t_queue_method_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_queue_method_bad.py +++ b/test_regress/t/t_queue_method_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_method_bad.v b/test_regress/t/t_queue_method_bad.v index c57d4e06c..f441ec850 100644 --- a/test_regress/t/t_queue_method_bad.v +++ b/test_regress/t/t_queue_method_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_queue_output_func.py b/test_regress/t/t_queue_output_func.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_output_func.py +++ b/test_regress/t/t_queue_output_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_output_func.v b/test_regress/t/t_queue_output_func.v index e873e163c..b571b5aea 100644 --- a/test_regress/t/t_queue_output_func.v +++ b/test_regress/t/t_queue_output_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_queue_persistence.v b/test_regress/t/t_queue_persistence.v index 46f5f397c..f6ac3698d 100644 --- a/test_regress/t/t_queue_persistence.v +++ b/test_regress/t/t_queue_persistence.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_queue_persistence_inl.py b/test_regress/t/t_queue_persistence_inl.py index 07551a9f2..48b9003cb 100755 --- a/test_regress/t/t_queue_persistence_inl.py +++ b/test_regress/t/t_queue_persistence_inl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_persistence_noinl.py b/test_regress/t/t_queue_persistence_noinl.py index 5367cb861..a8859ab7b 100755 --- a/test_regress/t/t_queue_persistence_noinl.py +++ b/test_regress/t/t_queue_persistence_noinl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_pushpop.py b/test_regress/t/t_queue_pushpop.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_pushpop.py +++ b/test_regress/t/t_queue_pushpop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_pushpop.v b/test_regress/t/t_queue_pushpop.v index 94992c471..be21ae97c 100644 --- a/test_regress/t/t_queue_pushpop.v +++ b/test_regress/t/t_queue_pushpop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_queue_slice.py b/test_regress/t/t_queue_slice.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_slice.py +++ b/test_regress/t/t_queue_slice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_slice.v b/test_regress/t/t_queue_slice.v index 6fa42a402..925dd6122 100644 --- a/test_regress/t/t_queue_slice.v +++ b/test_regress/t/t_queue_slice.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop @@ -77,7 +77,7 @@ module t; `checkp(q, "'{\"a\", \"b\", \"a\", \"b\"}"); begin - string ai[$] = '{ "Foo", "Bar" }; + static string ai[$] = '{ "Foo", "Bar" }; q = ai; // Copy i = q.size(); `checkh(i, 2); v = q.pop_front(); `checks(v, "Foo"); diff --git a/test_regress/t/t_queue_struct.py b/test_regress/t/t_queue_struct.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_struct.py +++ b/test_regress/t/t_queue_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_struct.v b/test_regress/t/t_queue_struct.v index cd8ca43e5..77969a1b0 100644 --- a/test_regress/t/t_queue_struct.v +++ b/test_regress/t/t_queue_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_queue_unknown_sel.py b/test_regress/t/t_queue_unknown_sel.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_queue_unknown_sel.py +++ b/test_regress/t/t_queue_unknown_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_unknown_sel.v b/test_regress/t/t_queue_unknown_sel.v index fa75b6c34..74c4033b7 100644 --- a/test_regress/t/t_queue_unknown_sel.v +++ b/test_regress/t/t_queue_unknown_sel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Alex Solomatnikov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 package z_pkg; diff --git a/test_regress/t/t_queue_unpacked.py b/test_regress/t/t_queue_unpacked.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_unpacked.py +++ b/test_regress/t/t_queue_unpacked.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_unpacked.v b/test_regress/t/t_queue_unpacked.v index ba8ffd2ee..7004050b5 100644 --- a/test_regress/t/t_queue_unpacked.v +++ b/test_regress/t/t_queue_unpacked.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_queue_var_slice.py b/test_regress/t/t_queue_var_slice.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_var_slice.py +++ b/test_regress/t/t_queue_var_slice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_var_slice.v b/test_regress/t/t_queue_var_slice.v index da4e24877..3e1501a39 100644 --- a/test_regress/t/t_queue_var_slice.v +++ b/test_regress/t/t_queue_var_slice.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_queue_void_ops.py b/test_regress/t/t_queue_void_ops.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_queue_void_ops.py +++ b/test_regress/t/t_queue_void_ops.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_queue_void_ops.v b/test_regress/t/t_queue_void_ops.v index b3363177c..309862e28 100644 --- a/test_regress/t/t_queue_void_ops.v +++ b/test_regress/t/t_queue_void_ops.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_rand_member_mode_deriv.py b/test_regress/t/t_rand_member_mode_deriv.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_rand_member_mode_deriv.py +++ b/test_regress/t/t_rand_member_mode_deriv.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_rand_member_mode_deriv.v b/test_regress/t/t_rand_member_mode_deriv.v index 00a4924ba..cb1376d2c 100644 --- a/test_regress/t/t_rand_member_mode_deriv.v +++ b/test_regress/t/t_rand_member_mode_deriv.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class RandomValue; @@ -24,7 +24,7 @@ endclass module t; Base b; initial begin - Foo d = new; + automatic Foo d = new; b = d; d.v.disable_val(); d.v.value = 11; diff --git a/test_regress/t/t_rand_stability_class.py b/test_regress/t/t_rand_stability_class.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_rand_stability_class.py +++ b/test_regress/t/t_rand_stability_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_rand_stability_class.v b/test_regress/t/t_rand_stability_class.v index f139994ae..35c6cdb9c 100644 --- a/test_regress/t/t_rand_stability_class.v +++ b/test_regress/t/t_rand_stability_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_rand_stability_process.py b/test_regress/t/t_rand_stability_process.py index 60ae366b2..4301f9380 100755 --- a/test_regress/t/t_rand_stability_process.py +++ b/test_regress/t/t_rand_stability_process.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_rand_stability_process.v b/test_regress/t/t_rand_stability_process.v index e635ad9ce..03ae6c579 100644 --- a/test_regress/t/t_rand_stability_process.v +++ b/test_regress/t/t_rand_stability_process.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Aleksander Kiryk. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Aleksander Kiryk // SPDX-License-Identifier: CC0-1.0 // This test checks if calls to get_randstate don't affect diff --git a/test_regress/t/t_randc.py b/test_regress/t/t_randc.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randc.py +++ b/test_regress/t/t_randc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randc.v b/test_regress/t/t_randc.v index 41011814f..409a30a95 100644 --- a/test_regress/t/t_randc.v +++ b/test_regress/t/t_randc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class ClsNarrow #(parameter int WIDTH); diff --git a/test_regress/t/t_randc_constraint.py b/test_regress/t/t_randc_constraint.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randc_constraint.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randc_constraint.v b/test_regress/t/t_randc_constraint.v new file mode 100644 index 000000000..3d5819d50 --- /dev/null +++ b/test_regress/t/t_randc_constraint.v @@ -0,0 +1,272 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// Test: randc variables with additional constraints limiting values +// IEEE 1800 Section 18.4.2: randc cyclic behavior over constrained domain + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); +// verilog_format: on + +class RandcRange; + randc bit [3:0] value; // 4-bit: unconstrained domain = 0-15 + + constraint c_range { + value >= 3; + value <= 10; + } + + function void test_cyclic; + automatic int count[16]; + automatic int domain_size = 8; // values 3..10 + automatic int randomize_result; + $display("Test randc with range constraint [3:10]"); + // Run 3 full cycles + for (int trial = 0; trial < 3; ++trial) begin + for (int i = 0; i < domain_size; ++i) begin + randomize_result = randomize(); + `checkd(randomize_result, 1); + `check_range(value, 3, 10); + ++count[value]; + end + end + // After 3 full cycles, each value in [3,10] should appear exactly 3 times + for (int v = 3; v <= 10; ++v) begin + `checkd(count[v], 3); + end + // Values outside [3,10] should never appear + for (int v = 0; v < 3; ++v) begin + `checkd(count[v], 0); + end + for (int v = 11; v < 16; ++v) begin + `checkd(count[v], 0); + end + endfunction +endclass + +class RandcSmall; + randc bit [1:0] val; // 4 possible values: 0,1,2,3 + constraint c_exclude {val != 0;} // 3 valid values: 1,2,3 + + function void test_cyclic; + automatic int count[4]; + automatic int domain_size = 3; + automatic int randomize_result; + $display("Test randc with exclude constraint (val != 0)"); + // Run 4 full cycles + for (int trial = 0; trial < 4; ++trial) begin + for (int i = 0; i < domain_size; ++i) begin + randomize_result = randomize(); + `checkd(randomize_result, 1); + `checkd(val == 0, 0); + ++count[val]; + end + end + // After 4 full cycles, each of 1,2,3 should appear exactly 4 times + `checkd(count[0], 0); + for (int v = 1; v <= 3; ++v) begin + `checkd(count[v], 4); + end + endfunction +endclass + +// Test 3: Inheritance - parent randc with constraint, child inherits +class RandcParent; + randc bit [2:0] code; // 8 values: 0-7 + constraint c_positive {code > 0;} // 7 valid values: 1-7 + + function void test_cyclic; + automatic int count[8]; + automatic int domain_size = 7; + automatic int randomize_result; + $display("Test randc parent with constraint (code > 0)"); + for (int trial = 0; trial < 3; ++trial) begin + for (int i = 0; i < domain_size; ++i) begin + randomize_result = randomize(); + `checkd(randomize_result, 1); + `checkd(code == 0, 0); + ++count[code]; + end + end + for (int v = 1; v <= 7; ++v) begin + `checkd(count[v], 3); + end + `checkd(count[0], 0); + endfunction +endclass + +class RandcChild extends RandcParent; + // Inherits randc code and c_positive constraint + constraint c_upper {code <= 5;} // Further restrict: 1-5 (5 values) + + function void test_cyclic; + automatic int count[8]; + automatic int domain_size = 5; + automatic int randomize_result; + $display("Test randc child with inherited + additional constraint (1 <= code <= 5)"); + for (int trial = 0; trial < 4; ++trial) begin + for (int i = 0; i < domain_size; ++i) begin + randomize_result = randomize(); + `checkd(randomize_result, 1); + `check_range(code, 1, 5); + ++count[code]; + end + end + for (int v = 1; v <= 5; ++v) begin + `checkd(count[v], 4); + end + for (int v = 6; v <= 7; ++v) begin + `checkd(count[v], 0); + end + endfunction +endclass + +// Test 5: constraint_mode() interaction +// Verifies randc cyclic behavior adapts when constraints are toggled at runtime. +// Note: randc cycles are continuous, not per-phase, so we verify constraint +// enforcement and that all valid values eventually appear rather than exact counts. +class RandcModeSwitch; + randc bit [1:0] x; // 4 values: 0-3 + constraint c_nonzero {x != 0;} // 3 valid values: 1,2,3 + + function void test_mode_switch; + automatic int randomize_result; + automatic bit seen_zero; + + // Phase 1: constraint ON -> x should never be 0, and all of {1,2,3} should appear + $display("Test constraint_mode: phase 1 (constraint ON)"); + begin + automatic bit seen[4] = '{0, 0, 0, 0}; + // Run 2 full cycles (6 calls) to ensure all constrained values appear + for (int i = 0; i < 6; ++i) begin + randomize_result = randomize(); + `checkd(randomize_result, 1); + `checkd(x == 0, 0); + seen[x] = 1; + end + for (int v = 1; v <= 3; ++v) begin + `checkd(seen[v], 1); + end + end + + // Phase 2: constraint OFF -> x=0 should eventually appear + $display("Test constraint_mode: phase 2 (constraint OFF)"); + c_nonzero.constraint_mode(0); + seen_zero = 0; + // Run enough calls (2 full cycles of 4 + margin) to see all values + for (int i = 0; i < 12; ++i) begin + randomize_result = randomize(); + `checkd(randomize_result, 1); + if (x == 0) seen_zero = 1; + end + `checkd(seen_zero, 1); + + // Phase 3: constraint back ON -> x should never be 0 again + $display("Test constraint_mode: phase 3 (constraint ON again)"); + c_nonzero.constraint_mode(1); + for (int i = 0; i < 9; ++i) begin + randomize_result = randomize(); + `checkd(randomize_result, 1); + `checkd(x == 0, 0); + end + endfunction +endclass + +// Test 6: Enum randc with constraint excluding some values +// Use a 2-bit enum where all bit values are valid enum members, +// so the solver domain matches the enum domain exactly. +class RandcEnumConstrained; + typedef enum bit [1:0] { + RED = 0, + GREEN = 1, + BLUE = 2, + WHITE = 3 + } color_t; + + randc color_t color; + constraint c_no_white {color != WHITE;} // 3 valid: RED, GREEN, BLUE + + function void test_cyclic; + automatic int count[4] = '{0, 0, 0, 0}; + automatic int domain_size = 3; + automatic int randomize_result; + $display("Test randc enum with constraint (exclude WHITE)"); + for (int trial = 0; trial < 4; ++trial) begin + for (int i = 0; i < domain_size; ++i) begin + randomize_result = randomize(); + `checkd(randomize_result, 1); + `checkd(color == WHITE, 0); + ++count[color]; + end + end + for (int v = 0; v <= 2; ++v) begin + `checkd(count[v], 4); + end + `checkd(count[3], 0); + endfunction +endclass + +// Test 7: Deep cyclic - full 4-bit range 0:15 (16 values, no constraint) +class RandcDeep; + randc bit [3:0] val; + + function void test_cyclic; + automatic int count[16]; + automatic int domain_size = 16; + automatic int randomize_result; + $display("Test randc deep cyclic [0:15] (16 values)"); + // Run 3 full cycles + for (int trial = 0; trial < 3; ++trial) begin + for (int i = 0; i < domain_size; ++i) begin + randomize_result = randomize(); + `checkd(randomize_result, 1); + ++count[val]; + end + end + // Each value 0..15 should appear exactly 3 times + for (int v = 0; v < 16; ++v) begin + `checkd(count[v], 3); + end + endfunction +endclass + +module t; + RandcRange rr; + RandcSmall rs; + RandcParent rp; + RandcChild rc; + RandcModeSwitch rms; + RandcEnumConstrained rec; + RandcDeep rd; + + initial begin + rr = new; + rr.test_cyclic(); + + rs = new; + rs.test_cyclic(); + + rp = new; + rp.test_cyclic(); + + rc = new; + rc.test_cyclic(); + + rms = new; + rms.test_mode_switch(); + + rec = new; + rec.test_cyclic(); + + rd = new; + rd.test_cyclic(); + + $write("*-* All Finished *-*\n"); + $finish(); + end +endmodule diff --git a/test_regress/t/t_randc_enum_constraint.py b/test_regress/t/t_randc_enum_constraint.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randc_enum_constraint.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randc_enum_constraint.v b/test_regress/t/t_randc_enum_constraint.v new file mode 100644 index 000000000..003142617 --- /dev/null +++ b/test_regress/t/t_randc_enum_constraint.v @@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +// Test that randc enum variables with user constraints only produce +// valid enum members (not arbitrary bitvector values). + +module t; + + typedef enum bit [2:0] { + RED = 0, + GREEN = 1, + BLUE = 2, + WHITE = 3, + BLACK = 4 + } color_t; + + class ColorClass; + randc color_t color; + constraint c_no_dark {color != BLACK;} + endclass + + // Test with all enum values allowed (no exclusion constraint) + class AllColorsClass; + randc color_t color; + constraint c_range {color <= WHITE;} + endclass + + initial begin + ColorClass c; + AllColorsClass ac; + int color_seen[5]; + int first_seq, all_same, this_seq; + + // Test 1: randc enum with exclusion constraint + // Values must be valid enum members (0-4) and not BLACK (4) + c = new; + repeat (40) begin + `checkd(c.randomize(), 1); + `checkd(c.color <= BLACK, 1); + `checkd(c.color == BLACK, 0); + end + + // Test 2: randc enum with range constraint - run multiple trials, + // verify only valid enum members produced and sequence varies + all_same = 1; + first_seq = 0; + for (int trial = 0; trial < 3; trial++) begin + ac = new; + this_seq = 0; + for (int j = 0; j < 4; j++) color_seen[j] = 0; + repeat (40) begin + `checkd(ac.randomize(), 1); + `checkd(ac.color <= WHITE, 1); + color_seen[ac.color] = 1; + end + // Record first 4 values for sequence comparison + repeat (4) begin + `checkd(ac.randomize(), 1); + this_seq = this_seq * 8 + int'(ac.color); + end + `checkd(color_seen[0], 1); + `checkd(color_seen[1], 1); + `checkd(color_seen[2], 1); + `checkd(color_seen[3], 1); + if (trial == 0) first_seq = this_seq; + else if (this_seq != first_seq) all_same = 0; + end + `checkd(all_same, 0); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_randc_extends.py b/test_regress/t/t_randc_extends.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_randc_extends.py +++ b/test_regress/t/t_randc_extends.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randc_extends.v b/test_regress/t/t_randc_extends.v index d86b46a7d..a9f4eddcc 100644 --- a/test_regress/t/t_randc_extends.v +++ b/test_regress/t/t_randc_extends.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; diff --git a/test_regress/t/t_randc_oversize_bad.py b/test_regress/t/t_randc_oversize_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_randc_oversize_bad.py +++ b/test_regress/t/t_randc_oversize_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randc_oversize_bad.v b/test_regress/t/t_randc_oversize_bad.v index 3b35d752c..63c8049f6 100644 --- a/test_regress/t/t_randc_oversize_bad.v +++ b/test_regress/t/t_randc_oversize_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_randcase.py b/test_regress/t/t_randcase.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randcase.py +++ b/test_regress/t/t_randcase.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randcase.v b/test_regress/t/t_randcase.v index 0840ef591..583827916 100644 --- a/test_regress/t/t_randcase.v +++ b/test_regress/t/t_randcase.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_randcase_bad.py b/test_regress/t/t_randcase_bad.py index 97abb660e..c03eaf086 100755 --- a/test_regress/t/t_randcase_bad.py +++ b/test_regress/t/t_randcase_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randcase_bad.v b/test_regress/t/t_randcase_bad.v index c40d63879..110b4d9eb 100644 --- a/test_regress/t/t_randcase_bad.v +++ b/test_regress/t/t_randcase_bad.v @@ -2,8 +2,8 @@ // // This tests issue #508, bit select of constant fails // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_randcase_fork.py b/test_regress/t/t_randcase_fork.py index ac142fe63..4caa0e109 100755 --- a/test_regress/t/t_randcase_fork.py +++ b/test_regress/t/t_randcase_fork.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randcase_fork.v b/test_regress/t/t_randcase_fork.v index 499a56273..a9ea217f1 100644 --- a/test_regress/t/t_randcase_fork.v +++ b/test_regress/t/t_randcase_fork.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module randcase_tb; diff --git a/test_regress/t/t_randomize.out b/test_regress/t/t_randomize.out index 136639289..1e9892a78 100644 --- a/test_regress/t/t_randomize.out +++ b/test_regress/t/t_randomize.out @@ -4,12 +4,4 @@ | ^~~~ ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. -%Warning-CONSTRAINTIGN: t/t_randomize.v:40:7: Constraint expression ignored (unsupported) - : ... note: In instance 't' - 40 | unique { array[0], array[1] }; - | ^~~~~~ -%Warning-CONSTRAINTIGN: t/t_randomize.v:43:23: Constraint expression ignored (imperfect distribution) - : ... note: In instance 't' - 43 | constraint order { solve length before header; } - | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize.py b/test_regress/t/t_randomize.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_randomize.py +++ b/test_regress/t/t_randomize.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize.v b/test_regress/t/t_randomize.v index d5a8ea97d..2c613ac94 100644 --- a/test_regress/t/t_randomize.v +++ b/test_regress/t/t_randomize.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Packet; @@ -56,8 +56,8 @@ module t; initial begin - int v; - bit if_4 = '0; + automatic int v; + automatic bit if_4 = '0; // TODO not testing constrained values v = p.randomize(); if (v != 1) $stop; diff --git a/test_regress/t/t_randomize_array.py b/test_regress/t/t_randomize_array.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_array.py +++ b/test_regress/t/t_randomize_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_array.v b/test_regress/t/t_randomize_array.v old mode 100755 new mode 100644 index f1a5abece..0d5af4374 --- a/test_regress/t/t_randomize_array.v +++ b/test_regress/t/t_randomize_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field) \ diff --git a/test_regress/t/t_randomize_array_elem_with.py b/test_regress/t/t_randomize_array_elem_with.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randomize_array_elem_with.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_array_elem_with.v b/test_regress/t/t_randomize_array_elem_with.v new file mode 100644 index 000000000..cae68681b --- /dev/null +++ b/test_regress/t/t_randomize_array_elem_with.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +class mbus_seq_item; + rand logic MREAD; +endclass + +module t; + initial begin + mbus_seq_item req_c[10]; + for (int i = 0; i < 10; i++) begin + req_c[i] = new; + + if (req_c[i].randomize() with {MREAD == 0;} == 0) begin + $stop; + end + if (req_c[i].MREAD != 0) begin + $stop; + end + + if (req_c[i].randomize() == 0) begin + $stop; + end + + req_c[i].srandom(42); + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_arraysel_membersel.py b/test_regress/t/t_randomize_arraysel_membersel.py new file mode 100755 index 000000000..8862c2c31 --- /dev/null +++ b/test_regress/t/t_randomize_arraysel_membersel.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_arraysel_membersel.v b/test_regress/t/t_randomize_arraysel_membersel.v new file mode 100644 index 000000000..845ccffd8 --- /dev/null +++ b/test_regress/t/t_randomize_arraysel_membersel.v @@ -0,0 +1,110 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +typedef struct {int x;} struct_t; + +class inner_class; + logic [3:0] c; + logic [3:0] d[2]; + logic [3:0] dyn[]; + struct_t s; +endclass + +class test_class; + logic [3:0] member[5]; + logic [3:0] member_2d[3][4]; + inner_class b; +endclass + +module t; + initial begin + automatic int x = 2; + test_class example; + example = new; + example.b = new; + example.b.dyn = new[3]; + + // Simple array element access + repeat (5) begin + if (std::randomize(example.member[1]) with {example.member[1] inside {[0 : 3]};} == 0) $stop; + if (example.member[1] > 3) $stop; + end + + // Different array indices + repeat (5) begin + if (std::randomize(example.member[0]) with {example.member[0] inside {[5 : 7]};} == 0) $stop; + if (example.member[0] < 5 || example.member[0] > 7) $stop; + end + + // Last element + repeat (5) begin + if (std::randomize(example.member[4]) with {example.member[4] inside {[10 : 15]};} == 0) + $stop; + if (example.member[4] < 10 || example.member[4] > 15) $stop; + end + + // 2D array access + repeat (5) begin + if (std::randomize( + example.member_2d[1][2] + ) with { + example.member_2d[1][2] inside {[8 : 12]}; + } == 0) + $stop; + if (example.member_2d[1][2] < 8 || example.member_2d[1][2] > 12) $stop; + end + + // 2D array different indices + repeat (5) begin + if (std::randomize( + example.member_2d[0][0] + ) with { + example.member_2d[0][0] inside {[1 : 4]}; + } == 0) + $stop; + if (example.member_2d[0][0] < 1 || example.member_2d[0][0] > 4) $stop; + end + + // Nested object: obj.b.c + repeat (5) begin + if (std::randomize(example.b.c) with {example.b.c inside {[5 : 9]};} == 0) $stop; + if (example.b.c < 5 || example.b.c > 9) $stop; + end + + // Nested object with array: obj.b.d[0] + repeat (5) begin + if (std::randomize(example.b.d[0]) with {example.b.d[0] inside {[11 : 14]};} == 0) $stop; + if (example.b.d[0] < 11 || example.b.d[0] > 14) $stop; + end + + // Nested object with array: obj.b.d[1] (different index) + repeat (5) begin + if (std::randomize(example.b.d[1]) with {example.b.d[1] inside {[2 : 6]};} == 0) $stop; + if (example.b.d[1] < 2 || example.b.d[1] > 6) $stop; + end + + // Nested object with dynamic array: obj.b.dyn[x] + repeat (5) begin + if (std::randomize(example.b.dyn[x]) with {example.b.dyn[x] inside {[1 : 3]};} == 0) $stop; + if (example.b.dyn[x] < 1 || example.b.dyn[x] > 3) $stop; + end + + // Nested object with struct: obj.b.s.x + repeat (5) begin + if (std::randomize(example.b.s.x) with {example.b.s.x inside {[7 : 9]};} == 0) $stop; + if (example.b.s.x < 7 || example.b.s.x > 9) $stop; + end + + // Inline randomization of object with array + repeat (5) begin + if (example.randomize(b) with {b.d[1] inside {[2 : 6]};} == 0) $stop; + if (example.b.d[1] < 2 || example.b.d[1] > 6) $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_assoc_size.py b/test_regress/t/t_randomize_assoc_size.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randomize_assoc_size.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_assoc_size.v b/test_regress/t/t_randomize_assoc_size.v new file mode 100644 index 000000000..cb10eb7cf --- /dev/null +++ b/test_regress/t/t_randomize_assoc_size.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t; + + // String-key associative array with size constraint + class StringKeyTest; + rand int data[string]; + constraint c_size {data.size() == 3;} + endclass + + // Int-key associative array with size constraint + class IntKeyTest; + rand bit [7:0] values[int]; + constraint c_size {values.size() == 2;} + endclass + + initial begin + automatic StringKeyTest str_obj = new(); + automatic IntKeyTest int_obj = new(); + automatic int rand_ok; + + // String-key: pre-populate 3 entries to match constraint + str_obj.data["x"] = 0; + str_obj.data["y"] = 0; + str_obj.data["z"] = 0; + + rand_ok = str_obj.randomize(); + `checkd(rand_ok, 1); + `checkd(str_obj.data.size(), 3); + + // Int-key: pre-populate 2 entries to match constraint + int_obj.values[10] = 0; + int_obj.values[20] = 0; + + rand_ok = int_obj.randomize(); + `checkd(rand_ok, 1); + `checkd(int_obj.values.size(), 2); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_randomize_bbox.py b/test_regress/t/t_randomize_bbox.py index 706273143..a727c0305 100755 --- a/test_regress/t/t_randomize_bbox.py +++ b/test_regress/t/t_randomize_bbox.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_complex.py b/test_regress/t/t_randomize_complex.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_randomize_complex.py +++ b/test_regress/t/t_randomize_complex.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_complex.v b/test_regress/t/t_randomize_complex.v index f6c5afa3e..9a0debf0f 100644 --- a/test_regress/t/t_randomize_complex.v +++ b/test_regress/t/t_randomize_complex.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class SubClass; @@ -34,8 +34,8 @@ endclass module t; initial begin - WeNeedToGoDeeper cl_inst = new; - MyClass cl_inst2 = new; + automatic WeNeedToGoDeeper cl_inst = new; + automatic MyClass cl_inst2 = new; repeat (10) begin if (cl_inst.sc_inst.sc_inst1.sc_inst2.randomize() with {field inside {1, 2, 3};} == 0) begin $stop; diff --git a/test_regress/t/t_randomize_complex_arrays.py b/test_regress/t/t_randomize_complex_arrays.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_complex_arrays.py +++ b/test_regress/t/t_randomize_complex_arrays.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_complex_arrays.v b/test_regress/t/t_randomize_complex_arrays.v index f7963ba5a..e266a895f 100644 --- a/test_regress/t/t_randomize_complex_arrays.v +++ b/test_regress/t/t_randomize_complex_arrays.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class SubClass; diff --git a/test_regress/t/t_randomize_complex_associative_arrays.py b/test_regress/t/t_randomize_complex_associative_arrays.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_complex_associative_arrays.py +++ b/test_regress/t/t_randomize_complex_associative_arrays.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_complex_associative_arrays.v b/test_regress/t/t_randomize_complex_associative_arrays.v index fc139db88..c5050416a 100644 --- a/test_regress/t/t_randomize_complex_associative_arrays.v +++ b/test_regress/t/t_randomize_complex_associative_arrays.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class SubClass; diff --git a/test_regress/t/t_randomize_complex_dynamic_arrays.py b/test_regress/t/t_randomize_complex_dynamic_arrays.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_complex_dynamic_arrays.py +++ b/test_regress/t/t_randomize_complex_dynamic_arrays.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_complex_dynamic_arrays.v b/test_regress/t/t_randomize_complex_dynamic_arrays.v index 308adf6c1..2db53ab2c 100644 --- a/test_regress/t/t_randomize_complex_dynamic_arrays.v +++ b/test_regress/t/t_randomize_complex_dynamic_arrays.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class SubClass; diff --git a/test_regress/t/t_randomize_complex_member_bad.py b/test_regress/t/t_randomize_complex_member_bad.py index a551e844d..75ee96830 100755 --- a/test_regress/t/t_randomize_complex_member_bad.py +++ b/test_regress/t/t_randomize_complex_member_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_complex_member_bad.v b/test_regress/t/t_randomize_complex_member_bad.v index 3673770c0..459c8f3e6 100644 --- a/test_regress/t/t_randomize_complex_member_bad.v +++ b/test_regress/t/t_randomize_complex_member_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class SubClass; diff --git a/test_regress/t/t_randomize_complex_queue.py b/test_regress/t/t_randomize_complex_queue.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_complex_queue.py +++ b/test_regress/t/t_randomize_complex_queue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_complex_queue.v b/test_regress/t/t_randomize_complex_queue.v index e1d37155d..9c3dc9e84 100644 --- a/test_regress/t/t_randomize_complex_queue.v +++ b/test_regress/t/t_randomize_complex_queue.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class SubClass; @@ -35,10 +35,10 @@ endclass module t; initial begin - WeNeedToGoDeeper inst = new; - MyClass inst2 = new; - WeNeedToGoDeeper cl_inst[$] = {inst}; - MyClass cl_inst2[$] = {inst2}; + automatic WeNeedToGoDeeper inst = new; + automatic MyClass inst2 = new; + automatic WeNeedToGoDeeper cl_inst[$] = {inst}; + automatic MyClass cl_inst2[$] = {inst2}; repeat (10) begin if (cl_inst[0].sc_inst.sc_inst1.sc_inst2[0].randomize() with { field inside {1, 2, 3}; diff --git a/test_regress/t/t_randomize_complex_typedef.py b/test_regress/t/t_randomize_complex_typedef.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_randomize_complex_typedef.py +++ b/test_regress/t/t_randomize_complex_typedef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_complex_typedef.v b/test_regress/t/t_randomize_complex_typedef.v index e9baa725c..eafd56c31 100644 --- a/test_regress/t/t_randomize_complex_typedef.v +++ b/test_regress/t/t_randomize_complex_typedef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class SubClass; diff --git a/test_regress/t/t_randomize_from_randomized_class.py b/test_regress/t/t_randomize_from_randomized_class.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_randomize_from_randomized_class.py +++ b/test_regress/t/t_randomize_from_randomized_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_from_randomized_class.v b/test_regress/t/t_randomize_from_randomized_class.v index 2080bf13f..46a6b8b7a 100644 --- a/test_regress/t/t_randomize_from_randomized_class.v +++ b/test_regress/t/t_randomize_from_randomized_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class A; @@ -22,7 +22,7 @@ endclass module t; initial begin - B b = new; + automatic B b = new; b.r(); if (b.a.j != 7) $stop; $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_randomize_inline_funclocal.py b/test_regress/t/t_randomize_inline_funclocal.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_randomize_inline_funclocal.py +++ b/test_regress/t/t_randomize_inline_funclocal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_inline_funclocal.v b/test_regress/t/t_randomize_inline_funclocal.v index 12940c650..46e93a93f 100644 --- a/test_regress/t/t_randomize_inline_funclocal.v +++ b/test_regress/t/t_randomize_inline_funclocal.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_randomize_inline_var_ctl.py b/test_regress/t/t_randomize_inline_var_ctl.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_inline_var_ctl.py +++ b/test_regress/t/t_randomize_inline_var_ctl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_inline_var_ctl.v b/test_regress/t/t_randomize_inline_var_ctl.v index 9bcc55e9f..3a5cf0a72 100644 --- a/test_regress/t/t_randomize_inline_var_ctl.v +++ b/test_regress/t/t_randomize_inline_var_ctl.v @@ -1,156 +1,156 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; - rand int zero; - int two; + rand int zero; + int two; endclass class Bar extends Foo; - rand int one; - static int three; + rand int one; + static int three; - function void test; - logic[1:0] ok = '0; - zero = 100; - one = 200; - two = 300; - three = 400; - for (int i = 0; i < 20; i++) begin - void'(randomize(one)); - if (zero != 100) $stop; - if (one != 200) ok[0] = 1; - if (two != 300) $stop; - if (three != 400) $stop; - end - if (!ok[0]) $stop; - ok = '0; + function void test; + logic [1:0] ok = '0; + zero = 100; + one = 200; + two = 300; + three = 400; + for (int i = 0; i < 20; i++) begin + void'(randomize(one)); + if (zero != 100) $stop; + if (one != 200) ok[0] = 1; + if (two != 300) $stop; + if (three != 400) $stop; + end + if (!ok[0]) $stop; + ok = '0; - if (zero.rand_mode() != 1) $stop; - if (one.rand_mode() != 1) $stop; - zero = 500; - one = 600; - two = 700; - three = 800; - one.rand_mode(0); - for (int i = 0; i < 20; i++) begin - void'(randomize(one, two)); - if (zero != 500) $stop; - if (one != 600) ok[0] = 1; - if (two != 700) ok[1] = 1; - if (three != 800) $stop; - end - if (one.rand_mode() != 0) $stop; - one.rand_mode(1); - if (ok != 'b11) $stop; - endfunction + if (zero.rand_mode() != 1) $stop; + if (one.rand_mode() != 1) $stop; + zero = 500; + one = 600; + two = 700; + three = 800; + one.rand_mode(0); + for (int i = 0; i < 20; i++) begin + void'(randomize(one, two)); + if (zero != 500) $stop; + if (one != 600) ok[0] = 1; + if (two != 700) ok[1] = 1; + if (three != 800) $stop; + end + if (one.rand_mode() != 0) $stop; + one.rand_mode(1); + if (ok != 'b11) $stop; + endfunction endclass class Baz; - int four; - Bar bar; + int four; + Bar bar; - function new; - bar = new; - endfunction + function new; + bar = new; + endfunction endclass class Qux; - Baz baz; + Baz baz; - function new; - baz = new; - endfunction + function new; + baz = new; + endfunction endclass class Boo extends Bar; - rand int five; + rand int five; endclass module t; - initial begin - Boo boo = new; - Bar bar = boo; - Qux qux = new; - logic[2:0] ok = '0; + initial begin + automatic Boo boo = new; + automatic Bar bar = boo; + automatic Qux qux = new; + automatic logic [2:0] ok = '0; - bar.test; + bar.test; - bar.zero = 1000; - bar.one = 2000; - bar.two = 3000; - bar.three = 4000; - boo.five = 999999; - for (int i = 0; i < 20; i++) begin - int res = bar.randomize(two); - if (boo.five != 999999) $stop; - end + bar.zero = 1000; + bar.one = 2000; + bar.two = 3000; + bar.three = 4000; + boo.five = 999999; + for (int i = 0; i < 20; i++) begin + automatic int res = bar.randomize(two); + if (boo.five != 999999) $stop; + end - bar.zero = 1000; - bar.one = 2000; - bar.two = 3000; - bar.three = 4000; - boo.five = 999999; - for (int i = 0; i < 20; i++) begin - int res = bar.randomize(two) with { two > 3000 && two < 4000; }; - if (bar.zero != 1000) $stop; - if (bar.one != 2000) $stop; - if (!(bar.two > 3000 && bar.two < 4000)) $stop; - if (bar.three != 4000) $stop; - if (boo.five != 999999) $stop; - end + bar.zero = 1000; + bar.one = 2000; + bar.two = 3000; + bar.three = 4000; + boo.five = 999999; + for (int i = 0; i < 20; i++) begin + automatic int res = bar.randomize(two) with {two > 3000 && two < 4000;}; + if (bar.zero != 1000) $stop; + if (bar.one != 2000) $stop; + if (!(bar.two > 3000 && bar.two < 4000)) $stop; + if (bar.three != 4000) $stop; + if (boo.five != 999999) $stop; + end - qux.baz.bar.zero = 5000; - qux.baz.bar.one = 6000; - qux.baz.bar.two = 7000; - qux.baz.bar.three = 8000; - qux.baz.four = 9000; - for (int i = 0; i < 20; i++) begin - void'(qux.randomize(baz)); - if (qux.baz.bar.zero != 5000) $stop; - if (qux.baz.bar.one != 6000) $stop; - if (qux.baz.bar.two != 7000) $stop; - if (qux.baz.bar.three != 8000) $stop; - if (qux.baz.four != 9000) $stop; - end - for (int i = 0; i < 20; i++) begin - void'(qux.randomize(baz.bar)); - if (qux.baz.bar.zero != 5000) ok[0] = 1; - if (qux.baz.bar.one != 6000) ok[1] = 1; - if (qux.baz.bar.two != 7000) $stop; - if (qux.baz.bar.three != 8000) $stop; - if (qux.baz.four != 9000) $stop; - end - if (!ok[0]) $stop; - if (!ok[1]) $stop; - ok = '0; - qux.baz.bar.zero = 10000; - qux.baz.bar.one = 20000; - for (int i = 0; i < 20; i++) begin - void'(qux.randomize(baz.four)); - if (qux.baz.bar.zero != 10000) $stop; - if (qux.baz.bar.one != 20000) $stop; - if (qux.baz.bar.two != 7000) $stop; - if (qux.baz.bar.three != 8000) $stop; - if (qux.baz.four != 9000) ok[0] = 1; - end - if (!ok[0]) $stop; - ok = '0; - qux.baz.four = 30000; - for (int i = 0; i < 20; i++) begin - void'(qux.randomize(baz.bar, qux.baz.bar.one, baz.four)); - if (qux.baz.bar.zero != 10000) ok[0] = 1; - if (qux.baz.bar.one != 20000) ok[1] = 1; - if (qux.baz.bar.two != 7000) $stop; - if (qux.baz.bar.three != 8000) $stop; - if (qux.baz.four != 30000) ok[2] = 1; - end - if (ok != 'b111) $stop; + qux.baz.bar.zero = 5000; + qux.baz.bar.one = 6000; + qux.baz.bar.two = 7000; + qux.baz.bar.three = 8000; + qux.baz.four = 9000; + for (int i = 0; i < 20; i++) begin + void'(qux.randomize(baz)); + if (qux.baz.bar.zero != 5000) $stop; + if (qux.baz.bar.one != 6000) $stop; + if (qux.baz.bar.two != 7000) $stop; + if (qux.baz.bar.three != 8000) $stop; + if (qux.baz.four != 9000) $stop; + end + for (int i = 0; i < 20; i++) begin + void'(qux.randomize(baz.bar)); + if (qux.baz.bar.zero != 5000) ok[0] = 1; + if (qux.baz.bar.one != 6000) ok[1] = 1; + if (qux.baz.bar.two != 7000) $stop; + if (qux.baz.bar.three != 8000) $stop; + if (qux.baz.four != 9000) $stop; + end + if (!ok[0]) $stop; + if (!ok[1]) $stop; + ok = '0; + qux.baz.bar.zero = 10000; + qux.baz.bar.one = 20000; + for (int i = 0; i < 20; i++) begin + void'(qux.randomize(baz.four)); + if (qux.baz.bar.zero != 10000) $stop; + if (qux.baz.bar.one != 20000) $stop; + if (qux.baz.bar.two != 7000) $stop; + if (qux.baz.bar.three != 8000) $stop; + if (qux.baz.four != 9000) ok[0] = 1; + end + if (!ok[0]) $stop; + ok = '0; + qux.baz.four = 30000; + for (int i = 0; i < 20; i++) begin + void'(qux.randomize(baz.bar, qux.baz.bar.one, baz.four)); + if (qux.baz.bar.zero != 10000) ok[0] = 1; + if (qux.baz.bar.one != 20000) ok[1] = 1; + if (qux.baz.bar.two != 7000) $stop; + if (qux.baz.bar.three != 8000) $stop; + if (qux.baz.four != 30000) ok[2] = 1; + end + if (ok != 'b111) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_randomize_inline_var_ctl_bad.py b/test_regress/t/t_randomize_inline_var_ctl_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_randomize_inline_var_ctl_bad.py +++ b/test_regress/t/t_randomize_inline_var_ctl_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_inline_var_ctl_bad.v b/test_regress/t/t_randomize_inline_var_ctl_bad.v index 5d5f2120f..6b806e823 100644 --- a/test_regress/t/t_randomize_inline_var_ctl_bad.v +++ b/test_regress/t/t_randomize_inline_var_ctl_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -19,10 +19,10 @@ endclass module t; initial begin - Foo foo = new; - Foo qux = new; - Bar bar = new; - int x; + automatic Foo foo = new; + automatic Foo qux = new; + automatic Bar bar = new; + automatic int x; void'(foo.randomize(x, foo.x, null, qux.x, bar.y, 0 + 1, x ** 2)); end endmodule diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py index 6038b562c..262e7ddcc 100755 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.v b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.v index 4f01c058c..96224aac2 100644 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_1.v +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -15,8 +15,8 @@ endclass module t; initial begin - Foo foo = Foo::get(); - Foo foos[] = new[1]; + automatic Foo foo = Foo::get(); + automatic Foo foos[] = new[1]; void'(foo.randomize(Foo::get().x)); void'(foo.randomize(foos[0].x)); void'(foo.randomize(null)); diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py index 6038b562c..262e7ddcc 100755 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.v b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.v index ed5fbe5a5..c8f44779a 100644 --- a/test_regress/t/t_randomize_inline_var_ctl_unsup_2.v +++ b/test_regress/t/t_randomize_inline_var_ctl_unsup_2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_randomize_local_param.py b/test_regress/t/t_randomize_local_param.py index cca4c9e73..d6d35e7fd 100755 --- a/test_regress/t/t_randomize_local_param.py +++ b/test_regress/t/t_randomize_local_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_local_param.v b/test_regress/t/t_randomize_local_param.v index 6735d2cae..fd197cbf3 100644 --- a/test_regress/t/t_randomize_local_param.v +++ b/test_regress/t/t_randomize_local_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Pkg; diff --git a/test_regress/t/t_randomize_member_select.py b/test_regress/t/t_randomize_member_select.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_randomize_member_select.py +++ b/test_regress/t/t_randomize_member_select.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_member_select.v b/test_regress/t/t_randomize_member_select.v index d0bd36df5..cd8b3465e 100644 --- a/test_regress/t/t_randomize_member_select.v +++ b/test_regress/t/t_randomize_member_select.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class B; diff --git a/test_regress/t/t_randomize_method.py b/test_regress/t/t_randomize_method.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randomize_method.py +++ b/test_regress/t/t_randomize_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method.v b/test_regress/t/t_randomize_method.v index 5e7ee09b7..d5fa914c0 100644 --- a/test_regress/t/t_randomize_method.v +++ b/test_regress/t/t_randomize_method.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ void'(cl.randomize()); \ prev_result = longint'(field); \ repeat(9) begin \ diff --git a/test_regress/t/t_randomize_method_bad.py b/test_regress/t/t_randomize_method_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_randomize_method_bad.py +++ b/test_regress/t/t_randomize_method_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method_bad.v b/test_regress/t/t_randomize_method_bad.v index f7112eb3e..45c3bb29e 100644 --- a/test_regress/t/t_randomize_method_bad.v +++ b/test_regress/t/t_randomize_method_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls1; diff --git a/test_regress/t/t_randomize_method_complex_bad.py b/test_regress/t/t_randomize_method_complex_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_randomize_method_complex_bad.py +++ b/test_regress/t/t_randomize_method_complex_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method_complex_bad.v b/test_regress/t/t_randomize_method_complex_bad.v index e2e360204..9af38bbd1 100644 --- a/test_regress/t/t_randomize_method_complex_bad.v +++ b/test_regress/t/t_randomize_method_complex_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_randomize_method_constraints.py b/test_regress/t/t_randomize_method_constraints.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_method_constraints.py +++ b/test_regress/t/t_randomize_method_constraints.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method_constraints.v b/test_regress/t/t_randomize_method_constraints.v index 482f6ced8..f61d009a1 100644 --- a/test_regress/t/t_randomize_method_constraints.v +++ b/test_regress/t/t_randomize_method_constraints.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef enum bit[15:0] { diff --git a/test_regress/t/t_randomize_method_nclass_bad.py b/test_regress/t/t_randomize_method_nclass_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_randomize_method_nclass_bad.py +++ b/test_regress/t/t_randomize_method_nclass_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method_nclass_bad.v b/test_regress/t/t_randomize_method_nclass_bad.v index 2f0acbc0f..f7026f717 100644 --- a/test_regress/t/t_randomize_method_nclass_bad.v +++ b/test_regress/t/t_randomize_method_nclass_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_randomize_method_param.py b/test_regress/t/t_randomize_method_param.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_randomize_method_param.py +++ b/test_regress/t/t_randomize_method_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method_param.v b/test_regress/t/t_randomize_method_param.v index 3aa32393d..d5f18a24a 100644 --- a/test_regress/t/t_randomize_method_param.v +++ b/test_regress/t/t_randomize_method_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; diff --git a/test_regress/t/t_randomize_method_std.py b/test_regress/t/t_randomize_method_std.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randomize_method_std.py +++ b/test_regress/t/t_randomize_method_std.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method_std.v b/test_regress/t/t_randomize_method_std.v index 7ed03f894..6c1d2cbe1 100644 --- a/test_regress/t/t_randomize_method_std.v +++ b/test_regress/t/t_randomize_method_std.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 process p; // force importing std into top-level namespace @@ -14,7 +14,7 @@ endclass module t; initial begin - C c = new; + automatic C c = new; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_randomize_method_types_unsup.py b/test_regress/t/t_randomize_method_types_unsup.py index 710a094ab..4ea94519e 100755 --- a/test_regress/t/t_randomize_method_types_unsup.py +++ b/test_regress/t/t_randomize_method_types_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method_types_unsup.v b/test_regress/t/t_randomize_method_types_unsup.v index 67210c627..cc1955a9e 100644 --- a/test_regress/t/t_randomize_method_types_unsup.v +++ b/test_regress/t/t_randomize_method_types_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_randomize_method_with.py b/test_regress/t/t_randomize_method_with.py index 0652adf1b..d71278a65 100755 --- a/test_regress/t/t_randomize_method_with.py +++ b/test_regress/t/t_randomize_method_with.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method_with.v b/test_regress/t/t_randomize_method_with.v index f1dad680a..4b2f638a9 100644 --- a/test_regress/t/t_randomize_method_with.v +++ b/test_regress/t/t_randomize_method_with.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ void'(cl.randomize()); \ prev_result = longint'(field); \ repeat(9) begin \ @@ -106,15 +106,16 @@ module mwith(); endfunction initial begin - int c = 30; - Foo foo = new(c); - Baz baz = new; + automatic int c = 30; + automatic Foo foo = new(c); + automatic Baz baz = new; typedef Baz baz_t; - baz_t baz1 = new; - Baz2 baz2 = new; - Bar bar = new; - Cls2 cls2 = new; - Cls cls = cls2; + automatic baz_t baz1 = new; + automatic Baz2 baz2 = new; + automatic Bar bar = new; + automatic Cls2 cls2 = new; + automatic Cls cls = cls2; + $display("foo.x = %d", foo.x); $display("-----------------"); diff --git a/test_regress/t/t_randomize_method_with_bad.out b/test_regress/t/t_randomize_method_with_bad.out index 736915084..b0dc8912b 100644 --- a/test_regress/t/t_randomize_method_with_bad.out +++ b/test_regress/t/t_randomize_method_with_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_randomize_method_with_bad.v:18:42: Can't find definition of task/function: 'in_mod_function' - 18 | int res = foo.randomize() with { v < in_mod_function(); }; - | ^~~~~~~~~~~~~~~ +%Error: t/t_randomize_method_with_bad.v:18:52: Can't find definition of task/function: 'in_mod_function' + 18 | automatic int res = foo.randomize() with { v < in_mod_function(); }; + | ^~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_randomize_method_with_bad.py b/test_regress/t/t_randomize_method_with_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_randomize_method_with_bad.py +++ b/test_regress/t/t_randomize_method_with_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method_with_bad.v b/test_regress/t/t_randomize_method_with_bad.v index b831634ce..5e6ce7ac8 100644 --- a/test_regress/t/t_randomize_method_with_bad.v +++ b/test_regress/t/t_randomize_method_with_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -14,7 +14,7 @@ module t_randomize_method_with_bad(); endfunction initial begin - Foo foo = new; - int res = foo.randomize() with { v < in_mod_function(); }; + automatic Foo foo = new; + automatic int res = foo.randomize() with { v < in_mod_function(); }; end endmodule diff --git a/test_regress/t/t_randomize_method_with_scoping.py b/test_regress/t/t_randomize_method_with_scoping.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_method_with_scoping.py +++ b/test_regress/t/t_randomize_method_with_scoping.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_method_with_scoping.v b/test_regress/t/t_randomize_method_with_scoping.v index 3f2deada5..803a24281 100644 --- a/test_regress/t/t_randomize_method_with_scoping.v +++ b/test_regress/t/t_randomize_method_with_scoping.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class c1; diff --git a/test_regress/t/t_randomize_module_var.py b/test_regress/t/t_randomize_module_var.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randomize_module_var.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_module_var.v b/test_regress/t/t_randomize_module_var.v new file mode 100644 index 000000000..85b78e83d --- /dev/null +++ b/test_regress/t/t_randomize_module_var.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + + +module t_randomize_module_var; + int golden_queue[$]; + + class Cls; + rand bit deq; + constraint valid_enq { + if (golden_queue.size() == 0) { + deq == 0; + } + } + endclass + + Cls tr; + + initial begin + tr = new; + + // Test 1: Empty queue - deq must be 0 + if (tr.randomize() == 0) begin + $stop; + end + if (tr.deq != 0) begin + $display("Error: Expected deq=0 when queue is empty, got %0d", tr.deq); + $stop; + end + + // Test 2: Non-empty queue - deq can be 0 or 1 + golden_queue.push_back(42); + if (tr.randomize() == 0) begin + $stop; + end + // deq can be 0 or 1, both are valid + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_randomize_nested_unsup.py b/test_regress/t/t_randomize_nested_unsup.py index 1bf1426f9..f3bbcad9d 100755 --- a/test_regress/t/t_randomize_nested_unsup.py +++ b/test_regress/t/t_randomize_nested_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_nested_unsup.v b/test_regress/t/t_randomize_nested_unsup.v index aa4977f57..e80ef256b 100644 --- a/test_regress/t/t_randomize_nested_unsup.v +++ b/test_regress/t/t_randomize_nested_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class A; diff --git a/test_regress/t/t_randomize_null_object.py b/test_regress/t/t_randomize_null_object.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randomize_null_object.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_null_object.v b/test_regress/t/t_randomize_null_object.v new file mode 100644 index 000000000..fdd156fab --- /dev/null +++ b/test_regress/t/t_randomize_null_object.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); +// verilog_format: on + +class SimpleRandClass; + rand bit [7:0] value; + constraint value_con {value > 0 && value < 200;} + function new(); + endfunction +endclass + +module t; + SimpleRandClass obj; + int rand_result; + + initial begin + obj = null; + rand_result = obj.randomize(); + `checkd(rand_result, 0); + + obj = new(); + rand_result = obj.randomize(); + `checkd(rand_result, 1); + `check_range(obj.value, 1, 199); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_param_with.py b/test_regress/t/t_randomize_param_with.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_param_with.py +++ b/test_regress/t/t_randomize_param_with.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_param_with.v b/test_regress/t/t_randomize_param_with.v index 3b7039436..89dcede46 100644 --- a/test_regress/t/t_randomize_param_with.v +++ b/test_regress/t/t_randomize_param_with.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, constr, cond) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ if (!bit'(cl.randomize() with { constr; })) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ @@ -30,8 +30,8 @@ endclass module t; initial begin - Cls#() cd = new; - Cls#(5) c5 = new; + automatic Cls#() cd = new; + automatic Cls#(5) c5 = new; `check_rand(cd, cd.x, x > 0, cd.x > 0 && cd.x <= 3); `check_rand(cd, cd.x, x > y, cd.x > -100 && cd.x <= 3); diff --git a/test_regress/t/t_randomize_prepost.py b/test_regress/t/t_randomize_prepost.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_prepost.py +++ b/test_regress/t/t_randomize_prepost.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_prepost.v b/test_regress/t/t_randomize_prepost.v index af65d780e..e0540f34c 100644 --- a/test_regress/t/t_randomize_prepost.v +++ b/test_regress/t/t_randomize_prepost.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_randomize_prepost_alone.py b/test_regress/t/t_randomize_prepost_alone.py index cca4c9e73..d6d35e7fd 100755 --- a/test_regress/t/t_randomize_prepost_alone.py +++ b/test_regress/t/t_randomize_prepost_alone.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_prepost_alone.v b/test_regress/t/t_randomize_prepost_alone.v index b6bdfd06a..d9479cf63 100644 --- a/test_regress/t/t_randomize_prepost_alone.v +++ b/test_regress/t/t_randomize_prepost_alone.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; diff --git a/test_regress/t/t_randomize_prepost_nested.py b/test_regress/t/t_randomize_prepost_nested.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randomize_prepost_nested.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_prepost_nested.v b/test_regress/t/t_randomize_prepost_nested.v new file mode 100644 index 000000000..4ce6c32ed --- /dev/null +++ b/test_regress/t/t_randomize_prepost_nested.v @@ -0,0 +1,244 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +// Test: pre/post_randomize callbacks on nested rand class objects and inherited methods +// Covers: IEEE 1800-2017 Section 18.4.1 recursive callback invocation + +// --- Inherited callbacks (no override) --- + +class BaseInherit; + rand int x; + int pre_count; + int post_count; + + function new(); + pre_count = 0; + post_count = 0; + endfunction + + function void pre_randomize; + pre_count++; + endfunction + + function void post_randomize; + post_count++; + endfunction +endclass + +class DerivedNoOverride extends BaseInherit; + rand int y; + + function new(); + super.new(); + endfunction + // Does NOT override pre/post_randomize +endclass + +class DerivedPartialOverride extends BaseInherit; + rand int z; + int derived_pre_count; + + function new(); + super.new(); + derived_pre_count = 0; + endfunction + + function void pre_randomize; + derived_pre_count++; + super.pre_randomize(); + endfunction + // Does NOT override post_randomize +endclass + +// Override both without calling super +class DerivedOverrideBoth extends BaseInherit; + rand int w; + int derived_pre_count; + int derived_post_count; + + function new(); + super.new(); + derived_pre_count = 0; + derived_post_count = 0; + endfunction + + function void pre_randomize; + derived_pre_count++; + endfunction + + function void post_randomize; + derived_post_count++; + endfunction +endclass + +// Override only post_randomize without calling super +class DerivedOverridePostOnly extends BaseInherit; + rand int v; + int derived_post_count; + + function new(); + super.new(); + derived_post_count = 0; + endfunction + + // Does NOT override pre_randomize -> should inherit BaseInherit's + function void post_randomize; + derived_post_count++; + endfunction +endclass + +// --- Nested rand class callbacks (3-level) --- + +class Level3; + rand bit [7:0] val; + int pre_count; + int post_count; + + constraint c_val {val inside {[10 : 200]};} + + function new(); + pre_count = 0; + post_count = 0; + endfunction + + function void pre_randomize; + pre_count++; + endfunction + + function void post_randomize; + post_count++; + endfunction +endclass + +class Level2; + rand Level3 l3; + rand bit [7:0] val; + int pre_count; + int post_count; + + constraint c_val {val inside {[1 : 100]};} + + function new(); + l3 = new(); + pre_count = 0; + post_count = 0; + endfunction + + function void pre_randomize; + pre_count++; + endfunction + + function void post_randomize; + post_count++; + endfunction +endclass + +class Level1; + rand Level2 l2; + rand bit [7:0] val; + int pre_count; + int post_count; + + constraint c_val {val inside {[50 : 150]};} + + function new(); + l2 = new(); + pre_count = 0; + post_count = 0; + endfunction + + function void pre_randomize; + pre_count++; + endfunction + + function void post_randomize; + post_count++; + endfunction +endclass + +module t; + + initial begin + automatic int r; + + // Test 1: Inherited callbacks (no override) + begin + automatic DerivedNoOverride obj = new; + r = obj.randomize(); + `checkd(r, 1); + `checkd(obj.pre_count, 1); + `checkd(obj.post_count, 1); + end + + // Test 2: Partial override (pre overridden, post inherited) + begin + automatic DerivedPartialOverride obj = new; + r = obj.randomize(); + `checkd(r, 1); + `checkd(obj.derived_pre_count, 1); + `checkd(obj.pre_count, 1); // super.pre_randomize called + `checkd(obj.post_count, 1); // inherited post_randomize + end + + // Test 3: Override both without super - base counts stay 0 + begin + automatic DerivedOverrideBoth obj = new; + r = obj.randomize(); + `checkd(r, 1); + `checkd(obj.derived_pre_count, 1); + `checkd(obj.derived_post_count, 1); + `checkd(obj.pre_count, 0); // base NOT called (no super) + `checkd(obj.post_count, 0); // base NOT called (no super) + end + + // Test 4: Override only post, inherit pre + begin + automatic DerivedOverridePostOnly obj = new; + r = obj.randomize(); + `checkd(r, 1); + `checkd(obj.pre_count, 1); // inherited pre_randomize called + `checkd(obj.derived_post_count, 1); // overridden post called + `checkd(obj.post_count, 0); // base post NOT called (no super) + end + + // Test 5: Nested callbacks (3-level) + begin + automatic Level1 l1 = new; + r = l1.randomize(); + `checkd(r, 1); + `checkd(l1.pre_count, 1); + `checkd(l1.post_count, 1); + `checkd(l1.l2.pre_count, 1); + `checkd(l1.l2.post_count, 1); + `checkd(l1.l2.l3.pre_count, 1); + `checkd(l1.l2.l3.post_count, 1); + end + + // Test 6: Multiple randomizations + begin + automatic Level1 l1 = new; + repeat (5) begin + r = l1.randomize(); + `checkd(r, 1); + end + `checkd(l1.pre_count, 5); + `checkd(l1.post_count, 5); + `checkd(l1.l2.pre_count, 5); + `checkd(l1.l2.post_count, 5); + `checkd(l1.l2.l3.pre_count, 5); + `checkd(l1.l2.l3.post_count, 5); + end + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_randomize_prepost_super.py b/test_regress/t/t_randomize_prepost_super.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_randomize_prepost_super.py +++ b/test_regress/t/t_randomize_prepost_super.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_prepost_super.v b/test_regress/t/t_randomize_prepost_super.v index 6327e05b7..de4e4030a 100644 --- a/test_regress/t/t_randomize_prepost_super.v +++ b/test_regress/t/t_randomize_prepost_super.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_randomize_queue_constraints.py b/test_regress/t/t_randomize_queue_constraints.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_queue_constraints.py +++ b/test_regress/t/t_randomize_queue_constraints.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_queue_constraints.v b/test_regress/t/t_randomize_queue_constraints.v index b88bace7b..6677b110e 100644 --- a/test_regress/t/t_randomize_queue_constraints.v +++ b/test_regress/t/t_randomize_queue_constraints.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ @@ -41,7 +41,7 @@ endclass module t_randomize_queue_constraints; initial begin - Foo foo = new; + automatic Foo foo = new; `check_rand(foo, foo.m_idx, foo.m_idx inside {[0:9]} && foo.m_intQueue[foo.m_idx] == foo.m_idx + 1); $display("Queue: %p", foo.m_intQueue); diff --git a/test_regress/t/t_randomize_queue_size.py b/test_regress/t/t_randomize_queue_size.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_queue_size.py +++ b/test_regress/t/t_randomize_queue_size.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_queue_size.v b/test_regress/t/t_randomize_queue_size.v old mode 100755 new mode 100644 index f1429f642..2fbc550a6 --- a/test_regress/t/t_randomize_queue_size.v +++ b/test_regress/t/t_randomize_queue_size.v @@ -1,13 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define check_rand(cl, field, cond) \ begin \ - longint prev_result; \ - int ok = 0; \ + automatic longint prev_result; \ + automatic int ok; \ if (!bit'(cl.randomize())) $stop; \ prev_result = longint'(field); \ if (!(cond)) $stop; \ @@ -55,9 +55,9 @@ endclass module t; initial begin - Foo foo = new; - Bar bar = new; - Baz baz = new; + automatic Foo foo = new; + automatic Bar bar = new; + automatic Baz baz = new; void'(foo.randomize()); if (foo.q.size() != 15) $stop; diff --git a/test_regress/t/t_randomize_queue_wide.py b/test_regress/t/t_randomize_queue_wide.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_randomize_queue_wide.py +++ b/test_regress/t/t_randomize_queue_wide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_queue_wide.v b/test_regress/t/t_randomize_queue_wide.v index 7fbb34516..12643c64e 100644 --- a/test_regress/t/t_randomize_queue_wide.v +++ b/test_regress/t/t_randomize_queue_wide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -26,7 +26,7 @@ endclass module t; int success; initial begin - Foo foo = new; + automatic Foo foo = new; success = foo.randomize(); if (success != 1) $stop; foo.self_check(); diff --git a/test_regress/t/t_randomize_rand_mode.py b/test_regress/t/t_randomize_rand_mode.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randomize_rand_mode.py +++ b/test_regress/t/t_randomize_rand_mode.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_rand_mode.v b/test_regress/t/t_randomize_rand_mode.v index 9e3e7e59e..afc3192b9 100644 --- a/test_regress/t/t_randomize_rand_mode.v +++ b/test_regress/t/t_randomize_rand_mode.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_randomize_rand_mode_bad.py b/test_regress/t/t_randomize_rand_mode_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_randomize_rand_mode_bad.py +++ b/test_regress/t/t_randomize_rand_mode_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_rand_mode_bad.v b/test_regress/t/t_randomize_rand_mode_bad.v index 6f3b5a0e9..0d3ba5236 100644 --- a/test_regress/t/t_randomize_rand_mode_bad.v +++ b/test_regress/t/t_randomize_rand_mode_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Packet; diff --git a/test_regress/t/t_randomize_rand_mode_constr.py b/test_regress/t/t_randomize_rand_mode_constr.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_rand_mode_constr.py +++ b/test_regress/t/t_randomize_rand_mode_constr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_rand_mode_constr.v b/test_regress/t/t_randomize_rand_mode_constr.v index 2e06b2061..49e6dba4d 100644 --- a/test_regress/t/t_randomize_rand_mode_constr.v +++ b/test_regress/t/t_randomize_rand_mode_constr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -99,11 +99,11 @@ endclass module t; initial begin - logic ok = 0; - int res; - Baz baz = new; - Qux qux = new; - Quux quux = new; + automatic logic ok = 0; + automatic int res; + automatic Baz baz = new; + automatic Qux qux = new; + automatic Quux quux = new; baz.test; qux.test; diff --git a/test_regress/t/t_randomize_rand_mode_funcarg.py b/test_regress/t/t_randomize_rand_mode_funcarg.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode_funcarg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_rand_mode_funcarg.v b/test_regress/t/t_randomize_rand_mode_funcarg.v new file mode 100644 index 000000000..2d8cb117b --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode_funcarg.v @@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// Test: rand_mode() used as a function argument (not standalone expression) +// Ensures nested rand_mode() calls inside function arguments are properly +// transformed and do not cause Internal Error in V3SplitVar. + +class RandModeClass; + rand int x; + rand int y; + + constraint c { + x inside {[1 : 255]}; + y inside {[1 : 255]}; + } + + task check_mode(string name, int actual, int expected); + if (actual !== expected) begin + $display("Error: %s.rand_mode() = %0d, expected %0d", name, actual, expected); + $stop; + end + endtask + + // Task that calls check_mode with rand_mode() as argument + task test_funcarg; + check_mode("x", x.rand_mode(), 1); + check_mode("y", y.rand_mode(), 1); + + x.rand_mode(0); + check_mode("x", x.rand_mode(), 0); + check_mode("y", y.rand_mode(), 1); + + x.rand_mode(1); + check_mode("x", x.rand_mode(), 1); + + // Also test using rand_mode() in $display arguments + $display("x.rand_mode=%0d y.rand_mode=%0d", x.rand_mode(), y.rand_mode()); + endtask +endclass + +module t; + initial begin + automatic RandModeClass obj = new; + obj.test_funcarg(); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_rand_mode_unsup.py b/test_regress/t/t_randomize_rand_mode_unsup.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_randomize_rand_mode_unsup.py +++ b/test_regress/t/t_randomize_rand_mode_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_rand_mode_unsup.v b/test_regress/t/t_randomize_rand_mode_unsup.v index 4132667fe..98fcdd99a 100644 --- a/test_regress/t/t_randomize_rand_mode_unsup.v +++ b/test_regress/t/t_randomize_rand_mode_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 class Packet; @@ -13,7 +13,7 @@ endclass module t; initial begin - Packet p = new; + automatic Packet p = new; p.m_dyn_arr[0].rand_mode(0); p.m_unp_arr[0].rand_mode(0); p.m_struct.y.rand_mode(0); diff --git a/test_regress/t/t_randomize_real.py b/test_regress/t/t_randomize_real.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_randomize_real.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_real.v b/test_regress/t/t_randomize_real.v new file mode 100644 index 000000000..bea1fdcc0 --- /dev/null +++ b/test_regress/t/t_randomize_real.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +class Cls; + rand real m_real; +endclass + +module test; + localparam LOOPS = 1000; + + int negative; + int bitcounts[64]; + int i; + bit [63:0] rbits; + + initial begin + Cls c; + c = new; + + repeat (LOOPS) begin + i = c.randomize(); + `checkd(i, 1); + + rbits = $realtobits(c.m_real); +`ifdef TEST_VERBOSE + $display("%x %g", rbits, c.m_real); +`endif + + if (c.m_real < 0) negative++; + for (int b = 0; b < 64; ++b) begin + if (rbits[b]) bitcounts[b]++; + end + end + + if (negative < LOOPS * 0.4) $error("Too few negative %0d", negative); + for (int b = 0; b < 64; ++b) begin + if (bitcounts[b] < LOOPS * 0.4) $error("Too few 1 bits at [%0d]: %0d", b, bitcounts[b]); + end + $finish; + end + +endmodule diff --git a/test_regress/t/t_randomize_srandom.py b/test_regress/t/t_randomize_srandom.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randomize_srandom.py +++ b/test_regress/t/t_randomize_srandom.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_srandom.v b/test_regress/t/t_randomize_srandom.v index cf6c32530..172f7df38 100644 --- a/test_regress/t/t_randomize_srandom.v +++ b/test_regress/t/t_randomize_srandom.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_randomize_struct_sel.py b/test_regress/t/t_randomize_struct_sel.py new file mode 100755 index 000000000..8862c2c31 --- /dev/null +++ b/test_regress/t/t_randomize_struct_sel.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_struct_sel.v b/test_regress/t/t_randomize_struct_sel.v new file mode 100644 index 000000000..aa65105ca --- /dev/null +++ b/test_regress/t/t_randomize_struct_sel.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +typedef struct {int x;} struct_t; + +class ConstrClass; + struct_t obj; + rand int rand_int; + constraint addr_c {rand_int == obj.x;} +endclass + +module t; + ConstrClass o; + initial begin + o = new; + o.obj.x = 42; + if (o.randomize() == 0) begin + $display("Randomization failed"); + $stop; + end + else if (o.obj.x != o.rand_int) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_this.py b/test_regress/t/t_randomize_this.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randomize_this.py +++ b/test_regress/t/t_randomize_this.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_this.v b/test_regress/t/t_randomize_this.v index 658a52c2f..6120581d6 100644 --- a/test_regress/t/t_randomize_this.v +++ b/test_regress/t/t_randomize_this.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Member; diff --git a/test_regress/t/t_randomize_this_inline.py b/test_regress/t/t_randomize_this_inline.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randomize_this_inline.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_this_inline.v b/test_regress/t/t_randomize_this_inline.v new file mode 100644 index 000000000..0f06b676f --- /dev/null +++ b/test_regress/t/t_randomize_this_inline.v @@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); +// verilog_format: on + +// Test: 'this' keyword inside inline randomize() with {} constraint blocks. +// 'this' should refer to the object being randomized (IEEE 1800-2023 18.7). + +class DataItem; + rand bit [7:0] value; + rand bit [7:0] limit; + constraint default_con {limit inside {[8'd50 : 8'd200]};} +endclass + +// Test 4: 'this' in inline constraint called from another class method. +// 'this' must bind to the randomized object, not the calling class. +class Caller; + rand bit [7:0] own_value; + function int do_rand(DataItem item); + return item.randomize() with { + this.value > 8'd30; + this.value < 8'd40; + }; + endfunction +endclass + +module t; + initial begin + automatic DataItem item = new(); + automatic Caller caller = new(); + automatic int rand_ok; + + // Test 1: 'this.member' in inline constraint from module-level code + rand_ok = item.randomize() with { + this.value > 8'd10; + this.value < 8'd50; + }; + `checkd(rand_ok, 1) + `check_range(item.value, 11, 49) + `check_range(item.limit, 50, 200) + + // Test 2: multiple 'this.member' references + rand_ok = item.randomize() with { + this.value > 8'd20; + this.value < 8'd30; + }; + `checkd(rand_ok, 1) + `check_range(item.value, 21, 29) + + // Test 3: mix of 'this.member' and unqualified member + rand_ok = item.randomize() with { + this.value > 8'd5; + this.value < 8'd100; + limit > 8'd150; + }; + `checkd(rand_ok, 1) + `check_range(item.value, 6, 99) + `check_range(item.limit, 151, 200) + + // Test 4: 'this' binds to randomized object, not calling class + rand_ok = caller.do_rand(item); + `checkd(rand_ok, 1) + `check_range(item.value, 31, 39) + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_this_with.py b/test_regress/t/t_randomize_this_with.py index c88b3d0f3..5e3c074cf 100755 --- a/test_regress/t/t_randomize_this_with.py +++ b/test_regress/t/t_randomize_this_with.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_this_with.v b/test_regress/t/t_randomize_this_with.v index 60bbd72d7..8a2d3d7b2 100644 --- a/test_regress/t/t_randomize_this_with.v +++ b/test_regress/t/t_randomize_this_with.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 // verilog_format: off @@ -23,7 +23,7 @@ endclass module t; initial begin - Cls c = new; + automatic Cls c = new; c.body(); $finish; end diff --git a/test_regress/t/t_randomize_union.py b/test_regress/t/t_randomize_union.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_randomize_union.py +++ b/test_regress/t/t_randomize_union.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_union.v b/test_regress/t/t_randomize_union.v old mode 100755 new mode 100644 index 900e606b4..4fbdcdf80 --- a/test_regress/t/t_randomize_union.v +++ b/test_regress/t/t_randomize_union.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 typedef union packed { diff --git a/test_regress/t/t_randomize_union_bad.py b/test_regress/t/t_randomize_union_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_randomize_union_bad.py +++ b/test_regress/t/t_randomize_union_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_union_bad.v b/test_regress/t/t_randomize_union_bad.v index 4fb462b74..08c00e22d 100644 --- a/test_regress/t/t_randomize_union_bad.v +++ b/test_regress/t/t_randomize_union_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 typedef union { diff --git a/test_regress/t/t_randomize_unique_elem.py b/test_regress/t/t_randomize_unique_elem.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randomize_unique_elem.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_unique_elem.v b/test_regress/t/t_randomize_unique_elem.v new file mode 100644 index 000000000..94fbc85ce --- /dev/null +++ b/test_regress/t/t_randomize_unique_elem.v @@ -0,0 +1,87 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +// Test unique constraint on explicit array element subsets (IEEE 18.5.9). +// bit [3:0] keeps the value space small so collisions are near-certain +// without proper constraint enforcement. + +class UniqueElemSubset; + rand bit [3:0] arr[10]; + + constraint unique_subset_con {unique {arr[2], arr[3], arr[4], arr[5], arr[6]};} + + function new(); + endfunction + + function bit check_unique(); + for (int i = 2; i <= 6; i++) begin + for (int j = i + 1; j <= 6; j++) begin + if (arr[i] == arr[j]) return 0; + end + end + return 1; + endfunction +endclass + +class UniqueElemFour; + rand bit [3:0] data[8]; + + constraint unique_data_con {unique {data[1], data[2], data[3], data[4]};} + + function new(); + endfunction + + function bit check_unique(); + for (int i = 1; i <= 4; i++) begin + for (int j = i + 1; j <= 4; j++) begin + if (data[i] == data[j]) return 0; + end + end + return 1; + endfunction +endclass + +class UniqueElemSingle; + rand bit [3:0] val[4]; + + constraint unique_single_con {unique {val[0]};} + + function new(); + endfunction +endclass + +module t; + UniqueElemSubset ues; + UniqueElemFour uef; + UniqueElemSingle uesgl; + + initial begin + ues = new(); + repeat (20) begin + `checkd(ues.randomize(), 1) + `checkd(ues.check_unique(), 1) + end + + uef = new(); + repeat (20) begin + `checkd(uef.randomize(), 1) + `checkd(uef.check_unique(), 1) + end + + uesgl = new(); + repeat (5) begin + `checkd(uesgl.randomize(), 1) + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_unpacked_bad.py b/test_regress/t/t_randomize_unpacked_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_randomize_unpacked_bad.py +++ b/test_regress/t/t_randomize_unpacked_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_unpacked_bad.v b/test_regress/t/t_randomize_unpacked_bad.v index d6a85358a..66cf26fec 100644 --- a/test_regress/t/t_randomize_unpacked_bad.v +++ b/test_regress/t/t_randomize_unpacked_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class ex; diff --git a/test_regress/t/t_randomize_unpacked_wide.py b/test_regress/t/t_randomize_unpacked_wide.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_randomize_unpacked_wide.py +++ b/test_regress/t/t_randomize_unpacked_wide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_unpacked_wide.v b/test_regress/t/t_randomize_unpacked_wide.v index 07d85986d..74c4174bc 100644 --- a/test_regress/t/t_randomize_unpacked_wide.v +++ b/test_regress/t/t_randomize_unpacked_wide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; @@ -22,7 +22,7 @@ endclass module t; int success; initial begin - Foo foo = new; + automatic Foo foo = new; success = foo.randomize(); if (success != 1) $stop; foo.self_check(); diff --git a/test_regress/t/t_randomize_with_constraint.py b/test_regress/t/t_randomize_with_constraint.py index 1bf1426f9..f3bbcad9d 100755 --- a/test_regress/t/t_randomize_with_constraint.py +++ b/test_regress/t/t_randomize_with_constraint.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_with_constraint.v b/test_regress/t/t_randomize_with_constraint.v index 87b56dbc0..496a31522 100644 --- a/test_regress/t/t_randomize_with_constraint.v +++ b/test_regress/t/t_randomize_with_constraint.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_randomize_within_func.py b/test_regress/t/t_randomize_within_func.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_randomize_within_func.py +++ b/test_regress/t/t_randomize_within_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randomize_within_func.v b/test_regress/t/t_randomize_within_func.v old mode 100755 new mode 100644 index e1eb0d2ad..d17390857 --- a/test_regress/t/t_randomize_within_func.v +++ b/test_regress/t/t_randomize_within_func.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Test for unsupported multiple global constraints -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 class Cls; @@ -23,7 +23,7 @@ endclass module t_randomize_within_func; initial begin - Cls c = new; + automatic Cls c = new; c.test_this_randomize(); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_randsequence.py b/test_regress/t/t_randsequence.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randsequence.py +++ b/test_regress/t/t_randsequence.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randsequence.v b/test_regress/t/t_randsequence.v index 92ae8d320..739178d02 100644 --- a/test_regress/t/t_randsequence.v +++ b/test_regress/t/t_randsequence.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // verilog_format: off diff --git a/test_regress/t/t_randsequence_bad.py b/test_regress/t/t_randsequence_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_randsequence_bad.py +++ b/test_regress/t/t_randsequence_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randsequence_bad.v b/test_regress/t/t_randsequence_bad.v index 1d19f5d2c..0eab9d242 100644 --- a/test_regress/t/t_randsequence_bad.v +++ b/test_regress/t/t_randsequence_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_randsequence_func.py b/test_regress/t/t_randsequence_func.py index 966dc53da..20b96a7d7 100755 --- a/test_regress/t/t_randsequence_func.py +++ b/test_regress/t/t_randsequence_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randsequence_func.v b/test_regress/t/t_randsequence_func.v index 0debc5249..d02b5d53a 100644 --- a/test_regress/t/t_randsequence_func.v +++ b/test_regress/t/t_randsequence_func.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2025 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // verilog_format: off diff --git a/test_regress/t/t_randsequence_randjoin.py b/test_regress/t/t_randsequence_randjoin.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randsequence_randjoin.py +++ b/test_regress/t/t_randsequence_randjoin.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randsequence_randjoin.v b/test_regress/t/t_randsequence_randjoin.v index 5b3f17236..47bd297c2 100644 --- a/test_regress/t/t_randsequence_randjoin.v +++ b/test_regress/t/t_randsequence_randjoin.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // verilog_format: off diff --git a/test_regress/t/t_randsequence_recurse.py b/test_regress/t/t_randsequence_recurse.py index d17523dd7..199967121 100755 --- a/test_regress/t/t_randsequence_recurse.py +++ b/test_regress/t/t_randsequence_recurse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randsequence_recurse.v b/test_regress/t/t_randsequence_recurse.v index 92fc5f467..f65b30e0b 100644 --- a/test_regress/t/t_randsequence_recurse.v +++ b/test_regress/t/t_randsequence_recurse.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // verilog_format: off diff --git a/test_regress/t/t_randsequence_rs_bad.py b/test_regress/t/t_randsequence_rs_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_randsequence_rs_bad.py +++ b/test_regress/t/t_randsequence_rs_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randsequence_rs_bad.v b/test_regress/t/t_randsequence_rs_bad.v index 7fe20dade..e0ad560fc 100644 --- a/test_regress/t/t_randsequence_rs_bad.v +++ b/test_regress/t/t_randsequence_rs_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2025 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_randsequence_svtests.py b/test_regress/t/t_randsequence_svtests.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randsequence_svtests.py +++ b/test_regress/t/t_randsequence_svtests.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randsequence_svtests.v b/test_regress/t/t_randsequence_svtests.v index 6978b9f51..dd087d63b 100644 --- a/test_regress/t/t_randsequence_svtests.v +++ b/test_regress/t/t_randsequence_svtests.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Based on code Copyright (C) 2019-2021 The SymbiFlow Authors. +// SPDX-FileCopyrightText: 2019-2021 The SymbiFlow Authors // SPDX-License-Identifier: ISC // verilog_format: off @@ -24,9 +24,9 @@ module t; initial begin int x; - bit flag = 1; - int switch = 1; - int break_on = 1; + automatic bit flag = 1; + automatic int switch = 1; + automatic int break_on = 1; static int return_on = 1; x = 0; diff --git a/test_regress/t/t_randstate_func.py b/test_regress/t/t_randstate_func.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randstate_func.py +++ b/test_regress/t/t_randstate_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randstate_func.v b/test_regress/t/t_randstate_func.v index eea140025..663309356 100644 --- a/test_regress/t/t_randstate_func.v +++ b/test_regress/t/t_randstate_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_randstate_obj.py b/test_regress/t/t_randstate_obj.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_randstate_obj.py +++ b/test_regress/t/t_randstate_obj.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randstate_obj.v b/test_regress/t/t_randstate_obj.v index fa246aca9..af0d8236f 100644 --- a/test_regress/t/t_randstate_obj.v +++ b/test_regress/t/t_randstate_obj.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_randstate_seed_bad.py b/test_regress/t/t_randstate_seed_bad.py index 97abb660e..c03eaf086 100755 --- a/test_regress/t/t_randstate_seed_bad.py +++ b/test_regress/t/t_randstate_seed_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_randstate_seed_bad.v b/test_regress/t/t_randstate_seed_bad.v index a15b415d4..c454710a9 100644 --- a/test_regress/t/t_randstate_seed_bad.v +++ b/test_regress/t/t_randstate_seed_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_real_cast.py b/test_regress/t/t_real_cast.py index 0e36f03cc..db898a84c 100755 --- a/test_regress/t/t_real_cast.py +++ b/test_regress/t/t_real_cast.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_real_cast.v b/test_regress/t/t_real_cast.v index bd698541e..4a5b3e187 100644 --- a/test_regress/t/t_real_cast.v +++ b/test_regress/t/t_real_cast.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Confirm x randomization stability // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_real_out_of_bounds.py b/test_regress/t/t_real_out_of_bounds.py index 563b6fc6f..78ebab213 100755 --- a/test_regress/t/t_real_out_of_bounds.py +++ b/test_regress/t/t_real_out_of_bounds.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_real_out_of_bounds.v b/test_regress/t/t_real_out_of_bounds.v index 62a9d406a..6aece1067 100644 --- a/test_regress/t/t_real_out_of_bounds.v +++ b/test_regress/t/t_real_out_of_bounds.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_real_param.py b/test_regress/t/t_real_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_real_param.py +++ b/test_regress/t/t_real_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_real_param.v b/test_regress/t/t_real_param.v index fe95bebad..8927b2436 100644 --- a/test_regress/t/t_real_param.v +++ b/test_regress/t/t_real_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Todd Strader // SPDX-License-Identifier: CC0-1.0 module foo diff --git a/test_regress/t/t_recursive_method.py b/test_regress/t/t_recursive_method.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_recursive_method.py +++ b/test_regress/t/t_recursive_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_recursive_method.v b/test_regress/t/t_recursive_method.v index 2e0e84268..1209221af 100644 --- a/test_regress/t/t_recursive_method.v +++ b/test_regress/t/t_recursive_method.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Fib; @@ -46,8 +46,8 @@ endclass module t; initial begin - Fib fib = new; - Getter3 getter3 = new; + automatic Fib fib = new; + automatic Getter3 getter3 = new; if (fib.get_fib(0) != 0) $stop; if (fib.get_fib(1) != 1) $stop; diff --git a/test_regress/t/t_recursive_module_bug.py b/test_regress/t/t_recursive_module_bug.py index 16de8f485..66009b455 100755 --- a/test_regress/t/t_recursive_module_bug.py +++ b/test_regress/t/t_recursive_module_bug.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_recursive_module_bug.v b/test_regress/t/t_recursive_module_bug.v index 00d362073..118d1460c 100644 --- a/test_regress/t/t_recursive_module_bug.v +++ b/test_regress/t/t_recursive_module_bug.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // This hits a case where parameter specialization of recursive modules diff --git a/test_regress/t/t_recursive_module_bug_2.py b/test_regress/t/t_recursive_module_bug_2.py index 16de8f485..66009b455 100755 --- a/test_regress/t/t_recursive_module_bug_2.py +++ b/test_regress/t/t_recursive_module_bug_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_recursive_module_bug_2.v b/test_regress/t/t_recursive_module_bug_2.v index 13ab908cf..658442cd8 100644 --- a/test_regress/t/t_recursive_module_bug_2.v +++ b/test_regress/t/t_recursive_module_bug_2.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module a #(parameter N) (); diff --git a/test_regress/t/t_recursive_typedef_bad.out b/test_regress/t/t_recursive_typedef_bad.out new file mode 100644 index 000000000..861046388 --- /dev/null +++ b/test_regress/t/t_recursive_typedef_bad.out @@ -0,0 +1,30 @@ +%Error: t/t_recursive_typedef_bad.v:12:20: Recursive type definition + : ... note: In instance 't.u_circ' + t/t_recursive_typedef_bad.v:12:20: ... Type chain: PARAMTYPEDTYPE 'A' + 12 | parameter type A = B, + | ^ + t/t_recursive_typedef_bad.v:12:24: ... Type chain: REFDTYPE 'B' + 12 | parameter type A = B, + | ^ + t/t_recursive_typedef_bad.v:13:20: ... Type chain: PARAMTYPEDTYPE 'B' + 13 | parameter type B = A + | ^ + t/t_recursive_typedef_bad.v:13:24: ... Type chain: REFDTYPE 'A' + 13 | parameter type B = A + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_recursive_typedef_bad.v:13:20: Recursive type definition + : ... note: In instance 't.u_circ' + t/t_recursive_typedef_bad.v:13:20: ... Type chain: PARAMTYPEDTYPE 'B' + 13 | parameter type B = A + | ^ + t/t_recursive_typedef_bad.v:13:24: ... Type chain: REFDTYPE 'A' + 13 | parameter type B = A + | ^ + t/t_recursive_typedef_bad.v:12:20: ... Type chain: PARAMTYPEDTYPE 'A' + 12 | parameter type A = B, + | ^ + t/t_recursive_typedef_bad.v:12:24: ... Type chain: REFDTYPE 'B' + 12 | parameter type A = B, + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_recursive_typedef_bad.py b/test_regress/t/t_recursive_typedef_bad.py new file mode 100755 index 000000000..3b2f23460 --- /dev/null +++ b/test_regress/t/t_recursive_typedef_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_recursive_typedef_bad.v b/test_regress/t/t_recursive_typedef_bad.v new file mode 100644 index 000000000..35811eedc --- /dev/null +++ b/test_regress/t/t_recursive_typedef_bad.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 +// +// Recursive type definition via circular parameter type defaults +// should produce a clear error with type chain display. + +// Circular: A defaults to B, B defaults to A +module circ #( + parameter type A = B, + parameter type B = A +) ( + input A ai, + output B bo +); + assign bo = ai; +endmodule + +module t (); + logic [7:0] x, y; + circ u_circ ( + .ai(x), + .bo(y) + ); + initial begin + $finish; + end +endmodule diff --git a/test_regress/t/t_reloop_cam.py b/test_regress/t/t_reloop_cam.py index 44a025926..3333f0da8 100755 --- a/test_regress/t/t_reloop_cam.py +++ b/test_regress/t/t_reloop_cam.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -18,7 +18,7 @@ test.compile(verilator_flags2=[ test.execute() if test.vlt_all: - test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 768) - test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 3) + test.file_grep(test.stats, r'Optimizations, Reloop iterations\s+(\d+)', 512) + test.file_grep(test.stats, r'Optimizations, Reloops\s+(\d+)', 2) test.passes() diff --git a/test_regress/t/t_reloop_cam.v b/test_regress/t/t_reloop_cam.v index 5c568524f..6f347345b 100644 --- a/test_regress/t/t_reloop_cam.v +++ b/test_regress/t/t_reloop_cam.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_reloop_cam_off.py b/test_regress/t/t_reloop_cam_off.py index 2c5747d83..935411bee 100755 --- a/test_regress/t/t_reloop_cam_off.py +++ b/test_regress/t/t_reloop_cam_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_reloop_inlined.py b/test_regress/t/t_reloop_inlined.py new file mode 100755 index 000000000..686612a8f --- /dev/null +++ b/test_regress/t/t_reloop_inlined.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=[ + "--binary", "--unroll-count", "1024", "--inline-cfuncs", "100000000", "--output-split-cfuncs", + "50", "--reloop-limit", "2" +]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_reloop_inlined.v b/test_regress/t/t_reloop_inlined.v new file mode 100644 index 000000000..e2cc17cc5 --- /dev/null +++ b/test_regress/t/t_reloop_inlined.v @@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + bit clk1 = 1'b0; + bit clk2 = 1'b0; + always #5 clk1 = ~clk1; + always #10 clk2 = ~clk2; + + int iarray[63:0]; + int oarray1[63:0]; + int oarray2[63:0]; + + initial begin + for (int i = 0; i < 64; i = i + 1) begin + iarray[i] = i; + end + + #100; + + for (int i = 0; i < 64; i = i + 1) begin + $display("%d %d %d", i, oarray1[i], oarray2[i]); + end + + $write("*-* All Finished *-*\n"); + $finish; + end + + always @(posedge clk1) begin + for (int i = 0; i < 64; i = i + 1) begin + oarray1[i] = iarray[i]; + end + end + always @(posedge clk2) begin + for (int i = 0; i < 64; i = i + 1) begin + oarray2[i] = iarray[i]; + end + end + +endmodule diff --git a/test_regress/t/t_reloop_local.py b/test_regress/t/t_reloop_local.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_reloop_local.py +++ b/test_regress/t/t_reloop_local.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_reloop_local.v b/test_regress/t/t_reloop_local.v index e66690090..9a9dce57c 100644 --- a/test_regress/t/t_reloop_local.v +++ b/test_regress/t/t_reloop_local.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Justin Yao Du. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Justin Yao Du // SPDX-License-Identifier: CC0-1.0 typedef logic [7:0] Word; diff --git a/test_regress/t/t_reloop_offset.py b/test_regress/t/t_reloop_offset.py index a391e447b..e54c302ba 100755 --- a/test_regress/t/t_reloop_offset.py +++ b/test_regress/t/t_reloop_offset.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_reloop_offset.v b/test_regress/t/t_reloop_offset.v index fff96064a..c043f44c8 100644 --- a/test_regress/t/t_reloop_offset.v +++ b/test_regress/t/t_reloop_offset.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: CC0-1.0 `define show(x) $display("oarray[%2d] is %2d", x, oarray[x]) diff --git a/test_regress/t/t_reloop_offset_lim_63.py b/test_regress/t/t_reloop_offset_lim_63.py index 9e9bd8b5f..f60eef341 100755 --- a/test_regress/t/t_reloop_offset_lim_63.py +++ b/test_regress/t/t_reloop_offset_lim_63.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_repeat.py b/test_regress/t/t_repeat.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_repeat.py +++ b/test_regress/t/t_repeat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_repeat.v b/test_regress/t/t_repeat.v index 3e557ee40..38445c644 100644 --- a/test_regress/t/t_repeat.v +++ b/test_regress/t/t_repeat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_resize_lvalue.py b/test_regress/t/t_resize_lvalue.py index b20365d31..66cb0a535 100755 --- a/test_regress/t/t_resize_lvalue.py +++ b/test_regress/t/t_resize_lvalue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_resize_lvalue.v b/test_regress/t/t_resize_lvalue.v index 6d7bf873d..c33049947 100644 --- a/test_regress/t/t_resize_lvalue.v +++ b/test_regress/t/t_resize_lvalue.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Alex Solomatnikov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Alex Solomatnikov // SPDX-License-Identifier: CC0-1.0 package x_pkg; diff --git a/test_regress/t/t_rnd.py b/test_regress/t/t_rnd.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_rnd.py +++ b/test_regress/t/t_rnd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_rnd.v b/test_regress/t/t_rnd.v index 3f097c571..09feede25 100644 --- a/test_regress/t/t_rnd.v +++ b/test_regress/t/t_rnd.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_runflag.py b/test_regress/t/t_runflag.py index 3504e8aca..074e097d3 100755 --- a/test_regress/t/t_runflag.py +++ b/test_regress/t/t_runflag.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_runflag.v b/test_regress/t/t_runflag.v index ff98975dc..115ceeccc 100644 --- a/test_regress/t/t_runflag.v +++ b/test_regress/t/t_runflag.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_runflag_bad.py b/test_regress/t/t_runflag_bad.py index 8a3c712a5..cb6f3f0e0 100755 --- a/test_regress/t/t_runflag_bad.py +++ b/test_regress/t/t_runflag_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_runflag_bad.v b/test_regress/t/t_runflag_bad.v index cfcf3ba54..52ef42d60 100644 --- a/test_regress/t/t_runflag_bad.v +++ b/test_regress/t/t_runflag_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_runflag_errorlimit_bad.py b/test_regress/t/t_runflag_errorlimit_bad.py index 2370a882b..f12c7227f 100755 --- a/test_regress/t/t_runflag_errorlimit_bad.py +++ b/test_regress/t/t_runflag_errorlimit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_runflag_errorlimit_bad.v b/test_regress/t/t_runflag_errorlimit_bad.v index 00ef993e9..3019a10d6 100644 --- a/test_regress/t/t_runflag_errorlimit_bad.v +++ b/test_regress/t/t_runflag_errorlimit_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_runflag_errorlimit_fatal_bad.py b/test_regress/t/t_runflag_errorlimit_fatal_bad.py index 2370a882b..f12c7227f 100755 --- a/test_regress/t/t_runflag_errorlimit_fatal_bad.py +++ b/test_regress/t/t_runflag_errorlimit_fatal_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_runflag_errorlimit_fatal_bad.v b/test_regress/t/t_runflag_errorlimit_fatal_bad.v index e4c546f64..3570c7f62 100644 --- a/test_regress/t/t_runflag_errorlimit_fatal_bad.v +++ b/test_regress/t/t_runflag_errorlimit_fatal_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_runflag_quiet.py b/test_regress/t/t_runflag_quiet.py index 34c826b21..0f1d64452 100755 --- a/test_regress/t/t_runflag_quiet.py +++ b/test_regress/t/t_runflag_quiet.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_runflag_quiet.v b/test_regress/t/t_runflag_quiet.v index 1c62e1b40..f968cd295 100644 --- a/test_regress/t/t_runflag_quiet.v +++ b/test_regress/t/t_runflag_quiet.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 timeunit 1us; diff --git a/test_regress/t/t_runflag_seed.py b/test_regress/t/t_runflag_seed.py index 836f602cd..8b90c3d9f 100755 --- a/test_regress/t/t_runflag_seed.py +++ b/test_regress/t/t_runflag_seed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -13,8 +13,8 @@ test.scenarios('vlt_all') test.compile() -test.execute(all_run_flags=["+verilator+seed+5 +SEED=fffffff4"]) +test.execute(all_run_flags=["+verilator+seed+5 +SEED=h2e564fe1"]) -test.execute(all_run_flags=["+verilator+seed+6 +SEED=fffffff2"]) +test.execute(all_run_flags=["+verilator+seed+6 +SEED=h3dca891b"]) test.passes() diff --git a/test_regress/t/t_runflag_seed.v b/test_regress/t/t_runflag_seed.v index 1e1892e56..5e52bf1ec 100644 --- a/test_regress/t/t_runflag_seed.v +++ b/test_regress/t/t_runflag_seed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop @@ -9,7 +9,7 @@ module t; initial begin - integer r = $random; + automatic integer r = $random; integer ex; if ($value$plusargs("SEED=%x", ex) !== 1) $stop; `checkh(r, ex); diff --git a/test_regress/t/t_runflag_uninit_bad.cpp b/test_regress/t/t_runflag_uninit_bad.cpp index 93b8eaf62..30b173758 100644 --- a/test_regress/t/t_runflag_uninit_bad.cpp +++ b/test_regress/t/t_runflag_uninit_bad.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_runflag_uninit_bad.py b/test_regress/t/t_runflag_uninit_bad.py index 54b3952a5..7604d8b42 100755 --- a/test_regress/t/t_runflag_uninit_bad.py +++ b/test_regress/t/t_runflag_uninit_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_runflag_uninit_bad.v b/test_regress/t/t_runflag_uninit_bad.v index 0f4e48ff9..fc082ba27 100644 --- a/test_regress/t/t_runflag_uninit_bad.v +++ b/test_regress/t/t_runflag_uninit_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_sampled_expr.py b/test_regress/t/t_sampled_expr.py index 2c4ffdce2..690ae1cbf 100755 --- a/test_regress/t/t_sampled_expr.py +++ b/test_regress/t/t_sampled_expr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sampled_expr.v b/test_regress/t/t_sampled_expr.v index 9447b48f8..cab5cf066 100644 --- a/test_regress/t/t_sampled_expr.v +++ b/test_regress/t/t_sampled_expr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_sampled_expr_unsup.py b/test_regress/t/t_sampled_expr_unsup.py index 09fb4cfa3..ab5aa5457 100755 --- a/test_regress/t/t_sampled_expr_unsup.py +++ b/test_regress/t/t_sampled_expr_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sampled_expr_unsup.v b/test_regress/t/t_sampled_expr_unsup.v index b46d74bf1..b9941b3ae 100644 --- a/test_regress/t/t_sampled_expr_unsup.v +++ b/test_regress/t/t_sampled_expr_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_sampled_sensitivity.out b/test_regress/t/t_sampled_sensitivity.out new file mode 100644 index 000000000..e35a70b97 --- /dev/null +++ b/test_regress/t/t_sampled_sensitivity.out @@ -0,0 +1,6 @@ +%Error-UNSUPPORTED: t/t_sampled_sensitivity.v:14:20: Unsupported: $sampled inside sensitivity list + : ... note: In instance 't' + 14 | always @(posedge $sampled(clk)) begin + | ^~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_sampled_sensitivity.py b/test_regress/t/t_sampled_sensitivity.py new file mode 100755 index 000000000..3160d0589 --- /dev/null +++ b/test_regress/t/t_sampled_sensitivity.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_sampled_sensitivity.v b/test_regress/t/t_sampled_sensitivity.v new file mode 100644 index 000000000..bff4af5a4 --- /dev/null +++ b/test_regress/t/t_sampled_sensitivity.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t ( /*AUTOARG*/ + // Inputs + clk +); + + input clk; + + always @(posedge $sampled(clk)) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_sarif.py b/test_regress/t/t_sarif.py index b62cbf5c1..cda774dd6 100755 --- a/test_regress/t/t_sarif.py +++ b/test_regress/t/t_sarif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sarif.v b/test_regress/t/t_sarif.v index f98e3d12b..c69fa047e 100644 --- a/test_regress/t/t_sarif.v +++ b/test_regress/t/t_sarif.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_sarif_output.py b/test_regress/t/t_sarif_output.py index c1db584cd..5425fe85b 100755 --- a/test_regress/t/t_sarif_output.py +++ b/test_regress/t/t_sarif_output.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_savable.py b/test_regress/t/t_savable.py index 289d8f855..333b3e2a0 100755 --- a/test_regress/t/t_savable.py +++ b/test_regress/t/t_savable.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_savable.v b/test_regress/t/t_savable.v index c5e2cac1d..2aca73c43 100644 --- a/test_regress/t/t_savable.v +++ b/test_regress/t/t_savable.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_savable_class_bad.py b/test_regress/t/t_savable_class_bad.py index 9ac0fdbc6..032ac396f 100755 --- a/test_regress/t/t_savable_class_bad.py +++ b/test_regress/t/t_savable_class_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_savable_class_bad.v b/test_regress/t/t_savable_class_bad.v index ef64829b3..49b5f52f3 100644 --- a/test_regress/t/t_savable_class_bad.v +++ b/test_regress/t/t_savable_class_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_savable_coverage_bad.py b/test_regress/t/t_savable_coverage_bad.py index 15eec4d60..266677c9a 100755 --- a/test_regress/t/t_savable_coverage_bad.py +++ b/test_regress/t/t_savable_coverage_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_savable_coverage_bad.v b/test_regress/t/t_savable_coverage_bad.v index 0f1777e05..13d882f59 100644 --- a/test_regress/t/t_savable_coverage_bad.v +++ b/test_regress/t/t_savable_coverage_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_savable_format1_bad.py b/test_regress/t/t_savable_format1_bad.py index 6965c4a35..9da748014 100755 --- a/test_regress/t/t_savable_format1_bad.py +++ b/test_regress/t/t_savable_format1_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_savable_format2_bad.py b/test_regress/t/t_savable_format2_bad.py index 8940d15ca..e3db8e74c 100755 --- a/test_regress/t/t_savable_format2_bad.py +++ b/test_regress/t/t_savable_format2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_savable_format3_bad.py b/test_regress/t/t_savable_format3_bad.py index cadd098c2..7fd834576 100755 --- a/test_regress/t/t_savable_format3_bad.py +++ b/test_regress/t/t_savable_format3_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_savable_open_bad.py b/test_regress/t/t_savable_open_bad.py index b7a64c02d..ccf4d977a 100755 --- a/test_regress/t/t_savable_open_bad.py +++ b/test_regress/t/t_savable_open_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_savable_open_bad2.cpp b/test_regress/t/t_savable_open_bad2.cpp index 8086da829..1aa27329c 100644 --- a/test_regress/t/t_savable_open_bad2.cpp +++ b/test_regress/t/t_savable_open_bad2.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_savable_open_bad2.py b/test_regress/t/t_savable_open_bad2.py index 3a759f54f..2cfecc0b8 100755 --- a/test_regress/t/t_savable_open_bad2.py +++ b/test_regress/t/t_savable_open_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_savable_open_bad2.v b/test_regress/t/t_savable_open_bad2.v index c473152e5..4eb773175 100644 --- a/test_regress/t/t_savable_open_bad2.v +++ b/test_regress/t/t_savable_open_bad2.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_savable_timing_bad.py b/test_regress/t/t_savable_timing_bad.py index 31065f1eb..ec51a6a9f 100755 --- a/test_regress/t/t_savable_timing_bad.py +++ b/test_regress/t/t_savable_timing_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sc_names.cpp b/test_regress/t/t_sc_names.cpp index 3d7b6cd7f..3f0ee6b90 100644 --- a/test_regress/t/t_sc_names.cpp +++ b/test_regress/t/t_sc_names.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Edgar E. Iglesias. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2020 Edgar E. Iglesias // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_sc_names.py b/test_regress/t/t_sc_names.py index c891a1ee0..fd4e8b8cf 100755 --- a/test_regress/t/t_sc_names.py +++ b/test_regress/t/t_sc_names.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sc_names.v b/test_regress/t/t_sc_names.v index 13bcd4371..67372319d 100644 --- a/test_regress/t/t_sc_names.v +++ b/test_regress/t/t_sc_names.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Edgar E. Iglesias. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2020 Edgar E. Iglesias // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_sc_vl_assign_sbw.cpp b/test_regress/t/t_sc_vl_assign_sbw.cpp index 32f0542f0..acc9afcb8 100644 --- a/test_regress/t/t_sc_vl_assign_sbw.cpp +++ b/test_regress/t/t_sc_vl_assign_sbw.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_sc_vl_assign_sbw.py b/test_regress/t/t_sc_vl_assign_sbw.py index 1a06f784b..f9993ae4a 100755 --- a/test_regress/t/t_sc_vl_assign_sbw.py +++ b/test_regress/t/t_sc_vl_assign_sbw.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sc_vl_assign_sbw.v b/test_regress/t/t_sc_vl_assign_sbw.v index 348ea05e5..7803f8697 100644 --- a/test_regress/t/t_sc_vl_assign_sbw.v +++ b/test_regress/t/t_sc_vl_assign_sbw.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Antmicro. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t( diff --git a/test_regress/t/t_scheduling_0.py b/test_regress/t/t_scheduling_0.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_scheduling_0.py +++ b/test_regress/t/t_scheduling_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_scheduling_0.v b/test_regress/t/t_scheduling_0.v index aa54a8aaa..98755dd14 100644 --- a/test_regress/t/t_scheduling_0.v +++ b/test_regress/t/t_scheduling_0.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR diff --git a/test_regress/t/t_scheduling_1.py b/test_regress/t/t_scheduling_1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_scheduling_1.py +++ b/test_regress/t/t_scheduling_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_scheduling_1.v b/test_regress/t/t_scheduling_1.v index 510754caa..73dce246a 100644 --- a/test_regress/t/t_scheduling_1.v +++ b/test_regress/t/t_scheduling_1.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top( diff --git a/test_regress/t/t_scheduling_2.py b/test_regress/t/t_scheduling_2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_scheduling_2.py +++ b/test_regress/t/t_scheduling_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_scheduling_2.v b/test_regress/t/t_scheduling_2.v index 9ed55461c..a42ef91f5 100644 --- a/test_regress/t/t_scheduling_2.v +++ b/test_regress/t/t_scheduling_2.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR diff --git a/test_regress/t/t_scheduling_3.py b/test_regress/t/t_scheduling_3.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_scheduling_3.py +++ b/test_regress/t/t_scheduling_3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_scheduling_3.v b/test_regress/t/t_scheduling_3.v index ad12dc8ab..13776b13c 100644 --- a/test_regress/t/t_scheduling_3.v +++ b/test_regress/t/t_scheduling_3.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR diff --git a/test_regress/t/t_scheduling_4.py b/test_regress/t/t_scheduling_4.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_scheduling_4.py +++ b/test_regress/t/t_scheduling_4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_scheduling_4.v b/test_regress/t/t_scheduling_4.v index 6b77f6bb9..e3518c79b 100644 --- a/test_regress/t/t_scheduling_4.v +++ b/test_regress/t/t_scheduling_4.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR diff --git a/test_regress/t/t_scheduling_5.py b/test_regress/t/t_scheduling_5.py index b80b4f79f..529492841 100755 --- a/test_regress/t/t_scheduling_5.py +++ b/test_regress/t/t_scheduling_5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_scheduling_5.v b/test_regress/t/t_scheduling_5.v index 6ca049d70..690ce25dd 100644 --- a/test_regress/t/t_scheduling_5.v +++ b/test_regress/t/t_scheduling_5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_scheduling_6.v b/test_regress/t/t_scheduling_6.v index cfb4f52e4..242241c85 100644 --- a/test_regress/t/t_scheduling_6.v +++ b/test_regress/t/t_scheduling_6.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2022 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module top( diff --git a/test_regress/t/t_scheduling_7.py b/test_regress/t/t_scheduling_7.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_scheduling_7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_7.v b/test_regress/t/t_scheduling_7.v new file mode 100644 index 000000000..e9487aabc --- /dev/null +++ b/test_regress/t/t_scheduling_7.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' +// +// Alias type check error test. +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +static int counter = 0; + +task wait_for_nba_region; + static int nba; + static int next_nba; + next_nba++; + nba <= next_nba; + @(nba); + counter++; +endtask + +class Foo; + task run_phases(); + repeat (2) begin + fork + if ($c(1)) wait_for_nba_region(); + join_none + end + endtask +endclass + +module top; + initial begin + static Foo p = new; + p.run_phases(); + #1; + if (counter != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_scheduling_beforeTrig_life_opt.py b/test_regress/t/t_scheduling_beforeTrig_life_opt.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_scheduling_beforeTrig_life_opt.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_beforeTrig_life_opt.v b/test_regress/t/t_scheduling_beforeTrig_life_opt.v new file mode 100644 index 000000000..efab98a8c --- /dev/null +++ b/test_regress/t/t_scheduling_beforeTrig_life_opt.v @@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' +// +// Alias type check error test. +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module s ( + input clk, + output wire rdy, + input reset +); + parameter ss = 5; + localparam w = 1 << ss; + reg [ss-1:0] bitl; + assign rdy = bitl[ss-1]; + (* ivl_synthesis_on *) + always @(posedge clk or posedge reset) begin + if (!reset) begin + bitl <= bitl - 1; + end + end +endmodule +module t; + parameter ss = 5; + parameter w = 1 << ss; + reg clk, reset; + wire done; + s dut ( + .clk(clk), + .rdy(done), + .reset(reset) + ); + always #5 clk = !clk; + task reset_dut; + reset = 1; + @(posedge clk); + #1 reset = 0; + endtask + task run_dut; + while (done == 0) begin + @(posedge clk); + end + endtask + initial begin + clk = 0; + reset_dut; + run_dut; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_scheduling_different_edges.py b/test_regress/t/t_scheduling_different_edges.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_scheduling_different_edges.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_scheduling_different_edges.v b/test_regress/t/t_scheduling_different_edges.v new file mode 100644 index 000000000..68873fe1b --- /dev/null +++ b/test_regress/t/t_scheduling_different_edges.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module x; + bit val = 0; + bit ok = 0; + + initial + #1 begin + val = 1; + @(val); + $write("*-* All Finished *-*\n"); + $finish; + end + + initial + @(posedge val) begin + val = 0; + ok = 1; + @(edge val); + $stop; + end + initial #10 $stop; +endmodule diff --git a/test_regress/t/t_scheduling_initial_event.py b/test_regress/t/t_scheduling_initial_event.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_scheduling_initial_event.py +++ b/test_regress/t/t_scheduling_initial_event.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_scheduling_initial_event.v b/test_regress/t/t_scheduling_initial_event.v index c3e2ee377..741775cbd 100644 --- a/test_regress/t/t_scheduling_initial_event.v +++ b/test_regress/t/t_scheduling_initial_event.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_scheduling_many_clocks.py b/test_regress/t/t_scheduling_many_clocks.py index f303f757c..838900266 100755 --- a/test_regress/t/t_scheduling_many_clocks.py +++ b/test_regress/t/t_scheduling_many_clocks.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_scheduling_many_clocks.v b/test_regress/t/t_scheduling_many_clocks.v index 009a8eace..fef5142c1 100644 --- a/test_regress/t/t_scheduling_many_clocks.v +++ b/test_regress/t/t_scheduling_many_clocks.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_scheduling_zero_delay.out b/test_regress/t/t_scheduling_zero_delay.out new file mode 100644 index 000000000..1e7bd02af --- /dev/null +++ b/test_regress/t/t_scheduling_zero_delay.out @@ -0,0 +1,22 @@ + 0 Waiting for 'a' + 5 Waiting for 'a' + 5 a= 1 b=11 +15 Waiting for 'a' +15 a= 2 b=12 +25 Waiting for 'a' +25 a= 3 b=13 +35 Waiting for 'a' +35 a= 4 b=14 +45 Waiting for 'a' +45 a= 5 b=15 +55 Waiting for 'a' +55 a= 6 b=16 +65 Waiting for 'a' +65 a= 7 b=17 +75 Waiting for 'a' +75 a= 8 b=18 +85 Waiting for 'a' +85 a= 9 b=19 +95 Waiting for 'a' +95 a=10 b=20 +*-* All Finished *-* diff --git a/test_regress/t/t_scheduling_zero_delay.py b/test_regress/t/t_scheduling_zero_delay.py new file mode 100755 index 000000000..1eaed2d2b --- /dev/null +++ b/test_regress/t/t_scheduling_zero_delay.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary", "--stats"]) + +test.execute(expect_filename=test.golden_filename) + +test.file_grep(test.stats, r'Timing, known #0 delays\s+(\d+)', 1) +test.file_grep(test.stats, r'Timing, known #const delays\s+(\d+)', 2) +test.file_grep(test.stats, r'Timing, unknown #variable delays\s+(\d+)', 0) + +test.passes() diff --git a/test_regress/t/t_scheduling_zero_delay.v b/test_regress/t/t_scheduling_zero_delay.v new file mode 100644 index 000000000..203c2797a --- /dev/null +++ b/test_regress/t/t_scheduling_zero_delay.v @@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define check(got,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: time=%t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0) +// verilog_format: on + +module top; + + logic clk = 0; + always #5 clk = ~clk; + + int a = 0; + int b; + + always begin + $display("%2t Waiting for 'a'", $time); + @a; + b = a + 10; + end + + always @(posedge clk) begin + ++a; + end + + always @(posedge clk) begin + #0; + $display("%2t a=%2d b=%2d", $time, a, b); + `check(b, a + 10); + end + + initial begin + #99; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_scope_cxx_equal_to.py b/test_regress/t/t_scope_cxx_equal_to.py index 9df4d731c..670cf16ac 100755 --- a/test_regress/t/t_scope_cxx_equal_to.py +++ b/test_regress/t/t_scope_cxx_equal_to.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_scope_cxx_equal_to.v b/test_regress/t/t_scope_cxx_equal_to.v index 09dd11f82..1c3537a89 100644 --- a/test_regress/t/t_scope_cxx_equal_to.v +++ b/test_regress/t/t_scope_cxx_equal_to.v @@ -9,8 +9,8 @@ // AstVarScope was missing an appropriate same method and is tickled by the LLVM // libcxx library. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by John Wehle. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 John Wehle // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_scope_map.cpp b/test_regress/t/t_scope_map.cpp index df1a12dd8..9bab16e03 100644 --- a/test_regress/t/t_scope_map.cpp +++ b/test_regress/t/t_scope_map.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_scope_map.py b/test_regress/t/t_scope_map.py index 202e6a897..6bff8cd57 100755 --- a/test_regress/t/t_scope_map.py +++ b/test_regress/t/t_scope_map.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_scope_map.v b/test_regress/t/t_scope_map.v index 1ba241d96..0080e5a33 100644 --- a/test_regress/t/t_scope_map.v +++ b/test_regress/t/t_scope_map.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Test symbol table scope map and general public // signal reflection // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_sdf_annotate_unsup.py b/test_regress/t/t_sdf_annotate_unsup.py index 272fc1280..1952b53a1 100755 --- a/test_regress/t/t_sdf_annotate_unsup.py +++ b/test_regress/t/t_sdf_annotate_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sdf_annotate_unsup.v b/test_regress/t/t_sdf_annotate_unsup.v index dcad1c56c..37bbf0d48 100644 --- a/test_regress/t/t_sdf_annotate_unsup.v +++ b/test_regress/t/t_sdf_annotate_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias' // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_select_2d.py b/test_regress/t/t_select_2d.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_2d.py +++ b/test_regress/t/t_select_2d.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_2d.v b/test_regress/t/t_select_2d.v index 4de9b5f01..d57b66623 100644 --- a/test_regress/t/t_select_2d.v +++ b/test_regress/t/t_select_2d.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_select_ascending.py b/test_regress/t/t_select_ascending.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_ascending.py +++ b/test_regress/t/t_select_ascending.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_ascending.v b/test_regress/t/t_select_ascending.v index 0f37470d9..a933a8187 100644 --- a/test_regress/t/t_select_ascending.v +++ b/test_regress/t/t_select_ascending.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_bad_msb.py b/test_regress/t/t_select_bad_msb.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_select_bad_msb.py +++ b/test_regress/t/t_select_bad_msb.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bad_msb.v b/test_regress/t/t_select_bad_msb.v index cbcd8f2c2..33fffbe54 100644 --- a/test_regress/t/t_select_bad_msb.v +++ b/test_regress/t/t_select_bad_msb.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_select_bad_range.py b/test_regress/t/t_select_bad_range.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_select_bad_range.py +++ b/test_regress/t/t_select_bad_range.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bad_range.v b/test_regress/t/t_select_bad_range.v index deb03f130..f862e5a64 100644 --- a/test_regress/t/t_select_bad_range.v +++ b/test_regress/t/t_select_bad_range.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_select_bad_range2.py b/test_regress/t/t_select_bad_range2.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_select_bad_range2.py +++ b/test_regress/t/t_select_bad_range2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bad_range2.v b/test_regress/t/t_select_bad_range2.v index 0efb7ce2d..455988cdf 100644 --- a/test_regress/t/t_select_bad_range2.v +++ b/test_regress/t/t_select_bad_range2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_bad_range3.py b/test_regress/t/t_select_bad_range3.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_select_bad_range3.py +++ b/test_regress/t/t_select_bad_range3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bad_range3.v b/test_regress/t/t_select_bad_range3.v index 3a788636e..0933370d4 100644 --- a/test_regress/t/t_select_bad_range3.v +++ b/test_regress/t/t_select_bad_range3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_bad_range4.py b/test_regress/t/t_select_bad_range4.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_select_bad_range4.py +++ b/test_regress/t/t_select_bad_range4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bad_range4.v b/test_regress/t/t_select_bad_range4.v index e845c9b0d..6429fc802 100644 --- a/test_regress/t/t_select_bad_range4.v +++ b/test_regress/t/t_select_bad_range4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_bad_range5.py b/test_regress/t/t_select_bad_range5.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_select_bad_range5.py +++ b/test_regress/t/t_select_bad_range5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bad_range5.v b/test_regress/t/t_select_bad_range5.v index 77e6577e6..1ea46eb6e 100644 --- a/test_regress/t/t_select_bad_range5.v +++ b/test_regress/t/t_select_bad_range5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_bad_range6.py b/test_regress/t/t_select_bad_range6.py index a6f7c2c22..c644d834e 100755 --- a/test_regress/t/t_select_bad_range6.py +++ b/test_regress/t/t_select_bad_range6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bad_range6.v b/test_regress/t/t_select_bad_range6.v index 3f632a7dc..3ddf50644 100644 --- a/test_regress/t/t_select_bad_range6.v +++ b/test_regress/t/t_select_bad_range6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_select_bad_tri.py b/test_regress/t/t_select_bad_tri.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_select_bad_tri.py +++ b/test_regress/t/t_select_bad_tri.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bad_tri.v b/test_regress/t/t_select_bad_tri.v index 5a0c02f3f..4ef3c2873 100644 --- a/test_regress/t/t_select_bad_tri.v +++ b/test_regress/t/t_select_bad_tri.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_select_bad_width0.out b/test_regress/t/t_select_bad_width0.out index 0e761e160..bb6fd52bb 100644 --- a/test_regress/t/t_select_bad_width0.out +++ b/test_regress/t/t_select_bad_width0.out @@ -1,12 +1,12 @@ -%Error: t/t_select_bad_width0.v:15:21: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) +%Error: t/t_select_bad_width0.v:15:31: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) : ... note: In instance 't' - 15 | int part = val[left +: ZERO]; - | ^ + 15 | automatic int part = val[left +: ZERO]; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-WIDTHEXPAND: t/t_select_bad_width0.v:15:21: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. +%Warning-WIDTHEXPAND: t/t_select_bad_width0.v:15:31: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits. : ... note: In instance 't' - 15 | int part = val[left +: ZERO]; - | ^ + 15 | automatic int part = val[left +: ZERO]; + | ^ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: t/t_select_bad_width0.v:17:17: Width of bit extract must be positive (IEEE 1800-2023 11.5.1) diff --git a/test_regress/t/t_select_bad_width0.py b/test_regress/t/t_select_bad_width0.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_select_bad_width0.py +++ b/test_regress/t/t_select_bad_width0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bad_width0.v b/test_regress/t/t_select_bad_width0.v index 0acd395a3..ec96804a7 100644 --- a/test_regress/t/t_select_bad_width0.v +++ b/test_regress/t/t_select_bad_width0.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; @@ -9,10 +9,10 @@ module t; parameter int ZERO = 0; initial begin - bit [31:0] val = '1; - int left = 4; + automatic bit [31:0] val = '1; + automatic int left = 4; - int part = val[left +: ZERO]; + automatic int part = val[left +: ZERO]; $display(part); part = val[left -: ZERO]; $display(part); diff --git a/test_regress/t/t_select_bound1.py b/test_regress/t/t_select_bound1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_bound1.py +++ b/test_regress/t/t_select_bound1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bound1.v b/test_regress/t/t_select_bound1.v index cd5764bd9..a47791fc5 100644 --- a/test_regress/t/t_select_bound1.v +++ b/test_regress/t/t_select_bound1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug823 diff --git a/test_regress/t/t_select_bound2.py b/test_regress/t/t_select_bound2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_bound2.py +++ b/test_regress/t/t_select_bound2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bound2.v b/test_regress/t/t_select_bound2.v index 85771588a..15ceed670 100644 --- a/test_regress/t/t_select_bound2.v +++ b/test_regress/t/t_select_bound2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug823 diff --git a/test_regress/t/t_select_bound3.py b/test_regress/t/t_select_bound3.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_select_bound3.py +++ b/test_regress/t/t_select_bound3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_bound3.v b/test_regress/t/t_select_bound3.v index 19f6ac8f7..6cb8f05ad 100644 --- a/test_regress/t/t_select_bound3.v +++ b/test_regress/t/t_select_bound3.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2025 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 class cls; diff --git a/test_regress/t/t_select_c.py b/test_regress/t/t_select_c.py index 8a08e98cd..d41ed916e 100755 --- a/test_regress/t/t_select_c.py +++ b/test_regress/t/t_select_c.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_c.v b/test_regress/t/t_select_c.v index c4ae30a64..225a2c980 100644 --- a/test_regress/t/t_select_c.v +++ b/test_regress/t/t_select_c.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_select_crazy.py b/test_regress/t/t_select_crazy.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_crazy.py +++ b/test_regress/t/t_select_crazy.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_crazy.v b/test_regress/t/t_select_crazy.v index ff33ddd6e..3206c006a 100644 --- a/test_regress/t/t_select_crazy.v +++ b/test_regress/t/t_select_crazy.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Dotted reference that uses another dotted reference // as the select expression // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 interface foo_intf; diff --git a/test_regress/t/t_select_index.py b/test_regress/t/t_select_index.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_index.py +++ b/test_regress/t/t_select_index.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_index.v b/test_regress/t/t_select_index.v index 8e58bc6f9..02ea629ed 100644 --- a/test_regress/t/t_select_index.v +++ b/test_regress/t/t_select_index.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_select_index2.py b/test_regress/t/t_select_index2.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_select_index2.py +++ b/test_regress/t/t_select_index2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_index2.v b/test_regress/t/t_select_index2.v index 6255a2e65..16c297444 100644 --- a/test_regress/t/t_select_index2.v +++ b/test_regress/t/t_select_index2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_select_lhs_oob.py b/test_regress/t/t_select_lhs_oob.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_lhs_oob.py +++ b/test_regress/t/t_select_lhs_oob.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_lhs_oob.v b/test_regress/t/t_select_lhs_oob.v index 948969667..6dbdde4dd 100644 --- a/test_regress/t/t_select_lhs_oob.v +++ b/test_regress/t/t_select_lhs_oob.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_lhs_oob2.py b/test_regress/t/t_select_lhs_oob2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_lhs_oob2.py +++ b/test_regress/t/t_select_lhs_oob2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_lhs_oob2.v b/test_regress/t/t_select_lhs_oob2.v index 597e629a4..2fc2f1093 100644 --- a/test_regress/t/t_select_lhs_oob2.v +++ b/test_regress/t/t_select_lhs_oob2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_little.py b/test_regress/t/t_select_little.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_little.py +++ b/test_regress/t/t_select_little.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_little.v b/test_regress/t/t_select_little.v index e8c1c191b..993f001a7 100644 --- a/test_regress/t/t_select_little.v +++ b/test_regress/t/t_select_little.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_little_pack.py b/test_regress/t/t_select_little_pack.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_little_pack.py +++ b/test_regress/t/t_select_little_pack.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_little_pack.v b/test_regress/t/t_select_little_pack.v index b2bec2b51..94b876604 100644 --- a/test_regress/t/t_select_little_pack.v +++ b/test_regress/t/t_select_little_pack.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_select_loop.py b/test_regress/t/t_select_loop.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_loop.py +++ b/test_regress/t/t_select_loop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_loop.v b/test_regress/t/t_select_loop.v index ce8084e33..c04dddbf1 100644 --- a/test_regress/t/t_select_loop.v +++ b/test_regress/t/t_select_loop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_mul_extend.py b/test_regress/t/t_select_mul_extend.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_mul_extend.py +++ b/test_regress/t/t_select_mul_extend.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_mul_extend.v b/test_regress/t/t_select_mul_extend.v index dc9d2a1d4..ebb042404 100644 --- a/test_regress/t/t_select_mul_extend.v +++ b/test_regress/t/t_select_mul_extend.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Varun Koyyalagunta. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_select_negative.py b/test_regress/t/t_select_negative.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_negative.py +++ b/test_regress/t/t_select_negative.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_negative.v b/test_regress/t/t_select_negative.v index 6bfad9f9e..3ca4c5617 100644 --- a/test_regress/t/t_select_negative.v +++ b/test_regress/t/t_select_negative.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_out_of_range.py b/test_regress/t/t_select_out_of_range.py index 9fff37b43..48ebaa8cf 100755 --- a/test_regress/t/t_select_out_of_range.py +++ b/test_regress/t/t_select_out_of_range.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_out_of_range.v b/test_regress/t/t_select_out_of_range.v index 7ecbbe6fa..25a7ec6c0 100644 --- a/test_regress/t/t_select_out_of_range.v +++ b/test_regress/t/t_select_out_of_range.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module serial_adder( diff --git a/test_regress/t/t_select_param.py b/test_regress/t/t_select_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_param.py +++ b/test_regress/t/t_select_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_param.v b/test_regress/t/t_select_param.v index a8830d6b4..b849d1ae7 100644 --- a/test_regress/t/t_select_param.v +++ b/test_regress/t/t_select_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_select_plus.py b/test_regress/t/t_select_plus.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_plus.py +++ b/test_regress/t/t_select_plus.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_plus.v b/test_regress/t/t_select_plus.v index 9604c93cd..61c061f0b 100644 --- a/test_regress/t/t_select_plus.v +++ b/test_regress/t/t_select_plus.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_plus_mul_pow2.py b/test_regress/t/t_select_plus_mul_pow2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_plus_mul_pow2.py +++ b/test_regress/t/t_select_plus_mul_pow2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_plus_mul_pow2.v b/test_regress/t/t_select_plus_mul_pow2.v index f010ec7af..c04f7303a 100644 --- a/test_regress/t/t_select_plus_mul_pow2.v +++ b/test_regress/t/t_select_plus_mul_pow2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Conor McCullough. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Conor McCullough // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_plusloop.py b/test_regress/t/t_select_plusloop.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_plusloop.py +++ b/test_regress/t/t_select_plusloop.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_plusloop.v b/test_regress/t/t_select_plusloop.v index a5cbbe063..16635a82d 100644 --- a/test_regress/t/t_select_plusloop.v +++ b/test_regress/t/t_select_plusloop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_runtime_range.py b/test_regress/t/t_select_runtime_range.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_runtime_range.py +++ b/test_regress/t/t_select_runtime_range.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_runtime_range.v b/test_regress/t/t_select_runtime_range.v index 71d06a8f7..07a7a73a2 100644 --- a/test_regress/t/t_select_runtime_range.v +++ b/test_regress/t/t_select_runtime_range.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_select_set.py b/test_regress/t/t_select_set.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_select_set.py +++ b/test_regress/t/t_select_set.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_set.v b/test_regress/t/t_select_set.v index ed37bc638..0523790f3 100644 --- a/test_regress/t/t_select_set.v +++ b/test_regress/t/t_select_set.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_select_sideeffect.py b/test_regress/t/t_select_sideeffect.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_select_sideeffect.py +++ b/test_regress/t/t_select_sideeffect.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_sideeffect.v b/test_regress/t/t_select_sideeffect.v index 37a57ae3a..b98a3e21f 100644 --- a/test_regress/t/t_select_sideeffect.v +++ b/test_regress/t/t_select_sideeffect.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_select_width.py b/test_regress/t/t_select_width.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_select_width.py +++ b/test_regress/t/t_select_width.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_select_width.v b/test_regress/t/t_select_width.v index fb997b998..8bf086724 100644 --- a/test_regress/t/t_select_width.v +++ b/test_regress/t/t_select_width.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_selextract_in_paramextends.py b/test_regress/t/t_selextract_in_paramextends.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_selextract_in_paramextends.py +++ b/test_regress/t/t_selextract_in_paramextends.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_selextract_in_paramextends.v b/test_regress/t/t_selextract_in_paramextends.v index f371482d6..a882aadb5 100644 --- a/test_regress/t/t_selextract_in_paramextends.v +++ b/test_regress/t/t_selextract_in_paramextends.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef class Foo; @@ -29,7 +29,7 @@ endclass module test(); initial begin - Foo foo = new; + automatic Foo foo = new; for (int i = 0; i < 10; i++) begin logic [3:0] v; diff --git a/test_regress/t/t_semaphore.py b/test_regress/t/t_semaphore.py index b2249f588..72b5f8d81 100755 --- a/test_regress/t/t_semaphore.py +++ b/test_regress/t/t_semaphore.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_semaphore.v b/test_regress/t/t_semaphore.v index 4c271bf59..283b2f7a7 100644 --- a/test_regress/t/t_semaphore.v +++ b/test_regress/t/t_semaphore.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: diff --git a/test_regress/t/t_semaphore_always.py b/test_regress/t/t_semaphore_always.py index 34b0247e9..c1140f359 100755 --- a/test_regress/t/t_semaphore_always.py +++ b/test_regress/t/t_semaphore_always.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_semaphore_always.v b/test_regress/t/t_semaphore_always.v index ddfc9b568..4de6f7079 100644 --- a/test_regress/t/t_semaphore_always.v +++ b/test_regress/t/t_semaphore_always.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_semaphore_bad.py b/test_regress/t/t_semaphore_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_semaphore_bad.py +++ b/test_regress/t/t_semaphore_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_semaphore_bad.v b/test_regress/t/t_semaphore_bad.v index e3d2c8974..2e9dc917b 100644 --- a/test_regress/t/t_semaphore_bad.v +++ b/test_regress/t/t_semaphore_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_semaphore_class.py b/test_regress/t/t_semaphore_class.py index 619878281..e6fe26a20 100755 --- a/test_regress/t/t_semaphore_class.py +++ b/test_regress/t/t_semaphore_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_semaphore_class.v b/test_regress/t/t_semaphore_class.v index 9460c6cf4..c07e58476 100644 --- a/test_regress/t/t_semaphore_class.v +++ b/test_regress/t/t_semaphore_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class semaphore_cls; diff --git a/test_regress/t/t_semaphore_class_nested.py b/test_regress/t/t_semaphore_class_nested.py index 619878281..e6fe26a20 100755 --- a/test_regress/t/t_semaphore_class_nested.py +++ b/test_regress/t/t_semaphore_class_nested.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_semaphore_class_nested.v b/test_regress/t/t_semaphore_class_nested.v index c18f65b45..2e2c0d86a 100644 --- a/test_regress/t/t_semaphore_class_nested.v +++ b/test_regress/t/t_semaphore_class_nested.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class semaphore_cls; diff --git a/test_regress/t/t_semaphore_concurrent.py b/test_regress/t/t_semaphore_concurrent.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_semaphore_concurrent.py +++ b/test_regress/t/t_semaphore_concurrent.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_semaphore_concurrent.v b/test_regress/t/t_semaphore_concurrent.v index 7062a3c72..58186867e 100644 --- a/test_regress/t/t_semaphore_concurrent.v +++ b/test_regress/t/t_semaphore_concurrent.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Liam Braun. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Liam Braun // SPDX-License-Identifier: CC0-1.0 module t(); diff --git a/test_regress/t/t_semaphore_std.py b/test_regress/t/t_semaphore_std.py index fa28f1d2d..f4ed98c34 100755 --- a/test_regress/t/t_semaphore_std.py +++ b/test_regress/t/t_semaphore_std.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sequence_first_match_unsup.out b/test_regress/t/t_sequence_first_match_unsup.out index 2edc27797..1ccf94aca 100644 --- a/test_regress/t/t_sequence_first_match_unsup.out +++ b/test_regress/t/t_sequence_first_match_unsup.out @@ -1,20 +1,20 @@ -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:47:40: Unsupported: or (in sequence expression) - 47 | initial p0: assert property ((##1 1) or (##2 1) |-> x==1); +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:50:40: Unsupported: or (in sequence expression) + 50 | initial p0: assert property ((##1 1) or (##2 1) |-> x==1); | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:50:52: Unsupported: or (in sequence expression) - 50 | initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:53:52: Unsupported: or (in sequence expression) + 53 | initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); | ^~ -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:50:32: Unsupported: first_match (in sequence expression) - 50 | initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:53:32: Unsupported: first_match (in sequence expression) + 53 | initial p1: assert property (first_match((##1 1) or (##2 1)) |-> x==1); | ^~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:53:34: Unsupported: or (in sequence expression) - 53 | initial p2: assert property (1 or ##1 1 |-> x==0); +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:56:34: Unsupported: or (in sequence expression) + 56 | initial p2: assert property (1 or ##1 1 |-> x==0); | ^~ -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:56:46: Unsupported: or (in sequence expression) - 56 | initial p3: assert property (first_match(1 or ##1 1) |-> x==0); +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:59:46: Unsupported: or (in sequence expression) + 59 | initial p3: assert property (first_match(1 or ##1 1) |-> x==0); | ^~ -%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:56:32: Unsupported: first_match (in sequence expression) - 56 | initial p3: assert property (first_match(1 or ##1 1) |-> x==0); +%Error-UNSUPPORTED: t/t_sequence_first_match_unsup.v:59:32: Unsupported: first_match (in sequence expression) + 59 | initial p3: assert property (first_match(1 or ##1 1) |-> x==0); | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_sequence_first_match_unsup.py b/test_regress/t/t_sequence_first_match_unsup.py index 26823c39a..235ad76f1 100755 --- a/test_regress/t/t_sequence_first_match_unsup.py +++ b/test_regress/t/t_sequence_first_match_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sequence_first_match_unsup.v b/test_regress/t/t_sequence_first_match_unsup.v index e0dd187cd..5658fc05a 100644 --- a/test_regress/t/t_sequence_first_match_unsup.v +++ b/test_regress/t/t_sequence_first_match_unsup.v @@ -1,3 +1,6 @@ +// SPDX-FileCopyrightText: 2001-2020 Daniel Kroening, Edmund Clarke +// SPDX-License-Identifier: BSD-3-Clause +// // (C) 2001-2020, Daniel Kroening, Edmund Clarke, // Computer Science Department, University of Oxford // Computer Science Department, Carnegie Mellon University diff --git a/test_regress/t/t_sequence_ref_unsup.py b/test_regress/t/t_sequence_ref_unsup.py index af14b700f..695572bb1 100755 --- a/test_regress/t/t_sequence_ref_unsup.py +++ b/test_regress/t/t_sequence_ref_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sequence_ref_unsup.v b/test_regress/t/t_sequence_ref_unsup.v index 32b86a3d5..21b512d81 100644 --- a/test_regress/t/t_sequence_ref_unsup.v +++ b/test_regress/t/t_sequence_ref_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sequence_sexpr_unsup.py b/test_regress/t/t_sequence_sexpr_unsup.py index 25f9960b8..4d0f745d0 100755 --- a/test_regress/t/t_sequence_sexpr_unsup.py +++ b/test_regress/t/t_sequence_sexpr_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sequence_sexpr_unsup.v b/test_regress/t/t_sequence_sexpr_unsup.v index d2ffb3a48..263800142 100644 --- a/test_regress/t/t_sequence_sexpr_unsup.v +++ b/test_regress/t/t_sequence_sexpr_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_sequence_unused.py b/test_regress/t/t_sequence_unused.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_sequence_unused.py +++ b/test_regress/t/t_sequence_unused.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sequence_unused.v b/test_regress/t/t_sequence_unused.v index 2ae824e2e..f40e2860e 100644 --- a/test_regress/t/t_sequence_unused.v +++ b/test_regress/t/t_sequence_unused.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface apb_if ( diff --git a/test_regress/t/t_setuphold.py b/test_regress/t/t_setuphold.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_setuphold.py +++ b/test_regress/t/t_setuphold.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_setuphold.v b/test_regress/t/t_setuphold.v index 3085c7d70..a7bb81aee 100644 --- a/test_regress/t/t_setuphold.v +++ b/test_regress/t/t_setuphold.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_simulate_array.py b/test_regress/t/t_simulate_array.py index 15d1de923..d19b59b98 100755 --- a/test_regress/t/t_simulate_array.py +++ b/test_regress/t/t_simulate_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_simulate_array.v b/test_regress/t/t_simulate_array.v index 055954f3b..ee5f06b41 100644 --- a/test_regress/t/t_simulate_array.v +++ b/test_regress/t/t_simulate_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 function integer fun; diff --git a/test_regress/t/t_slice_cmp.py b/test_regress/t/t_slice_cmp.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_slice_cmp.py +++ b/test_regress/t/t_slice_cmp.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_slice_cmp.v b/test_regress/t/t_slice_cmp.v index 15d3ccba6..1f12f0a81 100644 --- a/test_regress/t/t_slice_cmp.v +++ b/test_regress/t/t_slice_cmp.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_slice_cond.py b/test_regress/t/t_slice_cond.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_slice_cond.py +++ b/test_regress/t/t_slice_cond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_slice_cond.v b/test_regress/t/t_slice_cond.v index 8560bbce0..a94a00732 100644 --- a/test_regress/t/t_slice_cond.v +++ b/test_regress/t/t_slice_cond.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_slice_cond_2d_side_effect.py b/test_regress/t/t_slice_cond_2d_side_effect.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_slice_cond_2d_side_effect.py +++ b/test_regress/t/t_slice_cond_2d_side_effect.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_slice_cond_2d_side_effect.v b/test_regress/t/t_slice_cond_2d_side_effect.v index ff3d3575a..56e7b2276 100644 --- a/test_regress/t/t_slice_cond_2d_side_effect.v +++ b/test_regress/t/t_slice_cond_2d_side_effect.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 typedef int arr_t[5][3]; diff --git a/test_regress/t/t_slice_cond_side_effect.py b/test_regress/t/t_slice_cond_side_effect.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_slice_cond_side_effect.py +++ b/test_regress/t/t_slice_cond_side_effect.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_slice_cond_side_effect.v b/test_regress/t/t_slice_cond_side_effect.v index e9d9d556f..107ed0997 100644 --- a/test_regress/t/t_slice_cond_side_effect.v +++ b/test_regress/t/t_slice_cond_side_effect.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 typedef int arr_t[3]; diff --git a/test_regress/t/t_slice_init.py b/test_regress/t/t_slice_init.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_slice_init.py +++ b/test_regress/t/t_slice_init.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_slice_init.v b/test_regress/t/t_slice_init.v index a947919cc..5e7942f3f 100644 --- a/test_regress/t/t_slice_init.v +++ b/test_regress/t/t_slice_init.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_slice_struct_array_modport.py b/test_regress/t/t_slice_struct_array_modport.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_slice_struct_array_modport.py +++ b/test_regress/t/t_slice_struct_array_modport.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_slice_struct_array_modport.v b/test_regress/t/t_slice_struct_array_modport.v index d13ac77bb..b6c512e02 100644 --- a/test_regress/t/t_slice_struct_array_modport.v +++ b/test_regress/t/t_slice_struct_array_modport.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Varun Koyyalagunta. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 typedef struct packed { diff --git a/test_regress/t/t_specparam.py b/test_regress/t/t_specparam.py index c78c28783..148bcb2f4 100755 --- a/test_regress/t/t_specparam.py +++ b/test_regress/t/t_specparam.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_specparam.v b/test_regress/t/t_specparam.v index 3dc782844..72ea9a930 100644 --- a/test_regress/t/t_specparam.v +++ b/test_regress/t/t_specparam.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_split_var_0.py b/test_regress/t/t_split_var_0.py index d9c2c6068..ce5aea5dd 100755 --- a/test_regress/t/t_split_var_0.py +++ b/test_regress/t/t_split_var_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_split_var_0.v b/test_regress/t/t_split_var_0.v index 6d951d1c1..dddde330b 100644 --- a/test_regress/t/t_split_var_0.v +++ b/test_regress/t/t_split_var_0.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Yutetsu TAKATSUKASA. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 // If split_var pragma is removed, UNOPTFLAT appears. diff --git a/test_regress/t/t_split_var_0.vlt b/test_regress/t/t_split_var_0.vlt index 1f346a112..6cabc45bb 100644 --- a/test_regress/t/t_split_var_0.vlt +++ b/test_regress/t/t_split_var_0.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Marco Widmer. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Marco Widmer // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_split_var_1_bad.py b/test_regress/t/t_split_var_1_bad.py index fed583da0..95aae012d 100755 --- a/test_regress/t/t_split_var_1_bad.py +++ b/test_regress/t/t_split_var_1_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_split_var_1_bad.v b/test_regress/t/t_split_var_1_bad.v index f31bddcb4..b448b7a21 100644 --- a/test_regress/t/t_split_var_1_bad.v +++ b/test_regress/t/t_split_var_1_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Yutetsu TAKATSUKASA. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 logic [7:0] should_show_warning_global0 /* verilator split_var */; diff --git a/test_regress/t/t_split_var_2_trace.out b/test_regress/t/t_split_var_2_trace.out index f70c24b51..66230c7c9 100644 --- a/test_regress/t/t_split_var_2_trace.out +++ b/test_regress/t/t_split_var_2_trace.out @@ -1,409 +1,402 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end - $var wire 1 [" clk $end + $var wire 1 X" clk $end $scope module t $end - $var wire 1 [" clk $end - $var wire 32 \" DEPTH [31:0] $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 32 ^" NUMSUB [31:0] $end - $var wire 8 _" in [7:0] $end - $var wire 8 - out[0] [7:0] $end - $var wire 8 . out[1] [7:0] $end - $var wire 8 / out[2] [7:0] $end - $var wire 8 0 out[3] [7:0] $end - $var wire 8 1 out[4] [7:0] $end - $var wire 8 2 out[5] [7:0] $end - $var wire 8 3 out[6] [7:0] $end - $var wire 8 4 out[7] [7:0] $end - $var wire 8 5 out[8] [7:0] $end - $var wire 8 6 through_tmp [7:0] $end - $var wire 3 h shift [2:0] $end - $var wire 31 i hash_input_d [31:1] $end - $var wire 31 j hash_input_a [1:31] $end - $var wire 9 k hash_output_dd [8:0] $end - $var wire 9 l hash_output_da [8:0] $end - $var wire 9 m hash_output_ad [8:0] $end - $var wire 9 n hash_output_aa [8:0] $end - $var wire 64 `" expc [63:0] $end - $scope module always_block $end - $var wire 1 o failed $end - $var wire 9 p hash_expected [8:0] $end - $scope module unnamedblk1 $end - $var wire 32 q i [31:0] $end - $upscope $end - $upscope $end + $var wire 1 X" clk $end + $var wire 32 Y" DEPTH [31:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 32 [" NUMSUB [31:0] $end + $var wire 8 \" in [7:0] $end + $var wire 8 , out[0] [7:0] $end + $var wire 8 - out[1] [7:0] $end + $var wire 8 . out[2] [7:0] $end + $var wire 8 / out[3] [7:0] $end + $var wire 8 0 out[4] [7:0] $end + $var wire 8 1 out[5] [7:0] $end + $var wire 8 2 out[6] [7:0] $end + $var wire 8 3 out[7] [7:0] $end + $var wire 8 4 out[8] [7:0] $end + $var wire 8 5 through_tmp [7:0] $end + $var wire 3 g shift [2:0] $end + $var wire 31 h hash_input_d [31:1] $end + $var wire 31 i hash_input_a [1:31] $end + $var wire 9 j hash_output_dd [8:0] $end + $var wire 9 k hash_output_da [8:0] $end + $var wire 9 l hash_output_ad [8:0] $end + $var wire 9 m hash_output_aa [8:0] $end + $var wire 64 ]" expc [63:0] $end $scope module delay0 $end - $var wire 1 [" clk $end - $var wire 1 b" unpack_sig0(10) $end - $var wire 1 c" unpack_sig0(11) $end - $var wire 1 d" unpack_sig0(12) $end - $var wire 1 r unpack_sig0(13) $end - $var wire 1 s unpack_sig0(14) $end - $var wire 1 t unpack_sig0(15) $end - $var wire 1 u unpack_sig0(16) $end - $var wire 1 v unpack_sig1(13) $end - $var wire 1 w unpack_sig1(14) $end - $var wire 1 x unpack_sig1(15) $end - $var wire 1 y unpack_sig1(16) $end - $var wire 1 e" unpack_sig2(10) $end - $var wire 1 f" unpack_sig2(11) $end - $var wire 1 g" unpack_sig2(12) $end - $var wire 1 z unpack_sig2(13) $end - $var wire 1 { unpack_sig2(14) $end - $var wire 1 | unpack_sig2(15) $end - $var wire 1 } unpack_sig2(16) $end - $var wire 1 ~ unpack_sig3(13) $end - $var wire 1 !! unpack_sig3(14) $end - $var wire 1 "! unpack_sig3(15) $end - $var wire 1 #! unpack_sig3(16) $end - $var wire 32 $! c [31:0] $end + $var wire 1 X" clk $end + $var wire 1 _" unpack_sig0(10) $end + $var wire 1 `" unpack_sig0(11) $end + $var wire 1 a" unpack_sig0(12) $end + $var wire 1 n unpack_sig0(13) $end + $var wire 1 o unpack_sig0(14) $end + $var wire 1 p unpack_sig0(15) $end + $var wire 1 q unpack_sig0(16) $end + $var wire 1 r unpack_sig1(13) $end + $var wire 1 s unpack_sig1(14) $end + $var wire 1 t unpack_sig1(15) $end + $var wire 1 u unpack_sig1(16) $end + $var wire 1 b" unpack_sig2(10) $end + $var wire 1 c" unpack_sig2(11) $end + $var wire 1 d" unpack_sig2(12) $end + $var wire 1 v unpack_sig2(13) $end + $var wire 1 w unpack_sig2(14) $end + $var wire 1 x unpack_sig2(15) $end + $var wire 1 y unpack_sig2(16) $end + $var wire 1 z unpack_sig3(13) $end + $var wire 1 { unpack_sig3(14) $end + $var wire 1 | unpack_sig3(15) $end + $var wire 1 } unpack_sig3(16) $end + $var wire 32 ~ c [31:0] $end $upscope $end $scope module i_hash_aa $end - $var wire 31 j i [1:31] $end - $var wire 9 n o [8:0] $end - $upscope $end - $scope module i_hash_ad $end $var wire 31 i i [1:31] $end $var wire 9 m o [8:0] $end $upscope $end - $scope module i_hash_da $end - $var wire 31 j i [31:1] $end + $scope module i_hash_ad $end + $var wire 31 h i [1:31] $end $var wire 9 l o [8:0] $end $upscope $end - $scope module i_hash_dd $end + $scope module i_hash_da $end $var wire 31 i i [31:1] $end $var wire 9 k o [8:0] $end $upscope $end + $scope module i_hash_dd $end + $var wire 31 h i [31:1] $end + $var wire 9 j o [8:0] $end + $upscope $end $scope module i_t_array_rev $end - $var wire 1 [" clk $end - $var wire 32 h" cyc [31:0] $end - $var wire 1 # arrd(0) $end - $var wire 1 $ arrd(1) $end - $var wire 1 % y0 $end - $var wire 1 & y1 $end - $var wire 1 %! localbkw(0) $end - $var wire 1 &! localbkw(1) $end + $var wire 1 X" clk $end + $var wire 32 e" cyc [31:0] $end + $var wire 1 " arrd(0) $end + $var wire 1 # arrd(1) $end + $var wire 1 $ y0 $end + $var wire 1 % y1 $end + $var wire 1 !! localbkw(0) $end + $var wire 1 "! localbkw(1) $end $scope module arr_rev_u $end - $var wire 1 ' arrbkw[0] $end - $var wire 1 ( arrbkw[1] $end - $var wire 1 % y0 $end - $var wire 1 & y1 $end + $var wire 1 & arrbkw[0] $end + $var wire 1 ' arrbkw[1] $end + $var wire 1 $ y0 $end + $var wire 1 % y1 $end $upscope $end $upscope $end $scope module i_var_decl_with_init $end - $var wire 32 ) var0 [-1:30] $end - $var wire 32 * var2 [-1:30] $end - $var wire 32 + var1 [30:-1] $end - $var wire 32 , var3 [30:-1] $end + $var wire 32 ( var0 [-1:30] $end + $var wire 32 ) var2 [-1:30] $end + $var wire 32 * var1 [30:-1] $end + $var wire 32 + var3 [30:-1] $end $upscope $end $scope module shifter0 $end - $var wire 32 \" DEPTH [31:0] $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 _" in [7:0] $end - $var wire 3 h shift [2:0] $end - $var wire 8 '! out [7:0] $end - $var wire 32 i" OFFSET [31:0] $end - $var wire 8 (! tmp(-1) [7:0] $end - $var wire 8 )! tmp(-2) [7:0] $end - $var wire 8 _" tmp(-3) [7:0] $end - $var wire 8 '! tmp(0) [7:0] $end + $var wire 32 Y" DEPTH [31:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 \" in [7:0] $end + $var wire 3 g shift [2:0] $end + $var wire 8 #! out [7:0] $end + $var wire 32 f" OFFSET [31:0] $end + $var wire 8 $! tmp(-1) [7:0] $end + $var wire 8 %! tmp(-2) [7:0] $end + $var wire 8 \" tmp(-3) [7:0] $end + $var wire 8 &! tmp(0) [7:0] $end $upscope $end $scope module shifter1 $end - $var wire 32 \" DEPTH [31:0] $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 _" in [7:0] $end - $var wire 3 h shift [2:0] $end - $var wire 8 *! out [7:0] $end - $var wire 32 i" OFFSET [31:0] $end - $var wire 8 +! tmp(-1) [7:0] $end - $var wire 8 )! tmp(-2) [7:0] $end - $var wire 8 _" tmp(-3) [7:0] $end - $var wire 8 *! tmp(0) [7:0] $end + $var wire 32 Y" DEPTH [31:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 \" in [7:0] $end + $var wire 3 g shift [2:0] $end + $var wire 8 '! out [7:0] $end + $var wire 32 f" OFFSET [31:0] $end + $var wire 8 (! tmp(-1) [7:0] $end + $var wire 8 %! tmp(-2) [7:0] $end + $var wire 8 \" tmp(-3) [7:0] $end + $var wire 8 '! tmp(0) [7:0] $end $upscope $end $scope module shifter2 $end - $var wire 32 \" DEPTH [31:0] $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 _" in [7:0] $end - $var wire 3 h shift [2:0] $end - $var wire 8 ,! out [7:0] $end - $var wire 32 j" OFFSET [31:0] $end - $var wire 8 _" tmp(1) [7:0] $end - $var wire 8 -! tmp(2) [7:0] $end - $var wire 8 .! tmp(3) [7:0] $end - $var wire 8 ,! tmp(4) [7:0] $end + $var wire 32 Y" DEPTH [31:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 \" in [7:0] $end + $var wire 3 g shift [2:0] $end + $var wire 8 )! out [7:0] $end + $var wire 32 g" OFFSET [31:0] $end + $var wire 8 \" tmp(1) [7:0] $end + $var wire 8 *! tmp(2) [7:0] $end + $var wire 8 +! tmp(3) [7:0] $end + $var wire 8 )! tmp(4) [7:0] $end $upscope $end $scope module shifter3 $end - $var wire 32 \" DEPTH [31:0] $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 _" in [7:0] $end - $var wire 3 h shift [2:0] $end - $var wire 8 7 out [7:0] $end - $var wire 32 j" OFFSET [31:0] $end - $var wire 32 \" N [31:0] $end - $var wire 8 _" tmp0(1)(1) [7:0] $end - $var wire 8 _" tmp0(1)(2) [7:0] $end - $var wire 8 _" tmp0(1)(3) [7:0] $end - $var wire 8 )! tmp0(2)(1) [7:0] $end - $var wire 8 )! tmp0(2)(2) [7:0] $end - $var wire 8 )! tmp0(2)(3) [7:0] $end - $var wire 8 /! tmp0(3)(1) [7:0] $end - $var wire 8 0! tmp0(3)(2) [7:0] $end - $var wire 8 1! tmp0(3)(3) [7:0] $end - $var wire 8 2! tmp0(4)(1) [7:0] $end - $var wire 8 3! tmp0(4)(2) [7:0] $end - $var wire 8 4! tmp0(4)(3) [7:0] $end - $var wire 8 5! tmp1(1)(1) [7:0] $end - $var wire 8 6! tmp1(1)(2) [7:0] $end - $var wire 8 7! tmp1(1)(3) [7:0] $end - $var wire 8 8! tmp1(2)(1) [7:0] $end - $var wire 8 9! tmp1(2)(2) [7:0] $end - $var wire 8 :! tmp1(2)(3) [7:0] $end - $var wire 8 ;! tmp1(3)(1) [7:0] $end - $var wire 8 ! tmp1(4)(1) [7:0] $end - $var wire 8 ?! tmp1(4)(2) [7:0] $end - $var wire 8 @! tmp1(4)(3) [7:0] $end - $var wire 8 A! tmp2[1][1] [7:0] $end - $var wire 8 B! tmp2[1][2] [7:0] $end - $var wire 8 C! tmp2[1][3] [7:0] $end - $var wire 8 D! tmp2[2][1] [7:0] $end - $var wire 8 E! tmp2[2][2] [7:0] $end - $var wire 8 F! tmp2[2][3] [7:0] $end - $var wire 8 G! tmp2[3][1] [7:0] $end - $var wire 8 H! tmp2[3][2] [7:0] $end - $var wire 8 I! tmp2[3][3] [7:0] $end - $var wire 8 J! tmp2[4][1] [7:0] $end - $var wire 8 K! tmp2[4][2] [7:0] $end - $var wire 8 L! tmp2[4][3] [7:0] $end - $var wire 8 M! tmp3(1)(1) [7:0] $end - $var wire 8 N! tmp3(1)(2) [7:0] $end - $var wire 8 O! tmp3(1)(3) [7:0] $end - $var wire 8 P! tmp3(2)(1) [7:0] $end - $var wire 8 Q! tmp3(2)(2) [7:0] $end - $var wire 8 R! tmp3(2)(3) [7:0] $end - $var wire 8 S! tmp3(3)(1) [7:0] $end - $var wire 8 T! tmp3(3)(2) [7:0] $end - $var wire 8 U! tmp3(3)(3) [7:0] $end - $var wire 8 V! tmp3(4)(1) [7:0] $end - $var wire 8 W! tmp3(4)(2) [7:0] $end - $var wire 8 X! tmp3(4)(3) [7:0] $end - $var wire 8 Y! tmp4(1)(1) [7:0] $end - $var wire 8 Z! tmp4(1)(2) [7:0] $end - $var wire 8 [! tmp4(1)(3) [7:0] $end - $var wire 8 \! tmp4(2)(1) [7:0] $end - $var wire 8 ]! tmp4(2)(2) [7:0] $end - $var wire 8 ^! tmp4(2)(3) [7:0] $end - $var wire 8 _! tmp4(3)(1) [7:0] $end - $var wire 8 `! tmp4(3)(2) [7:0] $end - $var wire 8 a! tmp4(3)(3) [7:0] $end - $var wire 8 b! tmp4(4)(1) [7:0] $end - $var wire 8 c! tmp4(4)(2) [7:0] $end - $var wire 8 d! tmp4(4)(3) [7:0] $end - $var wire 8 e! tmp5[1][1] [7:0] $end - $var wire 8 f! tmp5[1][2] [7:0] $end - $var wire 8 g! tmp5[1][3] [7:0] $end - $var wire 8 h! tmp5[2][1] [7:0] $end - $var wire 8 i! tmp5[2][2] [7:0] $end - $var wire 8 j! tmp5[2][3] [7:0] $end - $var wire 8 k! tmp5[3][1] [7:0] $end - $var wire 8 l! tmp5[3][2] [7:0] $end - $var wire 8 m! tmp5[3][3] [7:0] $end - $var wire 8 n! tmp5[4][1] [7:0] $end - $var wire 8 o! tmp5[4][2] [7:0] $end - $var wire 8 p! tmp5[4][3] [7:0] $end - $var wire 8 q! tmp6(1)(1) [7:0] $end - $var wire 8 r! tmp6(1)(2) [7:0] $end - $var wire 8 s! tmp6(1)(3) [7:0] $end - $var wire 8 t! tmp6(2)(1) [7:0] $end - $var wire 8 u! tmp6(2)(2) [7:0] $end - $var wire 8 v! tmp6(2)(3) [7:0] $end - $var wire 8 w! tmp6(3)(1) [7:0] $end - $var wire 8 x! tmp6(3)(2) [7:0] $end - $var wire 8 y! tmp6(3)(3) [7:0] $end - $var wire 8 z! tmp6(4)(1) [7:0] $end - $var wire 8 {! tmp6(4)(2) [7:0] $end - $var wire 8 |! tmp6(4)(3) [7:0] $end - $var wire 8 }! tmp7(2)(1) [7:0] $end - $var wire 8 ~! tmp7(2)(2) [7:0] $end - $var wire 8 !" tmp7(2)(3) [7:0] $end - $var wire 8 "" tmp7(3)(1) [7:0] $end - $var wire 8 #" tmp7(3)(2) [7:0] $end - $var wire 8 $" tmp7(3)(3) [7:0] $end - $var wire 8 %" tmp7(4)(1) [7:0] $end - $var wire 8 &" tmp7(4)(2) [7:0] $end - $var wire 8 '" tmp7(4)(3) [7:0] $end - $var wire 8 (" tmp7(5)(1) [7:0] $end - $var wire 8 )" tmp7(5)(2) [7:0] $end - $var wire 8 *" tmp7(5)(3) [7:0] $end - $var wire 8 k" tmp8(0)(1) [7:0] $end - $var wire 8 l" tmp8(0)(2) [7:0] $end - $var wire 8 m" tmp8(0)(3) [7:0] $end - $var wire 8 n" tmp8(1)(1) [7:0] $end - $var wire 8 o" tmp8(1)(2) [7:0] $end - $var wire 8 p" tmp8(1)(3) [7:0] $end - $var wire 8 +" tmp8(2)(1) [7:0] $end - $var wire 8 ," tmp8(2)(2) [7:0] $end - $var wire 8 -" tmp8(2)(3) [7:0] $end - $var wire 8 ." tmp8(3)(1) [7:0] $end - $var wire 8 /" tmp8(3)(2) [7:0] $end - $var wire 8 0" tmp8(3)(3) [7:0] $end - $var wire 8 1" tmp8(4)(1) [7:0] $end - $var wire 8 2" tmp8(4)(2) [7:0] $end - $var wire 8 3" tmp8(4)(3) [7:0] $end - $var wire 8 4" tmp8(5)(1) [7:0] $end - $var wire 8 5" tmp8(5)(2) [7:0] $end - $var wire 8 6" tmp8(5)(3) [7:0] $end - $var wire 8 q" tmp8(6)(1) [7:0] $end - $var wire 8 r" tmp8(6)(2) [7:0] $end - $var wire 8 s" tmp8(6)(3) [7:0] $end - $var wire 8 t" tmp8(7)(1) [7:0] $end - $var wire 8 u" tmp8(7)(2) [7:0] $end - $var wire 8 v" tmp8(7)(3) [7:0] $end - $var wire 8 7" tmp9(4)(1) [7:0] $end - $var wire 8 8" tmp9(4)(2) [7:0] $end - $var wire 8 9" tmp9(4)(3) [7:0] $end - $var wire 8 :" tmp9(5)(1) [7:0] $end - $var wire 8 ;" tmp9(5)(2) [7:0] $end - $var wire 8 <" tmp9(5)(3) [7:0] $end - $var wire 8 =" tmp9(6)(1) [7:0] $end - $var wire 8 >" tmp9(6)(2) [7:0] $end - $var wire 8 ?" tmp9(6)(3) [7:0] $end - $var wire 8 @" tmp9(7)(1) [7:0] $end - $var wire 8 A" tmp9(7)(2) [7:0] $end - $var wire 8 B" tmp9(7)(3) [7:0] $end - $var wire 8 C" tmp10(1)(1) [7:0] $end - $var wire 8 D" tmp10(1)(2) [7:0] $end - $var wire 8 E" tmp10(1)(3) [7:0] $end - $var wire 8 F" tmp10(2)(1) [7:0] $end - $var wire 8 G" tmp10(2)(2) [7:0] $end - $var wire 8 H" tmp10(2)(3) [7:0] $end - $var wire 8 I" tmp10(3)(1) [7:0] $end - $var wire 8 J" tmp10(3)(2) [7:0] $end - $var wire 8 K" tmp10(3)(3) [7:0] $end - $var wire 8 L" tmp10(4)(1) [7:0] $end - $var wire 8 M" tmp10(4)(2) [7:0] $end - $var wire 8 N" tmp10(4)(3) [7:0] $end - $var wire 8 8 tmp12(-1)(1)(1) [7:0] $end - $var wire 8 9 tmp12(-1)(1)(2) [7:0] $end - $var wire 8 : tmp12(-1)(1)(3) [7:0] $end - $var wire 8 ; tmp12(-1)(2)(1) [7:0] $end - $var wire 8 < tmp12(-1)(2)(2) [7:0] $end - $var wire 8 = tmp12(-1)(2)(3) [7:0] $end - $var wire 8 > tmp12(-1)(3)(1) [7:0] $end - $var wire 8 ? tmp12(-1)(3)(2) [7:0] $end - $var wire 8 @ tmp12(-1)(3)(3) [7:0] $end - $var wire 8 7 tmp12(-1)(4)(1) [7:0] $end - $var wire 8 A tmp12(-1)(4)(2) [7:0] $end - $var wire 8 B tmp12(-1)(4)(3) [7:0] $end - $var wire 8 C tmp12(0)(1)(1) [7:0] $end - $var wire 8 D tmp12(0)(1)(2) [7:0] $end - $var wire 8 E tmp12(0)(1)(3) [7:0] $end - $var wire 8 F tmp12(0)(2)(1) [7:0] $end - $var wire 8 G tmp12(0)(2)(2) [7:0] $end - $var wire 8 H tmp12(0)(2)(3) [7:0] $end - $var wire 8 I tmp12(0)(3)(1) [7:0] $end - $var wire 8 J tmp12(0)(3)(2) [7:0] $end - $var wire 8 K tmp12(0)(3)(3) [7:0] $end - $var wire 8 L tmp12(0)(4)(1) [7:0] $end - $var wire 8 M tmp12(0)(4)(2) [7:0] $end - $var wire 8 N tmp12(0)(4)(3) [7:0] $end - $var wire 8 w" tmp13(1)(1) [7:0] $end - $var wire 8 x" tmp13(1)(2) [7:0] $end - $var wire 8 y" tmp13(1)(3) [7:0] $end - $var wire 8 z" tmp13(2)(1) [7:0] $end - $var wire 8 {" tmp13(2)(2) [7:0] $end - $var wire 8 |" tmp13(2)(3) [7:0] $end - $var wire 8 }" tmp13(3)(1) [7:0] $end - $var wire 8 ~" tmp13(3)(2) [7:0] $end - $var wire 8 !# tmp13(3)(3) [7:0] $end - $var wire 8 "# tmp13(4)(1) [7:0] $end - $var wire 8 ## tmp13(4)(2) [7:0] $end - $var wire 8 $# tmp13(4)(3) [7:0] $end + $var wire 32 Y" DEPTH [31:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 \" in [7:0] $end + $var wire 3 g shift [2:0] $end + $var wire 8 6 out [7:0] $end + $var wire 32 g" OFFSET [31:0] $end + $var wire 32 Y" N [31:0] $end + $var wire 8 \" tmp0(1)(1) [7:0] $end + $var wire 8 \" tmp0(1)(2) [7:0] $end + $var wire 8 \" tmp0(1)(3) [7:0] $end + $var wire 8 %! tmp0(2)(1) [7:0] $end + $var wire 8 %! tmp0(2)(2) [7:0] $end + $var wire 8 %! tmp0(2)(3) [7:0] $end + $var wire 8 ,! tmp0(3)(1) [7:0] $end + $var wire 8 -! tmp0(3)(2) [7:0] $end + $var wire 8 .! tmp0(3)(3) [7:0] $end + $var wire 8 /! tmp0(4)(1) [7:0] $end + $var wire 8 0! tmp0(4)(2) [7:0] $end + $var wire 8 1! tmp0(4)(3) [7:0] $end + $var wire 8 2! tmp1(1)(1) [7:0] $end + $var wire 8 3! tmp1(1)(2) [7:0] $end + $var wire 8 4! tmp1(1)(3) [7:0] $end + $var wire 8 5! tmp1(2)(1) [7:0] $end + $var wire 8 6! tmp1(2)(2) [7:0] $end + $var wire 8 7! tmp1(2)(3) [7:0] $end + $var wire 8 8! tmp1(3)(1) [7:0] $end + $var wire 8 9! tmp1(3)(2) [7:0] $end + $var wire 8 :! tmp1(3)(3) [7:0] $end + $var wire 8 ;! tmp1(4)(1) [7:0] $end + $var wire 8 ! tmp2[1][1] [7:0] $end + $var wire 8 ?! tmp2[1][2] [7:0] $end + $var wire 8 @! tmp2[1][3] [7:0] $end + $var wire 8 A! tmp2[2][1] [7:0] $end + $var wire 8 B! tmp2[2][2] [7:0] $end + $var wire 8 C! tmp2[2][3] [7:0] $end + $var wire 8 D! tmp2[3][1] [7:0] $end + $var wire 8 E! tmp2[3][2] [7:0] $end + $var wire 8 F! tmp2[3][3] [7:0] $end + $var wire 8 G! tmp2[4][1] [7:0] $end + $var wire 8 H! tmp2[4][2] [7:0] $end + $var wire 8 I! tmp2[4][3] [7:0] $end + $var wire 8 J! tmp3(1)(1) [7:0] $end + $var wire 8 K! tmp3(1)(2) [7:0] $end + $var wire 8 L! tmp3(1)(3) [7:0] $end + $var wire 8 M! tmp3(2)(1) [7:0] $end + $var wire 8 N! tmp3(2)(2) [7:0] $end + $var wire 8 O! tmp3(2)(3) [7:0] $end + $var wire 8 P! tmp3(3)(1) [7:0] $end + $var wire 8 Q! tmp3(3)(2) [7:0] $end + $var wire 8 R! tmp3(3)(3) [7:0] $end + $var wire 8 S! tmp3(4)(1) [7:0] $end + $var wire 8 T! tmp3(4)(2) [7:0] $end + $var wire 8 U! tmp3(4)(3) [7:0] $end + $var wire 8 V! tmp4(1)(1) [7:0] $end + $var wire 8 W! tmp4(1)(2) [7:0] $end + $var wire 8 X! tmp4(1)(3) [7:0] $end + $var wire 8 Y! tmp4(2)(1) [7:0] $end + $var wire 8 Z! tmp4(2)(2) [7:0] $end + $var wire 8 [! tmp4(2)(3) [7:0] $end + $var wire 8 \! tmp4(3)(1) [7:0] $end + $var wire 8 ]! tmp4(3)(2) [7:0] $end + $var wire 8 ^! tmp4(3)(3) [7:0] $end + $var wire 8 _! tmp4(4)(1) [7:0] $end + $var wire 8 `! tmp4(4)(2) [7:0] $end + $var wire 8 a! tmp4(4)(3) [7:0] $end + $var wire 8 b! tmp5[1][1] [7:0] $end + $var wire 8 c! tmp5[1][2] [7:0] $end + $var wire 8 d! tmp5[1][3] [7:0] $end + $var wire 8 e! tmp5[2][1] [7:0] $end + $var wire 8 f! tmp5[2][2] [7:0] $end + $var wire 8 g! tmp5[2][3] [7:0] $end + $var wire 8 h! tmp5[3][1] [7:0] $end + $var wire 8 i! tmp5[3][2] [7:0] $end + $var wire 8 j! tmp5[3][3] [7:0] $end + $var wire 8 k! tmp5[4][1] [7:0] $end + $var wire 8 l! tmp5[4][2] [7:0] $end + $var wire 8 m! tmp5[4][3] [7:0] $end + $var wire 8 n! tmp6(1)(1) [7:0] $end + $var wire 8 o! tmp6(1)(2) [7:0] $end + $var wire 8 p! tmp6(1)(3) [7:0] $end + $var wire 8 q! tmp6(2)(1) [7:0] $end + $var wire 8 r! tmp6(2)(2) [7:0] $end + $var wire 8 s! tmp6(2)(3) [7:0] $end + $var wire 8 t! tmp6(3)(1) [7:0] $end + $var wire 8 u! tmp6(3)(2) [7:0] $end + $var wire 8 v! tmp6(3)(3) [7:0] $end + $var wire 8 w! tmp6(4)(1) [7:0] $end + $var wire 8 x! tmp6(4)(2) [7:0] $end + $var wire 8 y! tmp6(4)(3) [7:0] $end + $var wire 8 z! tmp7(2)(1) [7:0] $end + $var wire 8 {! tmp7(2)(2) [7:0] $end + $var wire 8 |! tmp7(2)(3) [7:0] $end + $var wire 8 }! tmp7(3)(1) [7:0] $end + $var wire 8 ~! tmp7(3)(2) [7:0] $end + $var wire 8 !" tmp7(3)(3) [7:0] $end + $var wire 8 "" tmp7(4)(1) [7:0] $end + $var wire 8 #" tmp7(4)(2) [7:0] $end + $var wire 8 $" tmp7(4)(3) [7:0] $end + $var wire 8 %" tmp7(5)(1) [7:0] $end + $var wire 8 &" tmp7(5)(2) [7:0] $end + $var wire 8 '" tmp7(5)(3) [7:0] $end + $var wire 8 h" tmp8(0)(1) [7:0] $end + $var wire 8 i" tmp8(0)(2) [7:0] $end + $var wire 8 j" tmp8(0)(3) [7:0] $end + $var wire 8 k" tmp8(1)(1) [7:0] $end + $var wire 8 l" tmp8(1)(2) [7:0] $end + $var wire 8 m" tmp8(1)(3) [7:0] $end + $var wire 8 (" tmp8(2)(1) [7:0] $end + $var wire 8 )" tmp8(2)(2) [7:0] $end + $var wire 8 *" tmp8(2)(3) [7:0] $end + $var wire 8 +" tmp8(3)(1) [7:0] $end + $var wire 8 ," tmp8(3)(2) [7:0] $end + $var wire 8 -" tmp8(3)(3) [7:0] $end + $var wire 8 ." tmp8(4)(1) [7:0] $end + $var wire 8 /" tmp8(4)(2) [7:0] $end + $var wire 8 0" tmp8(4)(3) [7:0] $end + $var wire 8 1" tmp8(5)(1) [7:0] $end + $var wire 8 2" tmp8(5)(2) [7:0] $end + $var wire 8 3" tmp8(5)(3) [7:0] $end + $var wire 8 n" tmp8(6)(1) [7:0] $end + $var wire 8 o" tmp8(6)(2) [7:0] $end + $var wire 8 p" tmp8(6)(3) [7:0] $end + $var wire 8 q" tmp8(7)(1) [7:0] $end + $var wire 8 r" tmp8(7)(2) [7:0] $end + $var wire 8 s" tmp8(7)(3) [7:0] $end + $var wire 8 4" tmp9(4)(1) [7:0] $end + $var wire 8 5" tmp9(4)(2) [7:0] $end + $var wire 8 6" tmp9(4)(3) [7:0] $end + $var wire 8 7" tmp9(5)(1) [7:0] $end + $var wire 8 8" tmp9(5)(2) [7:0] $end + $var wire 8 9" tmp9(5)(3) [7:0] $end + $var wire 8 :" tmp9(6)(1) [7:0] $end + $var wire 8 ;" tmp9(6)(2) [7:0] $end + $var wire 8 <" tmp9(6)(3) [7:0] $end + $var wire 8 =" tmp9(7)(1) [7:0] $end + $var wire 8 >" tmp9(7)(2) [7:0] $end + $var wire 8 ?" tmp9(7)(3) [7:0] $end + $var wire 8 @" tmp10(1)(1) [7:0] $end + $var wire 8 A" tmp10(1)(2) [7:0] $end + $var wire 8 B" tmp10(1)(3) [7:0] $end + $var wire 8 C" tmp10(2)(1) [7:0] $end + $var wire 8 D" tmp10(2)(2) [7:0] $end + $var wire 8 E" tmp10(2)(3) [7:0] $end + $var wire 8 F" tmp10(3)(1) [7:0] $end + $var wire 8 G" tmp10(3)(2) [7:0] $end + $var wire 8 H" tmp10(3)(3) [7:0] $end + $var wire 8 I" tmp10(4)(1) [7:0] $end + $var wire 8 J" tmp10(4)(2) [7:0] $end + $var wire 8 K" tmp10(4)(3) [7:0] $end + $var wire 8 7 tmp12(-1)(1)(1) [7:0] $end + $var wire 8 8 tmp12(-1)(1)(2) [7:0] $end + $var wire 8 9 tmp12(-1)(1)(3) [7:0] $end + $var wire 8 : tmp12(-1)(2)(1) [7:0] $end + $var wire 8 ; tmp12(-1)(2)(2) [7:0] $end + $var wire 8 < tmp12(-1)(2)(3) [7:0] $end + $var wire 8 = tmp12(-1)(3)(1) [7:0] $end + $var wire 8 > tmp12(-1)(3)(2) [7:0] $end + $var wire 8 ? tmp12(-1)(3)(3) [7:0] $end + $var wire 8 6 tmp12(-1)(4)(1) [7:0] $end + $var wire 8 @ tmp12(-1)(4)(2) [7:0] $end + $var wire 8 A tmp12(-1)(4)(3) [7:0] $end + $var wire 8 B tmp12(0)(1)(1) [7:0] $end + $var wire 8 C tmp12(0)(1)(2) [7:0] $end + $var wire 8 D tmp12(0)(1)(3) [7:0] $end + $var wire 8 E tmp12(0)(2)(1) [7:0] $end + $var wire 8 F tmp12(0)(2)(2) [7:0] $end + $var wire 8 G tmp12(0)(2)(3) [7:0] $end + $var wire 8 H tmp12(0)(3)(1) [7:0] $end + $var wire 8 I tmp12(0)(3)(2) [7:0] $end + $var wire 8 J tmp12(0)(3)(3) [7:0] $end + $var wire 8 K tmp12(0)(4)(1) [7:0] $end + $var wire 8 L tmp12(0)(4)(2) [7:0] $end + $var wire 8 M tmp12(0)(4)(3) [7:0] $end + $var wire 8 t" tmp13(1)(1) [7:0] $end + $var wire 8 u" tmp13(1)(2) [7:0] $end + $var wire 8 v" tmp13(1)(3) [7:0] $end + $var wire 8 w" tmp13(2)(1) [7:0] $end + $var wire 8 x" tmp13(2)(2) [7:0] $end + $var wire 8 y" tmp13(2)(3) [7:0] $end + $var wire 8 z" tmp13(3)(1) [7:0] $end + $var wire 8 {" tmp13(3)(2) [7:0] $end + $var wire 8 |" tmp13(3)(3) [7:0] $end + $var wire 8 }" tmp13(4)(1) [7:0] $end + $var wire 8 ~" tmp13(4)(2) [7:0] $end + $var wire 8 !# tmp13(4)(3) [7:0] $end $upscope $end $scope module shifter4 $end - $var wire 32 \" DEPTH [31:0] $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 _" in [7:0] $end - $var wire 3 h shift [2:0] $end - $var wire 8 O" out [7:0] $end - $var wire 32 %# OFFSET [31:0] $end - $var wire 32 &# tmp(2) [31:0] $end - $var wire 32 P" tmp(3) [31:0] $end - $var wire 32 Q" tmp(4) [31:0] $end - $var wire 32 R" tmp(5) [31:0] $end - $var wire 24 '# PAD [23:0] $end + $var wire 32 Y" DEPTH [31:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 \" in [7:0] $end + $var wire 3 g shift [2:0] $end + $var wire 8 L" out [7:0] $end + $var wire 32 "# OFFSET [31:0] $end + $var wire 32 ## tmp(2) [31:0] $end + $var wire 32 M" tmp(3) [31:0] $end + $var wire 32 N" tmp(4) [31:0] $end + $var wire 32 O" tmp(5) [31:0] $end + $var wire 24 $# PAD [23:0] $end $upscope $end $scope module shifter5 $end - $var wire 32 \" DEPTH [31:0] $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 _" in [7:0] $end - $var wire 3 h shift [2:0] $end - $var wire 8 S" out [7:0] $end - $var wire 32 (# OFFSET [31:0] $end - $var wire 32 T" tmp [31:0] $end + $var wire 32 Y" DEPTH [31:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 \" in [7:0] $end + $var wire 3 g shift [2:0] $end + $var wire 8 P" out [7:0] $end + $var wire 32 %# OFFSET [31:0] $end + $var wire 32 Q" tmp [31:0] $end $upscope $end $scope module shifter6 $end - $var wire 32 \" DEPTH [31:0] $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 _" in [7:0] $end - $var wire 3 h shift [2:0] $end - $var wire 8 U" out [7:0] $end - $var wire 32 (# OFFSET [31:0] $end - $var wire 32 V" tmp [31:0] $end + $var wire 32 Y" DEPTH [31:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 \" in [7:0] $end + $var wire 3 g shift [2:0] $end + $var wire 8 R" out [7:0] $end + $var wire 32 %# OFFSET [31:0] $end + $var wire 32 S" tmp [31:0] $end $upscope $end $scope module shifter7 $end - $var wire 32 \" DEPTH [31:0] $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 _" in [7:0] $end - $var wire 3 h shift [2:0] $end - $var wire 8 W" out [7:0] $end - $var wire 32 X" tmp [31:0] $end + $var wire 32 Y" DEPTH [31:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 \" in [7:0] $end + $var wire 3 g shift [2:0] $end + $var wire 8 T" out [7:0] $end + $var wire 32 U" tmp [31:0] $end $upscope $end $scope module shifter8 $end - $var wire 32 \" DEPTH [31:0] $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 _" in [7:0] $end - $var wire 3 h shift [2:0] $end - $var wire 8 Y" out [7:0] $end - $var wire 32 Z" tmp [0:31] $end + $var wire 32 Y" DEPTH [31:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 \" in [7:0] $end + $var wire 3 g shift [2:0] $end + $var wire 8 V" out [7:0] $end + $var wire 32 W" tmp [0:31] $end $upscope $end $scope module though0 $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 O in [7:0] $end - $var wire 8 6 out [7:0] $end - $var wire 1 P unpack_tmp(0) $end - $var wire 1 Q unpack_tmp(1) $end - $var wire 1 R unpack_tmp(2) $end - $var wire 1 S unpack_tmp(3) $end - $var wire 1 T unpack_tmp(4) $end - $var wire 1 U unpack_tmp(5) $end - $var wire 1 V unpack_tmp(6) $end - $var wire 1 W unpack_tmp(7) $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 N in [7:0] $end + $var wire 8 5 out [7:0] $end + $var wire 1 O unpack_tmp(0) $end + $var wire 1 P unpack_tmp(1) $end + $var wire 1 Q unpack_tmp(2) $end + $var wire 1 R unpack_tmp(3) $end + $var wire 1 S unpack_tmp(4) $end + $var wire 1 T unpack_tmp(5) $end + $var wire 1 U unpack_tmp(6) $end + $var wire 1 V unpack_tmp(7) $end $scope module i_pack2unpack $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 8 O in [7:0] $end - $var wire 1 X out[0] $end - $var wire 1 Y out[1] $end - $var wire 1 Z out[2] $end - $var wire 1 [ out[3] $end - $var wire 1 \ out[4] $end - $var wire 1 ] out[5] $end - $var wire 1 ^ out[6] $end - $var wire 1 _ out[7] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 8 N in [7:0] $end + $var wire 1 W out[0] $end + $var wire 1 X out[1] $end + $var wire 1 Y out[2] $end + $var wire 1 Z out[3] $end + $var wire 1 [ out[4] $end + $var wire 1 \ out[5] $end + $var wire 1 ] out[6] $end + $var wire 1 ^ out[7] $end $upscope $end $scope module i_unpack2pack $end - $var wire 32 ]" WIDTH [31:0] $end - $var wire 1 ` in[0] $end - $var wire 1 a in[1] $end - $var wire 1 b in[2] $end - $var wire 1 c in[3] $end - $var wire 1 d in[4] $end - $var wire 1 e in[5] $end - $var wire 1 f in[6] $end - $var wire 1 g in[7] $end - $var wire 8 6 out [7:0] $end + $var wire 32 Z" WIDTH [31:0] $end + $var wire 1 _ in[0] $end + $var wire 1 ` in[1] $end + $var wire 1 a in[2] $end + $var wire 1 b in[3] $end + $var wire 1 c in[4] $end + $var wire 1 d in[5] $end + $var wire 1 e in[6] $end + $var wire 1 f in[7] $end + $var wire 8 5 out [7:0] $end $upscope $end $upscope $end $upscope $end @@ -412,16 +405,17 @@ $enddefinitions $end #0 -1# +1" +0# 0$ -0% -1& -0' -1( -b00000001001000110100010101100111 ) -b00100000000000000000000000000000 * -b00000001001000110100000000100111 + -b00000000000000000000000000000011 , +1% +0& +1' +b00000001001000110100010101100111 ( +b00100000000000000000000000000000 ) +b00000001001000110100000000100111 * +b00000000000000000000000000000011 + +b10001110 , b10001110 - b10001110 . b10001110 / @@ -456,41 +450,41 @@ b10001110 K b10001110 L b10001110 M b10001110 N -b10001110 O -1P +1O +0P 0Q 0R -0S +1S 1T 1U -1V +0V 0W -0X +1X 1Y 1Z -1[ +0[ 0\ 0] -0^ -1_ -0` +1^ +0_ +1` 1a 1b -1c +0c 0d 0e -0f -1g -b000 h +1f +b000 g +b0110010000100001010101111001101 h b0110010000100001010101111001101 i -b0110010000100001010101111001101 j +b100011100 j b100011100 k b100011100 l b100011100 m -b100011100 n +0n 0o -b000000000 p -b00000000000000000000000000000000 q +0p +0q 0r 0s 0t @@ -503,13 +497,13 @@ b00000000000000000000000000000000 q 0{ 0| 0} -0~ +b00000000000000000000000000000000 ~ 0!! 0"! -0#! -b00000000000000000000000000000000 $! -0%! -0&! +b10001110 #! +b10001110 $! +b10001110 %! +b10001110 &! b10001110 '! b10001110 (! b10001110 )! @@ -642,35 +636,35 @@ b10001110 I" b10001110 J" b10001110 K" b10001110 L" -b10001110 M" -b10001110 N" -b10001110 O" -b00000000000000000000000010001110 P" -b00000000000000000000000010001110 Q" -b00000000000000000000000010001110 R" -b10001110 S" -b10001110100011101000111010001110 T" -b10001110 U" -b10001110100011101000111010001110 V" -b10001110 W" -b10001110100011101000111010001110 X" -b10001110 Y" -b10001110100011101000111010001110 Z" -0[" -b00000000000000000000000000000011 \" -b00000000000000000000000000001000 ]" -b00000000000000000000000000001001 ^" -b10001110 _" -b1000111001000111101000111101000111101000011101000011101000011101 `" +b00000000000000000000000010001110 M" +b00000000000000000000000010001110 N" +b00000000000000000000000010001110 O" +b10001110 P" +b10001110100011101000111010001110 Q" +b10001110 R" +b10001110100011101000111010001110 S" +b10001110 T" +b10001110100011101000111010001110 U" +b10001110 V" +b10001110100011101000111010001110 W" +0X" +b00000000000000000000000000000011 Y" +b00000000000000000000000000001000 Z" +b00000000000000000000000000001001 [" +b10001110 \" +b1000111001000111101000111101000111101000011101000011101000011101 ]" +0_" +0`" +0a" 0b" 0c" 0d" -0e" -0f" -0g" -b00000000000000000000000000000000 h" -b11111111111111111111111111111101 i" -b00000000000000000000000000000001 j" +b00000000000000000000000000000000 e" +b11111111111111111111111111111101 f" +b00000000000000000000000000000001 g" +b00000000 h" +b00000000 i" +b00000000 j" b00000000 k" b00000000 l" b00000000 m" @@ -692,14 +686,12 @@ b00000000 |" b00000000 }" b00000000 ~" b00000000 !# -b00000000 "# -b00000000 ## -b00000000 $# -b00000000000000000000000000000010 %# -b00000000000000000000000010001110 &# -b000000000000000000000000 '# -b11111111111111111111111111111110 (# +b00000000000000000000000000000010 "# +b00000000000000000000000010001110 ## +b000000000000000000000000 $# +b11111111111111111111111111111110 %# #10 +b01000111 , b01000111 - b01000111 . b01000111 / @@ -710,7 +702,7 @@ b01000111 3 b01000111 4 b01000111 5 b01000111 6 -b01000111 7 +b01000111 : b01000111 ; b01000111 < b01000111 = @@ -718,7 +710,7 @@ b01000111 > b01000111 ? b01000111 @ b01000111 A -b01000111 B +b01000111 E b01000111 F b01000111 G b01000111 H @@ -728,34 +720,35 @@ b01000111 K b01000111 L b01000111 M b01000111 N -b01000111 O -0P -1Q -0T +0O +1P +0S +1V 1W -1X -0[ -1^ -0_ -1` -0c -1f -0g -b001 h +0Z +1] +0^ +1_ +0b +1e +0f +b001 g +b1011001000010000101010111100110 h b1011001000010000101010111100110 i -b1011001000010000101010111100110 j +b010001110 j b010001110 k b010001110 l b010001110 m -b010001110 n -b100011100 p -b00000000000000000000000000001001 q +1n 1r 1v 1z -1~ -b00000000000000000000000000000001 $! -1&! +b00000000000000000000000000000001 ~ +1"! +b01000111 #! +b01000111 $! +b01000111 %! +b01000111 &! b01000111 '! b01000111 (! b01000111 )! @@ -767,90 +760,90 @@ b01000111 .! b01000111 /! b01000111 0! b01000111 1! -b01000111 2! -b01000111 3! -b01000111 4! +b01000111 5! +b01000111 6! +b01000111 7! b01000111 8! b01000111 9! b01000111 :! b01000111 ;! b01000111 ! -b01000111 ?! -b01000111 @! +b01000111 A! +b01000111 B! +b01000111 C! b01000111 D! b01000111 E! b01000111 F! b01000111 G! b01000111 H! b01000111 I! -b01000111 J! -b01000111 K! -b01000111 L! +b01000111 M! +b01000111 N! +b01000111 O! b01000111 P! b01000111 Q! b01000111 R! b01000111 S! b01000111 T! b01000111 U! -b01000111 V! -b01000111 W! -b01000111 X! +b01000111 Y! +b01000111 Z! +b01000111 [! b01000111 \! b01000111 ]! b01000111 ^! b01000111 _! b01000111 `! b01000111 a! -b01000111 b! -b01000111 c! -b01000111 d! +b01000111 e! +b01000111 f! +b01000111 g! b01000111 h! b01000111 i! b01000111 j! b01000111 k! b01000111 l! b01000111 m! -b01000111 n! -b01000111 o! -b01000111 p! +b01000111 q! +b01000111 r! +b01000111 s! b01000111 t! b01000111 u! b01000111 v! b01000111 w! b01000111 x! b01000111 y! -b01000111 z! -b01000111 {! -b01000111 |! +b01000111 }! +b01000111 ~! +b01000111 !" b01000111 "" b01000111 #" b01000111 $" b01000111 %" b01000111 &" b01000111 '" -b01000111 (" -b01000111 )" -b01000111 *" +b01000111 +" +b01000111 ," +b01000111 -" b01000111 ." b01000111 /" b01000111 0" b01000111 1" b01000111 2" b01000111 3" -b01000111 4" -b01000111 5" -b01000111 6" +b01000111 7" +b01000111 8" +b01000111 9" b01000111 :" b01000111 ;" b01000111 <" b01000111 =" b01000111 >" b01000111 ?" -b01000111 @" -b01000111 A" -b01000111 B" +b01000111 C" +b01000111 D" +b01000111 E" b01000111 F" b01000111 G" b01000111 H" @@ -858,24 +851,22 @@ b01000111 I" b01000111 J" b01000111 K" b01000111 L" -b01000111 M" -b01000111 N" -b01000111 O" -b00000000000000000000000001000111 P" -b00000000000000000000000001000111 Q" -b00000000000000000000000001000111 R" -b01000111 S" -b10001110010001110100011101000111 T" -b01000111 U" -b10001110010001110100011101000111 V" -b01000111 W" -b10001110010001110100011101000111 X" -b01000111 Y" -b10001110010001110100011101000111 Z" -1[" +b00000000000000000000000001000111 M" +b00000000000000000000000001000111 N" +b00000000000000000000000001000111 O" +b01000111 P" +b10001110010001110100011101000111 Q" +b01000111 R" +b10001110010001110100011101000111 S" +b01000111 T" +b10001110010001110100011101000111 U" +b01000111 V" +b10001110010001110100011101000111 W" +1X" #15 -0[" +0X" #20 +b10100011 , b10100011 - b10100011 . b10100011 / @@ -886,170 +877,170 @@ b10100011 3 b10100011 4 b10100011 5 b10100011 6 -b10100011 7 +b10001110 : b10001110 ; b10001110 < -b10001110 = +b10100011 = b10100011 > b10100011 ? b10100011 @ b10100011 A -b10100011 B +b10001110 E b10001110 F b10001110 G -b10001110 H +b10100011 H b10100011 I b10100011 J b10100011 K b10100011 L b10100011 M b10100011 N -b10100011 O -1P -0Q -1R -0U -0Z -1] -0^ -1_ -0b -1e -0f -1g -b010 h +1O +0P +1Q +0T +0Y +1\ +0] +1^ +0a +1d +0e +1f +b010 g +b0101100100001000010101011110011 h b0101100100001000010101011110011 i -b0101100100001000010101011110011 j +b101000111 j b101000111 k b101000111 l b101000111 m -b101000111 n -b010001110 p +1o 1s 1w 1{ -1!! -b00000000000000000000000000000010 $! +b00000000000000000000000000000010 ~ +b10100011 #! +b10100011 $! +b10001110 %! +b10100011 &! b10100011 '! b10100011 (! -b10001110 )! -b10100011 *! +b10100011 )! +b10001110 *! b10100011 +! b10100011 ,! -b10001110 -! +b10100011 -! b10100011 .! b10100011 /! b10100011 0! b10100011 1! -b10100011 2! -b10100011 3! -b10100011 4! -b10001110 8! -b10001110 9! -b10001110 :! +b10001110 5! +b10001110 6! +b10001110 7! +b10100011 8! +b10100011 9! +b10100011 :! b10100011 ;! b10100011 ! -b10100011 ?! -b10100011 @! -b10001110 D! -b10001110 E! -b10001110 F! +b10001110 A! +b10001110 B! +b10001110 C! +b10100011 D! +b10100011 E! +b10100011 F! b10100011 G! b10100011 H! b10100011 I! -b10100011 J! -b10100011 K! -b10100011 L! -b10001110 P! -b10001110 Q! -b10001110 R! +b10001110 M! +b10001110 N! +b10001110 O! +b10100011 P! +b10100011 Q! +b10100011 R! b10100011 S! b10100011 T! b10100011 U! -b10100011 V! -b10100011 W! -b10100011 X! -b10001110 \! -b10001110 ]! -b10001110 ^! +b10001110 Y! +b10001110 Z! +b10001110 [! +b10100011 \! +b10100011 ]! +b10100011 ^! b10100011 _! b10100011 `! b10100011 a! -b10100011 b! -b10100011 c! -b10100011 d! -b10001110 h! -b10001110 i! -b10001110 j! +b10001110 e! +b10001110 f! +b10001110 g! +b10100011 h! +b10100011 i! +b10100011 j! b10100011 k! b10100011 l! b10100011 m! -b10100011 n! -b10100011 o! -b10100011 p! -b10001110 t! -b10001110 u! -b10001110 v! +b10001110 q! +b10001110 r! +b10001110 s! +b10100011 t! +b10100011 u! +b10100011 v! b10100011 w! b10100011 x! b10100011 y! -b10100011 z! -b10100011 {! -b10100011 |! -b10001110 "" -b10001110 #" -b10001110 $" +b10001110 }! +b10001110 ~! +b10001110 !" +b10100011 "" +b10100011 #" +b10100011 $" b10100011 %" b10100011 &" b10100011 '" -b10100011 (" -b10100011 )" -b10100011 *" -b10001110 ." -b10001110 /" -b10001110 0" +b10001110 +" +b10001110 ," +b10001110 -" +b10100011 ." +b10100011 /" +b10100011 0" b10100011 1" b10100011 2" b10100011 3" -b10100011 4" -b10100011 5" -b10100011 6" -b10001110 :" -b10001110 ;" -b10001110 <" +b10001110 7" +b10001110 8" +b10001110 9" +b10100011 :" +b10100011 ;" +b10100011 <" b10100011 =" b10100011 >" b10100011 ?" -b10100011 @" -b10100011 A" -b10100011 B" -b10001110 F" -b10001110 G" -b10001110 H" +b10001110 C" +b10001110 D" +b10001110 E" +b10100011 F" +b10100011 G" +b10100011 H" b10100011 I" b10100011 J" b10100011 K" b10100011 L" -b10100011 M" -b10100011 N" -b10100011 O" -b00000000000000000000000010001110 P" -b00000000000000000000000010100011 Q" -b00000000000000000000000010100011 R" -b10100011 S" -b10001110100011101010001110100011 T" -b10100011 U" -b10001110100011101010001110100011 V" -b10100011 W" -b10001110100011101010001110100011 X" -b10100011 Y" -b10001110100011101010001110100011 Z" -1[" +b00000000000000000000000010001110 M" +b00000000000000000000000010100011 N" +b00000000000000000000000010100011 O" +b10100011 P" +b10001110100011101010001110100011 Q" +b10100011 R" +b10001110100011101010001110100011 S" +b10100011 T" +b10001110100011101010001110100011 U" +b10100011 V" +b10001110100011101010001110100011 W" +1X" #25 -0[" +0X" #30 +b11010001 , b11010001 - b11010001 . b11010001 / @@ -1060,170 +1051,170 @@ b11010001 3 b11010001 4 b11010001 5 b11010001 6 -b11010001 7 +b01000111 : b01000111 ; b01000111 < -b01000111 = +b11010001 = b11010001 > b11010001 ? b11010001 @ b11010001 A -b11010001 B +b01000111 E b01000111 F b01000111 G -b01000111 H +b11010001 H b11010001 I b11010001 J b11010001 K b11010001 L b11010001 M b11010001 N -b11010001 O -1Q -0R -1S -0V -0Y -1\ -0] -1^ -0a -1d -0e -1f -b011 h +1P +0Q +1R +0U +0X +1[ +0\ +1] +0` +1c +0d +1e +b011 g +b1010110010000100001010101111001 h b1010110010000100001010101111001 i -b1010110010000100001010101111001 j +b110100011 j b110100011 k b110100011 l b110100011 m -b110100011 n -b101000111 p +1p 1t 1x 1| -1"! -b00000000000000000000000000000011 $! +b00000000000000000000000000000011 ~ +b11010001 #! +b11010001 $! +b01000111 %! +b11010001 &! b11010001 '! b11010001 (! -b01000111 )! -b11010001 *! +b11010001 )! +b01000111 *! b11010001 +! b11010001 ,! -b01000111 -! +b11010001 -! b11010001 .! b11010001 /! b11010001 0! b11010001 1! -b11010001 2! -b11010001 3! -b11010001 4! -b01000111 8! -b01000111 9! -b01000111 :! +b01000111 5! +b01000111 6! +b01000111 7! +b11010001 8! +b11010001 9! +b11010001 :! b11010001 ;! b11010001 ! -b11010001 ?! -b11010001 @! -b01000111 D! -b01000111 E! -b01000111 F! +b01000111 A! +b01000111 B! +b01000111 C! +b11010001 D! +b11010001 E! +b11010001 F! b11010001 G! b11010001 H! b11010001 I! -b11010001 J! -b11010001 K! -b11010001 L! -b01000111 P! -b01000111 Q! -b01000111 R! +b01000111 M! +b01000111 N! +b01000111 O! +b11010001 P! +b11010001 Q! +b11010001 R! b11010001 S! b11010001 T! b11010001 U! -b11010001 V! -b11010001 W! -b11010001 X! -b01000111 \! -b01000111 ]! -b01000111 ^! +b01000111 Y! +b01000111 Z! +b01000111 [! +b11010001 \! +b11010001 ]! +b11010001 ^! b11010001 _! b11010001 `! b11010001 a! -b11010001 b! -b11010001 c! -b11010001 d! -b01000111 h! -b01000111 i! -b01000111 j! +b01000111 e! +b01000111 f! +b01000111 g! +b11010001 h! +b11010001 i! +b11010001 j! b11010001 k! b11010001 l! b11010001 m! -b11010001 n! -b11010001 o! -b11010001 p! -b01000111 t! -b01000111 u! -b01000111 v! +b01000111 q! +b01000111 r! +b01000111 s! +b11010001 t! +b11010001 u! +b11010001 v! b11010001 w! b11010001 x! b11010001 y! -b11010001 z! -b11010001 {! -b11010001 |! -b01000111 "" -b01000111 #" -b01000111 $" +b01000111 }! +b01000111 ~! +b01000111 !" +b11010001 "" +b11010001 #" +b11010001 $" b11010001 %" b11010001 &" b11010001 '" -b11010001 (" -b11010001 )" -b11010001 *" -b01000111 ." -b01000111 /" -b01000111 0" +b01000111 +" +b01000111 ," +b01000111 -" +b11010001 ." +b11010001 /" +b11010001 0" b11010001 1" b11010001 2" b11010001 3" -b11010001 4" -b11010001 5" -b11010001 6" -b01000111 :" -b01000111 ;" -b01000111 <" +b01000111 7" +b01000111 8" +b01000111 9" +b11010001 :" +b11010001 ;" +b11010001 <" b11010001 =" b11010001 >" b11010001 ?" -b11010001 @" -b11010001 A" -b11010001 B" -b01000111 F" -b01000111 G" -b01000111 H" +b01000111 C" +b01000111 D" +b01000111 E" +b11010001 F" +b11010001 G" +b11010001 H" b11010001 I" b11010001 J" b11010001 K" b11010001 L" -b11010001 M" -b11010001 N" -b11010001 O" -b00000000000000000000000001000111 P" -b00000000000000000000000011010001 Q" -b00000000000000000000000011010001 R" -b11010001 S" -b10001110010001111101000111010001 T" -b11010001 U" -b10001110010001111101000111010001 V" -b11010001 W" -b10001110010001111101000111010001 X" -b11010001 Y" -b10001110010001111101000111010001 Z" -1[" +b00000000000000000000000001000111 M" +b00000000000000000000000011010001 N" +b00000000000000000000000011010001 O" +b11010001 P" +b10001110010001111101000111010001 Q" +b11010001 R" +b10001110010001111101000111010001 S" +b11010001 T" +b10001110010001111101000111010001 U" +b11010001 V" +b10001110010001111101000111010001 W" +1X" #35 -0[" +0X" #40 +b11101000 , b11101000 - b11101000 . b11101000 / @@ -1234,170 +1225,170 @@ b11101000 3 b11101000 4 b11101000 5 b11101000 6 -b11101000 7 +b10001110 : b10001110 ; b10001110 < b10001110 = b10001110 > b10001110 ? -b10001110 @ +b11101000 @ b11101000 A -b11101000 B +b10001110 E b10001110 F b10001110 G b10001110 H b10001110 I b10001110 J -b10001110 K +b11101000 K b11101000 L b11101000 M b11101000 N -b11101000 O -1R -0S -1T +1Q +0R +1S +0V 0W -0X -1[ -0\ -1] -0` -1c -0d -1e -b100 h +1Z +0[ +1\ +0_ +1b +0c +1d +b100 g +b1101011001000010000101010111100 h b1101011001000010000101010111100 i -b1101011001000010000101010111100 j +b011010001 j b011010001 k b011010001 l b011010001 m -b011010001 n -b110100011 p +1q 1u 1y 1} -1#! -b00000000000000000000000000000100 $! +b00000000000000000000000000000100 ~ +b11101000 #! +b10001110 $! +b10001110 %! +b11101000 &! b11101000 '! b10001110 (! -b10001110 )! -b11101000 *! +b11101000 )! +b10001110 *! b10001110 +! -b11101000 ,! +b10001110 ,! b10001110 -! b10001110 .! -b10001110 /! -b10001110 0! -b10001110 1! -b11101000 2! -b11101000 3! -b11101000 4! +b11101000 /! +b11101000 0! +b11101000 1! +b10001110 5! +b10001110 6! +b10001110 7! b10001110 8! b10001110 9! b10001110 :! -b10001110 ;! -b10001110 ! -b11101000 ?! -b11101000 @! +b11101000 ;! +b11101000 " -b10001110 ?" -b11101000 @" -b11101000 A" -b11101000 B" +b11101000 =" +b11101000 >" +b11101000 ?" +b10001110 C" +b10001110 D" +b10001110 E" b10001110 F" b10001110 G" b10001110 H" -b10001110 I" -b10001110 J" -b10001110 K" +b11101000 I" +b11101000 J" +b11101000 K" b11101000 L" -b11101000 M" -b11101000 N" -b11101000 O" -b00000000000000000000000010001110 P" -b00000000000000000000000010001110 Q" -b00000000000000000000000011101000 R" -b11101000 S" -b10001110100011101000111011101000 T" -b11101000 U" -b10001110100011101000111011101000 V" -b11101000 W" -b10001110100011101000111011101000 X" -b11101000 Y" -b10001110100011101000111011101000 Z" -1[" +b00000000000000000000000010001110 M" +b00000000000000000000000010001110 N" +b00000000000000000000000011101000 O" +b11101000 P" +b10001110100011101000111011101000 Q" +b11101000 R" +b10001110100011101000111011101000 S" +b11101000 T" +b10001110100011101000111011101000 U" +b11101000 V" +b10001110100011101000111011101000 W" +1X" #45 -0[" +0X" #50 +b01110100 , b01110100 - b01110100 . b01110100 / @@ -1408,166 +1399,166 @@ b01110100 3 b01110100 4 b01110100 5 b01110100 6 -b01110100 7 +b01000111 : b01000111 ; b01000111 < b01000111 = b01000111 > b01000111 ? -b01000111 @ +b01110100 @ b01110100 A -b01110100 B +b01000111 E b01000111 F b01000111 G b01000111 H b01000111 I b01000111 J -b01000111 K +b01110100 K b01110100 L b01110100 M b01110100 N -b01110100 O -0P -1S -0T -1U -1Z -0[ -1\ -0_ -1b -0c -1d -0g -b101 h +0O +1R +0S +1T +1Y +0Z +1[ +0^ +1a +0b +1c +0f +b101 g +b0110101100100001000010101011110 h b0110101100100001000010101011110 i -b0110101100100001000010101011110 j +b001101000 j b001101000 k b001101000 l b001101000 m -b001101000 n -b011010001 p -b00000000000000000000000000000101 $! +b00000000000000000000000000000101 ~ +b01110100 #! +b01000111 $! +b01000111 %! +b01110100 &! b01110100 '! b01000111 (! -b01000111 )! -b01110100 *! +b01110100 )! +b01000111 *! b01000111 +! -b01110100 ,! +b01000111 ,! b01000111 -! b01000111 .! -b01000111 /! -b01000111 0! -b01000111 1! -b01110100 2! -b01110100 3! -b01110100 4! +b01110100 /! +b01110100 0! +b01110100 1! +b01000111 5! +b01000111 6! +b01000111 7! b01000111 8! b01000111 9! b01000111 :! -b01000111 ;! -b01000111 ! -b01110100 ?! -b01110100 @! +b01110100 ;! +b01110100 " -b01000111 ?" -b01110100 @" -b01110100 A" -b01110100 B" +b01110100 =" +b01110100 >" +b01110100 ?" +b01000111 C" +b01000111 D" +b01000111 E" b01000111 F" b01000111 G" b01000111 H" -b01000111 I" -b01000111 J" -b01000111 K" +b01110100 I" +b01110100 J" +b01110100 K" b01110100 L" -b01110100 M" -b01110100 N" -b01110100 O" -b00000000000000000000000001000111 P" -b00000000000000000000000001000111 Q" -b00000000000000000000000001110100 R" -b01110100 S" -b10001110010001110100011101110100 T" -b01110100 U" -b10001110010001110100011101110100 V" -b01110100 W" -b10001110010001110100011101110100 X" -b01110100 Y" -b10001110010001110100011101110100 Z" -1[" +b00000000000000000000000001000111 M" +b00000000000000000000000001000111 N" +b00000000000000000000000001110100 O" +b01110100 P" +b10001110010001110100011101110100 Q" +b01110100 R" +b10001110010001110100011101110100 S" +b01110100 T" +b10001110010001110100011101110100 U" +b01110100 V" +b10001110010001110100011101110100 W" +1X" #55 -0[" +0X" #60 +b00111010 , b00111010 - b00111010 . b00111010 / @@ -1578,166 +1569,166 @@ b00111010 3 b00111010 4 b00111010 5 b00111010 6 -b00111010 7 +b10001110 : b10001110 ; b10001110 < -b10001110 = +b10100011 = b10100011 > b10100011 ? -b10100011 @ +b00111010 @ b00111010 A -b00111010 B +b10001110 E b10001110 F b10001110 G -b10001110 H +b10100011 H b10100011 I b10100011 J -b10100011 K +b00111010 K b00111010 L b00111010 M b00111010 N -b00111010 O -0Q -1T -0U -1V -1Y -0Z -1[ -0^ -1a -0b -1c -0f -b110 h +0P +1S +0T +1U +1X +0Y +1Z +0] +1` +0a +1b +0e +b110 g +b0011010110010000100001010101111 h b0011010110010000100001010101111 i -b0011010110010000100001010101111 j +b100110100 j b100110100 k b100110100 l b100110100 m -b100110100 n -b001101000 p -b00000000000000000000000000000110 $! +b00000000000000000000000000000110 ~ +b00111010 #! +b10100011 $! +b10001110 %! +b00111010 &! b00111010 '! b10100011 (! -b10001110 )! -b00111010 *! +b00111010 )! +b10001110 *! b10100011 +! -b00111010 ,! -b10001110 -! +b10100011 ,! +b10100011 -! b10100011 .! -b10100011 /! -b10100011 0! -b10100011 1! -b00111010 2! -b00111010 3! -b00111010 4! -b10001110 8! -b10001110 9! -b10001110 :! -b10100011 ;! -b10100011 ! -b00111010 ?! -b00111010 @! -b10001110 D! -b10001110 E! -b10001110 F! -b10100011 G! -b10100011 H! -b10100011 I! -b00111010 J! -b00111010 K! -b00111010 L! -b10001110 P! -b10001110 Q! -b10001110 R! -b10100011 S! -b10100011 T! -b10100011 U! -b00111010 V! -b00111010 W! -b00111010 X! -b10001110 \! -b10001110 ]! -b10001110 ^! -b10100011 _! -b10100011 `! -b10100011 a! -b00111010 b! -b00111010 c! -b00111010 d! -b10001110 h! -b10001110 i! -b10001110 j! -b10100011 k! -b10100011 l! -b10100011 m! -b00111010 n! -b00111010 o! -b00111010 p! -b10001110 t! -b10001110 u! -b10001110 v! -b10100011 w! -b10100011 x! -b10100011 y! -b00111010 z! -b00111010 {! -b00111010 |! -b10001110 "" -b10001110 #" -b10001110 $" -b10100011 %" -b10100011 &" -b10100011 '" -b00111010 (" -b00111010 )" -b00111010 *" -b10001110 ." -b10001110 /" -b10001110 0" -b10100011 1" -b10100011 2" -b10100011 3" -b00111010 4" -b00111010 5" -b00111010 6" -b10001110 :" -b10001110 ;" -b10001110 <" -b10100011 =" -b10100011 >" -b10100011 ?" -b00111010 @" -b00111010 A" -b00111010 B" -b10001110 F" -b10001110 G" -b10001110 H" -b10100011 I" -b10100011 J" -b10100011 K" +b00111010 /! +b00111010 0! +b00111010 1! +b10001110 5! +b10001110 6! +b10001110 7! +b10100011 8! +b10100011 9! +b10100011 :! +b00111010 ;! +b00111010 " +b00111010 ?" +b10001110 C" +b10001110 D" +b10001110 E" +b10100011 F" +b10100011 G" +b10100011 H" +b00111010 I" +b00111010 J" +b00111010 K" b00111010 L" -b00111010 M" -b00111010 N" -b00111010 O" -b00000000000000000000000010001110 P" -b00000000000000000000000010100011 Q" -b00000000000000000000000000111010 R" -b00111010 S" -b10001110100011101010001100111010 T" -b00111010 U" -b10001110100011101010001100111010 V" -b00111010 W" -b10001110100011101010001100111010 X" -b00111010 Y" -b10001110100011101010001100111010 Z" -1[" +b00000000000000000000000010001110 M" +b00000000000000000000000010100011 N" +b00000000000000000000000000111010 O" +b00111010 P" +b10001110100011101010001100111010 Q" +b00111010 R" +b10001110100011101010001100111010 S" +b00111010 T" +b10001110100011101010001100111010 U" +b00111010 V" +b10001110100011101010001100111010 W" +1X" #65 -0[" +0X" #70 +b00011101 , b00011101 - b00011101 . b00011101 / @@ -1748,166 +1739,166 @@ b00011101 3 b00011101 4 b00011101 5 b00011101 6 -b00011101 7 +b01000111 : b01000111 ; b01000111 < -b01000111 = +b11010001 = b11010001 > b11010001 ? -b11010001 @ +b00011101 @ b00011101 A -b00011101 B +b01000111 E b01000111 F b01000111 G -b01000111 H +b11010001 H b11010001 I b11010001 J -b11010001 K +b00011101 K b00011101 L b00011101 M b00011101 N -b00011101 O -0R -1U -0V +0Q +1T +0U +1V 1W -1X -0Y -1Z -0] -1` -0a -1b -0e -b111 h +0X +1Y +0\ +1_ +0` +1a +0d +b111 g +b1001101011001000010000101010111 h b1001101011001000010000101010111 i -b1001101011001000010000101010111 j +b010011010 j b010011010 k b010011010 l b010011010 m -b010011010 n -b100110100 p -b00000000000000000000000000000111 $! +b00000000000000000000000000000111 ~ +b00011101 #! +b11010001 $! +b01000111 %! +b00011101 &! b00011101 '! b11010001 (! -b01000111 )! -b00011101 *! +b00011101 )! +b01000111 *! b11010001 +! -b00011101 ,! -b01000111 -! +b11010001 ,! +b11010001 -! b11010001 .! -b11010001 /! -b11010001 0! -b11010001 1! -b00011101 2! -b00011101 3! -b00011101 4! -b01000111 8! -b01000111 9! -b01000111 :! -b11010001 ;! -b11010001 ! -b00011101 ?! -b00011101 @! -b01000111 D! -b01000111 E! -b01000111 F! -b11010001 G! -b11010001 H! -b11010001 I! -b00011101 J! -b00011101 K! -b00011101 L! -b01000111 P! -b01000111 Q! -b01000111 R! -b11010001 S! -b11010001 T! -b11010001 U! -b00011101 V! -b00011101 W! -b00011101 X! -b01000111 \! -b01000111 ]! -b01000111 ^! -b11010001 _! -b11010001 `! -b11010001 a! -b00011101 b! -b00011101 c! -b00011101 d! -b01000111 h! -b01000111 i! -b01000111 j! -b11010001 k! -b11010001 l! -b11010001 m! -b00011101 n! -b00011101 o! -b00011101 p! -b01000111 t! -b01000111 u! -b01000111 v! -b11010001 w! -b11010001 x! -b11010001 y! -b00011101 z! -b00011101 {! -b00011101 |! -b01000111 "" -b01000111 #" -b01000111 $" -b11010001 %" -b11010001 &" -b11010001 '" -b00011101 (" -b00011101 )" -b00011101 *" -b01000111 ." -b01000111 /" -b01000111 0" -b11010001 1" -b11010001 2" -b11010001 3" -b00011101 4" -b00011101 5" -b00011101 6" -b01000111 :" -b01000111 ;" -b01000111 <" -b11010001 =" -b11010001 >" -b11010001 ?" -b00011101 @" -b00011101 A" -b00011101 B" -b01000111 F" -b01000111 G" -b01000111 H" -b11010001 I" -b11010001 J" -b11010001 K" +b00011101 /! +b00011101 0! +b00011101 1! +b01000111 5! +b01000111 6! +b01000111 7! +b11010001 8! +b11010001 9! +b11010001 :! +b00011101 ;! +b00011101 " +b00011101 ?" +b01000111 C" +b01000111 D" +b01000111 E" +b11010001 F" +b11010001 G" +b11010001 H" +b00011101 I" +b00011101 J" +b00011101 K" b00011101 L" -b00011101 M" -b00011101 N" -b00011101 O" -b00000000000000000000000001000111 P" -b00000000000000000000000011010001 Q" -b00000000000000000000000000011101 R" -b00011101 S" -b10001110010001111101000100011101 T" -b00011101 U" -b10001110010001111101000100011101 V" -b00011101 W" -b10001110010001111101000100011101 X" -b00011101 Y" -b10001110010001111101000100011101 Z" -1[" +b00000000000000000000000001000111 M" +b00000000000000000000000011010001 N" +b00000000000000000000000000011101 O" +b00011101 P" +b10001110010001111101000100011101 Q" +b00011101 R" +b10001110010001111101000100011101 S" +b00011101 T" +b10001110010001111101000100011101 U" +b00011101 V" +b10001110010001111101000100011101 W" +1X" #75 -0[" +0X" #80 +b10001110 , b10001110 - b10001110 . b10001110 / @@ -1918,7 +1909,7 @@ b10001110 3 b10001110 4 b10001110 5 b10001110 6 -b10001110 7 +b10001110 : b10001110 ; b10001110 < b10001110 = @@ -1926,7 +1917,7 @@ b10001110 > b10001110 ? b10001110 @ b10001110 A -b10001110 B +b10001110 E b10001110 F b10001110 G b10001110 H @@ -1936,28 +1927,30 @@ b10001110 K b10001110 L b10001110 M b10001110 N -b10001110 O -1P -0S -1V +1O +0R +1U +0V 0W -0X -1Y -0\ -1_ -0` -1a -0d -1g -b000 h +1X +0[ +1^ +0_ +1` +0c +1f +b000 g +b1100110101100100001000010101011 h b1100110101100100001000010101011 i -b1100110101100100001000010101011 j +b001001101 j b001001101 k b001001101 l b001001101 m -b001001101 n -b010011010 p -b00000000000000000000000000001000 $! +b00000000000000000000000000001000 ~ +b10001110 #! +b10001110 $! +b10001110 %! +b10001110 &! b10001110 '! b10001110 (! b10001110 )! @@ -1969,90 +1962,90 @@ b10001110 .! b10001110 /! b10001110 0! b10001110 1! -b10001110 2! -b10001110 3! -b10001110 4! +b10001110 5! +b10001110 6! +b10001110 7! b10001110 8! b10001110 9! b10001110 :! b10001110 ;! b10001110 ! -b10001110 ?! -b10001110 @! +b10001110 A! +b10001110 B! +b10001110 C! b10001110 D! b10001110 E! b10001110 F! b10001110 G! b10001110 H! b10001110 I! -b10001110 J! -b10001110 K! -b10001110 L! +b10001110 M! +b10001110 N! +b10001110 O! b10001110 P! b10001110 Q! b10001110 R! b10001110 S! b10001110 T! b10001110 U! -b10001110 V! -b10001110 W! -b10001110 X! +b10001110 Y! +b10001110 Z! +b10001110 [! b10001110 \! b10001110 ]! b10001110 ^! b10001110 _! b10001110 `! b10001110 a! -b10001110 b! -b10001110 c! -b10001110 d! +b10001110 e! +b10001110 f! +b10001110 g! b10001110 h! b10001110 i! b10001110 j! b10001110 k! b10001110 l! b10001110 m! -b10001110 n! -b10001110 o! -b10001110 p! +b10001110 q! +b10001110 r! +b10001110 s! b10001110 t! b10001110 u! b10001110 v! b10001110 w! b10001110 x! b10001110 y! -b10001110 z! -b10001110 {! -b10001110 |! +b10001110 }! +b10001110 ~! +b10001110 !" b10001110 "" b10001110 #" b10001110 $" b10001110 %" b10001110 &" b10001110 '" -b10001110 (" -b10001110 )" -b10001110 *" +b10001110 +" +b10001110 ," +b10001110 -" b10001110 ." b10001110 /" b10001110 0" b10001110 1" b10001110 2" b10001110 3" -b10001110 4" -b10001110 5" -b10001110 6" +b10001110 7" +b10001110 8" +b10001110 9" b10001110 :" b10001110 ;" b10001110 <" b10001110 =" b10001110 >" b10001110 ?" -b10001110 @" -b10001110 A" -b10001110 B" +b10001110 C" +b10001110 D" +b10001110 E" b10001110 F" b10001110 G" b10001110 H" @@ -2060,18 +2053,15 @@ b10001110 I" b10001110 J" b10001110 K" b10001110 L" -b10001110 M" -b10001110 N" -b10001110 O" -b00000000000000000000000010001110 P" -b00000000000000000000000010001110 Q" -b00000000000000000000000010001110 R" -b10001110 S" -b10001110100011101000111010001110 T" -b10001110 U" -b10001110100011101000111010001110 V" -b10001110 W" -b10001110100011101000111010001110 X" -b10001110 Y" -b10001110100011101000111010001110 Z" -1[" +b00000000000000000000000010001110 M" +b00000000000000000000000010001110 N" +b00000000000000000000000010001110 O" +b10001110 P" +b10001110100011101000111010001110 Q" +b10001110 R" +b10001110100011101000111010001110 S" +b10001110 T" +b10001110100011101000111010001110 U" +b10001110 V" +b10001110100011101000111010001110 W" +1X" diff --git a/test_regress/t/t_split_var_2_trace.py b/test_regress/t/t_split_var_2_trace.py index 0fcaf3d8c..17b121bfd 100755 --- a/test_regress/t/t_split_var_2_trace.py +++ b/test_regress/t/t_split_var_2_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_split_var_3_wreal.py b/test_regress/t/t_split_var_3_wreal.py index 8860c1644..6ef5630c5 100755 --- a/test_regress/t/t_split_var_3_wreal.py +++ b/test_regress/t/t_split_var_3_wreal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_split_var_3_wreal.v b/test_regress/t/t_split_var_3_wreal.v index 46cca2e2a..135508eb7 100644 --- a/test_regress/t/t_split_var_3_wreal.v +++ b/test_regress/t/t_split_var_3_wreal.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Yutetsu TAKATSUKASA. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" diff --git a/test_regress/t/t_split_var_4.py b/test_regress/t/t_split_var_4.py index 4a461e645..9a537e5d1 100755 --- a/test_regress/t/t_split_var_4.py +++ b/test_regress/t/t_split_var_4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_split_var_4.v b/test_regress/t/t_split_var_4.v index 7b8a475bc..697399b2c 100644 --- a/test_regress/t/t_split_var_4.v +++ b/test_regress/t/t_split_var_4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 Yutetsu TAKATSUKASA. +// SPDX-FileCopyrightText: 2021 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 `ifdef ENABLE_SPLIT_VAR diff --git a/test_regress/t/t_split_var_5.py b/test_regress/t/t_split_var_5.py index 12d5eaabe..02b633344 100755 --- a/test_regress/t/t_split_var_5.py +++ b/test_regress/t/t_split_var_5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_split_var_auto.py b/test_regress/t/t_split_var_auto.py index 7936e760b..4e9240bde 100755 --- a/test_regress/t/t_split_var_auto.py +++ b/test_regress/t/t_split_var_auto.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_split_var_auto.v b/test_regress/t/t_split_var_auto.v index 8055bc9a1..25140d6ce 100644 --- a/test_regress/t/t_split_var_auto.v +++ b/test_regress/t/t_split_var_auto.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_split_var_issue.py b/test_regress/t/t_split_var_issue.py index 519ab4887..ff0625848 100755 --- a/test_regress/t/t_split_var_issue.py +++ b/test_regress/t/t_split_var_issue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_split_var_issue.v b/test_regress/t/t_split_var_issue.v index daf23cb9c..2f426a83b 100644 --- a/test_regress/t/t_split_var_issue.v +++ b/test_regress/t/t_split_var_issue.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module other_sub ( diff --git a/test_regress/t/t_split_var_types.py b/test_regress/t/t_split_var_types.py index 3fac9c971..e60c66adb 100755 --- a/test_regress/t/t_split_var_types.py +++ b/test_regress/t/t_split_var_types.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_split_var_types.v b/test_regress/t/t_split_var_types.v index cb94f7002..d73bab308 100644 --- a/test_regress/t/t_split_var_types.v +++ b/test_regress/t/t_split_var_types.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_split_var_xref.py b/test_regress/t/t_split_var_xref.py index 3476171ff..276645160 100755 --- a/test_regress/t/t_split_var_xref.py +++ b/test_regress/t/t_split_var_xref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_split_var_xref.v b/test_regress/t/t_split_var_xref.v index 022ec212d..59c8ff740 100644 --- a/test_regress/t/t_split_var_xref.v +++ b/test_regress/t/t_split_var_xref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module child ( diff --git a/test_regress/t/t_srandom_class_dep.py b/test_regress/t/t_srandom_class_dep.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_srandom_class_dep.py +++ b/test_regress/t/t_srandom_class_dep.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_srandom_class_dep.v b/test_regress/t/t_srandom_class_dep.v index 0e115dae1..300f3d37a 100644 --- a/test_regress/t/t_srandom_class_dep.v +++ b/test_regress/t/t_srandom_class_dep.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef class Cls; diff --git a/test_regress/t/t_stack_check.py b/test_regress/t/t_stack_check.py index 34009ba06..ac1ee2bf6 100755 --- a/test_regress/t/t_stack_check.py +++ b/test_regress/t/t_stack_check.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stack_check.v b/test_regress/t/t_stack_check.v index b545d8961..930c8a006 100644 --- a/test_regress/t/t_stack_check.v +++ b/test_regress/t/t_stack_check.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_stack_check_fail.py b/test_regress/t/t_stack_check_fail.py index fee5f470b..111e8bb29 100755 --- a/test_regress/t/t_stack_check_fail.py +++ b/test_regress/t/t_stack_check_fail.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stacktrace.py b/test_regress/t/t_stacktrace.py index d4f986441..09a3510fb 100755 --- a/test_regress/t/t_stacktrace.py +++ b/test_regress/t/t_stacktrace.py @@ -1,17 +1,17 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') -test.compile() +test.compile(verilator_flags2=['-CFLAGS -ggdb -LDFLAGS -ggdb -LDFLAGS -rdynamic']) test.execute() diff --git a/test_regress/t/t_stacktrace.v b/test_regress/t/t_stacktrace.v index b8ad7e34d..1ce27843e 100644 --- a/test_regress/t/t_stacktrace.v +++ b/test_regress/t/t_stacktrace.v @@ -1,27 +1,27 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - task automatic t; - // verilator no_inline_task - string trace; + task automatic t; + // verilator no_inline_task + string trace; - $display("== Trace Func"); - trace = $stacktrace(); - if (trace == "") $stop; - $display("%s", trace); + $display("== Trace Func"); + trace = $stacktrace(); + if (trace == "") $stop; + $display("%s", trace); - $display("== Trace Task"); - $stacktrace; + $display("== Trace Task"); + $stacktrace; - $write("*-* All Finished *-*\n"); - $finish; - endtask + $write("*-* All Finished *-*\n"); + $finish; + endtask - initial t(); + initial t(); endmodule diff --git a/test_regress/t/t_static_dup_name.py b/test_regress/t/t_static_dup_name.py index 629441927..af8b14903 100755 --- a/test_regress/t/t_static_dup_name.py +++ b/test_regress/t/t_static_dup_name.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_static_dup_name.v b/test_regress/t/t_static_dup_name.v index e4155526e..66b489970 100644 --- a/test_regress/t/t_static_dup_name.v +++ b/test_regress/t/t_static_dup_name.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_static_elab.py b/test_regress/t/t_static_elab.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_static_elab.py +++ b/test_regress/t/t_static_elab.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_static_elab.v b/test_regress/t/t_static_elab.v index d845db15c..013b5ed93 100644 --- a/test_regress/t/t_static_elab.v +++ b/test_regress/t/t_static_elab.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Simple static elaboration case // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_static_function_in_class.py b/test_regress/t/t_static_function_in_class.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_static_function_in_class.py +++ b/test_regress/t/t_static_function_in_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_static_function_in_class.v b/test_regress/t/t_static_function_in_class.v index 7911e81fe..b03eb9b6a 100644 --- a/test_regress/t/t_static_function_in_class.v +++ b/test_regress/t/t_static_function_in_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Simple static elaboration case // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Todd Strader // SPDX-License-Identifier: CC0-1.0 class string_utils; diff --git a/test_regress/t/t_static_function_in_class_noparen.py b/test_regress/t/t_static_function_in_class_noparen.py new file mode 100755 index 000000000..3cc73805c --- /dev/null +++ b/test_regress/t/t_static_function_in_class_noparen.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_function_in_class_call_without_parentheses.v b/test_regress/t/t_static_function_in_class_noparen.v similarity index 91% rename from test_regress/t/t_static_function_in_class_call_without_parentheses.v rename to test_regress/t/t_static_function_in_class_noparen.v index 4c125d7ff..654751306 100644 --- a/test_regress/t/t_static_function_in_class_call_without_parentheses.v +++ b/test_regress/t/t_static_function_in_class_noparen.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_static_in_loop.py b/test_regress/t/t_static_in_loop.py new file mode 100755 index 000000000..60a79a36b --- /dev/null +++ b/test_regress/t/t_static_in_loop.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_static_in_loop.v" + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_static_in_loop.v b/test_regress/t/t_static_in_loop.v new file mode 100644 index 000000000..4cf527329 --- /dev/null +++ b/test_regress/t/t_static_in_loop.v @@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + static int x = 0; + while (x < 10) begin : outer_loop + static int y = 0; + while (y < x) begin : inner_loop + static int a = 0; + a++; + y++; + end + x++; + end + if (outer_loop.inner_loop.a != 9) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_static_in_loop_unsup.out b/test_regress/t/t_static_in_loop_unsup.out index 0070d8d3f..48eb55263 100644 --- a/test_regress/t/t_static_in_loop_unsup.out +++ b/test_regress/t/t_static_in_loop_unsup.out @@ -1,6 +1,6 @@ -%Warning-STATICVAR: t/t_static_in_loop_unsup.v:14:24: Static variable with assignment declaration declared in a loop converted to automatic - 14 | static int a = 0; - | ^ +%Warning-STATICVAR: t/t_static_in_loop.v:13:20: Static variable with assignment declaration declared in a loop converted to automatic + 13 | static int a = 0; + | ^ ... For warning description see https://verilator.org/warn/STATICVAR?v=latest ... Use "/* verilator lint_off STATICVAR */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_static_in_loop_unsup.v b/test_regress/t/t_static_in_loop_unsup.v deleted file mode 100644 index 87c674688..000000000 --- a/test_regress/t/t_static_in_loop_unsup.v +++ /dev/null @@ -1,26 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. -// SPDX-License-Identifier: CC0-1.0 - - -module t; - initial begin - int x = 0; - while (x < 10) begin : outer_loop - int y = 0; - while (y < x) begin : inner_loop - static int a = 0; - a++; - y++; - end - x++; - end - if (outer_loop.inner_loop.a != 45) $stop; - - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_std_identifier.py b/test_regress/t/t_std_identifier.py index 6938ef706..5e48bb865 100755 --- a/test_regress/t/t_std_identifier.py +++ b/test_regress/t/t_std_identifier.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_identifier.v b/test_regress/t/t_std_identifier.v index 882fb5658..d1903f00b 100644 --- a/test_regress/t/t_std_identifier.v +++ b/test_regress/t/t_std_identifier.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 package foo; diff --git a/test_regress/t/t_std_identifier_bad.py b/test_regress/t/t_std_identifier_bad.py index cdc19d5ba..e6838ff3d 100755 --- a/test_regress/t/t_std_identifier_bad.py +++ b/test_regress/t/t_std_identifier_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_pkg_bad.py b/test_regress/t/t_std_pkg_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_std_pkg_bad.py +++ b/test_regress/t/t_std_pkg_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_pkg_bad.v b/test_regress/t/t_std_pkg_bad.v index c1969368e..efc83390e 100644 --- a/test_regress/t/t_std_pkg_bad.v +++ b/test_regress/t/t_std_pkg_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 package std; diff --git a/test_regress/t/t_std_process_self.py b/test_regress/t/t_std_process_self.py index 1211b1f6f..baeb93ae0 100755 --- a/test_regress/t/t_std_process_self.py +++ b/test_regress/t/t_std_process_self.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_process_self.v b/test_regress/t/t_std_process_self.v index ddcacedc8..9627bbaff 100644 --- a/test_regress/t/t_std_process_self.v +++ b/test_regress/t/t_std_process_self.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_std_process_self_std.py b/test_regress/t/t_std_process_self_std.py index 15da65e59..b99044e2f 100755 --- a/test_regress/t/t_std_process_self_std.py +++ b/test_regress/t/t_std_process_self_std.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_randomize.py b/test_regress/t/t_std_randomize.py index 466368b3d..8862c2c31 100755 --- a/test_regress/t/t_std_randomize.py +++ b/test_regress/t/t_std_randomize.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_randomize.v b/test_regress/t/t_std_randomize.v index e93c9a753..40f4906d7 100644 --- a/test_regress/t/t_std_randomize.v +++ b/test_regress/t/t_std_randomize.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_std_randomize_assoc.py b/test_regress/t/t_std_randomize_assoc.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_std_randomize_assoc.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_std_randomize_assoc.v b/test_regress/t/t_std_randomize_assoc.v new file mode 100644 index 000000000..a903214f2 --- /dev/null +++ b/test_regress/t/t_std_randomize_assoc.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop; +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +// Test std::randomize() with associative array variables + +module t_std_randomize_assoc; + + // Associative array variables + int assoc_int[int]; + bit [7:0] assoc_byte[string]; + + initial begin + // Test 1: std::randomize with int-keyed associative array (no constraints) + assoc_int[0] = 0; + assoc_int[1] = 0; + assoc_int[2] = 0; + `checkd(std::randomize(assoc_int), 1); + + // Test 2: std::randomize with string-keyed associative array + assoc_byte["a"] = 0; + assoc_byte["b"] = 0; + assoc_byte["c"] = 0; + `checkd(std::randomize(assoc_byte), 1); + + // Test 3: Multiple randomizations produce different values + begin + automatic int non_zero = 0; + repeat (5) begin + assoc_int[0] = 0; + assoc_int[1] = 0; + `checkd(std::randomize(assoc_int), 1); + if (assoc_int[0] != 0) non_zero++; + if (assoc_int[1] != 0) non_zero++; + end + // With 10 random int values, expect most non-zero + if (non_zero < 7) `stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_std_randomize_bad1.py b/test_regress/t/t_std_randomize_bad1.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_std_randomize_bad1.py +++ b/test_regress/t/t_std_randomize_bad1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_randomize_bad1.v b/test_regress/t/t_std_randomize_bad1.v index 5097f59e6..01a87f69a 100644 --- a/test_regress/t/t_std_randomize_bad1.v +++ b/test_regress/t/t_std_randomize_bad1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 module t_std_randomize_bad1; diff --git a/test_regress/t/t_std_randomize_mod.py b/test_regress/t/t_std_randomize_mod.py index 7dcbd6ae6..26440f70f 100755 --- a/test_regress/t/t_std_randomize_mod.py +++ b/test_regress/t/t_std_randomize_mod.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_randomize_mod.v b/test_regress/t/t_std_randomize_mod.v index f0dfbde87..4db4d6648 100644 --- a/test_regress/t/t_std_randomize_mod.v +++ b/test_regress/t/t_std_randomize_mod.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 module t_scope_std_randomize; @@ -28,7 +28,7 @@ module t_scope_std_randomize; endfunction initial begin - bit ok = 0; + automatic bit ok = 0; int success; ok = 0; diff --git a/test_regress/t/t_std_randomize_no_args.py b/test_regress/t/t_std_randomize_no_args.py index 7dcbd6ae6..26440f70f 100755 --- a/test_regress/t/t_std_randomize_no_args.py +++ b/test_regress/t/t_std_randomize_no_args.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_randomize_no_args.v b/test_regress/t/t_std_randomize_no_args.v index e2b52504c..ba0ec7f3a 100644 --- a/test_regress/t/t_std_randomize_no_args.v +++ b/test_regress/t/t_std_randomize_no_args.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 module t_no_args; diff --git a/test_regress/t/t_std_randomize_queue.py b/test_regress/t/t_std_randomize_queue.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_std_randomize_queue.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_std_randomize_queue.v b/test_regress/t/t_std_randomize_queue.v new file mode 100644 index 000000000..58ee816a5 --- /dev/null +++ b/test_regress/t/t_std_randomize_queue.v @@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop; +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +// Test std::randomize() with queue and dynamic array variables + +module t_std_randomize_queue; + + // Queue variables + bit [7:0] q8[$]; + bit [31:0] q32[$]; + + // Dynamic array variables + bit [7:0] dyn8[]; + + int i; + + initial begin + // Test 1: std::randomize with queue (no constraints) + q8 = {8'd0, 8'd0, 8'd0}; + `checkd(std::randomize(q8), 1); + + // Test 2: std::randomize with queue and constraints + q8 = {8'd0, 8'd0, 8'd0, 8'd0}; + `checkd(std::randomize(q8) with { + foreach (q8[j]) q8[j] > 8'd10 && q8[j] < 8'd100; + }, 1); + foreach (q8[j]) begin + if (q8[j] <= 8'd10 || q8[j] >= 8'd100) `stop; + end + + // Test 3: std::randomize with 32-bit queue + q32 = {32'd0, 32'd0, 32'd0}; + `checkd(std::randomize(q32) with { + foreach (q32[k]) q32[k] < 32'd1000; + }, 1); + foreach (q32[k]) begin + if (q32[k] >= 32'd1000) `stop; + end + + // Test 4: std::randomize with dynamic array + dyn8 = new[3]; + `checkd(std::randomize(dyn8) with { + foreach (dyn8[m]) dyn8[m] inside {[1:50]}; + }, 1); + foreach (dyn8[m]) begin + if (dyn8[m] < 1 || dyn8[m] > 50) `stop; + end + + // Test 5: Multiple randomizations produce different values + q8 = {8'd0, 8'd0, 8'd0}; + begin + automatic int non_zero = 0; + repeat (5) begin + `checkd(std::randomize(q8), 1); + foreach (q8[n]) if (q8[n] != 0) non_zero++; + end + // With 15 random 8-bit values, expect most non-zero + if (non_zero < 10) `stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_std_randomize_unsup_unq_arr.out b/test_regress/t/t_std_randomize_unsup_unq_arr.out new file mode 100644 index 000000000..94e7ccd26 --- /dev/null +++ b/test_regress/t/t_std_randomize_unsup_unq_arr.out @@ -0,0 +1,7 @@ +%Warning-CONSTRAINTIGN: t/t_std_randomize_unsup_unq_arr.v:10:39: Unsupported: Unique constraint in std::randomize() with {} + : ... note: In instance 't' + 10 | if (!bit'(std::randomize(x) with {unique {x};}) || x[0] == x[1]) $stop; + | ^~~~~~ + ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest + ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_std_randomize_unsup_unq_arr.py b/test_regress/t/t_std_randomize_unsup_unq_arr.py new file mode 100755 index 000000000..18ef27714 --- /dev/null +++ b/test_regress/t/t_std_randomize_unsup_unq_arr.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_std_randomize_unsup_unq_arr.v b/test_regress/t/t_std_randomize_unsup_unq_arr.v new file mode 100644 index 000000000..b0f6af776 --- /dev/null +++ b/test_regress/t/t_std_randomize_unsup_unq_arr.v @@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + bit x[2]; + if (!bit'(std::randomize(x) with {unique {x};}) || x[0] == x[1]) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_std_randomize_with.py b/test_regress/t/t_std_randomize_with.py index a2b131082..ab048b5e8 100755 --- a/test_regress/t/t_std_randomize_with.py +++ b/test_regress/t/t_std_randomize_with.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_randomize_with.v b/test_regress/t/t_std_randomize_with.v index 0c457184d..1428f763b 100644 --- a/test_regress/t/t_std_randomize_with.v +++ b/test_regress/t/t_std_randomize_with.v @@ -1,53 +1,98 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 class external_cl; - int x; - int y; + int x; + int y; + logic [7:0] dyn[][]; - function new(); - x = 0; - y = 0; - endfunction + function new(); + x = 0; + y = 0; + dyn = new[4]; + foreach (dyn[i]) dyn[i] = new[1]; + endfunction endclass module t; - initial begin - int a, b; - int limit = 10; - external_cl obj; + initial begin + int a, b; + automatic int limit = 10; + external_cl obj; - // Test 1: Basic std::randomize with 'with' clause - if (std::randomize(a, b) with { 2 < a; a < 7; b < a; } != 1) $stop; - if (!(2 < a && a < 7 && b < a)) $stop; - $display("Test 1 passed: a=%0d, b=%0d", a, b); + // Test 1: Basic std::randomize with 'with' clause + if (std::randomize( + a, b + ) with { + 2 < a; + a < 7; + b < a; + } != 1) + $stop; + if (!(2 < a && a < 7 && b < a)) $stop; + $display("Test 1 passed: a=%0d, b=%0d", a, b); - // Test 2: Local variable and class member with mutual constraints - obj = new; - if (std::randomize(a, obj.x) with { a > 10; a < 20; obj.x > a; obj.x < a + 5; } != 1) $stop; - if (!(a > 10 && a < 20 && obj.x > a && obj.x < a + 5)) $stop; - $display("Test 2 passed: a=%0d, obj.x=%0d (obj.x between a+1 and a+4)", a, obj.x); + // Test 2: Local variable and class member with mutual constraints + obj = new; + if (std::randomize( + a, obj.x + ) with { + a > 10; + a < 20; + obj.x > a; + obj.x < a + 5; + } != 1) + $stop; + if (!(a > 10 && a < 20 && obj.x > a && obj.x < a + 5)) $stop; + $display("Test 2 passed: a=%0d, obj.x=%0d (obj.x between a+1 and a+4)", a, obj.x); - // Test 3: Reference external variable in constraint - if (std::randomize(a) with { a > 0; a < limit; } != 1) $stop; - if (!(a > 0 && a < limit)) $stop; - $display("Test 3 passed: a=%0d, limit=%0d", a, limit); + // Test 3: Reference external variable in constraint + if (std::randomize( + a + ) with { + a > 0; + a < limit; + } != 1) + $stop; + if (!(a > 0 && a < limit)) $stop; + $display("Test 3 passed: a=%0d, limit=%0d", a, limit); - // Test 4: Randomize class member variables - obj = new; - if (std::randomize(obj.x, obj.y) with { obj.x > 5; obj.x < 20; obj.y == obj.x + 1; } != 1) $stop; - if (!(obj.x > 5 && obj.x < 20 && obj.y == obj.x + 1)) $stop; - $display("Test 4 passed: obj.x=%0d, obj.y=%0d", obj.x, obj.y); + // Test 4: Randomize class member variables + obj = new; + if (std::randomize( + obj.x, obj.y + ) with { + obj.x > 5; + obj.x < 20; + obj.y == obj.x + 1; + } != 1) + $stop; + if (!(obj.x > 5 && obj.x < 20 && obj.y == obj.x + 1)) $stop; + $display("Test 4 passed: obj.x=%0d, obj.y=%0d", obj.x, obj.y); - // Test 5: Multiple class members and local variable - if (std::randomize(a, obj.x, obj.y) with { a > 0; a < 5; obj.x > a; obj.y > obj.x; obj.y < a + 10; } != 1) $stop; - if (!(a > 0 && a < 5 && obj.x > a && obj.y > obj.x && obj.y < a + 10)) $stop; - $display("Test 5 passed: a=%0d, obj.x=%0d, obj.y=%0d", a, obj.x, obj.y); + // Test 5: Multiple class members and local variable + if (std::randomize( + a, obj.x, obj.y + ) with { + a > 0; + a < 5; + obj.x > a; + obj.y > obj.x; + obj.y < a + 10; + } != 1) + $stop; + if (!(a > 0 && a < 5 && obj.x > a && obj.y > obj.x && obj.y < a + 10)) $stop; + $display("Test 5 passed: a=%0d, obj.x=%0d, obj.y=%0d", a, obj.x, obj.y); - $write("*-* All Finished *-*\n"); - $finish; - end + // Test 6: Member of 2D array + assert (std::randomize(obj.dyn[2][0]) with {obj.dyn[2][0] inside {[1 : 10]};} == 1); + if (!(obj.dyn[2][0] inside {[1 : 10]})) $stop; + $display("Test 6 passed: obj.dyn[2][0]=%0d", obj.dyn[2][0]); + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_std_waiver.py b/test_regress/t/t_std_waiver.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_std_waiver.py +++ b/test_regress/t/t_std_waiver.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_waiver.v b/test_regress/t/t_std_waiver.v index 08cf87957..320289449 100644 --- a/test_regress/t/t_std_waiver.v +++ b/test_regress/t/t_std_waiver.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Rather than look at waivers, just check we included it diff --git a/test_regress/t/t_std_waiver_no.py b/test_regress/t/t_std_waiver_no.py index 2e67c6a6a..9678d8480 100755 --- a/test_regress/t/t_std_waiver_no.py +++ b/test_regress/t/t_std_waiver_no.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_std_waiver_no.v b/test_regress/t/t_std_waiver_no.v index 7cf201fb6..d0c7f6b9c 100644 --- a/test_regress/t/t_std_waiver_no.v +++ b/test_regress/t/t_std_waiver_no.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Rather than look at waivers, just check we included it diff --git a/test_regress/t/t_stmt_incr_unsup.py b/test_regress/t/t_stmt_incr_unsup.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_stmt_incr_unsup.py +++ b/test_regress/t/t_stmt_incr_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stmt_incr_unsup.v b/test_regress/t/t_stmt_incr_unsup.v index 09e258028..e95bc9a4f 100644 --- a/test_regress/t/t_stmt_incr_unsup.v +++ b/test_regress/t/t_stmt_incr_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 Krzysztof Boronski. +// SPDX-FileCopyrightText: 2022 Krzysztof Boronski // SPDX-License-Identifier: CC0-1.0 int i = 0; @@ -12,7 +12,7 @@ endfunction module t; initial begin - int arr [3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}}; + automatic int arr [3][3] = {{1, 2, 3}, {4, 5, 6}, {7, 8, 9}}; i = 0; arr[postincrement_i()][postincrement_i()]++; $display("Value: %d", i); diff --git a/test_regress/t/t_stop_bad.py b/test_regress/t/t_stop_bad.py index 2fdd6e92d..0dbd253f9 100755 --- a/test_regress/t/t_stop_bad.py +++ b/test_regress/t/t_stop_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stop_bad.v b/test_regress/t/t_stop_bad.v index 6fd1152fa..62d255e2b 100644 --- a/test_regress/t/t_stop_bad.v +++ b/test_regress/t/t_stop_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_stop_winos_bad.py b/test_regress/t/t_stop_winos_bad.py index 12c7421fd..33be76560 100755 --- a/test_regress/t/t_stop_winos_bad.py +++ b/test_regress/t/t_stop_winos_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stop_winos_bad.v b/test_regress/t/t_stop_winos_bad.v index 1b9cddd79..d01654f1a 100644 --- a/test_regress/t/t_stop_winos_bad.v +++ b/test_regress/t/t_stop_winos_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `line 7 "C:\\some\\windows\\path\\t_stop_winos_bad.v" 0 diff --git a/test_regress/t/t_stream.py b/test_regress/t/t_stream.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream.py +++ b/test_regress/t/t_stream.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream.v b/test_regress/t/t_stream.v index 39f147be4..dd7ccef27 100644 --- a/test_regress/t/t_stream.v +++ b/test_regress/t/t_stream.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Glen Gibb. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Glen Gibb // SPDX-License-Identifier: CC0-1.0 //module t; diff --git a/test_regress/t/t_stream2.py b/test_regress/t/t_stream2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream2.py +++ b/test_regress/t/t_stream2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream2.v b/test_regress/t/t_stream2.v index d272958d8..260f03628 100644 --- a/test_regress/t/t_stream2.v +++ b/test_regress/t/t_stream2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_stream3.py b/test_regress/t/t_stream3.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream3.py +++ b/test_regress/t/t_stream3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream3.v b/test_regress/t/t_stream3.v index ce0733039..766f5f2f3 100644 --- a/test_regress/t/t_stream3.v +++ b/test_regress/t/t_stream3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_stream4.py b/test_regress/t/t_stream4.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream4.py +++ b/test_regress/t/t_stream4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream4.v b/test_regress/t/t_stream4.v index 6bb61425c..4a5fa7e56 100644 --- a/test_regress/t/t_stream4.v +++ b/test_regress/t/t_stream4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2021 by Adrien Le Masle. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Adrien Le Masle // SPDX-License-Identifier: CC0-1.0 //module t; diff --git a/test_regress/t/t_stream5.py b/test_regress/t/t_stream5.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_stream5.py +++ b/test_regress/t/t_stream5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream5.v b/test_regress/t/t_stream5.v index 6f02169d5..9dce11cae 100644 --- a/test_regress/t/t_stream5.v +++ b/test_regress/t/t_stream5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_stream_bad.py b/test_regress/t/t_stream_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_stream_bad.py +++ b/test_regress/t/t_stream_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_bad.v b/test_regress/t/t_stream_bad.v index 09a74d432..9bedf6336 100644 --- a/test_regress/t/t_stream_bad.v +++ b/test_regress/t/t_stream_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_stream_bitqueue.py b/test_regress/t/t_stream_bitqueue.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream_bitqueue.py +++ b/test_regress/t/t_stream_bitqueue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_bitqueue.v b/test_regress/t/t_stream_bitqueue.v index a9fc0ed91..973129f4f 100644 --- a/test_regress/t/t_stream_bitqueue.v +++ b/test_regress/t/t_stream_bitqueue.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off @@ -48,14 +48,14 @@ module t ( /*AUTOARG*/ `checkh(bit_q[2], 1'b1); `checkh(bit_q[3], 1'b0); - bit_q = bit_q_t'(4'h3); + bit_q = bit_q_t'(4'h3); bit_qq = bit_q; `checkh(bit_qq[0], 1'b0); `checkh(bit_qq[1], 1'b0); `checkh(bit_qq[2], 1'b1); `checkh(bit_qq[3], 1'b1); - bit_q = bit_q_t'(4'h2); + bit_q = bit_q_t'(4'h2); bit_qq = bit_q_t'(bit_q); `checkh(bit_qq[0], 1'b0); `checkh(bit_qq[1], 1'b0); @@ -256,7 +256,7 @@ module t ( /*AUTOARG*/ begin byte_q_t bytq_init; byte_q_t bytq; - bit_q_t bitq; + bit_q_t bitq; bytq_init.push_back(8'h84); bytq_init.push_back(8'haa); @@ -269,8 +269,9 @@ module t ( /*AUTOARG*/ bitq = {<<8{bit_q_t'({<<{bytq}})}}; bytq = {<<8{bit_q_t'({<<{bitq}})}}; s = $sformatf("bitq=%p", bitq); - `checks(s, - "bitq='{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1}"); + `checks( + s, + "bitq='{'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1}"); s = $sformatf("bytq=%p", bytq); `checks(s, "bytq='{'h84, 'haa}"); @@ -403,7 +404,7 @@ module t ( /*AUTOARG*/ // Test StreamR (>>) operations - fairly simple since this should maintain left-to-right order. begin - bit_q_t bitq; + bit_q_t bitq; byte_q_t bytq; bitq = {1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0}; @@ -414,8 +415,9 @@ module t ( /*AUTOARG*/ bytq = {8'h84, 8'haa}; bitq = {>>{bit_q_t'({<<{bytq}})}}; s = $sformatf("bitq=%p", bitq); - `checks(s, - "bitq='{'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1}"); + `checks( + s, + "bitq='{'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h1}"); bitq = { 1'b1, @@ -452,8 +454,9 @@ module t ( /*AUTOARG*/ bytq = {8'h84, 8'haa}; bitq = {>>{bit_q_t'({>>{bytq}})}}; s = $sformatf("bitq=%p", bitq); - `checks(s, - "bitq='{'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0}"); + `checks( + s, + "bitq='{'h1, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0, 'h1, 'h0}"); bitq = { 1'b1, @@ -483,6 +486,36 @@ module t ( /*AUTOARG*/ `checks(s, "bytq='{'h12, 'h34, 'h56}"); end + begin + bit wide_bits[]; + bit [1023:0] wide_stream; + // verilator lint_off ASCRANGE + bit [0:1023] wide_streamr; + // verilator lint_on ASCRANGE + + // verilog_format: off + wide_bits = '{1,0,1,0,1,0,1,1,0,0,1,1,0,0,0,1,0,1,0,1,0,1,1,0,1,1,0,1,0,1,0,0, + 1,0,1,1,0,1,1,1,0,1,0,1,0,0,1,0,1,1,1,1,1,0,0,0,0,1,0,0,0,0,1,1, + 0,1,0,1,0,0,1,1,0,1,1,1,1,1,0,1,0,1,1,0,1,0,0,0,1,1,0,1,1,1,1,1, + 1,0,1,1,1,1,1,1,0,1,0,0,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,1,0,1,1,1, + 1,0,0,0,1,0,1,0,1,1,1,1,0,1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1, + 1,0,0,0,1,1,0,1,1,1,1,1,0,0,1,0,1,1,0,0,0,0,1,0,0,1,0,1,0,1,1,1, + 1,1,0,0,1,1,0,1,0,1,1,0,1,1,1,1,1,0,1,0,0,1,1,1,1,1,0,0,0,1,1,1, + 1,0,0,1,0,1,0,1,1,1,0,1,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, + 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0,0,1,0,1,1,0,1,1,1,0,1,1, + 1,1,1,1,0,1,0,1,1,1,0,0,1,1,0,0}; + // verilog_format: on + + `checkh(wide_bits.size(), 432); + wide_stream = {>>bit{wide_bits}}; + `checkh(wide_stream, + 1024'hab3156d4b752f843537d68dfbf48f1f78af787ff8df2c257cd6fa7c795d300000000000000000000000000000000ffffffffa5bbf5cc0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000); + end + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_stream_crc_example.py b/test_regress/t/t_stream_crc_example.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream_crc_example.py +++ b/test_regress/t/t_stream_crc_example.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_crc_example.v b/test_regress/t/t_stream_crc_example.v index 6b15bb2d1..a3aa0900a 100644 --- a/test_regress/t/t_stream_crc_example.v +++ b/test_regress/t/t_stream_crc_example.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_stream_dynamic.py b/test_regress/t/t_stream_dynamic.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream_dynamic.py +++ b/test_regress/t/t_stream_dynamic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_dynamic.v b/test_regress/t/t_stream_dynamic.v index 57b6ce26d..b278e061a 100644 --- a/test_regress/t/t_stream_dynamic.v +++ b/test_regress/t/t_stream_dynamic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_stream_integer_type.py b/test_regress/t/t_stream_integer_type.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream_integer_type.py +++ b/test_regress/t/t_stream_integer_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_integer_type.v b/test_regress/t/t_stream_integer_type.v index 8c8f8a747..7b0d6945d 100644 --- a/test_regress/t/t_stream_integer_type.v +++ b/test_regress/t/t_stream_integer_type.v @@ -11,8 +11,8 @@ // integer_atom_type ::= byte | shortint | int | longint | integer | time // integer_vector_type ::= bit | logic | reg // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Victor Besyakov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Victor Besyakov // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_stream_queue.py b/test_regress/t/t_stream_queue.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_stream_queue.py +++ b/test_regress/t/t_stream_queue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_queue.v b/test_regress/t/t_stream_queue.v index 5d5e76d7f..5c15e4e78 100644 --- a/test_regress/t/t_stream_queue.v +++ b/test_regress/t/t_stream_queue.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_stream_string_array.py b/test_regress/t/t_stream_string_array.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream_string_array.py +++ b/test_regress/t/t_stream_string_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_string_array.v b/test_regress/t/t_stream_string_array.v index 6e8081dd9..d52388309 100644 --- a/test_regress/t/t_stream_string_array.v +++ b/test_regress/t/t_stream_string_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_stream_struct.py b/test_regress/t/t_stream_struct.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream_struct.py +++ b/test_regress/t/t_stream_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_struct.v b/test_regress/t/t_stream_struct.v index c3a1fcde3..6cbec64b3 100644 --- a/test_regress/t/t_stream_struct.v +++ b/test_regress/t/t_stream_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_stream_trace.py b/test_regress/t/t_stream_trace.py index c326fed7b..5eeac50cf 100755 --- a/test_regress/t/t_stream_trace.py +++ b/test_regress/t/t_stream_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_trace.v b/test_regress/t/t_stream_trace.v index cc6e98cc5..bac5e8ab7 100644 --- a/test_regress/t/t_stream_trace.v +++ b/test_regress/t/t_stream_trace.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_stream_type.py b/test_regress/t/t_stream_type.py index c98ffb7ab..387abbd9b 100755 --- a/test_regress/t/t_stream_type.py +++ b/test_regress/t/t_stream_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_type.v b/test_regress/t/t_stream_type.v index bf299d93c..8b867513b 100644 --- a/test_regress/t/t_stream_type.v +++ b/test_regress/t/t_stream_type.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_stream_unpack.py b/test_regress/t/t_stream_unpack.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream_unpack.py +++ b/test_regress/t/t_stream_unpack.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_unpack.v b/test_regress/t/t_stream_unpack.v index 2f3a4ac5b..924f91e86 100644 --- a/test_regress/t/t_stream_unpack.v +++ b/test_regress/t/t_stream_unpack.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop @@ -17,30 +17,30 @@ module t; initial begin typedef bit [5:0] bit6_t; typedef bit bit6_unpacked_t[6]; - bit6_unpacked_t arr; - bit [1:0] arr2[3]; - bit6_t arr6[1]; - bit6_t [0:0] parr6; - bit6_t bit6 = 6'b111000; - bit [5:0] ans; - bit [2:0][1:0] ans_packed; - enum_t ans_enum; - logic [1:0] a [3] = {1, 0, 3}; - logic [1:0] b [3] = {1, 2, 0}; - logic c [4] = {1, 1, 0, 0}; - logic [15:0] d; - logic [3:0] e [2]; - logic f [8]; - logic [1:0][7:0] g; - logic [1:0][1:0][3:0] h; - byte i []; - longint j; - int k; - int l []; - logic [127:0] m; - longint n []; - logic [255:0] o; - logic [127:0] p[]; + automatic bit6_unpacked_t arr; + automatic bit [1:0] arr2[3]; + automatic bit6_t arr6[1]; + automatic bit6_t [0:0] parr6; + automatic bit6_t bit6 = 6'b111000; + automatic bit [5:0] ans; + automatic bit [2:0][1:0] ans_packed; + automatic enum_t ans_enum; + automatic logic [1:0] a [3] = {1, 0, 3}; + automatic logic [1:0] b [3] = {1, 2, 0}; + automatic logic c [4] = {1, 1, 0, 0}; + automatic logic [15:0] d; + automatic logic [3:0] e [2]; + automatic logic f [8]; + automatic logic [1:0][7:0] g; + automatic logic [1:0][1:0][3:0] h; + automatic byte i []; + automatic longint j; + automatic int k; + automatic int l []; + automatic logic [127:0] m; + automatic longint n []; + automatic logic [255:0] o; + automatic logic [127:0] p[]; { >> bit {arr}} = bit6; `checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0}"); diff --git a/test_regress/t/t_stream_unpack_lhs.py b/test_regress/t/t_stream_unpack_lhs.py index 7b6840f68..89259eaf2 100755 --- a/test_regress/t/t_stream_unpack_lhs.py +++ b/test_regress/t/t_stream_unpack_lhs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_unpack_lhs.v b/test_regress/t/t_stream_unpack_lhs.v index 8a6817eb2..969b03889 100644 --- a/test_regress/t/t_stream_unpack_lhs.v +++ b/test_regress/t/t_stream_unpack_lhs.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // Ref. to IEEE Std 1800-2017 11.4.14 & A.8.1 // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Victor Besyakov. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Victor Besyakov // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_stream_unpack_narrower.py b/test_regress/t/t_stream_unpack_narrower.py index efe8cc01c..382ad0d44 100755 --- a/test_regress/t/t_stream_unpack_narrower.py +++ b/test_regress/t/t_stream_unpack_narrower.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_unpack_narrower.v b/test_regress/t/t_stream_unpack_narrower.v index f4c49f250..51a486859 100644 --- a/test_regress/t/t_stream_unpack_narrower.v +++ b/test_regress/t/t_stream_unpack_narrower.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_stream_unpack_wider.py b/test_regress/t/t_stream_unpack_wider.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_stream_unpack_wider.py +++ b/test_regress/t/t_stream_unpack_wider.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_stream_unpack_wider.v b/test_regress/t/t_stream_unpack_wider.v index 0b3ce11de..5d53b551c 100644 --- a/test_regress/t/t_stream_unpack_wider.v +++ b/test_regress/t/t_stream_unpack_wider.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define stop $stop @@ -10,20 +10,20 @@ module t; initial begin - logic [7:0] src_1 = 8'b1010_0011; // 8 bits wide source - logic [1:0] dst_1 [3]; // 6 bits wide target - logic [1:0] exp_1 [3]; // 6 bits wide target + automatic logic [7:0] src_1 = 8'b1010_0011; // 8 bits wide source + automatic logic [1:0] dst_1 [3]; // 6 bits wide target + automatic logic [1:0] exp_1 [3]; // 6 bits wide target - logic [1:0] src_2 [3] = '{2'b10, 2'b10, 2'b10}; // 6 bits wide source - logic [7:0] dst_2; // 8 bits wide target - logic [7:0] exp_2; // 8 bits wide target + automatic logic [1:0] src_2 [3] = '{2'b10, 2'b10, 2'b10}; // 6 bits wide source + automatic logic [7:0] dst_2; // 8 bits wide target + automatic logic [7:0] exp_2; // 8 bits wide target - logic [7:0] src_3 = 8'hA5; // 8 bits wide source - logic [27:0] dst_3; // 28 bits wide target - logic [27:0] exp_3; // 28 bits wide target + automatic logic [7:0] src_3 = 8'hA5; // 8 bits wide source + automatic logic [27:0] dst_3; // 28 bits wide target + automatic logic [27:0] exp_3; // 28 bits wide target - string expv; - string gotv; + automatic string expv; + automatic string gotv; // unpack as target, StreamR {>>{dst_1}} = src_1; diff --git a/test_regress/t/t_strength_2_uneq_assign.py b/test_regress/t/t_strength_2_uneq_assign.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_strength_2_uneq_assign.py +++ b/test_regress/t/t_strength_2_uneq_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_strength_2_uneq_assign.v b/test_regress/t/t_strength_2_uneq_assign.v index 2c92a21b1..9c5bb2e6a 100644 --- a/test_regress/t/t_strength_2_uneq_assign.v +++ b/test_regress/t/t_strength_2_uneq_assign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_strength_assignments_constants.py b/test_regress/t/t_strength_assignments_constants.py index 43be79be3..73ee01534 100755 --- a/test_regress/t/t_strength_assignments_constants.py +++ b/test_regress/t/t_strength_assignments_constants.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_strength_assignments_constants.v b/test_regress/t/t_strength_assignments_constants.v index f2d6f36e9..c6c2314f1 100644 --- a/test_regress/t/t_strength_assignments_constants.v +++ b/test_regress/t/t_strength_assignments_constants.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_strength_bufif1.py b/test_regress/t/t_strength_bufif1.py index 6585af685..b7449248c 100755 --- a/test_regress/t/t_strength_bufif1.py +++ b/test_regress/t/t_strength_bufif1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_strength_bufif1.v b/test_regress/t/t_strength_bufif1.v index 51984da31..1d100b30f 100644 --- a/test_regress/t/t_strength_bufif1.v +++ b/test_regress/t/t_strength_bufif1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_strength_equal_strength.py b/test_regress/t/t_strength_equal_strength.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_strength_equal_strength.py +++ b/test_regress/t/t_strength_equal_strength.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_strength_equal_strength.v b/test_regress/t/t_strength_equal_strength.v index eb834bc33..ac7c4b28f 100644 --- a/test_regress/t/t_strength_equal_strength.v +++ b/test_regress/t/t_strength_equal_strength.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 interface inter diff --git a/test_regress/t/t_strength_highz.py b/test_regress/t/t_strength_highz.py index 3c9bbc984..22b4d3f1b 100755 --- a/test_regress/t/t_strength_highz.py +++ b/test_regress/t/t_strength_highz.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_strength_highz.v b/test_regress/t/t_strength_highz.v index 723b23e8d..37519d278 100644 --- a/test_regress/t/t_strength_highz.v +++ b/test_regress/t/t_strength_highz.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_strength_strong1_strong1_bad.py b/test_regress/t/t_strength_strong1_strong1_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_strength_strong1_strong1_bad.py +++ b/test_regress/t/t_strength_strong1_strong1_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_strength_strong1_strong1_bad.v b/test_regress/t/t_strength_strong1_strong1_bad.v index b4308138f..d6ea93b20 100644 --- a/test_regress/t/t_strength_strong1_strong1_bad.v +++ b/test_regress/t/t_strength_strong1_strong1_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_strength_strongest_constant.py b/test_regress/t/t_strength_strongest_constant.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_strength_strongest_constant.py +++ b/test_regress/t/t_strength_strongest_constant.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_strength_strongest_constant.v b/test_regress/t/t_strength_strongest_constant.v index d8fec7098..343078601 100644 --- a/test_regress/t/t_strength_strongest_constant.v +++ b/test_regress/t/t_strength_strongest_constant.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (clk1, clk2); diff --git a/test_regress/t/t_strength_strongest_non_tristate.py b/test_regress/t/t_strength_strongest_non_tristate.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_strength_strongest_non_tristate.py +++ b/test_regress/t/t_strength_strongest_non_tristate.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_strength_strongest_non_tristate.v b/test_regress/t/t_strength_strongest_non_tristate.v index 5c3c64c86..b8affbb9b 100644 --- a/test_regress/t/t_strength_strongest_non_tristate.v +++ b/test_regress/t/t_strength_strongest_non_tristate.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (clk1, clk2); diff --git a/test_regress/t/t_string.py b/test_regress/t/t_string.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_string.py +++ b/test_regress/t/t_string.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string.v b/test_regress/t/t_string.v index 3fd931b0f..cf24c7f08 100644 --- a/test_regress/t/t_string.v +++ b/test_regress/t/t_string.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_string_add_bad.py b/test_regress/t/t_string_add_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_string_add_bad.py +++ b/test_regress/t/t_string_add_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_add_bad.v b/test_regress/t/t_string_add_bad.v index 2ad9a3556..4b09d71e9 100644 --- a/test_regress/t/t_string_add_bad.v +++ b/test_regress/t/t_string_add_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_string_byte.py b/test_regress/t/t_string_byte.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_string_byte.py +++ b/test_regress/t/t_string_byte.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_byte.v b/test_regress/t/t_string_byte.v index fa289507d..6faf28161 100644 --- a/test_regress/t/t_string_byte.v +++ b/test_regress/t/t_string_byte.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_string_convert2.py b/test_regress/t/t_string_convert2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_string_convert2.py +++ b/test_regress/t/t_string_convert2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_convert2.v b/test_regress/t/t_string_convert2.v index 9e85e81c9..ef5e4059c 100644 --- a/test_regress/t/t_string_convert2.v +++ b/test_regress/t/t_string_convert2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Peter Monsson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Peter Monsson // SPDX-License-Identifier: Unlicense module t (/*AUTOARG*/ diff --git a/test_regress/t/t_string_dyn_num.py b/test_regress/t/t_string_dyn_num.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_string_dyn_num.py +++ b/test_regress/t/t_string_dyn_num.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_dyn_num.v b/test_regress/t/t_string_dyn_num.v index 1a36dc7bb..d0affad6f 100644 --- a/test_regress/t/t_string_dyn_num.v +++ b/test_regress/t/t_string_dyn_num.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_string_octal.py b/test_regress/t/t_string_octal.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_string_octal.py +++ b/test_regress/t/t_string_octal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_octal.v b/test_regress/t/t_string_octal.v index 0dc77466f..948592f9e 100644 --- a/test_regress/t/t_string_octal.v +++ b/test_regress/t/t_string_octal.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_string_repl.py b/test_regress/t/t_string_repl.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_string_repl.py +++ b/test_regress/t/t_string_repl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_repl.v b/test_regress/t/t_string_repl.v index b385ca09a..b42a45c99 100644 --- a/test_regress/t/t_string_repl.v +++ b/test_regress/t/t_string_repl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_string_sel.py b/test_regress/t/t_string_sel.py index b7a43ed66..6c0a5e6c7 100755 --- a/test_regress/t/t_string_sel.py +++ b/test_regress/t/t_string_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_sel.v b/test_regress/t/t_string_sel.v index 969d5a726..d0334c030 100644 --- a/test_regress/t/t_string_sel.v +++ b/test_regress/t/t_string_sel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 typedef struct { @@ -26,9 +26,9 @@ module t; endfunction initial begin - c o = new; - str_s st = '{"qux"}; - string sc = {"foo", "bar"}; + automatic c o = new; + automatic str_s st = '{"qux"}; + automatic string sc = {"foo", "bar"}; // read if (str[0] != "b") $stop; diff --git a/test_regress/t/t_string_size.py b/test_regress/t/t_string_size.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_string_size.py +++ b/test_regress/t/t_string_size.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_size.v b/test_regress/t/t_string_size.v index d940e2797..9c91a4f82 100644 --- a/test_regress/t/t_string_size.v +++ b/test_regress/t/t_string_size.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_string_to_bit.py b/test_regress/t/t_string_to_bit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_string_to_bit.py +++ b/test_regress/t/t_string_to_bit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_to_bit.v b/test_regress/t/t_string_to_bit.v index 8d90484cb..1dcaba8ea 100644 --- a/test_regress/t/t_string_to_bit.v +++ b/test_regress/t/t_string_to_bit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_string_type_methods.py b/test_regress/t/t_string_type_methods.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_string_type_methods.py +++ b/test_regress/t/t_string_type_methods.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_type_methods.v b/test_regress/t/t_string_type_methods.v index 603706cd3..2a55069c4 100644 --- a/test_regress/t/t_string_type_methods.v +++ b/test_regress/t/t_string_type_methods.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_string_type_methods_bad.py b/test_regress/t/t_string_type_methods_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_string_type_methods_bad.py +++ b/test_regress/t/t_string_type_methods_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_string_type_methods_bad.v b/test_regress/t/t_string_type_methods_bad.v index c355e93b5..b8434e746 100644 --- a/test_regress/t/t_string_type_methods_bad.v +++ b/test_regress/t/t_string_type_methods_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_anon.py b/test_regress/t/t_struct_anon.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_struct_anon.py +++ b/test_regress/t/t_struct_anon.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_anon.v b/test_regress/t/t_struct_anon.v index 5793e88c7..c2a62119a 100644 --- a/test_regress/t/t_struct_anon.v +++ b/test_regress/t/t_struct_anon.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Anonymous diff --git a/test_regress/t/t_struct_array.py b/test_regress/t/t_struct_array.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_array.py +++ b/test_regress/t/t_struct_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_array.v b/test_regress/t/t_struct_array.v index 9391b7417..71f069fc7 100644 --- a/test_regress/t/t_struct_array.v +++ b/test_regress/t/t_struct_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package TEST_TYPES; diff --git a/test_regress/t/t_struct_array_assignment.py b/test_regress/t/t_struct_array_assignment.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_array_assignment.py +++ b/test_regress/t/t_struct_array_assignment.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_array_assignment.v b/test_regress/t/t_struct_array_assignment.v old mode 100755 new mode 100644 index 60e5d1532..e9534138a --- a/test_regress/t/t_struct_array_assignment.v +++ b/test_regress/t/t_struct_array_assignment.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 class unconstrained_struct_array_test; diff --git a/test_regress/t/t_struct_array_assignment_delayed.py b/test_regress/t/t_struct_array_assignment_delayed.py index 3476171ff..276645160 100755 --- a/test_regress/t/t_struct_array_assignment_delayed.py +++ b/test_regress/t/t_struct_array_assignment_delayed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_array_assignment_delayed.v b/test_regress/t/t_struct_array_assignment_delayed.v index 1e4703c6c..7c1c2fc2f 100644 --- a/test_regress/t/t_struct_array_assignment_delayed.v +++ b/test_regress/t/t_struct_array_assignment_delayed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by sumpster. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 sumpster // SPDX-License-Identifier: CC0-1.0 module tb; diff --git a/test_regress/t/t_struct_assign.py b/test_regress/t/t_struct_assign.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_struct_assign.py +++ b/test_regress/t/t_struct_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_assign.v b/test_regress/t/t_struct_assign.v index 1c54ef06c..bc2597413 100644 --- a/test_regress/t/t_struct_assign.v +++ b/test_regress/t/t_struct_assign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_circ_bad.py b/test_regress/t/t_struct_circ_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_struct_circ_bad.py +++ b/test_regress/t/t_struct_circ_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_circ_bad.v b/test_regress/t/t_struct_circ_bad.v index 389374277..774741a58 100644 --- a/test_regress/t/t_struct_circ_bad.v +++ b/test_regress/t/t_struct_circ_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_clk.py b/test_regress/t/t_struct_clk.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_clk.py +++ b/test_regress/t/t_struct_clk.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_clk.v b/test_regress/t/t_struct_clk.v index 3e864f0ef..fe204c7ae 100644 --- a/test_regress/t/t_struct_clk.v +++ b/test_regress/t/t_struct_clk.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_struct_cons_cast.py b/test_regress/t/t_struct_cons_cast.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_cons_cast.py +++ b/test_regress/t/t_struct_cons_cast.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_cons_cast.v b/test_regress/t/t_struct_cons_cast.v index 1c07b1bf8..6e4b153dc 100644 --- a/test_regress/t/t_struct_cons_cast.v +++ b/test_regress/t/t_struct_cons_cast.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class uvm_policy; diff --git a/test_regress/t/t_struct_contents.py b/test_regress/t/t_struct_contents.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_contents.py +++ b/test_regress/t/t_struct_contents.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_contents.v b/test_regress/t/t_struct_contents.v index 3bd2113a2..da690d47f 100644 --- a/test_regress/t/t_struct_contents.v +++ b/test_regress/t/t_struct_contents.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_contents_bad.py b/test_regress/t/t_struct_contents_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_struct_contents_bad.py +++ b/test_regress/t/t_struct_contents_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_contents_bad.v b/test_regress/t/t_struct_contents_bad.v index c8efa323d..f655a6355 100644 --- a/test_regress/t/t_struct_contents_bad.v +++ b/test_regress/t/t_struct_contents_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_genfor.py b/test_regress/t/t_struct_genfor.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_struct_genfor.py +++ b/test_regress/t/t_struct_genfor.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_genfor.v b/test_regress/t/t_struct_genfor.v index 41af7634d..c6415abac 100644 --- a/test_regress/t/t_struct_genfor.v +++ b/test_regress/t/t_struct_genfor.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_struct_init.py b/test_regress/t/t_struct_init.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_init.py +++ b/test_regress/t/t_struct_init.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_init.v b/test_regress/t/t_struct_init.v index c9825d019..67de870f8 100644 --- a/test_regress/t/t_struct_init.v +++ b/test_regress/t/t_struct_init.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_init_bad.py b/test_regress/t/t_struct_init_bad.py index eed2c4efc..9275a4a1c 100755 --- a/test_regress/t/t_struct_init_bad.py +++ b/test_regress/t/t_struct_init_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_init_trace.py b/test_regress/t/t_struct_init_trace.py index 812fc2737..520fefb6b 100755 --- a/test_regress/t/t_struct_init_trace.py +++ b/test_regress/t/t_struct_init_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_initial_assign.py b/test_regress/t/t_struct_initial_assign.py index b044cabcd..f3c898f62 100755 --- a/test_regress/t/t_struct_initial_assign.py +++ b/test_regress/t/t_struct_initial_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_initial_assign.v b/test_regress/t/t_struct_initial_assign.v index 74f3ecaaf..96606123c 100644 --- a/test_regress/t/t_struct_initial_assign.v +++ b/test_regress/t/t_struct_initial_assign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Issue #5381 diff --git a/test_regress/t/t_struct_initial_assign_public.py b/test_regress/t/t_struct_initial_assign_public.py index 48b2cf60e..a17a67680 100755 --- a/test_regress/t/t_struct_initial_assign_public.py +++ b/test_regress/t/t_struct_initial_assign_public.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_literal_param.py b/test_regress/t/t_struct_literal_param.py index 7e2071c5d..5ce9247e4 100755 --- a/test_regress/t/t_struct_literal_param.py +++ b/test_regress/t/t_struct_literal_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_literal_param.v b/test_regress/t/t_struct_literal_param.v index 1e4ff1a2c..ed4e6d354 100644 --- a/test_regress/t/t_struct_literal_param.v +++ b/test_regress/t/t_struct_literal_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package Some_pkg; diff --git a/test_regress/t/t_struct_negate.py b/test_regress/t/t_struct_negate.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_struct_negate.py +++ b/test_regress/t/t_struct_negate.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_negate.v b/test_regress/t/t_struct_negate.v index bc0b17a96..d6f415057 100644 --- a/test_regress/t/t_struct_negate.v +++ b/test_regress/t/t_struct_negate.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_struct_nest.py b/test_regress/t/t_struct_nest.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_struct_nest.py +++ b/test_regress/t/t_struct_nest.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_nest.v b/test_regress/t/t_struct_nest.v index 549abd217..145233c83 100644 --- a/test_regress/t/t_struct_nest.v +++ b/test_regress/t/t_struct_nest.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef struct packed { diff --git a/test_regress/t/t_struct_nest_uarray.py b/test_regress/t/t_struct_nest_uarray.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_nest_uarray.py +++ b/test_regress/t/t_struct_nest_uarray.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_nest_uarray.v b/test_regress/t/t_struct_nest_uarray.v index 3556b33d5..875e290e3 100644 --- a/test_regress/t/t_struct_nest_uarray.v +++ b/test_regress/t/t_struct_nest_uarray.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_struct_notfound_bad.py b/test_regress/t/t_struct_notfound_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_struct_notfound_bad.py +++ b/test_regress/t/t_struct_notfound_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_notfound_bad.v b/test_regress/t/t_struct_notfound_bad.v index f56c9a3a4..1bcdac5e4 100644 --- a/test_regress/t/t_struct_notfound_bad.v +++ b/test_regress/t/t_struct_notfound_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_packed_init_bad.py b/test_regress/t/t_struct_packed_init_bad.py index 5be413421..0a4563d37 100755 --- a/test_regress/t/t_struct_packed_init_bad.py +++ b/test_regress/t/t_struct_packed_init_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_packed_init_bad.v b/test_regress/t/t_struct_packed_init_bad.v index 00b4f4d42..e372dd52f 100644 --- a/test_regress/t/t_struct_packed_init_bad.v +++ b/test_regress/t/t_struct_packed_init_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_packed_sysfunct.py b/test_regress/t/t_struct_packed_sysfunct.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_packed_sysfunct.py +++ b/test_regress/t/t_struct_packed_sysfunct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_packed_sysfunct.v b/test_regress/t/t_struct_packed_sysfunct.v index 540f27dcb..915801203 100644 --- a/test_regress/t/t_struct_packed_sysfunct.v +++ b/test_regress/t/t_struct_packed_sysfunct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_struct_packed_value_list.py b/test_regress/t/t_struct_packed_value_list.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_packed_value_list.py +++ b/test_regress/t/t_struct_packed_value_list.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_packed_value_list.v b/test_regress/t/t_struct_packed_value_list.v index 3321d3d9e..284c0eae6 100644 --- a/test_regress/t/t_struct_packed_value_list.v +++ b/test_regress/t/t_struct_packed_value_list.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_struct_packed_write_read.py b/test_regress/t/t_struct_packed_write_read.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_packed_write_read.py +++ b/test_regress/t/t_struct_packed_write_read.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_packed_write_read.v b/test_regress/t/t_struct_packed_write_read.v index fa7761d7d..80e434440 100644 --- a/test_regress/t/t_struct_packed_write_read.v +++ b/test_regress/t/t_struct_packed_write_read.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Iztok Jeras. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_struct_param.py b/test_regress/t/t_struct_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_param.py +++ b/test_regress/t/t_struct_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_param.v b/test_regress/t/t_struct_param.v index 02d6878ab..0e8bc6d6e 100644 --- a/test_regress/t/t_struct_param.v +++ b/test_regress/t/t_struct_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Matt Myers. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Matt Myers // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_struct_param_overflow.py b/test_regress/t/t_struct_param_overflow.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_param_overflow.py +++ b/test_regress/t/t_struct_param_overflow.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_param_overflow.v b/test_regress/t/t_struct_param_overflow.v index 29c3b6492..d74bbdc27 100644 --- a/test_regress/t/t_struct_param_overflow.v +++ b/test_regress/t/t_struct_param_overflow.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Varun Koyyalagunta. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 package config_pkg; diff --git a/test_regress/t/t_struct_pat.py b/test_regress/t/t_struct_pat.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_pat.py +++ b/test_regress/t/t_struct_pat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_pat.v b/test_regress/t/t_struct_pat.v index c393fd664..3f14934b3 100644 --- a/test_regress/t/t_struct_pat.v +++ b/test_regress/t/t_struct_pat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_pat_toomany_bad.py b/test_regress/t/t_struct_pat_toomany_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_struct_pat_toomany_bad.py +++ b/test_regress/t/t_struct_pat_toomany_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_pat_toomany_bad.v b/test_regress/t/t_struct_pat_toomany_bad.v index 2bc918d09..d120bb0dc 100644 --- a/test_regress/t/t_struct_pat_toomany_bad.v +++ b/test_regress/t/t_struct_pat_toomany_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_pat_width.py b/test_regress/t/t_struct_pat_width.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_pat_width.py +++ b/test_regress/t/t_struct_pat_width.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_pat_width.v b/test_regress/t/t_struct_pat_width.v index d1777abf3..412266eca 100644 --- a/test_regress/t/t_struct_pat_width.v +++ b/test_regress/t/t_struct_pat_width.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_struct_port.py b/test_regress/t/t_struct_port.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_port.py +++ b/test_regress/t/t_struct_port.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_port.v b/test_regress/t/t_struct_port.v index 928df04c8..d4da06ee8 100644 --- a/test_regress/t/t_struct_port.v +++ b/test_regress/t/t_struct_port.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef struct packed { diff --git a/test_regress/t/t_struct_portsel.py b/test_regress/t/t_struct_portsel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_portsel.py +++ b/test_regress/t/t_struct_portsel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_portsel.v b/test_regress/t/t_struct_portsel.v index 280f63024..f5b451f1d 100644 --- a/test_regress/t/t_struct_portsel.v +++ b/test_regress/t/t_struct_portsel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_struct_type_bad.py b/test_regress/t/t_struct_type_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_struct_type_bad.py +++ b/test_regress/t/t_struct_type_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_type_bad.v b/test_regress/t/t_struct_type_bad.v index 0993aa7fc..f31b67ec7 100644 --- a/test_regress/t/t_struct_type_bad.v +++ b/test_regress/t/t_struct_type_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_unaligned.py b/test_regress/t/t_struct_unaligned.py index 97da89c5f..643a457c5 100755 --- a/test_regress/t/t_struct_unaligned.py +++ b/test_regress/t/t_struct_unaligned.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_unaligned.v b/test_regress/t/t_struct_unaligned.v index 642d4af86..e8a608ed2 100644 --- a/test_regress/t/t_struct_unaligned.v +++ b/test_regress/t/t_struct_unaligned.v @@ -2,8 +2,8 @@ // Test an error where a shift amount was out of bounds and the compiler treats the // value as undefined (issue #803) // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Jeff Bush. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Jeff Bush // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_struct_unpacked.py b/test_regress/t/t_struct_unpacked.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_struct_unpacked.py +++ b/test_regress/t/t_struct_unpacked.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_unpacked.v b/test_regress/t/t_struct_unpacked.v index 5ab1f23ae..ed912ef0f 100644 --- a/test_regress/t/t_struct_unpacked.v +++ b/test_regress/t/t_struct_unpacked.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009-2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009-2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_struct_unpacked_array.py b/test_regress/t/t_struct_unpacked_array.py index 1d39072e8..713e425ae 100755 --- a/test_regress/t/t_struct_unpacked_array.py +++ b/test_regress/t/t_struct_unpacked_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_unpacked_array.v b/test_regress/t/t_struct_unpacked_array.v index 4d29b517a..606a8a351 100644 --- a/test_regress/t/t_struct_unpacked_array.v +++ b/test_regress/t/t_struct_unpacked_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_struct_unpacked_clean.py b/test_regress/t/t_struct_unpacked_clean.py index 1d39072e8..713e425ae 100755 --- a/test_regress/t/t_struct_unpacked_clean.py +++ b/test_regress/t/t_struct_unpacked_clean.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_unpacked_clean.v b/test_regress/t/t_struct_unpacked_clean.v index b1951a36d..90ee69277 100644 --- a/test_regress/t/t_struct_unpacked_clean.v +++ b/test_regress/t/t_struct_unpacked_clean.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_struct_unpacked_init.out b/test_regress/t/t_struct_unpacked_init.out deleted file mode 100644 index 5e6a8ecfc..000000000 --- a/test_regress/t/t_struct_unpacked_init.out +++ /dev/null @@ -1,6 +0,0 @@ -%Error-UNSUPPORTED: t/t_struct_unpacked_init.v:12:24: Unsupported: Initial values in struct/union members - : ... note: In instance 't' - 12 | bit [3:0] m_lo = P; - | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: Exiting due to diff --git a/test_regress/t/t_struct_unpacked_init.py b/test_regress/t/t_struct_unpacked_init.py index 31228c9a7..8a938befd 100755 --- a/test_regress/t/t_struct_unpacked_init.py +++ b/test_regress/t/t_struct_unpacked_init.py @@ -1,16 +1,18 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap -test.scenarios('linter') +test.scenarios('simulator') -test.lint(fails=True, expect_filename=test.golden_filename) +test.compile() + +test.execute() test.passes() diff --git a/test_regress/t/t_struct_unpacked_init.v b/test_regress/t/t_struct_unpacked_init.v index 4c5c43d8f..a9a18e61b 100644 --- a/test_regress/t/t_struct_unpacked_init.v +++ b/test_regress/t/t_struct_unpacked_init.v @@ -1,25 +1,40 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off +`define stop $stop +`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + module t; - parameter P = 4'h5; + parameter P = 4'h5; - struct { // Can't legally be packed - bit [3:0] m_lo = P; - bit [3:0] m_hi; - } s; + typedef struct { // Must be unpacked -- existing error check + // Update ctor_var_reset to check instead of making a constructor + bit [3:0] m_lo = P; + bit [93:0] m_mid = '1; // Wide + bit [3:0] m_hi; + } s_t; + s_t s; - initial begin - s.m_hi = 4'ha; - if (s.m_lo != 4'h5) $stop; - if (s.m_hi != 4'ha) $stop; + initial begin + $display("%p", s); + `checkh(s.m_lo, 4'h5); + `checkh(s.m_mid, ~94'h0); + `checkh(s.m_hi, 4'h0); + s.m_mid = 94'ha; + s.m_hi = 4'hb; + $display("%p", s); + `checkh(s.m_lo, 4'h5); + `checkh(s.m_mid, 94'ha); + `checkh(s.m_hi, 4'hb); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_struct_unpacked_init_param.py b/test_regress/t/t_struct_unpacked_init_param.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_struct_unpacked_init_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_struct_unpacked_init_param.v b/test_regress/t/t_struct_unpacked_init_param.v new file mode 100644 index 000000000..c194836e7 --- /dev/null +++ b/test_regress/t/t_struct_unpacked_init_param.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t; + + parameter P = 4'h5; + + typedef struct { // Must be unpacked -- existing error check + bit [3:0] m_lo = P; + bit [93:0] m_mid = '1; // Wide + bit [3:0] m_hi; + } s_t; + + localparam s_t S = '{m_hi: 6}; // Not setting m_mid/m_hi + + localparam S_LO = S.m_lo; + localparam S_HI = S.m_hi; + + initial begin + `checkh(S.m_hi, 4'h6); + `checkh(S_HI, 4'h6); + + `checkh(S.m_lo, 4'h5); + `checkh(S_LO, 4'h5); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_struct_unpacked_param.py b/test_regress/t/t_struct_unpacked_param.py index c39e83d77..903201f15 100755 --- a/test_regress/t/t_struct_unpacked_param.py +++ b/test_regress/t/t_struct_unpacked_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_unpacked_param.v b/test_regress/t/t_struct_unpacked_param.v index 9736c98a1..1bcc389f0 100644 --- a/test_regress/t/t_struct_unpacked_param.v +++ b/test_regress/t/t_struct_unpacked_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Jonathan Drolet. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Jonathan Drolet // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_struct_unused.py b/test_regress/t/t_struct_unused.py index 143e17cb5..09b830dae 100755 --- a/test_regress/t/t_struct_unused.py +++ b/test_regress/t/t_struct_unused.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_struct_unused.v b/test_regress/t/t_struct_unused.v index 07181488a..b8854c485 100644 --- a/test_regress/t/t_struct_unused.v +++ b/test_regress/t/t_struct_unused.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module x; diff --git a/test_regress/t/t_structu_dataType_assignment.py b/test_regress/t/t_structu_dataType_assignment.py index d80083531..1f96bf061 100755 --- a/test_regress/t/t_structu_dataType_assignment.py +++ b/test_regress/t/t_structu_dataType_assignment.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_structu_dataType_assignment.v b/test_regress/t/t_structu_dataType_assignment.v index 734b4dd46..cae4c5c35 100644 --- a/test_regress/t/t_structu_dataType_assignment.v +++ b/test_regress/t/t_structu_dataType_assignment.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for specialized type default values // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Mostafa Gamal. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Mostafa Gamal // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off UNPACKED */ diff --git a/test_regress/t/t_structu_dataType_assignment_bad.py b/test_regress/t/t_structu_dataType_assignment_bad.py index 2d150a9df..9e2d9b6bf 100755 --- a/test_regress/t/t_structu_dataType_assignment_bad.py +++ b/test_regress/t/t_structu_dataType_assignment_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_structu_dataType_assignment_bad.v b/test_regress/t/t_structu_dataType_assignment_bad.v index a5e87a441..fe0a353aa 100644 --- a/test_regress/t/t_structu_dataType_assignment_bad.v +++ b/test_regress/t/t_structu_dataType_assignment_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for specialized type default values // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Mostafa Gamal. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Mostafa Gamal // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off UNPACKED */ diff --git a/test_regress/t/t_structu_wide.py b/test_regress/t/t_structu_wide.py index b1fdec1e8..66e08e50f 100755 --- a/test_regress/t/t_structu_wide.py +++ b/test_regress/t/t_structu_wide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_structu_wide.v b/test_regress/t/t_structu_wide.v index 11858ba44..61dca1ad7 100644 --- a/test_regress/t/t_structu_wide.v +++ b/test_regress/t/t_structu_wide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Jomit626. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2022 Jomit626 // SPDX-License-Identifier: CC0-1.0 `ifndef WIDE_WIDTH diff --git a/test_regress/t/t_sv_bus_mux_demux.py b/test_regress/t/t_sv_bus_mux_demux.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_sv_bus_mux_demux.py +++ b/test_regress/t/t_sv_bus_mux_demux.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sv_bus_mux_demux.v b/test_regress/t/t_sv_bus_mux_demux.v index 39bbb1b71..c1ee81b1d 100644 --- a/test_regress/t/t_sv_bus_mux_demux.v +++ b/test_regress/t/t_sv_bus_mux_demux.v @@ -1,9 +1,9 @@ //////////////////////////////////////////////////////////////////////////////// -// // -// This file is placed into the Public Domain, for any use, without warranty. // -// 2012 by Iztok Jeras // -// SPDX-License-Identifier: CC0-1.0 // -// // +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras +// SPDX-License-Identifier: CC0-1.0 +// //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv index 30e64add1..fd8d5ef31 100644 --- a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv @@ -1,9 +1,9 @@ //////////////////////////////////////////////////////////////////////////////// -// // -// This file is placed into the Public Domain, for any use, without warranty. // -// 2012 by Iztok Jeras // -// SPDX-License-Identifier: CC0-1.0 // -// // +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras +// SPDX-License-Identifier: CC0-1.0 +// //////////////////////////////////////////////////////////////////////////////// // definition of data bus structure diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv index 7c68214fb..ee8d415da 100644 --- a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv @@ -1,9 +1,9 @@ //////////////////////////////////////////////////////////////////////////////// -// // -// This file is placed into the Public Domain, for any use, without warranty. // -// 2012 by Iztok Jeras // -// SPDX-License-Identifier: CC0-1.0 // -// // +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras +// SPDX-License-Identifier: CC0-1.0 +// //////////////////////////////////////////////////////////////////////////////// import package_bus::*; diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv index 4d963545b..9ea0c4eb4 100644 --- a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv @@ -1,9 +1,9 @@ //////////////////////////////////////////////////////////////////////////////// -// // -// This file is placed into the Public Domain, for any use, without warranty. // -// 2012 by Iztok Jeras // -// SPDX-License-Identifier: CC0-1.0 // -// // +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras +// SPDX-License-Identifier: CC0-1.0 +// //////////////////////////////////////////////////////////////////////////////// import package_bus::*; diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv index 7ca87c358..50ba0ec6a 100644 --- a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv @@ -1,9 +1,9 @@ //////////////////////////////////////////////////////////////////////////////// -// // -// This file is placed into the Public Domain, for any use, without warranty. // -// 2012 by Iztok Jeras // -// SPDX-License-Identifier: CC0-1.0 // -// // +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Iztok Jeras +// SPDX-License-Identifier: CC0-1.0 +// //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// diff --git a/test_regress/t/t_sv_conditional.py b/test_regress/t/t_sv_conditional.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_sv_conditional.py +++ b/test_regress/t/t_sv_conditional.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sv_conditional.v b/test_regress/t/t_sv_conditional.v index 336941462..8d19cf2eb 100644 --- a/test_regress/t/t_sv_conditional.v +++ b/test_regress/t/t_sv_conditional.v @@ -2,13 +2,10 @@ // // This code instantiates and runs a simple CPU written in System Verilog. // -// This file ONLY is placed into the Public Domain, for any use, without -// warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm // SPDX-License-Identifier: CC0-1.0 -// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. - - module t (/*AUTOARG*/ // Inputs clk diff --git a/test_regress/t/t_sv_cpu.py b/test_regress/t/t_sv_cpu.py index 84a49ebb7..dcc41dab2 100755 --- a/test_regress/t/t_sv_cpu.py +++ b/test_regress/t/t_sv_cpu.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sv_cpu.v b/test_regress/t/t_sv_cpu.v index 1e658d84c..1f2552cf2 100644 --- a/test_regress/t/t_sv_cpu.v +++ b/test_regress/t/t_sv_cpu.v @@ -2,8 +2,8 @@ // // This code instantiates and runs a simple CPU written in System Verilog. // -// This file ONLY is placed into the Public Domain, for any use, without -// warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. diff --git a/test_regress/t/t_sv_cpu_code/ac.sv b/test_regress/t/t_sv_cpu_code/ac.sv index 8ceb2262f..a44a4f74d 100644 --- a/test_regress/t/t_sv_cpu_code/ac.sv +++ b/test_regress/t/t_sv_cpu_code/ac.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/ac_ana.sv b/test_regress/t/t_sv_cpu_code/ac_ana.sv index a40728c29..efac5d685 100644 --- a/test_regress/t/t_sv_cpu_code/ac_ana.sv +++ b/test_regress/t/t_sv_cpu_code/ac_ana.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/ac_dig.sv b/test_regress/t/t_sv_cpu_code/ac_dig.sv index 046eae2f5..78570c3d3 100644 --- a/test_regress/t/t_sv_cpu_code/ac_dig.sv +++ b/test_regress/t/t_sv_cpu_code/ac_dig.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/adrdec.sv b/test_regress/t/t_sv_cpu_code/adrdec.sv index 0d2f925e0..37ca3a9ec 100644 --- a/test_regress/t/t_sv_cpu_code/adrdec.sv +++ b/test_regress/t/t_sv_cpu_code/adrdec.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/chip.sv b/test_regress/t/t_sv_cpu_code/chip.sv index 4f374cc6d..83970cdde 100644 --- a/test_regress/t/t_sv_cpu_code/chip.sv +++ b/test_regress/t/t_sv_cpu_code/chip.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/cpu.sv b/test_regress/t/t_sv_cpu_code/cpu.sv index 9f8a3526a..776aa4638 100644 --- a/test_regress/t/t_sv_cpu_code/cpu.sv +++ b/test_regress/t/t_sv_cpu_code/cpu.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/genbus_if.sv b/test_regress/t/t_sv_cpu_code/genbus_if.sv index 430e20ded..07fa4900d 100644 --- a/test_regress/t/t_sv_cpu_code/genbus_if.sv +++ b/test_regress/t/t_sv_cpu_code/genbus_if.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pad_gnd.sv b/test_regress/t/t_sv_cpu_code/pad_gnd.sv index e64220f29..ead447667 100644 --- a/test_regress/t/t_sv_cpu_code/pad_gnd.sv +++ b/test_regress/t/t_sv_cpu_code/pad_gnd.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pad_gpio.sv b/test_regress/t/t_sv_cpu_code/pad_gpio.sv index 5c99714d7..856f6e430 100644 --- a/test_regress/t/t_sv_cpu_code/pad_gpio.sv +++ b/test_regress/t/t_sv_cpu_code/pad_gpio.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pad_vdd.sv b/test_regress/t/t_sv_cpu_code/pad_vdd.sv index bad7cc902..ee392f25b 100644 --- a/test_regress/t/t_sv_cpu_code/pad_vdd.sv +++ b/test_regress/t/t_sv_cpu_code/pad_vdd.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pads.sv b/test_regress/t/t_sv_cpu_code/pads.sv index e4e3cbd99..aab4a285b 100644 --- a/test_regress/t/t_sv_cpu_code/pads.sv +++ b/test_regress/t/t_sv_cpu_code/pads.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pads_h.sv b/test_regress/t/t_sv_cpu_code/pads_h.sv index 4955d77c1..68b229c2b 100644 --- a/test_regress/t/t_sv_cpu_code/pads_h.sv +++ b/test_regress/t/t_sv_cpu_code/pads_h.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pads_if.sv b/test_regress/t/t_sv_cpu_code/pads_if.sv index acdbef77a..df5993d14 100644 --- a/test_regress/t/t_sv_cpu_code/pads_if.sv +++ b/test_regress/t/t_sv_cpu_code/pads_if.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pinout_h.sv b/test_regress/t/t_sv_cpu_code/pinout_h.sv index 6955249eb..822860bfa 100644 --- a/test_regress/t/t_sv_cpu_code/pinout_h.sv +++ b/test_regress/t/t_sv_cpu_code/pinout_h.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/ports.sv b/test_regress/t/t_sv_cpu_code/ports.sv index 5cfeeccbb..172bc3a2f 100644 --- a/test_regress/t/t_sv_cpu_code/ports.sv +++ b/test_regress/t/t_sv_cpu_code/ports.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/ports_h.sv b/test_regress/t/t_sv_cpu_code/ports_h.sv index 57676835b..bb953508a 100644 --- a/test_regress/t/t_sv_cpu_code/ports_h.sv +++ b/test_regress/t/t_sv_cpu_code/ports_h.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/program_h.sv b/test_regress/t/t_sv_cpu_code/program_h.sv index 999ea668b..87a34e798 100644 --- a/test_regress/t/t_sv_cpu_code/program_h.sv +++ b/test_regress/t/t_sv_cpu_code/program_h.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/rom.sv b/test_regress/t/t_sv_cpu_code/rom.sv index 25252d6cb..dfd3698f8 100644 --- a/test_regress/t/t_sv_cpu_code/rom.sv +++ b/test_regress/t/t_sv_cpu_code/rom.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/timescale.sv b/test_regress/t/t_sv_cpu_code/timescale.sv index cd6404194..16e2703f2 100644 --- a/test_regress/t/t_sv_cpu_code/timescale.sv +++ b/test_regress/t/t_sv_cpu_code/timescale.sv @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Large test for SystemVerilog -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2012 // SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sys_delta_monitor.py b/test_regress/t/t_sys_delta_monitor.py index 957a57046..b210cd8cd 100755 --- a/test_regress/t/t_sys_delta_monitor.py +++ b/test_regress/t/t_sys_delta_monitor.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_delta_monitor.v b/test_regress/t/t_sys_delta_monitor.v index 829c21385..b4ce121e6 100644 --- a/test_regress/t/t_sys_delta_monitor.v +++ b/test_regress/t/t_sys_delta_monitor.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; logic [31:0] tmp; diff --git a/test_regress/t/t_sys_file_autoflush.py b/test_regress/t/t_sys_file_autoflush.py index c753bd0e8..1a46a2805 100755 --- a/test_regress/t/t_sys_file_autoflush.py +++ b/test_regress/t/t_sys_file_autoflush.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_file_basic.py b/test_regress/t/t_sys_file_basic.py index d36d66d7c..6a0d42341 100755 --- a/test_regress/t/t_sys_file_basic.py +++ b/test_regress/t/t_sys_file_basic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_file_basic.v b/test_regress/t/t_sys_file_basic.v index 1ee489e88..27e2eb5a8 100644 --- a/test_regress/t/t_sys_file_basic.v +++ b/test_regress/t/t_sys_file_basic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_sys_file_basic_cover_expr.py b/test_regress/t/t_sys_file_basic_cover_expr.py index 0c86310dc..44303846d 100755 --- a/test_regress/t/t_sys_file_basic_cover_expr.py +++ b/test_regress/t/t_sys_file_basic_cover_expr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_file_basic_mcd.py b/test_regress/t/t_sys_file_basic_mcd.py index 307f60dff..b148c8295 100755 --- a/test_regress/t/t_sys_file_basic_mcd.py +++ b/test_regress/t/t_sys_file_basic_mcd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_file_basic_mcd.v b/test_regress/t/t_sys_file_basic_mcd.v index 285c696dc..ddf5b8ff2 100644 --- a/test_regress/t/t_sys_file_basic_mcd.v +++ b/test_regress/t/t_sys_file_basic_mcd.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_sys_file_basic_uz.py b/test_regress/t/t_sys_file_basic_uz.py index 8afc2b9d3..90409c781 100755 --- a/test_regress/t/t_sys_file_basic_uz.py +++ b/test_regress/t/t_sys_file_basic_uz.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_file_basic_uz.v b/test_regress/t/t_sys_file_basic_uz.v index ed9d61d70..0a7ca6a6d 100644 --- a/test_regress/t/t_sys_file_basic_uz.v +++ b/test_regress/t/t_sys_file_basic_uz.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2030 by Stephen Henry. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2030 Stephen Henry // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_sys_file_eof.py b/test_regress/t/t_sys_file_eof.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_sys_file_eof.py +++ b/test_regress/t/t_sys_file_eof.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_file_eof.v b/test_regress/t/t_sys_file_eof.v index fdc2d9ba4..38e385cc4 100644 --- a/test_regress/t/t_sys_file_eof.v +++ b/test_regress/t/t_sys_file_eof.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_sys_file_null.py b/test_regress/t/t_sys_file_null.py index 6f9225ca3..1fe02793b 100755 --- a/test_regress/t/t_sys_file_null.py +++ b/test_regress/t/t_sys_file_null.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_file_null.v b/test_regress/t/t_sys_file_null.v index de152ce3a..8bc135006 100644 --- a/test_regress/t/t_sys_file_null.v +++ b/test_regress/t/t_sys_file_null.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_sys_file_scan.py b/test_regress/t/t_sys_file_scan.py index 3f737df94..cad04be04 100755 --- a/test_regress/t/t_sys_file_scan.py +++ b/test_regress/t/t_sys_file_scan.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_file_scan.v b/test_regress/t/t_sys_file_scan.v index 545300dcc..88daf2456 100644 --- a/test_regress/t/t_sys_file_scan.v +++ b/test_regress/t/t_sys_file_scan.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_sys_file_scan2.py b/test_regress/t/t_sys_file_scan2.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_sys_file_scan2.py +++ b/test_regress/t/t_sys_file_scan2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_file_scan2.v b/test_regress/t/t_sys_file_scan2.v index a278bf57c..f1a53b7df 100644 --- a/test_regress/t/t_sys_file_scan2.v +++ b/test_regress/t/t_sys_file_scan2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_sys_file_zero.py b/test_regress/t/t_sys_file_zero.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_sys_file_zero.py +++ b/test_regress/t/t_sys_file_zero.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_file_zero.v b/test_regress/t/t_sys_file_zero.v index a4197543f..87c5e9b9b 100644 --- a/test_regress/t/t_sys_file_zero.v +++ b/test_regress/t/t_sys_file_zero.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_sys_fmonitor.py b/test_regress/t/t_sys_fmonitor.py index 8ec472516..9407f5e1a 100755 --- a/test_regress/t/t_sys_fmonitor.py +++ b/test_regress/t/t_sys_fmonitor.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_fmonitor.v b/test_regress/t/t_sys_fmonitor.v index dd7f1329f..aeb4661a5 100644 --- a/test_regress/t/t_sys_fmonitor.v +++ b/test_regress/t/t_sys_fmonitor.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_sys_fread.py b/test_regress/t/t_sys_fread.py index 29f0832f0..92829167d 100755 --- a/test_regress/t/t_sys_fread.py +++ b/test_regress/t/t_sys_fread.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_fread.v b/test_regress/t/t_sys_fread.v index 078a1be31..e3a9b7a01 100644 --- a/test_regress/t/t_sys_fread.v +++ b/test_regress/t/t_sys_fread.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_sys_fscanf_bad.py b/test_regress/t/t_sys_fscanf_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_sys_fscanf_bad.py +++ b/test_regress/t/t_sys_fscanf_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_fscanf_bad.v b/test_regress/t/t_sys_fscanf_bad.v index ec1321f8a..8e93da1a8 100644 --- a/test_regress/t/t_sys_fscanf_bad.v +++ b/test_regress/t/t_sys_fscanf_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_fstrobe.py b/test_regress/t/t_sys_fstrobe.py index 63d3560f9..af775d53e 100755 --- a/test_regress/t/t_sys_fstrobe.py +++ b/test_regress/t/t_sys_fstrobe.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_fstrobe.v b/test_regress/t/t_sys_fstrobe.v index de5c664b1..9f935fc8a 100644 --- a/test_regress/t/t_sys_fstrobe.v +++ b/test_regress/t/t_sys_fstrobe.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_sys_get_init_seed.py b/test_regress/t/t_sys_get_init_seed.py new file mode 100755 index 000000000..c27a581fe --- /dev/null +++ b/test_regress/t/t_sys_get_init_seed.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=False) + +test.compile(verilator_flags2=['--binary']) + +test.execute(all_run_flags=['+verilator+seed+22']) + +test.passes() diff --git a/test_regress/t/t_sys_get_init_seed.v b/test_regress/t/t_sys_get_init_seed.v new file mode 100644 index 000000000..01fe1762b --- /dev/null +++ b/test_regress/t/t_sys_get_init_seed.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Srinivasan Venkataramanan +// SPDX-License-Identifier: CC0-1.0 + +module t; + int seed = 1; + + initial begin + seed = $get_initial_random_seed(); + $display("get_initial_random_seed=%0d", seed); + if (seed != 22) $stop; + $write("*-* All Finished *-*\n"); + $finish(2); + end + +endmodule diff --git a/test_regress/t/t_sys_monitor.py b/test_regress/t/t_sys_monitor.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_sys_monitor.py +++ b/test_regress/t/t_sys_monitor.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_monitor.v b/test_regress/t/t_sys_monitor.v index a1619464a..4e2f9bde2 100644 --- a/test_regress/t/t_sys_monitor.v +++ b/test_regress/t/t_sys_monitor.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_sys_monitor_changes.py b/test_regress/t/t_sys_monitor_changes.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_sys_monitor_changes.py +++ b/test_regress/t/t_sys_monitor_changes.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_monitor_changes.v b/test_regress/t/t_sys_monitor_changes.v index aa864b6df..a0996f0a4 100644 --- a/test_regress/t/t_sys_monitor_changes.v +++ b/test_regress/t/t_sys_monitor_changes.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_monitor_dotted.py b/test_regress/t/t_sys_monitor_dotted.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_sys_monitor_dotted.py +++ b/test_regress/t/t_sys_monitor_dotted.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_monitor_dotted.v b/test_regress/t/t_sys_monitor_dotted.v index 92ac9b4b0..2ed12ab3a 100644 --- a/test_regress/t/t_sys_monitor_dotted.v +++ b/test_regress/t/t_sys_monitor_dotted.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface addsub_ifc; diff --git a/test_regress/t/t_sys_plusargs.py b/test_regress/t/t_sys_plusargs.py index 51529220e..fa6e7da58 100755 --- a/test_regress/t/t_sys_plusargs.py +++ b/test_regress/t/t_sys_plusargs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_plusargs.v b/test_regress/t/t_sys_plusargs.v index 1ca4f29bd..0d8ce3b80 100644 --- a/test_regress/t/t_sys_plusargs.v +++ b/test_regress/t/t_sys_plusargs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_plusargs_bad.py b/test_regress/t/t_sys_plusargs_bad.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_sys_plusargs_bad.py +++ b/test_regress/t/t_sys_plusargs_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_plusargs_bad.v b/test_regress/t/t_sys_plusargs_bad.v index b01d56f05..98dfe4dc9 100644 --- a/test_regress/t/t_sys_plusargs_bad.v +++ b/test_regress/t/t_sys_plusargs_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_psprintf.py b/test_regress/t/t_sys_psprintf.py index 45836a507..54f560e50 100755 --- a/test_regress/t/t_sys_psprintf.py +++ b/test_regress/t/t_sys_psprintf.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_psprintf.v b/test_regress/t/t_sys_psprintf.v index bcd001afa..84b865e40 100644 --- a/test_regress/t/t_sys_psprintf.v +++ b/test_regress/t/t_sys_psprintf.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_psprintf_warn_bad.py b/test_regress/t/t_sys_psprintf_warn_bad.py index 092329b04..76e4b842c 100755 --- a/test_regress/t/t_sys_psprintf_warn_bad.py +++ b/test_regress/t/t_sys_psprintf_warn_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_queue_unsup.py b/test_regress/t/t_sys_queue_unsup.py index f41d93235..b7449248c 100755 --- a/test_regress/t/t_sys_queue_unsup.py +++ b/test_regress/t/t_sys_queue_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_queue_unsup.v b/test_regress/t/t_sys_queue_unsup.v index 1e194cf48..e0589ae39 100644 --- a/test_regress/t/t_sys_queue_unsup.v +++ b/test_regress/t/t_sys_queue_unsup.v @@ -2,8 +2,8 @@ // // Simple bi-directional alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Based on iverilog/ivtest/ivltests/queue.v diff --git a/test_regress/t/t_sys_rand.py b/test_regress/t/t_sys_rand.py deleted file mode 100755 index d4f986441..000000000 --- a/test_regress/t/t_sys_rand.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile() - -test.execute() - -test.passes() diff --git a/test_regress/t/t_sys_rand.v b/test_regress/t/t_sys_rand.v deleted file mode 100644 index 49e222f1c..000000000 --- a/test_regress/t/t_sys_rand.v +++ /dev/null @@ -1,37 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t; - - reg [31:0] lastrand; - reg [31:0] thisrand; - - integer same = 0; - integer i; - -`define TRIES 20 - - initial begin - // There's a 1^32 chance of the numbers being the same twice, - // so we'll allow one failure - lastrand = $random; - for (i=0; i<`TRIES; i=i+1) begin - thisrand = $random; -`ifdef TEST_VERBOSE - $write("Random = %x\n", thisrand); -`endif - if (thisrand == lastrand) same=same+1; - lastrand = thisrand; - end - if (same > 1) begin - $write("%%Error: Too many similar numbers: %d\n", same); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_sys_rand_concat.v b/test_regress/t/t_sys_rand_concat.v deleted file mode 100644 index acbbf665e..000000000 --- a/test_regress/t/t_sys_rand_concat.v +++ /dev/null @@ -1,60 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define stop $stop -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) - -module t; - -`define TRIES 100 - - bit [6:0] b5a; // We use larger than [4:0] so make sure we truncate - bit [6:0] b5b; // We use larger than [4:0] so make sure we truncate - bit [6:0] b7c; - bit [6:0] b7d; - bit [59:0] b60c; - bit [89:0] b90c; - - bit [6:0] max_b5a; - bit [6:0] max_b5b; - bit [6:0] max_b7c; - bit [6:0] max_b7d; - bit [59:0] max_b60c; - bit [89:0] max_b90c; - - initial begin - for (int i = 0; i < `TRIES; ++i) begin - // verilator lint_off WIDTH - // Optimize away extracts - b5a = {$random}[4:0]; - b5b = {$random}[14:10]; - // Optimize away concats - b7c = {$random, $random, $random, $random, $random, $random, $random}; - b7d = {{{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}}; - b60c = {$random, $random, $random, $random, $random, $random, $random}; - b90c = {$random, $random, $random, $random, $random, $random, $random}; - // verilator lint_on WIDTH - - max_b5a = max_b5a | b5a; - max_b5b = max_b5b | b5b; - max_b7c = max_b7c | b7c; - max_b7d = max_b7d | b7d; - max_b60c = max_b60c | b60c; - max_b90c = max_b90c | b90c; - end - - `checkh(max_b5a, 7'h1f); - `checkh(max_b5b, 7'h1f); - `checkh(max_b7c, 7'h7f); - `checkh(max_b7d, 7'h1f); - `checkh(max_b60c, ~ 60'h0); - `checkh(max_b90c, ~ 90'h0); - - $write("*-* All Finished *-*\n"); - $finish; - end - -endmodule diff --git a/test_regress/t/t_sys_rand_seed.py b/test_regress/t/t_sys_rand_seed.py deleted file mode 100755 index d4f986441..000000000 --- a/test_regress/t/t_sys_rand_seed.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile() - -test.execute() - -test.passes() diff --git a/test_regress/t/t_sys_rand_seed.v b/test_regress/t/t_sys_rand_seed.v deleted file mode 100644 index 3a9acec20..000000000 --- a/test_regress/t/t_sys_rand_seed.v +++ /dev/null @@ -1,70 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t; - - integer seeda; - integer seedb; - integer seedc; - int valuea; - int valueb; - int valuec; - int igna; - int ignb; - int ignc; - - initial begin - // $random unlike $urandom updates the value if given - seeda = 10; - valuea = $random(seeda); - seedb = 10; - valueb = $random(seedb); - if (valuea !== valueb) $stop; - - seeda = 10; - valuea = $random(seeda); - seedb = seeda; - valueb = $random(seedb); - seedc = seedb; - valuec = $random(seedc); - if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 - if (seeda == seedb && seedb == seedc) $stop; // May false fail 1 in 1^64 - - valuea = $urandom(10); - valueb = $urandom(10); - valuec = $urandom(10); - if (valuea !== valueb && valueb != valuec) $stop; - - valuea = $urandom(10); - valueb = $urandom(11); - valuec = $urandom(12); - if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 - - $urandom(10); - valuea = $urandom; - $urandom(10); - valueb = $urandom; - $urandom(10); - valuec = $urandom; - if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64 - - igna = $urandom(10); - valuea = $urandom; - ignb = $urandom(10); - valueb = $urandom; - ignc = $urandom(10); - valuec = $urandom; - if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64 - - valuea = $urandom(10); - valueb = $urandom(); - valuec = $urandom(); - if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 - - $write("*-* All Finished *-*\n"); - $finish; - end -endmodule diff --git a/test_regress/t/t_sys_random.py b/test_regress/t/t_sys_random.py new file mode 100755 index 000000000..3cc73805c --- /dev/null +++ b/test_regress/t/t_sys_random.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_random.v b/test_regress/t/t_sys_random.v new file mode 100644 index 000000000..93930b7b2 --- /dev/null +++ b/test_regress/t/t_sys_random.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + + reg [31:0] lastrand; + reg [31:0] thisrand; + + integer same = 0; + integer i; + + `define TRIES 20 + + initial begin + // There's a 1^32 chance of the numbers being the same twice, + // so we'll allow one failure + lastrand = $random; + for (i = 0; i < `TRIES; i = i + 1) begin + thisrand = $random; +`ifdef TEST_VERBOSE + $write("Random = %x\n", thisrand); +`endif + if (thisrand == lastrand) same = same + 1; + lastrand = thisrand; + end + if (same > 1) begin + $write("%%Error: Too many similar numbers: %d\n", same); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_sys_rand_concat.py b/test_regress/t/t_sys_random_concat.py similarity index 62% rename from test_regress/t/t_sys_rand_concat.py rename to test_regress/t/t_sys_random_concat.py index aa46be6bb..55b02b66e 100755 --- a/test_regress/t/t_sys_rand_concat.py +++ b/test_regress/t/t_sys_random_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_random_concat.v b/test_regress/t/t_sys_random_concat.v new file mode 100644 index 000000000..e414613e3 --- /dev/null +++ b/test_regress/t/t_sys_random_concat.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: on + +module t; + + `define TRIES 100 + + bit [6:0] b5a; // We use larger than [4:0] so make sure we truncate + bit [6:0] b5b; // We use larger than [4:0] so make sure we truncate + bit [6:0] b7c; + bit [6:0] b7d; + bit [59:0] b60c; + bit [89:0] b90c; + + bit [6:0] max_b5a; + bit [6:0] max_b5b; + bit [6:0] max_b7c; + bit [6:0] max_b7d; + bit [59:0] max_b60c; + bit [89:0] max_b90c; + + initial begin + for (int i = 0; i < `TRIES; ++i) begin + // verilator lint_off WIDTH + // Optimize away extracts + b5a = {$random}[4:0]; + b5b = {$random}[14:10]; + // Optimize away concats + b7c = {$random, $random, $random, $random, $random, $random, $random}; + b7d = {{{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}}; + b60c = {$random, $random, $random, $random, $random, $random, $random}; + b90c = {$random, $random, $random, $random, $random, $random, $random}; + // verilator lint_on WIDTH + + max_b5a = max_b5a | b5a; + max_b5b = max_b5b | b5b; + max_b7c = max_b7c | b7c; + max_b7d = max_b7d | b7d; + max_b60c = max_b60c | b60c; + max_b90c = max_b90c | b90c; + end + + `checkh(max_b5a, 7'h1f); + `checkh(max_b5b, 7'h1f); + `checkh(max_b7c, 7'h7f); + `checkh(max_b7d, 7'h1f); + `checkh(max_b60c, ~60'h0); + `checkh(max_b90c, ~90'h0); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_sys_random_seed.py b/test_regress/t/t_sys_random_seed.py new file mode 100755 index 000000000..3cc73805c --- /dev/null +++ b/test_regress/t/t_sys_random_seed.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_sys_random_seed.v b/test_regress/t/t_sys_random_seed.v new file mode 100644 index 000000000..0342473e2 --- /dev/null +++ b/test_regress/t/t_sys_random_seed.v @@ -0,0 +1,70 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + + integer seeda; + integer seedb; + integer seedc; + int valuea; + int valueb; + int valuec; + int igna; + int ignb; + int ignc; + + initial begin + // $random unlike $urandom updates the value if given + seeda = 10; + valuea = $random(seeda); + seedb = 10; + valueb = $random(seedb); + if (valuea !== valueb) $stop; + + seeda = 10; + valuea = $random(seeda); + seedb = seeda; + valueb = $random(seedb); + seedc = seedb; + valuec = $random(seedc); + if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 + if (seeda == seedb && seedb == seedc) $stop; // May false fail 1 in 1^64 + + valuea = $urandom(10); + valueb = $urandom(10); + valuec = $urandom(10); + if (valuea !== valueb && valueb != valuec) $stop; + + valuea = $urandom(10); + valueb = $urandom(11); + valuec = $urandom(12); + if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 + + $urandom(10); + valuea = $urandom; + $urandom(10); + valueb = $urandom; + $urandom(10); + valuec = $urandom; + if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64 + + igna = $urandom(10); + valuea = $urandom; + ignb = $urandom(10); + valueb = $urandom; + ignc = $urandom(10); + valuec = $urandom; + if (valuea != valueb && valueb != valuec) $stop; // May false fail 1 in 1^64 + + valuea = $urandom(10); + valueb = $urandom(); + valuec = $urandom(); + if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_sys_readmem.py b/test_regress/t/t_sys_readmem.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_sys_readmem.py +++ b/test_regress/t/t_sys_readmem.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_readmem.v b/test_regress/t/t_sys_readmem.v index 60756207e..1f9d56034 100644 --- a/test_regress/t/t_sys_readmem.v +++ b/test_regress/t/t_sys_readmem.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_sys_readmem_4state.mem b/test_regress/t/t_sys_readmem_4state.mem index b3e4ce7a4..c6f7adc58 100644 --- a/test_regress/t/t_sys_readmem_4state.mem +++ b/test_regress/t/t_sys_readmem_4state.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 0 diff --git a/test_regress/t/t_sys_readmem_4state.py b/test_regress/t/t_sys_readmem_4state.py index 42497e676..aeeeb7891 100755 --- a/test_regress/t/t_sys_readmem_4state.py +++ b/test_regress/t/t_sys_readmem_4state.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_readmem_4state.v b/test_regress/t/t_sys_readmem_4state.v index e7acd7fc2..f51af3035 100644 --- a/test_regress/t/t_sys_readmem_4state.v +++ b/test_regress/t/t_sys_readmem_4state.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_sys_readmem_align_h.mem b/test_regress/t/t_sys_readmem_align_h.mem index 8c37e101e..d42b2f2f4 100644 --- a/test_regress/t/t_sys_readmem_align_h.mem +++ b/test_regress/t/t_sys_readmem_align_h.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 diff --git a/test_regress/t/t_sys_readmem_assoc.py b/test_regress/t/t_sys_readmem_assoc.py index 3ce8d6049..486ef733d 100755 --- a/test_regress/t/t_sys_readmem_assoc.py +++ b/test_regress/t/t_sys_readmem_assoc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_readmem_assoc.v b/test_regress/t/t_sys_readmem_assoc.v index d2a123837..f4322c997 100644 --- a/test_regress/t/t_sys_readmem_assoc.v +++ b/test_regress/t/t_sys_readmem_assoc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_sys_readmem_assoc_bad.py b/test_regress/t/t_sys_readmem_assoc_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_sys_readmem_assoc_bad.py +++ b/test_regress/t/t_sys_readmem_assoc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_readmem_assoc_bad.v b/test_regress/t/t_sys_readmem_assoc_bad.v index 8d6ca224e..ec692956e 100644 --- a/test_regress/t/t_sys_readmem_assoc_bad.v +++ b/test_regress/t/t_sys_readmem_assoc_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_b.mem b/test_regress/t/t_sys_readmem_b.mem index eeec4a511..96d4ce766 100644 --- a/test_regress/t/t_sys_readmem_b.mem +++ b/test_regress/t/t_sys_readmem_b.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # SRecord style comment diff --git a/test_regress/t/t_sys_readmem_b_8.mem b/test_regress/t/t_sys_readmem_b_8.mem index 693796c33..8107a013d 100644 --- a/test_regress/t/t_sys_readmem_b_8.mem +++ b/test_regress/t/t_sys_readmem_b_8.mem @@ -1,10 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// SPDX-FileCopyrightText: 2006 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 // ** Note this file has DOS CR's so we can test them! diff --git a/test_regress/t/t_sys_readmem_bad_addr.mem b/test_regress/t/t_sys_readmem_bad_addr.mem index 7d3c5dbe7..6bf4838da 100644 --- a/test_regress/t/t_sys_readmem_bad_addr.mem +++ b/test_regress/t/t_sys_readmem_bad_addr.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @121212 diff --git a/test_regress/t/t_sys_readmem_bad_addr.py b/test_regress/t/t_sys_readmem_bad_addr.py index be2efa43f..fea74d8c2 100755 --- a/test_regress/t/t_sys_readmem_bad_addr.py +++ b/test_regress/t/t_sys_readmem_bad_addr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_readmem_bad_addr.v b/test_regress/t/t_sys_readmem_bad_addr.v index ce030da54..f2f5ddcd1 100644 --- a/test_regress/t/t_sys_readmem_bad_addr.v +++ b/test_regress/t/t_sys_readmem_bad_addr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_bad_addr2.mem b/test_regress/t/t_sys_readmem_bad_addr2.mem index 85086709b..70ddb3971 100644 --- a/test_regress/t/t_sys_readmem_bad_addr2.mem +++ b/test_regress/t/t_sys_readmem_bad_addr2.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @10x 10x diff --git a/test_regress/t/t_sys_readmem_bad_addr2.py b/test_regress/t/t_sys_readmem_bad_addr2.py index be2efa43f..fea74d8c2 100755 --- a/test_regress/t/t_sys_readmem_bad_addr2.py +++ b/test_regress/t/t_sys_readmem_bad_addr2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_readmem_bad_addr2.v b/test_regress/t/t_sys_readmem_bad_addr2.v index 12f27a92b..c8ffd9b5d 100644 --- a/test_regress/t/t_sys_readmem_bad_addr2.v +++ b/test_regress/t/t_sys_readmem_bad_addr2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_bad_digit.mem b/test_regress/t/t_sys_readmem_bad_digit.mem index c67d16fa3..1157f333b 100644 --- a/test_regress/t/t_sys_readmem_bad_digit.mem +++ b/test_regress/t/t_sys_readmem_bad_digit.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 a0 diff --git a/test_regress/t/t_sys_readmem_bad_digit.py b/test_regress/t/t_sys_readmem_bad_digit.py index be2efa43f..fea74d8c2 100755 --- a/test_regress/t/t_sys_readmem_bad_digit.py +++ b/test_regress/t/t_sys_readmem_bad_digit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_readmem_bad_digit.v b/test_regress/t/t_sys_readmem_bad_digit.v index 52eb6f5ec..ddab6c8af 100644 --- a/test_regress/t/t_sys_readmem_bad_digit.v +++ b/test_regress/t/t_sys_readmem_bad_digit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_bad_end.mem b/test_regress/t/t_sys_readmem_bad_end.mem index ddebc6e54..f4b0ba6f7 100644 --- a/test_regress/t/t_sys_readmem_bad_end.mem +++ b/test_regress/t/t_sys_readmem_bad_end.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 00 diff --git a/test_regress/t/t_sys_readmem_bad_end.py b/test_regress/t/t_sys_readmem_bad_end.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_sys_readmem_bad_end.py +++ b/test_regress/t/t_sys_readmem_bad_end.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_readmem_bad_end.v b/test_regress/t/t_sys_readmem_bad_end.v index 772e74f55..3f9de2a3d 100644 --- a/test_regress/t/t_sys_readmem_bad_end.v +++ b/test_regress/t/t_sys_readmem_bad_end.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_bad_end2.mem b/test_regress/t/t_sys_readmem_bad_end2.mem index d4d4bc48a..a4f3be8d9 100644 --- a/test_regress/t/t_sys_readmem_bad_end2.mem +++ b/test_regress/t/t_sys_readmem_bad_end2.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 10 diff --git a/test_regress/t/t_sys_readmem_bad_notfound.py b/test_regress/t/t_sys_readmem_bad_notfound.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_sys_readmem_bad_notfound.py +++ b/test_regress/t/t_sys_readmem_bad_notfound.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_readmem_bad_notfound.v b/test_regress/t/t_sys_readmem_bad_notfound.v index 910b510dc..ec6d990c9 100644 --- a/test_regress/t/t_sys_readmem_bad_notfound.v +++ b/test_regress/t/t_sys_readmem_bad_notfound.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_c.mem b/test_regress/t/t_sys_readmem_c.mem index 31a4308b5..d6c20f1c6 100644 --- a/test_regress/t/t_sys_readmem_c.mem +++ b/test_regress/t/t_sys_readmem_c.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 diff --git a/test_regress/t/t_sys_readmem_eof.py b/test_regress/t/t_sys_readmem_eof.py index a34d539d0..5e176cb53 100755 --- a/test_regress/t/t_sys_readmem_eof.py +++ b/test_regress/t/t_sys_readmem_eof.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_readmem_eof.v b/test_regress/t/t_sys_readmem_eof.v index a3c604016..dac29b83d 100644 --- a/test_regress/t/t_sys_readmem_eof.v +++ b/test_regress/t/t_sys_readmem_eof.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_sys_readmem_h.mem b/test_regress/t/t_sys_readmem_h.mem index 5974c9c59..90ca00c86 100644 --- a/test_regress/t/t_sys_readmem_h.mem +++ b/test_regress/t/t_sys_readmem_h.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 diff --git a/test_regress/t/t_sys_readmem_i.mem b/test_regress/t/t_sys_readmem_i.mem index 6aa4b23a6..fe52a028b 100644 --- a/test_regress/t/t_sys_readmem_i.mem +++ b/test_regress/t/t_sys_readmem_i.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 diff --git a/test_regress/t/t_sys_readmem_q.mem b/test_regress/t/t_sys_readmem_q.mem index d52d768f8..afbdeaf18 100644 --- a/test_regress/t/t_sys_readmem_q.mem +++ b/test_regress/t/t_sys_readmem_q.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 diff --git a/test_regress/t/t_sys_readmem_s.mem b/test_regress/t/t_sys_readmem_s.mem index ca7a618c0..ec2969c3e 100644 --- a/test_regress/t/t_sys_readmem_s.mem +++ b/test_regress/t/t_sys_readmem_s.mem @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 diff --git a/test_regress/t/t_sys_sformat.py b/test_regress/t/t_sys_sformat.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_sys_sformat.py +++ b/test_regress/t/t_sys_sformat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_sformat.v b/test_regress/t/t_sys_sformat.v index 564d66ec8..9e370f6af 100644 --- a/test_regress/t/t_sys_sformat.v +++ b/test_regress/t/t_sys_sformat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_sformat_noopt.py b/test_regress/t/t_sys_sformat_noopt.py index ad41c3d45..a6f7a1b3a 100755 --- a/test_regress/t/t_sys_sformat_noopt.py +++ b/test_regress/t/t_sys_sformat_noopt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_sscanf.py b/test_regress/t/t_sys_sscanf.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_sys_sscanf.py +++ b/test_regress/t/t_sys_sscanf.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_sscanf.v b/test_regress/t/t_sys_sscanf.v index 53e809960..58fdca399 100644 --- a/test_regress/t/t_sys_sscanf.v +++ b/test_regress/t/t_sys_sscanf.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_sys_strobe.py b/test_regress/t/t_sys_strobe.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_sys_strobe.py +++ b/test_regress/t/t_sys_strobe.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_strobe.v b/test_regress/t/t_sys_strobe.v index 4365344d5..318e84aa3 100644 --- a/test_regress/t/t_sys_strobe.v +++ b/test_regress/t/t_sys_strobe.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_sys_system.py b/test_regress/t/t_sys_system.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_sys_system.py +++ b/test_regress/t/t_sys_system.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_system.v b/test_regress/t/t_sys_system.v index fc3bc66bc..424ffd380 100644 --- a/test_regress/t/t_sys_system.v +++ b/test_regress/t/t_sys_system.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_time.py b/test_regress/t/t_sys_time.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_sys_time.py +++ b/test_regress/t/t_sys_time.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_time.v b/test_regress/t/t_sys_time.v index 58d37931c..7be9b496b 100644 --- a/test_regress/t/t_sys_time.v +++ b/test_regress/t/t_sys_time.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_sys_writemem.py b/test_regress/t/t_sys_writemem.py index 27786c641..2696e7e84 100755 --- a/test_regress/t/t_sys_writemem.py +++ b/test_regress/t/t_sys_writemem.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_sys_writemem_b.py b/test_regress/t/t_sys_writemem_b.py index 902f273e2..3cac96257 100755 --- a/test_regress/t/t_sys_writemem_b.py +++ b/test_regress/t/t_sys_writemem_b.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tagged.out b/test_regress/t/t_tagged.out index 7cf6307f9..513aa3976 100644 --- a/test_regress/t/t_tagged.out +++ b/test_regress/t/t_tagged.out @@ -1,42 +1,69 @@ -%Error-UNSUPPORTED: t/t_tagged.v:9:18: Unsupported: tagged union - 9 | typedef union tagged { - | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_tagged.v:10:6: Unsupported: void (for tagged unions) 10 | void m_invalid; | ^~~~ -%Error: t/t_tagged.v:19:14: syntax error, unexpected tagged, expecting IDENTIFIER-for-type + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_tagged.v:19:14: Unsupported: tagged union 19 | u = tagged m_invalid; | ^~~~~~ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_tagged.v:24:16: Unsupported: matches (for tagged union) +%Error-UNSUPPORTED: t/t_tagged.v:24:7: Unsupported: case matches (for tagged union) 24 | case (u) matches - | ^~~~~~~ -%Error: t/t_tagged.v:29:9: syntax error, unexpected tagged, expecting IDENTIFIER-for-type + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged.v:28:7: Unsupported: case matches (for tagged union) + 28 | case (u) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged.v:29:9: Unsupported: tagged union 29 | tagged m_invalid: ; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:34:34: Unsupported: '{} tagged patterns - 34 | if (u matches tagged m_int .n) $stop; - | ^ -%Error-UNSUPPORTED: t/t_tagged.v:34:21: Unsupported: '{} tagged patterns - 34 | if (u matches tagged m_int .n) $stop; +%Error-UNSUPPORTED: t/t_tagged.v:30:9: Unsupported: tagged union + 30 | tagged m_int: $stop; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:33:13: Unsupported: matches operator + 33 | if (u matches tagged m_invalid) ; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:33:21: Unsupported: tagged union + 33 | if (u matches tagged m_invalid) ; | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged.v:34:13: Unsupported: matches operator 34 | if (u matches tagged m_int .n) $stop; | ^~~~~~~ -%Error: t/t_tagged.v:36:11: syntax error, unexpected tagged, expecting IDENTIFIER-for-type +%Error-UNSUPPORTED: t/t_tagged.v:34:21: Unsupported: tagged pattern + 34 | if (u matches tagged m_int .n) $stop; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:34:34: Unsupported: pattern variable + 34 | if (u matches tagged m_int .n) $stop; + | ^ +%Error-UNSUPPORTED: t/t_tagged.v:36:11: Unsupported: tagged union 36 | u = tagged m_int (123); | ^~~~~~ -%Error: t/t_tagged.v:40:9: syntax error, unexpected tagged, expecting IDENTIFIER-for-type +%Error-UNSUPPORTED: t/t_tagged.v:39:7: Unsupported: case matches (for tagged union) + 39 | case (u) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged.v:40:9: Unsupported: tagged union 40 | tagged m_invalid: $stop; | ^~~~~~ -%Error-UNSUPPORTED: t/t_tagged.v:45:34: Unsupported: '{} tagged patterns - 45 | if (u matches tagged m_int .n) if (n != 123) $stop; - | ^ -%Error-UNSUPPORTED: t/t_tagged.v:45:21: Unsupported: '{} tagged patterns - 45 | if (u matches tagged m_int .n) if (n != 123) $stop; +%Error-UNSUPPORTED: t/t_tagged.v:41:9: Unsupported: tagged pattern + 41 | tagged m_int .n: if (n !== 123) $stop; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:41:22: Unsupported: pattern variable + 41 | tagged m_int .n: if (n !== 123) $stop; + | ^ +%Error-UNSUPPORTED: t/t_tagged.v:44:13: Unsupported: matches operator + 44 | if (u matches tagged m_invalid) $stop; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:44:21: Unsupported: tagged union + 44 | if (u matches tagged m_invalid) $stop; | ^~~~~~ %Error-UNSUPPORTED: t/t_tagged.v:45:13: Unsupported: matches operator 45 | if (u matches tagged m_int .n) if (n != 123) $stop; | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:45:21: Unsupported: tagged pattern + 45 | if (u matches tagged m_int .n) if (n != 123) $stop; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged.v:45:34: Unsupported: pattern variable + 45 | if (u matches tagged m_int .n) if (n != 123) $stop; + | ^ +%Error: t/t_tagged.v:41:30: Can't find definition of variable: 'n' + 41 | tagged m_int .n: if (n !== 123) $stop; + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_tagged.py b/test_regress/t/t_tagged.py index 710a094ab..4ea94519e 100755 --- a/test_regress/t/t_tagged.py +++ b/test_regress/t/t_tagged.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tagged.v b/test_regress/t/t_tagged.v index 23637250c..9dacfaa52 100644 --- a/test_regress/t/t_tagged.v +++ b/test_regress/t/t_tagged.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_tagged_case.out b/test_regress/t/t_tagged_case.out new file mode 100644 index 000000000..36008d067 --- /dev/null +++ b/test_regress/t/t_tagged_case.out @@ -0,0 +1,152 @@ +%Error-UNSUPPORTED: t/t_tagged_case.v:27:5: Unsupported: void (for tagged unions) + 27 | void Invalid; + | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_tagged_case.v:33:5: Unsupported: void (for tagged unions) + 33 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:42:5: Unsupported: void (for tagged unions) + 42 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:63:5: Unsupported: void (for tagged unions) + 63 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:69:5: Unsupported: void (for tagged unions) + 69 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:78:5: Unsupported: void (for tagged unions) + 78 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:85:5: Unsupported: void (for tagged unions) + 85 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:91:5: Unsupported: void (for tagged unions) + 91 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:100:5: Unsupported: void (for tagged unions) + 100 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:124:9: Unsupported: tagged union + 124 | v = tagged Invalid; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:126:5: Unsupported: case matches (for tagged union) + 126 | case (v) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:127:7: Unsupported: tagged union + 127 | tagged Invalid : result = 1; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:128:7: Unsupported: tagged pattern + 128 | tagged Valid .n : result = n; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:128:20: Unsupported: pattern variable + 128 | tagged Valid .n : result = n; + | ^ +%Error-UNSUPPORTED: t/t_tagged_case.v:133:9: Unsupported: tagged union + 133 | v = tagged Valid (123); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:135:5: Unsupported: case matches (for tagged union) + 135 | case (v) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:136:7: Unsupported: tagged union + 136 | tagged Invalid : result = -1; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:137:7: Unsupported: tagged pattern + 137 | tagged Valid .n : result = n; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:137:20: Unsupported: pattern variable + 137 | tagged Valid .n : result = n; + | ^ +%Error-UNSUPPORTED: t/t_tagged_case.v:142:10: Unsupported: tagged union + 142 | wt = tagged Wide60 (60'hFEDCBA987654321); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:144:5: Unsupported: case matches (for tagged union) + 144 | case (wt) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:145:7: Unsupported: tagged union + 145 | tagged Invalid : wide60_result = 0; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:146:7: Unsupported: tagged pattern + 146 | tagged Wide60 .w : wide60_result = w; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:146:21: Unsupported: pattern variable + 146 | tagged Wide60 .w : wide60_result = w; + | ^ +%Error-UNSUPPORTED: t/t_tagged_case.v:152:10: Unsupported: tagged union + 152 | wt = tagged Wide90 (90'hDE_ADBEEFCA_FEBABE12_3456); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:154:5: Unsupported: case matches (for tagged union) + 154 | case (wt) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:155:7: Unsupported: tagged union + 155 | tagged Invalid : wide90_result = 0; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:156:7: Unsupported: tagged pattern + 156 | tagged Wide90 .w : wide90_result = w; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:156:21: Unsupported: pattern variable + 156 | tagged Wide90 .w : wide90_result = w; + | ^ +%Error-UNSUPPORTED: t/t_tagged_case.v:162:10: Unsupported: tagged union + 162 | wt = tagged Byte8NonZeroLSB (8'hA5); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:164:5: Unsupported: case matches (for tagged union) + 164 | case (wt) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:165:7: Unsupported: tagged pattern + 165 | tagged Byte8NonZeroLSB .b : result = b; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:165:30: Unsupported: pattern variable + 165 | tagged Byte8NonZeroLSB .b : result = b; + | ^ +%Error-UNSUPPORTED: t/t_tagged_case.v:171:10: Unsupported: tagged union + 171 | wt = tagged Word32LittleEndian (32'hDEADBEEF); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:173:5: Unsupported: case matches (for tagged union) + 173 | case (wt) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:174:7: Unsupported: tagged pattern + 174 | tagged Word32LittleEndian .w : result = w; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:174:33: Unsupported: pattern variable + 174 | tagged Word32LittleEndian .w : result = w; + | ^ +%Error-UNSUPPORTED: t/t_tagged_case.v:180:10: Unsupported: tagged union + 180 | at = tagged Arr '{10, 20, 30, 40}; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:182:5: Unsupported: case matches (for tagged union) + 182 | case (at) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:183:7: Unsupported: tagged union + 183 | tagged Invalid : result = -1; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:184:7: Unsupported: tagged pattern + 184 | tagged Scalar .s : result = s; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:184:21: Unsupported: pattern variable + 184 | tagged Scalar .s : result = s; + | ^ +%Error-UNSUPPORTED: t/t_tagged_case.v:185:7: Unsupported: tagged pattern + 185 | tagged Arr .a : result = a[0] + a[1] + a[2] + a[3]; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:185:18: Unsupported: pattern variable + 185 | tagged Arr .a : result = a[0] + a[1] + a[2] + a[3]; + | ^ +%Error-UNSUPPORTED: t/t_tagged_case.v:190:13: Unsupported: tagged union + 190 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:190:25: Unsupported: tagged union + 190 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:192:5: Unsupported: case matches (for tagged union) + 192 | case (instr) matches + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:193:7: Unsupported: tagged pattern + 193 | tagged Add .* : result = -1; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_case.v:193:18: Unsupported: pattern wildcard + 193 | tagged Add .* : result = -1; + | ^~ +%Error-UNSUPPORTED: t/t_tagged_case.v:194:7: Unsupported: tagged union + 194 | tagged Jmp (tagged JmpU .a) : result = a; + | ^~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_interface_virtual_unsup.py b/test_regress/t/t_tagged_case.py similarity index 51% rename from test_regress/t/t_interface_virtual_unsup.py rename to test_regress/t/t_tagged_case.py index 966dc53da..4ea94519e 100755 --- a/test_regress/t/t_interface_virtual_unsup.py +++ b/test_regress/t/t_tagged_case.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -13,7 +13,4 @@ test.scenarios('simulator') test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) -if not test.vlt_all: - test.execute() - test.passes() diff --git a/test_regress/t/t_tagged_case.v b/test_regress/t/t_tagged_case.v new file mode 100644 index 000000000..37f4ff28f --- /dev/null +++ b/test_regress/t/t_tagged_case.v @@ -0,0 +1,308 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilator lint_off SHORTREAL + +// Test case pattern matching with tagged unions +// IEEE 1800-2023 Section 12.6.1 + +// Class for testing class references in tagged unions +class TestClass; + int value; + function new(int v); + value = v; + endfunction +endclass + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); + +module t; + + // Basic tagged union (IEEE example) + typedef union tagged { + void Invalid; + int Valid; + } VInt; + + // Tagged union with wide types + typedef union tagged packed { + void Invalid; + bit [8:1] Byte8NonZeroLSB; // Non-zero LSB + bit [0:31] Word32LittleEndian; // Opposite endianness + bit [59:0] Wide60; // 60-bit (33-64 special handling) + bit [89:0] Wide90; // 90-bit (64+ special handling) + } WideType; + + // Tagged union with unpacked array + typedef union tagged { + void Invalid; + int Scalar; + int Arr[4]; // Unpacked array + } ArrayType; + + // Tagged union with nested structure (IEEE example) + typedef union tagged { + struct { + bit [4:0] reg1, reg2, regd; + } Add; + union tagged { + bit [9:0] JmpU; + struct { + bit [1:0] cc; + bit [9:0] addr; + } JmpC; + } Jmp; + } Instr; + + // Tagged union with chandle member + typedef union tagged { + void Invalid; + chandle Handle; + } ChandleType; + + // Tagged union with class reference member + typedef union tagged { + void Invalid; + TestClass Obj; + } ClassType; + + // Enum for testing enum members + typedef enum {RED, GREEN, BLUE} Color; + + // Tagged union with real/shortreal members + typedef union tagged { + void Invalid; + real RealVal; + shortreal ShortRealVal; + } RealType; + + // Tagged union with string member + typedef union tagged { + void Invalid; + string StrVal; + } StringType; + + // Tagged union with enum member + typedef union tagged { + void Invalid; + Color ColorVal; + } EnumType; + +`ifndef VCS + // Tagged union with event member + // Note: VCS incorrectly reports "the event data type is not allowed in structures and unions" + // but IEEE 1800-2023 does not prohibit this + typedef union tagged { + void Invalid; + event EvtVal; + } EventType; +`endif + + VInt v; + WideType wt; + ArrayType at; + Instr instr; + ChandleType cht; + ClassType clt; + TestClass obj; + RealType rt; + StringType st; + EnumType et; +`ifndef VCS + EventType evt; +`endif + int result; + bit [59:0] wide60_result; + bit [89:0] wide90_result; + + initial begin + // Test 1: Basic case matches with void tag + v = tagged Invalid; + result = 0; + case (v) matches + tagged Invalid : result = 1; + tagged Valid .n : result = n; + endcase + `checkh(result, 1); + + // Test 2: Case matches with value binding + v = tagged Valid (123); + result = 0; + case (v) matches + tagged Invalid : result = -1; + tagged Valid .n : result = n; + endcase + `checkh(result, 123); + + // Test 3: Wide type case matching - 60-bit + wt = tagged Wide60 (60'hFEDCBA987654321); + wide60_result = 0; + case (wt) matches + tagged Invalid : wide60_result = 0; + tagged Wide60 .w : wide60_result = w; + default : wide60_result = 0; + endcase + `checkh(wide60_result, 60'hFEDCBA987654321); + + // Test 4: Wide type case matching - 90-bit + wt = tagged Wide90 (90'hDE_ADBEEFCA_FEBABE12_3456); + wide90_result = 0; + case (wt) matches + tagged Invalid : wide90_result = 0; + tagged Wide90 .w : wide90_result = w; + default : wide90_result = 0; + endcase + `checkh(wide90_result, 90'hDE_ADBEEFCA_FEBABE12_3456); + + // Test 5: Non-zero LSB case match + wt = tagged Byte8NonZeroLSB (8'hA5); + result = 0; + case (wt) matches + tagged Byte8NonZeroLSB .b : result = b; + default : result = -1; + endcase + `checkh(result, 8'hA5); + + // Test 6: Opposite endianness case match + wt = tagged Word32LittleEndian (32'hDEADBEEF); + result = 0; + case (wt) matches + tagged Word32LittleEndian .w : result = w; + default : result = -1; + endcase + `checkh(result, 32'hDEADBEEF); + + // Test 7: Array type case matching + at = tagged Arr '{10, 20, 30, 40}; + result = 0; + case (at) matches + tagged Invalid : result = -1; + tagged Scalar .s : result = s; + tagged Arr .a : result = a[0] + a[1] + a[2] + a[3]; + endcase + `checkh(result, 100); + + // Test 8: Nested tagged union case matching + instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); + result = 0; + case (instr) matches + tagged Add .* : result = -1; + tagged Jmp (tagged JmpU .a) : result = a; + tagged Jmp (tagged JmpC '{cc:.c, addr:.a}) : result = a; + endcase + `checkh(result, 256); + + // Test 9: Chandle case matching (no binding - VCS limitation) + cht = tagged Invalid; + result = 0; + case (cht) matches + tagged Invalid : result = 1; + tagged Handle .* : result = 2; // Wildcard - can't bind chandle + endcase + `checkh(result, 1); + + // Test 10: Class reference case matching + obj = new(42); + clt = tagged Obj (obj); + result = 0; + case (clt) matches + tagged Invalid : result = -1; + tagged Obj .o : result = o.value; + endcase + `checkh(result, 42); + + // Test 11: Real member case matching + rt = tagged Invalid; + result = 0; + case (rt) matches + tagged Invalid : result = 1; + tagged RealVal .r : result = 2; + tagged ShortRealVal .r : result = 3; + endcase + `checkh(result, 1); + + rt = tagged RealVal (3.14159); + result = 0; + case (rt) matches + tagged Invalid : result = -1; + tagged RealVal .r : begin + if (r == 3.14159) result = 1; + else result = 2; + end + tagged ShortRealVal .r : result = 3; + endcase + `checkh(result, 1); + + // Test 12: Shortreal member case matching + rt = tagged ShortRealVal (2.5); + result = 0; + case (rt) matches + tagged Invalid : result = -1; + tagged RealVal .r : result = 2; + tagged ShortRealVal .r : begin + if (r == 2.5) result = 1; + else result = 3; + end + endcase + `checkh(result, 1); + + // Test 13: String member case matching + st = tagged Invalid; + result = 0; + case (st) matches + tagged Invalid : result = 1; + tagged StrVal .s : result = 2; + endcase + `checkh(result, 1); + + st = tagged StrVal ("hello"); + result = 0; + case (st) matches + tagged Invalid : result = -1; + tagged StrVal .s : begin + if (s == "hello") result = 1; + else result = 2; + end + endcase + `checkh(result, 1); + + // Test 14: Enum member case matching + et = tagged Invalid; + result = 0; + case (et) matches + tagged Invalid : result = 1; + tagged ColorVal .c : result = 2; + endcase + `checkh(result, 1); + + et = tagged ColorVal (GREEN); + result = 0; + case (et) matches + tagged Invalid : result = -1; + tagged ColorVal .c : begin + if (c == GREEN) result = 1; + else result = 2; + end + endcase + `checkh(result, 1); + +`ifndef VCS + // Test 15: Event member case matching + evt = tagged Invalid; + result = 0; + case (evt) matches + tagged Invalid : result = 1; + tagged EvtVal .* : result = 2; + endcase + `checkh(result, 1); +`endif + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_tagged_if.out b/test_regress/t/t_tagged_if.out new file mode 100644 index 000000000..42c5ebee7 --- /dev/null +++ b/test_regress/t/t_tagged_if.out @@ -0,0 +1,14 @@ +%Error-UNSUPPORTED: t/t_tagged_if.v:216:37: Unsupported: &&& expression + 216 | if (instr matches tagged Jmp .j &&& + | ^~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_tagged_if.v:226:35: Unsupported: &&& expression + 226 | if (v matches tagged Valid .n &&& (n > 50)) + | ^~~ +%Error-UNSUPPORTED: t/t_tagged_if.v:235:35: Unsupported: &&& expression + 235 | if (v matches tagged Valid .n &&& (n > 50)) + | ^~~ +%Error-UNSUPPORTED: t/t_tagged_if.v:264:37: Unsupported: &&& expression + 264 | if (instr matches tagged Jmp .j &&& + | ^~~ +%Error: Exiting due to diff --git a/test_regress/t/t_tagged_if.py b/test_regress/t/t_tagged_if.py new file mode 100755 index 000000000..4ea94519e --- /dev/null +++ b/test_regress/t/t_tagged_if.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tagged_if.v b/test_regress/t/t_tagged_if.v new file mode 100644 index 000000000..b3c816756 --- /dev/null +++ b/test_regress/t/t_tagged_if.v @@ -0,0 +1,414 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilator lint_off SHORTREAL + +// Test if pattern matching with tagged unions +// IEEE 1800-2023 Section 12.6.2 + +// Class for testing class references in tagged unions +class TestClass; + int value; + function new(int v); + value = v; + endfunction +endclass + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); + +module t; + + // Basic tagged union (IEEE example) + typedef union tagged { + void Invalid; + int Valid; + } VInt; + + // Tagged union with wide types + typedef union tagged packed { + void Invalid; + bit [8:1] Byte8NonZeroLSB; // Non-zero LSB + bit [0:31] Word32LittleEndian; // Opposite endianness + bit [59:0] Wide60; // 60-bit (33-64 special handling) + bit [89:0] Wide90; // 90-bit (64+ special handling) + } WideType; + + // Tagged union with unpacked array + typedef union tagged { + void Invalid; + int Scalar; + int Arr[4]; // Unpacked array + } ArrayType; + + // Tagged union with nested structure + typedef union tagged { + struct { + bit [4:0] reg1, reg2, regd; + } Add; + union tagged { + bit [9:0] JmpU; + struct { + bit [1:0] cc; + bit [9:0] addr; + } JmpC; + } Jmp; + } Instr; + + // Tagged union with chandle member + typedef union tagged { + void Invalid; + chandle Handle; + } ChandleType; + + // Tagged union with class reference member + typedef union tagged { + void Invalid; + TestClass Obj; + } ClassType; + + // Enum for testing enum members + typedef enum {RED, GREEN, BLUE} Color; + + // Tagged union with real/shortreal members + typedef union tagged { + void Invalid; + real RealVal; + shortreal ShortRealVal; + } RealType; + + // Tagged union with string member + typedef union tagged { + void Invalid; + string StrVal; + } StringType; + + // Tagged union with enum member + typedef union tagged { + void Invalid; + Color ColorVal; + } EnumType; + +`ifndef VCS + // Tagged union with event member + // Note: VCS incorrectly reports "the event data type is not allowed in structures and unions" + // but IEEE 1800-2023 does not prohibit this + typedef union tagged { + void Invalid; + event EvtVal; + } EventType; +`endif + + VInt v; + WideType wt; + ArrayType at; + Instr instr; + ChandleType cht; + ClassType clt; + TestClass obj; + RealType rt; + StringType st; + EnumType et; +`ifndef VCS + EventType evt; +`endif + int result; + bit [59:0] wide60_result; + bit [89:0] wide90_result; + + initial begin + // Test 1: Basic if matches - void tag + v = tagged Invalid; + result = 0; + if (v matches tagged Invalid) + result = 1; + else + result = 2; + `checkh(result, 1); + + // Test 2: Basic if matches - value with binding + v = tagged Valid (42); + result = 0; + if (v matches tagged Valid .n) + result = n; + else + result = -1; + `checkh(result, 42); + + // Test 3: if-else chain + v = tagged Valid (100); + result = 0; + if (v matches tagged Invalid) + result = 1; + else if (v matches tagged Valid .n) + result = n; + `checkh(result, 100); + + // Test 4: Wide type if matching - 60-bit + wt = tagged Wide60 (60'hFEDCBA987654321); + wide60_result = 0; + if (wt matches tagged Wide60 .w) + wide60_result = w; + else + wide60_result = 0; + `checkh(wide60_result, 60'hFEDCBA987654321); + + // Test 5: Wide type if matching - 90-bit + wt = tagged Wide90 (90'hDE_ADBEEFCA_FEBABE12_3456); + wide90_result = 0; + if (wt matches tagged Wide90 .w) + wide90_result = w; + else + wide90_result = 0; + `checkh(wide90_result, 90'hDE_ADBEEFCA_FEBABE12_3456); + + // Test 6: Non-zero LSB if match + wt = tagged Byte8NonZeroLSB (8'hA5); + result = 0; + if (wt matches tagged Byte8NonZeroLSB .b) + result = b; + else + result = -1; + `checkh(result, 8'hA5); + + // Test 7: Opposite endianness if match + wt = tagged Word32LittleEndian (32'hDEADBEEF); + result = 0; + if (wt matches tagged Word32LittleEndian .w) + result = w; + else + result = -1; + `checkh(result, 32'hDEADBEEF); + + // Test 8: Array type if matching + at = tagged Arr '{10, 20, 30, 40}; + result = 0; + if (at matches tagged Arr .a) + result = a[0] + a[1] + a[2] + a[3]; + else + result = -1; + `checkh(result, 100); + + // Test 9: Array type scalar if match + at = tagged Scalar (999); + result = 0; + if (at matches tagged Scalar .s) + result = s; + else + result = -1; + `checkh(result, 999); + + // Test 10: Nested pattern matching (IEEE example) + instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); + result = 0; + if (instr matches tagged Jmp (tagged JmpC '{cc:.c, addr:.a})) + result = a; // 'a' is bound in pattern + else + result = -1; + `checkh(result, 256); + + // Test 11: Chained matches with &&& (IEEE example) + instr = tagged Jmp (tagged JmpC '{2'd2, 10'd128}); + result = 0; + if (instr matches tagged Jmp .j &&& + j matches tagged JmpC '{cc:.c, addr:.a}) + result = a; // 'a' bound from second pattern + else + result = -1; + `checkh(result, 128); + + // Test 12: Pattern with boolean filter expression + v = tagged Valid (75); + result = 0; + if (v matches tagged Valid .n &&& (n > 50)) + result = 1; + else + result = 2; + `checkh(result, 1); + + // Test 13: Pattern with boolean filter - no match + v = tagged Valid (25); + result = 0; + if (v matches tagged Valid .n &&& (n > 50)) + result = 1; + else + result = 2; + `checkh(result, 2); + + // Test 14: Scope test - bound variable only in true branch + v = tagged Valid (99); + result = 0; + if (v matches tagged Valid .x) begin + result = x; // x is in scope here + end + // x is NOT in scope here (else branch / after) + `checkh(result, 99); + + // Test 15: Add instruction matching + instr = tagged Add '{5'd10, 5'd20, 5'd30}; + result = 0; + if (instr matches tagged Add '{.r1, .r2, .rd}) + result = r1 + r2 + rd; + else + result = -1; + `checkh(result, 60); + + // Test 16: Complex filter with register file simulation + instr = tagged Jmp (tagged JmpC '{2'd3, 10'd100}); + result = 0; + // If conditional jump and condition register is non-zero + // Use nested if for boolean filter (VCS limitation with &&& after chained matches) + if (instr matches tagged Jmp .j &&& + j matches tagged JmpC '{cc:.c, addr:.a}) begin + if (c != 0) + result = a; + else + result = -1; + end else + result = -1; + `checkh(result, 100); + + // Test 17: Unconditional jump matching + instr = tagged Jmp (tagged JmpU 10'd512); + result = 0; + if (instr matches tagged Jmp (tagged JmpU .a)) + result = a; + else + result = -1; + `checkh(result, 512); + + // Test 18: Wildcard pattern in if + instr = tagged Add '{5'd1, 5'd2, 5'd3}; + result = 0; + if (instr matches tagged Add .*) + result = 1; + else if (instr matches tagged Jmp .*) + result = 2; + `checkh(result, 1); + + // Test 19: Chandle member if matching + cht = tagged Invalid; + result = 0; + if (cht matches tagged Invalid) + result = 1; + else + result = 2; + `checkh(result, 1); + + cht = tagged Handle (null); + result = 0; + if (cht matches tagged Handle .*) // Wildcard - VCS can't bind chandle + result = 1; + else + result = 2; + `checkh(result, 1); + + // Test 20: Class reference member if matching + obj = new(42); + clt = tagged Invalid; + result = 0; + if (clt matches tagged Invalid) + result = 1; + else + result = 2; + `checkh(result, 1); + + clt = tagged Obj (obj); + result = 0; + if (clt matches tagged Obj .o) + result = o.value; + else + result = -1; + `checkh(result, 42); + + // Test 21: Real member if matching + rt = tagged Invalid; + result = 0; + if (rt matches tagged Invalid) + result = 1; + else + result = 2; + `checkh(result, 1); + + rt = tagged RealVal (3.14159); + result = 0; + if (rt matches tagged RealVal .r) begin + if (r == 3.14159) + result = 1; + else + result = 2; + end else + result = -1; + `checkh(result, 1); + + // Test 22: Shortreal member if matching + rt = tagged ShortRealVal (2.5); + result = 0; + if (rt matches tagged ShortRealVal .r) begin + if (r == 2.5) + result = 1; + else + result = 2; + end else + result = -1; + `checkh(result, 1); + + // Test 23: String member if matching + st = tagged Invalid; + result = 0; + if (st matches tagged Invalid) + result = 1; + else + result = 2; + `checkh(result, 1); + + st = tagged StrVal ("hello"); + result = 0; + if (st matches tagged StrVal .s) begin + if (s == "hello") + result = 1; + else + result = 2; + end else + result = -1; + `checkh(result, 1); + + // Test 24: Enum member if matching + et = tagged Invalid; + result = 0; + if (et matches tagged Invalid) + result = 1; + else + result = 2; + `checkh(result, 1); + + et = tagged ColorVal (GREEN); + result = 0; + if (et matches tagged ColorVal .c) begin + if (c == GREEN) + result = 1; + else + result = 2; + end else + result = -1; + `checkh(result, 1); + +`ifndef VCS + // Test 25: Event member if matching + evt = tagged Invalid; + result = 0; + if (evt matches tagged Invalid) + result = 1; + else + result = 2; + `checkh(result, 1); +`endif + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_tagged_union.out b/test_regress/t/t_tagged_union.out new file mode 100644 index 000000000..843b15977 --- /dev/null +++ b/test_regress/t/t_tagged_union.out @@ -0,0 +1,152 @@ +%Error-UNSUPPORTED: t/t_tagged_union.v:27:5: Unsupported: void (for tagged unions) + 27 | void Invalid; + | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_tagged_union.v:34:5: Unsupported: void (for tagged unions) + 34 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:55:5: Unsupported: void (for tagged unions) + 55 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:77:5: Unsupported: void (for tagged unions) + 77 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:83:5: Unsupported: void (for tagged unions) + 83 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:92:5: Unsupported: void (for tagged unions) + 92 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:99:5: Unsupported: void (for tagged unions) + 99 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:105:5: Unsupported: void (for tagged unions) + 105 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:114:5: Unsupported: void (for tagged unions) + 114 | void Invalid; + | ^~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:135:11: Unsupported: tagged union + 135 | vi1 = tagged Invalid; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:136:11: Unsupported: tagged union + 136 | vi2 = tagged Invalid; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:139:11: Unsupported: tagged union + 139 | vi1 = tagged Valid (42); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:142:11: Unsupported: tagged union + 142 | vi2 = tagged Valid (23 + 34); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:146:10: Unsupported: tagged union + 146 | mt = tagged Invalid; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:148:10: Unsupported: tagged union + 148 | mt = tagged IntVal (32'h12345678); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:151:10: Unsupported: tagged union + 151 | mt = tagged ShortVal (16'hABCD); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:154:10: Unsupported: tagged union + 154 | mt = tagged ByteVal (8'h5A); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:157:10: Unsupported: tagged union + 157 | mt = tagged BitVal (1'b1); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:161:10: Unsupported: tagged union + 161 | mt = tagged Byte8NonZeroLSB (8'hA5); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:164:10: Unsupported: tagged union + 164 | mt = tagged Word16NonZeroLSB (16'h1234); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:168:10: Unsupported: tagged union + 168 | mt = tagged Word32LittleEndian (32'hDEADBEEF); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:171:10: Unsupported: tagged union + 171 | mt = tagged Word16LittleEndian (16'hCAFE); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:175:10: Unsupported: tagged union + 175 | mt = tagged Wide60 (60'hFEDCBA987654321); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:178:10: Unsupported: tagged union + 178 | mt = tagged Wide60NonZeroLSB (60'h123456789ABCDEF); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:181:10: Unsupported: tagged union + 181 | mt = tagged Wide60LittleEndian (60'hABCDEF012345678); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:185:10: Unsupported: tagged union + 185 | mt = tagged Wide90 (90'hFF_FFFFFFFF_FFFFFFFF_FFFF); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:188:10: Unsupported: tagged union + 188 | mt = tagged Wide90NonZeroLSB (90'hDE_ADBEEFCA_FEBABE12_3456); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:191:10: Unsupported: tagged union + 191 | mt = tagged Wide90LittleEndian (90'h11_11111122_22222233_3333); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:195:10: Unsupported: tagged union + 195 | at = tagged Invalid; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:197:10: Unsupported: tagged union + 197 | at = tagged Scalar (999); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:200:10: Unsupported: tagged union + 200 | at = tagged UnpackedArr '{100, 200, 300, 400}; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:206:10: Unsupported: tagged union + 206 | at = tagged UnpackedArr2D '{'{32'hA, 32'hB, 32'hC}, '{32'hD, 32'hE, 32'hF}}; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:215:13: Unsupported: tagged union + 215 | instr = tagged Add '{5'd1, 5'd2, 5'd3}; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:221:13: Unsupported: tagged union + 221 | instr = tagged Add '{reg2:5'd10, regd:5'd20, reg1:5'd5}; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:227:13: Unsupported: tagged union + 227 | instr = tagged Jmp (tagged JmpU 10'd512); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:227:25: Unsupported: tagged union + 227 | instr = tagged Jmp (tagged JmpU 10'd512); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:231:13: Unsupported: tagged union + 231 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:231:25: Unsupported: tagged union + 231 | instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:236:13: Unsupported: tagged union + 236 | instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100}); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:236:25: Unsupported: tagged union + 236 | instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100}); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:241:11: Unsupported: tagged union + 241 | cht = tagged Invalid; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:242:11: Unsupported: tagged union + 242 | cht = tagged Handle (null); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:246:11: Unsupported: tagged union + 246 | clt = tagged Invalid; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:247:11: Unsupported: tagged union + 247 | clt = tagged Obj (obj); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:251:10: Unsupported: tagged union + 251 | rt = tagged Invalid; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:252:10: Unsupported: tagged union + 252 | rt = tagged RealVal (3.14159); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:256:10: Unsupported: tagged union + 256 | rt = tagged ShortRealVal (2.5); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:260:10: Unsupported: tagged union + 260 | st = tagged Invalid; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:261:10: Unsupported: tagged union + 261 | st = tagged StrVal ("hello"); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_tagged_union.v:265:10: Unsupported: tagged union + 265 | et = tagged Invalid; + | ^~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_tagged_union.py b/test_regress/t/t_tagged_union.py new file mode 100755 index 000000000..4ea94519e --- /dev/null +++ b/test_regress/t/t_tagged_union.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tagged_union.v b/test_regress/t/t_tagged_union.v new file mode 100644 index 000000000..b207c5b88 --- /dev/null +++ b/test_regress/t/t_tagged_union.v @@ -0,0 +1,278 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilator lint_off SHORTREAL + +// Test tagged union declaration, expressions, and member access +// IEEE 1800-2023 Sections 7.3.2, 11.9 + +// Class for testing class references in tagged unions +class TestClass; + int value; + function new(int v); + value = v; + endfunction +endclass + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); + +module t; + + // Basic tagged union with void and int (IEEE example) + typedef union tagged { + void Invalid; + int Valid; + } VInt; + + // Tagged union with multiple data types including wide types + // Tests: non-zero LSBs, 60-bit (33-64 range), 90-bit (64+ range), opposite endianness + typedef union tagged packed { + void Invalid; + int IntVal; + shortint ShortVal; + longint LongVal; + byte ByteVal; + bit BitVal; + logic LogicVal; + bit [8:1] Byte8NonZeroLSB; // Non-zero LSB + bit [16:1] Word16NonZeroLSB; // Non-zero LSB + bit [0:31] Word32LittleEndian; // Opposite endianness + bit [0:15] Word16LittleEndian; // Opposite endianness + bit [59:0] Wide60; // 60-bit (33-64 special handling) + bit [89:0] Wide90; // 90-bit (64+ special handling) + bit [63:4] Wide60NonZeroLSB; // 60-bit with non-zero LSB + bit [99:10] Wide90NonZeroLSB; // 90-bit with non-zero LSB + bit [0:59] Wide60LittleEndian; // 60-bit opposite endianness + bit [0:89] Wide90LittleEndian; // 90-bit opposite endianness + } MultiType; + + // Tagged union with unpacked array members + typedef union tagged { + void Invalid; + int Scalar; + int UnpackedArr[4]; // Unpacked array + bit [31:0] UnpackedArr2D[2][3]; // 2D unpacked array + } ArrayType; + + // Tagged union with nested struct (IEEE example) + typedef union tagged { + struct { + bit [4:0] reg1, reg2, regd; + } Add; + union tagged { + bit [9:0] JmpU; + struct { + bit [1:0] cc; + bit [9:0] addr; + } JmpC; + } Jmp; + } Instr; + + // Tagged union with chandle member + typedef union tagged { + void Invalid; + chandle Handle; + } ChandleType; + + // Tagged union with class reference member + typedef union tagged { + void Invalid; + TestClass Obj; + } ClassType; + + // Enum for testing enum members + typedef enum {RED, GREEN, BLUE} Color; + + // Tagged union with real/shortreal members + typedef union tagged { + void Invalid; + real RealVal; + shortreal ShortRealVal; + } RealType; + + // Tagged union with string member + typedef union tagged { + void Invalid; + string StrVal; + } StringType; + + // Tagged union with enum member + typedef union tagged { + void Invalid; + Color ColorVal; + } EnumType; + +`ifndef VCS + // Tagged union with event member + // Note: VCS incorrectly reports "the event data type is not allowed in structures and unions" + // but IEEE 1800-2023 does not prohibit this + typedef union tagged { + void Invalid; + event EvtVal; + } EventType; +`endif + + VInt vi1, vi2; + MultiType mt; + ArrayType at; + Instr instr; + ChandleType cht; + ClassType clt; + TestClass obj; + RealType rt; + StringType st; + EnumType et; +`ifndef VCS + EventType evt; +`endif + + initial begin + // Test 1: Basic void member + vi1 = tagged Invalid; + vi2 = tagged Invalid; + + // Test 2: Basic value member + vi1 = tagged Valid (42); + `checkh(vi1.Valid, 42); + + vi2 = tagged Valid (23 + 34); + `checkh(vi2.Valid, 57); + + // Test 3: MultiType with various data types + mt = tagged Invalid; + + mt = tagged IntVal (32'h12345678); + `checkh(mt.IntVal, 32'h12345678); + + mt = tagged ShortVal (16'hABCD); + `checkh(mt.ShortVal, 16'hABCD); + + mt = tagged ByteVal (8'h5A); + `checkh(mt.ByteVal, 8'h5A); + + mt = tagged BitVal (1'b1); + `checkh(mt.BitVal, 1'b1); + + // Test 4: Non-zero LSB types + mt = tagged Byte8NonZeroLSB (8'hA5); + `checkh(mt.Byte8NonZeroLSB, 8'hA5); + + mt = tagged Word16NonZeroLSB (16'h1234); + `checkh(mt.Word16NonZeroLSB, 16'h1234); + + // Test 5: Opposite endianness (little-endian style ranges) + mt = tagged Word32LittleEndian (32'hDEADBEEF); + `checkh(mt.Word32LittleEndian, 32'hDEADBEEF); + + mt = tagged Word16LittleEndian (16'hCAFE); + `checkh(mt.Word16LittleEndian, 16'hCAFE); + + // Test 6: Wide types (60-bit, in 33-64 range) + mt = tagged Wide60 (60'hFEDCBA987654321); + `checkh(mt.Wide60, 60'hFEDCBA987654321); + + mt = tagged Wide60NonZeroLSB (60'h123456789ABCDEF); + `checkh(mt.Wide60NonZeroLSB, 60'h123456789ABCDEF); + + mt = tagged Wide60LittleEndian (60'hABCDEF012345678); + `checkh(mt.Wide60LittleEndian, 60'hABCDEF012345678); + + // Test 7: Wide types (90-bit, in 64+ range) + mt = tagged Wide90 (90'hFF_FFFFFFFF_FFFFFFFF_FFFF); + `checkh(mt.Wide90, 90'hFF_FFFFFFFF_FFFFFFFF_FFFF); + + mt = tagged Wide90NonZeroLSB (90'hDE_ADBEEFCA_FEBABE12_3456); + `checkh(mt.Wide90NonZeroLSB, 90'hDE_ADBEEFCA_FEBABE12_3456); + + mt = tagged Wide90LittleEndian (90'h11_11111122_22222233_3333); + `checkh(mt.Wide90LittleEndian, 90'h11_11111122_22222233_3333); + + // Test 8: Unpacked array members + at = tagged Invalid; + + at = tagged Scalar (999); + `checkh(at.Scalar, 999); + + at = tagged UnpackedArr '{100, 200, 300, 400}; + `checkh(at.UnpackedArr[0], 100); + `checkh(at.UnpackedArr[1], 200); + `checkh(at.UnpackedArr[2], 300); + `checkh(at.UnpackedArr[3], 400); + + at = tagged UnpackedArr2D '{'{32'hA, 32'hB, 32'hC}, '{32'hD, 32'hE, 32'hF}}; + `checkh(at.UnpackedArr2D[0][0], 32'hA); + `checkh(at.UnpackedArr2D[0][1], 32'hB); + `checkh(at.UnpackedArr2D[0][2], 32'hC); + `checkh(at.UnpackedArr2D[1][0], 32'hD); + `checkh(at.UnpackedArr2D[1][1], 32'hE); + `checkh(at.UnpackedArr2D[1][2], 32'hF); + + // Test 9: Nested tagged union (Instr example from IEEE) + instr = tagged Add '{5'd1, 5'd2, 5'd3}; + `checkh(instr.Add.reg1, 5'd1); + `checkh(instr.Add.reg2, 5'd2); + `checkh(instr.Add.regd, 5'd3); + + // Create Add with named struct fields + instr = tagged Add '{reg2:5'd10, regd:5'd20, reg1:5'd5}; + `checkh(instr.Add.reg1, 5'd5); + `checkh(instr.Add.reg2, 5'd10); + `checkh(instr.Add.regd, 5'd20); + + // Test 10: Nested tagged union - unconditional jump + instr = tagged Jmp (tagged JmpU 10'd512); + `checkh(instr.Jmp.JmpU, 10'd512); + + // Test 11: Nested tagged union - conditional jump + instr = tagged Jmp (tagged JmpC '{2'd1, 10'd256}); + `checkh(instr.Jmp.JmpC.cc, 2'd1); + `checkh(instr.Jmp.JmpC.addr, 10'd256); + + // Test 12: Nested tagged union - conditional jump with named fields + instr = tagged Jmp (tagged JmpC '{cc:2'd3, addr:10'd100}); + `checkh(instr.Jmp.JmpC.cc, 2'd3); + `checkh(instr.Jmp.JmpC.addr, 10'd100); + + // Test 13: Chandle member + cht = tagged Invalid; + cht = tagged Handle (null); + + // Test 14: Class reference member + obj = new(42); + clt = tagged Invalid; + clt = tagged Obj (obj); + `checkh(clt.Obj.value, 42); + + // Test 15: Real member + rt = tagged Invalid; + rt = tagged RealVal (3.14159); + if (rt.RealVal != 3.14159) $stop; + + // Test 16: Shortreal member + rt = tagged ShortRealVal (2.5); + if (rt.ShortRealVal != 2.5) $stop; + + // Test 17: String member + st = tagged Invalid; + st = tagged StrVal ("hello"); + if (st.StrVal != "hello") $stop; + + // Test 18: Enum member + et = tagged Invalid; + et = tagged ColorVal (GREEN); + if (et.ColorVal != GREEN) $stop; + +`ifndef VCS + // Test 19: Event member + evt = tagged Invalid; +`endif + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_threads_counter.v b/test_regress/t/t_threads_counter.v index b853d69c8..c54808c4b 100644 --- a/test_regress/t/t_threads_counter.v +++ b/test_regress/t/t_threads_counter.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_threads_counter_0.py b/test_regress/t/t_threads_counter_0.py index 0dfdcdbb2..4f2fb2463 100755 --- a/test_regress/t/t_threads_counter_0.py +++ b/test_regress/t/t_threads_counter_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_threads_counter_1.py b/test_regress/t/t_threads_counter_1.py index 7cbd7389e..523b848f4 100755 --- a/test_regress/t/t_threads_counter_1.py +++ b/test_regress/t/t_threads_counter_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_threads_counter_2.py b/test_regress/t/t_threads_counter_2.py index d4ab7e2ba..ea9a7b750 100755 --- a/test_regress/t/t_threads_counter_2.py +++ b/test_regress/t/t_threads_counter_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_threads_counter_4.py b/test_regress/t/t_threads_counter_4.py index 50e637eae..21b4edc8e 100755 --- a/test_regress/t/t_threads_counter_4.py +++ b/test_regress/t/t_threads_counter_4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_threads_crazy.py b/test_regress/t/t_threads_crazy.py index 625fc874d..e63cd97f9 100755 --- a/test_regress/t/t_threads_crazy.py +++ b/test_regress/t/t_threads_crazy.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_threads_crazy.v b/test_regress/t/t_threads_crazy.v index b853d69c8..c54808c4b 100644 --- a/test_regress/t/t_threads_crazy.v +++ b/test_regress/t/t_threads_crazy.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_threads_crazy_context.py b/test_regress/t/t_threads_crazy_context.py index ae52d0316..188cbc1e3 100755 --- a/test_regress/t/t_threads_crazy_context.py +++ b/test_regress/t/t_threads_crazy_context.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_threads_nondeterminism.py b/test_regress/t/t_threads_nondeterminism.py index 51793a66a..207065a57 100755 --- a/test_regress/t/t_threads_nondeterminism.py +++ b/test_regress/t/t_threads_nondeterminism.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time.py b/test_regress/t/t_time.py index 2bf2a6f4f..93cb34ac2 100755 --- a/test_regress/t/t_time.py +++ b/test_regress/t/t_time.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time.v b/test_regress/t/t_time.v index 583e31b0b..02cb20e08 100644 --- a/test_regress/t/t_time.v +++ b/test_regress/t/t_time.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Paul Wright. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Paul Wright // SPDX-License-Identifier: CC0-1.0 /* Working through the $time example from IEEE Std 1364-2005 diff --git a/test_regress/t/t_time_literals.py b/test_regress/t/t_time_literals.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_time_literals.py +++ b/test_regress/t/t_time_literals.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_literals.v b/test_regress/t/t_time_literals.v index 2953c87e7..f533ec552 100644 --- a/test_regress/t/t_time_literals.v +++ b/test_regress/t/t_time_literals.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_time_param.py b/test_regress/t/t_time_param.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_time_param.py +++ b/test_regress/t/t_time_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_param.v b/test_regress/t/t_time_param.v index c27df5d8e..9be7aeac4 100644 --- a/test_regress/t/t_time_param.v +++ b/test_regress/t/t_time_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps diff --git a/test_regress/t/t_time_passed.py b/test_regress/t/t_time_passed.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_time_passed.py +++ b/test_regress/t/t_time_passed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_passed.v b/test_regress/t/t_time_passed.v index 17c9e4274..45a8f5096 100644 --- a/test_regress/t/t_time_passed.v +++ b/test_regress/t/t_time_passed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ps diff --git a/test_regress/t/t_time_print.py b/test_regress/t/t_time_print.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_time_print.py +++ b/test_regress/t/t_time_print.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_print.v b/test_regress/t/t_time_print.v index 9a68cda77..3432497ca 100644 --- a/test_regress/t/t_time_print.v +++ b/test_regress/t/t_time_print.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_time_sc.v b/test_regress/t/t_time_sc.v index 738dca5e1..55fb82691 100644 --- a/test_regress/t/t_time_sc.v +++ b/test_regress/t/t_time_sc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_time_sc_10_ns.py b/test_regress/t/t_time_sc_10_ns.py index 62ffd5f17..9b4251995 100755 --- a/test_regress/t/t_time_sc_10_ns.py +++ b/test_regress/t/t_time_sc_10_ns.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_sc_bad.py b/test_regress/t/t_time_sc_bad.py index 0ca15940f..6dc19a040 100755 --- a/test_regress/t/t_time_sc_bad.py +++ b/test_regress/t/t_time_sc_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_sc_bad_mt.py b/test_regress/t/t_time_sc_bad_mt.py index cf927d9fa..237e904a2 100755 --- a/test_regress/t/t_time_sc_bad_mt.py +++ b/test_regress/t/t_time_sc_bad_mt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_sc_fs.py b/test_regress/t/t_time_sc_fs.py index 70225625c..41f6279a7 100755 --- a/test_regress/t/t_time_sc_fs.py +++ b/test_regress/t/t_time_sc_fs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_sc_ms.py b/test_regress/t/t_time_sc_ms.py index 8027dd32b..6ae867db2 100755 --- a/test_regress/t/t_time_sc_ms.py +++ b/test_regress/t/t_time_sc_ms.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_sc_ns.py b/test_regress/t/t_time_sc_ns.py index 5db5c0710..6c17c824e 100755 --- a/test_regress/t/t_time_sc_ns.py +++ b/test_regress/t/t_time_sc_ns.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_sc_sec.py b/test_regress/t/t_time_sc_sec.py index 4dc51c0c4..44fc52bc9 100755 --- a/test_regress/t/t_time_sc_sec.py +++ b/test_regress/t/t_time_sc_sec.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_sc_us.py b/test_regress/t/t_time_sc_us.py index c93e31e4e..b940d5547 100755 --- a/test_regress/t/t_time_sc_us.py +++ b/test_regress/t/t_time_sc_us.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_sscanf.py b/test_regress/t/t_time_sscanf.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_time_sscanf.py +++ b/test_regress/t/t_time_sscanf.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_sscanf.v b/test_regress/t/t_time_sscanf.v index d2ecd5eb0..a647cc402 100644 --- a/test_regress/t/t_time_sscanf.v +++ b/test_regress/t/t_time_sscanf.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_time_stamp64.py b/test_regress/t/t_time_stamp64.py index b1ae8bfb1..0a7301088 100755 --- a/test_regress/t/t_time_stamp64.py +++ b/test_regress/t/t_time_stamp64.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_stamp64.v b/test_regress/t/t_time_stamp64.v index 7389afb8d..a840ae873 100644 --- a/test_regress/t/t_time_stamp64.v +++ b/test_regress/t/t_time_stamp64.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_time_stamp_double.py b/test_regress/t/t_time_stamp_double.py index 860803ab8..bcde615af 100755 --- a/test_regress/t/t_time_stamp_double.py +++ b/test_regress/t/t_time_stamp_double.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_timeunit.py b/test_regress/t/t_time_timeunit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_time_timeunit.py +++ b/test_regress/t/t_time_timeunit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_timeunit.v b/test_regress/t/t_time_timeunit.v index d1cba1b3e..a558422ae 100644 --- a/test_regress/t/t_time_timeunit.v +++ b/test_regress/t/t_time_timeunit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_time_vpi.v b/test_regress/t/t_time_vpi.v index b39395027..d20fe94b1 100644 --- a/test_regress/t/t_time_vpi.v +++ b/test_regress/t/t_time_vpi.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale `time_scale_units / `time_scale_prec diff --git a/test_regress/t/t_time_vpi_100s10ms.py b/test_regress/t/t_time_vpi_100s10ms.py index cfcf44e95..e0495322e 100755 --- a/test_regress/t/t_time_vpi_100s10ms.py +++ b/test_regress/t/t_time_vpi_100s10ms.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_vpi_10ms10ns.py b/test_regress/t/t_time_vpi_10ms10ns.py index 1851ccf3e..94bd3bf4c 100755 --- a/test_regress/t/t_time_vpi_10ms10ns.py +++ b/test_regress/t/t_time_vpi_10ms10ns.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_vpi_1fs1fs.py b/test_regress/t/t_time_vpi_1fs1fs.py index c95d44318..1d102b525 100755 --- a/test_regress/t/t_time_vpi_1fs1fs.py +++ b/test_regress/t/t_time_vpi_1fs1fs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_vpi_1ms10ns.py b/test_regress/t/t_time_vpi_1ms10ns.py index 501137c36..95203106c 100755 --- a/test_regress/t/t_time_vpi_1ms10ns.py +++ b/test_regress/t/t_time_vpi_1ms10ns.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_vpi_1ns1ns.py b/test_regress/t/t_time_vpi_1ns1ns.py index 8c333e2ec..5c326e3e0 100755 --- a/test_regress/t/t_time_vpi_1ns1ns.py +++ b/test_regress/t/t_time_vpi_1ns1ns.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_vpi_1ps1fs.py b/test_regress/t/t_time_vpi_1ps1fs.py index a85054b1c..b336b2cb4 100755 --- a/test_regress/t/t_time_vpi_1ps1fs.py +++ b/test_regress/t/t_time_vpi_1ps1fs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_vpi_1s10ns.py b/test_regress/t/t_time_vpi_1s10ns.py index ebed040b9..90da3c08c 100755 --- a/test_regress/t/t_time_vpi_1s10ns.py +++ b/test_regress/t/t_time_vpi_1s10ns.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_vpi_1us1ns.py b/test_regress/t/t_time_vpi_1us1ns.py index 4639def59..c509a3f0a 100755 --- a/test_regress/t/t_time_vpi_1us1ns.py +++ b/test_regress/t/t_time_vpi_1us1ns.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_time_vpi_c.cpp b/test_regress/t/t_time_vpi_c.cpp index 86ab6a5ef..4145c0824 100644 --- a/test_regress/t/t_time_vpi_c.cpp +++ b/test_regress/t/t_time_vpi_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2011 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_timescale_default.py b/test_regress/t/t_timescale_default.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_timescale_default.py +++ b/test_regress/t/t_timescale_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timescale_default.v b/test_regress/t/t_timescale_default.v index d5b3461be..976acd39c 100644 --- a/test_regress/t/t_timescale_default.v +++ b/test_regress/t/t_timescale_default.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Intentionally no timescale here, nor in driver file diff --git a/test_regress/t/t_timescale_lint.py b/test_regress/t/t_timescale_lint.py index eb4fffae6..8d16a8c77 100755 --- a/test_regress/t/t_timescale_lint.py +++ b/test_regress/t/t_timescale_lint.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timescale_lint.v b/test_regress/t/t_timescale_lint.v index 0195238f0..42a53545d 100644 --- a/test_regress/t/t_timescale_lint.v +++ b/test_regress/t/t_timescale_lint.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module pre_no_ts; diff --git a/test_regress/t/t_timescale_lint2.py b/test_regress/t/t_timescale_lint2.py index e8ac2b25f..0995c4e84 100755 --- a/test_regress/t/t_timescale_lint2.py +++ b/test_regress/t/t_timescale_lint2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timescale_lint_bad.py b/test_regress/t/t_timescale_lint_bad.py index 3d6a0cca6..faf34a5c9 100755 --- a/test_regress/t/t_timescale_lint_bad.py +++ b/test_regress/t/t_timescale_lint_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timescale_nobackwards.py b/test_regress/t/t_timescale_nobackwards.py index 592c3fc9a..cd7d52fe0 100755 --- a/test_regress/t/t_timescale_nobackwards.py +++ b/test_regress/t/t_timescale_nobackwards.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timescale_nobackwards.v b/test_regress/t/t_timescale_nobackwards.v index 1664fe4fd..2842d7a52 100644 --- a/test_regress/t/t_timescale_nobackwards.v +++ b/test_regress/t/t_timescale_nobackwards.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `define checkf function void f(); $printtimescale; $display("%0t", $time); endfunction diff --git a/test_regress/t/t_timescale_parse.cpp b/test_regress/t/t_timescale_parse.cpp index c3832e868..2769965a4 100644 --- a/test_regress/t/t_timescale_parse.cpp +++ b/test_regress/t/t_timescale_parse.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_timescale_parse.py b/test_regress/t/t_timescale_parse.py index 9d1dcec8d..1864fa13a 100755 --- a/test_regress/t/t_timescale_parse.py +++ b/test_regress/t/t_timescale_parse.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timescale_parse.v b/test_regress/t/t_timescale_parse.v index 2cea437c9..d6ae573b5 100644 --- a/test_regress/t/t_timescale_parse.v +++ b/test_regress/t/t_timescale_parse.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //verilator lint_off REALCVT diff --git a/test_regress/t/t_timescale_parse_bad.py b/test_regress/t/t_timescale_parse_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_timescale_parse_bad.py +++ b/test_regress/t/t_timescale_parse_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timescale_parse_bad.v b/test_regress/t/t_timescale_parse_bad.v index 5832836f7..be77e90eb 100644 --- a/test_regress/t/t_timescale_parse_bad.v +++ b/test_regress/t/t_timescale_parse_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // units < precision diff --git a/test_regress/t/t_timescale_udp.py b/test_regress/t/t_timescale_udp.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_timescale_udp.py +++ b/test_regress/t/t_timescale_udp.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timescale_udp.v b/test_regress/t/t_timescale_udp.v index bbd09408a..2d61a084b 100644 --- a/test_regress/t/t_timescale_udp.v +++ b/test_regress/t/t_timescale_udp.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns diff --git a/test_regress/t/t_timescale_unit.py b/test_regress/t/t_timescale_unit.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_timescale_unit.py +++ b/test_regress/t/t_timescale_unit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timescale_unit.v b/test_regress/t/t_timescale_unit.v index 55ec9e87e..00b95b273 100644 --- a/test_regress/t/t_timescale_unit.v +++ b/test_regress/t/t_timescale_unit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 timeunit 10ps; timeprecision 10ps; diff --git a/test_regress/t/t_timing_always.py b/test_regress/t/t_timing_always.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_always.py +++ b/test_regress/t/t_timing_always.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_always.v b/test_regress/t/t_timing_always.v index ab6644123..5f670b70e 100644 --- a/test_regress/t/t_timing_always.v +++ b/test_regress/t/t_timing_always.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE diff --git a/test_regress/t/t_timing_at_class.py b/test_regress/t/t_timing_at_class.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_timing_at_class.py +++ b/test_regress/t/t_timing_at_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_at_class.v b/test_regress/t/t_timing_at_class.v index 293d68f8f..0bef5f5ff 100644 --- a/test_regress/t/t_timing_at_class.v +++ b/test_regress/t/t_timing_at_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_timing_at_dtype_bad.py b/test_regress/t/t_timing_at_dtype_bad.py index f093111b2..f3bbcad9d 100755 --- a/test_regress/t/t_timing_at_dtype_bad.py +++ b/test_regress/t/t_timing_at_dtype_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_at_dtype_bad.v b/test_regress/t/t_timing_at_dtype_bad.v index d6739051a..72af27a0f 100644 --- a/test_regress/t/t_timing_at_dtype_bad.v +++ b/test_regress/t/t_timing_at_dtype_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_class.py b/test_regress/t/t_timing_class.py index a1700c6d9..a36e184d4 100755 --- a/test_regress/t/t_timing_class.py +++ b/test_regress/t/t_timing_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_class.v b/test_regress/t/t_timing_class.v index 27af2dc3e..4029ddd36 100644 --- a/test_regress/t/t_timing_class.v +++ b/test_regress/t/t_timing_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE @@ -193,12 +193,12 @@ module t; endclass initial begin - DelayClass dc; - Delay10 d10 = new; - Delay20 d20 = new; - Delay40 d40 = new; - NoDelay dNo = new; - AssignDelayClass dAsgn = new; + static DelayClass dc; + static Delay10 d10 = new; + static Delay20 d20 = new; + static Delay40 d40 = new; + static NoDelay dNo = new; + static AssignDelayClass dAsgn = new; `WRITE_VERBOSE(("I'm at time %0t\n", $time)); dc = d10; dc.do_delay; @@ -266,7 +266,7 @@ module t; endclass initial begin - ForkClass fc = new; + automatic ForkClass fc = new; fc.do_fork; if (fc.done != 4 || $time != 70) $stop; end diff --git a/test_regress/t/t_timing_class_static_delay.py b/test_regress/t/t_timing_class_static_delay.py index a1700c6d9..a36e184d4 100755 --- a/test_regress/t/t_timing_class_static_delay.py +++ b/test_regress/t/t_timing_class_static_delay.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_class_static_delay.v b/test_regress/t/t_timing_class_static_delay.v index 8e986829e..9a53bea0c 100644 --- a/test_regress/t/t_timing_class_static_delay.v +++ b/test_regress/t/t_timing_class_static_delay.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define DELAY 10 diff --git a/test_regress/t/t_timing_clkgen1.py b/test_regress/t/t_timing_clkgen1.py index 4fb18ff23..c847f1b57 100755 --- a/test_regress/t/t_timing_clkgen1.py +++ b/test_regress/t/t_timing_clkgen1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_clkgen1.v b/test_regress/t/t_timing_clkgen1.v index d1560f205..c0e12e5eb 100644 --- a/test_regress/t/t_timing_clkgen1.v +++ b/test_regress/t/t_timing_clkgen1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module clkgen(output bit clk); diff --git a/test_regress/t/t_timing_clkgen2.py b/test_regress/t/t_timing_clkgen2.py index c09383bcc..2f72a9f1c 100755 --- a/test_regress/t/t_timing_clkgen2.py +++ b/test_regress/t/t_timing_clkgen2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_clkgen2.v b/test_regress/t/t_timing_clkgen2.v index 4df0b2261..2b9eec094 100644 --- a/test_regress/t/t_timing_clkgen2.v +++ b/test_regress/t/t_timing_clkgen2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE diff --git a/test_regress/t/t_timing_clkgen3.py b/test_regress/t/t_timing_clkgen3.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_clkgen3.py +++ b/test_regress/t/t_timing_clkgen3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_clkgen3.v b/test_regress/t/t_timing_clkgen3.v index 28da638a3..2d6113506 100644 --- a/test_regress/t/t_timing_clkgen3.v +++ b/test_regress/t/t_timing_clkgen3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `timescale 10ns / 1ns diff --git a/test_regress/t/t_timing_clkgen_sc.py b/test_regress/t/t_timing_clkgen_sc.py index f64e24169..4f1bad764 100755 --- a/test_regress/t/t_timing_clkgen_sc.py +++ b/test_regress/t/t_timing_clkgen_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_clkgen_unsup.py b/test_regress/t/t_timing_clkgen_unsup.py index d4146bb3f..841af0c98 100755 --- a/test_regress/t/t_timing_clkgen_unsup.py +++ b/test_regress/t/t_timing_clkgen_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_cmake.py b/test_regress/t/t_timing_cmake.py index b14b62754..956b19829 100755 --- a/test_regress/t/t_timing_cmake.py +++ b/test_regress/t/t_timing_cmake.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_debug1.out b/test_regress/t/t_timing_debug1.out index fec6c3e48..3c603fba5 100644 --- a/test_regress/t/t_timing_debug1.out +++ b/test_regress/t/t_timing_debug1.out @@ -5,17 +5,21 @@ -V{t#,#}+ Initial -V{t#,#}+ Vt_timing_debug1___024root___eval_static -V{t#,#}+ Vt_timing_debug1___024root___eval_static__TOP +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready -V{t#,#}+ Vt_timing_debug1___024root___eval_initial -V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__0 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__1 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__2 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__3 -V{t#,#}+ Vt_timing_debug1___024root___eval_settle -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__stl -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__stl -V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] t.clk1) @@ -33,7 +37,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__stl -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__stl -V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) @@ -45,7 +49,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__stl -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__stl -V{t#,#} No 'stl' region triggers active @@ -53,7 +57,9 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) @@ -62,38 +68,45 @@ -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:48 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -102,14 +115,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 3: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 @@ -119,50 +142,71 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:18 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -171,13 +215,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -186,14 +232,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 6: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 @@ -204,50 +258,70 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -256,14 +330,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 @@ -271,32 +353,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -305,14 +390,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 @@ -322,44 +417,64 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -368,13 +483,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -383,14 +500,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:10 @@ -401,49 +526,66 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'act' region trigger index 8 is active: @(posedge t.clk2) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk2): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 --V{t#,#} Ready processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} Processes to resume waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Processes to resume waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -451,13 +593,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -466,14 +610,21 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:48 @@ -483,56 +634,77 @@ -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:48 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -541,14 +713,23 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 15: Process waiting at t/t_timing_sched.v:10 @@ -556,32 +737,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -590,14 +774,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 15: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 @@ -607,50 +801,71 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:18 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -659,13 +874,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -674,14 +891,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 18: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 19: Process waiting at t/t_timing_sched.v:17 @@ -692,50 +917,70 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -744,14 +989,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 19: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 21: Process waiting at t/t_timing_sched.v:10 @@ -759,32 +1012,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -793,14 +1049,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 21: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 @@ -810,44 +1076,64 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -856,13 +1142,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -871,14 +1159,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 24: Process waiting at t/t_timing_sched.v:10 @@ -889,50 +1185,70 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -941,14 +1257,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 24: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 @@ -959,50 +1283,70 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1011,14 +1355,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 27: Process waiting at t/t_timing_sched.v:10 @@ -1026,32 +1378,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1060,14 +1415,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 27: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 @@ -1077,44 +1442,64 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -1123,13 +1508,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1138,14 +1525,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 31: Process waiting at t/t_timing_sched.v:17 @@ -1156,50 +1551,70 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1208,14 +1623,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 31: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 @@ -1223,32 +1646,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1257,14 +1683,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:10 @@ -1275,28 +1711,40 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) -V{t#,#} 'act' region trigger index 8 is active: @(posedge t.clk2) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 --V{t#,#} Ready processes waiting for @(posedge t.clk2): +-V{t#,#} Processes to resume waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 --V{t#,#} Ready processes waiting for @(posedge t.clk2): +-V{t#,#} Processes to resume waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 @@ -1306,30 +1754,37 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -1338,13 +1793,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1353,14 +1810,21 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 34: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Awaiting time 36: Process waiting at t/t_timing_sched.v:10 @@ -1369,32 +1833,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:48 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1403,14 +1870,23 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 36: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 37: Process waiting at t/t_timing_sched.v:17 @@ -1421,50 +1897,72 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1473,14 +1971,23 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 37: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 39: Process waiting at t/t_timing_sched.v:10 @@ -1488,32 +1995,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1522,14 +2032,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 39: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 @@ -1539,50 +2059,71 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:18 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -1591,13 +2132,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1606,14 +2149,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 42: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 43: Process waiting at t/t_timing_sched.v:17 @@ -1624,50 +2175,70 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1676,14 +2247,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 43: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 @@ -1691,32 +2270,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1725,14 +2307,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 @@ -1742,50 +2334,74 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1794,14 +2410,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 @@ -1811,44 +2437,64 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -1857,13 +2503,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1872,14 +2520,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 48: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 49: Process waiting at t/t_timing_sched.v:17 @@ -1890,50 +2546,70 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1942,14 +2618,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 49: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 51: Process waiting at t/t_timing_sched.v:10 @@ -1957,32 +2641,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1991,14 +2678,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 51: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 @@ -2008,44 +2705,64 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -2054,13 +2771,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2069,14 +2788,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 54: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 @@ -2087,50 +2814,70 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2139,14 +2886,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:17 @@ -2155,55 +2910,74 @@ -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'act' region trigger index 8 is active: @(posedge t.clk2) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk2): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 --V{t#,#} Ready processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} Processes to resume waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Processes to resume waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -2211,13 +2985,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2226,14 +3002,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 56: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Awaiting time 57: Process waiting at t/t_timing_sched.v:10 @@ -2241,32 +3025,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:48 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:48 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2275,14 +3062,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 57: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 @@ -2292,50 +3089,71 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:18 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -2344,13 +3162,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2359,14 +3179,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 61: Process waiting at t/t_timing_sched.v:17 @@ -2377,50 +3205,70 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2429,14 +3277,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 61: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 63: Process waiting at t/t_timing_sched.v:10 @@ -2444,32 +3300,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2478,14 +3337,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 63: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 @@ -2495,44 +3364,64 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -2541,13 +3430,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2556,14 +3447,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:10 @@ -2575,56 +3474,76 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2633,14 +3552,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 67: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 69: Process waiting at t/t_timing_sched.v:10 @@ -2648,32 +3575,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2682,14 +3612,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 69: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 @@ -2699,44 +3639,64 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -2745,13 +3705,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2760,14 +3722,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 72: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 73: Process waiting at t/t_timing_sched.v:17 @@ -2778,50 +3748,70 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2830,14 +3820,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 73: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_sched.v:10 @@ -2845,32 +3843,35 @@ -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2879,14 +3880,24 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 @@ -2896,44 +3907,64 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) -V{t#,#} 'act' region trigger index 6 is active: @(posedge t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk1): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Processes to resume waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming processes waiting for @(posedge t.clk1) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -2942,13 +3973,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -2957,14 +3990,22 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 @@ -2975,49 +4016,66 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 3 is active: @([hybrid] t.clk2) -V{t#,#} 'act' region trigger index 8 is active: @(posedge t.clk2) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#} Ready processes waiting for @(posedge t.clk2): +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:48 --V{t#,#} Ready processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} Processes to resume waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:48 +-V{t#,#} Processes to resume waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:48 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root____VbeforeTrig_h########__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 4 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk1): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba @@ -3025,13 +4083,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -3040,14 +4100,21 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug1___024root___eval -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 7 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:10 @@ -3062,50 +4129,68 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] __VassignWgen_h########__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#} No process to resume waiting for @(posedge t.clk1) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk1): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#} Resuming processes waiting for @(posedge t.clk1) +-V{t#,#} No process to resume waiting for @(posedge t.clk2) +-V{t#,#} Resuming processes waiting for @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_debug1___024root___timing_ready +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug1___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup diff --git a/test_regress/t/t_timing_debug1.py b/test_regress/t/t_timing_debug1.py index 9318069af..94534429f 100755 --- a/test_regress/t/t_timing_debug1.py +++ b/test_regress/t/t_timing_debug1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_debug2.out b/test_regress/t/t_timing_debug2.out index c5b101bbd..15008c9d5 100644 --- a/test_regress/t/t_timing_debug2.out +++ b/test_regress/t/t_timing_debug2.out @@ -2,10 +2,7 @@ -V{t#,#}+ Vt_timing_debug2___024root___ctor_var_reset -V{t#,#}+ Vt_timing_debug2___024unit__03a__03aBaseClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2___024unit___ctor_var_reset --V{t#,#}+ Vt_timing_debug2_std___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t___ctor_var_reset --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess__Vclpkg___ctor_var_reset --V{t#,#}+ Vt_timing_debug2_std__03a__03asemaphore__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass__Vclpkg___ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10__Vclpkg___ctor_var_reset @@ -37,17 +34,6 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::_ctor_var_reset --V{t#,#}+ Vt_timing_debug2___024root___eval_initial --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__0 --V{t#,#} Suspending process waiting for @([event] t.ec.e) at t/t_timing_class.v:111 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__1 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__2 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__3 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__4 --V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_count_5 --V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__5 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10::new @@ -66,6 +52,19 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::_ctor_var_reset +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___eval_initial +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__0 +-V{t#,#}+ Vt_timing_debug2___024root____VbeforeTrig_h########__0 +-V{t#,#} Suspending process waiting for @([event] t.ec.e) at t/t_timing_class.v:111 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__1 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__2 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__3 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__4 +-V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_count_5 +-V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__5 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10::__VnoInFunc_do_delay -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__7 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::new @@ -83,19 +82,19 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:97 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#} Committing processes waiting for @([event] t.ec.e): --V{t#,#} - Process waiting at t/t_timing_class.v:111 --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -104,18 +103,23 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:97 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Not triggered processes waiting for @([event] t.ec.e): +-V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 5: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:173 @@ -131,50 +135,59 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:97 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 -V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 awaiting resumption +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Not triggered processes waiting for @([event] t.ec.e): +-V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:97 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:97 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -183,18 +196,23 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Not triggered processes waiting for @([event] t.ec.e): +-V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:173 -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:247 @@ -215,33 +233,37 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -250,18 +272,23 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Not triggered processes waiting for @([event] t.ec.e): +-V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 15: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 @@ -276,50 +303,59 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:98 awaiting resumption +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Not triggered processes waiting for @([event] t.ec.e): +-V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:98 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:98 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -328,18 +364,23 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Not triggered processes waiting for @([event] t.ec.e): +-V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 @@ -360,26 +401,31 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#} Committing processes waiting for @([event] t.ec.e): +-V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @([event] t.ec.e) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume --V{t#,#} Ready processes waiting for @([event] t.ec.e): +-V{t#,#} Moving to resume queue processes waiting for @([event] t.ec.e): +-V{t#,#} - Process waiting at t/t_timing_class.v:111 +-V{t#,#} Processes to resume waiting for @([event] t.ec.e): -V{t#,#} - Process waiting at t/t_timing_class.v:111 -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:111 -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_sleep -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -388,16 +434,18 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba @@ -405,7 +453,7 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_inc_trig_count -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -414,16 +462,18 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -432,7 +482,7 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -441,17 +491,20 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 @@ -464,7 +517,7 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -473,23 +526,26 @@ -V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:99 awaiting resumption -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:99 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:99 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -498,22 +554,24 @@ -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -522,16 +580,18 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -540,7 +600,7 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -549,17 +609,20 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 @@ -577,7 +640,7 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -586,22 +649,24 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -610,16 +675,18 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -628,7 +695,7 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -637,17 +704,20 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 35: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 @@ -660,7 +730,7 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -669,23 +739,26 @@ -V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:100 awaiting resumption -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:100 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:100 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -694,22 +767,24 @@ -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -718,16 +793,18 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} No 'act' region triggers active -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -736,7 +813,7 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -745,17 +822,20 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:131 @@ -769,7 +849,7 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -778,19 +858,20 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting the post update step --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} 'act' region trigger index 0 is active: @([event] t.ec.e) --V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) -V{t#,#} Doing post updates for processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:37 -V{t#,#} Process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:37 awaiting resumption --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#} 'act' region trigger index 0 is active: @([event] t.ec.e) +-V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume --V{t#,#} No ready processes waiting for @([event] t.ec.e) +-V{t#,#} No process to resume waiting for @([event] t.ec.e) -V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:37 @@ -799,7 +880,7 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aWaitClass::__VnoInFunc_await -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -808,12 +889,14 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba @@ -821,7 +904,7 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_inc_trig_count -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -830,12 +913,14 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -844,7 +929,7 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -853,13 +938,16 @@ -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 @@ -871,7 +959,7 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: @@ -880,44 +968,51 @@ -V{t#,#} Process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:101 awaiting resumption -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:101 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:101 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -926,18 +1021,21 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:131 @@ -950,33 +1048,37 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -985,18 +1087,21 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:123 @@ -1008,33 +1113,37 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1043,18 +1152,21 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Suspending process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:123 -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:131 @@ -1067,18 +1179,21 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 -V{t#,#} Process waiting for @([true] ((32'sh4 == t::WaitClass.a) & (32'sh10 < t::WaitClass.b))) at t/t_timing_class.v:58 awaiting resumption +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:58 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:58 @@ -1088,33 +1203,37 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aLocalWaitClass::__VnoInFunc_await____Vfork_1__1 -V{t#,#} Awaiting join of fork at: t/t_timing_class.v:74 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1123,18 +1242,21 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 65: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 @@ -1146,33 +1268,37 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1181,18 +1307,21 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Suspending process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 @@ -1210,64 +1339,60 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay40::__VnoInFunc_do_sth_else -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay::__VnoInFunc_do_delay -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay::__VnoInFunc_do_sth_else --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess__Vclpkg::__VnoInFunc_self --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess::new --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6____Vfork_1__0 --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess::__VnoInFunc_status --V{t#,#} Suspending process waiting for @([true] (32'h1 != $_EXPRSTMT( // Function: status t.__Vtask___VforkTask_0__25____VforkParent.(t.__Vtask_status__26__Vfuncout); , ); )) at t/t_timing_class.v:224 -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::__VnoInFunc_do_assign -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:76 -V{t#,#} Process forked at t/t_timing_class.v:76 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:224 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} Suspended processes waiting for dynamic trigger evaluation: -V{t#,#} - Process waiting at t/t_timing_class.v:75 --V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:224 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Process waiting for @([true] ((32'sh2a == t::LocalWaitClass.a) | (32'sh64 != t::LocalWaitClass.b))) at t/t_timing_class.v:75 awaiting resumption --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:224 --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess::__VnoInFunc_status --V{t#,#} Process waiting for @([true] (32'h1 != $_EXPRSTMT( // Function: status t.__Vtask___VforkTask_0__25____VforkParent.(t.__Vtask_status__26__Vfuncout); , ); )) at t/t_timing_class.v:224 awaiting resumption +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Resuming processes: -V{t#,#} - Process waiting at t/t_timing_class.v:75 --V{t#,#} - Process waiting at t/t_timing_class.v:224 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:75 -V{t#,#} Process forked at t/t_timing_class.v:75 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:74 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:224 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1276,15 +1401,18 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:224 @@ -1296,27 +1424,31 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:224 -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1325,15 +1457,18 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:190 @@ -1342,54 +1477,37 @@ -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:136 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:190 --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess__Vclpkg::__VnoInFunc_self --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess::new --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6____Vfork_2__0 --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess::__VnoInFunc_status --V{t#,#} Suspending process waiting for @([true] (32'h1 != $_EXPRSTMT( // Function: status t.__Vtask___VforkTask_1__29____VforkParent.(t.__Vtask_status__30__Vfuncout); , ); )) at t/t_timing_class.v:229 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip --V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act --V{t#,#} Suspended processes waiting for dynamic trigger evaluation: --V{t#,#} - Process waiting at t/t_timing_class.v:229 --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:229 --V{t#,#}+ Vt_timing_debug2_std__03a__03aprocess::__VnoInFunc_status --V{t#,#} Process waiting for @([true] (32'h1 != $_EXPRSTMT( // Function: status t.__Vtask___VforkTask_1__29____VforkParent.(t.__Vtask_status__30__Vfuncout); , ); )) at t/t_timing_class.v:229 awaiting resumption --V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#} 'act' region trigger index 2 is active: @([true] __VdynSched.evaluate()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act --V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act --V{t#,#}+ Vt_timing_debug2___024root___timing_resume --V{t#,#} Resuming processes: --V{t#,#} - Process waiting at t/t_timing_class.v:229 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:229 -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::__VnoInFunc_do_assign -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1398,15 +1516,18 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 85: Process waiting at t/t_timing_class.v:230 -V{t#,#} Awaiting time 85: Process waiting at t/t_timing_class.v:131 @@ -1417,27 +1538,31 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1446,15 +1571,18 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:190 -V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:131 @@ -1465,27 +1593,31 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1494,15 +1626,18 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 95: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 @@ -1511,27 +1646,31 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -1540,15 +1679,18 @@ -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 1 is active: @([true] __VdlySched.awaitingCurrentTime()) --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.ec.e) +-V{t#,#} Resuming processes waiting for @([event] t.ec.e) -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:131 @@ -1559,27 +1701,31 @@ -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}+ Vt_timing_debug2___024root___eval_nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_clear__act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_triggers_vec__act -V{t#,#} No suspended processes waiting for dynamic trigger evaluation +-V{t#,#}+ Vt_timing_debug2___024root___timing_ready +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___dump_triggers__act -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_timing_debug2___024root___timing_commit --V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act +-V{t#,#}+ Vt_timing_debug2___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_debug2___024root___eval_phase__inact -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug2___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup diff --git a/test_regress/t/t_timing_debug2.py b/test_regress/t/t_timing_debug2.py index 85d63a27d..18a53b76f 100755 --- a/test_regress/t/t_timing_debug2.py +++ b/test_regress/t/t_timing_debug2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_delay_callstack.py b/test_regress/t/t_timing_delay_callstack.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_delay_callstack.py +++ b/test_regress/t/t_timing_delay_callstack.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_delay_callstack.v b/test_regress/t/t_timing_delay_callstack.v index 995f25d87..d4bbe5959 100644 --- a/test_regress/t/t_timing_delay_callstack.v +++ b/test_regress/t/t_timing_delay_callstack.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_dlyassign.py b/test_regress/t/t_timing_dlyassign.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_dlyassign.py +++ b/test_regress/t/t_timing_dlyassign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_dlyassign.v b/test_regress/t/t_timing_dlyassign.v index 42cefffce..5b7e05054 100644 --- a/test_regress/t/t_timing_dlyassign.v +++ b/test_regress/t/t_timing_dlyassign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 // bug3781 diff --git a/test_regress/t/t_timing_dpi_unsup.cpp b/test_regress/t/t_timing_dpi_unsup.cpp index d8b610a03..1077bcb78 100644 --- a/test_regress/t/t_timing_dpi_unsup.cpp +++ b/test_regress/t/t_timing_dpi_unsup.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Toru Niina. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Toru Niina // SPDX-License-Identifier: CC0-1.0 #include "Vt_timing_dpi__Dpi.h" diff --git a/test_regress/t/t_timing_dpi_unsup.py b/test_regress/t/t_timing_dpi_unsup.py index 06c336dc5..462f02d81 100755 --- a/test_regress/t/t_timing_dpi_unsup.py +++ b/test_regress/t/t_timing_dpi_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_dpi_unsup.v b/test_regress/t/t_timing_dpi_unsup.v index 996ef1e39..1762761e7 100644 --- a/test_regress/t/t_timing_dpi_unsup.v +++ b/test_regress/t/t_timing_dpi_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Toru Niina. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Toru Niina // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE diff --git a/test_regress/t/t_timing_dynscope.py b/test_regress/t/t_timing_dynscope.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_dynscope.py +++ b/test_regress/t/t_timing_dynscope.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_dynscope.v b/test_regress/t/t_timing_dynscope.v index 73cc70d37..cc03503ea 100644 --- a/test_regress/t/t_timing_dynscope.v +++ b/test_regress/t/t_timing_dynscope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `timescale 1ns / 1ns diff --git a/test_regress/t/t_timing_eval_act.out b/test_regress/t/t_timing_eval_act.out new file mode 100644 index 000000000..1d71dde4f --- /dev/null +++ b/test_regress/t/t_timing_eval_act.out @@ -0,0 +1,184 @@ +-V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. +-V{t#,#}+ Vt_timing_eval_act___024root___ctor_var_reset +-V{t#,#}+++++TOP Evaluate Vt_timing_eval_act::eval_step +-V{t#,#}+ Vt_timing_eval_act___024root___eval_debug_assertions +-V{t#,#}+ Initial +-V{t#,#}+ Vt_timing_eval_act___024root___eval_static +-V{t#,#}+ Vt_timing_eval_act___024root___timing_ready +-V{t#,#}+ Vt_timing_eval_act___024root___eval_initial +-V{t#,#}+ Vt_timing_eval_act___024root___eval_initial__TOP__Vtiming__0 +-V{t#,#}+ Vt_timing_eval_act___024root____VbeforeTrig_h########__0 +-V{t#,#} Suspending process waiting for @([event] t.a) at t/t_timing_eval_act.v:18 +-V{t#,#}+ Vt_timing_eval_act___024root___eval_initial__TOP__Vtiming__1 +-V{t#,#}+ Vt_timing_eval_act___024root____VbeforeTrig_h########__0 +-V{t#,#} Suspending process waiting for @(posedge t.clk_inv) at t/t_timing_eval_act.v:25 +-V{t#,#}+ Vt_timing_eval_act___024root___eval_initial__TOP__Vtiming__2 +-V{t#,#}+ Vt_timing_eval_act___024root____VbeforeTrig_h########__0 +-V{t#,#} Suspending process waiting for @([event] t.a) at t/t_timing_eval_act.v:33 +-V{t#,#}+ Vt_timing_eval_act___024root___eval_initial__TOP__Vtiming__3 +-V{t#,#}+ Vt_timing_eval_act___024root___eval_settle +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__stl +-V{t#,#}+ Vt_timing_eval_act___024root___eval_triggers_vec__stl +-V{t#,#}+ Vt_timing_eval_act___024root___dump_triggers__stl +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__stl +-V{t#,#} 'stl' region trigger index 0 is active: Internal 'stl' trigger - first iteration +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__stl +-V{t#,#}+ Vt_timing_eval_act___024root___eval_stl +-V{t#,#}+ Vt_timing_eval_act___024root___act_comb__TOP__0 +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__stl +-V{t#,#}+ Vt_timing_eval_act___024root___eval_triggers_vec__stl +-V{t#,#}+ Vt_timing_eval_act___024root___dump_triggers__stl +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__stl +-V{t#,#} No 'stl' region triggers active +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__stl +-V{t#,#}+ Eval +-V{t#,#}+ Vt_timing_eval_act___024root___eval +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_eval_act___024root___timing_ready +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__inact +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__nba +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#}End-of-eval cleanup +-V{t#,#}+++++TOP Evaluate Vt_timing_eval_act::eval_step +-V{t#,#}+ Vt_timing_eval_act___024root___eval_debug_assertions +-V{t#,#}+ Eval +-V{t#,#}+ Vt_timing_eval_act___024root___eval +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_eval_act___024root___timing_ready +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#} 'act' region trigger index 3 is active: @([true] __VdlySched.awaitingCurrentTime()) +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_eval_act___024root___timing_resume +-V{t#,#} No process to resume waiting for @([event] t.a) +-V{t#,#} Not triggered processes waiting for @([event] t.a): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:18 +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:33 +-V{t#,#} Resuming processes waiting for @([event] t.a) +-V{t#,#} No process to resume waiting for @(posedge t.clk_inv) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk_inv): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:25 +-V{t#,#} Resuming processes waiting for @(posedge t.clk_inv) +-V{t#,#} No process to resume waiting for @([event] t.e) +-V{t#,#} Resuming processes waiting for @([event] t.e) +-V{t#,#} Delayed processes: +-V{t#,#} Awaiting time 1: Process waiting at t/t_timing_eval_act.v:39 +-V{t#,#} Resuming delayed processes +-V{t#,#} Resuming: Process waiting at t/t_timing_eval_act.v:39 +-V{t#,#}+ Vt_timing_eval_act___024root___eval_act +-V{t#,#}+ Vt_timing_eval_act___024root___act_comb__TOP__0 +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_eval_act___024root___timing_ready +-V{t#,#} Committing processes waiting for @([event] t.a): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:18 +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:33 +-V{t#,#} Committing processes waiting for @(posedge t.clk_inv): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:25 +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#} 'act' region trigger index 0 is active: @([event] t.a) +-V{t#,#} 'act' region trigger index 1 is active: @(posedge t.clk_inv) +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_eval_act___024root___timing_resume +-V{t#,#} Moving to resume queue processes waiting for @([event] t.a): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:18 +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:33 +-V{t#,#} Moving to resume queue processes waiting for @(posedge t.clk_inv): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:25 +-V{t#,#} Processes to resume waiting for @([event] t.a): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:18 +-V{t#,#} Processes to resume waiting for @([event] t.a): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:33 +-V{t#,#} Resuming processes waiting for @([event] t.a) +-V{t#,#} Resuming: Process waiting at t/t_timing_eval_act.v:18 +-V{t#,#}+ Vt_timing_eval_act___024root____VbeforeTrig_h########__0 +-V{t#,#} Suspending process waiting for @(posedge t.clk_inv) at t/t_timing_eval_act.v:19 +-V{t#,#} Resuming: Process waiting at t/t_timing_eval_act.v:33 +-V{t#,#}+ Vt_timing_eval_act___024root____VbeforeTrig_h########__0 +-V{t#,#} Suspending process waiting for @([event] t.e) at t/t_timing_eval_act.v:34 +-V{t#,#} Processes to resume waiting for @(posedge t.clk_inv): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:25 +-V{t#,#} Not triggered processes waiting for @(posedge t.clk_inv): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:19 +-V{t#,#} Resuming processes waiting for @(posedge t.clk_inv) +-V{t#,#} Resuming: Process waiting at t/t_timing_eval_act.v:25 +-V{t#,#}+ Vt_timing_eval_act___024root____VbeforeTrig_h########__0 +-V{t#,#} Committing processes waiting for @([event] t.e): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:34 +-V{t#,#} Suspending process waiting for @([event] t.e) at t/t_timing_eval_act.v:28 +-V{t#,#} No process to resume waiting for @([event] t.e) +-V{t#,#} Triggered processes waiting for @([event] t.e): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:28 +-V{t#,#} Not triggered processes waiting for @([event] t.e): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:28 +-V{t#,#} Resuming processes waiting for @([event] t.e) +-V{t#,#}+ Vt_timing_eval_act___024root___eval_act +-V{t#,#}+ Vt_timing_eval_act___024root___act_comb__TOP__0 +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_eval_act___024root___timing_ready +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#} 'act' region trigger index 2 is active: @([event] t.e) +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_eval_act___024root___timing_resume +-V{t#,#} Moving to resume queue processes waiting for @([event] t.e): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:34 +-V{t#,#} No process to resume waiting for @([event] t.a) +-V{t#,#} Resuming processes waiting for @([event] t.a) +-V{t#,#} No process to resume waiting for @(posedge t.clk_inv) +-V{t#,#} Not triggered processes waiting for @(posedge t.clk_inv): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:19 +-V{t#,#} Resuming processes waiting for @(posedge t.clk_inv) +-V{t#,#} Processes to resume waiting for @([event] t.e): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:34 +-V{t#,#} Not triggered processes waiting for @([event] t.e): +-V{t#,#} - Process waiting at t/t_timing_eval_act.v:28 +-V{t#,#} Resuming processes waiting for @([event] t.e) +-V{t#,#} Resuming: Process waiting at t/t_timing_eval_act.v:34 +-V{t#,#}+ Vt_timing_eval_act___024root___eval_act +-V{t#,#}+ Vt_timing_eval_act___024root___act_comb__TOP__0 +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_eval_act___024root___timing_ready +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__inact +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__nba +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_nba +-V{t#,#}+ Vt_timing_eval_act___024root___act_comb__TOP__0 +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_clear__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_triggers_vec__act +-V{t#,#}+ Vt_timing_eval_act___024root___timing_ready +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___dump_triggers__act +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#} No 'act' region triggers active +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__inact +-V{t#,#}+ Vt_timing_eval_act___024root___eval_phase__nba +-V{t#,#}+ Vt_timing_eval_act___024root___trigger_anySet__act +-V{t#,#}End-of-eval cleanup +-V{t#,#}+ Vt_timing_eval_act___024root___eval_final diff --git a/test_regress/t/t_timing_eval_act.py b/test_regress/t/t_timing_eval_act.py new file mode 100755 index 000000000..787745ab3 --- /dev/null +++ b/test_regress/t/t_timing_eval_act.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=["--binary", "--runtime-debug"]) + +test.file_grep( + test.obj_dir + "/" + test.vm_prefix + "___024root__0.cpp", r'void\s+' + test.vm_prefix + + r'___024root___timing_resume\(' + test.vm_prefix + r'___024root\*\s+vlSelf\)\s+\{' + + r'\n((?!})(.|\n))*' + r'\/\*' + test.top_filename + r':18\s0x[0-9a-f]+\*\/\s*' + + r'vlSelfRef\.__VtrigSched_[\d\w]*\.resume\([\n\s]*\"@\(\[event\]\st\.a\)\"\);\n\s+' + r'\/\*' + + test.top_filename + r':19\s0x[0-9a-f]+\*\/\s*' + + r'vlSelfRef\.__VtrigSched_[\d\w]*\.resume\([\n\s]*\"@\(posedge\st\.clk_inv\)\"\);\n\s+' + + r'\/\*' + test.top_filename + r':20\s0x[0-9a-f]+\*\/\s*' + + r'vlSelfRef\.__VtrigSched_[\d\w]*\.resume\([\n\s]*\"@\(\[event\]\st\.e\)\"\);') + +test.execute(all_run_flags=["+verilator+debug"], expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_timing_eval_act.v b/test_regress/t/t_timing_eval_act.v new file mode 100644 index 000000000..22c89c552 --- /dev/null +++ b/test_regress/t/t_timing_eval_act.v @@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module t; + logic clk = 1; + logic clk_inv; + event a; + event e; + + // This $c is required to prevent inlining clk_inv as ~clk + assign clk_inv = $c(1) & ~clk; + + // This is needed to provide right order of resumption in scheduler + initial begin + @a; + @(posedge clk_inv); + @e; + end + + initial begin + forever begin + @(posedge clk_inv) begin + clk = 1; + ->e; + @e; + end + end + end + initial begin + @a; + @e; + if (clk_inv != 0) $stop; + $finish; + end + initial begin + #1; + ->a; + clk = 0; + #2 $stop; + end +endmodule diff --git a/test_regress/t/t_timing_events.py b/test_regress/t/t_timing_events.py index a1700c6d9..a36e184d4 100755 --- a/test_regress/t/t_timing_events.py +++ b/test_regress/t/t_timing_events.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_events.v b/test_regress/t/t_timing_events.v index b9ae56964..e78e4bf60 100644 --- a/test_regress/t/t_timing_events.v +++ b/test_regress/t/t_timing_events.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_finish.py b/test_regress/t/t_timing_finish.py index 671072f97..93e1f30e1 100755 --- a/test_regress/t/t_timing_finish.py +++ b/test_regress/t/t_timing_finish.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_finish.v b/test_regress/t/t_timing_finish.v index a478269ab..19811bc28 100644 --- a/test_regress/t/t_timing_finish.v +++ b/test_regress/t/t_timing_finish.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 program t; diff --git a/test_regress/t/t_timing_finish2.py b/test_regress/t/t_timing_finish2.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_timing_finish2.py +++ b/test_regress/t/t_timing_finish2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_finish2.v b/test_regress/t/t_timing_finish2.v index 57e13c8fd..0bb0c6b44 100644 --- a/test_regress/t/t_timing_finish2.v +++ b/test_regress/t/t_timing_finish2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_timing_finish3.py b/test_regress/t/t_timing_finish3.py new file mode 100755 index 000000000..faf9c77f2 --- /dev/null +++ b/test_regress/t/t_timing_finish3.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.file_grep_not(test.run_log_filename, r'%Error:') # As $finish will suppress $stop + +test.passes() diff --git a/test_regress/t/t_timing_finish3.v b/test_regress/t/t_timing_finish3.v new file mode 100644 index 000000000..4f3246ee2 --- /dev/null +++ b/test_regress/t/t_timing_finish3.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t; + task phase(); + #1000; + $display("ended"); + endtask + + initial begin + fork + phase(); + join_none + #123; + $display("[%0t] $finish", $time); + $finish; + end + + final begin + $display("[%0t] final", $time); + `checkd($time, 123); + end + +endmodule diff --git a/test_regress/t/t_timing_fork_comb.py b/test_regress/t/t_timing_fork_comb.py index c53b55262..45bd2d5a7 100755 --- a/test_regress/t/t_timing_fork_comb.py +++ b/test_regress/t/t_timing_fork_comb.py @@ -1,17 +1,17 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--binary"]) +test.compile(verilator_flags2=["--binary -Wno-UNOPTFLAT"]) test.execute() diff --git a/test_regress/t/t_timing_fork_comb.v b/test_regress/t/t_timing_fork_comb.v index a3d28b0f8..86f45aaff 100644 --- a/test_regress/t/t_timing_fork_comb.v +++ b/test_regress/t/t_timing_fork_comb.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_fork_comb_bad.py b/test_regress/t/t_timing_fork_comb_bad.py new file mode 100755 index 000000000..896c0f0dc --- /dev/null +++ b/test_regress/t/t_timing_fork_comb_bad.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_timing_fork_comb.v" + +# Should convert the first always into combo and detect cycle +test.lint(fails=True, verilator_flags2=["--timing"]) + +test.file_grep( + test.compile_log_filename, + r'%Warning-UNOPTFLAT: t/t_timing_fork_comb.v:\d+:\d+: Signal unoptimizable: Circular combinational logic:' +) + +test.passes() diff --git a/test_regress/t/t_timing_fork_join.py b/test_regress/t/t_timing_fork_join.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_timing_fork_join.py +++ b/test_regress/t/t_timing_fork_join.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_fork_join.v b/test_regress/t/t_timing_fork_join.v index 71865da6a..dc1253ca5 100644 --- a/test_regress/t/t_timing_fork_join.v +++ b/test_regress/t/t_timing_fork_join.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_fork_join_forkproc.py b/test_regress/t/t_timing_fork_join_forkproc.py index e4bcc8e1a..8a325a8b4 100755 --- a/test_regress/t/t_timing_fork_join_forkproc.py +++ b/test_regress/t/t_timing_fork_join_forkproc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_fork_many.py b/test_regress/t/t_timing_fork_many.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_fork_many.py +++ b/test_regress/t/t_timing_fork_many.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_fork_many.v b/test_regress/t/t_timing_fork_many.v index 555865436..1acd7168f 100644 --- a/test_regress/t/t_timing_fork_many.v +++ b/test_regress/t/t_timing_fork_many.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_fork_nba.py b/test_regress/t/t_timing_fork_nba.py index c12d9cce8..f0459883f 100755 --- a/test_regress/t/t_timing_fork_nba.py +++ b/test_regress/t/t_timing_fork_nba.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_fork_nba.v b/test_regress/t/t_timing_fork_nba.v index 013367bdf..fea6be44c 100644 --- a/test_regress/t/t_timing_fork_nba.v +++ b/test_regress/t/t_timing_fork_nba.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_timing_fork_no_timing_ctrl.py b/test_regress/t/t_timing_fork_no_timing_ctrl.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_fork_no_timing_ctrl.py +++ b/test_regress/t/t_timing_fork_no_timing_ctrl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_fork_no_timing_ctrl.v b/test_regress/t/t_timing_fork_no_timing_ctrl.v index 2f9bb387c..bd360c32c 100644 --- a/test_regress/t/t_timing_fork_no_timing_ctrl.v +++ b/test_regress/t/t_timing_fork_no_timing_ctrl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_fork_rec_method.py b/test_regress/t/t_timing_fork_rec_method.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_fork_rec_method.py +++ b/test_regress/t/t_timing_fork_rec_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_fork_rec_method.v b/test_regress/t/t_timing_fork_rec_method.v index c5ddd2d72..f1ee319ee 100644 --- a/test_regress/t/t_timing_fork_rec_method.v +++ b/test_regress/t/t_timing_fork_rec_method.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class RecFork; diff --git a/test_regress/t/t_timing_fork_taskcall.py b/test_regress/t/t_timing_fork_taskcall.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_fork_taskcall.py +++ b/test_regress/t/t_timing_fork_taskcall.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_fork_taskcall.v b/test_regress/t/t_timing_fork_taskcall.v index f2b45b66b..a196e45bb 100644 --- a/test_regress/t/t_timing_fork_taskcall.v +++ b/test_regress/t/t_timing_fork_taskcall.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_func_bad.py b/test_regress/t/t_timing_func_bad.py index 7e3cbabde..bae3b3441 100755 --- a/test_regress/t/t_timing_func_bad.py +++ b/test_regress/t/t_timing_func_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_func_bad.v b/test_regress/t/t_timing_func_bad.v index 1fe88b211..4c59dd44a 100644 --- a/test_regress/t/t_timing_func_bad.v +++ b/test_regress/t/t_timing_func_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_func_fork.py b/test_regress/t/t_timing_func_fork.py index 0c6a8cd25..7de63d925 100755 --- a/test_regress/t/t_timing_func_fork.py +++ b/test_regress/t/t_timing_func_fork.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_func_fork.v b/test_regress/t/t_timing_func_fork.v index 60888a89a..f2ac78370 100644 --- a/test_regress/t/t_timing_func_fork.v +++ b/test_regress/t/t_timing_func_fork.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_func_fork_bad.py b/test_regress/t/t_timing_func_fork_bad.py index b36617573..839174d60 100755 --- a/test_regress/t/t_timing_func_fork_bad.py +++ b/test_regress/t/t_timing_func_fork_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_func_fork_bad.v b/test_regress/t/t_timing_func_fork_bad.v index bbb7aefd9..f2329ddba 100644 --- a/test_regress/t/t_timing_func_fork_bad.v +++ b/test_regress/t/t_timing_func_fork_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_func_join.py b/test_regress/t/t_timing_func_join.py index 671072f97..93e1f30e1 100755 --- a/test_regress/t/t_timing_func_join.py +++ b/test_regress/t/t_timing_func_join.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_func_join.v b/test_regress/t/t_timing_func_join.v index ad8111232..2bd942ffc 100644 --- a/test_regress/t/t_timing_func_join.v +++ b/test_regress/t/t_timing_func_join.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_initial_always.py b/test_regress/t/t_timing_initial_always.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_initial_always.py +++ b/test_regress/t/t_timing_initial_always.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_initial_always.v b/test_regress/t/t_timing_initial_always.v index 1acbc71b0..1587b43c4 100644 --- a/test_regress/t/t_timing_initial_always.v +++ b/test_regress/t/t_timing_initial_always.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_initial_edge.py b/test_regress/t/t_timing_initial_edge.py index 2e1f0f617..c94aaada8 100755 --- a/test_regress/t/t_timing_initial_edge.py +++ b/test_regress/t/t_timing_initial_edge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_initial_edge.v b/test_regress/t/t_timing_initial_edge.v index b1a095085..4ddd10bc1 100644 --- a/test_regress/t/t_timing_initial_edge.v +++ b/test_regress/t/t_timing_initial_edge.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_intra_assign.py b/test_regress/t/t_timing_intra_assign.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_timing_intra_assign.py +++ b/test_regress/t/t_timing_intra_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_intra_assign.v b/test_regress/t/t_timing_intra_assign.v index 15f4f16fd..b5e55596a 100644 --- a/test_regress/t/t_timing_intra_assign.v +++ b/test_regress/t/t_timing_intra_assign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_intra_assign_func.py b/test_regress/t/t_timing_intra_assign_func.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_timing_intra_assign_func.py +++ b/test_regress/t/t_timing_intra_assign_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_intra_assign_func.v b/test_regress/t/t_timing_intra_assign_func.v index 1c8d62fd1..37761c417 100644 --- a/test_regress/t/t_timing_intra_assign_func.v +++ b/test_regress/t/t_timing_intra_assign_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_intra_assign_nolocalize.py b/test_regress/t/t_timing_intra_assign_nolocalize.py index 1f097a2b0..c3804992b 100755 --- a/test_regress/t/t_timing_intra_assign_nolocalize.py +++ b/test_regress/t/t_timing_intra_assign_nolocalize.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_localevent.py b/test_regress/t/t_timing_localevent.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_localevent.py +++ b/test_regress/t/t_timing_localevent.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_localevent.v b/test_regress/t/t_timing_localevent.v index 69aaf8878..0616d0676 100644 --- a/test_regress/t/t_timing_localevent.v +++ b/test_regress/t/t_timing_localevent.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; @@ -31,7 +31,7 @@ module t; endclass initial begin - Foo foo = new; + automatic Foo foo = new; foo.test; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_timing_long.py b/test_regress/t/t_timing_long.py index 1762e724c..e32f87f90 100755 --- a/test_regress/t/t_timing_long.py +++ b/test_regress/t/t_timing_long.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_nba_1.py b/test_regress/t/t_timing_nba_1.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_nba_1.py +++ b/test_regress/t/t_timing_nba_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_nba_1.v b/test_regress/t/t_timing_nba_1.v index 9554a5ad3..23f78baee 100644 --- a/test_regress/t/t_timing_nba_1.v +++ b/test_regress/t/t_timing_nba_1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_nba_2.py b/test_regress/t/t_timing_nba_2.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_nba_2.py +++ b/test_regress/t/t_timing_nba_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_nba_2.v b/test_regress/t/t_timing_nba_2.v index 9f09d4c76..edc969edd 100644 --- a/test_regress/t/t_timing_nba_2.v +++ b/test_regress/t/t_timing_nba_2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_nested_assignment_on_lhs.py b/test_regress/t/t_timing_nested_assignment_on_lhs.py index 2721d0c88..d385ecc55 100755 --- a/test_regress/t/t_timing_nested_assignment_on_lhs.py +++ b/test_regress/t/t_timing_nested_assignment_on_lhs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_nested_assignment_on_lhs.v b/test_regress/t/t_timing_nested_assignment_on_lhs.v index 1bacb5579..1bc99f5ce 100644 --- a/test_regress/t/t_timing_nested_assignment_on_lhs.v +++ b/test_regress/t/t_timing_nested_assignment_on_lhs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class uvm_object_wrapper; diff --git a/test_regress/t/t_timing_off.py b/test_regress/t/t_timing_off.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_off.py +++ b/test_regress/t/t_timing_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_off.v b/test_regress/t/t_timing_off.v index 1f25a7670..5e6d4c8a4 100644 --- a/test_regress/t/t_timing_off.v +++ b/test_regress/t/t_timing_off.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_osc.py b/test_regress/t/t_timing_osc.py index ad21d33c5..c5fbbf167 100755 --- a/test_regress/t/t_timing_osc.py +++ b/test_regress/t/t_timing_osc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_osc.v b/test_regress/t/t_timing_osc.v index af184aacd..410d9ecb2 100644 --- a/test_regress/t/t_timing_osc.v +++ b/test_regress/t/t_timing_osc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_timing_pong.py b/test_regress/t/t_timing_pong.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_pong.py +++ b/test_regress/t/t_timing_pong.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_pong.v b/test_regress/t/t_timing_pong.v index a9972a4a3..bf90b8a29 100644 --- a/test_regress/t/t_timing_pong.v +++ b/test_regress/t/t_timing_pong.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_protect.py b/test_regress/t/t_timing_protect.py index 293a137e9..37979cc9a 100755 --- a/test_regress/t/t_timing_protect.py +++ b/test_regress/t/t_timing_protect.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_reentry.py b/test_regress/t/t_timing_reentry.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_reentry.py +++ b/test_regress/t/t_timing_reentry.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_reentry.v b/test_regress/t/t_timing_reentry.v index 209aa6011..18d44441d 100644 --- a/test_regress/t/t_timing_reentry.v +++ b/test_regress/t/t_timing_reentry.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_sched.py b/test_regress/t/t_timing_sched.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_sched.py +++ b/test_regress/t/t_timing_sched.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_sched.v b/test_regress/t/t_timing_sched.v index 596616a26..f7cb05d99 100644 --- a/test_regress/t/t_timing_sched.v +++ b/test_regress/t/t_timing_sched.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_sched_if.py b/test_regress/t/t_timing_sched_if.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_sched_if.py +++ b/test_regress/t/t_timing_sched_if.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_sched_if.v b/test_regress/t/t_timing_sched_if.v index a3260d9d5..ff199da8b 100644 --- a/test_regress/t/t_timing_sched_if.v +++ b/test_regress/t/t_timing_sched_if.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_sched_nba.py b/test_regress/t/t_timing_sched_nba.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_sched_nba.py +++ b/test_regress/t/t_timing_sched_nba.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_sched_nba.v b/test_regress/t/t_timing_sched_nba.v index f4d622eca..1650c1b62 100644 --- a/test_regress/t/t_timing_sched_nba.v +++ b/test_regress/t/t_timing_sched_nba.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_split.py b/test_regress/t/t_timing_split.py index 15b97428a..2d81294fe 100755 --- a/test_regress/t/t_timing_split.py +++ b/test_regress/t/t_timing_split.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_split.v b/test_regress/t/t_timing_split.v index f7fd5d8de..cd33fa6af 100644 --- a/test_regress/t/t_timing_split.v +++ b/test_regress/t/t_timing_split.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Jomit626. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2023 Jomit626 // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_timing_strobe.py b/test_regress/t/t_timing_strobe.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_timing_strobe.py +++ b/test_regress/t/t_timing_strobe.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_strobe.v b/test_regress/t/t_timing_strobe.v index f3ddfbca5..0e1fb82a1 100644 --- a/test_regress/t/t_timing_strobe.v +++ b/test_regress/t/t_timing_strobe.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_suspend_two_retrigger.py b/test_regress/t/t_timing_suspend_two_retrigger.py index aa5dacc93..3c6aa8922 100755 --- a/test_regress/t/t_timing_suspend_two_retrigger.py +++ b/test_regress/t/t_timing_suspend_two_retrigger.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_suspend_two_retrigger.v b/test_regress/t/t_timing_suspend_two_retrigger.v index 840e9790f..c5c10388a 100644 --- a/test_regress/t/t_timing_suspend_two_retrigger.v +++ b/test_regress/t/t_timing_suspend_two_retrigger.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module top; diff --git a/test_regress/t/t_timing_suspendable_deep.py b/test_regress/t/t_timing_suspendable_deep.py index 6bfd7cf18..08f671ec4 100755 --- a/test_regress/t/t_timing_suspendable_deep.py +++ b/test_regress/t/t_timing_suspendable_deep.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_suspendable_deep.v b/test_regress/t/t_timing_suspendable_deep.v index 32ecd0a4c..f5f7bdfa5 100644 --- a/test_regress/t/t_timing_suspendable_deep.v +++ b/test_regress/t/t_timing_suspendable_deep.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module for specialized type default values // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2023 Antmicro // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns diff --git a/test_regress/t/t_timing_timescale.out b/test_regress/t/t_timing_timescale.out index e28ab2ef6..c15c7c853 100644 --- a/test_regress/t/t_timing_timescale.out +++ b/test_regress/t/t_timing_timescale.out @@ -22,5 +22,5 @@ [1e-05] clkb is 1 [1e-05] Finishing (t.bot) *-* All Finished *-* -[10500] final (t) -[1.05e-05] final (t.bot) count was 21 +[10000] final (t) +[1e-05] final (t.bot) count was 21 diff --git a/test_regress/t/t_timing_timescale.py b/test_regress/t/t_timing_timescale.py index 1407fff26..bf27a0db2 100755 --- a/test_regress/t/t_timing_timescale.py +++ b/test_regress/t/t_timing_timescale.py @@ -1,17 +1,17 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--binary"]) +test.compile(verilator_flags2=["--binary", "--no-sched-zero-delay"]) test.execute(expect_filename=test.golden_filename) diff --git a/test_regress/t/t_timing_timescale.v b/test_regress/t/t_timing_timescale.v index 1ec17d076..74a834ee7 100644 --- a/test_regress/t/t_timing_timescale.v +++ b/test_regress/t/t_timing_timescale.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Paul Wright. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Paul Wright // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_trace.py b/test_regress/t/t_timing_trace.py index a9e870917..9b67765f6 100755 --- a/test_regress/t/t_timing_trace.py +++ b/test_regress/t/t_timing_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_trace.v b/test_regress/t/t_timing_trace.v index 393056f7a..c9ebb3a6f 100644 --- a/test_regress/t/t_timing_trace.v +++ b/test_regress/t/t_timing_trace.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_timing_trace_fst.py b/test_regress/t/t_timing_trace_fst.py index 07adb63b1..9e3c60240 100755 --- a/test_regress/t/t_timing_trace_fst.py +++ b/test_regress/t/t_timing_trace_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_trace_saif.py b/test_regress/t/t_timing_trace_saif.py index 6353b22ee..d4db413f3 100755 --- a/test_regress/t/t_timing_trace_saif.py +++ b/test_regress/t/t_timing_trace_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_unset1.py b/test_regress/t/t_timing_unset1.py index d50e1d8f9..c53ad57ac 100755 --- a/test_regress/t/t_timing_unset1.py +++ b/test_regress/t/t_timing_unset1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_unset2.py b/test_regress/t/t_timing_unset2.py index e19a52246..ad3da7d5f 100755 --- a/test_regress/t/t_timing_unset2.py +++ b/test_regress/t/t_timing_unset2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_unset3.py b/test_regress/t/t_timing_unset3.py index 5ff23db31..5acb5022a 100755 --- a/test_regress/t/t_timing_unset3.py +++ b/test_regress/t/t_timing_unset3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_wait1.py b/test_regress/t/t_timing_wait1.py index c363d0e6e..96df3e890 100755 --- a/test_regress/t/t_timing_wait1.py +++ b/test_regress/t/t_timing_wait1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_wait1.v b/test_regress/t/t_timing_wait1.v index 146e84ab2..0506ea95f 100644 --- a/test_regress/t/t_timing_wait1.v +++ b/test_regress/t/t_timing_wait1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_VERBOSE diff --git a/test_regress/t/t_timing_wait2.py b/test_regress/t/t_timing_wait2.py index 1407fff26..55248e18d 100755 --- a/test_regress/t/t_timing_wait2.py +++ b/test_regress/t/t_timing_wait2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_wait2.v b/test_regress/t/t_timing_wait2.v index 0bb5ec6b5..ec9bd33f8 100644 --- a/test_regress/t/t_timing_wait2.v +++ b/test_regress/t/t_timing_wait2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_wait3.py b/test_regress/t/t_timing_wait3.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_wait3.py +++ b/test_regress/t/t_timing_wait3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_wait3.v b/test_regress/t/t_timing_wait3.v index d898664ea..157bef253 100644 --- a/test_regress/t/t_timing_wait3.v +++ b/test_regress/t/t_timing_wait3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_timing_wait_long.py b/test_regress/t/t_timing_wait_long.py index 1407fff26..bf27a0db2 100755 --- a/test_regress/t/t_timing_wait_long.py +++ b/test_regress/t/t_timing_wait_long.py @@ -1,17 +1,17 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--binary"]) +test.compile(verilator_flags2=["--binary", "--no-sched-zero-delay"]) test.execute(expect_filename=test.golden_filename) diff --git a/test_regress/t/t_timing_wait_long.v b/test_regress/t/t_timing_wait_long.v index c9417b913..55dc9ae53 100644 --- a/test_regress/t/t_timing_wait_long.v +++ b/test_regress/t/t_timing_wait_long.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps diff --git a/test_regress/t/t_timing_write_expr.py b/test_regress/t/t_timing_write_expr.py index a4406cb80..bb3cf3bf1 100755 --- a/test_regress/t/t_timing_write_expr.py +++ b/test_regress/t/t_timing_write_expr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_write_expr.v b/test_regress/t/t_timing_write_expr.v index b66895d0d..f8d1d4bfc 100644 --- a/test_regress/t/t_timing_write_expr.v +++ b/test_regress/t/t_timing_write_expr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2023 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_zerodly.py b/test_regress/t/t_timing_zerodly.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_zerodly.py +++ b/test_regress/t/t_timing_zerodly.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_zerodly.v b/test_regress/t/t_timing_zerodly.v index 941c6df01..c6bf71719 100644 --- a/test_regress/t/t_timing_zerodly.v +++ b/test_regress/t/t_timing_zerodly.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_timing_zerodly_2.py b/test_regress/t/t_timing_zerodly_2.py new file mode 100755 index 000000000..b857f2819 --- /dev/null +++ b/test_regress/t/t_timing_zerodly_2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--exe --main --timing"]) + +test.execute(check_finished=True) + +test.passes() diff --git a/test_regress/t/t_timing_zerodly_unsup.v b/test_regress/t/t_timing_zerodly_2.v similarity index 79% rename from test_regress/t/t_timing_zerodly_unsup.v rename to test_regress/t/t_timing_zerodly_2.v index 5c10fa12e..b0c6417e6 100644 --- a/test_regress/t/t_timing_zerodly_unsup.v +++ b/test_regress/t/t_timing_zerodly_2.v @@ -1,26 +1,31 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t; +module top; logic v; int num; + time t; initial begin num = 1; #1; if (v) $stop; num = 21; + t = $time; // Zero delay should postpone the execution and resume it after // evaluating combinational logic which would update `v`. However, // currently we can't postpone the resumption in the current timeframe // past the combinatorial logic evaluation as that is intertwined with // NBA evaluation and partitioned for multithreading. This causes `v` // to not have its value updated despite being checked after #0 delay. - #0 if (v) $finish; - $stop; + #0; + if (!v) $stop; + if (t != $time) $stop; + $write("*-* All Finished *-*\n"); + $finish; end always_comb v = (num == 21); diff --git a/test_regress/t/t_timing_zerodly_consecutive.py b/test_regress/t/t_timing_zerodly_consecutive.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_timing_zerodly_consecutive.py +++ b/test_regress/t/t_timing_zerodly_consecutive.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_timing_zerodly_consecutive.v b/test_regress/t/t_timing_zerodly_consecutive.v index 5ff5817c5..af744cecb 100644 --- a/test_regress/t/t_timing_zerodly_consecutive.v +++ b/test_regress/t/t_timing_zerodly_consecutive.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_timing_zerodly_unsup.out b/test_regress/t/t_timing_zerodly_unsup.out deleted file mode 100644 index 8e56ef2cf..000000000 --- a/test_regress/t/t_timing_zerodly_unsup.out +++ /dev/null @@ -1,3 +0,0 @@ -%Warning: t/t_timing_zerodly_unsup.v:22: Encountered #0 delay. #0 scheduling support is incomplete and the process will be resumed before combinational logic evaluation. -%Error: t/t_timing_zerodly_unsup.v:23: Verilog $stop -Aborting... diff --git a/test_regress/t/t_timing_zerodly_unsup.py b/test_regress/t/t_timing_zerodly_unsup.py deleted file mode 100755 index ea4425d51..000000000 --- a/test_regress/t/t_timing_zerodly_unsup.py +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('simulator') - -test.compile(verilator_flags2=["--exe --main --timing"]) - -test.execute(fails=True, expect_filename=test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_trace_abort.py b/test_regress/t/t_trace_abort.py index b1fca5884..2ce07b064 100755 --- a/test_regress/t/t_trace_abort.py +++ b/test_regress/t/t_trace_abort.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_abort.v b/test_regress/t/t_trace_abort.v index b39927aad..94daf2528 100644 --- a/test_regress/t/t_trace_abort.v +++ b/test_regress/t/t_trace_abort.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_abort_fst.py b/test_regress/t/t_trace_abort_fst.py index d3606912a..86cb92b46 100755 --- a/test_regress/t/t_trace_abort_fst.py +++ b/test_regress/t/t_trace_abort_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_abort_fst_sc.py b/test_regress/t/t_trace_abort_fst_sc.py index 1e6f9c314..11117a842 100755 --- a/test_regress/t/t_trace_abort_fst_sc.py +++ b/test_regress/t/t_trace_abort_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_abort_saif.py b/test_regress/t/t_trace_abort_saif.py index 07166486e..3d5f8c1dd 100755 --- a/test_regress/t/t_trace_abort_saif.py +++ b/test_regress/t/t_trace_abort_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array.py b/test_regress/t/t_trace_array.py index 7761ba3c2..5a6c2da8b 100755 --- a/test_regress/t/t_trace_array.py +++ b/test_regress/t/t_trace_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array.v b/test_regress/t/t_trace_array.v index 233ede17e..7fa389382 100644 --- a/test_regress/t/t_trace_array.v +++ b/test_regress/t/t_trace_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_trace_array_fst.py b/test_regress/t/t_trace_array_fst.py index 3904c62b3..9d4d511f1 100755 --- a/test_regress/t/t_trace_array_fst.py +++ b/test_regress/t/t_trace_array_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_fst_portable.py b/test_regress/t/t_trace_array_fst_portable.py index eae37db14..ad8ce0000 100755 --- a/test_regress/t/t_trace_array_fst_portable.py +++ b/test_regress/t/t_trace_array_fst_portable.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_fst_portable_sc.py b/test_regress/t/t_trace_array_fst_portable_sc.py index 7f61d608b..c7fa01c2e 100755 --- a/test_regress/t/t_trace_array_fst_portable_sc.py +++ b/test_regress/t/t_trace_array_fst_portable_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_fst_sc.py b/test_regress/t/t_trace_array_fst_sc.py index f52ca446e..ade50f8f3 100755 --- a/test_regress/t/t_trace_array_fst_sc.py +++ b/test_regress/t/t_trace_array_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_fst_threads_1.py b/test_regress/t/t_trace_array_fst_threads_1.py index 22a40102b..9850941a4 100755 --- a/test_regress/t/t_trace_array_fst_threads_1.py +++ b/test_regress/t/t_trace_array_fst_threads_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_fst_threads_1_sc.py b/test_regress/t/t_trace_array_fst_threads_1_sc.py index 892a2c1c5..d1288dc04 100755 --- a/test_regress/t/t_trace_array_fst_threads_1_sc.py +++ b/test_regress/t/t_trace_array_fst_threads_1_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_fst_threads_2.py b/test_regress/t/t_trace_array_fst_threads_2.py index 15f369fde..bcd82d977 100755 --- a/test_regress/t/t_trace_array_fst_threads_2.py +++ b/test_regress/t/t_trace_array_fst_threads_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_fst_threads_2_sc.py b/test_regress/t/t_trace_array_fst_threads_2_sc.py index fe92dee32..ba21ee799 100755 --- a/test_regress/t/t_trace_array_fst_threads_2_sc.py +++ b/test_regress/t/t_trace_array_fst_threads_2_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_saif.py b/test_regress/t/t_trace_array_saif.py index 000fd2266..971a83073 100755 --- a/test_regress/t/t_trace_array_saif.py +++ b/test_regress/t/t_trace_array_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_saif_portable.py b/test_regress/t/t_trace_array_saif_portable.py index 7843a54cd..83f1a69e1 100755 --- a/test_regress/t/t_trace_array_saif_portable.py +++ b/test_regress/t/t_trace_array_saif_portable.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_saif_threads_1.py b/test_regress/t/t_trace_array_saif_threads_1.py index faaab87a7..578dea917 100755 --- a/test_regress/t/t_trace_array_saif_threads_1.py +++ b/test_regress/t/t_trace_array_saif_threads_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_saif_threads_2.py b/test_regress/t/t_trace_array_saif_threads_2.py index 4c0584abe..a021561be 100755 --- a/test_regress/t/t_trace_array_saif_threads_2.py +++ b/test_regress/t/t_trace_array_saif_threads_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_array_threads_1.py b/test_regress/t/t_trace_array_threads_1.py index 482670e3e..7a46dccae 100755 --- a/test_regress/t/t_trace_array_threads_1.py +++ b/test_regress/t/t_trace_array_threads_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_ascendingrange.py b/test_regress/t/t_trace_ascendingrange.py index 6d7562957..13da9fc7d 100755 --- a/test_regress/t/t_trace_ascendingrange.py +++ b/test_regress/t/t_trace_ascendingrange.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_ascendingrange.v b/test_regress/t/t_trace_ascendingrange.v index 348b80ea6..0ff3c8116 100644 --- a/test_regress/t/t_trace_ascendingrange.v +++ b/test_regress/t/t_trace_ascendingrange.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t #( diff --git a/test_regress/t/t_trace_ascendingrange_fst.py b/test_regress/t/t_trace_ascendingrange_fst.py index 2f812bb4c..f9aeccc2c 100755 --- a/test_regress/t/t_trace_ascendingrange_fst.py +++ b/test_regress/t/t_trace_ascendingrange_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_ascendingrange_fst_sc.py b/test_regress/t/t_trace_ascendingrange_fst_sc.py index a01e6692e..ca8083273 100755 --- a/test_regress/t/t_trace_ascendingrange_fst_sc.py +++ b/test_regress/t/t_trace_ascendingrange_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_ascendingrange_saif.py b/test_regress/t/t_trace_ascendingrange_saif.py index d56cb885a..31d24956a 100755 --- a/test_regress/t/t_trace_ascendingrange_saif.py +++ b/test_regress/t/t_trace_ascendingrange_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_binary.py b/test_regress/t/t_trace_binary.py index 2737cb863..8ce45feda 100755 --- a/test_regress/t/t_trace_binary.py +++ b/test_regress/t/t_trace_binary.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_binary.v b/test_regress/t/t_trace_binary.v index 8534536f5..79f5da68d 100644 --- a/test_regress/t/t_trace_binary.v +++ b/test_regress/t/t_trace_binary.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_binary_flag_off.py b/test_regress/t/t_trace_binary_flag_off.py index 2e846b7e1..23d2f7b36 100755 --- a/test_regress/t/t_trace_binary_flag_off.py +++ b/test_regress/t/t_trace_binary_flag_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_cat.cpp b/test_regress/t/t_trace_cat.cpp index 7b6b9ec26..7743ed677 100644 --- a/test_regress/t/t_trace_cat.cpp +++ b/test_regress/t/t_trace_cat.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_cat.py b/test_regress/t/t_trace_cat.py index 28d5fec65..27eba700e 100755 --- a/test_regress/t/t_trace_cat.py +++ b/test_regress/t/t_trace_cat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_cat.v b/test_regress/t/t_trace_cat.v index 7428682b5..d7adc992c 100644 --- a/test_regress/t/t_trace_cat.v +++ b/test_regress/t/t_trace_cat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_trace_cat_fst.cpp b/test_regress/t/t_trace_cat_fst.cpp index 2467ebc39..08aa9695c 100644 --- a/test_regress/t/t_trace_cat_fst.cpp +++ b/test_regress/t/t_trace_cat_fst.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_cat_fst.py b/test_regress/t/t_trace_cat_fst.py index f5ba2fd2e..a06f27bb3 100755 --- a/test_regress/t/t_trace_cat_fst.py +++ b/test_regress/t/t_trace_cat_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_cat_fst.v b/test_regress/t/t_trace_cat_fst.v index e56dc4a09..f74fec5d5 100644 --- a/test_regress/t/t_trace_cat_fst.v +++ b/test_regress/t/t_trace_cat_fst.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_trace_cat_renew.py b/test_regress/t/t_trace_cat_renew.py index e973db65f..251b94f4f 100755 --- a/test_regress/t/t_trace_cat_renew.py +++ b/test_regress/t/t_trace_cat_renew.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_cat_reopen.py b/test_regress/t/t_trace_cat_reopen.py index e973db65f..251b94f4f 100755 --- a/test_regress/t/t_trace_cat_reopen.py +++ b/test_regress/t/t_trace_cat_reopen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_class.py b/test_regress/t/t_trace_class.py index 95ad1b66e..10f302681 100755 --- a/test_regress/t/t_trace_class.py +++ b/test_regress/t/t_trace_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_class.v b/test_regress/t/t_trace_class.v index fdb3438a5..035eda7ed 100644 --- a/test_regress/t/t_trace_class.v +++ b/test_regress/t/t_trace_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_complex.out b/test_regress/t/t_trace_complex.out index 82004c937..dbfe9faa0 100644 --- a/test_regress/t/t_trace_complex.out +++ b/test_regress/t/t_trace_complex.out @@ -1,56 +1,50 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end - $var wire 1 = clk $end + $var wire 1 : clk $end $scope module $unit $end - $var wire 1 # global_bit $end + $var wire 1 " global_bit $end $upscope $end $scope module t $end - $var wire 1 = clk $end - $var wire 32 $ cyc [31:0] $end - $var wire 2 % v_strp [1:0] $end - $var wire 4 & v_strp_strp [3:0] $end - $var wire 2 ' v_unip_strp [1:0] $end - $var wire 2 ( v_arrp [2:1] $end - $var wire 4 ) v_arrp_arrp [3:0] $end - $var wire 4 * v_arrp_strp [3:0] $end - $var wire 1 > v_arru[1] $end - $var wire 1 ? v_arru[2] $end - $var wire 1 @ v_arru_arru[3][1] $end - $var wire 1 A v_arru_arru[3][2] $end - $var wire 1 B v_arru_arru[4][1] $end - $var wire 1 C v_arru_arru[4][2] $end - $var wire 2 + v_arru_arrp[3] [2:1] $end - $var wire 2 , v_arru_arrp[4] [2:1] $end - $var wire 2 - v_arru_strp[3] [1:0] $end - $var wire 2 . v_arru_strp[4] [1:0] $end - $var real 64 / v_real $end - $var real 64 1 v_arr_real[0] $end - $var real 64 3 v_arr_real[1] $end - $var wire 64 D v_chandle [63:0] $end - $var wire 64 5 v_str32x2 [63:0] $end - $var wire 32 7 v_enumed [31:0] $end - $var wire 32 8 v_enumed2 [31:0] $end - $var wire 3 9 v_enumb [2:0] $end - $var wire 6 : v_enumb2_str [5:0] $end - $var wire 8 F unpacked_array[-2] [7:0] $end - $var wire 8 G unpacked_array[-1] [7:0] $end - $var wire 8 H unpacked_array[0] [7:0] $end - $var wire 1 I LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end + $var wire 1 : clk $end + $var wire 32 # cyc [31:0] $end + $var wire 2 $ v_strp [1:0] $end + $var wire 4 % v_strp_strp [3:0] $end + $var wire 2 & v_unip_strp [1:0] $end + $var wire 2 ' v_arrp [2:1] $end + $var wire 4 ( v_arrp_arrp [3:0] $end + $var wire 4 ) v_arrp_strp [3:0] $end + $var wire 1 ; v_arru[1] $end + $var wire 1 < v_arru[2] $end + $var wire 1 = v_arru_arru[3][1] $end + $var wire 1 > v_arru_arru[3][2] $end + $var wire 1 ? v_arru_arru[4][1] $end + $var wire 1 @ v_arru_arru[4][2] $end + $var wire 2 * v_arru_arrp[3] [2:1] $end + $var wire 2 + v_arru_arrp[4] [2:1] $end + $var wire 2 , v_arru_strp[3] [1:0] $end + $var wire 2 - v_arru_strp[4] [1:0] $end + $var real 64 . v_real $end + $var real 64 0 v_arr_real[0] $end + $var real 64 2 v_arr_real[1] $end + $var wire 64 A v_chandle [63:0] $end + $var wire 64 4 v_str32x2 [63:0] $end + $var wire 32 6 v_enumed [31:0] $end + $var wire 32 7 v_enumed2 [31:0] $end + $var wire 3 8 v_enumb [2:0] $end + $var wire 6 9 v_enumb2_str [5:0] $end + $var wire 8 C unpacked_array[-2] [7:0] $end + $var wire 8 D unpacked_array[-1] [7:0] $end + $var wire 8 E unpacked_array[0] [7:0] $end + $var wire 1 F LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end - $var wire 32 J PARAM [31:0] $end + $var wire 32 G PARAM [31:0] $end $upscope $end $scope module p2 $end - $var wire 32 K PARAM [31:0] $end + $var wire 32 H PARAM [31:0] $end $upscope $end $scope module p3 $end - $var wire 32 L PARAM [31:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 ; b [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 < a [31:0] $end - $upscope $end + $var wire 32 I PARAM [31:0] $end $upscope $end $upscope $end $upscope $end @@ -58,177 +52,173 @@ $enddefinitions $end #0 -1# -b00000000000000000000000000000000 $ -b00 % -b0000 & +1" +b00000000000000000000000000000000 # +b00 $ +b0000 % +b00 & b00 ' -b00 ( +b0000 ( b0000 ) -b0000 * +b00 * b00 + b00 , b00 - -b00 . -r0 / -r0 1 -r0 3 -b0000000000000000000000000000000000000000000000000000000011111111 5 +r0 . +r0 0 +r0 2 +b0000000000000000000000000000000000000000000000000000000011111111 4 +b00000000000000000000000000000000 6 b00000000000000000000000000000000 7 -b00000000000000000000000000000000 8 -b000 9 -b000000 : -b00000000000000000000000000000000 ; -b00000000000000000000000000000000 < +b000 8 +b000000 9 +0: +0; +0< 0= 0> 0? 0@ -0A -0B -0C -b0000000000000000000000000000000000000000000000000000000000000000 D -b00000000 F -b00000000 G -b00000000 H -0I -b00000000000000000000000000000100 J -b00000000000000000000000000000010 K -b00000000000000000000000000000011 L +b0000000000000000000000000000000000000000000000000000000000000000 A +b00000000 C +b00000000 D +b00000000 E +0F +b00000000000000000000000000000100 G +b00000000000000000000000000000010 H +b00000000000000000000000000000011 I #10 -b00000000000000000000000000000001 $ -b11 % -b1111 & +b00000000000000000000000000000001 # +b11 $ +b1111 % +b11 & b11 ' -b11 ( +b1111 ( b1111 ) -b1111 * +b11 * b11 + b11 , b11 - -b11 . -r0.1 / -r0.2 1 -r0.3 3 -b0000000000000000000000000000000100000000000000000000000011111110 5 -b00000000000000000000000000000001 7 -b00000000000000000000000000000010 8 -b111 9 -b00000000000000000000000000000101 ; -b00000000000000000000000000000101 < -1= -#15 -0= -#20 -b00000000000000000000000000000010 $ -b00 % -b0000 & -b00 ' -b00 ( -b0000 ) -b0000 * -b00 + -b00 , -b00 - -b00 . -r0.2 / -r0.4 1 -r0.6 3 -b0000000000000000000000000000001000000000000000000000000011111101 5 +r0.1 . +r0.2 0 +r0.3 2 +b0000000000000000000000000000000100000000000000000000000011111110 4 +b00000000000000000000000000000001 6 b00000000000000000000000000000010 7 -b00000000000000000000000000000100 8 -b110 9 -b111111 : -1= -#25 -0= -#30 -b00000000000000000000000000000011 $ -b11 % -b1111 & -b11 ' -b11 ( -b1111 ) -b1111 * -b11 + -b11 , -b11 - -b11 . -r0.3 / -r0.6000000000000001 1 -r0.8999999999999999 3 -b0000000000000000000000000000001100000000000000000000000011111100 5 -b00000000000000000000000000000011 7 -b00000000000000000000000000000110 8 -b101 9 -b110110 : -1= -#35 -0= -#40 -b00000000000000000000000000000100 $ -b00 % -b0000 & +b111 8 +1: +#15 +0: +#20 +b00000000000000000000000000000010 # +b00 $ +b0000 % +b00 & b00 ' -b00 ( +b0000 ( b0000 ) -b0000 * +b00 * b00 + b00 , b00 - -b00 . -r0.4 / -r0.8 1 -r1.2 3 -b0000000000000000000000000000010000000000000000000000000011111011 5 +r0.2 . +r0.4 0 +r0.6 2 +b0000000000000000000000000000001000000000000000000000000011111101 4 +b00000000000000000000000000000010 6 b00000000000000000000000000000100 7 -b00000000000000000000000000001000 8 -b100 9 -b101101 : -1= -#45 -0= -#50 -b00000000000000000000000000000101 $ -b11 % -b1111 & +b110 8 +b111111 9 +1: +#25 +0: +#30 +b00000000000000000000000000000011 # +b11 $ +b1111 % +b11 & b11 ' -b11 ( +b1111 ( b1111 ) -b1111 * +b11 * b11 + b11 , b11 - -b11 . -r0.5 / -r1 1 -r1.5 3 -b0000000000000000000000000000010100000000000000000000000011111010 5 -b00000000000000000000000000000101 7 -b00000000000000000000000000001010 8 -b011 9 -b100100 : -1= -#55 -0= -#60 -b00000000000000000000000000000110 $ -b00 % -b0000 & +r0.3 . +r0.6000000000000001 0 +r0.8999999999999999 2 +b0000000000000000000000000000001100000000000000000000000011111100 4 +b00000000000000000000000000000011 6 +b00000000000000000000000000000110 7 +b101 8 +b110110 9 +1: +#35 +0: +#40 +b00000000000000000000000000000100 # +b00 $ +b0000 % +b00 & b00 ' -b00 ( +b0000 ( b0000 ) -b0000 * +b00 * b00 + b00 , b00 - -b00 . -r0.6 / -r1.2 1 -r1.8 3 -b0000000000000000000000000000011000000000000000000000000011111001 5 -b00000000000000000000000000000110 7 -b00000000000000000000000000001100 8 -b010 9 -b011011 : -1= +r0.4 . +r0.8 0 +r1.2 2 +b0000000000000000000000000000010000000000000000000000000011111011 4 +b00000000000000000000000000000100 6 +b00000000000000000000000000001000 7 +b100 8 +b101101 9 +1: +#45 +0: +#50 +b00000000000000000000000000000101 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +r0.5 . +r1 0 +r1.5 2 +b0000000000000000000000000000010100000000000000000000000011111010 4 +b00000000000000000000000000000101 6 +b00000000000000000000000000001010 7 +b011 8 +b100100 9 +1: +#55 +0: +#60 +b00000000000000000000000000000110 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +r0.6 . +r1.2 0 +r1.8 2 +b0000000000000000000000000000011000000000000000000000000011111001 4 +b00000000000000000000000000000110 6 +b00000000000000000000000000001100 7 +b010 8 +b011011 9 +1: diff --git a/test_regress/t/t_trace_complex.py b/test_regress/t/t_trace_complex.py index 219c74d41..87beec445 100755 --- a/test_regress/t/t_trace_complex.py +++ b/test_regress/t/t_trace_complex.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index 354f83f57..578a3c5c8 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 bit global_bit; diff --git a/test_regress/t/t_trace_complex_fst.out b/test_regress/t/t_trace_complex_fst.out index 0cf966dc5..ea505919e 100644 --- a/test_regress/t/t_trace_complex_fst.out +++ b/test_regress/t/t_trace_complex_fst.out @@ -1,5 +1,5 @@ $date - Tue Jun 10 19:02:36 2025 + Tue Feb 17 01:32:41 2026 $end $version @@ -59,19 +59,11 @@ $upscope $end $scope module p3 $end $var parameter 32 C PARAM [31:0] $end $upscope $end -$scope module unnamedblk1 $end -$var integer 32 D b [31:0] $end -$scope module unnamedblk2 $end -$var integer 32 E a [31:0] $end -$upscope $end -$upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 E -b00000000000000000000000000000000 D b00000000000000000000000000000011 C b00000000000000000000000000000010 B b00000000000000000000000000000100 A @@ -128,8 +120,6 @@ b0000000000000000000000000000000100000000000000000000000011111110 8 b00000000000000000000000000000001 9 b00000000000000000000000000000010 : b111 ; -b00000000000000000000000000000101 D -b00000000000000000000000000000101 E #15 0! #20 diff --git a/test_regress/t/t_trace_complex_fst.py b/test_regress/t/t_trace_complex_fst.py index 2d1104166..567b30c42 100755 --- a/test_regress/t/t_trace_complex_fst.py +++ b/test_regress/t/t_trace_complex_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_fst_sc.out b/test_regress/t/t_trace_complex_fst_sc.out index 2b842a967..eb99fbdb9 100644 --- a/test_regress/t/t_trace_complex_fst_sc.out +++ b/test_regress/t/t_trace_complex_fst_sc.out @@ -1,5 +1,5 @@ $date - Sat Apr 5 13:56:23 2025 + Tue Feb 17 01:32:41 2026 $end $version @@ -58,19 +58,11 @@ $upscope $end $scope module p3 $end $var parameter 32 C PARAM [31:0] $end $upscope $end -$scope module unnamedblk1 $end -$var integer 32 D b [31:0] $end -$scope module unnamedblk2 $end -$var integer 32 E a [31:0] $end -$upscope $end -$upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 E -b00000000000000000000000000000000 D b00000000000000000000000000000011 C b00000000000000000000000000000010 B b00000000000000000000000000000100 A @@ -127,8 +119,6 @@ b0000000000000000000000000000000100000000000000000000000011111110 8 b00000000000000000000000000000001 9 b00000000000000000000000000000010 : b111 ; -b00000000000000000000000000000101 D -b00000000000000000000000000000101 E #15 0" #20 diff --git a/test_regress/t/t_trace_complex_fst_sc.py b/test_regress/t/t_trace_complex_fst_sc.py index 0e4fe6ff3..fbdc3d473 100755 --- a/test_regress/t/t_trace_complex_fst_sc.py +++ b/test_regress/t/t_trace_complex_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_fst_threads_1.py b/test_regress/t/t_trace_complex_fst_threads_1.py index b1a3f7e85..2c3d0187b 100755 --- a/test_regress/t/t_trace_complex_fst_threads_1.py +++ b/test_regress/t/t_trace_complex_fst_threads_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_fst_threads_1_sc.py b/test_regress/t/t_trace_complex_fst_threads_1_sc.py index 6a62c90e9..a5a8d1e23 100755 --- a/test_regress/t/t_trace_complex_fst_threads_1_sc.py +++ b/test_regress/t/t_trace_complex_fst_threads_1_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_fst_threads_2.py b/test_regress/t/t_trace_complex_fst_threads_2.py index 451fad715..b42042c4c 100755 --- a/test_regress/t/t_trace_complex_fst_threads_2.py +++ b/test_regress/t/t_trace_complex_fst_threads_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_fst_threads_2_sc.py b/test_regress/t/t_trace_complex_fst_threads_2_sc.py index 7ddc967bd..45c71b135 100755 --- a/test_regress/t/t_trace_complex_fst_threads_2_sc.py +++ b/test_regress/t/t_trace_complex_fst_threads_2_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_noinl.py b/test_regress/t/t_trace_complex_noinl.py new file mode 100755 index 000000000..bad63ffb6 --- /dev/null +++ b/test_regress/t/t_trace_complex_noinl.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.top_filename = "t/t_trace_complex.v" + +test.compile(verilator_flags2=['--cc --trace-vcd -fno-inline']) + +test.execute() + +test.file_grep(test.trace_filename, r' v_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_arrp ') +test.file_grep(test.trace_filename, r' v_arrp_strp ') +test.file_grep(test.trace_filename, r' v_arru\[') +test.file_grep(test.trace_filename, r' v_arru_arrp\[') +test.file_grep(test.trace_filename, r' v_arru_arru\[') +test.file_grep(test.trace_filename, r' v_arru_strp\[') +test.file_grep(test.trace_filename, r' v_strp ') +test.file_grep(test.trace_filename, r' v_strp_strp ') + +# Should match with module inlining +test.vcd_identical(test.trace_filename, "t/t_trace_complex.out") + +test.passes() diff --git a/test_regress/t/t_trace_complex_params.out b/test_regress/t/t_trace_complex_params.out index 82004c937..dbfe9faa0 100644 --- a/test_regress/t/t_trace_complex_params.out +++ b/test_regress/t/t_trace_complex_params.out @@ -1,56 +1,50 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end - $var wire 1 = clk $end + $var wire 1 : clk $end $scope module $unit $end - $var wire 1 # global_bit $end + $var wire 1 " global_bit $end $upscope $end $scope module t $end - $var wire 1 = clk $end - $var wire 32 $ cyc [31:0] $end - $var wire 2 % v_strp [1:0] $end - $var wire 4 & v_strp_strp [3:0] $end - $var wire 2 ' v_unip_strp [1:0] $end - $var wire 2 ( v_arrp [2:1] $end - $var wire 4 ) v_arrp_arrp [3:0] $end - $var wire 4 * v_arrp_strp [3:0] $end - $var wire 1 > v_arru[1] $end - $var wire 1 ? v_arru[2] $end - $var wire 1 @ v_arru_arru[3][1] $end - $var wire 1 A v_arru_arru[3][2] $end - $var wire 1 B v_arru_arru[4][1] $end - $var wire 1 C v_arru_arru[4][2] $end - $var wire 2 + v_arru_arrp[3] [2:1] $end - $var wire 2 , v_arru_arrp[4] [2:1] $end - $var wire 2 - v_arru_strp[3] [1:0] $end - $var wire 2 . v_arru_strp[4] [1:0] $end - $var real 64 / v_real $end - $var real 64 1 v_arr_real[0] $end - $var real 64 3 v_arr_real[1] $end - $var wire 64 D v_chandle [63:0] $end - $var wire 64 5 v_str32x2 [63:0] $end - $var wire 32 7 v_enumed [31:0] $end - $var wire 32 8 v_enumed2 [31:0] $end - $var wire 3 9 v_enumb [2:0] $end - $var wire 6 : v_enumb2_str [5:0] $end - $var wire 8 F unpacked_array[-2] [7:0] $end - $var wire 8 G unpacked_array[-1] [7:0] $end - $var wire 8 H unpacked_array[0] [7:0] $end - $var wire 1 I LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end + $var wire 1 : clk $end + $var wire 32 # cyc [31:0] $end + $var wire 2 $ v_strp [1:0] $end + $var wire 4 % v_strp_strp [3:0] $end + $var wire 2 & v_unip_strp [1:0] $end + $var wire 2 ' v_arrp [2:1] $end + $var wire 4 ( v_arrp_arrp [3:0] $end + $var wire 4 ) v_arrp_strp [3:0] $end + $var wire 1 ; v_arru[1] $end + $var wire 1 < v_arru[2] $end + $var wire 1 = v_arru_arru[3][1] $end + $var wire 1 > v_arru_arru[3][2] $end + $var wire 1 ? v_arru_arru[4][1] $end + $var wire 1 @ v_arru_arru[4][2] $end + $var wire 2 * v_arru_arrp[3] [2:1] $end + $var wire 2 + v_arru_arrp[4] [2:1] $end + $var wire 2 , v_arru_strp[3] [1:0] $end + $var wire 2 - v_arru_strp[4] [1:0] $end + $var real 64 . v_real $end + $var real 64 0 v_arr_real[0] $end + $var real 64 2 v_arr_real[1] $end + $var wire 64 A v_chandle [63:0] $end + $var wire 64 4 v_str32x2 [63:0] $end + $var wire 32 6 v_enumed [31:0] $end + $var wire 32 7 v_enumed2 [31:0] $end + $var wire 3 8 v_enumb [2:0] $end + $var wire 6 9 v_enumb2_str [5:0] $end + $var wire 8 C unpacked_array[-2] [7:0] $end + $var wire 8 D unpacked_array[-1] [7:0] $end + $var wire 8 E unpacked_array[0] [7:0] $end + $var wire 1 F LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end - $var wire 32 J PARAM [31:0] $end + $var wire 32 G PARAM [31:0] $end $upscope $end $scope module p2 $end - $var wire 32 K PARAM [31:0] $end + $var wire 32 H PARAM [31:0] $end $upscope $end $scope module p3 $end - $var wire 32 L PARAM [31:0] $end - $upscope $end - $scope module unnamedblk1 $end - $var wire 32 ; b [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 < a [31:0] $end - $upscope $end + $var wire 32 I PARAM [31:0] $end $upscope $end $upscope $end $upscope $end @@ -58,177 +52,173 @@ $enddefinitions $end #0 -1# -b00000000000000000000000000000000 $ -b00 % -b0000 & +1" +b00000000000000000000000000000000 # +b00 $ +b0000 % +b00 & b00 ' -b00 ( +b0000 ( b0000 ) -b0000 * +b00 * b00 + b00 , b00 - -b00 . -r0 / -r0 1 -r0 3 -b0000000000000000000000000000000000000000000000000000000011111111 5 +r0 . +r0 0 +r0 2 +b0000000000000000000000000000000000000000000000000000000011111111 4 +b00000000000000000000000000000000 6 b00000000000000000000000000000000 7 -b00000000000000000000000000000000 8 -b000 9 -b000000 : -b00000000000000000000000000000000 ; -b00000000000000000000000000000000 < +b000 8 +b000000 9 +0: +0; +0< 0= 0> 0? 0@ -0A -0B -0C -b0000000000000000000000000000000000000000000000000000000000000000 D -b00000000 F -b00000000 G -b00000000 H -0I -b00000000000000000000000000000100 J -b00000000000000000000000000000010 K -b00000000000000000000000000000011 L +b0000000000000000000000000000000000000000000000000000000000000000 A +b00000000 C +b00000000 D +b00000000 E +0F +b00000000000000000000000000000100 G +b00000000000000000000000000000010 H +b00000000000000000000000000000011 I #10 -b00000000000000000000000000000001 $ -b11 % -b1111 & +b00000000000000000000000000000001 # +b11 $ +b1111 % +b11 & b11 ' -b11 ( +b1111 ( b1111 ) -b1111 * +b11 * b11 + b11 , b11 - -b11 . -r0.1 / -r0.2 1 -r0.3 3 -b0000000000000000000000000000000100000000000000000000000011111110 5 -b00000000000000000000000000000001 7 -b00000000000000000000000000000010 8 -b111 9 -b00000000000000000000000000000101 ; -b00000000000000000000000000000101 < -1= -#15 -0= -#20 -b00000000000000000000000000000010 $ -b00 % -b0000 & -b00 ' -b00 ( -b0000 ) -b0000 * -b00 + -b00 , -b00 - -b00 . -r0.2 / -r0.4 1 -r0.6 3 -b0000000000000000000000000000001000000000000000000000000011111101 5 +r0.1 . +r0.2 0 +r0.3 2 +b0000000000000000000000000000000100000000000000000000000011111110 4 +b00000000000000000000000000000001 6 b00000000000000000000000000000010 7 -b00000000000000000000000000000100 8 -b110 9 -b111111 : -1= -#25 -0= -#30 -b00000000000000000000000000000011 $ -b11 % -b1111 & -b11 ' -b11 ( -b1111 ) -b1111 * -b11 + -b11 , -b11 - -b11 . -r0.3 / -r0.6000000000000001 1 -r0.8999999999999999 3 -b0000000000000000000000000000001100000000000000000000000011111100 5 -b00000000000000000000000000000011 7 -b00000000000000000000000000000110 8 -b101 9 -b110110 : -1= -#35 -0= -#40 -b00000000000000000000000000000100 $ -b00 % -b0000 & +b111 8 +1: +#15 +0: +#20 +b00000000000000000000000000000010 # +b00 $ +b0000 % +b00 & b00 ' -b00 ( +b0000 ( b0000 ) -b0000 * +b00 * b00 + b00 , b00 - -b00 . -r0.4 / -r0.8 1 -r1.2 3 -b0000000000000000000000000000010000000000000000000000000011111011 5 +r0.2 . +r0.4 0 +r0.6 2 +b0000000000000000000000000000001000000000000000000000000011111101 4 +b00000000000000000000000000000010 6 b00000000000000000000000000000100 7 -b00000000000000000000000000001000 8 -b100 9 -b101101 : -1= -#45 -0= -#50 -b00000000000000000000000000000101 $ -b11 % -b1111 & +b110 8 +b111111 9 +1: +#25 +0: +#30 +b00000000000000000000000000000011 # +b11 $ +b1111 % +b11 & b11 ' -b11 ( +b1111 ( b1111 ) -b1111 * +b11 * b11 + b11 , b11 - -b11 . -r0.5 / -r1 1 -r1.5 3 -b0000000000000000000000000000010100000000000000000000000011111010 5 -b00000000000000000000000000000101 7 -b00000000000000000000000000001010 8 -b011 9 -b100100 : -1= -#55 -0= -#60 -b00000000000000000000000000000110 $ -b00 % -b0000 & +r0.3 . +r0.6000000000000001 0 +r0.8999999999999999 2 +b0000000000000000000000000000001100000000000000000000000011111100 4 +b00000000000000000000000000000011 6 +b00000000000000000000000000000110 7 +b101 8 +b110110 9 +1: +#35 +0: +#40 +b00000000000000000000000000000100 # +b00 $ +b0000 % +b00 & b00 ' -b00 ( +b0000 ( b0000 ) -b0000 * +b00 * b00 + b00 , b00 - -b00 . -r0.6 / -r1.2 1 -r1.8 3 -b0000000000000000000000000000011000000000000000000000000011111001 5 -b00000000000000000000000000000110 7 -b00000000000000000000000000001100 8 -b010 9 -b011011 : -1= +r0.4 . +r0.8 0 +r1.2 2 +b0000000000000000000000000000010000000000000000000000000011111011 4 +b00000000000000000000000000000100 6 +b00000000000000000000000000001000 7 +b100 8 +b101101 9 +1: +#45 +0: +#50 +b00000000000000000000000000000101 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +r0.5 . +r1 0 +r1.5 2 +b0000000000000000000000000000010100000000000000000000000011111010 4 +b00000000000000000000000000000101 6 +b00000000000000000000000000001010 7 +b011 8 +b100100 9 +1: +#55 +0: +#60 +b00000000000000000000000000000110 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +r0.6 . +r1.2 0 +r1.8 2 +b0000000000000000000000000000011000000000000000000000000011111001 4 +b00000000000000000000000000000110 6 +b00000000000000000000000000001100 7 +b010 8 +b011011 9 +1: diff --git a/test_regress/t/t_trace_complex_params.py b/test_regress/t/t_trace_complex_params.py index e331a365c..ddec49bd7 100755 --- a/test_regress/t/t_trace_complex_params.py +++ b/test_regress/t/t_trace_complex_params.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_params_fst.out b/test_regress/t/t_trace_complex_params_fst.out index 73f2152c0..ea505919e 100644 --- a/test_regress/t/t_trace_complex_params_fst.out +++ b/test_regress/t/t_trace_complex_params_fst.out @@ -1,5 +1,5 @@ $date - Tue Jun 10 19:02:39 2025 + Tue Feb 17 01:32:41 2026 $end $version @@ -59,19 +59,11 @@ $upscope $end $scope module p3 $end $var parameter 32 C PARAM [31:0] $end $upscope $end -$scope module unnamedblk1 $end -$var integer 32 D b [31:0] $end -$scope module unnamedblk2 $end -$var integer 32 E a [31:0] $end -$upscope $end -$upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 E -b00000000000000000000000000000000 D b00000000000000000000000000000011 C b00000000000000000000000000000010 B b00000000000000000000000000000100 A @@ -128,8 +120,6 @@ b0000000000000000000000000000000100000000000000000000000011111110 8 b00000000000000000000000000000001 9 b00000000000000000000000000000010 : b111 ; -b00000000000000000000000000000101 D -b00000000000000000000000000000101 E #15 0! #20 diff --git a/test_regress/t/t_trace_complex_params_fst.py b/test_regress/t/t_trace_complex_params_fst.py index cd052c278..fe5593c75 100755 --- a/test_regress/t/t_trace_complex_params_fst.py +++ b/test_regress/t/t_trace_complex_params_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_params_fst_sc.out b/test_regress/t/t_trace_complex_params_fst_sc.out index 2b842a967..eb99fbdb9 100644 --- a/test_regress/t/t_trace_complex_params_fst_sc.out +++ b/test_regress/t/t_trace_complex_params_fst_sc.out @@ -1,5 +1,5 @@ $date - Sat Apr 5 13:56:23 2025 + Tue Feb 17 01:32:41 2026 $end $version @@ -58,19 +58,11 @@ $upscope $end $scope module p3 $end $var parameter 32 C PARAM [31:0] $end $upscope $end -$scope module unnamedblk1 $end -$var integer 32 D b [31:0] $end -$scope module unnamedblk2 $end -$var integer 32 E a [31:0] $end -$upscope $end -$upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 E -b00000000000000000000000000000000 D b00000000000000000000000000000011 C b00000000000000000000000000000010 B b00000000000000000000000000000100 A @@ -127,8 +119,6 @@ b0000000000000000000000000000000100000000000000000000000011111110 8 b00000000000000000000000000000001 9 b00000000000000000000000000000010 : b111 ; -b00000000000000000000000000000101 D -b00000000000000000000000000000101 E #15 0" #20 diff --git a/test_regress/t/t_trace_complex_params_fst_sc.py b/test_regress/t/t_trace_complex_params_fst_sc.py index 99007833e..5acecde14 100755 --- a/test_regress/t/t_trace_complex_params_fst_sc.py +++ b/test_regress/t/t_trace_complex_params_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_params_saif.out b/test_regress/t/t_trace_complex_params_saif.out index 5b40b6493..7d002ed88 100644 --- a/test_regress/t/t_trace_complex_params_saif.out +++ b/test_regress/t/t_trace_complex_params_saif.out @@ -609,78 +609,6 @@ (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) - (INSTANCE unnamedblk1 - (NET - (b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (b\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (b\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - (INSTANCE unnamedblk2 - (NET - (a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (a\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (a\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - ) - ) ) ) ) diff --git a/test_regress/t/t_trace_complex_params_saif.py b/test_regress/t/t_trace_complex_params_saif.py index 86db8944d..215b0e646 100755 --- a/test_regress/t/t_trace_complex_params_saif.py +++ b/test_regress/t/t_trace_complex_params_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_portable.py b/test_regress/t/t_trace_complex_portable.py index bd072f3ac..f6e5795de 100755 --- a/test_regress/t/t_trace_complex_portable.py +++ b/test_regress/t/t_trace_complex_portable.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Same test as t_trace_complex, but exercising the old VCD tracing API diff --git a/test_regress/t/t_trace_complex_saif.out b/test_regress/t/t_trace_complex_saif.out index 5b40b6493..7d002ed88 100644 --- a/test_regress/t/t_trace_complex_saif.out +++ b/test_regress/t/t_trace_complex_saif.out @@ -609,78 +609,6 @@ (PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) ) ) - (INSTANCE unnamedblk1 - (NET - (b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (b\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (b\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - (INSTANCE unnamedblk2 - (NET - (a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (a\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (a\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - ) - ) ) ) ) diff --git a/test_regress/t/t_trace_complex_saif.py b/test_regress/t/t_trace_complex_saif.py index 97b4bf308..a86cedd9d 100755 --- a/test_regress/t/t_trace_complex_saif.py +++ b/test_regress/t/t_trace_complex_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_saif_threads_1.py b/test_regress/t/t_trace_complex_saif_threads_1.py index e5be93a6b..447762c07 100755 --- a/test_regress/t/t_trace_complex_saif_threads_1.py +++ b/test_regress/t/t_trace_complex_saif_threads_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_saif_threads_2.py b/test_regress/t/t_trace_complex_saif_threads_2.py index c8665de76..2c60ab1b4 100755 --- a/test_regress/t/t_trace_complex_saif_threads_2.py +++ b/test_regress/t/t_trace_complex_saif_threads_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_structs.out b/test_regress/t/t_trace_complex_structs.out index ee2694794..344918de0 100644 --- a/test_regress/t/t_trace_complex_structs.out +++ b/test_regress/t/t_trace_complex_structs.out @@ -1,99 +1,94 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end - $var wire 1 I clk $end + $var wire 1 F clk $end $scope module $unit $end - $var wire 1 # global_bit $end + $var wire 1 " global_bit $end $upscope $end $scope module t $end - $var wire 1 I clk $end - $var wire 32 $ cyc [31:0] $end + $var wire 1 F clk $end + $var wire 32 # cyc [31:0] $end $scope module v_strp $end - $var wire 1 % b1 $end - $var wire 1 & b0 $end + $var wire 1 $ b1 $end + $var wire 1 % b0 $end $upscope $end $scope module v_strp_strp $end $scope module x1 $end - $var wire 1 ' b1 $end - $var wire 1 ( b0 $end + $var wire 1 & b1 $end + $var wire 1 ' b0 $end $upscope $end $scope module x0 $end - $var wire 1 ) b1 $end - $var wire 1 * b0 $end + $var wire 1 ( b1 $end + $var wire 1 ) b0 $end $upscope $end $upscope $end $scope module v_unip_strp $end $scope module x1 $end - $var wire 1 + b1 $end - $var wire 1 , b0 $end + $var wire 1 * b1 $end + $var wire 1 + b0 $end $upscope $end $scope module x0 $end - $var wire 1 + b1 $end - $var wire 1 , b0 $end + $var wire 1 * b1 $end + $var wire 1 + b0 $end $upscope $end $upscope $end - $var wire 2 - v_arrp [2:1] $end - $var wire 2 . v_arrp_arrp[3] [2:1] $end - $var wire 2 / v_arrp_arrp[4] [2:1] $end + $var wire 2 , v_arrp [2:1] $end + $var wire 2 - v_arrp_arrp[3] [2:1] $end + $var wire 2 . v_arrp_arrp[4] [2:1] $end $scope module v_arrp_strp[3] $end - $var wire 1 0 b1 $end - $var wire 1 1 b0 $end + $var wire 1 / b1 $end + $var wire 1 0 b0 $end $upscope $end $scope module v_arrp_strp[4] $end - $var wire 1 2 b1 $end - $var wire 1 3 b0 $end + $var wire 1 1 b1 $end + $var wire 1 2 b0 $end $upscope $end - $var wire 1 J v_arru[1] $end - $var wire 1 K v_arru[2] $end - $var wire 1 L v_arru_arru[3][1] $end - $var wire 1 M v_arru_arru[3][2] $end - $var wire 1 N v_arru_arru[4][1] $end - $var wire 1 O v_arru_arru[4][2] $end - $var wire 2 4 v_arru_arrp[3] [2:1] $end - $var wire 2 5 v_arru_arrp[4] [2:1] $end + $var wire 1 G v_arru[1] $end + $var wire 1 H v_arru[2] $end + $var wire 1 I v_arru_arru[3][1] $end + $var wire 1 J v_arru_arru[3][2] $end + $var wire 1 K v_arru_arru[4][1] $end + $var wire 1 L v_arru_arru[4][2] $end + $var wire 2 3 v_arru_arrp[3] [2:1] $end + $var wire 2 4 v_arru_arrp[4] [2:1] $end $scope module v_arru_strp[3] $end - $var wire 1 6 b1 $end - $var wire 1 7 b0 $end + $var wire 1 5 b1 $end + $var wire 1 6 b0 $end $upscope $end $scope module v_arru_strp[4] $end - $var wire 1 8 b1 $end - $var wire 1 9 b0 $end + $var wire 1 7 b1 $end + $var wire 1 8 b0 $end $upscope $end - $var real 64 : v_real $end - $var real 64 < v_arr_real[0] $end - $var real 64 > v_arr_real[1] $end - $var wire 64 P v_chandle [63:0] $end + $var real 64 9 v_real $end + $var real 64 ; v_arr_real[0] $end + $var real 64 = v_arr_real[1] $end + $var wire 64 M v_chandle [63:0] $end $scope module v_str32x2[0] $end - $var wire 32 @ data [31:0] $end + $var wire 32 ? data [31:0] $end $upscope $end $scope module v_str32x2[1] $end - $var wire 32 A data [31:0] $end + $var wire 32 @ data [31:0] $end $upscope $end - $var wire 32 B v_enumed [31:0] $end - $var wire 32 C v_enumed2 [31:0] $end - $var wire 3 D v_enumb [2:0] $end + $var wire 32 A v_enumed [31:0] $end + $var wire 32 B v_enumed2 [31:0] $end + $var wire 3 C v_enumb [2:0] $end $scope module v_enumb2_str $end - $var wire 3 E a [2:0] $end - $var wire 3 F b [2:0] $end - $upscope $end - $var wire 8 R unpacked_array[-2] [7:0] $end - $var wire 8 S unpacked_array[-1] [7:0] $end - $var wire 8 T unpacked_array[0] [7:0] $end - $var wire 1 U LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end - $scope module unnamedblk1 $end - $var wire 32 G b [31:0] $end - $scope module unnamedblk2 $end - $var wire 32 H a [31:0] $end - $upscope $end + $var wire 3 D a [2:0] $end + $var wire 3 E b [2:0] $end $upscope $end + $var wire 8 O unpacked_array[-2] [7:0] $end + $var wire 8 P unpacked_array[-1] [7:0] $end + $var wire 8 Q unpacked_array[0] [7:0] $end + $var wire 1 R LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end $upscope $end $upscope $end $enddefinitions $end #0 -1# -b00000000000000000000000000000000 $ +1" +b00000000000000000000000000000000 # +0$ 0% 0& 0' @@ -101,46 +96,44 @@ b00000000000000000000000000000000 $ 0) 0* 0+ -0, +b00 , b00 - b00 . -b00 / +0/ 00 01 02 -03 +b00 3 b00 4 -b00 5 +05 06 07 08 -09 -r0 : -r0 < -r0 > -b00000000000000000000000011111111 @ +r0 9 +r0 ; +r0 = +b00000000000000000000000011111111 ? +b00000000000000000000000000000000 @ b00000000000000000000000000000000 A b00000000000000000000000000000000 B -b00000000000000000000000000000000 C +b000 C b000 D b000 E -b000 F -b00000000000000000000000000000000 G -b00000000000000000000000000000000 H +0F +0G +0H 0I 0J 0K 0L -0M -0N -0O -b0000000000000000000000000000000000000000000000000000000000000000 P -b00000000 R -b00000000 S -b00000000 T -0U +b0000000000000000000000000000000000000000000000000000000000000000 M +b00000000 O +b00000000 P +b00000000 Q +0R #10 -b00000000000000000000000000000001 $ +b00000000000000000000000000000001 # +1$ 1% 1& 1' @@ -148,107 +141,33 @@ b00000000000000000000000000000001 $ 1) 1* 1+ -1, +b11 , b11 - b11 . -b11 / +1/ 10 11 12 -13 +b11 3 b11 4 -b11 5 +15 16 17 18 -19 -r0.1 : -r0.2 < -r0.3 > -b00000000000000000000000011111110 @ +r0.1 9 +r0.2 ; +r0.3 = +b00000000000000000000000011111110 ? +b00000000000000000000000000000001 @ b00000000000000000000000000000001 A -b00000000000000000000000000000001 B -b00000000000000000000000000000010 C -b111 D -b00000000000000000000000000000101 G -b00000000000000000000000000000101 H -1I -#15 -0I -#20 -b00000000000000000000000000000010 $ -0% -0& -0' -0( -0) -0* -0+ -0, -b00 - -b00 . -b00 / -00 -01 -02 -03 -b00 4 -b00 5 -06 -07 -08 -09 -r0.2 : -r0.4 < -r0.6 > -b00000000000000000000000011111101 @ -b00000000000000000000000000000010 A b00000000000000000000000000000010 B -b00000000000000000000000000000100 C -b110 D -b111 E -b111 F -1I -#25 -0I -#30 -b00000000000000000000000000000011 $ -1% -1& -1' -1( -1) -1* -1+ -1, -b11 - -b11 . -b11 / -10 -11 -12 -13 -b11 4 -b11 5 -16 -17 -18 -19 -r0.3 : -r0.6000000000000001 < -r0.8999999999999999 > -b00000000000000000000000011111100 @ -b00000000000000000000000000000011 A -b00000000000000000000000000000011 B -b00000000000000000000000000000110 C -b101 D -b110 E -b110 F -1I -#35 -0I -#40 -b00000000000000000000000000000100 $ +b111 C +1F +#15 +0F +#20 +b00000000000000000000000000000010 # +0$ 0% 0& 0' @@ -256,35 +175,35 @@ b00000000000000000000000000000100 $ 0) 0* 0+ -0, +b00 , b00 - b00 . -b00 / +0/ 00 01 02 -03 +b00 3 b00 4 -b00 5 +05 06 07 08 -09 -r0.4 : -r0.8 < -r1.2 > -b00000000000000000000000011111011 @ -b00000000000000000000000000000100 A +r0.2 9 +r0.4 ; +r0.6 = +b00000000000000000000000011111101 ? +b00000000000000000000000000000010 @ +b00000000000000000000000000000010 A b00000000000000000000000000000100 B -b00000000000000000000000000001000 C -b100 D -b101 E -b101 F -1I -#45 -0I -#50 -b00000000000000000000000000000101 $ +b110 C +b111 D +b111 E +1F +#25 +0F +#30 +b00000000000000000000000000000011 # +1$ 1% 1& 1' @@ -292,35 +211,35 @@ b00000000000000000000000000000101 $ 1) 1* 1+ -1, +b11 , b11 - b11 . -b11 / +1/ 10 11 12 -13 +b11 3 b11 4 -b11 5 +15 16 17 18 -19 -r0.5 : -r1 < -r1.5 > -b00000000000000000000000011111010 @ -b00000000000000000000000000000101 A -b00000000000000000000000000000101 B -b00000000000000000000000000001010 C -b011 D -b100 E -b100 F -1I -#55 -0I -#60 -b00000000000000000000000000000110 $ +r0.3 9 +r0.6000000000000001 ; +r0.8999999999999999 = +b00000000000000000000000011111100 ? +b00000000000000000000000000000011 @ +b00000000000000000000000000000011 A +b00000000000000000000000000000110 B +b101 C +b110 D +b110 E +1F +#35 +0F +#40 +b00000000000000000000000000000100 # +0$ 0% 0& 0' @@ -328,28 +247,99 @@ b00000000000000000000000000000110 $ 0) 0* 0+ -0, +b00 , b00 - b00 . -b00 / +0/ 00 01 02 -03 +b00 3 b00 4 -b00 5 +05 06 07 08 -09 -r0.6 : -r1.2 < -r1.8 > -b00000000000000000000000011111001 @ +r0.4 9 +r0.8 ; +r1.2 = +b00000000000000000000000011111011 ? +b00000000000000000000000000000100 @ +b00000000000000000000000000000100 A +b00000000000000000000000000001000 B +b100 C +b101 D +b101 E +1F +#45 +0F +#50 +b00000000000000000000000000000101 # +1$ +1% +1& +1' +1( +1) +1* +1+ +b11 , +b11 - +b11 . +1/ +10 +11 +12 +b11 3 +b11 4 +15 +16 +17 +18 +r0.5 9 +r1 ; +r1.5 = +b00000000000000000000000011111010 ? +b00000000000000000000000000000101 @ +b00000000000000000000000000000101 A +b00000000000000000000000000001010 B +b011 C +b100 D +b100 E +1F +#55 +0F +#60 +b00000000000000000000000000000110 # +0$ +0% +0& +0' +0( +0) +0* +0+ +b00 , +b00 - +b00 . +0/ +00 +01 +02 +b00 3 +b00 4 +05 +06 +07 +08 +r0.6 9 +r1.2 ; +r1.8 = +b00000000000000000000000011111001 ? +b00000000000000000000000000000110 @ b00000000000000000000000000000110 A -b00000000000000000000000000000110 B -b00000000000000000000000000001100 C -b010 D +b00000000000000000000000000001100 B +b010 C +b011 D b011 E -b011 F -1I +1F diff --git a/test_regress/t/t_trace_complex_structs.py b/test_regress/t/t_trace_complex_structs.py index cbe5ceb16..dea6069d6 100755 --- a/test_regress/t/t_trace_complex_structs.py +++ b/test_regress/t/t_trace_complex_structs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_structs_fst.out b/test_regress/t/t_trace_complex_structs_fst.out index 54d3858d3..dade36ed5 100644 --- a/test_regress/t/t_trace_complex_structs_fst.out +++ b/test_regress/t/t_trace_complex_structs_fst.out @@ -1,5 +1,5 @@ $date - Tue Jun 10 19:02:40 2025 + Tue Feb 17 01:32:41 2026 $end $version @@ -95,19 +95,11 @@ $var logic 8 J unpacked_array[-2] [7:0] $end $var logic 8 K unpacked_array[-1] [7:0] $end $var logic 8 L unpacked_array[0] [7:0] $end $var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end -$scope module unnamedblk1 $end -$var integer 32 N b [31:0] $end -$scope module unnamedblk2 $end -$var integer 32 O a [31:0] $end -$upscope $end -$upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 O -b00000000000000000000000000000000 N 0M b00000000 L b00000000 K @@ -186,8 +178,6 @@ b00000000000000000000000000000001 D b00000000000000000000000000000001 E b00000000000000000000000000000010 F b111 G -b00000000000000000000000000000101 N -b00000000000000000000000000000101 O #15 0! #20 diff --git a/test_regress/t/t_trace_complex_structs_fst.py b/test_regress/t/t_trace_complex_structs_fst.py index 879cd5e97..52bc52e69 100755 --- a/test_regress/t/t_trace_complex_structs_fst.py +++ b/test_regress/t/t_trace_complex_structs_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.out b/test_regress/t/t_trace_complex_structs_fst_sc.out index e6a359b95..ca494c178 100644 --- a/test_regress/t/t_trace_complex_structs_fst_sc.out +++ b/test_regress/t/t_trace_complex_structs_fst_sc.out @@ -1,5 +1,5 @@ $date - Sat Apr 5 13:56:24 2025 + Tue Feb 17 01:32:42 2026 $end $version @@ -94,19 +94,11 @@ $var logic 8 J unpacked_array[-2] [7:0] $end $var logic 8 K unpacked_array[-1] [7:0] $end $var logic 8 L unpacked_array[0] [7:0] $end $var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end -$scope module unnamedblk1 $end -$var integer 32 N b [31:0] $end -$scope module unnamedblk2 $end -$var integer 32 O a [31:0] $end -$upscope $end -$upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 O -b00000000000000000000000000000000 N 0M b00000000 L b00000000 K @@ -185,8 +177,6 @@ b00000000000000000000000000000001 D b00000000000000000000000000000001 E b00000000000000000000000000000010 F b111 G -b00000000000000000000000000000101 N -b00000000000000000000000000000101 O #15 0" #20 diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.py b/test_regress/t/t_trace_complex_structs_fst_sc.py index 4e88e7f62..b0c72da72 100755 --- a/test_regress/t/t_trace_complex_structs_fst_sc.py +++ b/test_regress/t/t_trace_complex_structs_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_structs_saif.out b/test_regress/t/t_trace_complex_structs_saif.out index f6c86e5c7..ca02d9506 100644 --- a/test_regress/t/t_trace_complex_structs_saif.out +++ b/test_regress/t/t_trace_complex_structs_saif.out @@ -555,78 +555,6 @@ (b\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2)) ) ) - (INSTANCE unnamedblk1 - (NET - (b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (b\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (b\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (b\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - (INSTANCE unnamedblk2 - (NET - (a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (a\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1)) - (a\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (a\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - ) - ) ) ) ) diff --git a/test_regress/t/t_trace_complex_structs_saif.py b/test_regress/t/t_trace_complex_structs_saif.py index b7a192b9c..ce4cc3b42 100755 --- a/test_regress/t/t_trace_complex_structs_saif.py +++ b/test_regress/t/t_trace_complex_structs_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_complex_threads_1.py b/test_regress/t/t_trace_complex_threads_1.py index 182da2312..54ac16149 100755 --- a/test_regress/t/t_trace_complex_threads_1.py +++ b/test_regress/t/t_trace_complex_threads_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_decoration.py b/test_regress/t/t_trace_decoration.py index 7f423d2a9..a38295252 100755 --- a/test_regress/t/t_trace_decoration.py +++ b/test_regress/t/t_trace_decoration.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_decoration.v b/test_regress/t/t_trace_decoration.v index 4407c8390..f953d4dd1 100644 --- a/test_regress/t/t_trace_decoration.v +++ b/test_regress/t/t_trace_decoration.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_trace_depth.py b/test_regress/t/t_trace_depth.py index 60bce38e2..e73c6f4a7 100755 --- a/test_regress/t/t_trace_depth.py +++ b/test_regress/t/t_trace_depth.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_depth.v b/test_regress/t/t_trace_depth.v index c1ef11851..448d6d166 100644 --- a/test_regress/t/t_trace_depth.v +++ b/test_regress/t/t_trace_depth.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_trace_dumporder_bad.py b/test_regress/t/t_trace_dumporder_bad.py index 0e9c44d04..3ae909bb1 100755 --- a/test_regress/t/t_trace_dumporder_bad.py +++ b/test_regress/t/t_trace_dumporder_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumporder_bad.v b/test_regress/t/t_trace_dumporder_bad.v index e6715ab83..2356f76e4 100644 --- a/test_regress/t/t_trace_dumporder_bad.v +++ b/test_regress/t/t_trace_dumporder_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_trace_dumpvars_dyn.cpp b/test_regress/t/t_trace_dumpvars_dyn.cpp index 650772044..20b894452 100644 --- a/test_regress/t/t_trace_dumpvars_dyn.cpp +++ b/test_regress/t/t_trace_dumpvars_dyn.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_dumpvars_dyn.v b/test_regress/t/t_trace_dumpvars_dyn.v index 4c9705348..ff0cc6ec5 100644 --- a/test_regress/t/t_trace_dumpvars_dyn.v +++ b/test_regress/t/t_trace_dumpvars_dyn.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_0.py b/test_regress/t/t_trace_dumpvars_dyn_fst_0.py index 00778c82c..50769b6de 100755 --- a/test_regress/t/t_trace_dumpvars_dyn_fst_0.py +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_dyn_fst_1.py b/test_regress/t/t_trace_dumpvars_dyn_fst_1.py index 00778c82c..50769b6de 100755 --- a/test_regress/t/t_trace_dumpvars_dyn_fst_1.py +++ b/test_regress/t/t_trace_dumpvars_dyn_fst_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_0.py b/test_regress/t/t_trace_dumpvars_dyn_saif_0.py index 5504baf26..b12d179c4 100755 --- a/test_regress/t/t_trace_dumpvars_dyn_saif_0.py +++ b/test_regress/t/t_trace_dumpvars_dyn_saif_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_1.py b/test_regress/t/t_trace_dumpvars_dyn_saif_1.py index 5504baf26..b12d179c4 100755 --- a/test_regress/t/t_trace_dumpvars_dyn_saif_1.py +++ b/test_regress/t/t_trace_dumpvars_dyn_saif_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py index 9f2efb003..2d601cf13 100755 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py index 1771ec5e6..4c5419770 100755 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_empty.py b/test_regress/t/t_trace_empty.py index d9be4bbf9..b9fd79643 100755 --- a/test_regress/t/t_trace_empty.py +++ b/test_regress/t/t_trace_empty.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_empty.v b/test_regress/t/t_trace_empty.v index 132598f8a..ba9aa442a 100644 --- a/test_regress/t/t_trace_empty.v +++ b/test_regress/t/t_trace_empty.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Geza Lore // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_trace_ena.v b/test_regress/t/t_trace_ena.v index 85b3d3f40..b58ae0541 100644 --- a/test_regress/t/t_trace_ena.v +++ b/test_regress/t/t_trace_ena.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_ena_cc.py b/test_regress/t/t_trace_ena_cc.py index 925abfaf4..feaf52dec 100755 --- a/test_regress/t/t_trace_ena_cc.py +++ b/test_regress/t/t_trace_ena_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_ena_sc.py b/test_regress/t/t_trace_ena_sc.py index 7b26b4db3..8d20ab7f2 100755 --- a/test_regress/t/t_trace_ena_sc.py +++ b/test_regress/t/t_trace_ena_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_enum.v b/test_regress/t/t_trace_enum.v index 2e4e7005a..1d46134c0 100644 --- a/test_regress/t/t_trace_enum.v +++ b/test_regress/t/t_trace_enum.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef enum logic [1:0] {VAL_A, VAL_B, VAL_C, VAL_D} state_t; diff --git a/test_regress/t/t_trace_enum_fst.out b/test_regress/t/t_trace_enum_fst.out index 094fc30ab..5d0234de7 100644 --- a/test_regress/t/t_trace_enum_fst.out +++ b/test_regress/t/t_trace_enum_fst.out @@ -1,5 +1,5 @@ $date - Sat Apr 5 13:56:28 2025 + Tue Feb 10 13:05:32 2026 $end $version @@ -12,16 +12,18 @@ $scope module top $end $attrbegin misc 07 $unit::state_t 4 VAL_A VAL_B VAL_C VAL_D 00 01 10 11 1 $end $attrbegin misc 07 t.other_state_t 3 VAL_X VAL_Y VAL_Z 00 01 10 2 $end $var wire 1 ! clk $end +$scope module $unit $end +$upscope $end $scope module t $end $var wire 1 ! clk $end +$attrbegin misc 07 "" 1 $end +$var logic 2 " v_enumed [1:0] $end +$attrbegin misc 07 "" 2 $end +$var logic 2 # v_other_enumed [1:0] $end $scope interface sink $end $attrbegin misc 07 "" 1 $end -$var logic 2 " state [1:0] $end +$var logic 2 $ state [1:0] $end $upscope $end -$attrbegin misc 07 "" 1 $end -$var logic 2 # v_enumed [1:0] $end -$attrbegin misc 07 "" 2 $end -$var logic 2 $ v_other_enumed [1:0] $end $upscope $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_enum_fst.py b/test_regress/t/t_trace_enum_fst.py index 1f9a54afa..676f117bc 100755 --- a/test_regress/t/t_trace_enum_fst.py +++ b/test_regress/t/t_trace_enum_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_enum_saif.out b/test_regress/t/t_trace_enum_saif.out index b312c271c..7bf7fbe33 100644 --- a/test_regress/t/t_trace_enum_saif.out +++ b/test_regress/t/t_trace_enum_saif.out @@ -10,6 +10,8 @@ (NET (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) ) + (INSTANCE $unit + ) (INSTANCE t (NET (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) diff --git a/test_regress/t/t_trace_enum_saif.py b/test_regress/t/t_trace_enum_saif.py index 5cd4b2956..248b39c2a 100755 --- a/test_regress/t/t_trace_enum_saif.py +++ b/test_regress/t/t_trace_enum_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_event.py b/test_regress/t/t_trace_event.py index a39922fcf..34813642c 100755 --- a/test_regress/t/t_trace_event.py +++ b/test_regress/t/t_trace_event.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_event.v b/test_regress/t/t_trace_event.v index c6f471bf7..f6b9baca2 100644 --- a/test_regress/t/t_trace_event.v +++ b/test_regress/t/t_trace_event.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_event_fst.py b/test_regress/t/t_trace_event_fst.py index a0f87c134..55ff9751c 100755 --- a/test_regress/t/t_trace_event_fst.py +++ b/test_regress/t/t_trace_event_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_flag_off.py b/test_regress/t/t_trace_flag_off.py index d0074dd4a..615925674 100755 --- a/test_regress/t/t_trace_flag_off.py +++ b/test_regress/t/t_trace_flag_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test that without --trace we get a message when turning on traces diff --git a/test_regress/t/t_trace_flag_off.v b/test_regress/t/t_trace_flag_off.v index 50319e6f6..e17fb1aae 100644 --- a/test_regress/t/t_trace_flag_off.v +++ b/test_regress/t/t_trace_flag_off.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_trace_fst.out b/test_regress/t/t_trace_fst.out index e0b8d452d..9544822be 100644 --- a/test_regress/t/t_trace_fst.out +++ b/test_regress/t/t_trace_fst.out @@ -1,5 +1,5 @@ $date - Tue Oct 21 18:20:37 2025 + Tue Feb 17 01:32:42 2026 $end $version @@ -30,53 +30,44 @@ $var byte 8 . fst_byte [7:0] $end $var time 64 / fst_time [63:0] $end $var parameter 32 0 fst_parameter [31:0] $end $var parameter 32 1 fst_lparam [31:0] $end -$var supply0 1 2 fst_supply0 $end -$var supply1 1 3 fst_supply1 $end -$var tri0 1 2 fst_tri0 $end -$var tri1 1 3 fst_tri1 $end -$var tri 1 4 fst_tri $end -$var triand 1 5 fst_triand $end -$var trior 1 6 fst_trior $end -$var triand 1 7 fst_wand $end -$var trior 1 8 fst_wor $end -$var wire 1 9 fst_wire $end -$var wire 1 : fst_uwire $end +$var supply0 1 # fst_supply0 $end +$var supply1 1 2 fst_supply1 $end +$var tri0 1 # fst_tri0 $end +$var tri1 1 2 fst_tri1 $end +$var tri 1 3 fst_tri $end +$var triand 1 4 fst_triand $end +$var trior 1 5 fst_trior $end +$var triand 1 6 fst_wand $end +$var trior 1 7 fst_wor $end +$var wire 1 8 fst_wire $end +$var wire 1 9 fst_uwire $end $var wire 1 # fst_inout $end $scope module test $end $var wire 1 ! clk $end $var wire 1 % rstn $end $var wire 5 " state [4:0] $end -$var logic 5 ; state_w [4:0] $end -$var logic 5 < state_array[0] [4:0] $end -$var logic 5 = state_array[1] [4:0] $end -$var logic 5 > state_array[2] [4:0] $end -$scope module unnamedblk1 $end -$var int 32 ? i [31:0] $end -$upscope $end -$scope module unnamedblk2 $end -$var int 32 @ i [31:0] $end -$upscope $end +$var logic 5 : state_w [4:0] $end +$var logic 5 ; state_array[0] [4:0] $end +$var logic 5 < state_array[1] [4:0] $end +$var logic 5 = state_array[2] [4:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 @ -b00000000000000000000000000000000 ? -b00000 > b00000 = b00000 < b00000 ; -0: +b00000 : 09 08 07 06 05 04 -13 -02 +03 +12 b00000000000000000000000111001000 1 b00000000000000000000000001111011 0 b0000000000000000000000000000000000000000000000000000000000000000 / @@ -100,11 +91,10 @@ $end b00001 " b00000000000000000000000000000001 $ b0000000000000000000000000000000000000000000000000000000000001010 / -b10100 ; +b10100 : +b00001 ; b00001 < b00001 = -b00001 > -b00000000000000000000000000000011 ? #15 0! #20 @@ -172,972 +162,971 @@ b0000000000000000000000000000000000000000000000000000000001101110 / 1! b0000000000000000000000000000000000000000000000000000000001111000 / b00000000000000000000000000001100 $ -b10100 > -b01010 ; -b00000000000000000000000000000010 @ +b10100 = +b01010 : #125 0! #130 1! -b00101 ; -b01010 > +b00101 : +b01010 = b00000000000000000000000000001101 $ b0000000000000000000000000000000000000000000000000000000010000010 / -b10100 = +b10100 < #135 0! #140 1! -b01010 = +b01010 < b0000000000000000000000000000000000000000000000000000000010001100 / b00000000000000000000000000001110 $ -b00101 > -b10110 ; -b10100 < +b00101 = +b10110 : +b10100 ; b10100 " #145 0! #150 1! b01010 " -b01010 < -b01011 ; -b10110 > +b01010 ; +b01011 : +b10110 = b00000000000000000000000000001111 $ b0000000000000000000000000000000000000000000000000000000010010110 / -b00101 = +b00101 < #155 0! #160 1! -b10110 = +b10110 < b0000000000000000000000000000000000000000000000000000000010100000 / b00000000000000000000000000010000 $ -b01011 > -b10001 ; -b00101 < +b01011 = +b10001 : +b00101 ; b00101 " #165 0! #170 1! b10110 " -b10110 < -b11100 ; -b10001 > +b10110 ; +b11100 : +b10001 = b00000000000000000000000000010001 $ b0000000000000000000000000000000000000000000000000000000010101010 / -b01011 = +b01011 < #175 0! #180 1! -b10001 = +b10001 < b0000000000000000000000000000000000000000000000000000000010110100 / b00000000000000000000000000010010 $ -b11100 > -b01110 ; -b01011 < +b11100 = +b01110 : +b01011 ; b01011 " #185 0! #190 1! b10001 " -b10001 < -b00111 ; -b01110 > +b10001 ; +b00111 : +b01110 = b00000000000000000000000000010011 $ b0000000000000000000000000000000000000000000000000000000010111110 / -b11100 = +b11100 < #195 0! #200 1! -b01110 = +b01110 < b0000000000000000000000000000000000000000000000000000000011001000 / b00000000000000000000000000010100 $ -b00111 > -b10111 ; -b11100 < +b00111 = +b10111 : +b11100 ; b11100 " #205 0! #210 1! b01110 " -b01110 < -b11111 ; -b10111 > +b01110 ; +b11111 : +b10111 = b00000000000000000000000000010101 $ b0000000000000000000000000000000000000000000000000000000011010010 / -b00111 = +b00111 < #215 0! #220 1! -b10111 = +b10111 < b0000000000000000000000000000000000000000000000000000000011011100 / b00000000000000000000000000010110 $ -b11111 > -b11011 ; -b00111 < +b11111 = +b11011 : +b00111 ; b00111 " #225 0! #230 1! b10111 " -b10111 < -b11001 ; -b11011 > +b10111 ; +b11001 : +b11011 = b00000000000000000000000000010111 $ b0000000000000000000000000000000000000000000000000000000011100110 / -b11111 = +b11111 < #235 0! #240 1! -b11011 = +b11011 < b0000000000000000000000000000000000000000000000000000000011110000 / b00000000000000000000000000011000 $ -b11001 > -b11000 ; -b11111 < +b11001 = +b11000 : +b11111 ; b11111 " #245 0! #250 1! b11011 " -b11011 < -b01100 ; -b11000 > +b11011 ; +b01100 : +b11000 = b00000000000000000000000000011001 $ b0000000000000000000000000000000000000000000000000000000011111010 / -b11001 = +b11001 < #255 0! #260 1! -b11000 = +b11000 < b0000000000000000000000000000000000000000000000000000000100000100 / b00000000000000000000000000011010 $ -b01100 > -b00110 ; -b11001 < +b01100 = +b00110 : +b11001 ; b11001 " #265 0! #270 1! b11000 " -b11000 < -b00011 ; -b00110 > +b11000 ; +b00011 : +b00110 = b00000000000000000000000000011011 $ b0000000000000000000000000000000000000000000000000000000100001110 / -b01100 = +b01100 < #275 0! #280 1! -b00110 = +b00110 < b0000000000000000000000000000000000000000000000000000000100011000 / b00000000000000000000000000011100 $ -b00011 > -b10101 ; -b01100 < +b00011 = +b10101 : +b01100 ; b01100 " #285 0! #290 1! b00110 " -b00110 < -b11110 ; -b10101 > +b00110 ; +b11110 : +b10101 = b00000000000000000000000000011101 $ b0000000000000000000000000000000000000000000000000000000100100010 / -b00011 = +b00011 < #295 0! #300 1! -b10101 = +b10101 < b0000000000000000000000000000000000000000000000000000000100101100 / b00000000000000000000000000011110 $ -b11110 > -b01111 ; -b00011 < +b11110 = +b01111 : +b00011 ; b00011 " #305 0! #310 1! b10101 " -b10101 < -b10011 ; -b01111 > +b10101 ; +b10011 : +b01111 = b00000000000000000000000000011111 $ b0000000000000000000000000000000000000000000000000000000100110110 / -b11110 = +b11110 < #315 0! #320 1! -b01111 = +b01111 < b0000000000000000000000000000000000000000000000000000000101000000 / b00000000000000000000000000100000 $ -b10011 > -b11101 ; -b11110 < +b10011 = +b11101 : +b11110 ; b11110 " #325 0! #330 1! b01111 " -b01111 < -b11010 ; -b11101 > +b01111 ; +b11010 : +b11101 = b00000000000000000000000000100001 $ b0000000000000000000000000000000000000000000000000000000101001010 / -b10011 = +b10011 < #335 0! #340 1! -b11101 = +b11101 < b0000000000000000000000000000000000000000000000000000000101010100 / b00000000000000000000000000100010 $ -b11010 > -b01101 ; -b10011 < +b11010 = +b01101 : +b10011 ; b10011 " #345 0! #350 1! b11101 " -b11101 < -b10010 ; -b01101 > +b11101 ; +b10010 : +b01101 = b00000000000000000000000000100011 $ b0000000000000000000000000000000000000000000000000000000101011110 / -b11010 = +b11010 < #355 0! #360 1! -b01101 = +b01101 < b0000000000000000000000000000000000000000000000000000000101101000 / b00000000000000000000000000100100 $ -b10010 > -b01001 ; -b11010 < +b10010 = +b01001 : +b11010 ; b11010 " #365 0! #370 1! b01101 " -b01101 < -b10000 ; -b01001 > +b01101 ; +b10000 : +b01001 = b00000000000000000000000000100101 $ b0000000000000000000000000000000000000000000000000000000101110010 / -b10010 = +b10010 < #375 0! #380 1! -b01001 = +b01001 < b0000000000000000000000000000000000000000000000000000000101111100 / b00000000000000000000000000100110 $ -b10000 > -b01000 ; -b10010 < +b10000 = +b01000 : +b10010 ; b10010 " #385 0! #390 1! b01001 " -b01001 < -b00100 ; -b01000 > +b01001 ; +b00100 : +b01000 = b00000000000000000000000000100111 $ b0000000000000000000000000000000000000000000000000000000110000110 / -b10000 = +b10000 < #395 0! #400 1! -b01000 = +b01000 < b0000000000000000000000000000000000000000000000000000000110010000 / b00000000000000000000000000101000 $ -b00100 > -b00010 ; -b10000 < +b00100 = +b00010 : +b10000 ; b10000 " #405 0! #410 1! b01000 " -b01000 < -b00001 ; -b00010 > +b01000 ; +b00001 : +b00010 = b00000000000000000000000000101001 $ b0000000000000000000000000000000000000000000000000000000110011010 / -b00100 = +b00100 < #415 0! #420 1! -b00010 = +b00010 < b0000000000000000000000000000000000000000000000000000000110100100 / b00000000000000000000000000101010 $ -b00001 > -b10100 ; -b00100 < +b00001 = +b10100 : +b00100 ; b00100 " #425 0! #430 1! b00010 " -b00010 < -b01010 ; -b10100 > +b00010 ; +b01010 : +b10100 = b00000000000000000000000000101011 $ b0000000000000000000000000000000000000000000000000000000110101110 / -b00001 = +b00001 < #435 0! #440 1! -b10100 = +b10100 < b0000000000000000000000000000000000000000000000000000000110111000 / b00000000000000000000000000101100 $ -b01010 > -b00101 ; -b00001 < +b01010 = +b00101 : +b00001 ; b00001 " #445 0! #450 1! b10100 " -b10100 < -b10110 ; -b00101 > +b10100 ; +b10110 : +b00101 = b00000000000000000000000000101101 $ b0000000000000000000000000000000000000000000000000000000111000010 / -b01010 = +b01010 < #455 0! #460 1! -b00101 = +b00101 < b0000000000000000000000000000000000000000000000000000000111001100 / b00000000000000000000000000101110 $ -b10110 > -b01011 ; -b01010 < +b10110 = +b01011 : +b01010 ; b01010 " #465 0! #470 1! b00101 " -b00101 < -b10001 ; -b01011 > +b00101 ; +b10001 : +b01011 = b00000000000000000000000000101111 $ b0000000000000000000000000000000000000000000000000000000111010110 / -b10110 = +b10110 < #475 0! #480 1! -b01011 = +b01011 < b0000000000000000000000000000000000000000000000000000000111100000 / b00000000000000000000000000110000 $ -b10001 > -b11100 ; -b10110 < +b10001 = +b11100 : +b10110 ; b10110 " #485 0! #490 1! b01011 " -b01011 < -b01110 ; -b11100 > +b01011 ; +b01110 : +b11100 = b00000000000000000000000000110001 $ b0000000000000000000000000000000000000000000000000000000111101010 / -b10001 = +b10001 < #495 0! #500 1! -b11100 = +b11100 < b0000000000000000000000000000000000000000000000000000000111110100 / b00000000000000000000000000110010 $ -b01110 > -b00111 ; -b10001 < +b01110 = +b00111 : +b10001 ; b10001 " #505 0! #510 1! b11100 " -b11100 < -b10111 ; -b00111 > +b11100 ; +b10111 : +b00111 = b00000000000000000000000000110011 $ b0000000000000000000000000000000000000000000000000000000111111110 / -b01110 = +b01110 < #515 0! #520 1! -b00111 = +b00111 < b0000000000000000000000000000000000000000000000000000001000001000 / b00000000000000000000000000110100 $ -b10111 > -b11111 ; -b01110 < +b10111 = +b11111 : +b01110 ; b01110 " #525 0! #530 1! b00111 " -b00111 < -b11011 ; -b11111 > +b00111 ; +b11011 : +b11111 = b00000000000000000000000000110101 $ b0000000000000000000000000000000000000000000000000000001000010010 / -b10111 = +b10111 < #535 0! #540 1! -b11111 = +b11111 < b0000000000000000000000000000000000000000000000000000001000011100 / b00000000000000000000000000110110 $ -b11011 > -b11001 ; -b10111 < +b11011 = +b11001 : +b10111 ; b10111 " #545 0! #550 1! b11111 " -b11111 < -b11000 ; -b11001 > +b11111 ; +b11000 : +b11001 = b00000000000000000000000000110111 $ b0000000000000000000000000000000000000000000000000000001000100110 / -b11011 = +b11011 < #555 0! #560 1! -b11001 = +b11001 < b0000000000000000000000000000000000000000000000000000001000110000 / b00000000000000000000000000111000 $ -b11000 > -b01100 ; -b11011 < +b11000 = +b01100 : +b11011 ; b11011 " #565 0! #570 1! b11001 " -b11001 < -b00110 ; -b01100 > +b11001 ; +b00110 : +b01100 = b00000000000000000000000000111001 $ b0000000000000000000000000000000000000000000000000000001000111010 / -b11000 = +b11000 < #575 0! #580 1! -b01100 = +b01100 < b0000000000000000000000000000000000000000000000000000001001000100 / b00000000000000000000000000111010 $ -b00110 > -b00011 ; -b11000 < +b00110 = +b00011 : +b11000 ; b11000 " #585 0! #590 1! b01100 " -b01100 < -b10101 ; -b00011 > +b01100 ; +b10101 : +b00011 = b00000000000000000000000000111011 $ b0000000000000000000000000000000000000000000000000000001001001110 / -b00110 = +b00110 < #595 0! #600 1! -b00011 = +b00011 < b0000000000000000000000000000000000000000000000000000001001011000 / b00000000000000000000000000111100 $ -b10101 > -b11110 ; -b00110 < +b10101 = +b11110 : +b00110 ; b00110 " #605 0! #610 1! b00011 " -b00011 < -b01111 ; -b11110 > +b00011 ; +b01111 : +b11110 = b00000000000000000000000000111101 $ b0000000000000000000000000000000000000000000000000000001001100010 / -b10101 = +b10101 < #615 0! #620 1! -b11110 = +b11110 < b0000000000000000000000000000000000000000000000000000001001101100 / b00000000000000000000000000111110 $ -b01111 > -b10011 ; -b10101 < +b01111 = +b10011 : +b10101 ; b10101 " #625 0! #630 1! b11110 " -b11110 < -b11101 ; -b10011 > +b11110 ; +b11101 : +b10011 = b00000000000000000000000000111111 $ b0000000000000000000000000000000000000000000000000000001001110110 / -b01111 = +b01111 < #635 0! #640 1! -b10011 = +b10011 < b0000000000000000000000000000000000000000000000000000001010000000 / b00000000000000000000000001000000 $ -b11101 > -b11010 ; -b01111 < +b11101 = +b11010 : +b01111 ; b01111 " #645 0! #650 1! b10011 " -b10011 < -b01101 ; -b11010 > +b10011 ; +b01101 : +b11010 = b00000000000000000000000001000001 $ b0000000000000000000000000000000000000000000000000000001010001010 / -b11101 = +b11101 < #655 0! #660 1! -b11010 = +b11010 < b0000000000000000000000000000000000000000000000000000001010010100 / b00000000000000000000000001000010 $ -b01101 > -b10010 ; -b11101 < +b01101 = +b10010 : +b11101 ; b11101 " #665 0! #670 1! b11010 " -b11010 < -b01001 ; -b10010 > +b11010 ; +b01001 : +b10010 = b00000000000000000000000001000011 $ b0000000000000000000000000000000000000000000000000000001010011110 / -b01101 = +b01101 < #675 0! #680 1! -b10010 = +b10010 < b0000000000000000000000000000000000000000000000000000001010101000 / b00000000000000000000000001000100 $ -b01001 > -b10000 ; -b01101 < +b01001 = +b10000 : +b01101 ; b01101 " #685 0! #690 1! b10010 " -b10010 < -b01000 ; -b10000 > +b10010 ; +b01000 : +b10000 = b00000000000000000000000001000101 $ b0000000000000000000000000000000000000000000000000000001010110010 / -b01001 = +b01001 < #695 0! #700 1! -b10000 = +b10000 < b0000000000000000000000000000000000000000000000000000001010111100 / b00000000000000000000000001000110 $ -b01000 > -b00100 ; -b01001 < +b01000 = +b00100 : +b01001 ; b01001 " #705 0! #710 1! b10000 " -b10000 < -b00010 ; -b00100 > +b10000 ; +b00010 : +b00100 = b00000000000000000000000001000111 $ b0000000000000000000000000000000000000000000000000000001011000110 / -b01000 = +b01000 < #715 0! #720 1! -b00100 = +b00100 < b0000000000000000000000000000000000000000000000000000001011010000 / b00000000000000000000000001001000 $ -b00010 > -b00001 ; -b01000 < +b00010 = +b00001 : +b01000 ; b01000 " #725 0! #730 1! b00100 " -b00100 < -b10100 ; -b00001 > +b00100 ; +b10100 : +b00001 = b00000000000000000000000001001001 $ b0000000000000000000000000000000000000000000000000000001011011010 / -b00010 = +b00010 < #735 0! #740 1! -b00001 = +b00001 < b0000000000000000000000000000000000000000000000000000001011100100 / b00000000000000000000000001001010 $ -b10100 > -b01010 ; -b00010 < +b10100 = +b01010 : +b00010 ; b00010 " #745 0! #750 1! b00001 " -b00001 < -b00101 ; -b01010 > +b00001 ; +b00101 : +b01010 = b00000000000000000000000001001011 $ b0000000000000000000000000000000000000000000000000000001011101110 / -b10100 = +b10100 < #755 0! #760 1! -b01010 = +b01010 < b0000000000000000000000000000000000000000000000000000001011111000 / b00000000000000000000000001001100 $ -b00101 > -b10110 ; -b10100 < +b00101 = +b10110 : +b10100 ; b10100 " #765 0! #770 1! b01010 " -b01010 < -b01011 ; -b10110 > +b01010 ; +b01011 : +b10110 = b00000000000000000000000001001101 $ b0000000000000000000000000000000000000000000000000000001100000010 / -b00101 = +b00101 < #775 0! #780 1! -b10110 = +b10110 < b0000000000000000000000000000000000000000000000000000001100001100 / b00000000000000000000000001001110 $ -b01011 > -b10001 ; -b00101 < +b01011 = +b10001 : +b00101 ; b00101 " #785 0! #790 1! b10110 " -b10110 < -b11100 ; -b10001 > +b10110 ; +b11100 : +b10001 = b00000000000000000000000001001111 $ b0000000000000000000000000000000000000000000000000000001100010110 / -b01011 = +b01011 < #795 0! #800 1! -b10001 = +b10001 < b0000000000000000000000000000000000000000000000000000001100100000 / b00000000000000000000000001010000 $ -b11100 > -b01110 ; -b01011 < +b11100 = +b01110 : +b01011 ; b01011 " #805 0! #810 1! b10001 " -b10001 < -b00111 ; -b01110 > +b10001 ; +b00111 : +b01110 = b00000000000000000000000001010001 $ b0000000000000000000000000000000000000000000000000000001100101010 / -b11100 = +b11100 < #815 0! #820 1! -b01110 = +b01110 < b0000000000000000000000000000000000000000000000000000001100110100 / b00000000000000000000000001010010 $ -b00111 > -b10111 ; -b11100 < +b00111 = +b10111 : +b11100 ; b11100 " #825 0! #830 1! b01110 " -b01110 < -b11111 ; -b10111 > +b01110 ; +b11111 : +b10111 = b00000000000000000000000001010011 $ b0000000000000000000000000000000000000000000000000000001100111110 / -b00111 = +b00111 < #835 0! #840 1! -b10111 = +b10111 < b0000000000000000000000000000000000000000000000000000001101001000 / b00000000000000000000000001010100 $ -b11111 > -b11011 ; -b00111 < +b11111 = +b11011 : +b00111 ; b00111 " #845 0! #850 1! b10111 " -b10111 < -b11001 ; -b11011 > +b10111 ; +b11001 : +b11011 = b00000000000000000000000001010101 $ b0000000000000000000000000000000000000000000000000000001101010010 / -b11111 = +b11111 < #855 0! #860 1! -b11011 = +b11011 < b0000000000000000000000000000000000000000000000000000001101011100 / b00000000000000000000000001010110 $ -b11001 > -b11000 ; -b11111 < +b11001 = +b11000 : +b11111 ; b11111 " #865 0! #870 1! b11011 " -b11011 < -b01100 ; -b11000 > +b11011 ; +b01100 : +b11000 = b00000000000000000000000001010111 $ b0000000000000000000000000000000000000000000000000000001101100110 / -b11001 = +b11001 < #875 0! #880 1! -b11000 = +b11000 < b0000000000000000000000000000000000000000000000000000001101110000 / b00000000000000000000000001011000 $ -b01100 > -b00110 ; -b11001 < +b01100 = +b00110 : +b11001 ; b11001 " #885 0! #890 1! b11000 " -b11000 < -b00011 ; -b00110 > +b11000 ; +b00011 : +b00110 = b00000000000000000000000001011001 $ b0000000000000000000000000000000000000000000000000000001101111010 / -b01100 = +b01100 < #895 0! #900 1! -b00110 = +b00110 < b0000000000000000000000000000000000000000000000000000001110000100 / b00000000000000000000000001011010 $ -b00011 > -b10101 ; -b01100 < +b00011 = +b10101 : +b01100 ; b01100 " #905 0! #910 1! b00110 " -b00110 < -b11110 ; -b10101 > +b00110 ; +b11110 : +b10101 = b00000000000000000000000001011011 $ b0000000000000000000000000000000000000000000000000000001110001110 / -b00011 = +b00011 < #915 0! #920 1! -b10101 = +b10101 < b0000000000000000000000000000000000000000000000000000001110011000 / b00000000000000000000000001011100 $ -b11110 > -b01111 ; -b00011 < +b11110 = +b01111 : +b00011 ; b00011 " #925 0! #930 1! b10101 " -b10101 < -b10011 ; -b01111 > +b10101 ; +b10011 : +b01111 = b00000000000000000000000001011101 $ b0000000000000000000000000000000000000000000000000000001110100010 / -b11110 = +b11110 < #935 0! #940 1! -b01111 = +b01111 < b0000000000000000000000000000000000000000000000000000001110101100 / b00000000000000000000000001011110 $ -b10011 > -b11101 ; -b11110 < +b10011 = +b11101 : +b11110 ; b11110 " #945 0! #950 1! b01111 " -b01111 < -b11010 ; -b11101 > +b01111 ; +b11010 : +b11101 = b00000000000000000000000001011111 $ b0000000000000000000000000000000000000000000000000000001110110110 / -b10011 = +b10011 < #955 0! #960 1! -b11101 = +b11101 < b0000000000000000000000000000000000000000000000000000001111000000 / b00000000000000000000000001100000 $ -b11010 > -b01101 ; -b10011 < +b11010 = +b01101 : +b10011 ; b10011 " #965 0! #970 1! b11101 " -b11101 < -b10010 ; -b01101 > +b11101 ; +b10010 : +b01101 = b00000000000000000000000001100001 $ b0000000000000000000000000000000000000000000000000000001111001010 / -b11010 = +b11010 < #975 0! #980 1! -b01101 = +b01101 < b0000000000000000000000000000000000000000000000000000001111010100 / b00000000000000000000000001100010 $ -b10010 > -b01001 ; -b11010 < +b10010 = +b01001 : +b11010 ; b11010 " #985 0! #990 1! b01101 " -b01101 < -b10000 ; -b01001 > +b01101 ; +b10000 : +b01001 = b00000000000000000000000001100011 $ b0000000000000000000000000000000000000000000000000000001111011110 / -b10010 = +b10010 < #995 0! #1000 1! -b01001 = +b01001 < b0000000000000000000000000000000000000000000000000000001111101000 / b00000000000000000000000001100100 $ -b10000 > -b01000 ; -b10010 < +b10000 = +b01000 : +b10010 ; b10010 " diff --git a/test_regress/t/t_trace_fst.py b/test_regress/t/t_trace_fst.py index c1d629013..391b761ee 100755 --- a/test_regress/t/t_trace_fst.py +++ b/test_regress/t/t_trace_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_fst.v b/test_regress/t/t_trace_fst.v index 2e4f24dd4..3d3a7c322 100644 --- a/test_regress/t/t_trace_fst.v +++ b/test_regress/t/t_trace_fst.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_fst_cmake.out b/test_regress/t/t_trace_fst_cmake.out index 9cc0fb813..3e52b4c60 100644 --- a/test_regress/t/t_trace_fst_cmake.out +++ b/test_regress/t/t_trace_fst_cmake.out @@ -1,5 +1,5 @@ $date - Sat Apr 5 13:56:26 2025 + Tue Feb 17 01:32:42 2026 $end $version @@ -42,20 +42,12 @@ $var logic 5 4 state_w [4:0] $end $var logic 5 5 state_array[0] [4:0] $end $var logic 5 6 state_array[1] [4:0] $end $var logic 5 7 state_array[2] [4:0] $end -$scope module unnamedblk1 $end -$var int 32 8 i [31:0] $end -$upscope $end -$scope module unnamedblk2 $end -$var int 32 9 i [31:0] $end -$upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 9 -b00000000000000000000000000000000 8 b00000 7 b00000 6 b00000 5 @@ -88,7 +80,6 @@ b10100 4 b00001 5 b00001 6 b00001 7 -b00000000000000000000000000000011 8 #15 0! #20 @@ -147,7 +138,6 @@ b00000000000000000000000000001011 # b00000000000000000000000000001100 # b10100 7 b01010 4 -b00000000000000000000000000000010 9 #125 0! #130 diff --git a/test_regress/t/t_trace_fst_cmake.py b/test_regress/t/t_trace_fst_cmake.py index bb960e236..abec2a742 100755 --- a/test_regress/t/t_trace_fst_cmake.py +++ b/test_regress/t/t_trace_fst_cmake.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_fst_cmake.v b/test_regress/t/t_trace_fst_cmake.v index 288ddadfc..fa3159e84 100644 --- a/test_regress/t/t_trace_fst_cmake.v +++ b/test_regress/t/t_trace_fst_cmake.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_fst_sc.out b/test_regress/t/t_trace_fst_sc.out index ef0d227f1..b911ff93a 100644 --- a/test_regress/t/t_trace_fst_sc.out +++ b/test_regress/t/t_trace_fst_sc.out @@ -1,5 +1,5 @@ $date - Sat Apr 5 13:52:51 2025 + Tue Feb 17 01:32:42 2026 $end $version @@ -40,20 +40,12 @@ $var logic 5 4 state_w [4:0] $end $var logic 5 5 state_array[0] [4:0] $end $var logic 5 6 state_array[1] [4:0] $end $var logic 5 7 state_array[2] [4:0] $end -$scope module unnamedblk1 $end -$var int 32 8 i [31:0] $end -$upscope $end -$scope module unnamedblk2 $end -$var int 32 9 i [31:0] $end -$upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 9 -b00000000000000000000000000000000 8 b00000 7 b00000 6 b00000 5 @@ -86,7 +78,6 @@ b10100 4 b00001 5 b00001 6 b00001 7 -b00000000000000000000000000000011 8 #15 0! #20 @@ -145,7 +136,6 @@ b00000000000000000000000000001011 " b00000000000000000000000000001100 " b10100 7 b01010 4 -b00000000000000000000000000000010 9 #125 0! #130 diff --git a/test_regress/t/t_trace_fst_sc.py b/test_regress/t/t_trace_fst_sc.py index 70d59dba1..f142e7f0f 100755 --- a/test_regress/t/t_trace_fst_sc.py +++ b/test_regress/t/t_trace_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_fst_sc.v b/test_regress/t/t_trace_fst_sc.v index 52c148bd5..7b0bfb40c 100644 --- a/test_regress/t/t_trace_fst_sc.v +++ b/test_regress/t/t_trace_fst_sc.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_fst_sc_cmake.out b/test_regress/t/t_trace_fst_sc_cmake.out index 861031103..b911ff93a 100644 --- a/test_regress/t/t_trace_fst_sc_cmake.out +++ b/test_regress/t/t_trace_fst_sc_cmake.out @@ -1,5 +1,5 @@ $date - Sat Apr 5 13:56:27 2025 + Tue Feb 17 01:32:42 2026 $end $version @@ -40,20 +40,12 @@ $var logic 5 4 state_w [4:0] $end $var logic 5 5 state_array[0] [4:0] $end $var logic 5 6 state_array[1] [4:0] $end $var logic 5 7 state_array[2] [4:0] $end -$scope module unnamedblk1 $end -$var int 32 8 i [31:0] $end -$upscope $end -$scope module unnamedblk2 $end -$var int 32 9 i [31:0] $end -$upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000000000000000 9 -b00000000000000000000000000000000 8 b00000 7 b00000 6 b00000 5 @@ -86,7 +78,6 @@ b10100 4 b00001 5 b00001 6 b00001 7 -b00000000000000000000000000000011 8 #15 0! #20 @@ -145,7 +136,6 @@ b00000000000000000000000000001011 " b00000000000000000000000000001100 " b10100 7 b01010 4 -b00000000000000000000000000000010 9 #125 0! #130 diff --git a/test_regress/t/t_trace_fst_sc_cmake.py b/test_regress/t/t_trace_fst_sc_cmake.py index 29dd1e13f..5473e886d 100755 --- a/test_regress/t/t_trace_fst_sc_cmake.py +++ b/test_regress/t/t_trace_fst_sc_cmake.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_fst_sc_cmake.v b/test_regress/t/t_trace_fst_sc_cmake.v index 52c148bd5..7b0bfb40c 100644 --- a/test_regress/t/t_trace_fst_sc_cmake.v +++ b/test_regress/t/t_trace_fst_sc_cmake.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_iface.py b/test_regress/t/t_trace_iface.py index 0f4312521..91f67a0fe 100755 --- a/test_regress/t/t_trace_iface.py +++ b/test_regress/t/t_trace_iface.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_iface.v b/test_regress/t/t_trace_iface.v index eeb87f509..f04cd7624 100644 --- a/test_regress/t/t_trace_iface.v +++ b/test_regress/t/t_trace_iface.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface counter_if; diff --git a/test_regress/t/t_trace_jumps_do_while_saif.py b/test_regress/t/t_trace_jumps_do_while_saif.py index 5b8126639..6b9bc7b97 100755 --- a/test_regress/t/t_trace_jumps_do_while_saif.py +++ b/test_regress/t/t_trace_jumps_do_while_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_max.py b/test_regress/t/t_trace_max.py index 1ce918283..8a25e10cb 100755 --- a/test_regress/t/t_trace_max.py +++ b/test_regress/t/t_trace_max.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_max.v b/test_regress/t/t_trace_max.v index 2f8509ede..d5002c41d 100644 --- a/test_regress/t/t_trace_max.v +++ b/test_regress/t/t_trace_max.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_trace_max_default.py b/test_regress/t/t_trace_max_default.py index 2be59a866..6255dd131 100755 --- a/test_regress/t/t_trace_max_default.py +++ b/test_regress/t/t_trace_max_default.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_multi_bad.py b/test_regress/t/t_trace_multi_bad.py index cbb233614..760ed777e 100755 --- a/test_regress/t/t_trace_multi_bad.py +++ b/test_regress/t/t_trace_multi_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_multi_bad.v b/test_regress/t/t_trace_multi_bad.v index fbcbd7ce9..3fbbf0710 100644 --- a/test_regress/t/t_trace_multi_bad.v +++ b/test_regress/t/t_trace_multi_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_trace_no_top_name.py b/test_regress/t/t_trace_no_top_name.py index ebe166cbc..829683b15 100755 --- a/test_regress/t/t_trace_no_top_name.py +++ b/test_regress/t/t_trace_no_top_name.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_no_top_name.v b/test_regress/t/t_trace_no_top_name.v index d6c0c1213..2e314b20f 100644 --- a/test_regress/t/t_trace_no_top_name.v +++ b/test_regress/t/t_trace_no_top_name.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_no_top_name2.cpp b/test_regress/t/t_trace_no_top_name2.cpp index 7f626578b..cf2756a91 100644 --- a/test_regress/t/t_trace_no_top_name2.cpp +++ b/test_regress/t/t_trace_no_top_name2.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_no_top_name2.v b/test_regress/t/t_trace_no_top_name2.v index 4d02a9029..4b8e61c75 100644 --- a/test_regress/t/t_trace_no_top_name2.v +++ b/test_regress/t/t_trace_no_top_name2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package foo_pkg; diff --git a/test_regress/t/t_trace_no_top_name2_fst.py b/test_regress/t/t_trace_no_top_name2_fst.py index bedb57f89..d9ca4cfad 100755 --- a/test_regress/t/t_trace_no_top_name2_fst.py +++ b/test_regress/t/t_trace_no_top_name2_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_no_top_name2_saif.py b/test_regress/t/t_trace_no_top_name2_saif.py index 1d92228a8..46e190d0a 100755 --- a/test_regress/t/t_trace_no_top_name2_saif.py +++ b/test_regress/t/t_trace_no_top_name2_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_no_top_name2_vcd.py b/test_regress/t/t_trace_no_top_name2_vcd.py index 77142cc7b..9f472bdd9 100755 --- a/test_regress/t/t_trace_no_top_name2_vcd.py +++ b/test_regress/t/t_trace_no_top_name2_vcd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_noflag_bad.py b/test_regress/t/t_trace_noflag_bad.py index e46f07308..937bf2ff8 100755 --- a/test_regress/t/t_trace_noflag_bad.py +++ b/test_regress/t/t_trace_noflag_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_noflag_bad.v b/test_regress/t/t_trace_noflag_bad.v index a5a2b8e9b..54a5eefc8 100644 --- a/test_regress/t/t_trace_noflag_bad.v +++ b/test_regress/t/t_trace_noflag_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_trace_noflag_bad_c.cpp b/test_regress/t/t_trace_noflag_bad_c.cpp index d46885332..5f167981b 100644 --- a/test_regress/t/t_trace_noflag_bad_c.cpp +++ b/test_regress/t/t_trace_noflag_bad_c.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Yu-Sheng Lin. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2010 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_off_cc.py b/test_regress/t/t_trace_off_cc.py index 27f02bff7..330eae8fc 100755 --- a/test_regress/t/t_trace_off_cc.py +++ b/test_regress/t/t_trace_off_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_off_sc.py b/test_regress/t/t_trace_off_sc.py index 44a184b75..bf674de3e 100755 --- a/test_regress/t/t_trace_off_sc.py +++ b/test_regress/t/t_trace_off_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_open_wrong_order_bad.cpp b/test_regress/t/t_trace_open_wrong_order_bad.cpp index 2a8f4cad9..6235c9f7a 100644 --- a/test_regress/t/t_trace_open_wrong_order_bad.cpp +++ b/test_regress/t/t_trace_open_wrong_order_bad.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Yu-Sheng Lin. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2010 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_open_wrong_order_bad.out b/test_regress/t/t_trace_open_wrong_order_bad.out old mode 100755 new mode 100644 diff --git a/test_regress/t/t_trace_open_wrong_order_bad.py b/test_regress/t/t_trace_open_wrong_order_bad.py index 67239c35d..5e7428f5c 100755 --- a/test_regress/t/t_trace_open_wrong_order_bad.py +++ b/test_regress/t/t_trace_open_wrong_order_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_open_wrong_order_bad.v b/test_regress/t/t_trace_open_wrong_order_bad.v index 60a7504fd..38f8789fb 100644 --- a/test_regress/t/t_trace_open_wrong_order_bad.v +++ b/test_regress/t/t_trace_open_wrong_order_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog dummy test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Yu-Sheng Lin. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2022 Yu-Sheng Lin // SPDX-License-Identifier: CC0-1.0 module t(input clk); diff --git a/test_regress/t/t_trace_packed_struct.py b/test_regress/t/t_trace_packed_struct.py index 142fd5a91..956d14f45 100755 --- a/test_regress/t/t_trace_packed_struct.py +++ b/test_regress/t/t_trace_packed_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_packed_struct.v b/test_regress/t/t_trace_packed_struct.v index 06daeb581..2b60a99f5 100644 --- a/test_regress/t/t_trace_packed_struct.v +++ b/test_regress/t/t_trace_packed_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Andrew Bardsley. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Andrew Bardsley // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_packed_struct_fst.py b/test_regress/t/t_trace_packed_struct_fst.py index 4add1a2b6..82282acf6 100755 --- a/test_regress/t/t_trace_packed_struct_fst.py +++ b/test_regress/t/t_trace_packed_struct_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_packed_struct_fst_sc.py b/test_regress/t/t_trace_packed_struct_fst_sc.py index e329e22e9..c946f98d6 100755 --- a/test_regress/t/t_trace_packed_struct_fst_sc.py +++ b/test_regress/t/t_trace_packed_struct_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_packed_struct_saif.py b/test_regress/t/t_trace_packed_struct_saif.py index 338c14836..2368fa1fc 100755 --- a/test_regress/t/t_trace_packed_struct_saif.py +++ b/test_regress/t/t_trace_packed_struct_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_param.py b/test_regress/t/t_trace_param.py index 1cdcbdd57..90b85c827 100755 --- a/test_regress/t/t_trace_param.py +++ b/test_regress/t/t_trace_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_param.v b/test_regress/t/t_trace_param.v index e1366ec32..b89bc2f83 100644 --- a/test_regress/t/t_trace_param.v +++ b/test_regress/t/t_trace_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Jonathon Donaldson. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Jonathon Donaldson // SPDX-License-Identifier: CC0-1.0 package my_funcs; diff --git a/test_regress/t/t_trace_param_fst.py b/test_regress/t/t_trace_param_fst.py index 863328841..fdc7a622b 100755 --- a/test_regress/t/t_trace_param_fst.py +++ b/test_regress/t/t_trace_param_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_param_override.py b/test_regress/t/t_trace_param_override.py index 2f9c739f3..aceb2480d 100755 --- a/test_regress/t/t_trace_param_override.py +++ b/test_regress/t/t_trace_param_override.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_param_override.v b/test_regress/t/t_trace_param_override.v index 627cf285a..9b48c447c 100644 --- a/test_regress/t/t_trace_param_override.v +++ b/test_regress/t/t_trace_param_override.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_param_saif.py b/test_regress/t/t_trace_param_saif.py index d871baf85..1dd577e76 100755 --- a/test_regress/t/t_trace_param_saif.py +++ b/test_regress/t/t_trace_param_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_primitive.py b/test_regress/t/t_trace_primitive.py index 8ffc1cbfb..26c203087 100755 --- a/test_regress/t/t_trace_primitive.py +++ b/test_regress/t/t_trace_primitive.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_primitive.v b/test_regress/t/t_trace_primitive.v index fe08ff8ca..2df471972 100644 --- a/test_regress/t/t_trace_primitive.v +++ b/test_regress/t/t_trace_primitive.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Jie Xu // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_trace_primitive_fst.py b/test_regress/t/t_trace_primitive_fst.py index 186eb317d..e0efa3ca4 100755 --- a/test_regress/t/t_trace_primitive_fst.py +++ b/test_regress/t/t_trace_primitive_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_primitive_fst_sc.py b/test_regress/t/t_trace_primitive_fst_sc.py index 2c19efdfe..01bf153e3 100755 --- a/test_regress/t/t_trace_primitive_fst_sc.py +++ b/test_regress/t/t_trace_primitive_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_primitive_saif.py b/test_regress/t/t_trace_primitive_saif.py index d2f3be21e..4fa0dc08b 100755 --- a/test_regress/t/t_trace_primitive_saif.py +++ b/test_regress/t/t_trace_primitive_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_public.out b/test_regress/t/t_trace_public.out index c545c91dc..875fb6e14 100644 --- a/test_regress/t/t_trace_public.out +++ b/test_regress/t/t_trace_public.out @@ -1,28 +1,28 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module top $end - $var wire 1 5 CLK $end - $var wire 1 6 RESET $end + $var wire 1 4 CLK $end + $var wire 1 5 RESET $end $scope module t $end - $var wire 1 5 CLK $end - $var wire 1 # RESET $end + $var wire 1 4 CLK $end + $var wire 1 " RESET $end + $var wire 2 # vec[3] [2:1] $end + $var wire 2 $ vec[4] [2:1] $end + $var wire 32 % val [31:0] $end $scope module glbl $end - $var wire 1 7 GSR $end + $var wire 1 6 GSR $end $upscope $end - $var wire 2 $ vec[3] [2:1] $end - $var wire 2 % vec[4] [2:1] $end - $var wire 32 & val [31:0] $end $scope module little $end - $var wire 1 5 clk $end - $var wire 8 ' i8 [0:7] $end - $var wire 49 ( i48 [1:49] $end - $var wire 128 * i128 [63:190] $end + $var wire 1 4 clk $end + $var wire 8 & i8 [0:7] $end + $var wire 49 ' i48 [1:49] $end + $var wire 128 ) i128 [63:190] $end $upscope $end $scope module neg $end - $var wire 1 5 clk $end - $var wire 8 . i8 [0:-7] $end - $var wire 48 / i48 [-1:-48] $end - $var wire 128 1 i128 [63:-64] $end + $var wire 1 4 clk $end + $var wire 8 - i8 [0:-7] $end + $var wire 48 . i48 [-1:-48] $end + $var wire 128 0 i128 [63:-64] $end $upscope $end $upscope $end $upscope $end @@ -30,52 +30,52 @@ $enddefinitions $end #0 -1# +1" +b00 # b00 $ -b00 % -b00000000000000000000000000000000 & -b00000000 ' -b0000000000000000000000000000000000000000000000000 ( -b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 * -b00000000 . -b000000000000000000000000000000000000000000000000 / -b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1 -05 +b00000000000000000000000000000000 % +b00000000 & +b0000000000000000000000000000000000000000000000000 ' +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ) +b00000000 - +b000000000000000000000000000000000000000000000000 . +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0 +04 +15 16 -17 #3 -b11111111 ' -b1111111111111111111111111111111111111111111111111 ( -b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 * -b11111111 . -b111111111111111111111111111111111111111111111111 / -b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1 -15 +b11111111 & +b1111111111111111111111111111111111111111111111111 ' +b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 ) +b11111111 - +b111111111111111111111111111111111111111111111111 . +b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 0 +14 #6 -05 +04 #7 -07 -#9 -0# -b00000000 ' -b0000000000000000000000000000000000000000000000000 ( -b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 * -b00000000 . -b000000000000000000000000000000000000000000000000 / -b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1 -15 06 +#9 +0" +b00000000 & +b0000000000000000000000000000000000000000000000000 ' +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ) +b00000000 - +b000000000000000000000000000000000000000000000000 . +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0 +14 +05 #12 -05 +04 #15 -b00000000000000000000000000000001 & -b11111111 ' -b1111111111111111111111111111111111111111111111111 ( -b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 * -b11111111 . -b111111111111111111111111111111111111111111111111 / -b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1 -15 +b00000000000000000000000000000001 % +b11111111 & +b1111111111111111111111111111111111111111111111111 ' +b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 ) +b11111111 - +b111111111111111111111111111111111111111111111111 . +b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 0 +14 #18 -05 +04 #20 diff --git a/test_regress/t/t_trace_public.v b/test_regress/t/t_trace_public.v index e6ea04953..cebbd5258 100644 --- a/test_regress/t/t_trace_public.v +++ b/test_regress/t/t_trace_public.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_trace_public_func.cpp b/test_regress/t/t_trace_public_func.cpp index a05820e24..2d1c22a96 100644 --- a/test_regress/t/t_trace_public_func.cpp +++ b/test_regress/t/t_trace_public_func.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_public_func.py b/test_regress/t/t_trace_public_func.py index b9350881d..f830c67ee 100755 --- a/test_regress/t/t_trace_public_func.py +++ b/test_regress/t/t_trace_public_func.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_public_func.vlt b/test_regress/t/t_trace_public_func.vlt index 41089da90..c767bd046 100644 --- a/test_regress/t/t_trace_public_func.vlt +++ b/test_regress/t/t_trace_public_func.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_trace_public_func_vlt.py b/test_regress/t/t_trace_public_func_vlt.py index 1b361af85..d9bb72b4c 100755 --- a/test_regress/t/t_trace_public_func_vlt.py +++ b/test_regress/t/t_trace_public_func_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_public_sig.cpp b/test_regress/t/t_trace_public_sig.cpp index c694a85cc..cb42badfd 100644 --- a/test_regress/t/t_trace_public_sig.cpp +++ b/test_regress/t/t_trace_public_sig.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_public_sig.py b/test_regress/t/t_trace_public_sig.py index 4aa00e389..29037763f 100755 --- a/test_regress/t/t_trace_public_sig.py +++ b/test_regress/t/t_trace_public_sig.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_public_sig.vlt b/test_regress/t/t_trace_public_sig.vlt index dbe85510d..50e20437a 100644 --- a/test_regress/t/t_trace_public_sig.vlt +++ b/test_regress/t/t_trace_public_sig.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_trace_public_sig_vlt.py b/test_regress/t/t_trace_public_sig_vlt.py index e0b6c8498..6cdcdb806 100755 --- a/test_regress/t/t_trace_public_sig_vlt.py +++ b/test_regress/t/t_trace_public_sig_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_rollover.cpp b/test_regress/t/t_trace_rollover.cpp index ce4b6e130..8a17bdda8 100644 --- a/test_regress/t/t_trace_rollover.cpp +++ b/test_regress/t/t_trace_rollover.cpp @@ -2,8 +2,8 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_rollover.py b/test_regress/t/t_trace_rollover.py index 299193528..41d3402ff 100755 --- a/test_regress/t/t_trace_rollover.py +++ b/test_regress/t/t_trace_rollover.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_saif.out b/test_regress/t/t_trace_saif.out index 76e04cab1..a2f83dfc1 100644 --- a/test_regress/t/t_trace_saif.out +++ b/test_regress/t/t_trace_saif.out @@ -574,78 +574,6 @@ (state_array[2]\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) ) - (INSTANCE unnamedblk1 - (NET - (i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) - (i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) - (i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - ) - (INSTANCE unnamedblk2 - (NET - (i\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1)) - (i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - ) ) ) ) diff --git a/test_regress/t/t_trace_saif.py b/test_regress/t/t_trace_saif.py index 21bd2b9e2..7396b58b0 100755 --- a/test_regress/t/t_trace_saif.py +++ b/test_regress/t/t_trace_saif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_saif_cmake.out b/test_regress/t/t_trace_saif_cmake.out index b3929c760..c0e3c426f 100644 --- a/test_regress/t/t_trace_saif_cmake.out +++ b/test_regress/t/t_trace_saif_cmake.out @@ -503,78 +503,6 @@ (state_array[2]\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) ) - (INSTANCE unnamedblk1 - (NET - (i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) - (i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) - (i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - ) - (INSTANCE unnamedblk2 - (NET - (i\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1)) - (i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - ) ) ) ) diff --git a/test_regress/t/t_trace_saif_cmake.py b/test_regress/t/t_trace_saif_cmake.py index 11d689389..73b4d1ebd 100755 --- a/test_regress/t/t_trace_saif_cmake.py +++ b/test_regress/t/t_trace_saif_cmake.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_saif_sc.out b/test_regress/t/t_trace_saif_sc.out old mode 100755 new mode 100644 index f92131c4a..840660324 --- a/test_regress/t/t_trace_saif_sc.out +++ b/test_regress/t/t_trace_saif_sc.out @@ -495,78 +495,6 @@ (state_array[2]\[3\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) (state_array[2]\[4\] (T0 530) (T1 474) (TZ 0) (TX 0) (TB 0) (TC 47)) ) - (INSTANCE unnamedblk1 - (NET - (i\[0\] (T0 10) (T1 994) (TZ 0) (TX 0) (TB 0) (TC 1)) - (i\[1\] (T0 10) (T1 994) (TZ 0) (TX 0) (TB 0) (TC 1)) - (i\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - ) - (INSTANCE unnamedblk2 - (NET - (i\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[1\] (T0 120) (T1 884) (TZ 0) (TX 0) (TB 0) (TC 1)) - (i\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - (i\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) - ) - ) ) ) ) diff --git a/test_regress/t/t_trace_saif_sc.py b/test_regress/t/t_trace_saif_sc.py index aae4356a6..648fa0834 100755 --- a/test_regress/t/t_trace_saif_sc.py +++ b/test_regress/t/t_trace_saif_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_sc_empty.py b/test_regress/t/t_trace_sc_empty.py index 0c413116d..54df565ff 100755 --- a/test_regress/t/t_trace_sc_empty.py +++ b/test_regress/t/t_trace_sc_empty.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_sc_empty.v b/test_regress/t/t_trace_sc_empty.v index 4136b8663..a78a4f756 100644 --- a/test_regress/t/t_trace_sc_empty.v +++ b/test_regress/t/t_trace_sc_empty.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilsn Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_trace_scope_no_inline.py b/test_regress/t/t_trace_scope_no_inline.py index dc37817c5..d0f7105ec 100755 --- a/test_regress/t/t_trace_scope_no_inline.py +++ b/test_regress/t/t_trace_scope_no_inline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_scope_no_inline.v b/test_regress/t/t_trace_scope_no_inline.v index 08301f929..45f0f3a09 100644 --- a/test_regress/t/t_trace_scope_no_inline.v +++ b/test_regress/t/t_trace_scope_no_inline.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_trace_scope_no_inline.vlt b/test_regress/t/t_trace_scope_no_inline.vlt index 08369f630..3a90b0cb4 100644 --- a/test_regress/t/t_trace_scope_no_inline.vlt +++ b/test_regress/t/t_trace_scope_no_inline.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_trace_scope_vlt.py b/test_regress/t/t_trace_scope_vlt.py index 7d91064b2..1933262e2 100755 --- a/test_regress/t/t_trace_scope_vlt.py +++ b/test_regress/t/t_trace_scope_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_scope_vlt.v b/test_regress/t/t_trace_scope_vlt.v index 4c9705348..ff0cc6ec5 100644 --- a/test_regress/t/t_trace_scope_vlt.v +++ b/test_regress/t/t_trace_scope_vlt.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_scope_vlt.vlt b/test_regress/t/t_trace_scope_vlt.vlt index cd7dd85ab..7b6f44d3f 100644 --- a/test_regress/t/t_trace_scope_vlt.vlt +++ b/test_regress/t/t_trace_scope_vlt.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_trace_scstruct.py b/test_regress/t/t_trace_scstruct.py index 03ec178a4..dbd69ed8a 100755 --- a/test_regress/t/t_trace_scstruct.py +++ b/test_regress/t/t_trace_scstruct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_scstruct.v b/test_regress/t/t_trace_scstruct.v index 613171027..4196f42d6 100644 --- a/test_regress/t/t_trace_scstruct.v +++ b/test_regress/t/t_trace_scstruct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNUSED diff --git a/test_regress/t/t_trace_split_cfuncs.py b/test_regress/t/t_trace_split_cfuncs.py index c2536c656..8af8e39d0 100755 --- a/test_regress/t/t_trace_split_cfuncs.py +++ b/test_regress/t/t_trace_split_cfuncs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_split_cfuncs.v b/test_regress/t/t_trace_split_cfuncs.v index c2750d468..be695fa88 100644 --- a/test_regress/t/t_trace_split_cfuncs.v +++ b/test_regress/t/t_trace_split_cfuncs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Varun Koyyalagunta. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_trace_split_cfuncs_dpi_export.py b/test_regress/t/t_trace_split_cfuncs_dpi_export.py index c2536c656..8af8e39d0 100755 --- a/test_regress/t/t_trace_split_cfuncs_dpi_export.py +++ b/test_regress/t/t_trace_split_cfuncs_dpi_export.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_split_cfuncs_dpi_export.v b/test_regress/t/t_trace_split_cfuncs_dpi_export.v index aa82f7813..2951f36e1 100644 --- a/test_regress/t/t_trace_split_cfuncs_dpi_export.v +++ b/test_regress/t/t_trace_split_cfuncs_dpi_export.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Varun Koyyalagunta. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_trace_string.py b/test_regress/t/t_trace_string.py index 41f81a0a2..31b62b04e 100755 --- a/test_regress/t/t_trace_string.py +++ b/test_regress/t/t_trace_string.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_string.v b/test_regress/t/t_trace_string.v index 065a7c2f9..8e7220c8f 100644 --- a/test_regress/t/t_trace_string.v +++ b/test_regress/t/t_trace_string.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_string_fst.py b/test_regress/t/t_trace_string_fst.py index 32dc6d8d2..4e081fbbf 100755 --- a/test_regress/t/t_trace_string_fst.py +++ b/test_regress/t/t_trace_string_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_string_fst_sc.py b/test_regress/t/t_trace_string_fst_sc.py index 5bc0d3ad4..057c29cfe 100755 --- a/test_regress/t/t_trace_string_fst_sc.py +++ b/test_regress/t/t_trace_string_fst_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_timescale.py b/test_regress/t/t_trace_timescale.py index ce8cf9a96..a84224fa2 100755 --- a/test_regress/t/t_trace_timescale.py +++ b/test_regress/t/t_trace_timescale.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_timescale.v b/test_regress/t/t_trace_timescale.v index 206f7e601..aed05df84 100644 --- a/test_regress/t/t_trace_timescale.v +++ b/test_regress/t/t_trace_timescale.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `timescale 1ms/1ms diff --git a/test_regress/t/t_trace_timing1.py b/test_regress/t/t_trace_timing1.py index 4813384d9..fcf27f296 100755 --- a/test_regress/t/t_trace_timing1.py +++ b/test_regress/t/t_trace_timing1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_timing1.v b/test_regress/t/t_trace_timing1.v index 51afa7871..9c628a93f 100644 --- a/test_regress/t/t_trace_timing1.v +++ b/test_regress/t/t_trace_timing1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_two_a.v b/test_regress/t/t_trace_two_a.v index b6a310870..2d2db3180 100644 --- a/test_regress/t/t_trace_two_a.v +++ b/test_regress/t/t_trace_two_a.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define CONCAT(a, b) a``b diff --git a/test_regress/t/t_trace_two_b.v b/test_regress/t/t_trace_two_b.v index 22aad670b..a5bcad4c4 100644 --- a/test_regress/t/t_trace_two_b.v +++ b/test_regress/t/t_trace_two_b.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_trace_two_cc.cpp b/test_regress/t/t_trace_two_cc.cpp index 46ad12913..bc0dfae5d 100644 --- a/test_regress/t/t_trace_two_cc.cpp +++ b/test_regress/t/t_trace_two_cc.cpp @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // clang-format off diff --git a/test_regress/t/t_trace_two_dump_cc.py b/test_regress/t/t_trace_two_dump_cc.py index a51b7661e..a100832af 100755 --- a/test_regress/t/t_trace_two_dump_cc.py +++ b/test_regress/t/t_trace_two_dump_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced diff --git a/test_regress/t/t_trace_two_dump_sc.py b/test_regress/t/t_trace_two_dump_sc.py index 00db26b57..db421fb2f 100755 --- a/test_regress/t/t_trace_two_dump_sc.py +++ b/test_regress/t/t_trace_two_dump_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_two_dumpfst_cc.py b/test_regress/t/t_trace_two_dumpfst_cc.py index 625f3c8ac..b7f599a1b 100755 --- a/test_regress/t/t_trace_two_dumpfst_cc.py +++ b/test_regress/t/t_trace_two_dumpfst_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced diff --git a/test_regress/t/t_trace_two_hdr_cc.py b/test_regress/t/t_trace_two_hdr_cc.py index a6212983e..8f21dfeb7 100755 --- a/test_regress/t/t_trace_two_hdr_cc.py +++ b/test_regress/t/t_trace_two_hdr_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced diff --git a/test_regress/t/t_trace_two_hdr_sc.py b/test_regress/t/t_trace_two_hdr_sc.py index f189d58f0..c5dce0997 100755 --- a/test_regress/t/t_trace_two_hdr_sc.py +++ b/test_regress/t/t_trace_two_hdr_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_two_hdrfst_cc.py b/test_regress/t/t_trace_two_hdrfst_cc.py index 3836a14ad..161d13155 100755 --- a/test_regress/t/t_trace_two_hdrfst_cc.py +++ b/test_regress/t/t_trace_two_hdrfst_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced diff --git a/test_regress/t/t_trace_two_port_cc.py b/test_regress/t/t_trace_two_port_cc.py index e4317efaa..e860eb274 100755 --- a/test_regress/t/t_trace_two_port_cc.py +++ b/test_regress/t/t_trace_two_port_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced diff --git a/test_regress/t/t_trace_two_port_sc.py b/test_regress/t/t_trace_two_port_sc.py index b26f20592..320c1a2d7 100755 --- a/test_regress/t/t_trace_two_port_sc.py +++ b/test_regress/t/t_trace_two_port_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_two_portfst_cc.py b/test_regress/t/t_trace_two_portfst_cc.py index b1048f6a9..09fe16efd 100755 --- a/test_regress/t/t_trace_two_portfst_cc.py +++ b/test_regress/t/t_trace_two_portfst_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced diff --git a/test_regress/t/t_trace_two_sc.cpp b/test_regress/t/t_trace_two_sc.cpp index c1ba67b28..586ed20df 100644 --- a/test_regress/t/t_trace_two_sc.cpp +++ b/test_regress/t/t_trace_two_sc.cpp @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // clang-format off diff --git a/test_regress/t/t_trace_ub_misaligned_address.py b/test_regress/t/t_trace_ub_misaligned_address.py index e6729183e..4f9e45d45 100755 --- a/test_regress/t/t_trace_ub_misaligned_address.py +++ b/test_regress/t/t_trace_ub_misaligned_address.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_ub_misaligned_address.v b/test_regress/t/t_trace_ub_misaligned_address.v index 40b351aa7..b2ab81934 100644 --- a/test_regress/t/t_trace_ub_misaligned_address.v +++ b/test_regress/t/t_trace_ub_misaligned_address.v @@ -8,8 +8,8 @@ // due to 32 bit aligned addresses being used for types which require // stricter alignment. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by John Wehle. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 John Wehle // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_wide_struct.py b/test_regress/t/t_trace_wide_struct.py index d25b73259..558b51518 100755 --- a/test_regress/t/t_trace_wide_struct.py +++ b/test_regress/t/t_trace_wide_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_wide_struct.v b/test_regress/t/t_trace_wide_struct.v index 4a381de5a..25439fb8c 100644 --- a/test_regress/t/t_trace_wide_struct.v +++ b/test_regress/t/t_trace_wide_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_and_eqcase.py b/test_regress/t/t_tri_and_eqcase.py index 6585af685..b7449248c 100755 --- a/test_regress/t/t_tri_and_eqcase.py +++ b/test_regress/t/t_tri_and_eqcase.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_and_eqcase.v b/test_regress/t/t_tri_and_eqcase.v index 1c4b09a14..e7c0a4ea3 100644 --- a/test_regress/t/t_tri_and_eqcase.v +++ b/test_regress/t/t_tri_and_eqcase.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (clk1, clk2); diff --git a/test_regress/t/t_tri_array.py b/test_regress/t/t_tri_array.py index d0b1f865e..0f7fe1942 100755 --- a/test_regress/t/t_tri_array.py +++ b/test_regress/t/t_tri_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_array.v b/test_regress/t/t_tri_array.v index fbda60f76..d1fe77daf 100644 --- a/test_regress/t/t_tri_array.v +++ b/test_regress/t/t_tri_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_array_bufif.py b/test_regress/t/t_tri_array_bufif.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_array_bufif.py +++ b/test_regress/t/t_tri_array_bufif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_array_bufif.v b/test_regress/t/t_tri_array_bufif.v index 200bd4728..43f281976 100644 --- a/test_regress/t/t_tri_array_bufif.v +++ b/test_regress/t/t_tri_array_bufif.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_array_pull.py b/test_regress/t/t_tri_array_pull.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_array_pull.py +++ b/test_regress/t/t_tri_array_pull.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_array_pull.v b/test_regress/t/t_tri_array_pull.v index b29d1d5b5..6a6037599 100644 --- a/test_regress/t/t_tri_array_pull.v +++ b/test_regress/t/t_tri_array_pull.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Rod Steward. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Rod Steward // SPDX-License-Identifier: CC0-1.0 module IOBUF ( input T, input I, output O, inout IO ); diff --git a/test_regress/t/t_tri_clocking.py b/test_regress/t/t_tri_clocking.py new file mode 100755 index 000000000..84b274f68 --- /dev/null +++ b/test_regress/t/t_tri_clocking.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_tri_clocking.v b/test_regress/t/t_tri_clocking.v new file mode 100644 index 000000000..ddcaade89 --- /dev/null +++ b/test_regress/t/t_tri_clocking.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +interface wb_ifc; + logic clk; + wire rst; + tri0 cyc; + clocking mck @(posedge clk); + input rst; + output cyc; + endclocking +endinterface + +module t; + wb_ifc wb_ma (); + initial $finish; +endmodule diff --git a/test_regress/t/t_tri_compass_bad.py b/test_regress/t/t_tri_compass_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_tri_compass_bad.py +++ b/test_regress/t/t_tri_compass_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_compass_bad.v b/test_regress/t/t_tri_compass_bad.v index d95ced5c1..1843f76e8 100644 --- a/test_regress/t/t_tri_compass_bad.v +++ b/test_regress/t/t_tri_compass_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_tri_cond_eqcase_with_1.py b/test_regress/t/t_tri_cond_eqcase_with_1.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_cond_eqcase_with_1.py +++ b/test_regress/t/t_tri_cond_eqcase_with_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_cond_eqcase_with_1.v b/test_regress/t/t_tri_cond_eqcase_with_1.v index 552280b98..af7cff2f8 100644 --- a/test_regress/t/t_tri_cond_eqcase_with_1.v +++ b/test_regress/t/t_tri_cond_eqcase_with_1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_dangle.py b/test_regress/t/t_tri_dangle.py index 2b6ee4e44..3fe52cd1f 100755 --- a/test_regress/t/t_tri_dangle.py +++ b/test_regress/t/t_tri_dangle.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_dangle.v b/test_regress/t/t_tri_dangle.v index db659de70..4a82f15e6 100644 --- a/test_regress/t/t_tri_dangle.v +++ b/test_regress/t/t_tri_dangle.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_eqcase.py b/test_regress/t/t_tri_eqcase.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_eqcase.py +++ b/test_regress/t/t_tri_eqcase.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_eqcase.v b/test_regress/t/t_tri_eqcase.v index 17a634469..5a7919534 100644 --- a/test_regress/t/t_tri_eqcase.v +++ b/test_regress/t/t_tri_eqcase.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_eqcase_input.py b/test_regress/t/t_tri_eqcase_input.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_eqcase_input.py +++ b/test_regress/t/t_tri_eqcase_input.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_eqcase_input.v b/test_regress/t/t_tri_eqcase_input.v index 518ae40e1..9c61640db 100644 --- a/test_regress/t/t_tri_eqcase_input.v +++ b/test_regress/t/t_tri_eqcase_input.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_gate.cpp b/test_regress/t/t_tri_gate.cpp index 5996914aa..37e8df792 100644 --- a/test_regress/t/t_tri_gate.cpp +++ b/test_regress/t/t_tri_gate.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_tri_gate.v b/test_regress/t/t_tri_gate.v index bf0cccb8d..d2d404157 100644 --- a/test_regress/t/t_tri_gate.v +++ b/test_regress/t/t_tri_gate.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 module top (input SEL, input[1:0] A, output W, output X, output Y, output Z); diff --git a/test_regress/t/t_tri_gate_bufif0.py b/test_regress/t/t_tri_gate_bufif0.py index 4634d4e76..97ee1b367 100755 --- a/test_regress/t/t_tri_gate_bufif0.py +++ b/test_regress/t/t_tri_gate_bufif0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_bufif0_pins_inout.py b/test_regress/t/t_tri_gate_bufif0_pins_inout.py index 76fc851c5..05e7201b3 100755 --- a/test_regress/t/t_tri_gate_bufif0_pins_inout.py +++ b/test_regress/t/t_tri_gate_bufif0_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_bufif1.py b/test_regress/t/t_tri_gate_bufif1.py index 1a14c142e..29127de06 100755 --- a/test_regress/t/t_tri_gate_bufif1.py +++ b/test_regress/t/t_tri_gate_bufif1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_bufif1_pins_inout.py b/test_regress/t/t_tri_gate_bufif1_pins_inout.py index 6a4dce294..b0e2f3aeb 100755 --- a/test_regress/t/t_tri_gate_bufif1_pins_inout.py +++ b/test_regress/t/t_tri_gate_bufif1_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_cond.py b/test_regress/t/t_tri_gate_cond.py index c4b5851c4..2cfc0ee1a 100755 --- a/test_regress/t/t_tri_gate_cond.py +++ b/test_regress/t/t_tri_gate_cond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_cond_pins_inout.py b/test_regress/t/t_tri_gate_cond_pins_inout.py index 20ffe23ea..03c32e767 100755 --- a/test_regress/t/t_tri_gate_cond_pins_inout.py +++ b/test_regress/t/t_tri_gate_cond_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_nmos.py b/test_regress/t/t_tri_gate_nmos.py index 8b8c924f2..eca8b57d5 100755 --- a/test_regress/t/t_tri_gate_nmos.py +++ b/test_regress/t/t_tri_gate_nmos.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_nmos_pins_inout.py b/test_regress/t/t_tri_gate_nmos_pins_inout.py index fc4bbaa5c..3bb5fd1bf 100755 --- a/test_regress/t/t_tri_gate_nmos_pins_inout.py +++ b/test_regress/t/t_tri_gate_nmos_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_notif0.py b/test_regress/t/t_tri_gate_notif0.py index a9dd77046..f27090c7e 100755 --- a/test_regress/t/t_tri_gate_notif0.py +++ b/test_regress/t/t_tri_gate_notif0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_notif0_pins_inout.py b/test_regress/t/t_tri_gate_notif0_pins_inout.py index 797e8d163..d06b9a0b6 100755 --- a/test_regress/t/t_tri_gate_notif0_pins_inout.py +++ b/test_regress/t/t_tri_gate_notif0_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_notif1.py b/test_regress/t/t_tri_gate_notif1.py index 09350a74e..bc180bf81 100755 --- a/test_regress/t/t_tri_gate_notif1.py +++ b/test_regress/t/t_tri_gate_notif1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_notif1_pins_inout.py b/test_regress/t/t_tri_gate_notif1_pins_inout.py index c03f247c7..06c52aa2f 100755 --- a/test_regress/t/t_tri_gate_notif1_pins_inout.py +++ b/test_regress/t/t_tri_gate_notif1_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_pmos.py b/test_regress/t/t_tri_gate_pmos.py index 9f23ab621..6b26f68ff 100755 --- a/test_regress/t/t_tri_gate_pmos.py +++ b/test_regress/t/t_tri_gate_pmos.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gate_pmos_pins_inout.py b/test_regress/t/t_tri_gate_pmos_pins_inout.py index c9177fd57..172127396 100755 --- a/test_regress/t/t_tri_gate_pmos_pins_inout.py +++ b/test_regress/t/t_tri_gate_pmos_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gen.py b/test_regress/t/t_tri_gen.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_gen.py +++ b/test_regress/t/t_tri_gen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_gen.v b/test_regress/t/t_tri_gen.v index 53d8bbfa3..a7c479dee 100644 --- a/test_regress/t/t_tri_gen.v +++ b/test_regress/t/t_tri_gen.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_graph.py b/test_regress/t/t_tri_graph.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_tri_graph.py +++ b/test_regress/t/t_tri_graph.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_graph.v b/test_regress/t/t_tri_graph.v index 868d14c62..0dc1a68d9 100644 --- a/test_regress/t/t_tri_graph.v +++ b/test_regress/t/t_tri_graph.v @@ -2,8 +2,8 @@ // // This is a compile only regression test of tristate handling for bug514 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_ifbegin.py b/test_regress/t/t_tri_ifbegin.py index 3aafd524c..f8083269e 100755 --- a/test_regress/t/t_tri_ifbegin.py +++ b/test_regress/t/t_tri_ifbegin.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_ifbegin.v b/test_regress/t/t_tri_ifbegin.v index cd567515a..a30b81091 100644 --- a/test_regress/t/t_tri_ifbegin.v +++ b/test_regress/t/t_tri_ifbegin.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_inout.cpp b/test_regress/t/t_tri_inout.cpp index 812db4be0..836cdd95b 100644 --- a/test_regress/t/t_tri_inout.cpp +++ b/test_regress/t/t_tri_inout.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_tri_inout.py b/test_regress/t/t_tri_inout.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_tri_inout.py +++ b/test_regress/t/t_tri_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_inout.v b/test_regress/t/t_tri_inout.v index d9673beb9..4594bd2ef 100644 --- a/test_regress/t/t_tri_inout.v +++ b/test_regress/t/t_tri_inout.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 module top (input A, input B, input SEL, input clk, output Y1, output Y2, output Z, output done); diff --git a/test_regress/t/t_tri_inout2.py b/test_regress/t/t_tri_inout2.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_inout2.py +++ b/test_regress/t/t_tri_inout2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_inout2.v b/test_regress/t/t_tri_inout2.v index ed71712b4..5936c889e 100644 --- a/test_regress/t/t_tri_inout2.v +++ b/test_regress/t/t_tri_inout2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_inout_pins_inout.py b/test_regress/t/t_tri_inout_pins_inout.py index 18d447887..859c1b9f4 100755 --- a/test_regress/t/t_tri_inout_pins_inout.py +++ b/test_regress/t/t_tri_inout_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_inz.cpp b/test_regress/t/t_tri_inz.cpp index 816533dd3..5953d615e 100644 --- a/test_regress/t/t_tri_inz.cpp +++ b/test_regress/t/t_tri_inz.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include "Vt_tri_inz.h" diff --git a/test_regress/t/t_tri_inz.py b/test_regress/t/t_tri_inz.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_tri_inz.py +++ b/test_regress/t/t_tri_inz.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_inz.v b/test_regress/t/t_tri_inz.v index f26fce1cd..e0a882303 100644 --- a/test_regress/t/t_tri_inz.v +++ b/test_regress/t/t_tri_inz.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module top diff --git a/test_regress/t/t_tri_no_top.py b/test_regress/t/t_tri_no_top.py index 0e7d8d554..301be6869 100755 --- a/test_regress/t/t_tri_no_top.py +++ b/test_regress/t/t_tri_no_top.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_no_top.v b/test_regress/t/t_tri_no_top.v index de88be561..87778ccce 100644 --- a/test_regress/t/t_tri_no_top.v +++ b/test_regress/t/t_tri_no_top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Paul Wright. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Paul Wright // SPDX-License-Identifier: CC0-1.0 // The module t_tri_top_en_out is used to test that we can diff --git a/test_regress/t/t_tri_public.py b/test_regress/t/t_tri_public.py index c23e16d62..af5809d6c 100755 --- a/test_regress/t/t_tri_public.py +++ b/test_regress/t/t_tri_public.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_public.v b/test_regress/t/t_tri_public.v index 46b522d37..b2df6b26b 100644 --- a/test_regress/t/t_tri_public.v +++ b/test_regress/t/t_tri_public.v @@ -2,8 +2,8 @@ // // This is a compile only regression test of tristate handling for bug514 // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Rob Stoddard. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Rob Stoddard // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_pull01.py b/test_regress/t/t_tri_pull01.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_pull01.py +++ b/test_regress/t/t_tri_pull01.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_pull01.v b/test_regress/t/t_tri_pull01.v index 902d6248d..5439d656f 100644 --- a/test_regress/t/t_tri_pull01.v +++ b/test_regress/t/t_tri_pull01.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_pull2_bad.py b/test_regress/t/t_tri_pull2_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_tri_pull2_bad.py +++ b/test_regress/t/t_tri_pull2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_pull2_bad.v b/test_regress/t/t_tri_pull2_bad.v index 4b307d169..e4dc23f9c 100644 --- a/test_regress/t/t_tri_pull2_bad.v +++ b/test_regress/t/t_tri_pull2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Lane Brooks // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_tri_pull_bad.py b/test_regress/t/t_tri_pull_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_tri_pull_bad.py +++ b/test_regress/t/t_tri_pull_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_pull_bad.v b/test_regress/t/t_tri_pull_bad.v index 793786a1a..ba4d66624 100644 --- a/test_regress/t/t_tri_pull_bad.v +++ b/test_regress/t/t_tri_pull_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Lane Brooks // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_tri_pull_implicit.py b/test_regress/t/t_tri_pull_implicit.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_pull_implicit.py +++ b/test_regress/t/t_tri_pull_implicit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_pull_implicit.v b/test_regress/t/t_tri_pull_implicit.v index 5f15c006f..21bff656b 100644 --- a/test_regress/t/t_tri_pull_implicit.v +++ b/test_regress/t/t_tri_pull_implicit.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_tri_pull_unsup.py b/test_regress/t/t_tri_pull_unsup.py index 6585af685..b7449248c 100755 --- a/test_regress/t/t_tri_pull_unsup.py +++ b/test_regress/t/t_tri_pull_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_pull_unsup.v b/test_regress/t/t_tri_pull_unsup.v index b20379429..34d8010c2 100644 --- a/test_regress/t/t_tri_pull_unsup.v +++ b/test_regress/t/t_tri_pull_unsup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_tri_pullup.cpp b/test_regress/t/t_tri_pullup.cpp index 311c28744..fc2456350 100644 --- a/test_regress/t/t_tri_pullup.cpp +++ b/test_regress/t/t_tri_pullup.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_tri_pullup.py b/test_regress/t/t_tri_pullup.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_tri_pullup.py +++ b/test_regress/t/t_tri_pullup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_pullup.v b/test_regress/t/t_tri_pullup.v index 00c41ce0a..7efff2ddb 100644 --- a/test_regress/t/t_tri_pullup.v +++ b/test_regress/t/t_tri_pullup.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 module top (input A, input OE, output X, output Y, output Z); diff --git a/test_regress/t/t_tri_pullup_pins_inout.py b/test_regress/t/t_tri_pullup_pins_inout.py index fcfabc5fe..f9f977fff 100755 --- a/test_regress/t/t_tri_pullup_pins_inout.py +++ b/test_regress/t/t_tri_pullup_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_pullvec_bad.py b/test_regress/t/t_tri_pullvec_bad.py index 6585af685..b7449248c 100755 --- a/test_regress/t/t_tri_pullvec_bad.py +++ b/test_regress/t/t_tri_pullvec_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_pullvec_bad.v b/test_regress/t/t_tri_pullvec_bad.v index cd38fd202..1fa8f6dcf 100644 --- a/test_regress/t/t_tri_pullvec_bad.v +++ b/test_regress/t/t_tri_pullvec_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_tri_select.cpp b/test_regress/t/t_tri_select.cpp index fbea109aa..b64579e76 100644 --- a/test_regress/t/t_tri_select.cpp +++ b/test_regress/t/t_tri_select.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_tri_select.py b/test_regress/t/t_tri_select.py index 273ccc85c..c012be81c 100755 --- a/test_regress/t/t_tri_select.py +++ b/test_regress/t/t_tri_select.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_select.v b/test_regress/t/t_tri_select.v index a270dd927..7d7105a44 100644 --- a/test_regress/t/t_tri_select.v +++ b/test_regress/t/t_tri_select.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 `define WIDTH 2 diff --git a/test_regress/t/t_tri_select_eqcase.py b/test_regress/t/t_tri_select_eqcase.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_select_eqcase.py +++ b/test_regress/t/t_tri_select_eqcase.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_select_eqcase.v b/test_regress/t/t_tri_select_eqcase.v index e2b33fb83..3ad2d1376 100644 --- a/test_regress/t/t_tri_select_eqcase.v +++ b/test_regress/t/t_tri_select_eqcase.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_tri_select_pins_inout.py b/test_regress/t/t_tri_select_pins_inout.py index da7c9bb9c..0865258ca 100755 --- a/test_regress/t/t_tri_select_pins_inout.py +++ b/test_regress/t/t_tri_select_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_select_unsized.py b/test_regress/t/t_tri_select_unsized.py index 55e4826e3..8a664fff2 100755 --- a/test_regress/t/t_tri_select_unsized.py +++ b/test_regress/t/t_tri_select_unsized.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_select_unsized.v b/test_regress/t/t_tri_select_unsized.v index 87a250039..fa62e318c 100644 --- a/test_regress/t/t_tri_select_unsized.v +++ b/test_regress/t/t_tri_select_unsized.v @@ -2,8 +2,8 @@ // // Test selecting Z when size is not explicit. Issue 510. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_struct.py b/test_regress/t/t_tri_struct.py index 2b4837fcc..096e10e28 100755 --- a/test_regress/t/t_tri_struct.py +++ b/test_regress/t/t_tri_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_struct.v b/test_regress/t/t_tri_struct.v index e2aba4d5f..1898e4a37 100644 --- a/test_regress/t/t_tri_struct.v +++ b/test_regress/t/t_tri_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef struct { diff --git a/test_regress/t/t_tri_struct_packed.py b/test_regress/t/t_tri_struct_packed.py index 8c78c7f82..6a295cd2f 100755 --- a/test_regress/t/t_tri_struct_packed.py +++ b/test_regress/t/t_tri_struct_packed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_struct_packed.v b/test_regress/t/t_tri_struct_packed.v index df1f8aa6e..13271a16c 100644 --- a/test_regress/t/t_tri_struct_packed.v +++ b/test_regress/t/t_tri_struct_packed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef struct packed { diff --git a/test_regress/t/t_tri_struct_pins_inout.py b/test_regress/t/t_tri_struct_pins_inout.py index bc97e2d68..e7835e924 100755 --- a/test_regress/t/t_tri_struct_pins_inout.py +++ b/test_regress/t/t_tri_struct_pins_inout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_top_en_out.cpp b/test_regress/t/t_tri_top_en_out.cpp index 2a3228353..e1e9943a4 100644 --- a/test_regress/t/t_tri_top_en_out.cpp +++ b/test_regress/t/t_tri_top_en_out.cpp @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module, C driver code // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Paul Wright. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Paul Wright // SPDX-License-Identifier: CC0-1.0 #include "verilated.h" diff --git a/test_regress/t/t_tri_top_en_out.py b/test_regress/t/t_tri_top_en_out.py index da6e614c5..50bd0ba46 100755 --- a/test_regress/t/t_tri_top_en_out.py +++ b/test_regress/t/t_tri_top_en_out.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_top_en_out.v b/test_regress/t/t_tri_top_en_out.v index 1f69dafe8..02df3e84b 100644 --- a/test_regress/t/t_tri_top_en_out.v +++ b/test_regress/t/t_tri_top_en_out.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Paul Wright. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Paul Wright // SPDX-License-Identifier: CC0-1.0 // A submodule to ensure that __en and __out propagate upwards diff --git a/test_regress/t/t_tri_top_en_out_bad.py b/test_regress/t/t_tri_top_en_out_bad.py index 6b0e5e228..f5fd8e225 100755 --- a/test_regress/t/t_tri_top_en_out_bad.py +++ b/test_regress/t/t_tri_top_en_out_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_top_en_out_bad.v b/test_regress/t/t_tri_top_en_out_bad.v index 0e42fcbde..1363cae09 100644 --- a/test_regress/t/t_tri_top_en_out_bad.v +++ b/test_regress/t/t_tri_top_en_out_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Paul Wright. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Paul Wright // SPDX-License-Identifier: CC0-1.0 // // A submodule to ensure that __en and __out propagate upwards diff --git a/test_regress/t/t_tri_unconn.py b/test_regress/t/t_tri_unconn.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_unconn.py +++ b/test_regress/t/t_tri_unconn.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_unconn.v b/test_regress/t/t_tri_unconn.v index 1c18d1500..c1989faac 100644 --- a/test_regress/t/t_tri_unconn.v +++ b/test_regress/t/t_tri_unconn.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_tri_various.py b/test_regress/t/t_tri_various.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_tri_various.py +++ b/test_regress/t/t_tri_various.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_tri_various.v b/test_regress/t/t_tri_various.v index e492ec1de..7a9b332e7 100644 --- a/test_regress/t/t_tri_various.v +++ b/test_regress/t/t_tri_various.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_type.py b/test_regress/t/t_type.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_type.py +++ b/test_regress/t/t_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_type.v b/test_regress/t/t_type.v index e48807d5d..486f1940c 100644 --- a/test_regress/t/t_type.v +++ b/test_regress/t/t_type.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_type_array.py b/test_regress/t/t_type_array.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_type_array.py +++ b/test_regress/t/t_type_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_type_array.v b/test_regress/t/t_type_array.v index 2c38d64b2..ad29322c2 100644 --- a/test_regress/t/t_type_array.v +++ b/test_regress/t/t_type_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_type_compare.py b/test_regress/t/t_type_compare.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_type_compare.py +++ b/test_regress/t/t_type_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_type_compare.v b/test_regress/t/t_type_compare.v index a209dffee..49b519a18 100644 --- a/test_regress/t/t_type_compare.v +++ b/test_regress/t/t_type_compare.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module Sub #(parameter type T = type(logic[11:0])); diff --git a/test_regress/t/t_type_compare_bad.py b/test_regress/t/t_type_compare_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_type_compare_bad.py +++ b/test_regress/t/t_type_compare_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_type_compare_bad.v b/test_regress/t/t_type_compare_bad.v index 1b22fabb3..01a01402b 100644 --- a/test_regress/t/t_type_compare_bad.v +++ b/test_regress/t/t_type_compare_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_type_expression_compare.py b/test_regress/t/t_type_expression_compare.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_type_expression_compare.py +++ b/test_regress/t/t_type_expression_compare.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_type_expression_compare.v b/test_regress/t/t_type_expression_compare.v index d94e9fc70..023f289b5 100644 --- a/test_regress/t/t_type_expression_compare.v +++ b/test_regress/t/t_type_expression_compare.v @@ -1,15 +1,15 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 typedef int Int_T; module t; initial begin - Int_T value1 = 7; - int value2 = 13; + automatic Int_T value1 = 7; + automatic int value2 = 13; real r; if (type(value1) != type(value2)) $stop; if (type(value1 + value2) != type(value2 + 18)) $stop; diff --git a/test_regress/t/t_type_match.py b/test_regress/t/t_type_match.py index c37bc018e..30ee5e479 100755 --- a/test_regress/t/t_type_match.py +++ b/test_regress/t/t_type_match.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_type_match.v b/test_regress/t/t_type_match.v index b6560e3ce..c792bbdf5 100644 --- a/test_regress/t/t_type_match.v +++ b/test_regress/t/t_type_match.v @@ -5,8 +5,8 @@ // // Generated C++ code should compile. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Pawel Jewstafjew (Pawel.Jewstafjew@gmail.com). +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Pawel Jewstafjew // SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_type_non_type.py b/test_regress/t/t_type_non_type.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_type_non_type.py +++ b/test_regress/t/t_type_non_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_type_non_type.v b/test_regress/t/t_type_non_type.v index 2aca3bc16..22137ddb0 100644 --- a/test_regress/t/t_type_non_type.v +++ b/test_regress/t/t_type_non_type.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Cls; diff --git a/test_regress/t/t_type_param.py b/test_regress/t/t_type_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_type_param.py +++ b/test_regress/t/t_type_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_type_param.v b/test_regress/t/t_type_param.v index 61ca69b19..ed22d9d21 100644 --- a/test_regress/t/t_type_param.v +++ b/test_regress/t/t_type_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Todd Strader // SPDX-License-Identifier: CC0-1.0 package some_package; diff --git a/test_regress/t/t_type_param_circ_bad.out b/test_regress/t/t_type_param_circ_bad.out index fdc98f7cd..58dc74892 100644 --- a/test_regress/t/t_type_param_circ_bad.out +++ b/test_regress/t/t_type_param_circ_bad.out @@ -1,6 +1,10 @@ -%Error: t/t_type_param_circ_bad.v:14:22: Recursive type definition, or over 1000 types deep +%Error: t/t_type_param_circ_bad.v:14:22: Recursive type definition : ... note: In instance 't' + t/t_type_param_circ_bad.v:14:22: ... Type chain: PARAMTYPEDTYPE 'SZ' 14 | # (parameter type SZ = SZ) | ^~ + t/t_type_param_circ_bad.v:14:27: ... Type chain: REFDTYPE 'SZ' + 14 | # (parameter type SZ = SZ) + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_type_param_circ_bad.py b/test_regress/t/t_type_param_circ_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_type_param_circ_bad.py +++ b/test_regress/t/t_type_param_circ_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_type_param_circ_bad.v b/test_regress/t/t_type_param_circ_bad.v index 9eea5887a..9def0a114 100644 --- a/test_regress/t/t_type_param_circ_bad.v +++ b/test_regress/t/t_type_param_circ_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_type_param_collision.py b/test_regress/t/t_type_param_collision.py index a4337c4ed..663223516 100755 --- a/test_regress/t/t_type_param_collision.py +++ b/test_regress/t/t_type_param_collision.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef.py b/test_regress/t/t_typedef.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_typedef.py +++ b/test_regress/t/t_typedef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef.v b/test_regress/t/t_typedef.v index 0ea3d25de..59384da9d 100644 --- a/test_regress/t/t_typedef.v +++ b/test_regress/t/t_typedef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_typedef_array.py b/test_regress/t/t_typedef_array.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_typedef_array.py +++ b/test_regress/t/t_typedef_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_array.v b/test_regress/t/t_typedef_array.v index 8fe08ffcc..f640d1a01 100644 --- a/test_regress/t/t_typedef_array.v +++ b/test_regress/t/t_typedef_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by James Pallister. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 James Pallister // SPDX-License-Identifier: CC0-1.0 typedef logic logic_alias_t; diff --git a/test_regress/t/t_typedef_circ_bad.py b/test_regress/t/t_typedef_circ_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_typedef_circ_bad.py +++ b/test_regress/t/t_typedef_circ_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_circ_bad.v b/test_regress/t/t_typedef_circ_bad.v index 937eb24bb..1669b5c86 100644 --- a/test_regress/t/t_typedef_circ_bad.v +++ b/test_regress/t/t_typedef_circ_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef a_t; diff --git a/test_regress/t/t_typedef_consistency_0.py b/test_regress/t/t_typedef_consistency_0.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_typedef_consistency_0.py +++ b/test_regress/t/t_typedef_consistency_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_consistency_0.v b/test_regress/t/t_typedef_consistency_0.v index 14da498a0..e8b1adad7 100644 --- a/test_regress/t/t_typedef_consistency_0.v +++ b/test_regress/t/t_typedef_consistency_0.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_typedef_fwd.py b/test_regress/t/t_typedef_fwd.py index cca4c9e73..d6d35e7fd 100755 --- a/test_regress/t/t_typedef_fwd.py +++ b/test_regress/t/t_typedef_fwd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_fwd.v b/test_regress/t/t_typedef_fwd.v index c7d16e283..dc8df8177 100644 --- a/test_regress/t/t_typedef_fwd.v +++ b/test_regress/t/t_typedef_fwd.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package P; diff --git a/test_regress/t/t_typedef_fwd_bad.py b/test_regress/t/t_typedef_fwd_bad.py index cc0ca5d61..45e735d36 100755 --- a/test_regress/t/t_typedef_fwd_bad.py +++ b/test_regress/t/t_typedef_fwd_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_fwd_class.py b/test_regress/t/t_typedef_fwd_class.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_typedef_fwd_class.py +++ b/test_regress/t/t_typedef_fwd_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_fwd_class.v b/test_regress/t/t_typedef_fwd_class.v index 67ae2e046..68992970f 100644 --- a/test_regress/t/t_typedef_fwd_class.v +++ b/test_regress/t/t_typedef_fwd_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef logic [3:0] T; diff --git a/test_regress/t/t_typedef_fwd_nested.py b/test_regress/t/t_typedef_fwd_nested.py index dbdaf4551..1a93d5310 100755 --- a/test_regress/t/t_typedef_fwd_nested.py +++ b/test_regress/t/t_typedef_fwd_nested.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_fwd_nested.v b/test_regress/t/t_typedef_fwd_nested.v index e6e99040b..7c330cbba 100644 --- a/test_regress/t/t_typedef_fwd_nested.v +++ b/test_regress/t/t_typedef_fwd_nested.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 typedef class Bar; diff --git a/test_regress/t/t_typedef_id_bad.py b/test_regress/t/t_typedef_id_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_typedef_id_bad.py +++ b/test_regress/t/t_typedef_id_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_id_bad.v b/test_regress/t/t_typedef_id_bad.v index fd4482a5f..aaf60e5a6 100644 --- a/test_regress/t/t_typedef_id_bad.v +++ b/test_regress/t/t_typedef_id_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 int i; diff --git a/test_regress/t/t_typedef_iface_typedef.py b/test_regress/t/t_typedef_iface_typedef.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_typedef_iface_typedef.py +++ b/test_regress/t/t_typedef_iface_typedef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_iface_typedef.v b/test_regress/t/t_typedef_iface_typedef.v index 0331d03ef..258275225 100644 --- a/test_regress/t/t_typedef_iface_typedef.v +++ b/test_regress/t/t_typedef_iface_typedef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting diff --git a/test_regress/t/t_typedef_iface_typedef2.py b/test_regress/t/t_typedef_iface_typedef2.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_typedef_iface_typedef2.py +++ b/test_regress/t/t_typedef_iface_typedef2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_iface_typedef2.v b/test_regress/t/t_typedef_iface_typedef2.v index a43f480fc..9635acfed 100644 --- a/test_regress/t/t_typedef_iface_typedef2.v +++ b/test_regress/t/t_typedef_iface_typedef2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_typedef_iface_typedef3.py b/test_regress/t/t_typedef_iface_typedef3.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_typedef_iface_typedef3.py +++ b/test_regress/t/t_typedef_iface_typedef3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_iface_typedef3.v b/test_regress/t/t_typedef_iface_typedef3.v index 9125ef207..67f7bbe84 100644 --- a/test_regress/t/t_typedef_iface_typedef3.v +++ b/test_regress/t/t_typedef_iface_typedef3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting diff --git a/test_regress/t/t_typedef_iface_typedef4.py b/test_regress/t/t_typedef_iface_typedef4.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_typedef_iface_typedef4.py +++ b/test_regress/t/t_typedef_iface_typedef4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_iface_typedef4.v b/test_regress/t/t_typedef_iface_typedef4.v index 9899ce41f..6d112ad26 100644 --- a/test_regress/t/t_typedef_iface_typedef4.v +++ b/test_regress/t/t_typedef_iface_typedef4.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting diff --git a/test_regress/t/t_typedef_iface_typedef5.py b/test_regress/t/t_typedef_iface_typedef5.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_typedef_iface_typedef5.py +++ b/test_regress/t/t_typedef_iface_typedef5.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_iface_typedef5.v b/test_regress/t/t_typedef_iface_typedef5.v index b384185c1..d26bb9512 100644 --- a/test_regress/t/t_typedef_iface_typedef5.v +++ b/test_regress/t/t_typedef_iface_typedef5.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting diff --git a/test_regress/t/t_typedef_iface_typedef6.py b/test_regress/t/t_typedef_iface_typedef6.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_typedef_iface_typedef6.py +++ b/test_regress/t/t_typedef_iface_typedef6.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_iface_typedef6.v b/test_regress/t/t_typedef_iface_typedef6.v index 8a824fef4..d6c6a3175 100644 --- a/test_regress/t/t_typedef_iface_typedef6.v +++ b/test_regress/t/t_typedef_iface_typedef6.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // assign localparam from interface typedef, single level nesting diff --git a/test_regress/t/t_typedef_iface_typedef7.py b/test_regress/t/t_typedef_iface_typedef7.py index c6e56559a..31b1f0e53 100755 --- a/test_regress/t/t_typedef_iface_typedef7.py +++ b/test_regress/t/t_typedef_iface_typedef7.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_iface_typedef7.v b/test_regress/t/t_typedef_iface_typedef7.v index 968579e3f..b1483f683 100644 --- a/test_regress/t/t_typedef_iface_typedef7.v +++ b/test_regress/t/t_typedef_iface_typedef7.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // // Chained typedef aliases from an interface typedef diff --git a/test_regress/t/t_typedef_no_bad.py b/test_regress/t/t_typedef_no_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_typedef_no_bad.py +++ b/test_regress/t/t_typedef_no_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_no_bad.v b/test_regress/t/t_typedef_no_bad.v index 11da87f92..b6fe352db 100644 --- a/test_regress/t/t_typedef_no_bad.v +++ b/test_regress/t/t_typedef_no_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef sometype; diff --git a/test_regress/t/t_typedef_package.py b/test_regress/t/t_typedef_package.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_typedef_package.py +++ b/test_regress/t/t_typedef_package.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_package.v b/test_regress/t/t_typedef_package.v index ae40ba79b..0f2724182 100644 --- a/test_regress/t/t_typedef_package.v +++ b/test_regress/t/t_typedef_package.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Driss Hafdi. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 package pkg1; diff --git a/test_regress/t/t_typedef_param.py b/test_regress/t/t_typedef_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_typedef_param.py +++ b/test_regress/t/t_typedef_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_param.v b/test_regress/t/t_typedef_param.v index 2c3b13426..f39c8522a 100644 --- a/test_regress/t/t_typedef_param.v +++ b/test_regress/t/t_typedef_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef reg [2:0] threeansi_t; diff --git a/test_regress/t/t_typedef_param_class.py b/test_regress/t/t_typedef_param_class.py index f989a35fb..84b274f68 100755 --- a/test_regress/t/t_typedef_param_class.py +++ b/test_regress/t/t_typedef_param_class.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_param_class.v b/test_regress/t/t_typedef_param_class.v index 21a4da1ef..c21c88bbd 100644 --- a/test_regress/t/t_typedef_param_class.v +++ b/test_regress/t/t_typedef_param_class.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 class Class1 #( @@ -16,9 +16,9 @@ endclass module t; initial begin - int value0 = 7; - Class1#(Class2)::Some_type1 value1 = value0; - int value2 = value1; + automatic int value0 = 7; + automatic Class1#(Class2)::Some_type1 value1 = value0; + automatic int value2 = value1; $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_typedef_port.py b/test_regress/t/t_typedef_port.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_typedef_port.py +++ b/test_regress/t/t_typedef_port.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_port.v b/test_regress/t/t_typedef_port.v index e773027b1..4f0d0bce2 100644 --- a/test_regress/t/t_typedef_port.v +++ b/test_regress/t/t_typedef_port.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef reg [2:0] threeansi_t; diff --git a/test_regress/t/t_typedef_signed.py b/test_regress/t/t_typedef_signed.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_typedef_signed.py +++ b/test_regress/t/t_typedef_signed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_signed.v b/test_regress/t/t_typedef_signed.v index 2bab2c8f7..9d2052814 100644 --- a/test_regress/t/t_typedef_signed.v +++ b/test_regress/t/t_typedef_signed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug456 diff --git a/test_regress/t/t_typedef_unused_bad.py b/test_regress/t/t_typedef_unused_bad.py index 285f30e23..e04ce3ae5 100755 --- a/test_regress/t/t_typedef_unused_bad.py +++ b/test_regress/t/t_typedef_unused_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typedef_unused_bad.v b/test_regress/t/t_typedef_unused_bad.v index 896840cd7..4d55d3730 100644 --- a/test_regress/t/t_typedef_unused_bad.v +++ b/test_regress/t/t_typedef_unused_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef logic ok_t; diff --git a/test_regress/t/t_typename.py b/test_regress/t/t_typename.py index 1a1bebba6..82792bbb0 100755 --- a/test_regress/t/t_typename.py +++ b/test_regress/t/t_typename.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typename.v b/test_regress/t/t_typename.v index 6ba9f4930..073265842 100644 --- a/test_regress/t/t_typename.v +++ b/test_regress/t/t_typename.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_typename_min.py b/test_regress/t/t_typename_min.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_typename_min.py +++ b/test_regress/t/t_typename_min.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_typename_min.v b/test_regress/t/t_typename_min.v index 49499924f..eb02ed5dd 100644 --- a/test_regress/t/t_typename_min.v +++ b/test_regress/t/t_typename_min.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_udp_bad.out b/test_regress/t/t_udp_bad.out index e630d303f..6e235b3c5 100644 --- a/test_regress/t/t_udp_bad.out +++ b/test_regress/t/t_udp_bad.out @@ -13,6 +13,9 @@ %Error-PINNOTFOUND: t/t_udp_bad.v:10:13: Pin not found: '__pinNumber1' 10 | udp_x x (a, b); | ^ + : ... Location of instance's primitive declaration + 14 | primitive udp_x (a_bad, b, c_bad); + | ^~~~~ ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error: t/t_udp_bad.v:17:11: Multiple outputs not allowed in udp modules 17 | output c_bad; diff --git a/test_regress/t/t_udp_bad.py b/test_regress/t/t_udp_bad.py index d0a97a711..a1e666663 100755 --- a/test_regress/t/t_udp_bad.py +++ b/test_regress/t/t_udp_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_bad.v b/test_regress/t/t_udp_bad.v index d61212c02..8a9cc5b10 100644 --- a/test_regress/t/t_udp_bad.v +++ b/test_regress/t/t_udp_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_udp_bad_comb_trigger.py b/test_regress/t/t_udp_bad_comb_trigger.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_udp_bad_comb_trigger.py +++ b/test_regress/t/t_udp_bad_comb_trigger.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_bad_comb_trigger.v b/test_regress/t/t_udp_bad_comb_trigger.v old mode 100755 new mode 100644 index 302ec6f79..129ed99f5 --- a/test_regress/t/t_udp_bad_comb_trigger.v +++ b/test_regress/t/t_udp_bad_comb_trigger.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive t_gate(dout, a, b, c); diff --git a/test_regress/t/t_udp_bad_first_input.py b/test_regress/t/t_udp_bad_first_input.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_udp_bad_first_input.py +++ b/test_regress/t/t_udp_bad_first_input.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_bad_first_input.v b/test_regress/t/t_udp_bad_first_input.v old mode 100755 new mode 100644 index 2354307fd..b6ff5b160 --- a/test_regress/t/t_udp_bad_first_input.v +++ b/test_regress/t/t_udp_bad_first_input.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive t_gate(a, b, c, dout); diff --git a/test_regress/t/t_udp_bad_illegal_output.py b/test_regress/t/t_udp_bad_illegal_output.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_udp_bad_illegal_output.py +++ b/test_regress/t/t_udp_bad_illegal_output.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_bad_illegal_output.v b/test_regress/t/t_udp_bad_illegal_output.v old mode 100755 new mode 100644 index 02f1895f9..af6ee1fe1 --- a/test_regress/t/t_udp_bad_illegal_output.v +++ b/test_regress/t/t_udp_bad_illegal_output.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive t_gate_comb(dout, a, b, c); diff --git a/test_regress/t/t_udp_bad_input_num.py b/test_regress/t/t_udp_bad_input_num.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_udp_bad_input_num.py +++ b/test_regress/t/t_udp_bad_input_num.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_bad_input_num.v b/test_regress/t/t_udp_bad_input_num.v old mode 100755 new mode 100644 index bac50a163..9acb61225 --- a/test_regress/t/t_udp_bad_input_num.v +++ b/test_regress/t/t_udp_bad_input_num.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive t_gate(dout, a, b, c); diff --git a/test_regress/t/t_udp_bad_line_inputs.py b/test_regress/t/t_udp_bad_line_inputs.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_udp_bad_line_inputs.py +++ b/test_regress/t/t_udp_bad_line_inputs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_bad_line_inputs.v b/test_regress/t/t_udp_bad_line_inputs.v index 98489c285..f69b5a04b 100644 --- a/test_regress/t/t_udp_bad_line_inputs.v +++ b/test_regress/t/t_udp_bad_line_inputs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive udp_0(output o, input i); diff --git a/test_regress/t/t_udp_bad_line_outputs.py b/test_regress/t/t_udp_bad_line_outputs.py index e20848999..0e485f609 100755 --- a/test_regress/t/t_udp_bad_line_outputs.py +++ b/test_regress/t/t_udp_bad_line_outputs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_bad_line_outputs.v b/test_regress/t/t_udp_bad_line_outputs.v index 42c2186ba..cbfd4eec7 100644 --- a/test_regress/t/t_udp_bad_line_outputs.v +++ b/test_regress/t/t_udp_bad_line_outputs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive udp_1(output reg o, input i); diff --git a/test_regress/t/t_udp_bad_multi_output.py b/test_regress/t/t_udp_bad_multi_output.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_udp_bad_multi_output.py +++ b/test_regress/t/t_udp_bad_multi_output.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_bad_multi_output.v b/test_regress/t/t_udp_bad_multi_output.v old mode 100755 new mode 100644 index 690c7c6d2..296df8726 --- a/test_regress/t/t_udp_bad_multi_output.v +++ b/test_regress/t/t_udp_bad_multi_output.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive t_gate(dout1, dout2, a, b, c); diff --git a/test_regress/t/t_udp_binary.py b/test_regress/t/t_udp_binary.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_udp_binary.py +++ b/test_regress/t/t_udp_binary.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_binary.v b/test_regress/t/t_udp_binary.v index f98676a16..b3f80033e 100644 --- a/test_regress/t/t_udp_binary.v +++ b/test_regress/t/t_udp_binary.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Test that a standalone primitive can be a top level module diff --git a/test_regress/t/t_udp_binary_top.py b/test_regress/t/t_udp_binary_top.py index f33fc647b..5c55b641d 100755 --- a/test_regress/t/t_udp_binary_top.py +++ b/test_regress/t/t_udp_binary_top.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_binary_top.v b/test_regress/t/t_udp_binary_top.v index f45244d3c..0587127e0 100644 --- a/test_regress/t/t_udp_binary_top.v +++ b/test_regress/t/t_udp_binary_top.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Test that a standalone primitive can be a top level module diff --git a/test_regress/t/t_udp_delay.py b/test_regress/t/t_udp_delay.py index 055e14291..514786060 100755 --- a/test_regress/t/t_udp_delay.py +++ b/test_regress/t/t_udp_delay.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_delay.v b/test_regress/t/t_udp_delay.v index 238a514ab..e850c0bc5 100644 --- a/test_regress/t/t_udp_delay.v +++ b/test_regress/t/t_udp_delay.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive not_u(out, in); diff --git a/test_regress/t/t_udp_noname.py b/test_regress/t/t_udp_noname.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_udp_noname.py +++ b/test_regress/t/t_udp_noname.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_noname.v b/test_regress/t/t_udp_noname.v index 862a57e86..94128c664 100644 --- a/test_regress/t/t_udp_noname.v +++ b/test_regress/t/t_udp_noname.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_udp_nonsequential_x.py b/test_regress/t/t_udp_nonsequential_x.py index 9e4a474a0..7f1257b2c 100755 --- a/test_regress/t/t_udp_nonsequential_x.py +++ b/test_regress/t/t_udp_nonsequential_x.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_nonsequential_x.v b/test_regress/t/t_udp_nonsequential_x.v index d835943db..d415442c3 100644 --- a/test_regress/t/t_udp_nonsequential_x.v +++ b/test_regress/t/t_udp_nonsequential_x.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Michael Bikovitsky. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Michael Bikovitsky // SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_udp_param_bad.py b/test_regress/t/t_udp_param_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_udp_param_bad.py +++ b/test_regress/t/t_udp_param_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_param_bad.v b/test_regress/t/t_udp_param_bad.v index 8ac68827e..37e09e82b 100644 --- a/test_regress/t/t_udp_param_bad.v +++ b/test_regress/t/t_udp_param_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Anthony Donlon. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Anthony Donlon // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_udp_sequential.py b/test_regress/t/t_udp_sequential.py index 610578b91..222d55aa0 100755 --- a/test_regress/t/t_udp_sequential.py +++ b/test_regress/t/t_udp_sequential.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_sequential.v b/test_regress/t/t_udp_sequential.v index a3cfa33ac..8b86b6f7d 100644 --- a/test_regress/t/t_udp_sequential.v +++ b/test_regress/t/t_udp_sequential.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Mike Thyer. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Mike Thyer // SPDX-License-Identifier: CC0-1.0 primitive d_edge_ff (q, clock, data); diff --git a/test_regress/t/t_udp_sequential_bad.py b/test_regress/t/t_udp_sequential_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_udp_sequential_bad.py +++ b/test_regress/t/t_udp_sequential_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_sequential_bad.v b/test_regress/t/t_udp_sequential_bad.v old mode 100755 new mode 100644 index 1e26f7e5c..892a9ed09 --- a/test_regress/t/t_udp_sequential_bad.v +++ b/test_regress/t/t_udp_sequential_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive or_gate(dout, a, b, c); diff --git a/test_regress/t/t_udp_sequential_x.py b/test_regress/t/t_udp_sequential_x.py index 3ed3afcba..f3e251121 100755 --- a/test_regress/t/t_udp_sequential_x.py +++ b/test_regress/t/t_udp_sequential_x.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_sequential_x.v b/test_regress/t/t_udp_sequential_x.v index ce12aaef6..2631470f2 100644 --- a/test_regress/t/t_udp_sequential_x.v +++ b/test_regress/t/t_udp_sequential_x.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Michael Bikovitsky. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Michael Bikovitsky // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_udp_tableend_bad.py b/test_regress/t/t_udp_tableend_bad.py index a0f699e19..8d78305d6 100755 --- a/test_regress/t/t_udp_tableend_bad.py +++ b/test_regress/t/t_udp_tableend_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_tableend_bad.v b/test_regress/t/t_udp_tableend_bad.v index 6597e7be6..52034cc68 100644 --- a/test_regress/t/t_udp_tableend_bad.v +++ b/test_regress/t/t_udp_tableend_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive udp_x (a_bad, b, c_bad); diff --git a/test_regress/t/t_udp_tableeof_bad.py b/test_regress/t/t_udp_tableeof_bad.py index 12b1678d4..c2571161f 100755 --- a/test_regress/t/t_udp_tableeof_bad.py +++ b/test_regress/t/t_udp_tableeof_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_udp_tableeof_bad.v b/test_regress/t/t_udp_tableeof_bad.v index 064573395..3435716bc 100644 --- a/test_regress/t/t_udp_tableeof_bad.v +++ b/test_regress/t/t_udp_tableeof_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 primitive udp_x (a_bad, b, c_bad); diff --git a/test_regress/t/t_unbounded.py b/test_regress/t/t_unbounded.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unbounded.py +++ b/test_regress/t/t_unbounded.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unbounded.v b/test_regress/t/t_unbounded.v index a8b6d3bba..4b66ecd21 100644 --- a/test_regress/t/t_unbounded.v +++ b/test_regress/t/t_unbounded.v @@ -1,23 +1,23 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; - localparam UNB = $; - localparam int UNB2 = $; - localparam SIX = 6; + parameter int UNB /*verilator public*/ = $; + localparam int UNB2 = $; + localparam SIX = 6; - initial begin - if ($bits($isunbounded(0)) !== 1) $stop; - if ($isunbounded(0) !== 1'b0) $stop; - if ($isunbounded(SIX) !== 0) $stop; - if ($isunbounded($) !== 1) $stop; - if ($isunbounded(UNB) !== 1) $stop; - if ($isunbounded(UNB2) !== 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if ($bits($isunbounded(0)) !== 1) $stop; + if ($isunbounded(0) !== 1'b0) $stop; + if ($isunbounded(SIX) !== 0) $stop; + if ($isunbounded($) !== 1) $stop; + if ($isunbounded(UNB) !== 1) $stop; + if ($isunbounded(UNB2) !== 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_unbounded_bad.py b/test_regress/t/t_unbounded_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_unbounded_bad.py +++ b/test_regress/t/t_unbounded_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unbounded_bad.v b/test_regress/t/t_unbounded_bad.v index 7927e7bfb..c555933b5 100644 --- a/test_regress/t/t_unbounded_bad.v +++ b/test_regress/t/t_unbounded_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_unconnected.py b/test_regress/t/t_unconnected.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unconnected.py +++ b/test_regress/t/t_unconnected.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unconnected.v b/test_regress/t/t_unconnected.v index 4cce7be42..d90551318 100644 --- a/test_regress/t/t_unconnected.v +++ b/test_regress/t/t_unconnected.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_unconnected_bad.py b/test_regress/t/t_unconnected_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_unconnected_bad.py +++ b/test_regress/t/t_unconnected_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unconnected_bad.v b/test_regress/t/t_unconnected_bad.v index 46affd2f9..ebfbf29bc 100644 --- a/test_regress/t/t_unconnected_bad.v +++ b/test_regress/t/t_unconnected_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `unconnected_drive diff --git a/test_regress/t/t_unicode.py b/test_regress/t/t_unicode.py index 61dc58004..7e2787dc8 100755 --- a/test_regress/t/t_unicode.py +++ b/test_regress/t/t_unicode.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_union_hard_bad.py b/test_regress/t/t_union_hard_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_union_hard_bad.py +++ b/test_regress/t/t_union_hard_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_union_hard_bad.v b/test_regress/t/t_union_hard_bad.v index 2322a39e6..9f100e060 100644 --- a/test_regress/t/t_union_hard_bad.v +++ b/test_regress/t/t_union_hard_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_union_soft.py b/test_regress/t/t_union_soft.py index fc5a55e3f..eafe7e6e5 100755 --- a/test_regress/t/t_union_soft.py +++ b/test_regress/t/t_union_soft.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_union_soft.v b/test_regress/t/t_union_soft.v index f926fc432..972c7ba78 100644 --- a/test_regress/t/t_union_soft.v +++ b/test_regress/t/t_union_soft.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_union_unpacked.py b/test_regress/t/t_union_unpacked.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_union_unpacked.py +++ b/test_regress/t/t_union_unpacked.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_union_unpacked.v b/test_regress/t/t_union_unpacked.v index 817e69541..de0971571 100644 --- a/test_regress/t/t_union_unpacked.v +++ b/test_regress/t/t_union_unpacked.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_uniqueif.py b/test_regress/t/t_uniqueif.py index d97aaff01..cae36a498 100755 --- a/test_regress/t/t_uniqueif.py +++ b/test_regress/t/t_uniqueif.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_uniqueif.v b/test_regress/t/t_uniqueif.v index ba1ee4555..6270cba1c 100644 --- a/test_regress/t/t_uniqueif.v +++ b/test_regress/t/t_uniqueif.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_uniqueif_else.py b/test_regress/t/t_uniqueif_else.py index ac142fe63..4caa0e109 100755 --- a/test_regress/t/t_uniqueif_else.py +++ b/test_regress/t/t_uniqueif_else.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_uniqueif_else.v b/test_regress/t/t_uniqueif_else.v index 77ea0c5ff..2cd329481 100644 --- a/test_regress/t/t_uniqueif_else.v +++ b/test_regress/t/t_uniqueif_else.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_uniqueif_fail1.py b/test_regress/t/t_uniqueif_fail1.py index 8eeaeefee..53445c3da 100755 --- a/test_regress/t/t_uniqueif_fail1.py +++ b/test_regress/t/t_uniqueif_fail1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_uniqueif_fail2.py b/test_regress/t/t_uniqueif_fail2.py index f94dedc48..d0e23fcfa 100755 --- a/test_regress/t/t_uniqueif_fail2.py +++ b/test_regress/t/t_uniqueif_fail2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_uniqueif_fail3.py b/test_regress/t/t_uniqueif_fail3.py index e52b3e975..0442aefd9 100755 --- a/test_regress/t/t_uniqueif_fail3.py +++ b/test_regress/t/t_uniqueif_fail3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_uniqueif_fail4.py b/test_regress/t/t_uniqueif_fail4.py index ee0e4f768..787d96e16 100755 --- a/test_regress/t/t_uniqueif_fail4.py +++ b/test_regress/t/t_uniqueif_fail4.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_array.py b/test_regress/t/t_unopt_array.py index 51e61aa39..0bed5b40c 100755 --- a/test_regress/t/t_unopt_array.py +++ b/test_regress/t/t_unopt_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_array.v b/test_regress/t/t_unopt_array.v index 899315663..9908764c6 100644 --- a/test_regress/t/t_unopt_array.v +++ b/test_regress/t/t_unopt_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unopt_array_csplit.py b/test_regress/t/t_unopt_array_csplit.py index 3d22d22a4..5de52004f 100755 --- a/test_regress/t/t_unopt_array_csplit.py +++ b/test_regress/t/t_unopt_array_csplit.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_array_typedef.py b/test_regress/t/t_unopt_array_typedef.py index fb7da0974..58c78ca86 100755 --- a/test_regress/t/t_unopt_array_typedef.py +++ b/test_regress/t/t_unopt_array_typedef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_bound.py b/test_regress/t/t_unopt_bound.py index dc6cab445..c02254607 100755 --- a/test_regress/t/t_unopt_bound.py +++ b/test_regress/t/t_unopt_bound.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_bound.v b/test_regress/t/t_unopt_bound.v index 7c708c035..0c93555e6 100644 --- a/test_regress/t/t_unopt_bound.v +++ b/test_regress/t/t_unopt_bound.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jue Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jue Xu // SPDX-License-Identifier: CC0-1.0 // bug630 diff --git a/test_regress/t/t_unopt_combo.py b/test_regress/t/t_unopt_combo.py index 9027b0470..b576750b6 100755 --- a/test_regress/t/t_unopt_combo.py +++ b/test_regress/t/t_unopt_combo.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_combo.v b/test_regress/t/t_unopt_combo.v index 6620e7459..961f0bb3d 100644 --- a/test_regress/t/t_unopt_combo.v +++ b/test_regress/t/t_unopt_combo.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unopt_combo.vlt b/test_regress/t/t_unopt_combo.vlt index 5231aa4e6..553c4be92 100644 --- a/test_regress/t/t_unopt_combo.vlt +++ b/test_regress/t/t_unopt_combo.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_unopt_combo_bad.py b/test_regress/t/t_unopt_combo_bad.py index c659a17b7..d863f5a00 100755 --- a/test_regress/t/t_unopt_combo_bad.py +++ b/test_regress/t/t_unopt_combo_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_combo_isolate.py b/test_regress/t/t_unopt_combo_isolate.py index 6fa0cf8b4..f35574a26 100755 --- a/test_regress/t/t_unopt_combo_isolate.py +++ b/test_regress/t/t_unopt_combo_isolate.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_combo_isolate.vlt b/test_regress/t/t_unopt_combo_isolate.vlt index 1fe38e10e..c21284e2b 100644 --- a/test_regress/t/t_unopt_combo_isolate.vlt +++ b/test_regress/t/t_unopt_combo_isolate.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_unopt_combo_isolate_vlt.py b/test_regress/t/t_unopt_combo_isolate_vlt.py index a30b5b105..803550765 100755 --- a/test_regress/t/t_unopt_combo_isolate_vlt.py +++ b/test_regress/t/t_unopt_combo_isolate_vlt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_combo_waive.py b/test_regress/t/t_unopt_combo_waive.py index 34a421ec1..c4824f4df 100755 --- a/test_regress/t/t_unopt_combo_waive.py +++ b/test_regress/t/t_unopt_combo_waive.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_converge.v b/test_regress/t/t_unopt_converge.v index 702c0f32a..324d6fdf8 100644 --- a/test_regress/t/t_unopt_converge.v +++ b/test_regress/t/t_unopt_converge.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unopt_converge_initial.v b/test_regress/t/t_unopt_converge_initial.v index abfc6f32e..3fea89cef 100644 --- a/test_regress/t/t_unopt_converge_initial.v +++ b/test_regress/t/t_unopt_converge_initial.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unopt_converge_initial_run_bad.out b/test_regress/t/t_unopt_converge_initial_run_bad.out index 5c449acfb..aa074a750 100644 --- a/test_regress/t/t_unopt_converge_initial_run_bad.out +++ b/test_regress/t/t_unopt_converge_initial_run_bad.out @@ -1,3 +1,3 @@ -V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] x) -%Error: t/t_unopt_converge_initial.v:7: Settle region did not converge after 100 tries +%Error-DIDNOTCONVERGE: t/t_unopt_converge_initial.v:7: Settle region did not converge after '--converge-limit' of 100 tries Aborting... diff --git a/test_regress/t/t_unopt_converge_initial_run_bad.py b/test_regress/t/t_unopt_converge_initial_run_bad.py index eaa85d927..f6be1d6bb 100755 --- a/test_regress/t/t_unopt_converge_initial_run_bad.py +++ b/test_regress/t/t_unopt_converge_initial_run_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_converge_ndbg_bad.out b/test_regress/t/t_unopt_converge_ndbg_bad.out index d8b1afa04..53f00719b 100644 --- a/test_regress/t/t_unopt_converge_ndbg_bad.out +++ b/test_regress/t/t_unopt_converge_ndbg_bad.out @@ -1,2 +1,2 @@ -%Error: t/t_unopt_converge.v:7: Settle region did not converge after 100 tries +%Error-DIDNOTCONVERGE: t/t_unopt_converge.v:7: Settle region did not converge after '--converge-limit' of 100 tries Aborting... diff --git a/test_regress/t/t_unopt_converge_ndbg_bad.py b/test_regress/t/t_unopt_converge_ndbg_bad.py index fbc3822fe..e5807fe72 100755 --- a/test_regress/t/t_unopt_converge_ndbg_bad.py +++ b/test_regress/t/t_unopt_converge_ndbg_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_converge_print_bad.out b/test_regress/t/t_unopt_converge_print_bad.out index 29a108c3c..555b85b4a 100644 --- a/test_regress/t/t_unopt_converge_print_bad.out +++ b/test_regress/t/t_unopt_converge_print_bad.out @@ -1,3 +1,3 @@ -V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] x) -%Error: t/t_unopt_converge.v:7: Settle region did not converge after 100 tries +%Error-DIDNOTCONVERGE: t/t_unopt_converge.v:7: Settle region did not converge after '--converge-limit' of 100 tries Aborting... diff --git a/test_regress/t/t_unopt_converge_print_bad.py b/test_regress/t/t_unopt_converge_print_bad.py index ac1bfd49d..155d7dc95 100755 --- a/test_regress/t/t_unopt_converge_print_bad.py +++ b/test_regress/t/t_unopt_converge_print_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_converge_run_bad.out b/test_regress/t/t_unopt_converge_run_bad.out index aad3c80e0..7d2e6d461 100644 --- a/test_regress/t/t_unopt_converge_run_bad.out +++ b/test_regress/t/t_unopt_converge_run_bad.out @@ -1,3 +1,3 @@ -V{t#,#} 'stl' region trigger index 0 is active: @([hybrid] x) -%Error: t/t_unopt_converge.v:7: Settle region did not converge after 5 tries +%Error-DIDNOTCONVERGE: t/t_unopt_converge.v:7: Settle region did not converge after '--converge-limit' of 5 tries Aborting... diff --git a/test_regress/t/t_unopt_converge_run_bad.py b/test_regress/t/t_unopt_converge_run_bad.py index 5db39f3c4..367ecb192 100755 --- a/test_regress/t/t_unopt_converge_run_bad.py +++ b/test_regress/t/t_unopt_converge_run_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unopt_converge_unopt_bad.py b/test_regress/t/t_unopt_converge_unopt_bad.py index 75751ea27..02162c7a9 100755 --- a/test_regress/t/t_unopt_converge_unopt_bad.py +++ b/test_regress/t/t_unopt_converge_unopt_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unoptflat_simple.v b/test_regress/t/t_unoptflat_simple.v index 2198ae1b8..72b31227e 100644 --- a/test_regress/t/t_unoptflat_simple.v +++ b/test_regress/t/t_unoptflat_simple.v @@ -2,8 +2,8 @@ // // Simple demonstration of an UNOPTFLAT combinatorial loop, using just 2 bits. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unoptflat_simple_2.v b/test_regress/t/t_unoptflat_simple_2.v index b455b1469..cf72d6643 100644 --- a/test_regress/t/t_unoptflat_simple_2.v +++ b/test_regress/t/t_unoptflat_simple_2.v @@ -2,8 +2,8 @@ // // Simple demonstration of an UNOPTFLAT combinatorial loop, using 3 bits. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unoptflat_simple_2_bad.py b/test_regress/t/t_unoptflat_simple_2_bad.py index 6ed146135..43b3725ee 100755 --- a/test_regress/t/t_unoptflat_simple_2_bad.py +++ b/test_regress/t/t_unoptflat_simple_2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -14,7 +14,7 @@ test.top_filename = "t/t_unoptflat_simple_2.v" # Compile only test.compile(verilator_flags3=[], - verilator_flags2=["--report-unoptflat", "-fno-dfg"], + verilator_flags2=["--report-unoptflat", "-fno-dfg", "--dumpi-V3SchedAcyclic", "6"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_unoptflat_simple_3.v b/test_regress/t/t_unoptflat_simple_3.v index f275a2e02..55eae8aa5 100644 --- a/test_regress/t/t_unoptflat_simple_3.v +++ b/test_regress/t/t_unoptflat_simple_3.v @@ -3,8 +3,8 @@ // Demonstration of an UNOPTFLAT combinatorial loop using 3 bits and looping // through 2 sub-modules. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jeremy Bennett. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jeremy Bennett // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unoptflat_simple_3_bad.py b/test_regress/t/t_unoptflat_simple_3_bad.py index 3f1eae376..0ad46840f 100755 --- a/test_regress/t/t_unoptflat_simple_3_bad.py +++ b/test_regress/t/t_unoptflat_simple_3_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unoptflat_simple_bad.py b/test_regress/t/t_unoptflat_simple_bad.py index 45a8f5331..3e1c35038 100755 --- a/test_regress/t/t_unoptflat_simple_bad.py +++ b/test_regress/t/t_unoptflat_simple_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpack_array_direct_assignment.py b/test_regress/t/t_unpack_array_direct_assignment.py index dd7cd31de..f290b6a69 100755 --- a/test_regress/t/t_unpack_array_direct_assignment.py +++ b/test_regress/t/t_unpack_array_direct_assignment.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpack_array_no_expand.py b/test_regress/t/t_unpack_array_no_expand.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unpack_array_no_expand.py +++ b/test_regress/t/t_unpack_array_no_expand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpack_array_no_expand.v b/test_regress/t/t_unpack_array_no_expand.v index 04e83813d..9bbd61ed0 100644 --- a/test_regress/t/t_unpack_array_no_expand.v +++ b/test_regress/t/t_unpack_array_no_expand.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_unpacked_array_order.py b/test_regress/t/t_unpacked_array_order.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unpacked_array_order.py +++ b/test_regress/t/t_unpacked_array_order.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_array_order.v b/test_regress/t/t_unpacked_array_order.v index adee38eec..d37fa7aa7 100644 --- a/test_regress/t/t_unpacked_array_order.v +++ b/test_regress/t/t_unpacked_array_order.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Duraid Madina. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Duraid Madina // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unpacked_array_p_fmt.py b/test_regress/t/t_unpacked_array_p_fmt.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_unpacked_array_p_fmt.py +++ b/test_regress/t/t_unpacked_array_p_fmt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_array_p_fmt.v b/test_regress/t/t_unpacked_array_p_fmt.v index da364084c..b04ad1586 100644 --- a/test_regress/t/t_unpacked_array_p_fmt.v +++ b/test_regress/t/t_unpacked_array_p_fmt.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_unpacked_concat.py b/test_regress/t/t_unpacked_concat.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unpacked_concat.py +++ b/test_regress/t/t_unpacked_concat.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_concat.v b/test_regress/t/t_unpacked_concat.v index fe1b06ddb..f78b44540 100644 --- a/test_regress/t/t_unpacked_concat.v +++ b/test_regress/t/t_unpacked_concat.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Yutetsu TAKATSUKASA. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_unpacked_concat_bad.py b/test_regress/t/t_unpacked_concat_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_unpacked_concat_bad.py +++ b/test_regress/t/t_unpacked_concat_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_concat_bad.v b/test_regress/t/t_unpacked_concat_bad.v index 3e947f5f9..905760dbb 100644 --- a/test_regress/t/t_unpacked_concat_bad.v +++ b/test_regress/t/t_unpacked_concat_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_unpacked_concat_bad2.py b/test_regress/t/t_unpacked_concat_bad2.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_unpacked_concat_bad2.py +++ b/test_regress/t/t_unpacked_concat_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_concat_bad2.v b/test_regress/t/t_unpacked_concat_bad2.v index 8f40928ec..420333134 100644 --- a/test_regress/t/t_unpacked_concat_bad2.v +++ b/test_regress/t/t_unpacked_concat_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Yutetsu TAKATSUKASA. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_unpacked_concat_bad3.py b/test_regress/t/t_unpacked_concat_bad3.py index 88e1a07b1..0a3fb15f2 100755 --- a/test_regress/t/t_unpacked_concat_bad3.py +++ b/test_regress/t/t_unpacked_concat_bad3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_concat_bad3.v b/test_regress/t/t_unpacked_concat_bad3.v index abc818c05..6ac6eebd8 100644 --- a/test_regress/t/t_unpacked_concat_bad3.v +++ b/test_regress/t/t_unpacked_concat_bad3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_unpacked_init.py b/test_regress/t/t_unpacked_init.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unpacked_init.py +++ b/test_regress/t/t_unpacked_init.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_init.v b/test_regress/t/t_unpacked_init.v index 6a09955a7..a233e26b2 100644 --- a/test_regress/t/t_unpacked_init.v +++ b/test_regress/t/t_unpacked_init.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_unpacked_slice.py b/test_regress/t/t_unpacked_slice.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unpacked_slice.py +++ b/test_regress/t/t_unpacked_slice.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_slice.v b/test_regress/t/t_unpacked_slice.v index 5a899733e..24bcb5dec 100644 --- a/test_regress/t/t_unpacked_slice.v +++ b/test_regress/t/t_unpacked_slice.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_unpacked_slice_range.py b/test_regress/t/t_unpacked_slice_range.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unpacked_slice_range.py +++ b/test_regress/t/t_unpacked_slice_range.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_slice_range.v b/test_regress/t/t_unpacked_slice_range.v index 1e431425a..9d31e3359 100644 --- a/test_regress/t/t_unpacked_slice_range.v +++ b/test_regress/t/t_unpacked_slice_range.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Yutetsu TAKATSUKASA +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Yutetsu TAKATSUKASA // SPDX-License-Identifier: Unlicense module t ( diff --git a/test_regress/t/t_unpacked_str_init.py b/test_regress/t/t_unpacked_str_init.py index e77872b79..5e011058b 100755 --- a/test_regress/t/t_unpacked_str_init.py +++ b/test_regress/t/t_unpacked_str_init.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_str_init.v b/test_regress/t/t_unpacked_str_init.v index d7bce5f71..114c04d89 100644 --- a/test_regress/t/t_unpacked_str_init.v +++ b/test_regress/t/t_unpacked_str_init.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 package pkg; diff --git a/test_regress/t/t_unpacked_str_init2.py b/test_regress/t/t_unpacked_str_init2.py index ab5dca066..ed8db10e9 100755 --- a/test_regress/t/t_unpacked_str_init2.py +++ b/test_regress/t/t_unpacked_str_init2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_str_init2.v b/test_regress/t/t_unpacked_str_init2.v index ea164825f..11a7dc7b4 100644 --- a/test_regress/t/t_unpacked_str_init2.v +++ b/test_regress/t/t_unpacked_str_init2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // issue2895 diff --git a/test_regress/t/t_unpacked_str_pair.py b/test_regress/t/t_unpacked_str_pair.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unpacked_str_pair.py +++ b/test_regress/t/t_unpacked_str_pair.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_str_pair.v b/test_regress/t/t_unpacked_str_pair.v index 27da57f37..60b68735b 100644 --- a/test_regress/t/t_unpacked_str_pair.v +++ b/test_regress/t/t_unpacked_str_pair.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; @@ -37,8 +37,8 @@ module t; endfunction initial begin - string raw_filter = "parta-partb"; - filter_expression_parts_t parts = get_filter_expression_parts(raw_filter); + automatic string raw_filter = "parta-partb"; + automatic filter_expression_parts_t parts = get_filter_expression_parts(raw_filter); $display("%p", parts); if (parts.positive != "parta") $stop; if (parts.negative != "partb") $stop; diff --git a/test_regress/t/t_unpacked_struct_eq.py b/test_regress/t/t_unpacked_struct_eq.py index 671072f97..93e1f30e1 100755 --- a/test_regress/t/t_unpacked_struct_eq.py +++ b/test_regress/t/t_unpacked_struct_eq.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_struct_eq.v b/test_regress/t/t_unpacked_struct_eq.v index 2394909f5..6f656dea9 100644 --- a/test_regress/t/t_unpacked_struct_eq.v +++ b/test_regress/t/t_unpacked_struct_eq.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_unpacked_struct_redef.py b/test_regress/t/t_unpacked_struct_redef.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unpacked_struct_redef.py +++ b/test_regress/t/t_unpacked_struct_redef.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_struct_redef.v b/test_regress/t/t_unpacked_struct_redef.v index 931177607..2ad084b83 100644 --- a/test_regress/t/t_unpacked_struct_redef.v +++ b/test_regress/t/t_unpacked_struct_redef.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Class#(parameter WIDTH); diff --git a/test_regress/t/t_unpacked_struct_sel.py b/test_regress/t/t_unpacked_struct_sel.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unpacked_struct_sel.py +++ b/test_regress/t/t_unpacked_struct_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_struct_sel.v b/test_regress/t/t_unpacked_struct_sel.v index acdfcc328..db59b70eb 100644 --- a/test_regress/t/t_unpacked_struct_sel.v +++ b/test_regress/t/t_unpacked_struct_sel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 typedef struct { diff --git a/test_regress/t/t_unpacked_to_packed_param.py b/test_regress/t/t_unpacked_to_packed_param.py index 0e36f03cc..db898a84c 100755 --- a/test_regress/t/t_unpacked_to_packed_param.py +++ b/test_regress/t/t_unpacked_to_packed_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_to_packed_param.v b/test_regress/t/t_unpacked_to_packed_param.v index f8db8786b..69a37d234 100644 --- a/test_regress/t/t_unpacked_to_packed_param.v +++ b/test_regress/t/t_unpacked_to_packed_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Confirm x randomization stability // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unpacked_to_queue.py b/test_regress/t/t_unpacked_to_queue.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unpacked_to_queue.py +++ b/test_regress/t/t_unpacked_to_queue.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_to_queue.v b/test_regress/t/t_unpacked_to_queue.v index 302c2d537..fdd4e99dd 100644 --- a/test_regress/t/t_unpacked_to_queue.v +++ b/test_regress/t/t_unpacked_to_queue.v @@ -1,8 +1,8 @@ // DESCRIPTION: Verilator: Casting queues and dynamic arrays // into queues as function arguments // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_unpacked_wide_unknown.py b/test_regress/t/t_unpacked_wide_unknown.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_unpacked_wide_unknown.py +++ b/test_regress/t/t_unpacked_wide_unknown.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unpacked_wide_unknown.v b/test_regress/t/t_unpacked_wide_unknown.v index e9a8f4eae..12cdedeaa 100644 --- a/test_regress/t/t_unpacked_wide_unknown.v +++ b/test_regress/t/t_unpacked_wide_unknown.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef struct packed { diff --git a/test_regress/t/t_unroll_automatic_task_fork.py b/test_regress/t/t_unroll_automatic_task_fork.py index d2498e873..7d7bce1b7 100755 --- a/test_regress/t/t_unroll_automatic_task_fork.py +++ b/test_regress/t/t_unroll_automatic_task_fork.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_automatic_task_fork.v b/test_regress/t/t_unroll_automatic_task_fork.v index 60a2b7045..b479a1dd1 100644 --- a/test_regress/t/t_unroll_automatic_task_fork.v +++ b/test_regress/t/t_unroll_automatic_task_fork.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Targets issue 6194 diff --git a/test_regress/t/t_unroll_complexcond.py b/test_regress/t/t_unroll_complexcond.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unroll_complexcond.py +++ b/test_regress/t/t_unroll_complexcond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_complexcond.v b/test_regress/t/t_unroll_complexcond.v index 6857616c9..535067837 100644 --- a/test_regress/t/t_unroll_complexcond.v +++ b/test_regress/t/t_unroll_complexcond.v @@ -4,8 +4,8 @@ // is actually caused by not being able to unroll the for loop. // // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Jie Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2013 Jie Xu // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unroll_delay.py b/test_regress/t/t_unroll_delay.py index 340ad8afb..94e38f5e5 100755 --- a/test_regress/t/t_unroll_delay.py +++ b/test_regress/t/t_unroll_delay.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_delay.v b/test_regress/t/t_unroll_delay.v index 778e99980..59985b851 100644 --- a/test_regress/t/t_unroll_delay.v +++ b/test_regress/t/t_unroll_delay.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_unroll_forfor.py b/test_regress/t/t_unroll_forfor.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unroll_forfor.py +++ b/test_regress/t/t_unroll_forfor.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_forfor.v b/test_regress/t/t_unroll_forfor.v index 972620b1a..20aed5e4a 100644 --- a/test_regress/t/t_unroll_forfor.v +++ b/test_regress/t/t_unroll_forfor.v @@ -3,8 +3,8 @@ // This files is used to generated the following error: // %Error: Internal Error: t/t_unroll_forfor.v:27: ../V3Simulate.h:177: No value found for node. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Jan Egil Ruud. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Jan Egil Ruud // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unroll_genf.py b/test_regress/t/t_unroll_genf.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unroll_genf.py +++ b/test_regress/t/t_unroll_genf.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_genf.v b/test_regress/t/t_unroll_genf.v index d1c0b459f..4ddabf1f2 100644 --- a/test_regress/t/t_unroll_genf.v +++ b/test_regress/t/t_unroll_genf.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 //bug830 diff --git a/test_regress/t/t_unroll_nested.py b/test_regress/t/t_unroll_nested.py index 15f66fc8d..d0331a036 100755 --- a/test_regress/t/t_unroll_nested.py +++ b/test_regress/t/t_unroll_nested.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_nested.v b/test_regress/t/t_unroll_nested.v index 652568b22..5cecb2126 100644 --- a/test_regress/t/t_unroll_nested.v +++ b/test_regress/t/t_unroll_nested.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifndef VERILATOR diff --git a/test_regress/t/t_unroll_nested_param.py b/test_regress/t/t_unroll_nested_param.py index 7de8d399e..4db3c5fd1 100755 --- a/test_regress/t/t_unroll_nested_param.py +++ b/test_regress/t/t_unroll_nested_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_nested_param.v b/test_regress/t/t_unroll_nested_param.v index 52ae975f8..8bdaad0b9 100644 --- a/test_regress/t/t_unroll_nested_param.v +++ b/test_regress/t/t_unroll_nested_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_unroll_nested_unroll.py b/test_regress/t/t_unroll_nested_unroll.py index c47ce67e5..d058def07 100755 --- a/test_regress/t/t_unroll_nested_unroll.py +++ b/test_regress/t/t_unroll_nested_unroll.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_pragma.v b/test_regress/t/t_unroll_pragma.v index 52bd062b0..281caf8b4 100644 --- a/test_regress/t/t_unroll_pragma.v +++ b/test_regress/t/t_unroll_pragma.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef TEST_DISABLE diff --git a/test_regress/t/t_unroll_pragma_disable.py b/test_regress/t/t_unroll_pragma_disable.py index d385bac05..18e48d129 100755 --- a/test_regress/t/t_unroll_pragma_disable.py +++ b/test_regress/t/t_unroll_pragma_disable.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_pragma_full.py b/test_regress/t/t_unroll_pragma_full.py index 653d6e8dd..135ea9cd7 100755 --- a/test_regress/t/t_unroll_pragma_full.py +++ b/test_regress/t/t_unroll_pragma_full.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_pragma_none.py b/test_regress/t/t_unroll_pragma_none.py index 6ba506a65..24144ca3f 100755 --- a/test_regress/t/t_unroll_pragma_none.py +++ b/test_regress/t/t_unroll_pragma_none.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_signed.py b/test_regress/t/t_unroll_signed.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_unroll_signed.py +++ b/test_regress/t/t_unroll_signed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_signed.v b/test_regress/t/t_unroll_signed.v index 72e910314..68347998c 100644 --- a/test_regress/t/t_unroll_signed.v +++ b/test_regress/t/t_unroll_signed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_unroll_stmt.py b/test_regress/t/t_unroll_stmt.py index 428b44f21..d7b6c0bfe 100755 --- a/test_regress/t/t_unroll_stmt.py +++ b/test_regress/t/t_unroll_stmt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_stmt.v b/test_regress/t/t_unroll_stmt.v index d6e7e1a8c..2b651df4b 100644 --- a/test_regress/t/t_unroll_stmt.v +++ b/test_regress/t/t_unroll_stmt.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_unroll_unopt_io.py b/test_regress/t/t_unroll_unopt_io.py index af1f37c0c..13b7a55a0 100755 --- a/test_regress/t/t_unroll_unopt_io.py +++ b/test_regress/t/t_unroll_unopt_io.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_unroll_unopt_io.v b/test_regress/t/t_unroll_unopt_io.v index fe6390b24..22135915a 100644 --- a/test_regress/t/t_unroll_unopt_io.v +++ b/test_regress/t/t_unroll_unopt_io.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_upd_nonsequential.py b/test_regress/t/t_upd_nonsequential.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_upd_nonsequential.py +++ b/test_regress/t/t_upd_nonsequential.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_upd_nonsequential.v b/test_regress/t/t_upd_nonsequential.v old mode 100755 new mode 100644 index b4dba4877..bdb5b1d80 --- a/test_regress/t/t_upd_nonsequential.v +++ b/test_regress/t/t_upd_nonsequential.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Mike Thyer. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Mike Thyer // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_urandom.py b/test_regress/t/t_urandom.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_urandom.py +++ b/test_regress/t/t_urandom.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_urandom.v b/test_regress/t/t_urandom.v index e8a1bc5c6..84fab0440 100644 --- a/test_regress/t/t_urandom.v +++ b/test_regress/t/t_urandom.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Methods defined by IEEE: diff --git a/test_regress/t/t_user_type_xassign.py b/test_regress/t/t_user_type_xassign.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_user_type_xassign.py +++ b/test_regress/t/t_user_type_xassign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_user_type_xassign.v b/test_regress/t/t_user_type_xassign.v index 9cfc02cd9..70f8f5dca 100644 --- a/test_regress/t/t_user_type_xassign.v +++ b/test_regress/t/t_user_type_xassign.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Demonstrate complex user typea problem with --x-assign // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_uvm_dpi.v b/test_regress/t/t_uvm_dpi.v index 6d9de4de7..6319504c2 100644 --- a/test_regress/t/t_uvm_dpi.v +++ b/test_regress/t/t_uvm_dpi.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef T_V2020_3_1 @@ -44,153 +44,238 @@ module t; logic not_exposed; logic exposed_not_forceable; + logic [83:4] wide_dec /* verilator public*/; + // verilator lint_off ASCRANGE + logic [4:83] wide_asc /* verilator public*/; + // verilator lint_on ASCRANGE + + logic [31:0] mem1d[1:2] /* verilator public*/; + logic [31:0] mem2d[1:2][3:4] /* verilator public*/; + uvm_hdl_data_t lval; initial begin // TODO TEST: // extern const char* uvm_dpi_get_next_arg_c(int init); - //===== Exports - uvm_pkg::m__uvm_report_dpi(1, "id", "message", 1, `__FILE__, `__LINE__); + begin : t_exports + uvm_pkg::m__uvm_report_dpi(1, "id", "message", 1, `__FILE__, `__LINE__); + end - //===== Tool - s = uvm_dpi_get_tool_name_c(); - $display("uvm_dpi_get_tool_name_c() = %s", s); - `checks(s, "Verilator"); + begin : t_tool + s = uvm_dpi_get_tool_name_c(); + $display("uvm_dpi_get_tool_name_c() = %s", s); + `checks(s, "Verilator"); - s = uvm_dpi_get_tool_version_c(); - // - is so doesn't compare in .out file, in case version changes - $display("- uvm_dpi_get_tool_version_c() = %s", s); - if (s == "") $stop; + s = uvm_dpi_get_tool_version_c(); + // - is so doesn't compare in .out file, in case version changes + $display("- uvm_dpi_get_tool_version_c() = %s", s); + if (s == "") $stop; + end - //===== Regexp - $display("= uvm_re"); - h = uvm_dpi_regcomp("a.*b"); + begin : t_regexp + $display("= uvm_re"); + h = uvm_dpi_regcomp("a.*b"); - i = uvm_dpi_regexec(h, "__a_b__"); - `checkh(i, 0); - i = uvm_dpi_regexec(h, "__a_z__"); - `checkh(i, 1); + i = uvm_dpi_regexec(h, "__a_b__"); + `checkh(i, 0); + i = uvm_dpi_regexec(h, "__a_z__"); + `checkh(i, 1); + uvm_dpi_regfree(h); - uvm_dpi_regfree(h); + i = uvm_re_match("a.*b", "__a__b__"); + `checkh(i, 0); + i = uvm_re_match("a.*b", "__a__z__"); + `checkh(i, 1); - i = uvm_re_match("a.*b", "__a__b__"); - `checkh(i, 0); + s = uvm_glob_to_re("a foo bar"); + `checks(s, "/^a foo bar$/"); + end - i = uvm_re_match("a.*b", "__a__z__"); - `checkh(i, 1); - - s = uvm_glob_to_re("a foo bar"); - `checks(s, "/^a foo bar$/"); - - //===== Hier + begin : t_hier `ifdef VERILATOR - $c("Verilated::lastContextp()->fatalOnVpiError(false);"); + $c("Verilated::lastContextp()->fatalOnVpiError(false);"); `ifdef TEST_VERBOSE - $c("Verilated::scopesDump();"); + $c("Verilated::scopesDump();"); `endif `endif + end - $display("= uvm_hdl_check_path"); - i = uvm_hdl_check_path("t.__NOT_FOUND"); - `checkh(i, 0); - i = uvm_hdl_check_path("t.exposed"); - `checkh(i, 1); - i = uvm_hdl_check_path("$root.t.exposed"); - `checkh(i, 1); + begin : t_uvm_hdl_check_path + $display("= uvm_hdl_check_path"); + i = uvm_hdl_check_path("t.__NOT_FOUND"); + `checkh(i, 0); + i = uvm_hdl_check_path("t.exposed"); + `checkh(i, 1); + i = uvm_hdl_check_path("$root.t.exposed"); + `checkh(i, 1); + end - $display("= uvm_hdl_read simple variable"); - exposed = 32'hb001; - lval = '0; // Upper bits not cleared by uvm_hdl_read - i = uvm_hdl_read("t.exposed", lval); - `checkh(i, 1); - `checkh(lval[31:0], exposed); + begin : t_simple + $display("= uvm_hdl_read simple variable"); + exposed = 32'hb001; + lval = '0; // Upper bits not cleared by uvm_hdl_read + i = uvm_hdl_read("t.exposed", lval); + `checkh(i, 1); + `checkh(lval[31:0], exposed); - $display("= uvm_hdl_deposit simple variable"); - lval = 1024'hab; - i = uvm_hdl_deposit("t.exposed", lval); - `checkh(i, 1); - `checkh(exposed, 32'hab); + $display("= uvm_hdl_deposit simple variable"); + lval = 1024'hab; + i = uvm_hdl_deposit("t.exposed", lval); + `checkh(i, 1); + `checkh(exposed, 32'hab); - $display("= uvm_hdl_read single bit"); - exposed = 32'habcd; - lval = '0; // Upper bits not cleared by uvm_hdl_read - i = uvm_hdl_read("t.exposed[11]", lval); - `checkh(i, 1); - `checkh(lval[0], exposed[11]); + $display("= uvm_hdl_read single bit"); + exposed = 32'habcd; + lval = '0; // Upper bits not cleared by uvm_hdl_read + i = uvm_hdl_read("t.exposed[11]", lval); + `checkh(i, 1); + `checkh(lval[0], exposed[11]); - $display("= uvm_hdl_deposit single bit"); - lval = 1024'h0; - i = uvm_hdl_deposit("t.exposed[11]", lval); - `checkh(i, 1); - `checkh(exposed, 32'habc5); + $display("= uvm_hdl_deposit single bit"); + lval = 1024'h0; + i = uvm_hdl_deposit("t.exposed[11]", lval); + `checkh(i, 1); + `checkh(exposed, 32'habc5); + end - $display("= uvm_hdl_read multi-bit"); - exposed = 32'habcd; - lval = '0; // Upper bits not cleared by uvm_hdl_read - i = uvm_hdl_read("t.exposed[19:12]", lval); - `checkh(i, 1); - `checkh(lval[7:0], exposed[19:12]); + begin : t_multibit + $display("= uvm_hdl_read multi-bit"); + exposed = 32'habcd; + lval = '0; // Upper bits not cleared by uvm_hdl_read + i = uvm_hdl_read("t.exposed[19:12]", lval); + `checkh(i, 1); + `checkh(lval[7:0], exposed[19:12]); - $display("= uvm_hdl_deposit multi-bit"); - lval = 1024'h12; - i = uvm_hdl_deposit("t.exposed[19:12]", lval); - `checkh(i, 1); - `checkh(exposed, 32'ha12d); + $display("= uvm_hdl_deposit multi-bit"); + lval = 1024'h12; + i = uvm_hdl_deposit("t.exposed[19:12]", lval); + `checkh(i, 1); + `checkh(exposed, 32'ha12d); - $display("= uvm_hdl_deposit bad ranges"); - $display("===\nUVM Report expected on next line:"); - i = uvm_hdl_deposit("t.exposed[10:3]", lval); - `checkh(i, 0); - $display("===\nUVM Report expected on next line:"); - i = uvm_hdl_deposit("t.exposed[99:15]", lval); - `checkh(i, 0); + $display("= uvm_hdl_read/deposit wide decending"); + wide_dec = 80'h1234_56789abc_dcba8765; + lval = '0; // Upper bits not cleared by uvm_hdl_read + i = uvm_hdl_read("t.wide_dec[79:64]", lval); + `checkh(i, 1); + `checkh(lval[15:0], wide_dec[79:64]); + lval = 1024'hffe; + i = uvm_hdl_deposit("t.wide_dec[79:64]", lval); + `checkh(i, 1); + // .vvv_v......._........ + `checkh(wide_dec, 80'h10ff_e6789abc_dcba8765); - $display("= uvm_hdl_deposit not found (bad)"); - $display("===\nUVM Report expected on next line:"); - i = uvm_hdl_deposit("t.__DEPOSIT_NOT_FOUND", 12); - `checkh(i, 0); + $display("= uvm_hdl_read/deposit wide ascending"); + wide_asc = 80'h1234_56789abc_dcba8765; + lval = '0; // Upper bits not cleared by uvm_hdl_read + i = uvm_hdl_read("t.wide_asc[64:79]", lval); + `checkh(i, 1); + `checkh(lval[15:0], wide_asc[64:79]); + lval = 1024'hffe; + i = uvm_hdl_deposit("t.wide_asc[64:79]", lval); + `checkh(i, 1); + // ...._........_...vvvv. + `checkh(wide_asc, 80'h1234_56789abc_dcb0ffe5); + end + +`ifndef VERILATOR // Unsupported + begin : memory_1d + $display("= uvm_hdl_read/deposit 1D memory"); + i = uvm_hdl_check_path("t.mem1d[0]"); + `checkh(i, 0); + i = uvm_hdl_check_path("t.mem1d[1]"); + `checkh(i, 1); + i = uvm_hdl_check_path("t.mem1d[2]"); + `checkh(i, 1); + i = uvm_hdl_check_path("t.mem1d[3]"); + `checkh(i, 0); + mem1d[1] = 1; + mem1d[2] = 2; + lval = '0; // Upper bits not cleared by uvm_hdl_read + i = uvm_hdl_read("t.mem1d[2]", lval); + `checkh(i, 1); + `checkh(lval[31:0], 2); + lval = 1024'h200; + i = uvm_hdl_deposit("t.mem1d[2]", lval); + `checkh(i, 1); + `checkh(mem1d[2], 32'h200); + end + + begin : memory_2d + $display("= uvm_hdl_read/deposit 2D memory"); + i = uvm_hdl_check_path("t.mem2d[0][2]"); + `checkh(i, 0); + i = uvm_hdl_check_path("t.mem2d[1][3]"); + `checkh(i, 1); + i = uvm_hdl_check_path("t.mem2d[2][4]"); + `checkh(i, 1); + i = uvm_hdl_check_path("t.mem2d[2][5]"); + `checkh(i, 0); + mem2d = '{'{13, 14}, '{23, 24}}; + lval = '0; // Upper bits not cleared by uvm_hdl_read + i = uvm_hdl_read("t.mem2d[2][3]", lval); + `checkh(i, 1); + `checkh(lval[31:0], 23); + lval = 1024'h2300; + i = uvm_hdl_deposit("t.mem2d[2][3]", lval); + `checkh(i, 1); + `checkh(mem2d[2][3], 32'h2300); + end +`endif + + begin : t_deposit_bad + $display("= uvm_hdl_deposit bad ranges"); + $display("===\nUVM Report expected on next line:"); + i = uvm_hdl_deposit("t.exposed[10:3]", lval); + `checkh(i, 0); + $display("===\nUVM Report expected on next line:"); + i = uvm_hdl_deposit("t.exposed[99:15]", lval); + `checkh(i, 0); + + $display("= uvm_hdl_deposit not found (bad)"); + $display("===\nUVM Report expected on next line:"); + i = uvm_hdl_deposit("t.__DEPOSIT_NOT_FOUND", 12); + `checkh(i, 0); `ifdef VERILATOR - $display("= uvm_hdl_deposit to not exposed (bad)"); - $display("===\nUVM Report expected on next line:"); - i = uvm_hdl_deposit("t.not_exposed", 12); - `checkh(i, 0); + $display("= uvm_hdl_deposit to not exposed (bad)"); + $display("===\nUVM Report expected on next line:"); + i = uvm_hdl_deposit("t.not_exposed", 12); + `checkh(i, 0); `endif + end - // Force-release - exposed = 32'h11223344; - i = uvm_hdl_read("t.exposed", lval); - `checkh(i, 1); - `checkh(lval[31:0], exposed); -`ifdef VERILATOR - // UNSUPPORTED: force/release via VPI - // If support, validate or throw unsupported on force/release part-selects - $display("= uvm_hdl_force"); - $display("===\nUVM Report expected on next line:"); - i = uvm_hdl_force("t.exposed", 62); - `checkh(i, 0); + begin : t_force_release + exposed = 32'h11223344; + i = uvm_hdl_read("t.exposed", lval); + `checkh(i, 1); + `checkh(lval[31:0], exposed); + // UNSUPPORTED: force/release via VPI + // If support, validate or throw unsupported on force/release part-selects + $display("= uvm_hdl_force"); + i = uvm_hdl_force("t.exposed", 62); + `checkh(i, 1); - $display("= uvm_hdl_release"); - $display("===\nUVM Report expected on next line:"); - i = uvm_hdl_release("t.exposed"); - `checkh(i, 0); + $display("= uvm_hdl_release"); + i = uvm_hdl_release("t.exposed"); + `checkh(i, 1); - $display("= uvm_hdl_release_and_read"); - $display("===\nUVM Report expected on next line:"); - i = uvm_hdl_release_and_read("t.exposed", lval); - `checkh(i, 0); + $display("= uvm_hdl_release_and_read"); + i = uvm_hdl_release_and_read("t.exposed", lval); + `checkh(i, 1); + end - $display("= uvm_hdl_force to not exposed (bad)"); - $display("===\nUVM Report expected on next line:"); - i = uvm_hdl_force("t.not_exposed", 12); - `checkh(i, 0); + begin : t_force_expose_bad + $display("= uvm_hdl_force to not exposed (bad)"); + $display("===\nUVM Report expected on next line:"); + i = uvm_hdl_force("t.not_exposed", 12); + `checkh(i, 0); - $display("= uvm_hdl_force to not forcable (bad)"); - $display("===\nUVM Report expected on next line:"); - i = uvm_hdl_force("t.exposed_not_forceable", 12); - `checkh(i, 0); -`endif + $display("= uvm_hdl_force to not forcable (bad)"); + $display("===\nUVM Report expected on next line:"); + i = uvm_hdl_force("t.exposed_not_forceable", 12); + `checkh(i, 0); + end $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_uvm_dpi_v2017_1_0.out b/test_regress/t/t_uvm_dpi_v2017_1_0.out index d25cb639e..98e5a7a56 100644 --- a/test_regress/t/t_uvm_dpi_v2017_1_0.out +++ b/test_regress/t/t_uvm_dpi_v2017_1_0.out @@ -1,4 +1,4 @@ -UVM Report t/t_uvm_dpi.v:54: id message +UVM Report t/t_uvm_dpi.v:62: id message uvm_dpi_get_tool_name_c() = Verilator = uvm_re = uvm_hdl_check_path @@ -8,6 +8,8 @@ uvm_dpi_get_tool_name_c() = Verilator = uvm_hdl_deposit single bit = uvm_hdl_read multi-bit = uvm_hdl_deposit multi-bit += uvm_hdl_read/deposit wide decending += uvm_hdl_read/deposit wide ascending = uvm_hdl_deposit bad ranges === UVM Report expected on next line: @@ -28,23 +30,16 @@ UVM Report expected on next line: UVM Report ../../t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.not_exposed) Either the name is incorrect, or you may not have PLI/ACC visibility to that name = uvm_hdl_force -=== -UVM Report expected on next line: -UVM Report ../../t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_release -=== -UVM Report expected on next line: -UVM Report ../../t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_release_and_read -=== -UVM Report expected on next line: -UVM Report ../../t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_force to not exposed (bad) === UVM Report expected on next line: -UVM Report ../../t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.not_exposed' +UVM Report ../../t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.not_exposed) + Either the name is incorrect, or you may not have PLI/ACC visibility to that name = uvm_hdl_force to not forcable (bad) === UVM Report expected on next line: -UVM Report ../../t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed_not_forceable' +UVM Report ../../t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.exposed_not_forceable) + Either the name is incorrect, or you may not have PLI/ACC visibility to that name *-* All Finished *-* diff --git a/test_regress/t/t_uvm_dpi_v2017_1_0.py b/test_regress/t/t_uvm_dpi_v2017_1_0.py index dea4e1ece..42e81f4b6 100755 --- a/test_regress/t/t_uvm_dpi_v2017_1_0.py +++ b/test_regress/t/t_uvm_dpi_v2017_1_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -17,7 +17,7 @@ if re.search(r'clang', test.cxx_version): test.skip("uvm_regex.cc from upstream has clang warnings") test.compile(verilator_flags2=[ - "--binary", "--build-jobs 4", "--vpi", "+define+T_V2017_1_0", "+incdir+t/uvm/v2017_1_0", + "--binary", test.build_jobs, "--vpi", "+define+T_V2017_1_0", "+incdir+t/uvm/v2017_1_0", test.pli_filename ]) diff --git a/test_regress/t/t_uvm_dpi_v2020_3_1.out b/test_regress/t/t_uvm_dpi_v2020_3_1.out index e81c061b7..a9ae1fb8e 100644 --- a/test_regress/t/t_uvm_dpi_v2020_3_1.out +++ b/test_regress/t/t_uvm_dpi_v2020_3_1.out @@ -1,4 +1,4 @@ -UVM Report t/t_uvm_dpi.v:54: id message +UVM Report t/t_uvm_dpi.v:62: id message uvm_dpi_get_tool_name_c() = Verilator = uvm_re = uvm_hdl_check_path @@ -8,6 +8,8 @@ uvm_dpi_get_tool_name_c() = Verilator = uvm_hdl_deposit single bit = uvm_hdl_read multi-bit = uvm_hdl_deposit multi-bit += uvm_hdl_read/deposit wide decending += uvm_hdl_read/deposit wide ascending = uvm_hdl_deposit bad ranges === UVM Report expected on next line: @@ -28,23 +30,16 @@ UVM Report expected on next line: UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.not_exposed) Either the name is incorrect, or you may not have PLI/ACC visibility to that name = uvm_hdl_force -=== -UVM Report expected on next line: -UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_release -=== -UVM Report expected on next line: -UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_release_and_read -=== -UVM Report expected on next line: -UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed' = uvm_hdl_force to not exposed (bad) === UVM Report expected on next line: -UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.not_exposed' +UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.not_exposed) + Either the name is incorrect, or you may not have PLI/ACC visibility to that name = uvm_hdl_force to not forcable (bad) === UVM Report expected on next line: -UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/VLOG_GET Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path 't.exposed_not_forceable' +UVM Report ../../t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c:54: UVM/DPI/HDL_SET set: unable to locate hdl path (t.exposed_not_forceable) + Either the name is incorrect, or you may not have PLI/ACC visibility to that name *-* All Finished *-* diff --git a/test_regress/t/t_uvm_dpi_v2020_3_1.py b/test_regress/t/t_uvm_dpi_v2020_3_1.py index 733ed4716..288cde74e 100755 --- a/test_regress/t/t_uvm_dpi_v2020_3_1.py +++ b/test_regress/t/t_uvm_dpi_v2020_3_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -17,7 +17,7 @@ if re.search(r'clang', test.cxx_version): test.skip("uvm_regex.cc from upstream has clang warnings") test.compile(verilator_flags2=[ - "--binary", "--build-jobs 4", "--vpi", "+define+T_V2020_3_1", "+incdir+t/uvm/v2020_3_1", + "--binary", test.build_jobs, "--vpi", "+define+T_V2020_3_1", "+incdir+t/uvm/v2020_3_1", test.pli_filename ]) diff --git a/test_regress/t/t_uvm_hello.v b/test_regress/t/t_uvm_hello.v index 1968c311e..70a18ae83 100644 --- a/test_regress/t/t_uvm_hello.v +++ b/test_regress/t/t_uvm_hello.v @@ -1,8 +1,8 @@ // -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Test requires command line be passed uvm_pkg.sv before this filename @@ -11,8 +11,23 @@ module t; import uvm_pkg::*; + // verilator lint_off UNUSEDSIGNAL + // verilator lint_off WIDTHTRUNC + class test extends uvm_test; + + `uvm_component_utils(test) + + function new(string name, uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void report_phase(uvm_phase phase); + super.report_phase(phase); + $write("** UVM TEST PASSED **\n"); + endfunction + endclass + initial begin - // verilator lint_off WIDTHTRUNC - `uvm_info("TOP", "UVM TEST PASSED", UVM_MEDIUM); + run_test("test"); end endmodule diff --git a/test_regress/t/t_uvm_hello_all_v2017_1_0_dpi.py b/test_regress/t/t_uvm_hello_all_v2017_1_0_dpi.py index 0315ef712..2cdca660e 100755 --- a/test_regress/t/t_uvm_hello_all_v2017_1_0_dpi.py +++ b/test_regress/t/t_uvm_hello_all_v2017_1_0_dpi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_uvm_hello_all_v2017_1_0_nodpi.py b/test_regress/t/t_uvm_hello_all_v2017_1_0_nodpi.py index cc9aba966..9bb7b08fe 100755 --- a/test_regress/t/t_uvm_hello_all_v2017_1_0_nodpi.py +++ b/test_regress/t/t_uvm_hello_all_v2017_1_0_nodpi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_uvm_hello_all_v2020_3_1_dpi.py b/test_regress/t/t_uvm_hello_all_v2020_3_1_dpi.py index bafba287c..35b107f08 100755 --- a/test_regress/t/t_uvm_hello_all_v2020_3_1_dpi.py +++ b/test_regress/t/t_uvm_hello_all_v2020_3_1_dpi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_uvm_hello_all_v2020_3_1_nodpi.py b/test_regress/t/t_uvm_hello_all_v2020_3_1_nodpi.py index 0f3b03587..5184f0e79 100755 --- a/test_regress/t/t_uvm_hello_all_v2020_3_1_nodpi.py +++ b/test_regress/t/t_uvm_hello_all_v2020_3_1_nodpi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vams_basic.py b/test_regress/t/t_vams_basic.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_vams_basic.py +++ b/test_regress/t/t_vams_basic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vams_basic.v b/test_regress/t/t_vams_basic.v index e805206fd..11f243c2e 100644 --- a/test_regress/t/t_vams_basic.v +++ b/test_regress/t/t_vams_basic.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" diff --git a/test_regress/t/t_vams_kwd_bad.py b/test_regress/t/t_vams_kwd_bad.py index 45a114b8a..79419345a 100755 --- a/test_regress/t/t_vams_kwd_bad.py +++ b/test_regress/t/t_vams_kwd_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vams_kwd_bad.v b/test_regress/t/t_vams_kwd_bad.v index e21f9889a..d20e82d24 100644 --- a/test_regress/t/t_vams_kwd_bad.v +++ b/test_regress/t/t_vams_kwd_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Driss Hafdi // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" diff --git a/test_regress/t/t_vams_wreal.py b/test_regress/t/t_vams_wreal.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_vams_wreal.py +++ b/test_regress/t/t_vams_wreal.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vams_wreal.v b/test_regress/t/t_vams_wreal.v index 4025a86c7..6964449f2 100644 --- a/test_regress/t/t_vams_wreal.v +++ b/test_regress/t/t_vams_wreal.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" diff --git a/test_regress/t/t_var_assign_landr.py b/test_regress/t/t_var_assign_landr.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_assign_landr.py +++ b/test_regress/t/t_var_assign_landr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_assign_landr.v b/test_regress/t/t_var_assign_landr.v index 5c6d4faa9..67669486b 100644 --- a/test_regress/t/t_var_assign_landr.v +++ b/test_regress/t/t_var_assign_landr.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014. +// This file ONLY is placed under the Creative Commons Public Domain, for +// SPDX-FileCopyrightText: 2014 // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_assign_landr_noexpand.py b/test_regress/t/t_var_assign_landr_noexpand.py index 5b4129fff..9f5c9af04 100755 --- a/test_regress/t/t_var_assign_landr_noexpand.py +++ b/test_regress/t/t_var_assign_landr_noexpand.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_bad_hide.py b/test_regress/t/t_var_bad_hide.py index 84ba24c85..836d3abfe 100755 --- a/test_regress/t/t_var_bad_hide.py +++ b/test_regress/t/t_var_bad_hide.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_bad_hide.v b/test_regress/t/t_var_bad_hide.v index 88130fb8a..61fa93949 100644 --- a/test_regress/t/t_var_bad_hide.v +++ b/test_regress/t/t_var_bad_hide.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_bad_hide2.py b/test_regress/t/t_var_bad_hide2.py index 04d516c0f..9fc9ce6d8 100755 --- a/test_regress/t/t_var_bad_hide2.py +++ b/test_regress/t/t_var_bad_hide2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_bad_hide2.v b/test_regress/t/t_var_bad_hide2.v index 2861ac167..125de7068 100644 --- a/test_regress/t/t_var_bad_hide2.v +++ b/test_regress/t/t_var_bad_hide2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_bad_hide_docs.py b/test_regress/t/t_var_bad_hide_docs.py index 1b7e7a797..7c8806d08 100755 --- a/test_regress/t/t_var_bad_hide_docs.py +++ b/test_regress/t/t_var_bad_hide_docs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_bad_hide_docs.v b/test_regress/t/t_var_bad_hide_docs.v index ff91817b3..cbbb49285 100644 --- a/test_regress/t/t_var_bad_hide_docs.v +++ b/test_regress/t/t_var_bad_hide_docs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_bad_sameas.py b/test_regress/t/t_var_bad_sameas.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_var_bad_sameas.py +++ b/test_regress/t/t_var_bad_sameas.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_bad_sameas.v b/test_regress/t/t_var_bad_sameas.v index 65f9178fa..9b6f2bf64 100644 --- a/test_regress/t/t_var_bad_sameas.v +++ b/test_regress/t/t_var_bad_sameas.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_bad_sv.py b/test_regress/t/t_var_bad_sv.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_var_bad_sv.py +++ b/test_regress/t/t_var_bad_sv.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_bad_sv.v b/test_regress/t/t_var_bad_sv.v index 08bc61ab1..70ddfa56a 100644 --- a/test_regress/t/t_var_bad_sv.v +++ b/test_regress/t/t_var_bad_sv.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_const.py b/test_regress/t/t_var_const.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_const.py +++ b/test_regress/t/t_var_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_const.v b/test_regress/t/t_var_const.v index c8ff9be07..8133f9bbf 100644 --- a/test_regress/t/t_var_const.v +++ b/test_regress/t/t_var_const.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_const2.py b/test_regress/t/t_var_const2.py index cca4c9e73..d6d35e7fd 100755 --- a/test_regress/t/t_var_const2.py +++ b/test_regress/t/t_var_const2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_const2.v b/test_regress/t/t_var_const2.v index 5e70192bc..163062047 100644 --- a/test_regress/t/t_var_const2.v +++ b/test_regress/t/t_var_const2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_const_bad.py b/test_regress/t/t_var_const_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_var_const_bad.py +++ b/test_regress/t/t_var_const_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_const_bad.v b/test_regress/t/t_var_const_bad.v index 1a1914c21..08498d485 100644 --- a/test_regress/t/t_var_const_bad.v +++ b/test_regress/t/t_var_const_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_dotted1.v b/test_regress/t/t_var_dotted1.v index 2b0f1318b..260c0fb91 100644 --- a/test_regress/t/t_var_dotted1.v +++ b/test_regress/t/t_var_dotted1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_dotted1_inl0.py b/test_regress/t/t_var_dotted1_inl0.py index 4fc10fede..604bcb233 100755 --- a/test_regress/t/t_var_dotted1_inl0.py +++ b/test_regress/t/t_var_dotted1_inl0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_dotted1_inl1.py b/test_regress/t/t_var_dotted1_inl1.py index e2a6573e0..b27436339 100755 --- a/test_regress/t/t_var_dotted1_inl1.py +++ b/test_regress/t/t_var_dotted1_inl1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_dotted1_inl2.py b/test_regress/t/t_var_dotted1_inl2.py index 9af70f709..4608951b0 100755 --- a/test_regress/t/t_var_dotted1_inl2.py +++ b/test_regress/t/t_var_dotted1_inl2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_dotted2.v b/test_regress/t/t_var_dotted2.v index b15546752..0730d90ff 100644 --- a/test_regress/t/t_var_dotted2.v +++ b/test_regress/t/t_var_dotted2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef USE_INLINE diff --git a/test_regress/t/t_var_dotted2_inl0.py b/test_regress/t/t_var_dotted2_inl0.py index d1929af8d..cdd88b557 100755 --- a/test_regress/t/t_var_dotted2_inl0.py +++ b/test_regress/t/t_var_dotted2_inl0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_dotted2_inl1.py b/test_regress/t/t_var_dotted2_inl1.py index 1638e3047..8d800dcde 100755 --- a/test_regress/t/t_var_dotted2_inl1.py +++ b/test_regress/t/t_var_dotted2_inl1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_dotted_dup_bad.py b/test_regress/t/t_var_dotted_dup_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_var_dotted_dup_bad.py +++ b/test_regress/t/t_var_dotted_dup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_dotted_dup_bad.v b/test_regress/t/t_var_dotted_dup_bad.v index e4a4eff8a..d02a4cc2a 100644 --- a/test_regress/t/t_var_dotted_dup_bad.v +++ b/test_regress/t/t_var_dotted_dup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_dup2.py b/test_regress/t/t_var_dup2.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_var_dup2.py +++ b/test_regress/t/t_var_dup2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_dup2.v b/test_regress/t/t_var_dup2.v index d2b18006f..39a81e0a6 100644 --- a/test_regress/t/t_var_dup2.v +++ b/test_regress/t/t_var_dup2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Legal with ANSI Verilog 2001 style ports diff --git a/test_regress/t/t_var_dup2_bad.py b/test_regress/t/t_var_dup2_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_var_dup2_bad.py +++ b/test_regress/t/t_var_dup2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_dup2_bad.v b/test_regress/t/t_var_dup2_bad.v index 3d762be23..aea82ee73 100644 --- a/test_regress/t/t_var_dup2_bad.v +++ b/test_regress/t/t_var_dup2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Illegal with ANSI Verilog 2001 style ports diff --git a/test_regress/t/t_var_dup3.py b/test_regress/t/t_var_dup3.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_var_dup3.py +++ b/test_regress/t/t_var_dup3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_dup3.v b/test_regress/t/t_var_dup3.v index 812c92746..b144221e3 100644 --- a/test_regress/t/t_var_dup3.v +++ b/test_regress/t/t_var_dup3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Legal with Verilog 1995 style ports diff --git a/test_regress/t/t_var_dup_bad.py b/test_regress/t/t_var_dup_bad.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_var_dup_bad.py +++ b/test_regress/t/t_var_dup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_dup_bad.v b/test_regress/t/t_var_dup_bad.v index ae153fbed..104f8f4e5 100644 --- a/test_regress/t/t_var_dup_bad.v +++ b/test_regress/t/t_var_dup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t diff --git a/test_regress/t/t_var_escape.py b/test_regress/t/t_var_escape.py index c4d5794db..feae45552 100755 --- a/test_regress/t/t_var_escape.py +++ b/test_regress/t/t_var_escape.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_escape.v b/test_regress/t/t_var_escape.v index 910c61332..12606b655 100644 --- a/test_regress/t/t_var_escape.v +++ b/test_regress/t/t_var_escape.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_escape_noinl.py b/test_regress/t/t_var_escape_noinl.py new file mode 100755 index 000000000..4bb346b5d --- /dev/null +++ b/test_regress/t/t_var_escape_noinl.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_var_escape.v" +test.golden_filename = "t/t_var_escape.out" + +test.compile( + # Access is so we can dump waves + v_flags2=['-trace' if test.vlt_all else ' +access+rwc', '-fno-inline']) + +test.execute() + +if test.vlt_all: + test.file_grep(test.trace_filename, r'\$enddefinitions') + sigre = re.escape("bra[ket]slash/dash-colon:9") + test.file_grep(test.trace_filename, sigre) + test.file_grep(test.trace_filename, r' other\.cyc ') + test.file_grep(test.trace_filename, r' module mod\.with_dot ') + test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_var_extern_method_lifetime.py b/test_regress/t/t_var_extern_method_lifetime.py index c53b55262..4b9293add 100755 --- a/test_regress/t/t_var_extern_method_lifetime.py +++ b/test_regress/t/t_var_extern_method_lifetime.py @@ -1,17 +1,17 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--binary"]) +test.compile(verilator_flags2=["--binary", "--no-sched-zero-delay"]) test.execute() diff --git a/test_regress/t/t_var_extern_method_lifetime.v b/test_regress/t/t_var_extern_method_lifetime.v index 899faae30..1b1feb3d9 100644 --- a/test_regress/t/t_var_extern_method_lifetime.v +++ b/test_regress/t/t_var_extern_method_lifetime.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 class Foo; diff --git a/test_regress/t/t_var_in_assign.py b/test_regress/t/t_var_in_assign.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_in_assign.py +++ b/test_regress/t/t_var_in_assign.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_in_assign.v b/test_regress/t/t_var_in_assign.v index cf6c488ac..3c6457be6 100644 --- a/test_regress/t/t_var_in_assign.v +++ b/test_regress/t/t_var_in_assign.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_in_assign_bad.py b/test_regress/t/t_var_in_assign_bad.py index 5629f9846..303a2a4ae 100755 --- a/test_regress/t/t_var_in_assign_bad.py +++ b/test_regress/t/t_var_in_assign_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_in_assign_bad.v b/test_regress/t/t_var_in_assign_bad.v index bf4614b10..3de951051 100644 --- a/test_regress/t/t_var_in_assign_bad.v +++ b/test_regress/t/t_var_in_assign_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_in_assign_pedantic.py b/test_regress/t/t_var_in_assign_pedantic.py index 778ba42c8..e69900c14 100755 --- a/test_regress/t/t_var_in_assign_pedantic.py +++ b/test_regress/t/t_var_in_assign_pedantic.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_in_fork.py b/test_regress/t/t_var_in_fork.py index c53b55262..7ded63f3a 100755 --- a/test_regress/t/t_var_in_fork.py +++ b/test_regress/t/t_var_in_fork.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_in_fork.v b/test_regress/t/t_var_in_fork.v index d4a10079e..8406377a9 100644 --- a/test_regress/t/t_var_in_fork.v +++ b/test_regress/t/t_var_in_fork.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 int static_var; diff --git a/test_regress/t/t_var_init.py b/test_regress/t/t_var_init.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_init.py +++ b/test_regress/t/t_var_init.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_init.v b/test_regress/t/t_var_init.v index 0c96cd72b..6b3336365 100644 --- a/test_regress/t/t_var_init.v +++ b/test_regress/t/t_var_init.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_init_static_automatic.py b/test_regress/t/t_var_init_static_automatic.py new file mode 100755 index 000000000..f090e5249 --- /dev/null +++ b/test_regress/t/t_var_init_static_automatic.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--timing']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_var_init_static_automatic.v b/test_regress/t/t_var_init_static_automatic.v new file mode 100644 index 000000000..2a469e67b --- /dev/null +++ b/test_regress/t/t_var_init_static_automatic.v @@ -0,0 +1,226 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end +`define checkd_elab(gotv,expv) if ((gotv) !== (expv)) begin $error("%%Error: %s:%0d: got=%0d exp=%0d", `__FILE__,`__LINE__, (gotv), (expv)); end +// verilog_format: on + +class Cls; + + task tsk(); + for (int i = 0; i < 3; i++) begin + /*automatic*/ int tj_auto; + /*automatic*/ int tj_auto_init = 10; + /*automatic*/ int tqueue_auto[$]; + /*automatic*/ int tqueue_auto_init[$] = '{1}; + static int tj_static; // = 0 + static int tj_static_init = 10; + static int tqueue_static[$]; + static int tqueue_static_init[$] = '{1}; + + $display("Function iteration %0d:", i); + tj_auto = tj_auto + 1; + `checkd(tj_auto, 1); + + tj_auto_init = tj_auto_init + 1; + `checkd(tj_auto_init, 11); + + `checkd(tqueue_auto.size(), 0); + tqueue_auto.push_back(i + 10); + `checkd(tqueue_auto.size(), 1); + + `checkd(tqueue_auto_init.size(), 1); + tqueue_auto_init.push_back(i + 20); + `checkd(tqueue_auto_init.size(), 2); + + tj_static = tj_static + 1; + `checkd(tj_static, i + 1); + + tj_static_init = tj_static_init + 1; + `checkd(tj_static_init, i + 1 + 10); + + tqueue_static.push_back(i + 20); + `checkd(tqueue_static.size(), i + 1); + + tqueue_static_init.push_back(i + 20); + `checkd(tqueue_static_init.size(), i + 2); + end + endtask + +endclass + +module t; + + function int func_const_kj_init(); + int r; + for (int i = 0; i < 3; i++) begin + automatic int kj; + automatic int kj_init = 10; + + kj = kj + 1; + `checkd_elab(kj, 1); + + kj_init = kj_init + 1; + `checkd_elab(kj_init, 11); + r = kj_init; + end + return r; + endfunction + + localparam FUNC_CONST_KJ_INIT = func_const_kj_init(); + + task forked; + automatic int forktop = 100; + for (int i = 0; i < 3; i++) begin + // fork declarations are executed before all parallel statements (IEEE 1800-2023 9.3.2) + fork : f_named + // Automatics-in-forks Verilator will move to a VDynScope class + automatic int fj_auto; + automatic int fj_auto_init = 10; + automatic int fqueue_auto[$]; + automatic int fqueue_auto_init[$] = '{1}; + // Statics-in-forks will stay in the original task + static int fj_static; // = 0 + static int fj_static_init = 10; + static int fqueue_static[$]; + static int fqueue_static_init[$] = '{1}; + begin + $display("Fork iteration %0d:", i); + ++forktop; + + fj_auto = fj_auto + 1; + `checkd(fj_auto, 1); + + fj_auto_init = fj_auto_init + 1; + `checkd(fj_auto_init, 11); + + `checkd(fqueue_auto.size(), 0); + fqueue_auto.push_back(i + 10); + `checkd(fqueue_auto.size(), 1); + + `checkd(fqueue_auto_init.size(), 1); + fqueue_auto_init.push_back(i + 20); + `checkd(fqueue_auto_init.size(), 2); + + fj_static = fj_static + 1; + `checkd(fj_static, i + 1); + + fj_static_init = fj_static_init + 1; + `checkd(fj_static_init, i + 1 + 10); + + fqueue_static.push_back(i + 20); + `checkd(fqueue_static.size(), i + 1); + + fqueue_static_init.push_back(i + 20); + `checkd(fqueue_static_init.size(), i + 2); + end + join + end + `checkd(forktop, 100 + 3); + endtask + + task forked_begin; + // fork declarations are executed before all parallel statements (IEEE 1800-2023 9.3.2) + fork : f_named + for (int i = 0; i < 3; i++) begin + // Automatics-in-zorks Verilator will move to a VDynScope class + automatic int zj_auto; + automatic int zj_auto_init = 10; + automatic int zqueue_auto[$]; + automatic int zqueue_auto_init[$] = '{1}; + // Statics-in-forks will stay in the original task + static int zj_static; // = 0 + static int zj_static_init = 10; + static int zqueue_static[$]; + static int zqueue_static_init[$] = '{1}; + begin + $display("Fork-begin iteration %0d:", i); + + zj_auto = zj_auto + 1; + `checkd(zj_auto, 1); + + zj_auto_init = zj_auto_init + 1; + `checkd(zj_auto_init, 11); + + `checkd(zqueue_auto.size(), 0); + zqueue_auto.push_back(i + 10); + `checkd(zqueue_auto.size(), 1); + + `checkd(zqueue_auto_init.size(), 1); + zqueue_auto_init.push_back(i + 20); + `checkd(zqueue_auto_init.size(), 2); + + zj_static = zj_static + 1; + `checkd(zj_static, i + 1); + + zj_static_init = zj_static_init + 1; + `checkd(zj_static_init, i + 1 + 10); + + zqueue_static.push_back(i + 20); + `checkd(zqueue_static.size(), i + 1); + + zqueue_static_init.push_back(i + 20); + `checkd(zqueue_static_init.size(), i + 2); + end + end + join + endtask + + initial begin + Cls c; + c = new(); + c.tsk(); + + `checkd(FUNC_CONST_KJ_INIT, 11); + + for (int i = 0; i < 3; i++) begin : p_named + automatic int pj_auto; + automatic int pj_auto_init = 10; + automatic int pqueue_auto[$]; + automatic int pqueue_auto_init[$] = '{1}; + static int pj_static; // = 0 + static int pj_static_init = 10; + static int pqueue_static[$]; + static int pqueue_static_init[$] = '{1}; + + $display("Process iteration %0d:", i); + pj_auto = pj_auto + 1; + `checkd(pj_auto, 1); + `checkd(p_named.pj_auto, 1); + + pj_auto_init = pj_auto_init + 1; + `checkd(pj_auto_init, 11); + + `checkd(pqueue_auto.size(), 0); + pqueue_auto.push_back(i + 10); + `checkd(pqueue_auto.size(), 1); + + `checkd(pqueue_auto_init.size(), 1); + pqueue_auto_init.push_back(i + 20); + `checkd(pqueue_auto_init.size(), 2); + + pj_static = pj_static + 1; + `checkd(pj_static, i + 1); + + pj_static_init = pj_static_init + 1; + `checkd(pj_static_init, i + 1 + 10); + + pqueue_static.push_back(i + 10); + `checkd(pqueue_static.size(), i + 1); + + pqueue_static_init.push_back(i + 20); + `checkd(pqueue_static_init.size(), i + 2); + end + + forked(); + forked_begin(); + + $finish; + end + +endmodule diff --git a/test_regress/t/t_var_lifetime_module_bad.py b/test_regress/t/t_var_lifetime_module_bad.py index 55203b6c9..1d5ccb8f4 100755 --- a/test_regress/t/t_var_lifetime_module_bad.py +++ b/test_regress/t/t_var_lifetime_module_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_lifetime_module_bad.v b/test_regress/t/t_var_lifetime_module_bad.v index a529822a6..765d17df3 100644 --- a/test_regress/t/t_var_lifetime_module_bad.v +++ b/test_regress/t/t_var_lifetime_module_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_local.py b/test_regress/t/t_var_local.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_local.py +++ b/test_regress/t/t_var_local.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_local.v b/test_regress/t/t_var_local.v index be0e1042f..fbc74d2f5 100644 --- a/test_regress/t/t_var_local.v +++ b/test_regress/t/t_var_local.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class cls; @@ -33,8 +33,8 @@ module t; initial begin begin : a - integer lower; - integer lower_assign=1; + automatic integer lower; + automatic integer lower_assign = 1; lower = 1; top = 1; if (lower != 1) $stop; diff --git a/test_regress/t/t_var_nonamebegin.py b/test_regress/t/t_var_nonamebegin.py index a6754718f..6f6a0cc62 100755 --- a/test_regress/t/t_var_nonamebegin.py +++ b/test_regress/t/t_var_nonamebegin.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_nonamebegin.v b/test_regress/t/t_var_nonamebegin.v index 2c366c5dd..3a607ff29 100644 --- a/test_regress/t/t_var_nonamebegin.v +++ b/test_regress/t/t_var_nonamebegin.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_notfound_bad.py b/test_regress/t/t_var_notfound_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_var_notfound_bad.py +++ b/test_regress/t/t_var_notfound_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_notfound_bad.v b/test_regress/t/t_var_notfound_bad.v index c0fae653b..668b00fe1 100644 --- a/test_regress/t/t_var_notfound_bad.v +++ b/test_regress/t/t_var_notfound_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_outoforder.py b/test_regress/t/t_var_outoforder.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_outoforder.py +++ b/test_regress/t/t_var_outoforder.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_outoforder.v b/test_regress/t/t_var_outoforder.v index 90b386e39..be3e78841 100644 --- a/test_regress/t/t_var_outoforder.v +++ b/test_regress/t/t_var_outoforder.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_overcmp.py b/test_regress/t/t_var_overcmp.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_overcmp.py +++ b/test_regress/t/t_var_overcmp.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_overcmp.v b/test_regress/t/t_var_overcmp.v index c03da0f48..46e551a45 100644 --- a/test_regress/t/t_var_overcmp.v +++ b/test_regress/t/t_var_overcmp.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_overwidth_bad.cpp b/test_regress/t/t_var_overwidth_bad.cpp index 053be27da..2ab1b6f25 100644 --- a/test_regress/t/t_var_overwidth_bad.cpp +++ b/test_regress/t/t_var_overwidth_bad.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_var_overwidth_bad.py b/test_regress/t/t_var_overwidth_bad.py index 8f9635a27..96e69ef2c 100755 --- a/test_regress/t/t_var_overwidth_bad.py +++ b/test_regress/t/t_var_overwidth_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_overwidth_bad.v b/test_regress/t/t_var_overwidth_bad.v index 96d441841..3f0709c9b 100644 --- a/test_regress/t/t_var_overwidth_bad.v +++ b/test_regress/t/t_var_overwidth_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_overzero.py b/test_regress/t/t_var_overzero.py index a2adc5082..e7be559d1 100755 --- a/test_regress/t/t_var_overzero.py +++ b/test_regress/t/t_var_overzero.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_overzero.v b/test_regress/t/t_var_overzero.v index dbff3598c..5cd28f4c6 100644 --- a/test_regress/t/t_var_overzero.v +++ b/test_regress/t/t_var_overzero.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_pins_bad.py b/test_regress/t/t_var_pins_bad.py index a7ccd7462..a7556b86c 100755 --- a/test_regress/t/t_var_pins_bad.py +++ b/test_regress/t/t_var_pins_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_cc.py b/test_regress/t/t_var_pins_cc.py index 1912bf071..a9e8f9786 100755 --- a/test_regress/t/t_var_pins_cc.py +++ b/test_regress/t/t_var_pins_cc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_sc1.py b/test_regress/t/t_var_pins_sc1.py index 7e9d114a9..157e2b2ff 100755 --- a/test_regress/t/t_var_pins_sc1.py +++ b/test_regress/t/t_var_pins_sc1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_sc2.py b/test_regress/t/t_var_pins_sc2.py index 8cf009783..4339e6c27 100755 --- a/test_regress/t/t_var_pins_sc2.py +++ b/test_regress/t/t_var_pins_sc2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_sc32.py b/test_regress/t/t_var_pins_sc32.py index 55d5fc5c2..3b2cccd0c 100755 --- a/test_regress/t/t_var_pins_sc32.py +++ b/test_regress/t/t_var_pins_sc32.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_sc64.py b/test_regress/t/t_var_pins_sc64.py index b550f6899..a97c4a284 100755 --- a/test_regress/t/t_var_pins_sc64.py +++ b/test_regress/t/t_var_pins_sc64.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_sc_biguint.py b/test_regress/t/t_var_pins_sc_biguint.py index 7336b83fd..5852501c4 100755 --- a/test_regress/t/t_var_pins_sc_biguint.py +++ b/test_regress/t/t_var_pins_sc_biguint.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_sc_uint.py b/test_regress/t/t_var_pins_sc_uint.py index 0836de46a..3aa6428f9 100755 --- a/test_regress/t/t_var_pins_sc_uint.py +++ b/test_regress/t/t_var_pins_sc_uint.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_sc_uint_biguint.py b/test_regress/t/t_var_pins_sc_uint_biguint.py index 5f7abceda..7049f7321 100755 --- a/test_regress/t/t_var_pins_sc_uint_biguint.py +++ b/test_regress/t/t_var_pins_sc_uint_biguint.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_sc_uint_bool.py b/test_regress/t/t_var_pins_sc_uint_bool.py index e2b556580..8050f1ed3 100755 --- a/test_regress/t/t_var_pins_sc_uint_bool.py +++ b/test_regress/t/t_var_pins_sc_uint_bool.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_sc_uint_bool_nomain.py b/test_regress/t/t_var_pins_sc_uint_bool_nomain.py index b466547a0..efc72b6c1 100755 --- a/test_regress/t/t_var_pins_sc_uint_bool_nomain.py +++ b/test_regress/t/t_var_pins_sc_uint_bool_nomain.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pins_scui.py b/test_regress/t/t_var_pins_scui.py index c3600fa8a..f9e3634e5 100755 --- a/test_regress/t/t_var_pins_scui.py +++ b/test_regress/t/t_var_pins_scui.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_pinsizes.cpp b/test_regress/t/t_var_pinsizes.cpp index b898aa792..186a11f6e 100644 --- a/test_regress/t/t_var_pinsizes.cpp +++ b/test_regress/t/t_var_pinsizes.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_var_pinsizes.v b/test_regress/t/t_var_pinsizes.v index 20621c891..f26be1353 100644 --- a/test_regress/t/t_var_pinsizes.v +++ b/test_regress/t/t_var_pinsizes.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Also check that SystemC is ordering properly diff --git a/test_regress/t/t_var_pinsizes.vlt b/test_regress/t/t_var_pinsizes.vlt index 40e17265b..af5160e01 100644 --- a/test_regress/t/t_var_pinsizes.vlt +++ b/test_regress/t/t_var_pinsizes.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Stefan Wallentowitz. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_var_port2_bad.py b/test_regress/t/t_var_port2_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_var_port2_bad.py +++ b/test_regress/t/t_var_port2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_port2_bad.v b/test_regress/t/t_var_port2_bad.v index 504af82db..a48f90a59 100644 --- a/test_regress/t/t_var_port2_bad.v +++ b/test_regress/t/t_var_port2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (portwithoin); diff --git a/test_regress/t/t_var_port_bad.py b/test_regress/t/t_var_port_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_var_port_bad.py +++ b/test_regress/t/t_var_port_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_port_bad.v b/test_regress/t/t_var_port_bad.v index 03f042560..09d51d14f 100644 --- a/test_regress/t/t_var_port_bad.v +++ b/test_regress/t/t_var_port_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_port_json_only.out b/test_regress/t/t_var_port_json_only.out index b4eb00370..19eef5222 100644 --- a/test_regress/t/t_var_port_json_only.out +++ b/test_regress/t/t_var_port_json_only.out @@ -1,77 +1,77 @@ -{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED","stlFirstIterationp":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"mh2","addr":"(E)","loc":"d,18:8,18:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh2","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"mh2","addr":"(E)","loc":"d,18:8,18:11","origName":"mh2","verilogName":"mh2","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_inout_wire_integer","addr":"(F)","loc":"d,18:27,18:47","dtypep":"(G)","origName":"x_inout_wire_integer","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INOUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_inout_wire_integer","addr":"(F)","loc":"d,18:27,18:47","dtypep":"(G)","origName":"x_inout_wire_integer","verilogName":"x_inout_wire_integer","isPrimaryIO":true,"direction":"INOUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, - {"type":"MODULE","name":"mh5","addr":"(H)","loc":"d,24:8,24:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh5","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"mh5","addr":"(H)","loc":"d,24:8,24:11","origName":"mh5","verilogName":"mh5","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_input_wire_logic","addr":"(I)","loc":"d,24:19,24:37","dtypep":"(J)","origName":"x_input_wire_logic","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_input_wire_logic","addr":"(I)","loc":"d,24:19,24:37","dtypep":"(J)","origName":"x_input_wire_logic","verilogName":"x_input_wire_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, - {"type":"MODULE","name":"mh6","addr":"(K)","loc":"d,26:8,26:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh6","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"mh6","addr":"(K)","loc":"d,26:8,26:11","origName":"mh6","verilogName":"mh6","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_input_var_logic","addr":"(L)","loc":"d,26:23,26:40","dtypep":"(J)","origName":"x_input_var_logic","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_input_var_logic","addr":"(L)","loc":"d,26:23,26:40","dtypep":"(J)","origName":"x_input_var_logic","verilogName":"x_input_var_logic","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, - {"type":"MODULE","name":"mh7","addr":"(M)","loc":"d,28:8,28:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"mh7","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"mh7","addr":"(M)","loc":"d,28:8,28:11","origName":"mh7","verilogName":"mh7","level":1,"timeunit":"1ps","inlinesp": [], "stmtsp": [ - {"type":"VAR","name":"x_input_var_integer","addr":"(N)","loc":"d,28:31,28:50","dtypep":"(G)","origName":"x_input_var_integer","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"x_input_var_integer","addr":"(N)","loc":"d,28:31,28:50","dtypep":"(G)","origName":"x_input_var_integer","verilogName":"x_input_var_integer","isPrimaryIO":true,"direction":"INPUT","isSigPublic":true,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"integer","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ]}, - 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{"type":"UNPACKARRAYDTYPE","name":"","addr":"(RB)","loc":"d,58:34,58:35","dtypep":"(RB)","isCompound":false,"declRange":"[5:0]","generic":false,"refDTypep":"(J)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(RB)","loc":"d,58:34,58:35","dtypep":"(RB)","declRange":"[5:0]","refDTypep":"(J)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(TB)","loc":"d,58:34,58:35","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(TB)","loc":"d,58:34,58:35", "leftp": [ {"type":"CONST","name":"32'sh5","addr":"(UB)","loc":"d,58:35,58:36","dtypep":"(VB)"} ], @@ -80,9 +80,9 @@ ]} ]}, {"type":"BASICDTYPE","name":"logic","addr":"(J)","loc":"d,58:41,58:56","dtypep":"(J)","keyword":"logic","generic":true,"rangep": []}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(CB)","loc":"d,40:36,40:37","dtypep":"(CB)","isCompound":false,"declRange":"[5:0]","generic":false,"refDTypep":"(J)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(CB)","loc":"d,40:36,40:37","dtypep":"(CB)","declRange":"[5:0]","refDTypep":"(J)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(XB)","loc":"d,40:36,40:37","ascending":false,"fromBracket":false, + {"type":"RANGE","name":"","addr":"(XB)","loc":"d,40:36,40:37", "leftp": [ {"type":"CONST","name":"32'sh5","addr":"(YB)","loc":"d,40:37,40:38","dtypep":"(VB)"} ], @@ -97,7 +97,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(AC)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(BC)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(AC)","varsp": [],"blocksp": [],"inlinesp": []} ]} diff --git a/test_regress/t/t_var_port_json_only.py b/test_regress/t/t_var_port_json_only.py index c445dd503..6759caffd 100755 --- a/test_regress/t/t_var_port_json_only.py +++ b/test_regress/t/t_var_port_json_only.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_port_json_only.v b/test_regress/t/t_var_port_json_only.v index 88418b19c..0815fdeff 100644 --- a/test_regress/t/t_var_port_json_only.v +++ b/test_regress/t/t_var_port_json_only.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // This checks IEEE ports work correctly, we use XML output to make it easy to diff --git a/test_regress/t/t_var_port_xml.out b/test_regress/t/t_var_port_xml.out deleted file mode 100644 index 74a0b020e..000000000 --- a/test_regress/t/t_var_port_xml.out +++ /dev/null @@ -1,129 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_var_port_xml.py b/test_regress/t/t_var_port_xml.py deleted file mode 100755 index 854552434..000000000 --- a/test_regress/t/t_var_port_xml.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--bbox-unsup'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_var_port_xml.v b/test_regress/t/t_var_port_xml.v deleted file mode 100644 index 88418b19c..000000000 --- a/test_regress/t/t_var_port_xml.v +++ /dev/null @@ -1,59 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -// This checks IEEE ports work correctly, we use XML output to make it easy to -// see all attributes are propagated - -// verilator lint_off MULTITOP - -`ifndef VERILATOR -module mh0 (wire x_inout_wire_logic); -endmodule -module mh1 (integer x_inout_wire_integer); -endmodule -`endif -module mh2 (inout integer x_inout_wire_integer); -endmodule -`ifndef VERILATOR -module mh3 ([5:0] x_inout_wire_logic_p6); -endmodule -`endif -module mh5 (input x_input_wire_logic); -endmodule -module mh6 (input var x_input_var_logic); -endmodule -module mh7 (input var integer x_input_var_integer); -endmodule -module mh8 (output x_output_wire_logic); -endmodule -module mh9 (output var x_output_var_logic); -endmodule -module mh10(output signed [5:0] x_output_wire_logic_signed_p6); -endmodule -module mh11(output integer x_output_var_integer); -endmodule -module mh12(ref [5:0] x_ref_logic_p6); -endmodule -module mh13(ref x_ref_var_logic_u6 [5:0]); -endmodule -`ifndef VERILATOR -module mh14(wire x_inout_wire_logic, y_inout_wire_logic_p8 [7:0]); -endmodule -module mh15(integer x_inout_wire_integer, signed [5:0] y_inout_wire_logic_signed6); -endmodule -module mh16([5:0] x_inout_wire_logic_p6, wire y_inout_wire_logic); -endmodule -`endif -module mh17(input var integer x_input_var_integer, wire y_input_wire_logic); -endmodule -module mh18(output var x_output_var_logic, input y_input_wire_logic); -endmodule -module mh19(output signed [5:0] x_output_wire_logic_signed_p6, integer y_output_var_integer); -endmodule -module mh20(ref [5:0] x_ref_var_logic_p6, y_ref_var_logic_p6); -endmodule -module mh21(ref ref_var_logic_u6 [5:0], y_ref_var_logic); -endmodule diff --git a/test_regress/t/t_var_ref.py b/test_regress/t/t_var_ref.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_ref.py +++ b/test_regress/t/t_var_ref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_ref.v b/test_regress/t/t_var_ref.v index 81feb657a..e5081e066 100644 --- a/test_regress/t/t_var_ref.v +++ b/test_regress/t/t_var_ref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_var_ref_bad1.py b/test_regress/t/t_var_ref_bad1.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_var_ref_bad1.py +++ b/test_regress/t/t_var_ref_bad1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_ref_bad1.v b/test_regress/t/t_var_ref_bad1.v index 20149514b..3c9c4c45a 100644 --- a/test_regress/t/t_var_ref_bad1.v +++ b/test_regress/t/t_var_ref_bad1.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable diff --git a/test_regress/t/t_var_ref_bad2.py b/test_regress/t/t_var_ref_bad2.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_var_ref_bad2.py +++ b/test_regress/t/t_var_ref_bad2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_ref_bad2.v b/test_regress/t/t_var_ref_bad2.v index 307880832..86d4186fa 100644 --- a/test_regress/t/t_var_ref_bad2.v +++ b/test_regress/t/t_var_ref_bad2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable diff --git a/test_regress/t/t_var_ref_bad3.py b/test_regress/t/t_var_ref_bad3.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_var_ref_bad3.py +++ b/test_regress/t/t_var_ref_bad3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_ref_bad3.v b/test_regress/t/t_var_ref_bad3.v index f6fc60143..1890389ea 100644 --- a/test_regress/t/t_var_ref_bad3.v +++ b/test_regress/t/t_var_ref_bad3.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable diff --git a/test_regress/t/t_var_ref_noinline.py b/test_regress/t/t_var_ref_noinline.py index f5064fa95..457d074fe 100755 --- a/test_regress/t/t_var_ref_noinline.py +++ b/test_regress/t/t_var_ref_noinline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 test.top_filename = "t/t_var_ref.v" diff --git a/test_regress/t/t_var_ref_static.py b/test_regress/t/t_var_ref_static.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_var_ref_static.py +++ b/test_regress/t/t_var_ref_static.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_ref_static.v b/test_regress/t/t_var_ref_static.v index 1d3a248c9..4b13091ea 100644 --- a/test_regress/t/t_var_ref_static.v +++ b/test_regress/t/t_var_ref_static.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable diff --git a/test_regress/t/t_var_rsvd.py b/test_regress/t/t_var_rsvd.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_rsvd.py +++ b/test_regress/t/t_var_rsvd.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_rsvd.v b/test_regress/t/t_var_rsvd.v index aa3e53a2c..dc972d13b 100644 --- a/test_regress/t/t_var_rsvd.v +++ b/test_regress/t/t_var_rsvd.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD diff --git a/test_regress/t/t_var_rsvd_bad.py b/test_regress/t/t_var_rsvd_bad.py index 113352b72..4ceae144c 100755 --- a/test_regress/t/t_var_rsvd_bad.py +++ b/test_regress/t/t_var_rsvd_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_rsvd_port.py b/test_regress/t/t_var_rsvd_port.py index 13c220107..551293a78 100755 --- a/test_regress/t/t_var_rsvd_port.py +++ b/test_regress/t/t_var_rsvd_port.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_rsvd_port.v b/test_regress/t/t_var_rsvd_port.v index a9d81abe0..5cc594967 100644 --- a/test_regress/t/t_var_rsvd_port.v +++ b/test_regress/t/t_var_rsvd_port.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_sc_bv.cpp b/test_regress/t/t_var_sc_bv.cpp index 97d45745f..116ac6aa5 100644 --- a/test_regress/t/t_var_sc_bv.cpp +++ b/test_regress/t/t_var_sc_bv.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_var_sc_bv.py b/test_regress/t/t_var_sc_bv.py index fb4049cf1..04b92947c 100755 --- a/test_regress/t/t_var_sc_bv.py +++ b/test_regress/t/t_var_sc_bv.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_sc_bv.v b/test_regress/t/t_var_sc_bv.v index d3164ee09..499a81da5 100644 --- a/test_regress/t/t_var_sc_bv.v +++ b/test_regress/t/t_var_sc_bv.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Lane Brooks // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_sc_double.cpp b/test_regress/t/t_var_sc_double.cpp index 70a787e6d..58a72c9f3 100644 --- a/test_regress/t/t_var_sc_double.cpp +++ b/test_regress/t/t_var_sc_double.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by George Polack. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 George Polack // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_var_sc_double.py b/test_regress/t/t_var_sc_double.py index fb4049cf1..04b92947c 100755 --- a/test_regress/t/t_var_sc_double.py +++ b/test_regress/t/t_var_sc_double.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_sc_double.v b/test_regress/t/t_var_sc_double.v index c140ce083..44fa1cf67 100644 --- a/test_regress/t/t_var_sc_double.v +++ b/test_regress/t/t_var_sc_double.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2025 by George Polack. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 George Polack // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_var_set_link.py b/test_regress/t/t_var_set_link.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_set_link.py +++ b/test_regress/t/t_var_set_link.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_set_link.v b/test_regress/t/t_var_set_link.v index d01f989df..281f405f3 100644 --- a/test_regress/t/t_var_set_link.v +++ b/test_regress/t/t_var_set_link.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_static.py b/test_regress/t/t_var_static.py index df3c5c280..8537b369d 100755 --- a/test_regress/t/t_var_static.py +++ b/test_regress/t/t_var_static.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_static.v b/test_regress/t/t_var_static.v index dd79f5703..046eb3370 100644 --- a/test_regress/t/t_var_static.v +++ b/test_regress/t/t_var_static.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_var_static_assign_decl_bad.out b/test_regress/t/t_var_static_assign_decl_bad.out index cd0e9d02c..83904ac2d 100644 --- a/test_regress/t/t_var_static_assign_decl_bad.out +++ b/test_regress/t/t_var_static_assign_decl_bad.out @@ -1,71 +1,71 @@ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:101:17: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:103:19: Static variable initializer : is dependent on function/task I/O variable - 101 | logic tmp = in; - | ^~ + 103 | logic tmp = in; + | ^~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:106:17: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:108:19: Static variable initializer : is dependent on function/task I/O variable - 106 | logic tmp = in; - | ^~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:111:24: Static variable initializer + 108 | logic tmp = in; + | ^~ +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:113:24: Static variable initializer : is dependent on function/task I/O variable - 111 | static logic tmp = in; + 113 | static logic tmp = in; | ^~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:116:17: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:118:17: Static variable initializer : is dependent on function/task I/O variable - 116 | logic tmp = out; + 118 | logic tmp = out; | ^~~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:121:20: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:123:20: Static variable initializer : is dependent on function/task I/O variable - 121 | logic tmp = in + 1; + 123 | logic tmp = in + 1; | ^ -%Error: t/t_var_static_assign_decl_bad.v:126:26: Static variable initializer +%Error: t/t_var_static_assign_decl_bad.v:128:26: Static variable initializer : is dependent on automatic variable - 126 | static int foo = tmp + 1; + 128 | static int foo = tmp + 1; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_var_static_assign_decl_bad.v:132:26: Static variable initializer +%Error: t/t_var_static_assign_decl_bad.v:134:26: Static variable initializer : is dependent on automatic variable - 132 | static int foo = tmp + 1; + 134 | static int foo = tmp + 1; | ^ -%Error: t/t_var_static_assign_decl_bad.v:138:29: Static variable initializer +%Error: t/t_var_static_assign_decl_bad.v:140:29: Static variable initializer : is dependent on automatic variable - 138 | static logic func_var = loc; + 140 | static logic func_var = loc; | ^~~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:9:15: Static variable initializer - : is dependent on function/task I/O variable - 9 | logic tmp = in; +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:11:15: Static variable initializer + : is dependent on function/task I/O variable + 11 | logic tmp = in; | ^~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:14:15: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:16:15: Static variable initializer : is dependent on function/task I/O variable - 14 | logic tmp = in; + 16 | logic tmp = in; | ^~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:20:17: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:22:17: Static variable initializer : is dependent on function/task I/O variable - 20 | logic tmp = in; + 22 | logic tmp = in; | ^~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:25:17: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:27:17: Static variable initializer : is dependent on function/task I/O variable - 25 | logic tmp = in; + 27 | logic tmp = in; | ^~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:32:17: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:34:17: Static variable initializer : is dependent on function/task I/O variable - 32 | logic tmp = in; + 34 | logic tmp = in; | ^~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:37:17: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:39:17: Static variable initializer : is dependent on function/task I/O variable - 37 | logic tmp = in; + 39 | logic tmp = in; | ^~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:44:17: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:46:17: Static variable initializer : is dependent on function/task I/O variable - 44 | logic tmp = in; + 46 | logic tmp = in; | ^~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:49:17: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:51:17: Static variable initializer : is dependent on function/task I/O variable - 49 | logic tmp = in; + 51 | logic tmp = in; | ^~ -%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:72:17: Static variable initializer +%Error-UNSUPPORTED: t/t_var_static_assign_decl_bad.v:74:17: Static variable initializer : is dependent on function/task I/O variable - 72 | logic tmp = in; + 74 | logic tmp = in; | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_var_static_assign_decl_bad.py b/test_regress/t/t_var_static_assign_decl_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_var_static_assign_decl_bad.py +++ b/test_regress/t/t_var_static_assign_decl_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_static_assign_decl_bad.v b/test_regress/t/t_var_static_assign_decl_bad.v index 6e0f5b260..5d2164889 100644 --- a/test_regress/t/t_var_static_assign_decl_bad.v +++ b/test_regress/t/t_var_static_assign_decl_bad.v @@ -1,9 +1,11 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 +// verilator lint_off NORETURN + function static func_stat; input logic in; logic tmp = in; @@ -63,8 +65,8 @@ module no_warn#(PARAM = 1)(input in, input clk); // Do not warn on constant assignments. function static func_param; - static logic func_var = PARAM; - static logic func_enum = A; + static bit func_var = PARAM != 0; + static bit func_enum = A != B; endfunction // Do not warn on assignment referencing module I/O. @@ -87,7 +89,7 @@ module no_warn#(PARAM = 1)(input in, input clk); // Do not warn on variables under blocks. initial begin - logic init_tmp = in; + static logic init_tmp = in; end always @(posedge clk) begin @@ -98,12 +100,12 @@ endmodule module t(input clk); function static func_stat; input logic in; - logic tmp = in; + /*static*/ logic tmp = in; endfunction task static task_stat; input logic in; - logic tmp = in; + /*static*/ logic tmp = in; endtask function automatic func_auto_with_static; diff --git a/test_regress/t/t_var_static_param.py b/test_regress/t/t_var_static_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_static_param.py +++ b/test_regress/t/t_var_static_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_static_param.v b/test_regress/t/t_var_static_param.v index 72b989329..39814a874 100644 --- a/test_regress/t/t_var_static_param.v +++ b/test_regress/t/t_var_static_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `define stop $stop diff --git a/test_regress/t/t_var_suggest_bad.py b/test_regress/t/t_var_suggest_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_var_suggest_bad.py +++ b/test_regress/t/t_var_suggest_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_suggest_bad.v b/test_regress/t/t_var_suggest_bad.v index 8d321505a..f6f6063f5 100644 --- a/test_regress/t/t_var_suggest_bad.v +++ b/test_regress/t/t_var_suggest_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_tieout.py b/test_regress/t/t_var_tieout.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_var_tieout.py +++ b/test_regress/t/t_var_tieout.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_tieout.v b/test_regress/t/t_var_tieout.v index 96855d921..967ed5dba 100644 --- a/test_regress/t/t_var_tieout.v +++ b/test_regress/t/t_var_tieout.v @@ -1,6 +1,6 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug291 diff --git a/test_regress/t/t_var_top_struct.py b/test_regress/t/t_var_top_struct.py index c3bd7274f..66009b455 100755 --- a/test_regress/t/t_var_top_struct.py +++ b/test_regress/t/t_var_top_struct.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_top_struct.v b/test_regress/t/t_var_top_struct.v index a27336e0b..e468508ec 100644 --- a/test_regress/t/t_var_top_struct.v +++ b/test_regress/t/t_var_top_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 typedef struct { diff --git a/test_regress/t/t_var_types.py b/test_regress/t/t_var_types.py index 9964558dd..8b5344d9a 100755 --- a/test_regress/t/t_var_types.py +++ b/test_regress/t/t_var_types.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_types.v b/test_regress/t/t_var_types.v index 40d05d94e..d410af232 100644 --- a/test_regress/t/t_var_types.v +++ b/test_regress/t/t_var_types.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_types_bad.py b/test_regress/t/t_var_types_bad.py index 8e9543a6c..5e2791bb4 100755 --- a/test_regress/t/t_var_types_bad.py +++ b/test_regress/t/t_var_types_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_types_bad.v b/test_regress/t/t_var_types_bad.v index 2f307d898..ccd9a587f 100644 --- a/test_regress/t/t_var_types_bad.v +++ b/test_regress/t/t_var_types_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_vec_sel.py b/test_regress/t/t_var_vec_sel.py index c2d985114..67b896515 100755 --- a/test_regress/t/t_var_vec_sel.py +++ b/test_regress/t/t_var_vec_sel.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_vec_sel.v b/test_regress/t/t_var_vec_sel.v index e55cf45a8..b7ac89c82 100644 --- a/test_regress/t/t_var_vec_sel.v +++ b/test_regress/t/t_var_vec_sel.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // bug601 diff --git a/test_regress/t/t_var_xref_bad.py b/test_regress/t/t_var_xref_bad.py index 30c3d4f77..1952b53a1 100755 --- a/test_regress/t/t_var_xref_bad.py +++ b/test_regress/t/t_var_xref_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_xref_bad.v b/test_regress/t/t_var_xref_bad.v index ec7be7c09..c7b00fb81 100644 --- a/test_regress/t/t_var_xref_bad.v +++ b/test_regress/t/t_var_xref_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_xref_gen.py b/test_regress/t/t_var_xref_gen.py index 75684187a..52389589b 100755 --- a/test_regress/t/t_var_xref_gen.py +++ b/test_regress/t/t_var_xref_gen.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_var_xref_gen.v b/test_regress/t/t_var_xref_gen.v index bff5037a9..39a3faf1e 100644 --- a/test_regress/t/t_var_xref_gen.v +++ b/test_regress/t/t_var_xref_gen.v @@ -3,8 +3,8 @@ // This is to test the handling of VarXRef when the referenced VAR is // under a generate construction. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Jie Xu and Roland Kruse. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2015 Jie Xu and Roland Kruse // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_varref_scope_in_interface.py b/test_regress/t/t_varref_scope_in_interface.py index f81c3d68d..88752b416 100755 --- a/test_regress/t/t_varref_scope_in_interface.py +++ b/test_regress/t/t_varref_scope_in_interface.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_varref_scope_in_interface.v b/test_regress/t/t_varref_scope_in_interface.v old mode 100755 new mode 100644 index d030b5c13..d598f35e6 --- a/test_regress/t/t_varref_scope_in_interface.v +++ b/test_regress/t/t_varref_scope_in_interface.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface iface #(parameter DWIDTH = 32)(); diff --git a/test_regress/t/t_verilated_all.py b/test_regress/t/t_verilated_all.py index 86812d347..28cd6b097 100755 --- a/test_regress/t/t_verilated_all.py +++ b/test_regress/t/t_verilated_all.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_verilated_all.v b/test_regress/t/t_verilated_all.v index 660a709bb..f34361b2c 100644 --- a/test_regress/t/t_verilated_all.v +++ b/test_regress/t/t_verilated_all.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 class Rnd; diff --git a/test_regress/t/t_verilated_all_newest.py b/test_regress/t/t_verilated_all_newest.py index 0bfa92b93..417fc64a7 100755 --- a/test_regress/t/t_verilated_all_newest.py +++ b/test_regress/t/t_verilated_all_newest.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_verilated_all_oldest.py b/test_regress/t/t_verilated_all_oldest.py index c07c374b9..b0f512f72 100755 --- a/test_regress/t/t_verilated_all_oldest.py +++ b/test_regress/t/t_verilated_all_oldest.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_verilated_debug.out b/test_regress/t/t_verilated_debug.out index e4f93ddf7..1d7867bab 100644 --- a/test_regress/t/t_verilated_debug.out +++ b/test_regress/t/t_verilated_debug.out @@ -16,11 +16,11 @@ internalsDump: -V{t#,#}+ Eval -V{t#,#}+ Vt_verilated_debug___024root___eval -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__act --V{t#,#}+ Vt_verilated_debug___024root___eval_triggers__act +-V{t#,#}+ Vt_verilated_debug___024root___eval_triggers_vec__act -V{t#,#}+ Vt_verilated_debug___024root___dump_triggers__act -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act +-V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__nba -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup @@ -29,22 +29,22 @@ internalsDump: -V{t#,#}+ Eval -V{t#,#}+ Vt_verilated_debug___024root___eval -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__act --V{t#,#}+ Vt_verilated_debug___024root___eval_triggers__act +-V{t#,#}+ Vt_verilated_debug___024root___eval_triggers_vec__act -V{t#,#}+ Vt_verilated_debug___024root___dump_triggers__act -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#} 'act' region trigger index 0 is active: @(posedge clk) --V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act +-V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__nba -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#}+ Vt_verilated_debug___024root___eval_nba *-* All Finished *-* -V{t#,#}+ Vt_verilated_debug___024root___trigger_clear__act -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__act --V{t#,#}+ Vt_verilated_debug___024root___eval_triggers__act +-V{t#,#}+ Vt_verilated_debug___024root___eval_triggers_vec__act -V{t#,#}+ Vt_verilated_debug___024root___dump_triggers__act -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#} No 'act' region triggers active --V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act +-V{t#,#}+ Vt_verilated_debug___024root___trigger_orInto__act_vec_vec -V{t#,#}+ Vt_verilated_debug___024root___eval_phase__nba -V{t#,#}+ Vt_verilated_debug___024root___trigger_anySet__act -V{t#,#}End-of-eval cleanup diff --git a/test_regress/t/t_verilated_debug.py b/test_regress/t/t_verilated_debug.py index 221a3478d..dbc82d1c1 100755 --- a/test_regress/t/t_verilated_debug.py +++ b/test_regress/t/t_verilated_debug.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_verilated_debug.v b/test_regress/t/t_verilated_debug.v index 3f4e000eb..7795281e6 100644 --- a/test_regress/t/t_verilated_debug.v +++ b/test_regress/t/t_verilated_debug.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_verilated_header.py b/test_regress/t/t_verilated_header.py index 64fff6852..7d58e7d17 100755 --- a/test_regress/t/t_verilated_header.py +++ b/test_regress/t/t_verilated_header.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_verilated_header.v b/test_regress/t/t_verilated_header.v index 0081c4644..6a41aac7c 100644 --- a/test_regress/t/t_verilated_header.v +++ b/test_regress/t/t_verilated_header.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "verilated.v" diff --git a/test_regress/t/t_verilated_threaded.py b/test_regress/t/t_verilated_threaded.py index f8371587a..b7f070268 100755 --- a/test_regress/t/t_verilated_threaded.py +++ b/test_regress/t/t_verilated_threaded.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_virtual_interface_delayed.py b/test_regress/t/t_virtual_interface_delayed.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_virtual_interface_delayed.py +++ b/test_regress/t/t_virtual_interface_delayed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_virtual_interface_delayed.v b/test_regress/t/t_virtual_interface_delayed.v index 20df1840e..3c7126751 100644 --- a/test_regress/t/t_virtual_interface_delayed.v +++ b/test_regress/t/t_virtual_interface_delayed.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off diff --git a/test_regress/t/t_virtual_interface_gen_for_ref.py b/test_regress/t/t_virtual_interface_gen_for_ref.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_virtual_interface_gen_for_ref.py +++ b/test_regress/t/t_virtual_interface_gen_for_ref.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_virtual_interface_gen_for_ref.v b/test_regress/t/t_virtual_interface_gen_for_ref.v index 2d8b30a86..b6761b8a7 100644 --- a/test_regress/t/t_virtual_interface_gen_for_ref.v +++ b/test_regress/t/t_virtual_interface_gen_for_ref.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 package uvm_pkg; diff --git a/test_regress/t/t_virtual_interface_member_trigger.py b/test_regress/t/t_virtual_interface_member_trigger.py index f1e665db3..567f18b29 100755 --- a/test_regress/t/t_virtual_interface_member_trigger.py +++ b/test_regress/t/t_virtual_interface_member_trigger.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_virtual_interface_member_trigger.v b/test_regress/t/t_virtual_interface_member_trigger.v old mode 100755 new mode 100644 index 593e78baa..391075ae1 --- a/test_regress/t/t_virtual_interface_member_trigger.v +++ b/test_regress/t/t_virtual_interface_member_trigger.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps diff --git a/test_regress/t/t_virtual_interface_member_trigger_realistic_case.py b/test_regress/t/t_virtual_interface_member_trigger_real.py similarity index 56% rename from test_regress/t/t_virtual_interface_member_trigger_realistic_case.py rename to test_regress/t/t_virtual_interface_member_trigger_real.py index f1e665db3..567f18b29 100755 --- a/test_regress/t/t_virtual_interface_member_trigger_realistic_case.py +++ b/test_regress/t/t_virtual_interface_member_trigger_real.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_virtual_interface_member_trigger_realistic_case.v b/test_regress/t/t_virtual_interface_member_trigger_real.v old mode 100755 new mode 100644 similarity index 98% rename from test_regress/t/t_virtual_interface_member_trigger_realistic_case.v rename to test_regress/t/t_virtual_interface_member_trigger_real.v index 617f94732..11eef5026 --- a/test_regress/t/t_virtual_interface_member_trigger_realistic_case.v +++ b/test_regress/t/t_virtual_interface_member_trigger_real.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by PlanV GmbH. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ps diff --git a/test_regress/t/t_virtual_interface_method.py b/test_regress/t/t_virtual_interface_method.py index d2e0fe791..61fae108a 100755 --- a/test_regress/t/t_virtual_interface_method.py +++ b/test_regress/t/t_virtual_interface_method.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_virtual_interface_method.v b/test_regress/t/t_virtual_interface_method.v index 28e8c6003..d85419b3f 100644 --- a/test_regress/t/t_virtual_interface_method.v +++ b/test_regress/t/t_virtual_interface_method.v @@ -1,7 +1,7 @@ -// Copyright 2003 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // Create stimulus and Drive the interface class DriverStim; @@ -122,8 +122,8 @@ module t; initial begin: main - DriverStim driverStim = new(); - MonitorCheck monitorCheck = new(); + static DriverStim driverStim = new(); + static MonitorCheck monitorCheck = new(); driverStim.bind_if(example_if_inst); monitorCheck.bind_if(example_if_inst); diff --git a/test_regress/t/t_virtual_interface_method_bad.py b/test_regress/t/t_virtual_interface_method_bad.py index 2ce66844f..b6af58c86 100755 --- a/test_regress/t/t_virtual_interface_method_bad.py +++ b/test_regress/t/t_virtual_interface_method_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_virtual_interface_method_bad.v b/test_regress/t/t_virtual_interface_method_bad.v index 3b789011a..41af2735e 100644 --- a/test_regress/t/t_virtual_interface_method_bad.v +++ b/test_regress/t/t_virtual_interface_method_bad.v @@ -1,7 +1,7 @@ -// Copyright 2003 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 class ExampleClass; localparam NUM_TXNS = 10; @@ -27,7 +27,7 @@ module t; example_if example_if_inst(); initial begin: main - ExampleClass exampleClass = new(); + automatic ExampleClass exampleClass = new(); exampleClass.bind_if(example_if_inst); exampleClass.run(); diff --git a/test_regress/t/t_virtual_interface_nba_assign.py b/test_regress/t/t_virtual_interface_nba_assign.py new file mode 100755 index 000000000..4ee7f9e14 --- /dev/null +++ b/test_regress/t/t_virtual_interface_nba_assign.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_virtual_interface_nba_assign.v b/test_regress/t/t_virtual_interface_nba_assign.v new file mode 100644 index 000000000..b23443b61 --- /dev/null +++ b/test_regress/t/t_virtual_interface_nba_assign.v @@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +interface clk_if; + bit a; + bit clk; +endinterface + +interface inf; + bit clk; + bit v; + + clocking cb @(posedge clk); + inout v; + endclocking +endinterface + +class Clocker; + virtual clk_if clk; + + task clock(); + fork forever #1 clk.clk = ~clk.clk; + join_none + endtask +endclass + +module t; + clk_if c(); + inf i(); + assign i.clk = c.clk; + Clocker clocker; + initial begin + i.clk = 0; + i.v = 0; + clocker = new; + clocker.clk = c; + clocker.clock(); + i.cb.v <= 1; + #5; + $stop; + end + initial @(posedge i.cb.v) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_virtual_interface_only_with_assignw.py b/test_regress/t/t_virtual_interface_only_with_assignw.py new file mode 100755 index 000000000..46d1fe4c0 --- /dev/null +++ b/test_regress/t/t_virtual_interface_only_with_assignw.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_virtual_interface_only_with_assignw.v b/test_regress/t/t_virtual_interface_only_with_assignw.v new file mode 100644 index 000000000..04e1e2879 --- /dev/null +++ b/test_regress/t/t_virtual_interface_only_with_assignw.v @@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Antmicro Ltd +// SPDX-License-Identifier: CC0-1.0 + +interface sys_if; + logic clk; +endinterface + +interface axi_if; + wire clk; +endinterface + +class sys_config; + virtual sys_if sys_vi; +endclass + +class axi_agent_config; + virtual axi_if axi_vi; + sys_config cfg; + task start_clk(); + fork + forever begin + cfg.sys_vi.clk = 1'b1; + #1; + end + join_none + @(posedge axi_vi.clk); + endtask + task test(); + cfg.sys_vi.clk = 0; + #1; + start_clk(); + $write("*-* All Finished *-*\n"); + $finish; + endtask +endclass + +module axi_tb_top; + sys_if sys_vi (); + axi_if axi_vi (); + assign axi_vi.clk = sys_vi.clk; + sys_config a; + axi_agent_config b; + initial begin + a = new; + b = new; + a.sys_vi = sys_vi; + b.axi_vi = axi_vi; + b.cfg = a; + b.test(); + #3 $stop; + end +endmodule diff --git a/test_regress/t/t_virtual_interface_param.py b/test_regress/t/t_virtual_interface_param.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_virtual_interface_param.py +++ b/test_regress/t/t_virtual_interface_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_virtual_interface_param.v b/test_regress/t/t_virtual_interface_param.v index 032c01fd2..529f4ae43 100644 --- a/test_regress/t/t_virtual_interface_param.v +++ b/test_regress/t/t_virtual_interface_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface b_if #( @@ -14,8 +14,8 @@ module t; m #(.p(2)) m_i (); initial begin - virtual b_if #(2) vif = m_i.b; - int y = m_i.b.x; + automatic virtual b_if #(2) vif = m_i.b; + automatic int y = m_i.b.x; if (vif.x != 2) $stop; if (y != 2) $stop; diff --git a/test_regress/t/t_virtual_interface_param_bind.py b/test_regress/t/t_virtual_interface_param_bind.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_virtual_interface_param_bind.py +++ b/test_regress/t/t_virtual_interface_param_bind.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_virtual_interface_param_bind.v b/test_regress/t/t_virtual_interface_param_bind.v index 483166c3a..72b87ddeb 100644 --- a/test_regress/t/t_virtual_interface_param_bind.v +++ b/test_regress/t/t_virtual_interface_param_bind.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 interface b_if; @@ -14,8 +14,8 @@ module t; typedef virtual b_if vif_t; initial begin - vif_t vif = t.m_i.if_bind; - int y = t.m_i.if_bind.x; + automatic vif_t vif = t.m_i.if_bind; + automatic int y = t.m_i.if_bind.x; if (vif.x != 1) $stop; if (y != 1) $stop; diff --git a/test_regress/t/t_virtual_interface_pkg.py b/test_regress/t/t_virtual_interface_pkg.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_virtual_interface_pkg.py +++ b/test_regress/t/t_virtual_interface_pkg.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_virtual_interface_pkg.v b/test_regress/t/t_virtual_interface_pkg.v index 0167863c1..8d94418b4 100644 --- a/test_regress/t/t_virtual_interface_pkg.v +++ b/test_regress/t/t_virtual_interface_pkg.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Yilou Wang. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Yilou Wang // SPDX-License-Identifier: CC0-1.0 package my_pkg; diff --git a/test_regress/t/t_vlcov_debugi.py b/test_regress/t/t_vlcov_debugi.py index b3d310b71..a8d57ece9 100755 --- a/test_regress/t/t_vlcov_debugi.py +++ b/test_regress/t/t_vlcov_debugi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_flag_invalid_bad.py b/test_regress/t/t_vlcov_flag_invalid_bad.py index 8e3fec647..5d95d4575 100755 --- a/test_regress/t/t_vlcov_flag_invalid_bad.py +++ b/test_regress/t/t_vlcov_flag_invalid_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_info.py b/test_regress/t/t_vlcov_info.py index 19def3282..a4ed84de9 100755 --- a/test_regress/t/t_vlcov_info.py +++ b/test_regress/t/t_vlcov_info.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_merge.py b/test_regress/t/t_vlcov_merge.py index 271a8d1c7..44639a512 100755 --- a/test_regress/t/t_vlcov_merge.py +++ b/test_regress/t/t_vlcov_merge.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_nfound_bad.py b/test_regress/t/t_vlcov_nfound_bad.py index d435f38ee..a38c79391 100755 --- a/test_regress/t/t_vlcov_nfound_bad.py +++ b/test_regress/t/t_vlcov_nfound_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_opt_branch.py b/test_regress/t/t_vlcov_opt_branch.py index d784b9006..88a3b1cd2 100755 --- a/test_regress/t/t_vlcov_opt_branch.py +++ b/test_regress/t/t_vlcov_opt_branch.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_opt_expr.py b/test_regress/t/t_vlcov_opt_expr.py index 4fa8200d2..2672c395a 100755 --- a/test_regress/t/t_vlcov_opt_expr.py +++ b/test_regress/t/t_vlcov_opt_expr.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_opt_line.py b/test_regress/t/t_vlcov_opt_line.py index f5f4b8195..ece30cd93 100755 --- a/test_regress/t/t_vlcov_opt_line.py +++ b/test_regress/t/t_vlcov_opt_line.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_opt_toggle.py b/test_regress/t/t_vlcov_opt_toggle.py index 49da6830d..4371d9893 100755 --- a/test_regress/t/t_vlcov_opt_toggle.py +++ b/test_regress/t/t_vlcov_opt_toggle.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_opt_user.py b/test_regress/t/t_vlcov_opt_user.py index 805813778..38fe3c837 100755 --- a/test_regress/t/t_vlcov_opt_user.py +++ b/test_regress/t/t_vlcov_opt_user.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_opt_wild.py b/test_regress/t/t_vlcov_opt_wild.py index 7fea40269..7a3a1c94f 100755 --- a/test_regress/t/t_vlcov_opt_wild.py +++ b/test_regress/t/t_vlcov_opt_wild.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_rank.py b/test_regress/t/t_vlcov_rank.py index 6013b047c..19a71718f 100755 --- a/test_regress/t/t_vlcov_rank.py +++ b/test_regress/t/t_vlcov_rank.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_rewrite.py b/test_regress/t/t_vlcov_rewrite.py index 91fdfa1d0..c2eead44b 100755 --- a/test_regress/t/t_vlcov_rewrite.py +++ b/test_regress/t/t_vlcov_rewrite.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlcov_unlink.py b/test_regress/t/t_vlcov_unlink.py index 90f9428f4..3b63aadf1 100755 --- a/test_regress/t/t_vlcov_unlink.py +++ b/test_regress/t/t_vlcov_unlink.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlprocess_missing.py b/test_regress/t/t_vlprocess_missing.py index 35076ad18..0a6cf5898 100755 --- a/test_regress/t/t_vlprocess_missing.py +++ b/test_regress/t/t_vlprocess_missing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_legacy.py b/test_regress/t/t_vlt_legacy.py index 7437ff992..4c820dfa1 100755 --- a/test_regress/t/t_vlt_legacy.py +++ b/test_regress/t/t_vlt_legacy.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_legacy.v b/test_regress/t/t_vlt_legacy.v index 8b389fdf1..efb3e17f6 100644 --- a/test_regress/t/t_vlt_legacy.v +++ b/test_regress/t/t_vlt_legacy.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_vlt_legacy.vlt b/test_regress/t/t_vlt_legacy.vlt index 7bd9adc07..d959b2289 100644 --- a/test_regress/t/t_vlt_legacy.vlt +++ b/test_regress/t/t_vlt_legacy.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_match_contents.py b/test_regress/t/t_vlt_match_contents.py index 1c0bcea9a..5e720b678 100755 --- a/test_regress/t/t_vlt_match_contents.py +++ b/test_regress/t/t_vlt_match_contents.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_match_contents.v b/test_regress/t/t_vlt_match_contents.v index dc1c5d6fe..7991f2d90 100644 --- a/test_regress/t/t_vlt_match_contents.v +++ b/test_regress/t/t_vlt_match_contents.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Ethan Sifferman. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Ethan Sifferman // SPDX-License-Identifier: CC0-1.0 string MATCH_VERSION = "10.20"; diff --git a/test_regress/t/t_vlt_match_contents.vlt b/test_regress/t/t_vlt_match_contents.vlt index e568f5af0..55ebc3483 100644 --- a/test_regress/t/t_vlt_match_contents.vlt +++ b/test_regress/t/t_vlt_match_contents.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Ethan Sifferman. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Ethan Sifferman // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_match_error.v b/test_regress/t/t_vlt_match_error.v index 762d1daf5..a6a7f0447 100644 --- a/test_regress/t/t_vlt_match_error.v +++ b/test_regress/t/t_vlt_match_error.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Ethan Sifferman. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Ethan Sifferman // SPDX-License-Identifier: CC0-1.0 module DECLFILENAME; diff --git a/test_regress/t/t_vlt_match_error.vlt b/test_regress/t/t_vlt_match_error.vlt index 7b6aa8e7f..64c0d4cf7 100644 --- a/test_regress/t/t_vlt_match_error.vlt +++ b/test_regress/t/t_vlt_match_error.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Ethan Sifferman. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Ethan Sifferman // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_match_error_1.py b/test_regress/t/t_vlt_match_error_1.py index 209cca7be..6ff21feb1 100755 --- a/test_regress/t/t_vlt_match_error_1.py +++ b/test_regress/t/t_vlt_match_error_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_match_error_2.py b/test_regress/t/t_vlt_match_error_2.py index 3d67fbdd1..e586d0fdf 100755 --- a/test_regress/t/t_vlt_match_error_2.py +++ b/test_regress/t/t_vlt_match_error_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_match_error_3.py b/test_regress/t/t_vlt_match_error_3.py index c7d750e2c..70e9b89eb 100755 --- a/test_regress/t/t_vlt_match_error_3.py +++ b/test_regress/t/t_vlt_match_error_3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_public_spec.py b/test_regress/t/t_vlt_public_spec.py index 01e358441..4798ba0c4 100755 --- a/test_regress/t/t_vlt_public_spec.py +++ b/test_regress/t/t_vlt_public_spec.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_public_spec.v b/test_regress/t/t_vlt_public_spec.v index 7a166825e..166b37f89 100644 --- a/test_regress/t/t_vlt_public_spec.v +++ b/test_regress/t/t_vlt_public_spec.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_vlt_public_spec.vlt b/test_regress/t/t_vlt_public_spec.vlt index fc1a202d3..6d4fa1ef2 100644 --- a/test_regress/t/t_vlt_public_spec.vlt +++ b/test_regress/t/t_vlt_public_spec.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_syntax_bad.py b/test_regress/t/t_vlt_syntax_bad.py index 90b3aecba..73cb205ca 100755 --- a/test_regress/t/t_vlt_syntax_bad.py +++ b/test_regress/t/t_vlt_syntax_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_syntax_bad.v b/test_regress/t/t_vlt_syntax_bad.v index 0f1777e05..13d882f59 100644 --- a/test_regress/t/t_vlt_syntax_bad.v +++ b/test_regress/t/t_vlt_syntax_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_vlt_syntax_bad.vlt b/test_regress/t/t_vlt_syntax_bad.vlt index 129141465..2ebcefa7c 100644 --- a/test_regress/t/t_vlt_syntax_bad.vlt +++ b/test_regress/t/t_vlt_syntax_bad.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_timing.py b/test_regress/t/t_vlt_timing.py index 7c4d12ae4..23cc86544 100755 --- a/test_regress/t/t_vlt_timing.py +++ b/test_regress/t/t_vlt_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_timing.v b/test_regress/t/t_vlt_timing.v index 8472ae6b5..ccf2fa2a4 100644 --- a/test_regress/t/t_vlt_timing.v +++ b/test_regress/t/t_vlt_timing.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_vlt_timing.vlt b/test_regress/t/t_vlt_timing.vlt index d35c3a5d6..16e738099 100644 --- a/test_regress/t/t_vlt_timing.vlt +++ b/test_regress/t/t_vlt_timing.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_var_sc_biguint_bad.py b/test_regress/t/t_vlt_var_sc_biguint_bad.py index f9df35643..b041f5b52 100755 --- a/test_regress/t/t_vlt_var_sc_biguint_bad.py +++ b/test_regress/t/t_vlt_var_sc_biguint_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_var_sc_biguint_bad.vlt b/test_regress/t/t_vlt_var_sc_biguint_bad.vlt index 5f0ac35b3..2e2ab2b3b 100644 --- a/test_regress/t/t_vlt_var_sc_biguint_bad.vlt +++ b/test_regress/t/t_vlt_var_sc_biguint_bad.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Antmicro. +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2025 Antmicro // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_var_spec_bad.py b/test_regress/t/t_vlt_var_spec_bad.py index f9df35643..b041f5b52 100755 --- a/test_regress/t/t_vlt_var_spec_bad.py +++ b/test_regress/t/t_vlt_var_spec_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_var_spec_bad.vlt b/test_regress/t/t_vlt_var_spec_bad.vlt index 85b26f6a7..ac0078c79 100644 --- a/test_regress/t/t_vlt_var_spec_bad.vlt +++ b/test_regress/t/t_vlt_var_spec_bad.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_warn.py b/test_regress/t/t_vlt_warn.py index 4260c4bdc..3860afadd 100755 --- a/test_regress/t/t_vlt_warn.py +++ b/test_regress/t/t_vlt_warn.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_warn.v b/test_regress/t/t_vlt_warn.v index 7fdd59c36..99285a4ab 100644 --- a/test_regress/t/t_vlt_warn.v +++ b/test_regress/t/t_vlt_warn.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // Try inline config diff --git a/test_regress/t/t_vlt_warn.vlt b/test_regress/t/t_vlt_warn.vlt index e850e9fd8..f6f589ba0 100644 --- a/test_regress/t/t_vlt_warn.vlt +++ b/test_regress/t/t_vlt_warn.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_warn_bad.py b/test_regress/t/t_vlt_warn_bad.py index b06923482..ef78578ba 100755 --- a/test_regress/t/t_vlt_warn_bad.py +++ b/test_regress/t/t_vlt_warn_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_warn_bad.vlt b/test_regress/t/t_vlt_warn_bad.vlt index 323ae27fa..2a8319454 100644 --- a/test_regress/t/t_vlt_warn_bad.vlt +++ b/test_regress/t/t_vlt_warn_bad.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_warn_ecode_bad.py b/test_regress/t/t_vlt_warn_ecode_bad.py index b89538328..338666d51 100755 --- a/test_regress/t/t_vlt_warn_ecode_bad.py +++ b/test_regress/t/t_vlt_warn_ecode_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_warn_ecode_bad.vlt b/test_regress/t/t_vlt_warn_ecode_bad.vlt index af0780399..1e3185e70 100644 --- a/test_regress/t/t_vlt_warn_ecode_bad.vlt +++ b/test_regress/t/t_vlt_warn_ecode_bad.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_warn_file2_bad.py b/test_regress/t/t_vlt_warn_file2_bad.py index 6b6b023e4..54ac3c90e 100755 --- a/test_regress/t/t_vlt_warn_file2_bad.py +++ b/test_regress/t/t_vlt_warn_file2_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_warn_file2_bad.v b/test_regress/t/t_vlt_warn_file2_bad.v index aa761484f..b4c649b43 100644 --- a/test_regress/t/t_vlt_warn_file2_bad.v +++ b/test_regress/t/t_vlt_warn_file2_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef verilator diff --git a/test_regress/t/t_vlt_warn_file_bad.py b/test_regress/t/t_vlt_warn_file_bad.py index 35484f938..43b2a05e8 100755 --- a/test_regress/t/t_vlt_warn_file_bad.py +++ b/test_regress/t/t_vlt_warn_file_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_warn_file_bad.v b/test_regress/t/t_vlt_warn_file_bad.v index 89ef7bfc2..47dcc0ad1 100644 --- a/test_regress/t/t_vlt_warn_file_bad.v +++ b/test_regress/t/t_vlt_warn_file_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `include "t_vlt_warn_file_bad_b.vh" diff --git a/test_regress/t/t_vlt_warn_file_bad.vlt b/test_regress/t/t_vlt_warn_file_bad.vlt index 14107e8a0..543bb9937 100644 --- a/test_regress/t/t_vlt_warn_file_bad.vlt +++ b/test_regress/t/t_vlt_warn_file_bad.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_warn_file_bad_b.vh b/test_regress/t/t_vlt_warn_file_bad_b.vh index bf1bb1067..f97aad506 100644 --- a/test_regress/t/t_vlt_warn_file_bad_b.vh +++ b/test_regress/t/t_vlt_warn_file_bad_b.vh @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module sub; diff --git a/test_regress/t/t_vlt_warn_one_on_bad.py b/test_regress/t/t_vlt_warn_one_on_bad.py index 6b6b023e4..54ac3c90e 100755 --- a/test_regress/t/t_vlt_warn_one_on_bad.py +++ b/test_regress/t/t_vlt_warn_one_on_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_warn_one_on_bad.v b/test_regress/t/t_vlt_warn_one_on_bad.v index a43270f7d..1fbadba29 100644 --- a/test_regress/t/t_vlt_warn_one_on_bad.v +++ b/test_regress/t/t_vlt_warn_one_on_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef verilator diff --git a/test_regress/t/t_vlt_warn_range_bad.py b/test_regress/t/t_vlt_warn_range_bad.py index 6b6b023e4..54ac3c90e 100755 --- a/test_regress/t/t_vlt_warn_range_bad.py +++ b/test_regress/t/t_vlt_warn_range_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vlt_warn_range_bad.v b/test_regress/t/t_vlt_warn_range_bad.v index 8c045e32a..5215f16d9 100644 --- a/test_regress/t/t_vlt_warn_range_bad.v +++ b/test_regress/t/t_vlt_warn_range_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `ifdef verilator diff --git a/test_regress/t/t_vpi_cb_iter.cpp b/test_regress/t/t_vpi_cb_iter.cpp index d98fe968c..611c06f0d 100644 --- a/test_regress/t/t_vpi_cb_iter.cpp +++ b/test_regress/t/t_vpi_cb_iter.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder and Marlon James // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_cb_iter.py b/test_regress/t/t_vpi_cb_iter.py index 663e45330..88d019a3e 100755 --- a/test_regress/t/t_vpi_cb_iter.py +++ b/test_regress/t/t_vpi_cb_iter.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_cb_iter.v b/test_regress/t/t_vpi_cb_iter.v index 9c4d0fa91..c29aa6eb7 100644 --- a/test_regress/t/t_vpi_cb_iter.v +++ b/test_regress/t/t_vpi_cb_iter.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Wilson Snyder and Marlon James. +// SPDX-FileCopyrightText: 2020 Wilson Snyder and Marlon James // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_vpi_const_type.cpp b/test_regress/t/t_vpi_const_type.cpp index 5efd97175..e1f8d886b 100644 --- a/test_regress/t/t_vpi_const_type.cpp +++ b/test_regress/t/t_vpi_const_type.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_const_type.py b/test_regress/t/t_vpi_const_type.py index 61cf61c9e..136827742 100755 --- a/test_regress/t/t_vpi_const_type.py +++ b/test_regress/t/t_vpi_const_type.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_const_type.v b/test_regress/t/t_vpi_const_type.v index 2ae4e2f59..df13f23f4 100644 --- a/test_regress/t/t_vpi_const_type.v +++ b/test_regress/t/t_vpi_const_type.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" context function int mon_check(); diff --git a/test_regress/t/t_vpi_dump.cpp b/test_regress/t/t_vpi_dump.cpp index cf2147e54..6e9e9d950 100644 --- a/test_regress/t/t_vpi_dump.cpp +++ b/test_regress/t/t_vpi_dump.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_dump.py b/test_regress/t/t_vpi_dump.py index 218f5e912..89b8841ed 100755 --- a/test_regress/t/t_vpi_dump.py +++ b/test_regress/t/t_vpi_dump.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_dump.v b/test_regress/t/t_vpi_dump.v index 2c553e88d..81ea91a8d 100644 --- a/test_regress/t/t_vpi_dump.v +++ b/test_regress/t/t_vpi_dump.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 /* verilator public_on */ diff --git a/test_regress/t/t_vpi_dump_missing_scopes.py b/test_regress/t/t_vpi_dump_missing_scopes.py index 686d688f4..a762066ee 100755 --- a/test_regress/t/t_vpi_dump_missing_scopes.py +++ b/test_regress/t/t_vpi_dump_missing_scopes.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_dump_missing_scopes.v b/test_regress/t/t_vpi_dump_missing_scopes.v index f35f3862a..c97803e7e 100644 --- a/test_regress/t/t_vpi_dump_missing_scopes.v +++ b/test_regress/t/t_vpi_dump_missing_scopes.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 diff --git a/test_regress/t/t_vpi_dump_no_inline.py b/test_regress/t/t_vpi_dump_no_inline.py index 2f7379242..e15bbd2a9 100755 --- a/test_regress/t/t_vpi_dump_no_inline.py +++ b/test_regress/t/t_vpi_dump_no_inline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_escape.cpp b/test_regress/t/t_vpi_escape.cpp index 03f206e88..929c30109 100644 --- a/test_regress/t/t_vpi_escape.cpp +++ b/test_regress/t/t_vpi_escape.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2023 by Wilson Snyder and Marlon James. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2023 Wilson Snyder and Marlon James // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_escape.py b/test_regress/t/t_vpi_escape.py index dcc91956c..ad5236557 100755 --- a/test_regress/t/t_vpi_escape.py +++ b/test_regress/t/t_vpi_escape.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_escape.v b/test_regress/t/t_vpi_escape.v index 4c2a8ecc7..8d02fee8c 100644 --- a/test_regress/t/t_vpi_escape.v +++ b/test_regress/t/t_vpi_escape.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010-2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI diff --git a/test_regress/t/t_vpi_escape.vlt b/test_regress/t/t_vpi_escape.vlt index 409c71fc8..15bf559f6 100644 --- a/test_regress/t/t_vpi_escape.vlt +++ b/test_regress/t/t_vpi_escape.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vpi_finish.py b/test_regress/t/t_vpi_finish.py index 34a4cc6f1..7ddfb7429 100755 --- a/test_regress/t/t_vpi_finish.py +++ b/test_regress/t/t_vpi_finish.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_finish.v b/test_regress/t/t_vpi_finish.v index dcde332c8..e626020b4 100644 --- a/test_regress/t/t_vpi_finish.v +++ b/test_regress/t/t_vpi_finish.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_vpi_finish_c.cpp b/test_regress/t/t_vpi_finish_c.cpp index 27563051d..2c83b02c6 100644 --- a/test_regress/t/t_vpi_finish_c.cpp +++ b/test_regress/t/t_vpi_finish_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_force.cpp b/test_regress/t/t_vpi_force.cpp new file mode 100644 index 000000000..949f0d075 --- /dev/null +++ b/test_regress/t/t_vpi_force.cpp @@ -0,0 +1,876 @@ +// ====================================================================== +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Christian Hecken +// SPDX-License-Identifier: CC0-1.0 +// ====================================================================== + +// DESCRIPTION: vpi force and release test +// +// This test checks that forcing a signal using vpi_put_value with vpiForceFlag +// sets it to the correct value, and then releasing it with vpiReleaseFlag +// returns it to the initial state. + +#include "verilated.h" // For VL_PRINTF +#include "verilated_sym_props.h" // For VerilatedVar +#include "verilated_syms.h" // For VerilatedVarNameMap +#include "verilated_vpi.h" // For VerilatedVpi::doInertialPuts(); + +#include "TestSimulator.h" // For is_verilator() +#include "TestVpi.h" // For CHECK_RESULT_NZ +#include "vpi_user.h" + +#include +#include // For std::unique_ptr + +namespace { + +constexpr int maxAllowedErrorLevel = vpiWarning; +const std::string scopeName = "t.test"; + +using signalValueTypes = union { + const char* str; + PLI_INT32 integer; + double real; + const struct t_vpi_vecval* vector; +}; + +using TestSignal = const struct { + const char* signalName; + PLI_INT32 valueType; + signalValueTypes releaseValue; + signalValueTypes forceValue; + std::pair + partialForceValue; // No std::optional on C++14, so the bool inside the pair is used to + // specify if a partial force should be tested for this signal. For a + // partial force, the first part of the signal is left at the release + // value, while the second part is forced to the force value. +}; + +constexpr std::array TestSignals = { + TestSignal{"onebit", + vpiIntVal, + {.integer = 1}, + {.integer = 0}, + {{}, false}}, // Can't partially force just one bit + TestSignal{"intval", + vpiIntVal, + {.integer = -1431655766}, // 1010...1010 + {.integer = 0x55555555}, // 0101...0101 + {{.integer = -1431677611}, true}}, // 1010...010_010...0101 + + TestSignal{"vectorC", + vpiVectorVal, + // NOLINTBEGIN (cppcoreguidelines-avoid-c-arrays) + {.vector = (t_vpi_vecval[]){{0b10101010, 0}}}, + {.vector = (t_vpi_vecval[]){{0b01010101, 0}}}, + {{.vector = (t_vpi_vecval[]){{0b10100101, 0}}}, true}}, + // NOLINTEND (cppcoreguidelines-avoid-c-arrays) + + TestSignal{ + "vectorQ", + vpiVectorVal, + // NOTE: This is a 62 bit signal, so the first two bits of the MSBs (*second* vecval, + // since the LSBs come first) are set to 0, hence the 0x2 and 0x1, respectively. + + // NOLINTBEGIN (cppcoreguidelines-avoid-c-arrays) + {.vector = (t_vpi_vecval[]){{0xAAAAAAAAUL, 0}, {0x2AAAAAAAUL, 0}}}, // (00)1010...1010 + {.vector = (t_vpi_vecval[]){{0x55555555UL, 0}, {0x15555555UL, 0}}}, // (00)0101...0101 + {{.vector = (t_vpi_vecval[]){{0xD5555555UL, 0}, {0x2AAAAAAAUL, 0}}}, + true}}, // 1010...010_010...0101 + // NOLINTEND (cppcoreguidelines-avoid-c-arrays) + + TestSignal{"vectorW", + vpiVectorVal, + // NOLINTBEGIN (cppcoreguidelines-avoid-c-arrays) + {.vector = (t_vpi_vecval[]){{0xAAAAAAAAUL, 0}, // 1010...1010 + {0xAAAAAAAAUL, 0}, + {0xAAAAAAAAUL, 0}, + {0xAAAAAAAAUL, 0}}}, + {.vector = (t_vpi_vecval[]){{0x55555555UL, 0}, // 0101...0101 + {0x55555555UL, 0}, + {0x55555555UL, 0}, + {0x55555555UL, 0}}}, + {{.vector = (t_vpi_vecval[]){{0x55555555UL, 0}, // 1010...010_010...0101 + {0x55555555UL, 0}, + {0xAAAAAAAAUL, 0}, + {0xAAAAAAAAUL, 0}}}, + true}}, + // NOLINTEND (cppcoreguidelines-avoid-c-arrays) + + TestSignal{"real1", + vpiRealVal, + {.real = 1.0}, + {.real = 123456.789}, + {{}, false}}, // reals cannot be packed and individual bits cannot be accessed, so + // there is no way to partially force a real signal. + + TestSignal{"textHalf", vpiStringVal, {.str = "Hf"}, {.str = "T2"}, {{.str = "H2"}, true}}, + TestSignal{"textLong", + vpiStringVal, + {.str = "Long64b"}, + {.str = "44Four44"}, + {{.str = "Lonur44"}, true}}, + TestSignal{"text", + vpiStringVal, + {.str = "Verilog Test module"}, + {.str = "lorem ipsum"}, + {{.str = "Verilog Tesem ipsum"}, true}}, + + TestSignal{"binString", + vpiBinStrVal, + {.str = "10101010"}, + {.str = "01010101"}, + {{.str = "10100101"}, true}}, + TestSignal{"octString", + vpiOctStrVal, + {.str = "25252"}, // 010101010101010 + {.str = "52525"}, // 101010101010101 + {{.str = "25325"}, true}}, // 010101011010101 + TestSignal{"hexString", + vpiHexStrVal, + {.str = "aaaaaaaaaaaaaaaa"}, // 1010...1010 + {.str = "5555555555555555"}, // 0101...0101 + {{.str = "aaaaaaaa55555555"}, true}}, // 1010...010_010...0101 + + TestSignal{"decStringC", + vpiDecStrVal, + {.str = "170"}, // 10101010 + {.str = "85"}, // 01010101 + {{.str = "165"}, true}}, // 10100101 + TestSignal{"decStringS", + vpiDecStrVal, + {.str = "43690"}, // 1010...1010 + {.str = "21845"}, // 0101...0101 + {{.str = "43605"}, true}}, // 1010...010_010...0101 + TestSignal{"decStringI", + vpiDecStrVal, + {.str = "2863311530"}, // 1010...1010 + {.str = "1431655765"}, // 0101...0101 + {{.str = "2863289685"}, true}}, // 1010...010_010...0101 + TestSignal{"decStringQ", + vpiDecStrVal, + {.str = "12297829382473034410"}, // 1010...1010 + {.str = "6148914691236517205"}, // 0101...0101 + {{.str = "12297829381041378645"}, true}}, // 1010...010_010...0101 +}; + +bool vpiCheckErrorLevel(const int maxAllowedErrorLevel) { + t_vpi_error_info errorInfo{}; + const bool errorOccured = vpi_chk_error(&errorInfo); + if (VL_UNLIKELY(errorOccured)) { + VL_PRINTF("%s", errorInfo.message); + return errorInfo.level > maxAllowedErrorLevel; + } + return false; +} + +std::pair vpiGetErrorMessage() { + t_vpi_error_info errorInfo{}; + const bool errorOccured = vpi_chk_error(&errorInfo); + return {errorOccured ? errorInfo.message : std::string{}, errorOccured}; +} + +#ifdef VERILATOR // m_varsp is Verilator-specific and does not make sense for other simulators +std::unique_ptr removeSignalFromScope(const std::string& scopeName, + const std::string& signalName) { + const VerilatedScope* const scopep = Verilated::threadContextp()->scopeFind(scopeName.c_str()); + if (!scopep) return nullptr; + VerilatedVarNameMap* const varsp = scopep->varsp(); + const VerilatedVarNameMap::const_iterator foundSignalIt = varsp->find(signalName.c_str()); + if (foundSignalIt == varsp->end()) return nullptr; + VerilatedVar foundSignal = foundSignalIt->second; + varsp->erase(foundSignalIt); + return std::make_unique(foundSignal); +} + +bool insertSignalIntoScope(const std::pair& scopeAndSignalNames, + const std::unique_ptr signal) { + const std::string& scopeName = scopeAndSignalNames.first; + const std::string& signalName = scopeAndSignalNames.second; + + const VerilatedScope* const scopep = Verilated::threadContextp()->scopeFind(scopeName.c_str()); + if (!scopep) return false; + VerilatedVarNameMap* const varsp = scopep->varsp(); + + // NOTE: The lifetime of the name inserted into varsp must be the same as the scopep, i.e. the + // same as threadContextp. Otherwise, the key in the m_varsp map will be a stale pointer. + // Hence, names of signals being inserted are stored in the static set, and it is assumed that + // the set's lifetime is the same as the threadContextp. + static std::set insertedSignalNames; + const auto insertedSignalName = insertedSignalNames.insert(signalName); + + varsp->insert( + std::pair{insertedSignalName.first->c_str(), *signal}); + return true; +} + +int tryVpiGetWithMissingSignal(const TestVpiHandle& signalToGet, // NOLINT(misc-misplaced-const) + const PLI_INT32 signalFormat, + const std::pair& scopeAndSignalNames, + const std::string& expectedErrorMessage) { + const std::string& scopeName = scopeAndSignalNames.first; + const std::string& signalNameToRemove = scopeAndSignalNames.second; + std::unique_ptr removedSignal + = removeSignalFromScope(scopeName, signalNameToRemove); + CHECK_RESULT_NZ(removedSignal); // NOLINT(concurrency-mt-unsafe) + + s_vpi_value value_s{.format = signalFormat, .value = {}}; + + // Prevent program from terminating, so error message can be collected + Verilated::fatalOnVpiError(false); + vpi_get_value(signalToGet, &value_s); + // Re-enable so tests that should pass properly terminate the simulation on failure + Verilated::fatalOnVpiError(true); + + std::pair receivedError = vpiGetErrorMessage(); + const bool errorOccurred = receivedError.second; + const std::string receivedErrorMessage = receivedError.first; + CHECK_RESULT_NZ(errorOccurred); // NOLINT(concurrency-mt-unsafe) + + // NOLINTNEXTLINE(concurrency-mt-unsafe,performance-avoid-endl) + CHECK_RESULT(receivedErrorMessage, expectedErrorMessage); + bool insertSuccess + = insertSignalIntoScope({scopeName, signalNameToRemove}, std::move(removedSignal)); + CHECK_RESULT_NZ(insertSuccess); // NOLINT(concurrency-mt-unsafe) + return 0; +} + +int tryVpiPutWithMissingSignal(const s_vpi_value value_s, + const TestVpiHandle& signalToPut, // NOLINT(misc-misplaced-const) + const int flag, const std::string& scopeName, + const std::string& signalNameToRemove, + const std::vector& expectedErrorMessageSubstrings) { + std::unique_ptr removedSignal + = removeSignalFromScope(scopeName, signalNameToRemove); + CHECK_RESULT_NZ(removedSignal); // NOLINT(concurrency-mt-unsafe) + + // Prevent program from terminating, so error message can be collected + Verilated::fatalOnVpiError(false); + vpi_put_value(signalToPut, const_cast(&value_s), nullptr, flag); + // Re-enable so tests that should pass properly terminate the simulation on failure + Verilated::fatalOnVpiError(true); + + std::pair receivedError = vpiGetErrorMessage(); + const bool errorOccurred = receivedError.second; + const std::string receivedErrorMessage = receivedError.first; + CHECK_RESULT_NZ(errorOccurred); // NOLINT(concurrency-mt-unsafe) + + const bool allExpectedErrorSubstringsFound + = std::all_of(expectedErrorMessageSubstrings.begin(), expectedErrorMessageSubstrings.end(), + [receivedErrorMessage](const std::string& expectedSubstring) { + return receivedErrorMessage.find(expectedSubstring) != std::string::npos; + }); + CHECK_RESULT_NZ(allExpectedErrorSubstringsFound); // NOLINT(concurrency-mt-unsafe) + bool insertSuccess + = insertSignalIntoScope({scopeName, signalNameToRemove}, std::move(removedSignal)); + CHECK_RESULT_NZ(insertSuccess); // NOLINT(concurrency-mt-unsafe) + return 0; +} + +// Simpler function that expects an exact string instead of a number of substrings, and just a +// signalName instead of a handle. +int expectVpiPutError(const std::string& signalName, s_vpi_value value_s, const int flag, + const std::string& expectedErrorMessage) { + const std::string fullSignalName = std::string{scopeName} + "." + signalName; + TestVpiHandle const signalHandle //NOLINT(misc-misplaced-const) + = vpi_handle_by_name(const_cast(fullSignalName.c_str()), nullptr); + CHECK_RESULT_NZ(signalHandle); // NOLINT(concurrency-mt-unsafe) + + // Prevent program from terminating, so error message can be collected + Verilated::fatalOnVpiError(false); + vpi_put_value(signalHandle, &value_s, nullptr, flag); + // Re-enable so tests that should pass properly terminate the simulation on failure + Verilated::fatalOnVpiError(true); + + std::pair receivedError = vpiGetErrorMessage(); + const bool errorOccurred = receivedError.second; + const std::string receivedErrorMessage = receivedError.first; + CHECK_RESULT_NZ(errorOccurred); // NOLINT(concurrency-mt-unsafe) + + // NOLINTNEXTLINE(concurrency-mt-unsafe,performance-avoid-endl) + CHECK_RESULT(receivedErrorMessage, expectedErrorMessage); + return 0; +} + +#endif + +bool vpiValuesEqual(const std::size_t bitCount, const s_vpi_value& first, + const s_vpi_value& second) { + if (first.format != second.format) return false; + switch (first.format) { + case vpiIntVal: return first.value.integer == second.value.integer; break; + case vpiVectorVal: { + const t_vpi_vecval* const firstVecval = first.value.vector; + const t_vpi_vecval* const secondVecval = second.value.vector; + const std::size_t vectorElements = (bitCount + 31) / 32; // Ceil + for (std::size_t i{0}; i < vectorElements; ++i) { + if (firstVecval[i].aval != secondVecval[i].aval) return false; + } + return true; + } + case vpiRealVal: + return std::abs(first.value.real - second.value.real) + < std::numeric_limits::epsilon(); + break; + case vpiStringVal: + case vpiBinStrVal: + case vpiOctStrVal: + case vpiDecStrVal: + case vpiHexStrVal: { + // Same as CHECK_RESULT_CSTR_STRIP, but should return true when equal, false otherwise + const std::string firstUnpadded = first.value.str + std::strspn(first.value.str, " "); + return std::string{firstUnpadded} == std::string{second.value.str}; + break; + } + default: + VL_PRINTF("Unsupported value format %i passed to vpiValuesEqual\n", first.format); + return false; + } +} + +std::unique_ptr vpiValueWithFormat(const PLI_INT32 signalFormat, + const signalValueTypes value) { + std::unique_ptr value_sp = std::make_unique(); + value_sp->format = signalFormat; + + switch (signalFormat) { + case vpiIntVal: value_sp->value = {.integer = value.integer}; break; + case vpiVectorVal: value_sp->value = {.vector = const_cast(value.vector)}; break; + case vpiRealVal: value_sp->value = {.real = value.real}; break; + case vpiStringVal: + case vpiBinStrVal: + case vpiOctStrVal: + case vpiDecStrVal: + case vpiHexStrVal: value_sp->value = {.str = const_cast(value.str)}; break; + default: + VL_PRINTF("Unsupported value format %i passed to vpiValueWithFormat\n", signalFormat); + return nullptr; + } + + return value_sp; +} + +int checkValue(const std::string& scopeName, const std::string& testSignalName, + const PLI_INT32 signalFormat, const signalValueTypes expectedValue) { + const std::string testSignalFullName + = std::string{scopeName} + "." + std::string{testSignalName}; + TestVpiHandle const signalHandle //NOLINT(misc-misplaced-const) + = vpi_handle_by_name(const_cast(testSignalFullName.c_str()), nullptr); + CHECK_RESULT_NZ(signalHandle); // NOLINT(concurrency-mt-unsafe) + +#ifdef VERILATOR + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(tryVpiGetWithMissingSignal( + signalHandle, signalFormat, {scopeName, testSignalName + "__VforceEn"}, + "vl_vpi_get_value: Signal '" + testSignalFullName + + "' is marked forceable, but force control signals could not be retrieved. Error " + "message: getForceControlSignals: VPI force or release requested for '" + + testSignalFullName + "', but vpiHandle '(nil)' of enable signal '" + + testSignalFullName + + "__VforceEn' could not be cast to VerilatedVpioVar*. Ensure signal is marked as " + "forceable")); + + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(tryVpiGetWithMissingSignal( + signalHandle, signalFormat, {scopeName, testSignalName + "__VforceVal"}, + "vl_vpi_get_value: Signal '" + testSignalFullName + + "' is marked forceable, but force control signals could not be retrieved. Error " + "message: getForceControlSignals: VPI force or release requested for '" + + testSignalFullName + "', but vpiHandle '(nil)' of value signal '" + + testSignalFullName + + "__VforceVal' could not be cast to VerilatedVpioVar*. Ensure signal is marked " + "as " + "forceable")); +#endif + + std::unique_ptr receivedValueSp = vpiValueWithFormat(signalFormat, {}); + CHECK_RESULT_NZ(receivedValueSp); // NOLINT(concurrency-mt-unsafe) + vpi_get_value(signalHandle, receivedValueSp.get()); + + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(vpiCheckErrorLevel(maxAllowedErrorLevel)) + + const std::unique_ptr expectedValueSp + = vpiValueWithFormat(signalFormat, expectedValue); + CHECK_RESULT_NZ(expectedValueSp); // NOLINT(concurrency-mt-unsafe) + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_NZ( + vpiValuesEqual(vpi_get(vpiSize, signalHandle), *receivedValueSp, *expectedValueSp)); + + return 0; +} + +int forceSignal(const std::string& scopeName, const std::string& testSignalName, + const PLI_INT32 signalFormat, const signalValueTypes forceValue) { + const std::string testSignalFullName + = std::string{scopeName} + "." + std::string{testSignalName}; + TestVpiHandle const signalHandle //NOLINT(misc-misplaced-const) + = vpi_handle_by_name(const_cast(testSignalFullName.c_str()), nullptr); + CHECK_RESULT_NZ(signalHandle); // NOLINT(concurrency-mt-unsafe) + + std::unique_ptr value_sp = vpiValueWithFormat(signalFormat, forceValue); + CHECK_RESULT_NZ(value_sp); // NOLINT(concurrency-mt-unsafe) + +#ifdef VERILATOR + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(tryVpiPutWithMissingSignal( + *value_sp, signalHandle, vpiForceFlag, scopeName, testSignalName + "__VforceEn", + {"vpi_put_value: Signal '" + testSignalFullName + "' with vpiHandle ", + // Exact handle address does not matter + " is marked forceable, but force control signals could not be retrieved. Error " + "message: getForceControlSignals: VPI force or release requested for '" + + testSignalFullName + "', but vpiHandle '(nil)' of enable signal '" + + testSignalFullName + + "__VforceEn' could not be cast to VerilatedVpioVar*. Ensure signal is marked " + "as " + "forceable"})); + + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(tryVpiPutWithMissingSignal( + *value_sp, signalHandle, vpiForceFlag, scopeName, testSignalName + "__VforceVal", + {"vpi_put_value: Signal '" + testSignalFullName + "' with vpiHandle ", + // Exact handle address does not matter + " is marked forceable, but force control signals could not be retrieved. Error " + "message: getForceControlSignals: VPI force or release requested for '" + + testSignalFullName + "', but vpiHandle '(nil)' of value signal '" + + testSignalFullName + + "__VforceVal' could not be cast to VerilatedVpioVar*. Ensure signal is marked " + "as " + "forceable"})); +#endif + + vpi_put_value(signalHandle, value_sp.get(), nullptr, vpiForceFlag); + + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(vpiCheckErrorLevel(maxAllowedErrorLevel)) + + return 0; +} + +int releaseSignal(const std::string& scopeName, const std::string& testSignalName, + const PLI_INT32 signalFormat, + const std::pair releaseValue) { + const signalValueTypes expectedReleaseValueInit = releaseValue.first; + const signalValueTypes expectedReleaseValue = releaseValue.second; + const std::string testSignalFullName + = std::string{scopeName} + "." + std::string{testSignalName}; + TestVpiHandle const signalHandle //NOLINT(misc-misplaced-const) + = vpi_handle_by_name(const_cast(testSignalFullName.c_str()), nullptr); + CHECK_RESULT_NZ(signalHandle); // NOLINT(concurrency-mt-unsafe) + + // initialize value_sp to the value that is *not* expected (i.e. forceValue for continuously + // assigned signals, and releaseValue for clocked signals) to ensure the test fails if value_sp + // is not updated + std::unique_ptr value_sp + = vpiValueWithFormat(signalFormat, expectedReleaseValueInit); + CHECK_RESULT_NZ(value_sp); //NOLINT(concurrency-mt-unsafe) + +#ifdef VERILATOR + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(tryVpiPutWithMissingSignal( + *value_sp, signalHandle, vpiReleaseFlag, scopeName, testSignalName + "__VforceEn", + {"vpi_put_value: Signal '" + testSignalFullName + "' with vpiHandle ", + // Exact handle address does not matter + " is marked forceable, but force control signals could not be retrieved. Error " + "message: getForceControlSignals: VPI force or release requested for '" + + testSignalFullName + "', but vpiHandle '(nil)' of enable signal '" + + testSignalFullName + + "__VforceEn' could not be cast to VerilatedVpioVar*. Ensure signal is marked " + "as " + "forceable"})); + + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(tryVpiPutWithMissingSignal( + *value_sp, signalHandle, vpiReleaseFlag, scopeName, testSignalName + "__VforceVal", + {"vpi_put_value: Signal '" + testSignalFullName + "' with vpiHandle ", + // Exact handle address does not matter + " is marked forceable, but force control signals could not be retrieved. Error " + "message: getForceControlSignals: VPI force or release requested for '" + + testSignalFullName + "', but vpiHandle '(nil)' of value signal '" + + testSignalFullName + + "__VforceVal' could not be cast to VerilatedVpioVar*. Ensure signal is marked " + "as " + "forceable"})); +#endif + + vpi_put_value(signalHandle, value_sp.get(), nullptr, vpiReleaseFlag); + + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(vpiCheckErrorLevel(maxAllowedErrorLevel)) + +#ifdef XRUN + // Special case: real1Continuously is continuously assigned, but in xrun the value for the + // s_vpi_value output parameter upon releasing using vpi_put_value is *not* the releaseValue as + // expected, but the forceValue. This ifdef ensures the test still passes on xrun. + const std::unique_ptr expectedValueSp = vpiValueWithFormat( + signalFormat, testSignalName == "real1Continuously" ? signalValueTypes{.real = 123456.789} + : expectedReleaseValue); +#else + const std::unique_ptr expectedValueSp + = vpiValueWithFormat(signalFormat, expectedReleaseValue); +#endif + CHECK_RESULT_NZ(expectedValueSp); // NOLINT(concurrency-mt-unsafe) + + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_NZ(vpiValuesEqual(vpi_get(vpiSize, signalHandle), *value_sp, *expectedValueSp)); + + return 0; +} + +} // namespace + +extern "C" int checkValuesForced(void) { + // Clocked signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + checkValue(scopeName, signal.signalName, signal.valueType, signal.forceValue)); + return 0; + })); + + // Continuously assigned signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + const std::string continouslyAssignedSignal + = std::string{signal.signalName} + "Continuously"; + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + checkValue(scopeName, continouslyAssignedSignal, signal.valueType, + signal.forceValue)); + return 0; + })); + return 0; +} + +extern "C" int checkValuesPartiallyForced(void) { + // Clocked signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + if (signal.partialForceValue.second) + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + checkValue(scopeName, signal.signalName, signal.valueType, + signal.partialForceValue.first)); + return 0; + })); + + // Continuously assigned signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + if (signal.partialForceValue.second) + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + checkValue(scopeName, std::string{signal.signalName} + "Continuously", + signal.valueType, signal.partialForceValue.first)); + return 0; + })); + return 0; +} + +extern "C" int checkValuesReleased(void) { + // Clocked signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + checkValue(scopeName, signal.signalName, signal.valueType, signal.releaseValue)); + return 0; + })); + + // Continuously assigned signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + checkValue(scopeName, std::string{signal.signalName} + "Continuously", + signal.valueType, signal.releaseValue)); + return 0; + })); + return 0; +} + +#ifdef VERILATOR +// This function only makes sense with Verilator, because its purpose is testing error messages +// emitted from verilated_vpi. +extern "C" int tryInvalidPutOperations() { + CHECK_RESULT_Z(expectVpiPutError( // NOLINT(concurrency-mt-unsafe) + "str1", {.format = vpiStringVal, .value = {.str = const_cast("foo")}}, + vpiForceFlag, + "vpi_put_value used with vpiForceFlag on non-forceable signal 't.test.str1'")); + + CHECK_RESULT_Z(expectVpiPutError( // NOLINT(concurrency-mt-unsafe) + "octString", {.format = vpiOctStrVal, .value = {.str = const_cast("123A")}}, + vpiForceFlag, + "vpi_put_value: Non octal character 'A' in '123A' as value " + "vpiOctStrVal for t.test.octString__VforceVal")); + + CHECK_RESULT_Z(expectVpiPutError( // NOLINT(concurrency-mt-unsafe) + "decStringC", {.format = vpiDecStrVal, .value = {.str = const_cast("A123")}}, + vpiForceFlag, + "vpi_put_value: Parsing failed for 'A123' as value vpiDecStrVal for " + "t.test.decStringC__VforceVal")); + + CHECK_RESULT_Z(expectVpiPutError( // NOLINT(concurrency-mt-unsafe) + "decStringC", {.format = vpiDecStrVal, .value = {.str = const_cast("123A")}}, + vpiForceFlag, + "vpi_put_value: Trailing garbage 'A' in '123A' as value vpiDecStrVal for " + "t.test.decStringC__VforceVal")); + + CHECK_RESULT_Z(expectVpiPutError( // NOLINT(concurrency-mt-unsafe) + "hexString", {.format = vpiHexStrVal, .value = {.str = const_cast("12AG")}}, + vpiForceFlag, + "vpi_put_value: Non hex character 'G' in '12AG' as value vpiHexStrVal for " + "t.test.hexString__VforceVal")); + + // vop was replaced with baseSignalVop in vpi_put_value, so these tests are required to hit the + // test coverage target and ensure the error messages still work. + CHECK_RESULT_Z(expectVpiPutError( // NOLINT(concurrency-mt-unsafe) + "onebit", {.format = vpiRawFourStateVal, .value = {}}, vpiForceFlag, + "vl_check_format: Unsupported format (vpiRawFourStateVal) for t.test.onebit")); + + CHECK_RESULT_Z(expectVpiPutError( // NOLINT(concurrency-mt-unsafe) + "onebit", {.format = vpiSuppressVal, .value = {}}, vpiForceFlag, + "vpi_put_value: Unsupported format (vpiSuppressVal) as " + "requested for t.test.onebit__VforceVal")); + + CHECK_RESULT_Z(expectVpiPutError( // NOLINT(concurrency-mt-unsafe) + "onebit", {.format = vpiStringVal, .value = {}}, vpiInertialDelay, + "vpi_put_value: Unsupported p_vpi_value as requested for 't.test.onebit' with " + "vpiInertialDelay")); + + return 0; +} + +// This function is just needed for hitting the test coverage target for verilated_vpi.cpp and +// ensuring that vpi_put_value to a string without vpiForceFlag still works. +extern "C" int putString() { + const std::string stringName = std::string{scopeName} + ".str1"; + TestVpiHandle const stringSignalHandle //NOLINT(misc-misplaced-const) + = vpi_handle_by_name(const_cast(stringName.c_str()), nullptr); + CHECK_RESULT_NZ(stringSignalHandle); // NOLINT(concurrency-mt-unsafe) + + s_vpi_value value_s{.format = vpiStringVal, .value = {.str = const_cast("foo")}}; + + vpi_put_value(stringSignalHandle, &value_s, nullptr, vpiNoDelay); + + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(vpiCheckErrorLevel(maxAllowedErrorLevel)) + + value_s.value.str + = const_cast("bar"); // Ensure that test fails if value_s is not updated + + vpi_get_value(stringSignalHandle, &value_s); + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(vpiCheckErrorLevel(maxAllowedErrorLevel)) + + s_vpi_value expectedValueS{.format = vpiStringVal, + .value = {.str = const_cast("foo")}}; + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_NZ(vpiValuesEqual(vpi_get(vpiSize, stringSignalHandle), value_s, expectedValueS)); + + return 0; +} + +// This function is just needed for hitting the test coverage target for verilated_vpi.cpp and +// ensuring that vpiInertialDelay still works after renaming vop to baseSignalVop. +extern "C" int putInertialDelay() { + const std::string fullSignalName = std::string{scopeName} + ".delayed"; + TestVpiHandle const signalHandle //NOLINT(misc-misplaced-const) + = vpi_handle_by_name(const_cast(fullSignalName.c_str()), nullptr); + CHECK_RESULT_NZ(signalHandle); // NOLINT(concurrency-mt-unsafe) + + constexpr int delayedValue = 123; + s_vpi_value value_s{.format = vpiIntVal, .value = {.integer = delayedValue}}; + s_vpi_time time{.type = vpiSimTime, .high = 0, .low = 0, .real = {}}; + vpi_put_value(signalHandle, &value_s, &time, vpiInertialDelay); + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(vpiCheckErrorLevel(maxAllowedErrorLevel)) + + // Check that the put had no immediate effect + + vpi_get_value(signalHandle, &value_s); + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(vpiCheckErrorLevel(maxAllowedErrorLevel)) + + s_vpi_value expectedValueS{.format = vpiIntVal, .value = {.integer = 0}}; + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_NZ(vpiValuesEqual(vpi_get(vpiSize, signalHandle), value_s, expectedValueS)); + + // Check that the put is executed upon doInertialPuts + VerilatedVpi::doInertialPuts(); + + value_s.value.integer = 0; // Ensure that test fails if value_s is not updated + vpi_get_value(signalHandle, &value_s); + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_Z(vpiCheckErrorLevel(maxAllowedErrorLevel)) + + expectedValueS.value.integer = delayedValue; + // NOLINTNEXTLINE(concurrency-mt-unsafe) + CHECK_RESULT_NZ(vpiValuesEqual(vpi_get(vpiSize, signalHandle), value_s, expectedValueS)); + + return 0; +} +#endif + +extern "C" int forceValues(void) { + if (!TestSimulator::is_verilator()) { +#ifdef VERILATOR + printf("TestSimulator indicating not verilator, but VERILATOR macro is defined\n"); + return 1; +#endif + } + + // Clocked signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + forceSignal(scopeName, signal.signalName, signal.valueType, signal.forceValue)); + return 0; + })); + + // Continuously assigned signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + forceSignal(scopeName, std::string{signal.signalName} + "Continuously", + signal.valueType, signal.forceValue)); + return 0; + })); + return 0; +} + +extern "C" int releaseValues(void) { + // Clocked signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + releaseSignal(scopeName, signal.signalName, signal.valueType, + {signal.releaseValue, signal.forceValue})); + return 0; + })); + + // Continuously assigned signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + releaseSignal(scopeName, std::string{signal.signalName} + "Continuously", + signal.valueType, {signal.forceValue, signal.releaseValue})); + return 0; + })); + return 0; +} + +extern "C" int releasePartiallyForcedValues(void) { + // Skip any values that cannot be partially forced. Can't just reuse releaseValues, because the + // output argument s_vpi_value of vpi_put_value with vpiReleaseFlag differs depending on + // whether or not a signal was forced before, and not all signals are forced in the partial + // forcing test. + + // Clocked signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + if (signal.partialForceValue.second) + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + releaseSignal(scopeName, signal.signalName, signal.valueType, + {signal.releaseValue, signal.partialForceValue.first})); + return 0; + })); + + // Continuously assigned signals + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + std::any_of(TestSignals.begin(), TestSignals.end(), [](const TestSignal& signal) { + if (signal.partialForceValue.second) + CHECK_RESULT_Z( // NOLINT(concurrency-mt-unsafe) + releaseSignal(scopeName, std::string{signal.signalName} + "Continuously", + signal.valueType, + {signal.partialForceValue.first, signal.releaseValue})); + return 0; + })); + return 0; +} + +#ifdef IS_VPI + +static int checkValuesForcedVpi() { + TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); + s_vpi_value vpi_value; + + vpi_value.format = vpiIntVal; + vpi_value.value.integer = checkValuesForced(); + vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); + + return 0; +} + +static int checkValuesPartiallyForcedVpi() { + TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); + s_vpi_value vpi_value; + + vpi_value.format = vpiIntVal; + vpi_value.value.integer = checkValuesPartiallyForced(); + vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); + + return 0; +} + +static int checkValuesReleasedVpi() { + TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); + s_vpi_value vpi_value; + + vpi_value.format = vpiIntVal; + vpi_value.value.integer = checkValuesReleased(); + vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); + + return 0; +} + +static int forceValuesVpi() { + TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); + s_vpi_value vpi_value; + + vpi_value.format = vpiIntVal; + vpi_value.value.integer = forceValues(); + vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); + + return 0; +} + +static int releaseValuesVpi() { + TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); + s_vpi_value vpiValue; + + vpiValue.format = vpiIntVal; + vpiValue.value.integer = releaseValues(); + vpi_put_value(href, &vpiValue, NULL, vpiNoDelay); + + return 0; +} + +static int releasePartiallyForcedValuesVpi() { + TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); + s_vpi_value vpiValue; + + vpiValue.format = vpiIntVal; + vpiValue.value.integer = releasePartiallyForcedValues(); + vpi_put_value(href, &vpiValue, NULL, vpiNoDelay); + + return 0; +} + +std::array vpi_systf_data + = {s_vpi_systf_data{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$forceValues", + (PLI_INT32(*)(PLI_BYTE8*))forceValuesVpi, 0, 0, 0}, + s_vpi_systf_data{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$releaseValues", + (PLI_INT32(*)(PLI_BYTE8*))releaseValuesVpi, 0, 0, 0}, + s_vpi_systf_data{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$releasePartiallyForcedValues", + (PLI_INT32(*)(PLI_BYTE8*))releasePartiallyForcedValuesVpi, 0, 0, 0}, + s_vpi_systf_data{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$checkValuesForced", + (PLI_INT32(*)(PLI_BYTE8*))checkValuesForcedVpi, 0, 0, 0}, + s_vpi_systf_data{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$checkValuesPartiallyForced", + (PLI_INT32(*)(PLI_BYTE8*))checkValuesPartiallyForcedVpi, 0, 0, 0}, + s_vpi_systf_data{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$checkValuesReleased", + (PLI_INT32(*)(PLI_BYTE8*))checkValuesReleasedVpi, 0, 0, 0}}; + +// cver entry +extern "C" void vpi_compat_bootstrap(void) { + for (s_vpi_systf_data& systf : vpi_systf_data) vpi_register_systf(&systf); +} + +// icarus entry +void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; +#endif diff --git a/test_regress/t/t_vpi_force.py b/test_regress/t/t_vpi_force.py new file mode 100755 index 000000000..20ff5295c --- /dev/null +++ b/test_regress/t/t_vpi_force.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["+define+VERILATOR_COMMENTS --binary --vpi", test.pli_filename], + v_flags2=["+define+USE_VPI_NOT_DPI"]) + +test.execute(xrun_flags2=["+define+USE_VPI_NOT_DPI"], use_libvpi=True, check_finished=True) + +test.passes() diff --git a/test_regress/t/t_vpi_force.v b/test_regress/t/t_vpi_force.v new file mode 100644 index 000000000..f6041846e --- /dev/null +++ b/test_regress/t/t_vpi_force.v @@ -0,0 +1,704 @@ +// ====================================================================== +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Christian Hecken +// SPDX-License-Identifier: CC0-1.0 +// ====================================================================== + +`define STRINGIFY(x) `"x`" + +`ifdef VERILATOR_COMMENTS +`define PUBLIC_FORCEABLE /*verilator public_flat_rw*/ /*verilator forceable*/ +`else +`define PUBLIC_FORCEABLE +`endif + +module t; + + reg clk; + + initial begin + clk = 0; + forever #1 clk = ~clk; + end + + Test test (.clk(clk)); + + +endmodule + +module Test ( + input clk +); + +`ifdef IVERILOG +`elsif USE_VPI_NOT_DPI +`ifdef VERILATOR +`systemc_header + extern "C" int putString(); + extern "C" int tryInvalidPutOperations(); + extern "C" int putInertialDelay(); + extern "C" int forceValues(); + extern "C" int releaseValues(); + extern "C" int releasePartiallyForcedValues(); + extern "C" int checkValuesForced(); + extern "C" int checkValuesPartiallyForced(); + extern "C" int checkValuesReleased(); +`verilog +`endif +`else +`ifdef VERILATOR + import "DPI-C" context function int putString(); + import "DPI-C" context function int tryInvalidPutOperations(); + import "DPI-C" context function int putInertialDelay(); +`endif + import "DPI-C" context function int forceValues(); + import "DPI-C" context function int releaseValues(); + import "DPI-C" context function int releasePartiallyForcedValues(); + import "DPI-C" context function int checkValuesPartiallyForced(); + import "DPI-C" context function int checkValuesForced(); + import "DPI-C" context function int checkValuesReleased(); +`endif + + // Verify that vpi_put_value still works for strings + string str1 /*verilator public_flat_rw*/; // std::string + + // Verify that vpi_put_value still works with vpiInertialDelay + logic [ 31:0] delayed `PUBLIC_FORCEABLE; // IData + + // Clocked signals + + // Force with vpiIntVal + logic onebit `PUBLIC_FORCEABLE; // CData + logic [ 31:0] intval `PUBLIC_FORCEABLE; // IData + + // Force with vpiVectorVal + logic [ 7:0] vectorC `PUBLIC_FORCEABLE; // CData + logic [ 61:0] vectorQ `PUBLIC_FORCEABLE; // QData + logic [127:0] vectorW `PUBLIC_FORCEABLE; // VlWide + + // Force with vpiRealVal + real real1 `PUBLIC_FORCEABLE; // double + + // Force with vpiStringVal + logic [ 15:0] textHalf `PUBLIC_FORCEABLE; // SData + logic [ 63:0] textLong `PUBLIC_FORCEABLE; // QData + logic [511:0] text `PUBLIC_FORCEABLE; // VlWide + + // Force with vpiBinStrVal, vpiOctStrVal, vpiHexStrVal + logic [ 7:0] binString `PUBLIC_FORCEABLE; // CData + logic [ 14:0] octString `PUBLIC_FORCEABLE; // SData + logic [ 63:0] hexString `PUBLIC_FORCEABLE; // QData + + // Force with vpiDecStrVal + logic [ 7:0] decStringC `PUBLIC_FORCEABLE; // CData + logic [ 15:0] decStringS `PUBLIC_FORCEABLE; // SData + logic [ 31:0] decStringI `PUBLIC_FORCEABLE; // IData + logic [ 63:0] decStringQ `PUBLIC_FORCEABLE; // QData + + // Continuously assigned signals: + + // Force with vpiIntVal + wire onebitContinuously `PUBLIC_FORCEABLE; // CData + wire [ 31:0] intvalContinuously `PUBLIC_FORCEABLE; // IData + + // Force with vpiVectorVal + wire [ 7:0] vectorCContinuously `PUBLIC_FORCEABLE; // CData + wire [ 61:0] vectorQContinuously `PUBLIC_FORCEABLE; // QData + wire [127:0] vectorWContinuously `PUBLIC_FORCEABLE; // VlWide + + // Force with vpiRealVal + `ifdef IVERILOG + // Need wreal with Icarus for forcing continuously assigned real + wreal real1Continuously `PUBLIC_FORCEABLE; // double + `else + real real1Continuously `PUBLIC_FORCEABLE; // double + `endif + + // Force with vpiStringVal + wire [ 15:0] textHalfContinuously `PUBLIC_FORCEABLE; // SData + wire [ 63:0] textLongContinuously `PUBLIC_FORCEABLE; // QData + wire [511:0] textContinuously `PUBLIC_FORCEABLE; // VlWide + + // Force with vpiBinStrVal, vpiOctStrVal, vpiHexStrVal + wire [ 7:0] binStringContinuously `PUBLIC_FORCEABLE; // CData + wire [ 14:0] octStringContinuously `PUBLIC_FORCEABLE; // SData + wire [ 63:0] hexStringContinuously `PUBLIC_FORCEABLE; // QData + + // Force with vpiDecStrVal + wire [ 7:0] decStringCContinuously `PUBLIC_FORCEABLE; // CData + wire [ 15:0] decStringSContinuously `PUBLIC_FORCEABLE; // SData + wire [ 31:0] decStringIContinuously `PUBLIC_FORCEABLE; // IData + wire [ 63:0] decStringQContinuously `PUBLIC_FORCEABLE; // QData + + always @(posedge clk) begin + onebit <= 1; + intval <= 32'hAAAAAAAA; + + vectorC <= 8'hAA; + vectorQ <= 62'h2AAAAAAA_AAAAAAAA; + vectorW <= 128'hAAAAAAAA_AAAAAAAA_AAAAAAAA_AAAAAAAA; + + real1 <= 1.0; + + textHalf <= "Hf"; + textLong <= "Long64b"; + text <= "Verilog Test module"; + + binString <= 8'b10101010; + octString <= 15'o25252; // 0b1010... + hexString <= 64'hAAAAAAAAAAAAAAAA; // 0b1010... + + decStringC <= 8'hAA; + decStringS <= 16'hAAAA; + decStringI <= 32'hAAAAAAAA; + decStringQ <= 64'd12297829382473034410; // 0b1010... + end + + assign onebitContinuously = 1; + assign intvalContinuously = 32'hAAAAAAAA; + + assign vectorCContinuously = 8'hAA; + assign vectorQContinuously = 62'h2AAAAAAA_AAAAAAAA; + assign vectorWContinuously = 128'hAAAAAAAA_AAAAAAAA_AAAAAAAA_AAAAAAAA; + + assign real1Continuously = 1.0; + + assign textHalfContinuously = "Hf"; + assign textLongContinuously = "Long64b"; + assign textContinuously = "Verilog Test module"; + + assign binStringContinuously = 8'b10101010; + assign octStringContinuously = 15'o25252; // 0b1010... + assign hexStringContinuously = 64'hAAAAAAAAAAAAAAAA; // 0b1010... + + assign decStringCContinuously = 8'hAA; + assign decStringSContinuously = 16'hAAAA; + assign decStringIContinuously = 32'hAAAAAAAA; + assign decStringQContinuously = 64'd12297829382473034410; // 0b1010... + + task automatic svForceValues(); + force onebit = 0; + force intval = 32'h55555555; + force vectorC = 8'h55; + force vectorQ = 62'h15555555_55555555; + force vectorW = 128'h55555555_55555555_55555555_55555555; + force real1 = 123456.789; + force textHalf = "T2"; + force textLong = "44Four44"; + force text = "lorem ipsum"; + force binString = 8'b01010101; + force octString = 15'o52525; + force hexString = 64'h5555555555555555; + force decStringC = 8'h55; + force decStringS = 16'h5555; + force decStringI = 32'h55555555; + force decStringQ = 64'd6148914691236517205; + + force onebitContinuously = 0; + force intvalContinuously = 32'h55555555; + force vectorCContinuously = 8'h55; + force vectorQContinuously = 62'h15555555_55555555; + force vectorWContinuously = 128'h55555555_55555555_55555555_55555555; + force real1Continuously = 123456.789; + force textHalfContinuously = "T2"; + force textLongContinuously = "44Four44"; + force textContinuously = "lorem ipsum"; + force binStringContinuously = 8'b01010101; + force octStringContinuously = 15'o52525; + force hexStringContinuously = 64'h5555555555555555; + force decStringCContinuously = 8'h55; + force decStringSContinuously = 16'h5555; + force decStringIContinuously = 32'h55555555; + force decStringQContinuously = 64'd6148914691236517205; + endtask + + task automatic svPartiallyForceValues(); + force intval[15:0] = 16'h5555; + + force vectorC[3:0] = 4'h5; + force vectorQ[30:0] = 31'h55555555; + force vectorW[63:0] = 64'h55555555_55555555; + + force textHalf[7:0] = "2"; + force textLong[31:0] = "ur44"; + force text[63:0] = "em ipsum"; + force binString[3:0] = 4'b0101; + + force octString[6:0] = 7'o125; + force hexString[31:0] = 32'h55555555; + + force decStringC[3:0] = 4'h5; + force decStringS[7:0] = 8'h55; + force decStringI[15:0] = 16'h5555; + force decStringQ[31:0] = 32'd1431655765; + + force intvalContinuously[15:0] = 16'h5555; + + force vectorCContinuously[3:0] = 4'h5; + force vectorQContinuously[30:0] = 31'h55555555; + force vectorWContinuously[63:0] = 64'h55555555_55555555; + + force textHalfContinuously[7:0] = "2"; + force textLongContinuously[31:0] = "ur44"; + force textContinuously[63:0] = "em ipsum"; + force binStringContinuously[3:0] = 4'b0101; + + force octStringContinuously[6:0] = 7'o125; + force hexStringContinuously[31:0] = 32'h55555555; + + force decStringCContinuously[3:0] = 4'h5; + force decStringSContinuously[7:0] = 8'h55; + force decStringIContinuously[15:0] = 16'h5555; + force decStringQContinuously[31:0] = 32'd1431655765; + endtask + + task automatic vpiPutString(); + integer vpiStatus = 1; // Default to failed status to ensure that a function *not* getting + // called also causes simulation termination +`ifdef VERILATOR +`ifdef USE_VPI_NOT_DPI + vpiStatus = $c32("putString()"); +`else + vpiStatus = putString(); +`endif +`else + $stop; // This task only makes sense with Verilator, since other simulators ignore the "verilator forceable" metacomment. +`endif + + if (vpiStatus != 0) begin + $write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus); + $display( + "C Test failed (vpi_put_value failed for string)"); + $stop; + end + endtask + + task automatic vpiTryInvalidPutOperations(); + integer vpiStatus = 1; // Default to failed status to ensure that a function *not* getting + // called also causes simulation termination +`ifdef VERILATOR +`ifdef USE_VPI_NOT_DPI + vpiStatus = $c32("tryInvalidPutOperations()"); +`else + vpiStatus = tryInvalidPutOperations(); +`endif +`else + $stop; // This task only makes sense with Verilator, since it tests verilated_vpi.cpp +`endif + + if (vpiStatus != 0) begin + $write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus); + $display( + "C Test failed (invalid vpi_put_value operation either succeeded, even though it should have failed, or produced an unexpected error message.)"); + $stop; + end + endtask + + task automatic vpiPutInertialDelay(); + integer vpiStatus = 1; // Default to failed status to ensure that a function *not* getting + // called also causes simulation termination +`ifdef VERILATOR +`ifdef USE_VPI_NOT_DPI + vpiStatus = $c32("putInertialDelay()"); +`else + vpiStatus = putInertialDelay(); +`endif +`else + $stop; // This task only makes sense with Verilator, since it tests verilated_vpi.cpp +`endif + + if (vpiStatus != 0) begin + $write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus); + $display( + "C Test failed (vpi_put_value with vpiInertialDelay failed)"); + $stop; + end + endtask + + task automatic vpiForceValues(); + integer vpiStatus = 1; +`ifdef VERILATOR +`ifdef USE_VPI_NOT_DPI + vpiStatus = $c32("forceValues()"); +`else + vpiStatus = forceValues(); +`endif +`elsif IVERILOG + vpiStatus = $forceValues; +`elsif USE_VPI_NOT_DPI + vpiStatus = $forceValues; +`else + vpiStatus = forceValues(); +`endif + + if (vpiStatus != 0) begin + $write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus); + $display("C Test failed (could not force value)"); + $stop; + end + endtask + + task automatic svReleaseValues(); + release onebit; + release intval; + release vectorC; + release vectorQ; + release vectorW; + release real1; + release textHalf; + release textLong; + release text; + release binString; + release octString; + release hexString; + release decStringC; + release decStringS; + release decStringI; + release decStringQ; + + release onebitContinuously; + release intvalContinuously; + release vectorCContinuously; + release vectorQContinuously; + release vectorWContinuously; + release real1Continuously; + release textHalfContinuously; + release textLongContinuously; + release textContinuously; + release binStringContinuously; + release octStringContinuously; + release hexStringContinuously; + release decStringCContinuously; + release decStringSContinuously; + release decStringIContinuously; + release decStringQContinuously; + endtask + + task automatic vpiReleaseValues(); + integer vpiStatus = 1; +`ifdef VERILATOR +`ifdef USE_VPI_NOT_DPI + vpiStatus = $c32("releaseValues()"); +`else + vpiStatus = releaseValues(); +`endif +`elsif IVERILOG + vpiStatus = $releaseValues; +`elsif USE_VPI_NOT_DPI + vpiStatus = $releaseValues; +`else + vpiStatus = releaseValues(); +`endif + + if (vpiStatus != 0) begin + $write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus); + $display("C Test failed (could not release value)"); + $stop; + end + endtask + + task automatic vpiReleasePartiallyForcedValues(); + integer vpiStatus = 1; +`ifdef VERILATOR +`ifdef USE_VPI_NOT_DPI + vpiStatus = $c32("releasePartiallyForcedValues()"); +`else + vpiStatus = releasePartiallyForcedValues(); +`endif +`elsif IVERILOG + vpiStatus = $releasePartiallyForcedValues; +`elsif USE_VPI_NOT_DPI + vpiStatus = $releasePartiallyForcedValues; +`else + vpiStatus = releasePartiallyForcedValues(); +`endif + + if (vpiStatus != 0) begin + $write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus); + $display("C Test failed (could not release value)"); + $stop; + end + endtask + + task automatic svCheckValuesForced(); + if(onebit != 0) $stop; + if(intval != 32'h55555555) $stop; + if(vectorC != 8'h55) $stop; + if(vectorQ != 62'h15555555_55555555) $stop; + if(vectorW != 128'h55555555_55555555_55555555_55555555) $stop; + if(real1 != 123456.789) $stop; + if(textHalf != "T2") $stop; + if(textLong != "44Four44") $stop; + if(text != "lorem ipsum") $stop; + if(binString != 8'b01010101) $stop; + if(octString != 15'o52525) $stop; + if(hexString != 64'h5555555555555555) $stop; + if(decStringC != 8'h55) $stop; + if(decStringS != 16'h5555) $stop; + if(decStringI != 32'h55555555) $stop; + if(decStringQ != 64'd6148914691236517205) $stop; + + if(onebitContinuously != 0) $stop; + if(intvalContinuously != 32'h55555555) $stop; + if(vectorCContinuously != 8'h55) $stop; + if(vectorQContinuously != 62'h15555555_55555555) $stop; + if(vectorWContinuously != 128'h55555555_55555555_55555555_55555555) $stop; + if(real1Continuously != 123456.789) $stop; + if(textHalfContinuously != "T2") $stop; + if(textLongContinuously != "44Four44") $stop; + if(textContinuously != "lorem ipsum") $stop; + if(binStringContinuously != 8'b01010101) $stop; + if(octStringContinuously != 15'o52525) $stop; + if(hexStringContinuously != 64'h5555555555555555) $stop; + if(decStringCContinuously != 8'h55) $stop; + if(decStringSContinuously != 16'h5555) $stop; + if(decStringIContinuously != 32'h55555555) $stop; + if(decStringQContinuously != 64'd6148914691236517205) $stop; + endtask + + task automatic vpiCheckValuesForced(); + integer vpiStatus = 1; +`ifdef VERILATOR +`ifdef USE_VPI_NOT_DPI + vpiStatus = $c32("checkValuesForced()"); +`else + vpiStatus = checkValuesForced(); +`endif +`elsif IVERILOG + vpiStatus = $checkValuesForced; +`elsif USE_VPI_NOT_DPI + vpiStatus = $checkValuesForced; +`else + vpiStatus = checkValuesForced(); +`endif + + if (vpiStatus != 0) begin + $write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus); + $display("C Test failed (value after forcing does not match expectation)"); + $stop; + end + endtask + + task automatic svCheckValuesPartiallyForced(); + if (intval != 32'hAAAA_5555) $stop; + if (vectorC != 8'h A5) $stop; + if (vectorQ != 62'h2AAAAAAAD5555555) $stop; + if (vectorW != 128'hAAAAAAAA_AAAAAAAA_55555555_55555555) $stop; + if (textHalf != "H2") $stop; + if (textLong != "Lonur44") $stop; + if (text != "Verilog Tesem ipsum") $stop; + if (binString != 8'b1010_0101) $stop; + if (octString != 15'b01010101_1010101) $stop; + if (hexString != 64'hAAAAAAAA_55555555) $stop; + if (decStringC != 8'hA5) $stop; + if (decStringS != 16'hAA55) $stop; + if (decStringI != 32'hAAAA_5555) $stop; + if (decStringQ != 64'hAAAAAAAA_55555555) $stop; + + if (intvalContinuously != 32'hAAAA_5555) $stop; + if (vectorCContinuously != 8'h A5) $stop; + if (vectorQContinuously != 62'h2AAAAAAAD5555555) $stop; + if (vectorWContinuously != 128'hAAAAAAAA_AAAAAAAA_55555555_55555555) $stop; + if (textHalfContinuously != "H2") $stop; + if (textLongContinuously != "Lonur44") $stop; + if (textContinuously != "Verilog Tesem ipsum") $stop; + if (binStringContinuously != 8'b1010_0101) $stop; + if (octStringContinuously != 15'b01010101_1010101) $stop; + if (hexStringContinuously != 64'hAAAAAAAA_55555555) $stop; + if (decStringCContinuously != 8'hA5) $stop; + if (decStringSContinuously != 16'hAA55) $stop; + if (decStringIContinuously != 32'hAAAA_5555) $stop; + if (decStringQContinuously != 64'hAAAAAAAA_55555555) $stop; + endtask + + task automatic vpiCheckValuesPartiallyForced(); + integer vpiStatus = 1; +`ifdef VERILATOR +`ifdef USE_VPI_NOT_DPI + vpiStatus = $c32("checkValuesPartiallyForced()"); +`else + vpiStatus = checkValuesPartiallyForced(); +`endif +`elsif IVERILOG + vpiStatus = $checkValuesPartiallyForced; +`elsif USE_VPI_NOT_DPI + vpiStatus = $checkValuesPartiallyForced; +`else + vpiStatus = checkValuesPartiallyForced(); +`endif + + if (vpiStatus != 0) begin + $write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus); + $display("C Test failed (value after partial forcing does not match expectation)"); + $stop; + end + endtask + + task automatic svCheckValuesReleased(); + if (onebit != 1) $stop; + if (intval != 32'hAAAAAAAA) $stop; + if (vectorC != 8'hAA) $stop; + if (vectorQ != 62'h2AAAAAAA_AAAAAAAA) $stop; + if (vectorW != 128'hAAAAAAAA_AAAAAAAA_AAAAAAAA_AAAAAAAA) $stop; + if (real1 != 1.0) $stop; + if (textHalf != "Hf") $stop; + if (textLong != "Long64b") $stop; + if (text != "Verilog Test module") $stop; + if (binString != 8'b10101010) $stop; + if (octString != 15'o25252) $stop; + if (hexString != 64'hAAAAAAAAAAAAAAAA) $stop; + if (decStringC != 8'hAA) $stop; + if (decStringS != 16'hAAAA) $stop; + if (decStringI != 32'hAAAAAAAA) $stop; + if (decStringQ != 64'd12297829382473034410) $stop; + + if (onebitContinuously != 1) $stop; + if (intvalContinuously != 32'hAAAAAAAA) $stop; + if (vectorCContinuously != 8'hAA) $stop; + if (vectorQContinuously != 62'h2AAAAAAA_AAAAAAAA) $stop; + if (vectorWContinuously != 128'hAAAAAAAA_AAAAAAAA_AAAAAAAA_AAAAAAAA) $stop; + if (real1Continuously != 1.0) $stop; + if (textHalfContinuously != "Hf") $stop; + if (textLongContinuously != "Long64b") $stop; + if (textContinuously != "Verilog Test module") $stop; + if (binStringContinuously != 8'b10101010) $stop; + if (octStringContinuously != 15'o25252) $stop; + if (hexStringContinuously != 64'hAAAAAAAAAAAAAAAA) $stop; + if (decStringCContinuously != 8'hAA) $stop; + if (decStringSContinuously != 16'hAAAA) $stop; + if (decStringIContinuously != 32'hAAAAAAAA) $stop; + if (decStringQContinuously != 64'd12297829382473034410) $stop; + endtask + + task automatic vpiCheckValuesReleased(); + integer vpiStatus = 1; +`ifdef VERILATOR +`ifdef USE_VPI_NOT_DPI + vpiStatus = $c32("checkValuesReleased()"); +`else + vpiStatus = checkValuesReleased(); +`endif +`elsif IVERILOG + vpiStatus = $checkValuesReleased; +`elsif USE_VPI_NOT_DPI + vpiStatus = $checkValuesReleased; +`else + vpiStatus = checkValuesReleased(); +`endif + + if (vpiStatus != 0) begin + $write("%%Error: t_vpi_force.cpp:%0d:", vpiStatus); + $display("C Test failed (value after releasing does not match expectation)"); + $stop; + end + endtask + + initial begin +`ifdef WAVES +$dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(); +`endif + +`ifdef VERILATOR + vpiPutString(); + vpiTryInvalidPutOperations(); + vpiPutInertialDelay(); +`endif + + // Wait a bit before triggering the force to see a change in the traces + #4 vpiForceValues(); + + // Time delay to ensure setting and checking values does not happen + // at the same time, so that the signals can have their values overwritten + // by other processes + #4 vpiCheckValuesForced(); + svCheckValuesForced(); + #4 vpiReleaseValues(); + #4 vpiCheckValuesReleased(); + svCheckValuesReleased(); + + // Force through VPI, release through Verilog + #4 vpiForceValues(); + #4 vpiCheckValuesForced(); + svCheckValuesForced(); + #4 svReleaseValues(); + #4 vpiCheckValuesReleased(); + svCheckValuesReleased(); + + // Force through Verilog, release through VPI + #4 svForceValues(); + #4 vpiCheckValuesForced(); + svCheckValuesForced(); + #4 vpiReleaseValues(); + #4 vpiCheckValuesReleased(); + svCheckValuesReleased(); + + // Force only some bits, check if __VforceRd yields correct signal, + // release through VPI + #4 svPartiallyForceValues(); + #4 vpiCheckValuesPartiallyForced(); + svCheckValuesPartiallyForced(); + #4 vpiReleasePartiallyForcedValues(); + #4 vpiCheckValuesReleased(); + svCheckValuesReleased(); + + // Force only some bits, check if __VforceRd yields correct signal, + // release through Verilog + #4 svPartiallyForceValues(); + #4 vpiCheckValuesPartiallyForced(); + svCheckValuesPartiallyForced(); + #4 svReleaseValues(); + #4 vpiCheckValuesReleased(); + svCheckValuesReleased(); + + + #5 $display("*-* All Finished *-*"); + $finish; + end + +`ifdef TEST_VERBOSE + always @(posedge clk or negedge clk) begin + $display("time: %0t\tclk:%b", $time, clk); + + $display("str1: %s", str1); + $display("delayed: %x", delayed); + + $display("onebit: %x", onebit); + $display("intval: %x", intval); + $display("vectorC: %x", vectorC); + $display("vectorQ: %x", vectorQ); + $display("vectorW: %x", vectorW); + $display("real1: %f", real1); + $display("textHalf: %s", textHalf); + $display("textLong: %s", textLong); + $display("text: %s", text); + $display("binString: %x", binString); + $display("octString: %x", octString); + $display("hexString: %x", hexString); + $display("decStringC: %x", decStringC); + $display("decStringS: %x", decStringS); + $display("decStringI: %x", decStringI); + $display("decStringQ: %x", decStringQ); + + $display("onebitContinuously: %x", onebitContinuously); + $display("intvalContinuously: %x", intvalContinuously); + $display("vectorCContinuously: %x", vectorCContinuously); + $display("vectorQContinuously: %x", vectorQContinuously); + $display("vectorWContinuously: %x", vectorWContinuously); + $display("real1Continuously: %f", real1Continuously); + $display("textHalfContinuously: %s", textHalfContinuously); + $display("textLongContinuously: %s", textLongContinuously); + $display("textContinuously: %s", textContinuously); + $display("binStringContinuously: %x", binStringContinuously); + $display("octStringContinuously: %x", octStringContinuously); + $display("hexStringContinuously: %x", hexStringContinuously); + $display("decStringCContinuously: %x", decStringCContinuously); + $display("decStringSContinuously: %x", decStringSContinuously); + $display("decStringIContinuously: %x", decStringIContinuously); + $display("decStringQContinuously: %x", decStringQContinuously); + + $display("========================\n"); + end +`endif + +endmodule diff --git a/test_regress/t/t_vpi_forceable_bad.cpp b/test_regress/t/t_vpi_forceable_bad.cpp new file mode 100644 index 000000000..d38bb9371 --- /dev/null +++ b/test_regress/t/t_vpi_forceable_bad.cpp @@ -0,0 +1,65 @@ +// ====================================================================== +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Christian Hecken +// SPDX-License-Identifier: CC0-1.0 +// ====================================================================== + +// DESCRIPTION: Test failure of trying to force a non-forceable signal +// +// This test checks that attempting to force a signal that is not marked as +// forceable causes an error under Verilator, and does not cause an error in +// other simulators that do not need this metacomment to be able to force +// signals. + +#include "verilated.h" + +#include "TestSimulator.h" // For is_verilator() +#include "TestVpi.h" // For CHECK_RESULT_NZ +#include "vpi_user.h" + +extern "C" int forceValue(void) { + if (!TestSimulator::is_verilator()) { +#ifdef VERILATOR + printf("TestSimulator indicating not verilator, but VERILATOR macro is defined\n"); + return 1; +#endif + } + + PLI_BYTE8 testSignalName[] = "t.nonForceableSignal"; + vpiHandle signal = vpi_handle_by_name(testSignalName, nullptr); + CHECK_RESULT_NZ(signal); // NOLINT(concurrency-mt-unsafe) + + s_vpi_value value_s; + value_s.format = vpiIntVal; + value_s.value.integer = 0; + vpi_put_value(signal, &value_s, nullptr, vpiForceFlag); + // NOLINTNEXTLINE(concurrency-mt-unsafe); + CHECK_RESULT_Z(vpi_chk_error(nullptr)) + + return 0; +} + +#ifdef IS_VPI +static int force_value_vpi() { + TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); + s_vpi_value vpi_value; + + vpi_value.format = vpiIntVal; + vpi_value.value.integer = forceValue(); + vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); + + return 0; +} + +std::array vpi_systf_data + = {s_vpi_systf_data{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$forceValue", + (PLI_INT32(*)(PLI_BYTE8*))force_value_vpi, 0, 0, 0}}; + +// cver entry +extern "C" void vpi_compat_bootstrap(void) { + for (s_vpi_systf_data& systf : vpi_systf_data) vpi_register_systf(&systf); +} + +// icarus entry +void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; +#endif diff --git a/test_regress/t/t_vpi_forceable_bad.out b/test_regress/t/t_vpi_forceable_bad.out new file mode 100644 index 000000000..cfac5bfe4 --- /dev/null +++ b/test_regress/t/t_vpi_forceable_bad.out @@ -0,0 +1,2 @@ +%Error: vpi_put_value used with vpiForceFlag on non-forceable signal 't.nonForceableSignal' +Aborting... diff --git a/test_regress/t/t_vpi_forceable_bad.py b/test_regress/t/t_vpi_forceable_bad.py new file mode 100755 index 000000000..d82925bf2 --- /dev/null +++ b/test_regress/t/t_vpi_forceable_bad.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, + make_main=False, + make_pli=True, + verilator_flags2=["--binary --vpi", test.pli_filename]) + +test.execute(use_libvpi=True, + fails=test.vlt_all, + expect_filename=test.golden_filename, + check_finished=test.iv) # or check_finished=test.xrun + +test.passes() diff --git a/test_regress/t/t_vpi_forceable_bad.v b/test_regress/t/t_vpi_forceable_bad.v new file mode 100644 index 000000000..13a053d97 --- /dev/null +++ b/test_regress/t/t_vpi_forceable_bad.v @@ -0,0 +1,51 @@ +// ====================================================================== +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Christian Hecken +// SPDX-License-Identifier: CC0-1.0 +// ====================================================================== + +module t; + +`ifdef IVERILOG +`elsif USE_VPI_NOT_DPI +`ifdef VERILATOR +`systemc_header + extern "C" int forceValue(); +`verilog +`endif +`else + import "DPI-C" context function int forceValue(); +`endif + + wire nonForceableSignal /*verilator public_flat_rw*/ = 1'b0; + integer vpiStatus = 1; + + initial begin + +`ifdef VERILATOR +`ifdef USE_VPI_NOT_DPI + vpiStatus = $c32("forceValue()"); +`else + vpiStatus = forceValue(); +`endif +`elsif IVERILOG + vpiStatus = $forceValue; +`elsif USE_VPI_NOT_DPI + vpiStatus = $forceValue; +`else + vpiStatus = forceValue(); +`endif + + if (vpiStatus != 0) begin + $write("%%Error: t_vpi_forceable_bad.cpp:%0d:", vpiStatus); + $display("C Test failed (could not force value)"); + $stop; + end + vpiStatus = 1; // Reset status to ensure that a function *not* getting + // called also causes failure + + $display("*-* All Finished *-*"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_vpi_get.cpp b/test_regress/t/t_vpi_get.cpp index 7a9e5711f..93e957cea 100644 --- a/test_regress/t/t_vpi_get.cpp +++ b/test_regress/t/t_vpi_get.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_get.py b/test_regress/t/t_vpi_get.py index 9f7ed1832..499796518 100755 --- a/test_regress/t/t_vpi_get.py +++ b/test_regress/t/t_vpi_get.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_get.v b/test_regress/t/t_vpi_get.v index ec1fbc4d4..0a673a05e 100644 --- a/test_regress/t/t_vpi_get.v +++ b/test_regress/t/t_vpi_get.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI diff --git a/test_regress/t/t_vpi_get_public_rw_switch.py b/test_regress/t/t_vpi_get_public_rw_switch.py index b6e094445..158ec956a 100755 --- a/test_regress/t/t_vpi_get_public_rw_switch.py +++ b/test_regress/t/t_vpi_get_public_rw_switch.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_get_value_array.cpp b/test_regress/t/t_vpi_get_value_array.cpp index 621d1ac62..c2564447a 100644 --- a/test_regress/t/t_vpi_get_value_array.cpp +++ b/test_regress/t/t_vpi_get_value_array.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2024 by Diego Roux. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Diego Roux // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_get_value_array.py b/test_regress/t/t_vpi_get_value_array.py index 9f7ed1832..499796518 100755 --- a/test_regress/t/t_vpi_get_value_array.py +++ b/test_regress/t/t_vpi_get_value_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_get_value_array.v b/test_regress/t/t_vpi_get_value_array.v index 86a82df92..522141003 100644 --- a/test_regress/t/t_vpi_get_value_array.v +++ b/test_regress/t/t_vpi_get_value_array.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Diego Roux. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Diego Roux // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR_COMMENTS diff --git a/test_regress/t/t_vpi_hierarchy_clear.cpp b/test_regress/t/t_vpi_hierarchy_clear.cpp index a304477e4..518f20f28 100644 --- a/test_regress/t/t_vpi_hierarchy_clear.cpp +++ b/test_regress/t/t_vpi_hierarchy_clear.cpp @@ -1,6 +1,6 @@ // ====================================================================== -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Christian Hecken // SPDX-License-Identifier: CC0-1.0 // ====================================================================== diff --git a/test_regress/t/t_vpi_hierarchy_clear.py b/test_regress/t/t_vpi_hierarchy_clear.py index c850792e2..de86a91e5 100755 --- a/test_regress/t/t_vpi_hierarchy_clear.py +++ b/test_regress/t/t_vpi_hierarchy_clear.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_hierarchy_clear.v b/test_regress/t/t_vpi_hierarchy_clear.v index 190886548..1069dd580 100644 --- a/test_regress/t/t_vpi_hierarchy_clear.v +++ b/test_regress/t/t_vpi_hierarchy_clear.v @@ -1,6 +1,6 @@ // ====================================================================== -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Christian Hecken // SPDX-License-Identifier: CC0-1.0 // ====================================================================== diff --git a/test_regress/t/t_vpi_memory.cpp b/test_regress/t/t_vpi_memory.cpp index 857ee2d90..f536d25d0 100644 --- a/test_regress/t/t_vpi_memory.cpp +++ b/test_regress/t/t_vpi_memory.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_memory.py b/test_regress/t/t_vpi_memory.py index 31a4ce4b1..83449045d 100755 --- a/test_regress/t/t_vpi_memory.py +++ b/test_regress/t/t_vpi_memory.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_memory.v b/test_regress/t/t_vpi_memory.v index 11696d6f6..26d873254 100644 --- a/test_regress/t/t_vpi_memory.v +++ b/test_regress/t/t_vpi_memory.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI diff --git a/test_regress/t/t_vpi_module.cpp b/test_regress/t/t_vpi_module.cpp index a0a3c030f..169088f84 100644 --- a/test_regress/t/t_vpi_module.cpp +++ b/test_regress/t/t_vpi_module.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_module.py b/test_regress/t/t_vpi_module.py index ef8a5d334..2c06858e9 100755 --- a/test_regress/t/t_vpi_module.py +++ b/test_regress/t/t_vpi_module.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_module.v b/test_regress/t/t_vpi_module.v index be1d4a46c..aa6c6a8bd 100644 --- a/test_regress/t/t_vpi_module.v +++ b/test_regress/t/t_vpi_module.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifndef IVERILOG diff --git a/test_regress/t/t_vpi_module_dpi.py b/test_regress/t/t_vpi_module_dpi.py index 879bda0ca..65cf40b86 100755 --- a/test_regress/t/t_vpi_module_dpi.py +++ b/test_regress/t/t_vpi_module_dpi.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_module_empty.cpp b/test_regress/t/t_vpi_module_empty.cpp index f08ebb27d..652a6a5a0 100644 --- a/test_regress/t/t_vpi_module_empty.cpp +++ b/test_regress/t/t_vpi_module_empty.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_module_empty.py b/test_regress/t/t_vpi_module_empty.py index ef8a5d334..2c06858e9 100755 --- a/test_regress/t/t_vpi_module_empty.py +++ b/test_regress/t/t_vpi_module_empty.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_module_empty.v b/test_regress/t/t_vpi_module_empty.v index cd0f78d34..dd193f7f2 100644 --- a/test_regress/t/t_vpi_module_empty.v +++ b/test_regress/t/t_vpi_module_empty.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 interface sv_if(); diff --git a/test_regress/t/t_vpi_multidim.cpp b/test_regress/t/t_vpi_multidim.cpp index 848c5bc7c..8174ee705 100644 --- a/test_regress/t/t_vpi_multidim.cpp +++ b/test_regress/t/t_vpi_multidim.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_multidim.py b/test_regress/t/t_vpi_multidim.py index ab0961ef9..e891344e5 100755 --- a/test_regress/t/t_vpi_multidim.py +++ b/test_regress/t/t_vpi_multidim.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_multidim.v b/test_regress/t/t_vpi_multidim.v index 2cdd39c9b..d4f6d9f32 100644 --- a/test_regress/t/t_vpi_multidim.v +++ b/test_regress/t/t_vpi_multidim.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_vpi_onetime_cbs.cpp b/test_regress/t/t_vpi_onetime_cbs.cpp index b41bed563..441ffae76 100644 --- a/test_regress/t/t_vpi_onetime_cbs.cpp +++ b/test_regress/t/t_vpi_onetime_cbs.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2021 by Wilson Snyder and Marlon James. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2021 Wilson Snyder and Marlon James // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_onetime_cbs.py b/test_regress/t/t_vpi_onetime_cbs.py index 620a74cde..7c5bb911a 100755 --- a/test_regress/t/t_vpi_onetime_cbs.py +++ b/test_regress/t/t_vpi_onetime_cbs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_onetime_cbs.v b/test_regress/t/t_vpi_onetime_cbs.v index 3568bf9d7..33ca974e1 100644 --- a/test_regress/t/t_vpi_onetime_cbs.v +++ b/test_regress/t/t_vpi_onetime_cbs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Wilson Snyder and Marlon James. +// SPDX-FileCopyrightText: 2020 Wilson Snyder and Marlon James // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_vpi_package.cpp b/test_regress/t/t_vpi_package.cpp index c36b28f1e..409d78f6a 100644 --- a/test_regress/t/t_vpi_package.cpp +++ b/test_regress/t/t_vpi_package.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_package.py b/test_regress/t/t_vpi_package.py index 91593a3fe..aeab48da3 100755 --- a/test_regress/t/t_vpi_package.py +++ b/test_regress/t/t_vpi_package.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_package.v b/test_regress/t/t_vpi_package.v index b69e2cdad..4d51d187a 100644 --- a/test_regress/t/t_vpi_package.v +++ b/test_regress/t/t_vpi_package.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" context function int mon_check(); diff --git a/test_regress/t/t_vpi_param.cpp b/test_regress/t/t_vpi_param.cpp index d5700b10a..6396e22bb 100644 --- a/test_regress/t/t_vpi_param.cpp +++ b/test_regress/t/t_vpi_param.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_param.py b/test_regress/t/t_vpi_param.py index 31a4ce4b1..83449045d 100755 --- a/test_regress/t/t_vpi_param.py +++ b/test_regress/t/t_vpi_param.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_param.v b/test_regress/t/t_vpi_param.v index 4ae1dbb47..8e90125d8 100644 --- a/test_regress/t/t_vpi_param.v +++ b/test_regress/t/t_vpi_param.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI diff --git a/test_regress/t/t_vpi_public_depth.cpp b/test_regress/t/t_vpi_public_depth.cpp index e1bf6e2a6..61f9c4dea 100644 --- a/test_regress/t/t_vpi_public_depth.cpp +++ b/test_regress/t/t_vpi_public_depth.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_public_depth.py b/test_regress/t/t_vpi_public_depth.py index d5766b917..7dfbbde26 100755 --- a/test_regress/t/t_vpi_public_depth.py +++ b/test_regress/t/t_vpi_public_depth.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_public_depth.v b/test_regress/t/t_vpi_public_depth.v index 3766dfec3..a0ccafb40 100644 --- a/test_regress/t/t_vpi_public_depth.v +++ b/test_regress/t/t_vpi_public_depth.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifndef IVERILOG diff --git a/test_regress/t/t_vpi_public_depth_off.py b/test_regress/t/t_vpi_public_depth_off.py index 925b535de..0a5818489 100755 --- a/test_regress/t/t_vpi_public_depth_off.py +++ b/test_regress/t/t_vpi_public_depth_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_public_depthn.v b/test_regress/t/t_vpi_public_depthn.v index ee29e32d1..b1cfbba34 100644 --- a/test_regress/t/t_vpi_public_depthn.v +++ b/test_regress/t/t_vpi_public_depthn.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 interface AXIS_IF ( diff --git a/test_regress/t/t_vpi_public_depthn_1.py b/test_regress/t/t_vpi_public_depthn_1.py index fb9c03bc5..62caa1eed 100755 --- a/test_regress/t/t_vpi_public_depthn_1.py +++ b/test_regress/t/t_vpi_public_depthn_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_public_depthn_2.py b/test_regress/t/t_vpi_public_depthn_2.py index 398908a03..f3ef9238b 100755 --- a/test_regress/t/t_vpi_public_depthn_2.py +++ b/test_regress/t/t_vpi_public_depthn_2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_public_depthn_3.py b/test_regress/t/t_vpi_public_depthn_3.py index e3d95f1a4..9d9be297b 100755 --- a/test_regress/t/t_vpi_public_depthn_3.py +++ b/test_regress/t/t_vpi_public_depthn_3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_public_off.py b/test_regress/t/t_vpi_public_off.py index 34b624b8e..171a80e92 100755 --- a/test_regress/t/t_vpi_public_off.py +++ b/test_regress/t/t_vpi_public_off.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_public_params.py b/test_regress/t/t_vpi_public_params.py index 43d10bc97..26d0b8c0e 100755 --- a/test_regress/t/t_vpi_public_params.py +++ b/test_regress/t/t_vpi_public_params.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_public_params.v b/test_regress/t/t_vpi_public_params.v index 6286e7481..8be64a20e 100644 --- a/test_regress/t/t_vpi_public_params.v +++ b/test_regress/t/t_vpi_public_params.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI diff --git a/test_regress/t/t_vpi_put_value_array.cpp b/test_regress/t/t_vpi_put_value_array.cpp index b8f8c65a7..e0749093f 100644 --- a/test_regress/t/t_vpi_put_value_array.cpp +++ b/test_regress/t/t_vpi_put_value_array.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2024 by Diego Roux. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Diego Roux // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_put_value_array.py b/test_regress/t/t_vpi_put_value_array.py index 9f7ed1832..499796518 100755 --- a/test_regress/t/t_vpi_put_value_array.py +++ b/test_regress/t/t_vpi_put_value_array.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_put_value_array.v b/test_regress/t/t_vpi_put_value_array.v index f0aefe35b..c9c04397c 100644 --- a/test_regress/t/t_vpi_put_value_array.v +++ b/test_regress/t/t_vpi_put_value_array.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2024 by Diego Roux. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it under +// the terms of either the GNU Lesser General Public License Version 3 or the +// Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2024 Diego Roux // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR_COMMENTS diff --git a/test_regress/t/t_vpi_release_dup_bad.py b/test_regress/t/t_vpi_release_dup_bad.py index f49cdbdec..fcf0fe88b 100755 --- a/test_regress/t/t_vpi_release_dup_bad.py +++ b/test_regress/t/t_vpi_release_dup_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_release_dup_bad.v b/test_regress/t/t_vpi_release_dup_bad.v index 7a54f1b06..605660bd2 100644 --- a/test_regress/t/t_vpi_release_dup_bad.v +++ b/test_regress/t/t_vpi_release_dup_bad.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under The Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 import "DPI-C" context function void dpii_check(); diff --git a/test_regress/t/t_vpi_release_dup_bad_c.cpp b/test_regress/t/t_vpi_release_dup_bad_c.cpp index d78f3f329..62ea5781b 100644 --- a/test_regress/t/t_vpi_release_dup_bad_c.cpp +++ b/test_regress/t/t_vpi_release_dup_bad_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2011 by Wilson Snyder. This program is free software; you -// can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_repetitive_cbs.cpp b/test_regress/t/t_vpi_repetitive_cbs.cpp index 1ed4e48f6..e1d82a101 100644 --- a/test_regress/t/t_vpi_repetitive_cbs.cpp +++ b/test_regress/t/t_vpi_repetitive_cbs.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder and Marlon James // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_repetitive_cbs.py b/test_regress/t/t_vpi_repetitive_cbs.py index 620a74cde..7c5bb911a 100755 --- a/test_regress/t/t_vpi_repetitive_cbs.py +++ b/test_regress/t/t_vpi_repetitive_cbs.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_repetitive_cbs.v b/test_regress/t/t_vpi_repetitive_cbs.v index 3568bf9d7..33ca974e1 100644 --- a/test_regress/t/t_vpi_repetitive_cbs.v +++ b/test_regress/t/t_vpi_repetitive_cbs.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 Wilson Snyder and Marlon James. +// SPDX-FileCopyrightText: 2020 Wilson Snyder and Marlon James // SPDX-License-Identifier: CC0-1.0 diff --git a/test_regress/t/t_vpi_sc.cpp b/test_regress/t/t_vpi_sc.cpp index 71f45e2aa..e1bad2b62 100644 --- a/test_regress/t/t_vpi_sc.cpp +++ b/test_regress/t/t_vpi_sc.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_vpi_sc.py b/test_regress/t/t_vpi_sc.py index cf18f768b..bb2cd47cf 100755 --- a/test_regress/t/t_vpi_sc.py +++ b/test_regress/t/t_vpi_sc.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_sc.v b/test_regress/t/t_vpi_sc.v index fdd3bc959..2453b4841 100644 --- a/test_regress/t/t_vpi_sc.v +++ b/test_regress/t/t_vpi_sc.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_vpi_stop_bad.py b/test_regress/t/t_vpi_stop_bad.py index fb9404ffa..652535171 100755 --- a/test_regress/t/t_vpi_stop_bad.py +++ b/test_regress/t/t_vpi_stop_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_stop_bad.v b/test_regress/t/t_vpi_stop_bad.v index 4028992ff..87dfe5dd0 100644 --- a/test_regress/t/t_vpi_stop_bad.v +++ b/test_regress/t/t_vpi_stop_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_vpi_stop_bad_c.cpp b/test_regress/t/t_vpi_stop_bad_c.cpp index f66641e1e..80ca9862e 100644 --- a/test_regress/t/t_vpi_stop_bad_c.cpp +++ b/test_regress/t/t_vpi_stop_bad_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2009-2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_time_cb.cpp b/test_regress/t/t_vpi_time_cb.cpp index 8bc06e2f1..1aa0da70c 100644 --- a/test_regress/t/t_vpi_time_cb.cpp +++ b/test_regress/t/t_vpi_time_cb.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_time_cb.py b/test_regress/t/t_vpi_time_cb.py index a0b1ae435..183cbded4 100755 --- a/test_regress/t/t_vpi_time_cb.py +++ b/test_regress/t/t_vpi_time_cb.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_time_cb.v b/test_regress/t/t_vpi_time_cb.v index 5b1249718..e6659e5e8 100644 --- a/test_regress/t/t_vpi_time_cb.v +++ b/test_regress/t/t_vpi_time_cb.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" function void dpii_init(); diff --git a/test_regress/t/t_vpi_time_cb_c.cpp b/test_regress/t/t_vpi_time_cb_c.cpp index 4f69d232c..9dbcbac7b 100644 --- a/test_regress/t/t_vpi_time_cb_c.cpp +++ b/test_regress/t/t_vpi_time_cb_c.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_unimpl.cpp b/test_regress/t/t_vpi_unimpl.cpp index 732b30d53..05e998241 100644 --- a/test_regress/t/t_vpi_unimpl.cpp +++ b/test_regress/t/t_vpi_unimpl.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_unimpl.py b/test_regress/t/t_vpi_unimpl.py index 24ecd0ed9..efe2ab890 100755 --- a/test_regress/t/t_vpi_unimpl.py +++ b/test_regress/t/t_vpi_unimpl.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_unimpl.v b/test_regress/t/t_vpi_unimpl.v index b7ec59af2..924be11be 100644 --- a/test_regress/t/t_vpi_unimpl.v +++ b/test_regress/t/t_vpi_unimpl.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR diff --git a/test_regress/t/t_vpi_var.cpp b/test_regress/t/t_vpi_var.cpp index b5a8bccb4..caf9be138 100644 --- a/test_regress/t/t_vpi_var.cpp +++ b/test_regress/t/t_vpi_var.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -419,6 +419,28 @@ int _mon_check_var() { CHECK_RESULT(d, vpiUndefined); } + // other unsigned types + { + TestVpiHandle vh999 = VPI_HANDLE("bit1"); + CHECK_RESULT_NZ(vh999); + d = vpi_get(vpiType, vh999); + CHECK_RESULT(d, vpiBitVar); // Required by uvm_hdl_polling + for (PLI_INT32 i : {vpi0, vpi1, vpiX, vpiZ}) { + t_vpi_value value; + value.format = vpiScalarVal; + value.value.scalar = i; + vpi_put_value(vh999, &value, NULL, vpiNoDelay); + value.value.scalar = 9; + vpi_get_value(vh999, &value); +#ifdef VERILATOR // 2-state + const PLI_INT32 expv = (i == vpi1) ? vpi1 : vpi0; +#else + const PLI_INT32 expv = i; +#endif + TEST_CHECK_EQ(value.value.scalar, expv); + } + } + // other integer types tmpValue.format = vpiIntVal; constexpr struct { @@ -475,6 +497,28 @@ int _mon_check_var() { return errors; } +int _mon_check_rev() { + t_vpi_value value; + TestVpiHandle vh9 = VPI_HANDLE("rev"); + CHECK_RESULT_NZ(vh9); + value.format = vpiIntVal; + { + TestVpiHandle vh10 = vpi_handle(vpiLeftRange, vh9); + CHECK_RESULT_NZ(vh10); + vpi_get_value(vh10, &value); + TEST_CHECK_EQ(value.value.integer, 8); + TestVpiHandle vh11 = vpi_handle(vpiRightRange, vh9); + CHECK_RESULT_NZ(vh11); + vpi_get_value(vh11, &value); + TEST_CHECK_EQ(value.value.integer, 19); + + value.format = vpiVectorVal; + vpi_get_value(vh9, &value); + CHECK_RESULT(value.value.vector[0].aval, 0xabc); + } + return errors; +} + int _mon_check_varlist() { const char* p; @@ -789,10 +833,14 @@ int _mon_check_delayed() { CHECK_RESULT_NZ(vpi_chk_error(nullptr)); // This format throws an error now +#ifdef VERILATOR Verilated::fatalOnVpiError(false); +#endif v.format = vpiObjTypeVal; vpi_put_value(vh, &v, &t, vpiInertialDelay); +#ifdef VERILATOR Verilated::fatalOnVpiError(true); +#endif return 0; } @@ -993,6 +1041,7 @@ extern "C" int mon_check() { if (int status = _mon_check_callbacks()) return status; if (int status = _mon_check_value_callbacks()) return status; if (int status = _mon_check_var()) return status; + if (int status = _mon_check_rev()) return status; if (int status = _mon_check_varlist()) return status; if (int status = _mon_check_var_long_name()) return status; // Ports are not public_flat_rw in t_vpi_var diff --git a/test_regress/t/t_vpi_var.py b/test_regress/t/t_vpi_var.py index 610e7454d..86de3c42a 100755 --- a/test_regress/t/t_vpi_var.py +++ b/test_regress/t/t_vpi_var.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_var.v b/test_regress/t/t_vpi_var.v index a94fab60d..0adcdf638 100644 --- a/test_regress/t/t_vpi_var.v +++ b/test_regress/t/t_vpi_var.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI @@ -37,6 +37,7 @@ extern "C" int mon_check(); // verilator lint_off ASCRANGE reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */; + reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */; // verilator lint_on ASCRANGE reg [31:0] count /*verilator public_flat */; @@ -53,6 +54,7 @@ extern "C" int mon_check(); integer status; + bit bit1 /*verilator public_flat_rw */; integer integer1 /*verilator public_flat_rw */; byte byte1 /*verilator public_flat_rw */; shortint short1 /*verilator public_flat_rw */; @@ -81,6 +83,7 @@ extern "C" int mon_check(); text = "Verilog Test module"; too_big = "some text"; + bit1 = 1; integer1 = 123; byte1 = 123; short1 = 123; @@ -89,6 +92,8 @@ extern "C" int mon_check(); real1 = 1.0; str1 = "hello"; + rev = 12'habc; + `ifdef VERILATOR status = $c32("mon_check()"); `endif diff --git a/test_regress/t/t_vpi_var2.py b/test_regress/t/t_vpi_var2.py index 62511e4cb..7d4a550b1 100755 --- a/test_regress/t/t_vpi_var2.py +++ b/test_regress/t/t_vpi_var2.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_var2.v b/test_regress/t/t_vpi_var2.v index 53329b4cb..bea0e11e8 100644 --- a/test_regress/t/t_vpi_var2.v +++ b/test_regress/t/t_vpi_var2.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2023 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI @@ -47,6 +47,7 @@ extern "C" int mon_check(); reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; // verilator lint_off ASCRANGE reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk)*/; + reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */; /*verilator public_off*/ reg invisible1; // verilator lint_on ASCRANGE @@ -72,6 +73,7 @@ extern "C" int mon_check(); integer status; /*verilator public_flat_rw_on*/ + bit bit1; integer integer1; byte byte1; shortint short1; @@ -98,6 +100,7 @@ extern "C" int mon_check(); text = "Verilog Test module"; too_big = "some text"; + bit1 = 1; integer1 = 123; byte1 = 123; short1 = 123; @@ -106,6 +109,8 @@ extern "C" int mon_check(); real1 = 1.0; str1 = "hello"; + rev = 12'habc; + `ifdef VERILATOR status = $c32("mon_check()"); `endif diff --git a/test_regress/t/t_vpi_var3.py b/test_regress/t/t_vpi_var3.py index f4a2b3cc4..7b2d9f412 100755 --- a/test_regress/t/t_vpi_var3.py +++ b/test_regress/t/t_vpi_var3.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_var3.v b/test_regress/t/t_vpi_var3.v index f5565dd48..0870059cd 100644 --- a/test_regress/t/t_vpi_var3.v +++ b/test_regress/t/t_vpi_var3.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI @@ -37,6 +37,7 @@ extern "C" int mon_check(); // verilator lint_off ASCRANGE reg [0:61] quads[2:3]; + reg [8:19] rev /*verilator public_flat_rw @(posedge clk) */; // verilator lint_on ASCRANGE reg [31:0] count; @@ -53,6 +54,7 @@ extern "C" int mon_check(); integer status; + bit bit1; integer integer1; byte byte1; shortint short1; @@ -78,6 +80,7 @@ extern "C" int mon_check(); text = "Verilog Test module"; too_big = "some text"; + bit1 = 1; integer1 = 123; byte1 = 123; short1 = 123; @@ -86,6 +89,8 @@ extern "C" int mon_check(); real1 = 1.0; str1 = "hello"; + rev = 12'habc; + `ifdef VERILATOR status = $c32("mon_check()"); `endif diff --git a/test_regress/t/t_vpi_zero_time_cb.cpp b/test_regress/t/t_vpi_zero_time_cb.cpp index e19bd7f38..82b742ccc 100644 --- a/test_regress/t/t_vpi_zero_time_cb.cpp +++ b/test_regress/t/t_vpi_zero_time_cb.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010-2011 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_zero_time_cb.py b/test_regress/t/t_vpi_zero_time_cb.py index aff674d1e..4fc9bb5f7 100755 --- a/test_regress/t/t_vpi_zero_time_cb.py +++ b/test_regress/t/t_vpi_zero_time_cb.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_vpi_zero_time_cb.v b/test_regress/t/t_vpi_zero_time_cb.v index 1ac2d001f..153e29b61 100644 --- a/test_regress/t/t_vpi_zero_time_cb.v +++ b/test_regress/t/t_vpi_zero_time_cb.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2010 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_vthread.py b/test_regress/t/t_vthread.py index 670b5c0fa..d783c2065 100755 --- a/test_regress/t/t_vthread.py +++ b/test_regress/t/t_vthread.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wait.out b/test_regress/t/t_wait.out index 9b6b885fb..a9de9bb96 100644 --- a/test_regress/t/t_wait.out +++ b/test_regress/t/t_wait.out @@ -1,40 +1,40 @@ -%Error-NOTIMING: t/t_wait.v:12:7: Wait statements require --timing +%Error-NOTIMING: t/t_wait.v:12:5: Wait statements require --timing : ... note: In instance 't' - 12 | wait (value == 1); - | ^~~~ + 12 | wait (value == 1); + | ^~~~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest -%Error-NOTIMING: t/t_wait.v:14:7: Wait statements require --timing +%Error-NOTIMING: t/t_wait.v:14:5: Wait statements require --timing : ... note: In instance 't' - 14 | wait (0); - | ^~~~ -%Error-NOTIMING: t/t_wait.v:17:7: Wait statements require --timing + 14 | wait (0); + | ^~~~ +%Error-NOTIMING: t/t_wait.v:17:5: Wait statements require --timing : ... note: In instance 't' - 17 | wait (value == 2); - | ^~~~ -%Error-NOTIMING: t/t_wait.v:20:7: Wait statements require --timing + 17 | wait (value == 2); + | ^~~~ +%Error-NOTIMING: t/t_wait.v:20:5: Wait statements require --timing : ... note: In instance 't' - 20 | wait (value == 3) if (value != 3) $stop; - | ^~~~ -%Warning-STMTDLY: t/t_wait.v:25:7: Ignoring delay on this statement due to --no-timing + 20 | wait (value == 3) if (value != 3) $stop; + | ^~~~ +%Warning-STMTDLY: t/t_wait.v:25:5: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 25 | #10; - | ^ + 25 | #10; + | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. -%Warning-STMTDLY: t/t_wait.v:27:7: Ignoring delay on this statement due to --no-timing +%Warning-STMTDLY: t/t_wait.v:27:5: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 27 | #10; - | ^ -%Warning-STMTDLY: t/t_wait.v:29:7: Ignoring delay on this statement due to --no-timing + 27 | #10; + | ^ +%Warning-STMTDLY: t/t_wait.v:29:5: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 29 | #10; - | ^ -%Warning-STMTDLY: t/t_wait.v:31:7: Ignoring delay on this statement due to --no-timing + 29 | #10; + | ^ +%Warning-STMTDLY: t/t_wait.v:31:5: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 31 | #10; - | ^ -%Warning-STMTDLY: t/t_wait.v:33:7: Ignoring delay on this statement due to --no-timing + 31 | #10; + | ^ +%Warning-STMTDLY: t/t_wait.v:33:5: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 33 | #10; - | ^ + 33 | #10; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_wait.py b/test_regress/t/t_wait.py index 8fe17ddf9..f4a8053d2 100755 --- a/test_regress/t/t_wait.py +++ b/test_regress/t/t_wait.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wait.v b/test_regress/t/t_wait.v index 91a271a86..2bfa7f2c5 100644 --- a/test_regress/t/t_wait.v +++ b/test_regress/t/t_wait.v @@ -1,38 +1,38 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - int value; + int value; - initial begin - wait (value == 1); - if (value != 1) $stop; - wait (0); - if (value != 1) $stop; - // - wait (value == 2); - if (value != 2) $stop; - // - wait (value == 3) if (value != 3) $stop; - if (value != 3) $stop; - end + initial begin + wait (value == 1); + if (value != 1) $stop; + wait (0); + if (value != 1) $stop; + // + wait (value == 2); + if (value != 2) $stop; + // + wait (value == 3) if (value != 3) $stop; + if (value != 3) $stop; + end - initial begin - #10; - value = 1; - #10; - value = 2; - #10; - value = 3; - #10; - value = 4; - #10; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + #10; + value = 1; + #10; + value = 2; + #10; + value = 3; + #10; + value = 4; + #10; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_wait_const.py b/test_regress/t/t_wait_const.py index a1700c6d9..a36e184d4 100755 --- a/test_regress/t/t_wait_const.py +++ b/test_regress/t/t_wait_const.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wait_const.v b/test_regress/t/t_wait_const.v index a1972bb22..50cca094c 100644 --- a/test_regress/t/t_wait_const.v +++ b/test_regress/t/t_wait_const.v @@ -1,19 +1,19 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - // This test is separate from t_wait.v because we needed a process with - // just one wait of a non-zero to see a bug where GCC gave "return value - // not used" - // verilator lint_off WAITCONST - wait (1); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // This test is separate from t_wait.v because we needed a process with + // just one wait of a non-zero to see a bug where GCC gave "return value + // not used" + // verilator lint_off WAITCONST + wait (1); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_wait_fork.py b/test_regress/t/t_wait_fork.py index 2bf2a6f4f..93cb34ac2 100755 --- a/test_regress/t/t_wait_fork.py +++ b/test_regress/t/t_wait_fork.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wait_fork.v b/test_regress/t/t_wait_fork.v index 159087ffa..3dc4e5def 100644 --- a/test_regress/t/t_wait_fork.v +++ b/test_regress/t/t_wait_fork.v @@ -1,25 +1,29 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - logic never; + logic never; - integer n = 0; + integer n = 0; - initial begin - disable fork; - fork - #10 if (n != 0) $stop; else n = 1; - #15 if (n != 1) $stop; else n = 2; - join_none - wait fork; - if (n != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + disable fork; + fork + #10 + if (n != 0) $stop; + else n = 1; + #15 + if (n != 1) $stop; + else n = 2; + join_none + wait fork; + if (n != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_wait_no_triggered_bad.out b/test_regress/t/t_wait_no_triggered_bad.out old mode 100755 new mode 100644 index 3b8332e3e..a2a998d21 --- a/test_regress/t/t_wait_no_triggered_bad.out +++ b/test_regress/t/t_wait_no_triggered_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_wait_no_triggered_bad.v:15:12: Wait statement conditions do not take raw events (IEEE 1800-2023 15.5.3) +%Error: t/t_wait_no_triggered_bad.v:15:11: Wait statement conditions do not take raw events (IEEE 1800-2023 15.5.3) : ... note: In instance 't' : ... Suggest use 'e_my_event.triggered' - 15 | wait(e_my_event); - | ^~~~~~~~~~ + 15 | wait (e_my_event); + | ^~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_wait_no_triggered_bad.py b/test_regress/t/t_wait_no_triggered_bad.py index 31228c9a7..c7d9b21a5 100755 --- a/test_regress/t/t_wait_no_triggered_bad.py +++ b/test_regress/t/t_wait_no_triggered_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wait_no_triggered_bad.v b/test_regress/t/t_wait_no_triggered_bad.v index 0d827874d..ba0863d48 100644 --- a/test_regress/t/t_wait_no_triggered_bad.v +++ b/test_regress/t/t_wait_no_triggered_bad.v @@ -1,21 +1,21 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - event e_my_event; + event e_my_event; - initial begin - #(1us); - wait(e_my_event.triggered); // Ok - #(1us); - wait(e_my_event); // Bad + initial begin + #(1us); + wait (e_my_event.triggered); // Ok + #(1us); + wait (e_my_event); // Bad - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_wait_order.out b/test_regress/t/t_wait_order.out index 9f5cdd27e..15c01267f 100644 --- a/test_regress/t/t_wait_order.out +++ b/test_regress/t/t_wait_order.out @@ -1,17 +1,17 @@ -%Error-UNSUPPORTED: t/t_wait_order.v:17:23: Unsupported: wait_order - 17 | wait_order (a, b) wif[0] = '1; - | ^ +%Error-UNSUPPORTED: t/t_wait_order.v:19:21: Unsupported: wait_order + 19 | wait_order (a, b) wif[0] = '1; + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_wait_order.v:26:23: Unsupported: wait_order - 26 | wait_order (a, b) else welse[1] = '1; - | ^ -%Error-UNSUPPORTED: t/t_wait_order.v:29:23: Unsupported: wait_order - 29 | wait_order (b, a) else nelse[1] = '1; - | ^ -%Error-UNSUPPORTED: t/t_wait_order.v:33:23: Unsupported: wait_order - 33 | wait_order (a, b) wif[2] = '1; else welse[2] = '1; - | ^ -%Error-UNSUPPORTED: t/t_wait_order.v:36:23: Unsupported: wait_order - 36 | wait_order (b, a) nif[2] = '1; else nelse[2] = '1; - | ^ +%Error-UNSUPPORTED: t/t_wait_order.v:28:21: Unsupported: wait_order + 28 | wait_order (a, b) else welse[1] = '1; + | ^ +%Error-UNSUPPORTED: t/t_wait_order.v:31:21: Unsupported: wait_order + 31 | wait_order (b, a) else nelse[1] = '1; + | ^ +%Error-UNSUPPORTED: t/t_wait_order.v:35:21: Unsupported: wait_order + 35 | wait_order (a, b) wif[2] = '1; else welse[2] = '1; + | ^ +%Error-UNSUPPORTED: t/t_wait_order.v:38:21: Unsupported: wait_order + 38 | wait_order (b, a) nif[2] = '1; else nelse[2] = '1; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_wait_order.py b/test_regress/t/t_wait_order.py index 22467ab79..c132b489d 100755 --- a/test_regress/t/t_wait_order.py +++ b/test_regress/t/t_wait_order.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wait_order.v b/test_regress/t/t_wait_order.v index 910454ade..5acdd1a22 100644 --- a/test_regress/t/t_wait_order.v +++ b/test_regress/t/t_wait_order.v @@ -1,63 +1,65 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - event a, b, c; - bit wif[10], welse[10]; - bit nif[10], nelse[10]; + event a, b, c; + bit wif[10], welse[10]; + bit nif[10], nelse[10]; - initial begin - wait_order (a, b) wif[0] = '1; - end + initial begin + wait_order (a, b) wif[0] = '1; + end `ifdef FAIL_ASSERT_1 - initial begin - wait_order (b, a) nif[0] = '1; - end + initial begin + wait_order (b, a) nif[0] = '1; + end `endif - initial begin - wait_order (a, b) else welse[1] = '1; - end - initial begin - wait_order (b, a) else nelse[1] = '1; - end + initial begin + wait_order (a, b) else welse[1] = '1; + end + initial begin + wait_order (b, a) else nelse[1] = '1; + end - initial begin - wait_order (a, b) wif[2] = '1; else welse[2] = '1; - end - initial begin - wait_order (b, a) nif[2] = '1; else nelse[2] = '1; - end + initial begin + wait_order (a, b) wif[2] = '1; else welse[2] = '1; + end + initial begin + wait_order (b, a) nif[2] = '1; else nelse[2] = '1; + end - initial begin - #10; - -> a; - #10; - -> b; - #10; - -> c; - #10; + initial begin + #10; + -> a; + #10; + -> b; + #10; + -> c; + #10; - `checkd(wif[0], 1'b1); - `checkd(nif[0], 1'b0); + `checkd(wif[0], 1'b1); + `checkd(nif[0], 1'b0); - `checkd(welse[1], 1'b0); - `checkd(nelse[1], 1'b1); + `checkd(welse[1], 1'b0); + `checkd(nelse[1], 1'b1); - `checkd(wif[2], 1'b1); - `checkd(welse[2], 1'b0); - `checkd(nif[2], 1'b0); - `checkd(nelse[2], 1'b1); + `checkd(wif[2], 1'b1); + `checkd(welse[2], 1'b0); + `checkd(nif[2], 1'b0); + `checkd(nelse[2], 1'b1); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_wait_timing.py b/test_regress/t/t_wait_timing.py index dce50a25c..56e3b606d 100755 --- a/test_regress/t/t_wait_timing.py +++ b/test_regress/t/t_wait_timing.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_waiveroutput.py b/test_regress/t/t_waiveroutput.py index df3799f05..3d2b380ef 100755 --- a/test_regress/t/t_waiveroutput.py +++ b/test_regress/t/t_waiveroutput.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_waiveroutput.v b/test_regress/t/t_waiveroutput.v index f3441479c..56c446820 100644 --- a/test_regress/t/t_waiveroutput.v +++ b/test_regress/t/t_waiveroutput.v @@ -1,15 +1,15 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t_waiveroutput; - reg width_warn = 2'b11; // Width warning - must be line 8 + reg width_warn = 2'b11; // Width warning - must be line 8 - // verilator lint_off UNUSEDSIGNAL - // verilator lint_off WIDTHTRUNC - reg width_warn2 = 2'b11; - // verilator lint_on UNUSEDSIGNAL - // verilator lint_on WIDTHTRUNC + // verilator lint_off UNUSEDSIGNAL + // verilator lint_off WIDTHTRUNC + reg width_warn2 = 2'b11; + // verilator lint_on UNUSEDSIGNAL + // verilator lint_on WIDTHTRUNC endmodule diff --git a/test_regress/t/t_waiveroutput.vlt b/test_regress/t/t_waiveroutput.vlt index 5771d85dc..4f842eb18 100644 --- a/test_regress/t/t_waiveroutput.vlt +++ b/test_regress/t/t_waiveroutput.vlt @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_waiveroutput_allgood.py b/test_regress/t/t_waiveroutput_allgood.py index 502abc15b..aa2b64137 100755 --- a/test_regress/t/t_waiveroutput_allgood.py +++ b/test_regress/t/t_waiveroutput_allgood.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_waiveroutput_multiline.py b/test_regress/t/t_waiveroutput_multiline.py index ddbe93341..d4274bb75 100755 --- a/test_regress/t/t_waiveroutput_multiline.py +++ b/test_regress/t/t_waiveroutput_multiline.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_waiveroutput_roundtrip.py b/test_regress/t/t_waiveroutput_roundtrip.py index 39834358b..e3bc2e547 100755 --- a/test_regress/t/t_waiveroutput_roundtrip.py +++ b/test_regress/t/t_waiveroutput_roundtrip.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_waiveroutput_roundtrip.v b/test_regress/t/t_waiveroutput_roundtrip.v index d9f68bdf1..e0c2318bf 100644 --- a/test_regress/t/t_waiveroutput_roundtrip.v +++ b/test_regress/t/t_waiveroutput_roundtrip.v @@ -1,38 +1,42 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - out, out2, - // Inputs - clk, a0, d0, d1 - ); +module t ( /*AUTOARG*/ + // Outputs + out, + out2, + // Inputs + clk, + a0, + d0, + d1 +); - input clk; - input [1:0] a0; - input [7:0] d0; - input [7:0] d1; - output reg [31:0] out; - output reg [15:0] out2; + input clk; + input [1:0] a0; + input [7:0] d0; + input [7:0] d1; + output reg [31:0] out; + output reg [15:0] out2; - reg [7:0] mem [4]; + reg [7:0] mem[4]; - always @(posedge clk) begin - mem[a0] <= d0; // <--- Warning - end - always @(negedge clk) begin - mem[a0] <= d1; // <--- Warning - end - assign out = {mem[3],mem[2],mem[1],mem[0]}; + always @(posedge clk) begin + mem[a0] <= d0; // <--- Warning + end + always @(negedge clk) begin + mem[a0] <= d1; // <--- Warning + end + assign out = {mem[3], mem[2], mem[1], mem[0]}; - always @(posedge clk) begin - out2[7:0] <= d0; // <--- Warning - end - always @(negedge clk) begin - out2[15:8] <= d0; // <--- Warning - end + always @(posedge clk) begin + out2[7:0] <= d0; // <--- Warning + end + always @(negedge clk) begin + out2[15:8] <= d0; // <--- Warning + end endmodule diff --git a/test_regress/t/t_while_cond_is_stmt.py b/test_regress/t/t_while_cond_is_stmt.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_while_cond_is_stmt.py +++ b/test_regress/t/t_while_cond_is_stmt.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_while_cond_is_stmt.v b/test_regress/t/t_while_cond_is_stmt.v index 9e7289d05..7bc31dcdb 100644 --- a/test_regress/t/t_while_cond_is_stmt.v +++ b/test_regress/t/t_while_cond_is_stmt.v @@ -1,29 +1,31 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - function int unsigned nth_power_of_2(input int unsigned n); - nth_power_of_2 = 1; - while (n != 0) begin - n = n - 1; - nth_power_of_2 = nth_power_of_2 << 1; - end - endfunction + function int unsigned nth_power_of_2(input int unsigned n); + nth_power_of_2 = 1; + while (n != 0) begin + n = n - 1; + nth_power_of_2 = nth_power_of_2 << 1; + end + endfunction - initial begin - // Evaluating the function call in the loop condition used - // to cause an infinite loop at run-time - while (nth_power_of_2(8) != 256) begin - $display("2**8 != 256 ?!"); - $stop; - end - - $write("*-* All Finished *-*\n"); - $finish; + initial begin + // Evaluating the function call in the loop condition used + // to cause an infinite loop at run-time + while (nth_power_of_2( + 8 + ) != 256) begin + $display("2**8 != 256 ?!"); + $stop; end + $write("*-* All Finished *-*\n"); + $finish; + end + endmodule diff --git a/test_regress/t/t_while_finish.py b/test_regress/t/t_while_finish.py index bd059b0f2..4ee7f9e14 100755 --- a/test_regress/t/t_while_finish.py +++ b/test_regress/t/t_while_finish.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_while_finish.v b/test_regress/t/t_while_finish.v index 82692197d..3ca0b7191 100644 --- a/test_regress/t/t_while_finish.v +++ b/test_regress/t/t_while_finish.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_while_timing_control.py b/test_regress/t/t_while_timing_control.py index 8303ed1f1..7e421df2e 100755 --- a/test_regress/t/t_while_timing_control.py +++ b/test_regress/t/t_while_timing_control.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_while_timing_control.v b/test_regress/t/t_while_timing_control.v index 11d54b9c6..21e0ec755 100644 --- a/test_regress/t/t_while_timing_control.v +++ b/test_regress/t/t_while_timing_control.v @@ -1,24 +1,24 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Antmicro Ltd. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(); - logic clk = 0; - logic out = 1; +module t; + logic clk = 0; + logic out = 1; - always #5 clk = ~clk; + always #5 clk = ~clk; - initial begin - while(1) begin - if(out) begin - break; - end - @(negedge clk); + initial begin + while (1) begin + if (out) begin + break; end + @(negedge clk); + end - $write("*-* All Finished *-*\n"); - $finish(); - end + $write("*-* All Finished *-*\n"); + $finish(); + end endmodule diff --git a/test_regress/t/t_wide_temp_while_cond.cpp b/test_regress/t/t_wide_temp_while_cond.cpp index d6e745f07..675cad9eb 100644 --- a/test_regress/t/t_wide_temp_while_cond.cpp +++ b/test_regress/t/t_wide_temp_while_cond.cpp @@ -2,10 +2,10 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2025 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2025 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* diff --git a/test_regress/t/t_wide_temp_while_cond.py b/test_regress/t/t_wide_temp_while_cond.py index d64df839f..65878e7d0 100755 --- a/test_regress/t/t_wide_temp_while_cond.py +++ b/test_regress/t/t_wide_temp_while_cond.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wide_temp_while_cond.v b/test_regress/t/t_wide_temp_while_cond.v index 2a88840c4..7911a4327 100644 --- a/test_regress/t/t_wide_temp_while_cond.v +++ b/test_regress/t/t_wide_temp_while_cond.v @@ -1,26 +1,26 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Geza Lore. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Geza Lore // SPDX-License-Identifier: CC0-1.0 import "DPI-C" pure function int identity(input int value); module t; - initial begin - int n = 0; - logic [127:0] val = 128'b1; - logic [15:0] one = 16'b1; + initial begin + automatic int n; + automatic logic [127:0] val = 128'b1; + automatic logic [15:0] one = 16'b1; - // This condition involves multiple wide temporaries, and an over-width - // shift, all of which requires V3Premit to fix up. - while (|((val[ 7'(one >> identity(32)) +: 96] << n) >> n)) begin - ++n; - end + // This condition involves multiple wide temporaries, and an over-width + // shift, all of which requires V3Premit to fix up. + while (|((val[ 7'(one >> identity(32)) +: 96] << n) >> n)) begin + ++n; + end - $display("n=%0d", n); - if (n != 96) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $display("n=%0d", n); + if (n != 96) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_wire_beh1364_bad.out b/test_regress/t/t_wire_beh1364_bad.out index 27c4fa6ac..d04e4140c 100644 --- a/test_regress/t/t_wire_beh1364_bad.out +++ b/test_regress/t/t_wire_beh1364_bad.out @@ -1,22 +1,22 @@ -%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' : ... note: In instance 't' - 26 | w = 0; - | ^ + 26 | w = 0; + | ^ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest -%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' : ... note: In instance 't' - 27 | o = 0; - | ^ -%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' + 27 | o = 0; + | ^ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' : ... note: In instance 't' - 28 | oa = 0; - | ^~ -%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'wo' + 28 | oa = 0; + | ^~ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:29:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'wo' : ... note: In instance 't' - 29 | wo = 0; - | ^~ -%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:30:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'woa' + 29 | wo = 0; + | ^~ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:30:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'woa' : ... note: In instance 't' - 30 | woa = 0; - | ^~~ + 30 | woa = 0; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_beh1364_bad.py b/test_regress/t/t_wire_beh1364_bad.py index 797770aeb..a7b6ba93f 100755 --- a/test_regress/t/t_wire_beh1364_bad.py +++ b/test_regress/t/t_wire_beh1364_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wire_beh1364_bad.v b/test_regress/t/t_wire_beh1364_bad.v index d983139f8..6cb6c07e3 100644 --- a/test_regress/t/t_wire_beh1364_bad.v +++ b/test_regress/t/t_wire_beh1364_bad.v @@ -1,39 +1,39 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - o, oa, ro, roa, wo, woa - ); +module t ( /*AUTOARG*/ + // Outputs + o, oa, ro, roa, wo, woa + ); - wire w; - reg r; - output o; - output [1:0] oa; - output reg ro; - output reg [1:0] roa; - output wire wo; - output wire [1:0] woa; - //1800 only: - //output var vo; - //output var [1:0] voa; + wire w; + reg r; + output o; + output [1:0] oa; + output reg ro; + output reg [1:0] roa; + output wire wo; + output wire [1:0] woa; + //1800 only: + //output var vo; + //output var [1:0] voa; - initial begin - // Error - w = 0; - o = 0; - oa = 0; - wo = 0; - woa = 0; - // Not an error - r = 0; - ro = 0; - roa = 0; - //vo = 0; - //voa = 0; - end + initial begin + // Error + w = 0; + o = 0; + oa = 0; + wo = 0; + woa = 0; + // Not an error + r = 0; + ro = 0; + roa = 0; + //vo = 0; + //voa = 0; + end endmodule diff --git a/test_regress/t/t_wire_beh1800_bad.out b/test_regress/t/t_wire_beh1800_bad.out index c96825da8..0a2a0673f 100644 --- a/test_regress/t/t_wire_beh1800_bad.out +++ b/test_regress/t/t_wire_beh1800_bad.out @@ -1,22 +1,22 @@ -%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' : ... note: In instance 't' - 25 | w = '0; - | ^ + 25 | w = '0; + | ^ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest -%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' : ... note: In instance 't' - 26 | o = '0; - | ^ -%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' + 26 | o = '0; + | ^ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' : ... note: In instance 't' - 27 | oa = '0; - | ^~ -%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'wo' + 27 | oa = '0; + | ^~ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'wo' : ... note: In instance 't' - 28 | wo = '0; - | ^~ -%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'woa' + 28 | wo = '0; + | ^~ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:29:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'woa' : ... note: In instance 't' - 29 | woa = '0; - | ^~~ + 29 | woa = '0; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_beh1800_bad.py b/test_regress/t/t_wire_beh1800_bad.py index 2ce66844f..b6af58c86 100755 --- a/test_regress/t/t_wire_beh1800_bad.py +++ b/test_regress/t/t_wire_beh1800_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wire_beh1800_bad.v b/test_regress/t/t_wire_beh1800_bad.v index 9f080c9eb..bb43df9f7 100644 --- a/test_regress/t/t_wire_beh1800_bad.v +++ b/test_regress/t/t_wire_beh1800_bad.v @@ -1,37 +1,37 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - o, oa, ro, roa, wo, woa, vo, voa - ); + // Outputs + o, oa, ro, roa, wo, woa, vo, voa + ); - wire w; - reg r; - output o; - output [1:0] oa; - output reg ro; - output reg [1:0] roa; - output wire wo; - output wire [1:0] woa; - // 1800 only - output var vo; - output var [1:0] voa; + wire w; + reg r; + output o; + output [1:0] oa; + output reg ro; + output reg [1:0] roa; + output wire wo; + output wire [1:0] woa; + // 1800 only + output var vo; + output var [1:0] voa; - initial begin - w = '0; // Error - o = '0; // Error - oa = '0; // Error - wo = '0; // Error - woa = '0; // Error - r = '0; // Not an error - ro = '0; // Not an error - roa = '0; // Not an error - vo = '0; // Not an error - voa = '0; // Not an error - end + initial begin + w = '0; // Error + o = '0; // Error + oa = '0; // Error + wo = '0; // Error + woa = '0; // Error + r = '0; // Not an error + ro = '0; // Not an error + roa = '0; // Not an error + vo = '0; // Not an error + voa = '0; // Not an error + end endmodule diff --git a/test_regress/t/t_wire_behp1364_bad.out b/test_regress/t/t_wire_behp1364_bad.out index a5998991f..5b857fe69 100644 --- a/test_regress/t/t_wire_behp1364_bad.out +++ b/test_regress/t/t_wire_behp1364_bad.out @@ -1,14 +1,14 @@ -%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' +%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' : ... note: In instance 't' - 24 | w = 0; - | ^ + 24 | w = 0; + | ^ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest -%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' +%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:25:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' : ... note: In instance 't' - 25 | o = 0; - | ^ -%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' + 25 | o = 0; + | ^ +%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:26:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' : ... note: In instance 't' - 26 | oa = 0; - | ^~ + 26 | oa = 0; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_behp1364_bad.py b/test_regress/t/t_wire_behp1364_bad.py index c3c017906..cee56ddf4 100755 --- a/test_regress/t/t_wire_behp1364_bad.py +++ b/test_regress/t/t_wire_behp1364_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wire_behp1364_bad.v b/test_regress/t/t_wire_behp1364_bad.v index e88ea744d..e62416c31 100644 --- a/test_regress/t/t_wire_behp1364_bad.v +++ b/test_regress/t/t_wire_behp1364_bad.v @@ -1,37 +1,37 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( - output o, - output [1:0] oa, - output reg ro, - output reg [1:0] roa, - output wire wo, - output wire [1:0] woa - //1800 only: - //output var vo; - //output var [1:0] voa; - ); + output o, + output [1:0] oa, + output reg ro, + output reg [1:0] roa, + output wire wo, + output wire [1:0] woa + //1800 only: + //output var vo; + //output var [1:0] voa; +); - wire w; - reg r; + wire w; + reg r; - initial begin - // Error - w = 0; - o = 0; - oa = 0; - wo = 0; - woa = 0; - // Not an error - r = 0; - ro = 0; - roa = 0; - //vo = 0; - //voa = 0; - end + initial begin + // Error + w = 0; + o = 0; + oa = 0; + wo = 0; + woa = 0; + // Not an error + r = 0; + ro = 0; + roa = 0; + //vo = 0; + //voa = 0; + end endmodule diff --git a/test_regress/t/t_wire_behp1800_bad.out b/test_regress/t/t_wire_behp1800_bad.out index 6ccd52919..3e906dc5e 100644 --- a/test_regress/t/t_wire_behp1800_bad.out +++ b/test_regress/t/t_wire_behp1800_bad.out @@ -1,14 +1,14 @@ -%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' +%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'w' : ... note: In instance 't' - 23 | w = '0; - | ^ + 23 | w = '0; + | ^ ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest -%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' +%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'o' : ... note: In instance 't' - 24 | o = '0; - | ^ -%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' + 24 | o = '0; + | ^ +%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:25:5: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'oa' : ... note: In instance 't' - 25 | oa = '0; - | ^~ + 25 | oa = '0; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_behp1800_bad.py b/test_regress/t/t_wire_behp1800_bad.py index 2ce66844f..b6af58c86 100755 --- a/test_regress/t/t_wire_behp1800_bad.py +++ b/test_regress/t/t_wire_behp1800_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wire_behp1800_bad.v b/test_regress/t/t_wire_behp1800_bad.v index b80f7c041..ecadc3c57 100644 --- a/test_regress/t/t_wire_behp1800_bad.v +++ b/test_regress/t/t_wire_behp1800_bad.v @@ -1,35 +1,35 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2018 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t ( - output o, - output [1:0] oa, - output reg ro, - output reg [1:0] roa, - output wire wo, - output wire [1:0] woa, - // 1800 only - output var vo, - output var [1:0] voa - ); + output o, + output [1:0] oa, + output reg ro, + output reg [1:0] roa, + output wire wo, + output wire [1:0] woa, + // 1800 only + output var vo, + output var [1:0] voa +); - wire w; - reg r; + wire w; + reg r; - initial begin - w = '0; // Error - o = '0; // Error - oa = '0; // Error - wo = '0; // Error - woa = '0; // Error - r = '0; // Not an error - ro = '0; // Not an error - roa = '0; // Not an error - vo = '0; // Not an error - voa = '0; // Not an error - end + initial begin + w = '0; // Error + o = '0; // Error + oa = '0; // Error + wo = '0; // Error + woa = '0; // Error + r = '0; // Not an error + ro = '0; // Not an error + roa = '0; // Not an error + vo = '0; // Not an error + voa = '0; // Not an error + end endmodule diff --git a/test_regress/t/t_wire_self_bad.out b/test_regress/t/t_wire_self_bad.out index 0404b753d..c72b6bff5 100644 --- a/test_regress/t/t_wire_self_bad.out +++ b/test_regress/t/t_wire_self_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_wire_self_bad.v:11:16: Wire inputs its own output, creating circular logic (wire x=x) - 11 | wire myself = myself; - | ^ +%Error: t/t_wire_self_bad.v:11:15: Wire inputs its own output, creating circular logic (wire x=x) + 11 | wire myself = myself; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_wire_self_bad.py b/test_regress/t/t_wire_self_bad.py index 2ce66844f..b6af58c86 100755 --- a/test_regress/t/t_wire_self_bad.py +++ b/test_regress/t/t_wire_self_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wire_self_bad.v b/test_regress/t/t_wire_self_bad.v index a35cad9c4..027274afd 100644 --- a/test_regress/t/t_wire_self_bad.v +++ b/test_regress/t/t_wire_self_bad.v @@ -2,12 +2,12 @@ // // Simple bi-directional alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - wire myself = myself; + wire myself = myself; endmodule diff --git a/test_regress/t/t_wire_trireg_unsup.py b/test_regress/t/t_wire_trireg_unsup.py index e33e10acf..3160d0589 100755 --- a/test_regress/t/t_wire_trireg_unsup.py +++ b/test_regress/t/t_wire_trireg_unsup.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wire_trireg_unsup.v b/test_regress/t/t_wire_trireg_unsup.v index dd5086be6..b0c2668e9 100644 --- a/test_regress/t/t_wire_trireg_unsup.v +++ b/test_regress/t/t_wire_trireg_unsup.v @@ -2,8 +2,8 @@ // // Simple bi-directional alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_wire_types.py b/test_regress/t/t_wire_types.py index 8b49c4409..62c1fbed7 100755 --- a/test_regress/t/t_wire_types.py +++ b/test_regress/t/t_wire_types.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wire_types.v b/test_regress/t/t_wire_types.v index d99864d9b..5d59ff1ce 100644 --- a/test_regress/t/t_wire_types.v +++ b/test_regress/t/t_wire_types.v @@ -1,38 +1,40 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - // IEEE: integer_atom_type - wire integer w_integer; + // IEEE: integer_atom_type + wire integer w_integer; - // IEEE: integer_atom_type - wire logic w_logic; + // IEEE: integer_atom_type + wire logic w_logic; - wire logic [1:0] w_logic2; + wire logic [1:0] w_logic2; - assign w_integer = -123456; + assign w_integer = -123456; - assign w_logic = 1'b1; + assign w_logic = 1'b1; - assign w_logic2 = 2'b10; + assign w_logic2 = 2'b10; - always @ (posedge clk) begin - `checkh(w_integer, -123456); - `checkh(w_logic, 1'b1); - `checkh(w_logic2, 2'b10); - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + `checkh(w_integer, -123456); + `checkh(w_logic, 1'b1); + `checkh(w_logic2, 2'b10); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_wired_net_test.py b/test_regress/t/t_wired_net_test.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_wired_net_test.py +++ b/test_regress/t/t_wired_net_test.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wired_net_test.v b/test_regress/t/t_wired_net_test.v old mode 100755 new mode 100644 index 741c558a1..7efed4033 --- a/test_regress/t/t_wired_net_test.v +++ b/test_regress/t/t_wired_net_test.v @@ -1,71 +1,73 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t( clk /*AUTOARG*/); - input clk; - wor [3:0] ptrior1; - trior [3:0] ptrior2; - wand [3:0] ptriand1; - triand [3:0] ptriand2; - wire [3:0] z1; - wire [3:0] z2; - wire [3:0] tri_z1; - wire [3:0] tri_z2; - logic [3:0] x; - logic [3:0] y; - logic [3:0] tri_x; - logic [3:0] tri_y; - logic [3:0] tri_x_dat; - logic [3:0] tri_y_dat; - logic [3:0] tri_x_en; - logic [3:0] tri_y_en; - assign ptrior1 = x & y; - assign ptrior1 = x + y; - assign ptrior2 = tri_x & tri_y; - assign ptrior2 = tri_x + tri_y; - assign ptriand1 = x & y; - assign ptriand1 = x + y; - assign ptriand2 = tri_x & tri_y; - assign ptriand2 = tri_x + tri_y; - assign z1 = (x & y) | (x + y); - assign z2 = (x & y) & (x + y); - assign tri_z1 = (tri_x & tri_y) | (tri_x + tri_y); - assign tri_z2 = (tri_x & tri_y) & (tri_x + tri_y); - integer cyc = 0; - integer xz_index = 0; - integer xz_num = 0; - integer i; - assign tri_x[0] = tri_x_en[0] ? tri_x_dat[0] : 1'bz; - assign tri_x[1] = tri_x_en[1] ? tri_x_dat[1] : 1'bz; - assign tri_x[2] = tri_x_en[2] ? tri_x_dat[2] : 1'bz; - assign tri_x[3] = tri_x_en[3] ? tri_x_dat[3] : 1'bz; - assign tri_y[0] = tri_y_en[0] ? tri_y_dat[0] : 1'bz; - assign tri_y[1] = tri_y_en[1] ? tri_y_dat[1] : 1'bz; - assign tri_y[2] = tri_y_en[2] ? tri_y_dat[2] : 1'bz; - assign tri_y[3] = tri_y_en[3] ? tri_y_dat[3] : 1'bz; - always @ (posedge clk) begin - cyc <= cyc + 1; - x = {$random}[3:0]; - y = {$random}[3:0]; - tri_x_dat = {$random}[3:0]; - tri_y_dat = {$random}[3:0]; - tri_x_en = {$random}[3:0]; - tri_y_en = {$random}[3:0]; - `checkb(ptrior1, z1); - `checkb(ptrior2, tri_z1); - `checkb(ptriand1, z2); - `checkb(ptriand2, tri_z2); - if (cyc == 20) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + input clk; + wor [3:0] ptrior1; + trior [3:0] ptrior2; + wand [3:0] ptriand1; + triand [3:0] ptriand2; + wire [3:0] z1; + wire [3:0] z2; + wire [3:0] tri_z1; + wire [3:0] tri_z2; + logic [3:0] x; + logic [3:0] y; + logic [3:0] tri_x; + logic [3:0] tri_y; + logic [3:0] tri_x_dat; + logic [3:0] tri_y_dat; + logic [3:0] tri_x_en; + logic [3:0] tri_y_en; + assign ptrior1 = x & y; + assign ptrior1 = x + y; + assign ptrior2 = tri_x & tri_y; + assign ptrior2 = tri_x + tri_y; + assign ptriand1 = x & y; + assign ptriand1 = x + y; + assign ptriand2 = tri_x & tri_y; + assign ptriand2 = tri_x + tri_y; + assign z1 = (x & y) | (x + y); + assign z2 = (x & y) & (x + y); + assign tri_z1 = (tri_x & tri_y) | (tri_x + tri_y); + assign tri_z2 = (tri_x & tri_y) & (tri_x + tri_y); + integer cyc = 0; + integer xz_index = 0; + integer xz_num = 0; + integer i; + assign tri_x[0] = tri_x_en[0] ? tri_x_dat[0] : 1'bz; + assign tri_x[1] = tri_x_en[1] ? tri_x_dat[1] : 1'bz; + assign tri_x[2] = tri_x_en[2] ? tri_x_dat[2] : 1'bz; + assign tri_x[3] = tri_x_en[3] ? tri_x_dat[3] : 1'bz; + assign tri_y[0] = tri_y_en[0] ? tri_y_dat[0] : 1'bz; + assign tri_y[1] = tri_y_en[1] ? tri_y_dat[1] : 1'bz; + assign tri_y[2] = tri_y_en[2] ? tri_y_dat[2] : 1'bz; + assign tri_y[3] = tri_y_en[3] ? tri_y_dat[3] : 1'bz; + always @ (posedge clk) begin + cyc <= cyc + 1; + x = {$random}[3:0]; + y = {$random}[3:0]; + tri_x_dat = {$random}[3:0]; + tri_y_dat = {$random}[3:0]; + tri_x_en = {$random}[3:0]; + tri_y_en = {$random}[3:0]; + `checkb(ptrior1, z1); + `checkb(ptrior2, tri_z1); + `checkb(ptriand1, z2); + `checkb(ptriand2, tri_z2); + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_with.py b/test_regress/t/t_with.py index d4f986441..3cc73805c 100755 --- a/test_regress/t/t_with.py +++ b/test_regress/t/t_with.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_with.v b/test_regress/t/t_with.v index d3f62df58..312e0e63c 100644 --- a/test_regress/t/t_with.v +++ b/test_regress/t/t_with.v @@ -2,8 +2,8 @@ // // Simple bi-directional alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 // verilog_format: off @@ -15,14 +15,14 @@ module t; initial begin - int tofind; - int aliases[$]; - int found[$]; - int i; - byte byteq[$] = {2, -1, 127}; - byte b[]; - logic [7:0] m[2][2]; - logic bit_arr[1024]; + automatic int tofind; + automatic int aliases[$]; + automatic int found[$]; + automatic int i; + automatic byte byteq[$] = {2, -1, 127}; + automatic byte b[]; + automatic logic [7:0] m[2][2]; + automatic logic bit_arr[1024]; aliases = '{1, 4, 6, 8}; tofind = 6; diff --git a/test_regress/t/t_with_suggest_bad.out b/test_regress/t/t_with_suggest_bad.out index 6c557eba3..17f794b97 100644 --- a/test_regress/t/t_with_suggest_bad.out +++ b/test_regress/t/t_with_suggest_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_with_suggest_bad.v:16:25: Can't find definition of variable: 'itemm' +%Error: t/t_with_suggest_bad.v:16:23: Can't find definition of variable: 'itemm' : ... Suggested alternative: 'item' - 16 | qv = q.find with (itemm == 2); - | ^~~~~ + 16 | qv = q.find with (itemm == 2); + | ^~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_with_suggest_bad.v:18:37: Can't find definition of variable: 'misspelledd' +%Error: t/t_with_suggest_bad.v:18:35: Can't find definition of variable: 'misspelledd' : ... Suggested alternative: 'misspelled' - 18 | qv = q.find(misspelled) with (misspelledd == 2); - | ^~~~~~~~~~~ + 18 | qv = q.find(misspelled) with (misspelledd == 2); + | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_with_suggest_bad.py b/test_regress/t/t_with_suggest_bad.py index 2ce66844f..b6af58c86 100755 --- a/test_regress/t/t_with_suggest_bad.py +++ b/test_regress/t/t_with_suggest_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_with_suggest_bad.v b/test_regress/t/t_with_suggest_bad.v index 3d7a4f77a..40a880483 100644 --- a/test_regress/t/t_with_suggest_bad.v +++ b/test_regress/t/t_with_suggest_bad.v @@ -2,20 +2,20 @@ // // Simple bi-directional alias test. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - int q[$]; - int qv[$]; // Value returns - q = '{1, 2, 2, 4, 3}; + initial begin + int q[$]; + int qv[$]; // Value returns + q = '{1, 2, 2, 4, 3}; - qv = q.find with (itemm == 2); + qv = q.find with (itemm == 2); - qv = q.find(misspelled) with (misspelledd == 2); - end + qv = q.find(misspelled) with (misspelledd == 2); + end endmodule diff --git a/test_regress/t/t_wrapper_clone.cpp b/test_regress/t/t_wrapper_clone.cpp index 296c00321..838e53b33 100644 --- a/test_regress/t/t_wrapper_clone.cpp +++ b/test_regress/t/t_wrapper_clone.cpp @@ -1,8 +1,8 @@ // // DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Yinan Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Yinan Xu // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_wrapper_clone.py b/test_regress/t/t_wrapper_clone.py index 123fd2a37..cb9e8dec6 100755 --- a/test_regress/t/t_wrapper_clone.py +++ b/test_regress/t/t_wrapper_clone.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wrapper_clone.v b/test_regress/t/t_wrapper_clone.v index fa6546a8b..2b0c2ce14 100644 --- a/test_regress/t/t_wrapper_clone.v +++ b/test_regress/t/t_wrapper_clone.v @@ -3,36 +3,36 @@ // This model counts from 0 to 8. It forks a child process (in C++) at 6 // and waits for the child to simulate and exit for resumption (of the parent). // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2023 by Yinan Xu. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2023 Yinan Xu // SPDX-License-Identifier: CC0-1.0 -module top( - input clock, - input reset, - input is_parent, - output do_clone +module top ( + input clock, + input reset, + input is_parent, + output do_clone ); -reg [3:0] counter; + reg [3:0] counter; -assign do_clone = counter == 4'h6; + assign do_clone = counter == 4'h6; -always @(posedge clock) begin - if (reset) begin - counter <= 4'h0; - end - else begin - counter <= counter + 4'h1; - $write("counter = %d\n", counter); - end - - if (counter[3]) begin - if (is_parent) begin - $write("*-* All Finished *-*\n"); + always @(posedge clock) begin + if (reset) begin + counter <= 4'h0; + end + else begin + counter <= counter + 4'h1; + $write("counter = %d\n", counter); + end + + if (counter[3]) begin + if (is_parent) begin + $write("*-* All Finished *-*\n"); + end + $finish(0); end - $finish(0); end -end endmodule diff --git a/test_regress/t/t_wrapper_context.cpp b/test_regress/t/t_wrapper_context.cpp index 267932a21..9651a71a6 100644 --- a/test_regress/t/t_wrapper_context.cpp +++ b/test_regress/t/t_wrapper_context.cpp @@ -1,8 +1,8 @@ // // DESCRIPTION: Verilator: Verilog Multiple Model Test Module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020-2021 by Andreas Kuster. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020-2021 Andreas Kuster // SPDX-License-Identifier: CC0-1.0 // diff --git a/test_regress/t/t_wrapper_context.py b/test_regress/t/t_wrapper_context.py index d6fa7e7c0..8df7e10ef 100755 --- a/test_regress/t/t_wrapper_context.py +++ b/test_regress/t/t_wrapper_context.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Multiple Model Test Module # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wrapper_context.v b/test_regress/t/t_wrapper_context.v index e0a833752..d448b091e 100644 --- a/test_regress/t/t_wrapper_context.v +++ b/test_regress/t/t_wrapper_context.v @@ -3,56 +3,53 @@ // This model counts from 0 to 10. It is instantiated twice in concurrent // threads to check for race conditions/signal interference. // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2020-2021 by Andreas Kuster. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2020-2021 Andreas Kuster // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" -module top - ( - input clk, - input rst, - input [31:0] trace_number, - input stop, - output bit [31:0] counter, - output bit done_o - ); +module top ( + input clk, + input rst, + input [31:0] trace_number, + input stop, + output bit [31:0] counter, + output bit done_o +); - initial begin - string number; - string filename; - number.itoa(trace_number); + initial begin + string number; + string filename; + number.itoa(trace_number); `ifdef TRACE_FST - filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".fst"}; + filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".fst"}; `else - filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".vcd"}; + filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".vcd"}; `endif - $display("Writing dumpfile '%s'", filename); - $dumpfile(filename); - $dumpvars(); - end + $display("Writing dumpfile '%s'", filename); + $dumpfile(filename); + $dumpvars(); + end - always@(posedge clk) begin - if (rst) - counter <= 0; - else - counter <= counter + 1; - end - always_comb begin - done_o = '0; - if (stop) begin - if (counter >= 5 && stop) begin - done_o = '1; - $stop; - end + always @(posedge clk) begin + if (rst) counter <= 0; + else counter <= counter + 1; + end + always_comb begin + done_o = '0; + if (stop) begin + if (counter >= 5 && stop) begin + done_o = '1; + $stop; end - else begin - if (counter >= 10) begin - done_o = '1; - $finish; - end + end + else begin + if (counter >= 10) begin + done_o = '1; + $finish; end - end + end + end endmodule diff --git a/test_regress/t/t_wrapper_context__top0.dat.out b/test_regress/t/t_wrapper_context__top0.dat.out index c12f007f4..07d4800da 100644 --- a/test_regress/t/t_wrapper_context__top0.dat.out +++ b/test_regress/t/t_wrapper_context__top0.dat.out @@ -1,150 +1,150 @@ # SystemC::Coverage-3 -C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:0->1htop0.top' 11 -C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:1->0htop0.top' 10 -C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:0->1htop0.top' 1 -C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:1->0htop0.top' 1 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:0->1htop0.top' 1 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:1->0htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:0->1htop0.top' 5 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:1->0htop0.top' 5 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:0->1htop0.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:1->0htop0.top' 0 -C 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'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[1]:0->1htop0.top' 3 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[1]:1->0htop0.top' 2 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[20]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[20]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[21]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[21]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[22]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[22]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[23]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[23]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[24]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[24]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[25]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[25]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[26]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[26]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[27]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[27]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[28]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[28]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[29]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[29]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[2]:0->1htop0.top' 1 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[2]:1->0htop0.top' 1 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[30]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[30]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[31]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[31]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[3]:0->1htop0.top' 1 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[3]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[4]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[4]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[5]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[5]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[6]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[6]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[7]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[7]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[8]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[8]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[9]:0->1htop0.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[9]:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl18n16ttogglepagev_toggle/topodone_o:0->1htop0.top' 1 +C 'ft/t_wrapper_context.vl18n16ttogglepagev_toggle/topodone_o:1->0htop0.top' 0 +C 'ft/t_wrapper_context.vl21n3tlinepagev_line/topoblockS21-24,28,30-32htop0.top' 1 +C 'ft/t_wrapper_context.vl35n3tlinepagev_line/topoblockS35htop0.top' 11 +C 'ft/t_wrapper_context.vl36n5tbranchpagev_branch/topoifS36htop0.top' 1 +C 'ft/t_wrapper_context.vl36n6tbranchpagev_branch/topoelseS37htop0.top' 10 +C 'ft/t_wrapper_context.vl39n3tlinepagev_line/topoblockS39-40htop0.top' 34 +C 'ft/t_wrapper_context.vl41n5tbranchpagev_branch/topoifS41htop0.top' 0 +C 'ft/t_wrapper_context.vl41n6tbranchpagev_branch/topoelseS47htop0.top' 34 +C 'ft/t_wrapper_context.vl42n24texprpagev_expr/topo((counter >= 32'sh5)==0) => 0htop0.top' 0 +C 'ft/t_wrapper_context.vl42n24texprpagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop0.top' 0 +C 'ft/t_wrapper_context.vl42n24texprpagev_expr/topo(stop==0) => 0htop0.top' 0 +C 'ft/t_wrapper_context.vl42n8tlinepagev_line/topoelsehtop0.top' 0 +C 'ft/t_wrapper_context.vl48n7tbranchpagev_branch/topoifS48-50htop0.top' 1 +C 'ft/t_wrapper_context.vl48n8tbranchpagev_branch/topoelsehtop0.top' 33 diff --git a/test_regress/t/t_wrapper_context__top1.dat.out b/test_regress/t/t_wrapper_context__top1.dat.out index dc2e16ccd..8ef66f3d0 100644 --- a/test_regress/t/t_wrapper_context__top1.dat.out +++ b/test_regress/t/t_wrapper_context__top1.dat.out @@ -1,150 +1,150 @@ # SystemC::Coverage-3 -C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:0->1htop1.top' 6 -C 'ft/t_wrapper_context.vl14n22ttogglepagev_toggle/topoclk:1->0htop1.top' 5 -C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:0->1htop1.top' 1 -C 'ft/t_wrapper_context.vl15n22ttogglepagev_toggle/toporst:1->0htop1.top' 1 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[0]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[10]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[11]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[12]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[13]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[14]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[15]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[16]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[17]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[18]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[19]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[1]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[20]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[21]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[22]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[23]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[24]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[25]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[26]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[27]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[28]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[29]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[2]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[30]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[31]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[3]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[4]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[5]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[6]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[7]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[8]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl16n22ttogglepagev_toggle/topotrace_number[9]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:0->1htop1.top' 1 -C 'ft/t_wrapper_context.vl17n22ttogglepagev_toggle/topostop:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:0->1htop1.top' 3 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[0]:1->0htop1.top' 2 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[10]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[11]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[12]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[13]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[14]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[15]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[16]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[17]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[18]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[19]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]:0->1htop1.top' 1 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[1]:1->0htop1.top' 1 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[20]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[21]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[22]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[23]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[24]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[25]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[26]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[27]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[28]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[29]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]:0->1htop1.top' 1 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[2]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[30]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[31]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[3]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[4]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[5]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[6]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[7]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[8]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]:0->1htop1.top' 0 -C 'ft/t_wrapper_context.vl18n22ttogglepagev_toggle/topocounter[9]:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_o:0->1htop1.top' 1 -C 'ft/t_wrapper_context.vl19n22ttogglepagev_toggle/topodone_o:1->0htop1.top' 0 -C 'ft/t_wrapper_context.vl22n4tlinepagev_line/topoblockS22,25,29,31-33htop1.top' 1 -C 'ft/t_wrapper_context.vl36n4tlinepagev_line/topoblockS36htop1.top' 6 -C 'ft/t_wrapper_context.vl37n7tbranchpagev_branch/topoifS37-38htop1.top' 1 -C 'ft/t_wrapper_context.vl37n8tbranchpagev_branch/topoelseS40htop1.top' 5 -C 'ft/t_wrapper_context.vl42n4tlinepagev_line/topoblockS42-43htop1.top' 19 -C 'ft/t_wrapper_context.vl44n7tbranchpagev_branch/topoifS44htop1.top' 19 -C 'ft/t_wrapper_context.vl44n8tbranchpagev_branch/topoelseS50htop1.top' 0 -C 'ft/t_wrapper_context.vl45n11tlinepagev_line/topoelsehtop1.top' 18 -C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo((counter >= 32'sh5)==0) => 0htop1.top' 18 -C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop1.top' 1 -C 'ft/t_wrapper_context.vl45n27texprpagev_expr/topo(stop==0) => 0htop1.top' 0 -C 'ft/t_wrapper_context.vl51n10tbranchpagev_branch/topoifS51-53htop1.top' 0 -C 'ft/t_wrapper_context.vl51n11tbranchpagev_branch/topoelsehtop1.top' 0 +C 'ft/t_wrapper_context.vl13n11ttogglepagev_toggle/topoclk:0->1htop1.top' 6 +C 'ft/t_wrapper_context.vl13n11ttogglepagev_toggle/topoclk:1->0htop1.top' 5 +C 'ft/t_wrapper_context.vl14n11ttogglepagev_toggle/toporst:0->1htop1.top' 1 +C 'ft/t_wrapper_context.vl14n11ttogglepagev_toggle/toporst:1->0htop1.top' 1 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[0]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[0]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[10]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[10]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[11]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[11]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[12]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[12]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[13]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[13]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[14]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[14]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[15]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[15]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[16]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[16]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[17]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[17]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[18]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[18]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[19]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[19]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[1]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[1]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[20]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[20]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[21]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[21]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[22]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[22]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[23]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[23]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[24]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[24]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[25]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[25]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[26]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[26]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[27]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[27]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[28]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[28]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[29]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[29]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[2]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[2]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[30]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[30]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[31]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[31]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[3]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[3]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[4]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[4]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[5]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[5]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[6]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[6]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[7]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[7]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[8]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[8]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[9]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl15n18ttogglepagev_toggle/topotrace_number[9]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl16n11ttogglepagev_toggle/topostop:0->1htop1.top' 1 +C 'ft/t_wrapper_context.vl16n11ttogglepagev_toggle/topostop:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[0]:0->1htop1.top' 3 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[0]:1->0htop1.top' 2 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[10]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[10]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[11]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[11]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[12]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[12]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[13]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[13]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[14]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[14]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[15]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[15]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[16]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[16]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[17]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[17]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[18]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[18]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[19]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[19]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[1]:0->1htop1.top' 1 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[1]:1->0htop1.top' 1 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[20]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[20]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[21]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[21]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[22]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[22]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[23]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[23]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[24]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[24]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[25]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[25]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[26]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[26]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[27]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[27]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[28]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[28]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[29]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[29]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[2]:0->1htop1.top' 1 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[2]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[30]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[30]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[31]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[31]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[3]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[3]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[4]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[4]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[5]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[5]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[6]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[6]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[7]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[7]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[8]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[8]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[9]:0->1htop1.top' 0 +C 'ft/t_wrapper_context.vl17n23ttogglepagev_toggle/topocounter[9]:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl18n16ttogglepagev_toggle/topodone_o:0->1htop1.top' 1 +C 'ft/t_wrapper_context.vl18n16ttogglepagev_toggle/topodone_o:1->0htop1.top' 0 +C 'ft/t_wrapper_context.vl21n3tlinepagev_line/topoblockS21-24,28,30-32htop1.top' 1 +C 'ft/t_wrapper_context.vl35n3tlinepagev_line/topoblockS35htop1.top' 6 +C 'ft/t_wrapper_context.vl36n5tbranchpagev_branch/topoifS36htop1.top' 1 +C 'ft/t_wrapper_context.vl36n6tbranchpagev_branch/topoelseS37htop1.top' 5 +C 'ft/t_wrapper_context.vl39n3tlinepagev_line/topoblockS39-40htop1.top' 19 +C 'ft/t_wrapper_context.vl41n5tbranchpagev_branch/topoifS41htop1.top' 19 +C 'ft/t_wrapper_context.vl41n6tbranchpagev_branch/topoelseS47htop1.top' 0 +C 'ft/t_wrapper_context.vl42n24texprpagev_expr/topo((counter >= 32'sh5)==0) => 0htop1.top' 18 +C 'ft/t_wrapper_context.vl42n24texprpagev_expr/topo((counter >= 32'sh5)==1 && stop==1) => 1htop1.top' 1 +C 'ft/t_wrapper_context.vl42n24texprpagev_expr/topo(stop==0) => 0htop1.top' 0 +C 'ft/t_wrapper_context.vl42n8tlinepagev_line/topoelsehtop1.top' 18 +C 'ft/t_wrapper_context.vl48n7tbranchpagev_branch/topoifS48-50htop1.top' 0 +C 'ft/t_wrapper_context.vl48n8tbranchpagev_branch/topoelsehtop1.top' 0 diff --git a/test_regress/t/t_wrapper_context_fst.py b/test_regress/t/t_wrapper_context_fst.py index 414ff4ea2..b4bed53eb 100755 --- a/test_regress/t/t_wrapper_context_fst.py +++ b/test_regress/t/t_wrapper_context_fst.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Multiple Model Test Module # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wrapper_context_seq.py b/test_regress/t/t_wrapper_context_seq.py index ebcdee42e..3a1222abc 100755 --- a/test_regress/t/t_wrapper_context_seq.py +++ b/test_regress/t/t_wrapper_context_seq.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Multiple Model Test Module # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wrapper_del_context_bad.cpp b/test_regress/t/t_wrapper_del_context_bad.cpp index b825a5a4b..994315bf2 100644 --- a/test_regress/t/t_wrapper_del_context_bad.cpp +++ b/test_regress/t/t_wrapper_del_context_bad.cpp @@ -1,8 +1,8 @@ // // DESCRIPTION: Verilator: Verilog Multiple Model Test Module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_wrapper_del_context_bad.py b/test_regress/t/t_wrapper_del_context_bad.py index a7310eb61..8ec19f0ba 100755 --- a/test_regress/t/t_wrapper_del_context_bad.py +++ b/test_regress/t/t_wrapper_del_context_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Multiple Model Test Module # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wrapper_del_context_bad.v b/test_regress/t/t_wrapper_del_context_bad.v index f4ae87f02..a98854c51 100644 --- a/test_regress/t/t_wrapper_del_context_bad.v +++ b/test_regress/t/t_wrapper_del_context_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module top; - initial $finish; + initial $finish; endmodule diff --git a/test_regress/t/t_wrapper_legacy.cpp b/test_regress/t/t_wrapper_legacy.cpp index be799c77d..058a97d01 100644 --- a/test_regress/t/t_wrapper_legacy.cpp +++ b/test_regress/t/t_wrapper_legacy.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Wilson Snyder and Marlon James. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_wrapper_legacy.py b/test_regress/t/t_wrapper_legacy.py index 5aaf32d75..d31ccfb6f 100755 --- a/test_regress/t/t_wrapper_legacy.py +++ b/test_regress/t/t_wrapper_legacy.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wrapper_legacy.v b/test_regress/t/t_wrapper_legacy.v index c6fd4a2e0..8bde01c10 100644 --- a/test_regress/t/t_wrapper_legacy.v +++ b/test_regress/t/t_wrapper_legacy.v @@ -1,24 +1,24 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2021 Wilson Snyder and Marlon James. +// SPDX-FileCopyrightText: 2021 Wilson Snyder and Marlon James // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); - input clk; - int count; + input clk; + int count; - always @(posedge clk) begin - count <= count + 1; - if (count == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + count <= count + 1; + if (count == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule : t diff --git a/test_regress/t/t_wrapper_legacy_time64.py b/test_regress/t/t_wrapper_legacy_time64.py index 1e14ef94a..b57318aa7 100755 --- a/test_regress/t/t_wrapper_legacy_time64.py +++ b/test_regress/t/t_wrapper_legacy_time64.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wrapper_legacy_timed.py b/test_regress/t/t_wrapper_legacy_timed.py index 74ebc2c1b..11f2e6178 100755 --- a/test_regress/t/t_wrapper_legacy_timed.py +++ b/test_regress/t/t_wrapper_legacy_timed.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wrapper_reuse_context_bad.cpp b/test_regress/t/t_wrapper_reuse_context_bad.cpp index 684fee858..859680341 100644 --- a/test_regress/t/t_wrapper_reuse_context_bad.cpp +++ b/test_regress/t/t_wrapper_reuse_context_bad.cpp @@ -1,8 +1,8 @@ // // DESCRIPTION: Verilator: Verilog Multiple Model Test Module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2024 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_wrapper_reuse_context_bad.py b/test_regress/t/t_wrapper_reuse_context_bad.py index a7310eb61..8ec19f0ba 100755 --- a/test_regress/t/t_wrapper_reuse_context_bad.py +++ b/test_regress/t/t_wrapper_reuse_context_bad.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Multiple Model Test Module # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_wrapper_reuse_context_bad.v b/test_regress/t/t_wrapper_reuse_context_bad.v index f4ae87f02..a98854c51 100644 --- a/test_regress/t/t_wrapper_reuse_context_bad.v +++ b/test_regress/t/t_wrapper_reuse_context_bad.v @@ -1,9 +1,9 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2022 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 module top; - initial $finish; + initial $finish; endmodule diff --git a/test_regress/t/t_x_assign.cpp b/test_regress/t/t_x_assign.cpp index eec3f5816..fe52af097 100644 --- a/test_regress/t/t_x_assign.cpp +++ b/test_regress/t/t_x_assign.cpp @@ -1,10 +1,10 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_x_assign.v b/test_regress/t/t_x_assign.v index e031bae31..4a940619a 100644 --- a/test_regress/t/t_x_assign.v +++ b/test_regress/t/t_x_assign.v @@ -1,18 +1,19 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Copyright 2020 by Geza Lore. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t_x_assign( - input wire clk, - output reg o, - output reg[31:0] o_int +module t_x_assign ( + input wire clk, + output reg o, + output reg [31:0] o_int ); - always @(posedge clk) begin - if (1'bx) o <= 1'd1; else o <= 1'd0; - o_int <= 'x; - end + always @(posedge clk) begin + if (1'bx) o <= 1'd1; + else o <= 1'd0; + o_int <= 'x; + end endmodule diff --git a/test_regress/t/t_x_assign_0.py b/test_regress/t/t_x_assign_0.py index 37663b85c..586ae8f62 100755 --- a/test_regress/t/t_x_assign_0.py +++ b/test_regress/t/t_x_assign_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_assign_1.py b/test_regress/t/t_x_assign_1.py index 97778b4f0..8957289a5 100755 --- a/test_regress/t/t_x_assign_1.py +++ b/test_regress/t/t_x_assign_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_assign_unique_0.py b/test_regress/t/t_x_assign_unique_0.py index 22aa92b35..723512416 100755 --- a/test_regress/t/t_x_assign_unique_0.py +++ b/test_regress/t/t_x_assign_unique_0.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_assign_unique_1.py b/test_regress/t/t_x_assign_unique_1.py index 22aa92b35..723512416 100755 --- a/test_regress/t/t_x_assign_unique_1.py +++ b/test_regress/t/t_x_assign_unique_1.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_rand_mt_stability.out b/test_regress/t/t_x_rand_mt_stability.out index 0eecc36cb..422585c0b 100644 --- a/test_regress/t/t_x_rand_mt_stability.out +++ b/test_regress/t/t_x_rand_mt_stability.out @@ -1,17 +1,17 @@ -uninitialized = 0xf5bbcbc0 +uninitialized = 0xb108d062 x_assigned (initial) = 0x00000000 -uninitialized2 = 0xa979eb54 -big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 -random_init = 0x952aaa76 -top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 -top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 -top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd -top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 -rand = 0xb3cf9302 -rand = 0xf0acf3e4 -rand = 0xca0ac74c -rand = 0x4eddfc2c -rand = 0x1919db69 -x_assigned = 0x486aeb2d -Last rand = 0x2d118c9b +uninitialized2 = 0xca249856 +big = 0x0d97b7afc0a2ac6784d0eaa74cd8feaf468cf05328c319f1a26fc1b219605edd +random_init = 0x65d066c8 +top.t.the_sub_yes_inline_1 no_init 0x6f6ddbaeadd8dba4 +top.t.the_sub_yes_inline_2 no_init 0xfdf89c0b44e7f5d8 +top.t.the_sub_no_inline_1 no_init 0x76dc510f643e939 +top.t.the_sub_no_inline_2 no_init 0x61a6ab3d0369cf60 +rand = 0xc31fbc3d +rand = 0xcbb440c9 +rand = 0x030234c6 +rand = 0xf53bab60 +rand = 0xcf071500 +x_assigned = 0x80742d9b +Last rand = 0xddacca56 *-* All Finished *-* diff --git a/test_regress/t/t_x_rand_mt_stability.py b/test_regress/t/t_x_rand_mt_stability.py index 459473d4d..820119492 100755 --- a/test_regress/t/t_x_rand_mt_stability.py +++ b/test_regress/t/t_x_rand_mt_stability.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_rand_mt_stability_add.out b/test_regress/t/t_x_rand_mt_stability_add.out index 0eecc36cb..422585c0b 100644 --- a/test_regress/t/t_x_rand_mt_stability_add.out +++ b/test_regress/t/t_x_rand_mt_stability_add.out @@ -1,17 +1,17 @@ -uninitialized = 0xf5bbcbc0 +uninitialized = 0xb108d062 x_assigned (initial) = 0x00000000 -uninitialized2 = 0xa979eb54 -big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 -random_init = 0x952aaa76 -top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 -top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 -top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd -top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 -rand = 0xb3cf9302 -rand = 0xf0acf3e4 -rand = 0xca0ac74c -rand = 0x4eddfc2c -rand = 0x1919db69 -x_assigned = 0x486aeb2d -Last rand = 0x2d118c9b +uninitialized2 = 0xca249856 +big = 0x0d97b7afc0a2ac6784d0eaa74cd8feaf468cf05328c319f1a26fc1b219605edd +random_init = 0x65d066c8 +top.t.the_sub_yes_inline_1 no_init 0x6f6ddbaeadd8dba4 +top.t.the_sub_yes_inline_2 no_init 0xfdf89c0b44e7f5d8 +top.t.the_sub_no_inline_1 no_init 0x76dc510f643e939 +top.t.the_sub_no_inline_2 no_init 0x61a6ab3d0369cf60 +rand = 0xc31fbc3d +rand = 0xcbb440c9 +rand = 0x030234c6 +rand = 0xf53bab60 +rand = 0xcf071500 +x_assigned = 0x80742d9b +Last rand = 0xddacca56 *-* All Finished *-* diff --git a/test_regress/t/t_x_rand_mt_stability_add.py b/test_regress/t/t_x_rand_mt_stability_add.py index 0dc0f0af8..0bcc359a5 100755 --- a/test_regress/t/t_x_rand_mt_stability_add.py +++ b/test_regress/t/t_x_rand_mt_stability_add.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_rand_mt_stability_add_trace.out b/test_regress/t/t_x_rand_mt_stability_add_trace.out index 0eecc36cb..422585c0b 100644 --- a/test_regress/t/t_x_rand_mt_stability_add_trace.out +++ b/test_regress/t/t_x_rand_mt_stability_add_trace.out @@ -1,17 +1,17 @@ -uninitialized = 0xf5bbcbc0 +uninitialized = 0xb108d062 x_assigned (initial) = 0x00000000 -uninitialized2 = 0xa979eb54 -big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 -random_init = 0x952aaa76 -top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 -top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 -top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd -top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 -rand = 0xb3cf9302 -rand = 0xf0acf3e4 -rand = 0xca0ac74c -rand = 0x4eddfc2c -rand = 0x1919db69 -x_assigned = 0x486aeb2d -Last rand = 0x2d118c9b +uninitialized2 = 0xca249856 +big = 0x0d97b7afc0a2ac6784d0eaa74cd8feaf468cf05328c319f1a26fc1b219605edd +random_init = 0x65d066c8 +top.t.the_sub_yes_inline_1 no_init 0x6f6ddbaeadd8dba4 +top.t.the_sub_yes_inline_2 no_init 0xfdf89c0b44e7f5d8 +top.t.the_sub_no_inline_1 no_init 0x76dc510f643e939 +top.t.the_sub_no_inline_2 no_init 0x61a6ab3d0369cf60 +rand = 0xc31fbc3d +rand = 0xcbb440c9 +rand = 0x030234c6 +rand = 0xf53bab60 +rand = 0xcf071500 +x_assigned = 0x80742d9b +Last rand = 0xddacca56 *-* All Finished *-* diff --git a/test_regress/t/t_x_rand_mt_stability_add_trace.py b/test_regress/t/t_x_rand_mt_stability_add_trace.py index 0e6d3dc4f..278edc8c2 100755 --- a/test_regress/t/t_x_rand_mt_stability_add_trace.py +++ b/test_regress/t/t_x_rand_mt_stability_add_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_rand_mt_stability_trace.out b/test_regress/t/t_x_rand_mt_stability_trace.out index 0eecc36cb..422585c0b 100644 --- a/test_regress/t/t_x_rand_mt_stability_trace.out +++ b/test_regress/t/t_x_rand_mt_stability_trace.out @@ -1,17 +1,17 @@ -uninitialized = 0xf5bbcbc0 +uninitialized = 0xb108d062 x_assigned (initial) = 0x00000000 -uninitialized2 = 0xa979eb54 -big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 -random_init = 0x952aaa76 -top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 -top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 -top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd -top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 -rand = 0xb3cf9302 -rand = 0xf0acf3e4 -rand = 0xca0ac74c -rand = 0x4eddfc2c -rand = 0x1919db69 -x_assigned = 0x486aeb2d -Last rand = 0x2d118c9b +uninitialized2 = 0xca249856 +big = 0x0d97b7afc0a2ac6784d0eaa74cd8feaf468cf05328c319f1a26fc1b219605edd +random_init = 0x65d066c8 +top.t.the_sub_yes_inline_1 no_init 0x6f6ddbaeadd8dba4 +top.t.the_sub_yes_inline_2 no_init 0xfdf89c0b44e7f5d8 +top.t.the_sub_no_inline_1 no_init 0x76dc510f643e939 +top.t.the_sub_no_inline_2 no_init 0x61a6ab3d0369cf60 +rand = 0xc31fbc3d +rand = 0xcbb440c9 +rand = 0x030234c6 +rand = 0xf53bab60 +rand = 0xcf071500 +x_assigned = 0x80742d9b +Last rand = 0xddacca56 *-* All Finished *-* diff --git a/test_regress/t/t_x_rand_mt_stability_trace.py b/test_regress/t/t_x_rand_mt_stability_trace.py index b7248be24..042bf344a 100755 --- a/test_regress/t/t_x_rand_mt_stability_trace.py +++ b/test_regress/t/t_x_rand_mt_stability_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_rand_mt_stability_zeros.out b/test_regress/t/t_x_rand_mt_stability_zeros.out index 573a7650c..635f134ab 100644 --- a/test_regress/t/t_x_rand_mt_stability_zeros.out +++ b/test_regress/t/t_x_rand_mt_stability_zeros.out @@ -2,16 +2,16 @@ uninitialized = 0x00000000 x_assigned (initial) = 0x00000000 uninitialized2 = 0x00000000 big = 0x0000000000000000000000000000000000000000000000000000000000000000 -random_init = 0x952aaa76 +random_init = 0x65d066c8 top.t.the_sub_yes_inline_1 no_init 0x0 top.t.the_sub_yes_inline_2 no_init 0x0 top.t.the_sub_no_inline_1 no_init 0x0 top.t.the_sub_no_inline_2 no_init 0x0 -rand = 0xb3cf9302 -rand = 0xf0acf3e4 -rand = 0xca0ac74c -rand = 0x4eddfc2c -rand = 0x1919db69 -x_assigned = 0x486aeb2d -Last rand = 0x2d118c9b +rand = 0xc31fbc3d +rand = 0xcbb440c9 +rand = 0x030234c6 +rand = 0xf53bab60 +rand = 0xcf071500 +x_assigned = 0x80742d9b +Last rand = 0xddacca56 *-* All Finished *-* diff --git a/test_regress/t/t_x_rand_mt_stability_zeros.py b/test_regress/t/t_x_rand_mt_stability_zeros.py index a82b8586d..8a062d04d 100755 --- a/test_regress/t/t_x_rand_mt_stability_zeros.py +++ b/test_regress/t/t_x_rand_mt_stability_zeros.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_rand_scoped_is_random.py b/test_regress/t/t_x_rand_scoped_is_random.py new file mode 100755 index 000000000..4d5a57238 --- /dev/null +++ b/test_regress/t/t_x_rand_scoped_is_random.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios("simulator_st") + +test.compile(timing_loop=True, verilator_flags2=["--timing"]) + +filename = test.obj_dir + "/bits.log" + +test.unlink_ok(filename) + +for seed in range(1, 6): + test.execute(all_run_flags=["+verilator+rand+reset+2", f"+verilator+seed+{seed}"]) + +unique_strings = set() + +with open(filename, "r", encoding="utf-8") as file: + for line in file: + unique_strings.update(line.split()) + +count_unique_strings = len(unique_strings) + +# A ideal random generator has a fail chance of 1 in 66 million +expected_unique_strings = 4 +if count_unique_strings < expected_unique_strings: + test.error( + f"Expected at least {expected_unique_strings} unique strings, got {count_unique_strings}") + +test.passes() diff --git a/test_regress/t/t_x_rand_scoped_is_random.v b/test_regress/t/t_x_rand_scoped_is_random.v new file mode 100644 index 000000000..e3b4ce968 --- /dev/null +++ b/test_regress/t/t_x_rand_scoped_is_random.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2016 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t (); + reg a0 = 'x; + reg a1 = 'x; + reg a2 = 'x; + reg a3 = 'x; + reg a4 = 'x; + reg a5 = 'x; + reg a6 = 'x; + reg a7 = 'x; + reg a8 = 'x; + reg a9 = 'x; + reg a10 = 'x; + reg a11 = 'x; + reg a12 = 'x; + reg a13 = 'x; + reg a14 = 'x; + reg a15 = 'x; + + integer fd; + initial begin + fd = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/bits.log"}, "a"); + $fwrite(fd, "%b\n", {a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15}); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_x_rand_stability.out b/test_regress/t/t_x_rand_stability.out index 6a22ff04e..65d07b271 100644 --- a/test_regress/t/t_x_rand_stability.out +++ b/test_regress/t/t_x_rand_stability.out @@ -1,17 +1,17 @@ -uninitialized = 0xf5bbcbc0 +uninitialized = 0xb108d062 x_assigned (initial) = 0x00000000 -uninitialized2 = 0xa979eb54 -big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 -random_init = 0x952aaa76 -top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 -top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 -top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd -top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 -rand = 0xe3e54aaa -rand = 0xe85acf2d -rand = 0x15e12c6a -rand = 0x0f7f28c0 -rand = 0xe189c52a -x_assigned = 0x486aeb2d -Last rand = 0xf0700dbf +uninitialized2 = 0xca249856 +big = 0x0d97b7afc0a2ac6784d0eaa74cd8feaf468cf05328c319f1a26fc1b219605edd +random_init = 0x65d066c8 +top.t.the_sub_yes_inline_1 no_init 0x6f6ddbaeadd8dba4 +top.t.the_sub_yes_inline_2 no_init 0xfdf89c0b44e7f5d8 +top.t.the_sub_no_inline_1 no_init 0x76dc510f643e939 +top.t.the_sub_no_inline_2 no_init 0x61a6ab3d0369cf60 +rand = 0xf89a1fb9 +rand = 0x0577f875 +rand = 0x7bc34037 +rand = 0x2027e5c6 +rand = 0xc57ff769 +x_assigned = 0x80742d9b +Last rand = 0x37a9fa91 *-* All Finished *-* diff --git a/test_regress/t/t_x_rand_stability.py b/test_regress/t/t_x_rand_stability.py index a08c45ed6..e992309d3 100755 --- a/test_regress/t/t_x_rand_stability.py +++ b/test_regress/t/t_x_rand_stability.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_rand_stability.v b/test_regress/t/t_x_rand_stability.v index 5c47811ee..6d0ed08e8 100644 --- a/test_regress/t/t_x_rand_stability.v +++ b/test_regress/t/t_x_rand_stability.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Confirm x randomization stability // -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Todd Strader // SPDX-License-Identifier: CC0-1.0 @@ -9,66 +9,66 @@ module t ( input clk ); - int cyc = 0; + int cyc = 0; - logic [31:0] uninitialized; - logic [31:0] x_assigned = '0; + logic [31:0] uninitialized; + logic [31:0] x_assigned = '0; `ifdef ADD_SIGNAL - logic [31:0] added; - logic [31:0] x_assigned_added = '0; + logic [31:0] added; + logic [31:0] x_assigned_added = '0; `endif - logic [31:0] unused; - logic [31:0] x_assigned_unused = '0; - logic [31:0] uninitialized2; - logic [255:0] big; - int random_init = $random(); + logic [31:0] unused; + logic [31:0] x_assigned_unused = '0; + logic [31:0] uninitialized2; + logic [255:0] big; + int random_init = $random(); - sub_no_inline the_sub_no_inline_1(); - sub_no_inline the_sub_no_inline_2(); - sub_yes_inline the_sub_yes_inline_1(); - sub_yes_inline the_sub_yes_inline_2(); + sub_no_inline the_sub_no_inline_1 (); + sub_no_inline the_sub_no_inline_2 (); + sub_yes_inline the_sub_yes_inline_1 (); + sub_yes_inline the_sub_yes_inline_2 (); - initial begin - $display("uninitialized = 0x%x", uninitialized); - $display("x_assigned (initial) = 0x%x", x_assigned); - $display("uninitialized2 = 0x%x", uninitialized2); - $display("big = 0x%x", big); - $display("random_init = 0x%x", random_init); - end + initial begin + $display("uninitialized = 0x%x", uninitialized); + $display("x_assigned (initial) = 0x%x", x_assigned); + $display("uninitialized2 = 0x%x", uninitialized2); + $display("big = 0x%x", big); + $display("random_init = 0x%x", random_init); + end - always @(posedge clk) begin - x_assigned_unused = 'x; - x_assigned <= 'x; + always @(posedge clk) begin + x_assigned_unused = 'x; + x_assigned <= 'x; `ifdef ADD_SIGNAL - x_assigned_added <= 'x; + x_assigned_added <= 'x; `endif - cyc <= cyc + 1; - $display("rand = 0x%x", $random()); - if (cyc == 4) begin - $display("x_assigned = 0x%x", x_assigned); + cyc <= cyc + 1; + $display("rand = 0x%x", $random()); + if (cyc == 4) begin + $display("x_assigned = 0x%x", x_assigned); `ifndef NOT_RAND - if (uninitialized == uninitialized2) $stop(); - if (the_sub_yes_inline_1.no_init == the_sub_yes_inline_2.no_init) $stop(); - if (the_sub_no_inline_1.no_init == the_sub_no_inline_2.no_init) $stop(); + if (uninitialized == uninitialized2) $stop(); + if (the_sub_yes_inline_1.no_init == the_sub_yes_inline_2.no_init) $stop(); + if (the_sub_no_inline_1.no_init == the_sub_no_inline_2.no_init) $stop(); `endif `ifdef ADD_SIGNAL - if (added == 0) $stop(); - if (x_assigned_added == 0) $stop(); + if (added == 0) $stop(); + if (x_assigned_added == 0) $stop(); `endif - $display("Last rand = 0x%x", $random()); - $write("*-* All Finished *-*\n"); - $finish; - end + $display("Last rand = 0x%x", $random()); + $write("*-* All Finished *-*\n"); + $finish; end + end endmodule -module sub_no_inline; /* verilator no_inline_module */ - logic [63:0] no_init; - initial $display("%m no_init 0x%0x", no_init); +module sub_no_inline; /* verilator no_inline_module */ + logic [63:0] no_init; + initial $display("%m no_init 0x%0x", no_init); endmodule -module sub_yes_inline; /* verilator inline_module */ - logic [63:0] no_init; - initial $display("%m no_init 0x%0x", no_init); +module sub_yes_inline; /* verilator inline_module */ + logic [63:0] no_init; + initial $display("%m no_init 0x%0x", no_init); endmodule diff --git a/test_regress/t/t_x_rand_stability_add.out b/test_regress/t/t_x_rand_stability_add.out index 6a22ff04e..65d07b271 100644 --- a/test_regress/t/t_x_rand_stability_add.out +++ b/test_regress/t/t_x_rand_stability_add.out @@ -1,17 +1,17 @@ -uninitialized = 0xf5bbcbc0 +uninitialized = 0xb108d062 x_assigned (initial) = 0x00000000 -uninitialized2 = 0xa979eb54 -big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 -random_init = 0x952aaa76 -top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 -top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 -top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd -top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 -rand = 0xe3e54aaa -rand = 0xe85acf2d -rand = 0x15e12c6a -rand = 0x0f7f28c0 -rand = 0xe189c52a -x_assigned = 0x486aeb2d -Last rand = 0xf0700dbf +uninitialized2 = 0xca249856 +big = 0x0d97b7afc0a2ac6784d0eaa74cd8feaf468cf05328c319f1a26fc1b219605edd +random_init = 0x65d066c8 +top.t.the_sub_yes_inline_1 no_init 0x6f6ddbaeadd8dba4 +top.t.the_sub_yes_inline_2 no_init 0xfdf89c0b44e7f5d8 +top.t.the_sub_no_inline_1 no_init 0x76dc510f643e939 +top.t.the_sub_no_inline_2 no_init 0x61a6ab3d0369cf60 +rand = 0xf89a1fb9 +rand = 0x0577f875 +rand = 0x7bc34037 +rand = 0x2027e5c6 +rand = 0xc57ff769 +x_assigned = 0x80742d9b +Last rand = 0x37a9fa91 *-* All Finished *-* diff --git a/test_regress/t/t_x_rand_stability_add.py b/test_regress/t/t_x_rand_stability_add.py index c2766d031..4d2c7c257 100755 --- a/test_regress/t/t_x_rand_stability_add.py +++ b/test_regress/t/t_x_rand_stability_add.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_rand_stability_add_trace.out b/test_regress/t/t_x_rand_stability_add_trace.out index 6a22ff04e..65d07b271 100644 --- a/test_regress/t/t_x_rand_stability_add_trace.out +++ b/test_regress/t/t_x_rand_stability_add_trace.out @@ -1,17 +1,17 @@ -uninitialized = 0xf5bbcbc0 +uninitialized = 0xb108d062 x_assigned (initial) = 0x00000000 -uninitialized2 = 0xa979eb54 -big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 -random_init = 0x952aaa76 -top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 -top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 -top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd -top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 -rand = 0xe3e54aaa -rand = 0xe85acf2d -rand = 0x15e12c6a -rand = 0x0f7f28c0 -rand = 0xe189c52a -x_assigned = 0x486aeb2d -Last rand = 0xf0700dbf +uninitialized2 = 0xca249856 +big = 0x0d97b7afc0a2ac6784d0eaa74cd8feaf468cf05328c319f1a26fc1b219605edd +random_init = 0x65d066c8 +top.t.the_sub_yes_inline_1 no_init 0x6f6ddbaeadd8dba4 +top.t.the_sub_yes_inline_2 no_init 0xfdf89c0b44e7f5d8 +top.t.the_sub_no_inline_1 no_init 0x76dc510f643e939 +top.t.the_sub_no_inline_2 no_init 0x61a6ab3d0369cf60 +rand = 0xf89a1fb9 +rand = 0x0577f875 +rand = 0x7bc34037 +rand = 0x2027e5c6 +rand = 0xc57ff769 +x_assigned = 0x80742d9b +Last rand = 0x37a9fa91 *-* All Finished *-* diff --git a/test_regress/t/t_x_rand_stability_add_trace.py b/test_regress/t/t_x_rand_stability_add_trace.py index ea6207b6e..ace3b9790 100755 --- a/test_regress/t/t_x_rand_stability_add_trace.py +++ b/test_regress/t/t_x_rand_stability_add_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_rand_stability_trace.out b/test_regress/t/t_x_rand_stability_trace.out index 6a22ff04e..65d07b271 100644 --- a/test_regress/t/t_x_rand_stability_trace.out +++ b/test_regress/t/t_x_rand_stability_trace.out @@ -1,17 +1,17 @@ -uninitialized = 0xf5bbcbc0 +uninitialized = 0xb108d062 x_assigned (initial) = 0x00000000 -uninitialized2 = 0xa979eb54 -big = 0xa20c93ac50d8c57d4c80949aa68e82775da6af98ce08f75dc6ccfad97b059a33 -random_init = 0x952aaa76 -top.t.the_sub_yes_inline_1 no_init 0x4a544f7798b83fc8 -top.t.the_sub_yes_inline_2 no_init 0x19b7000ee0472c9 -top.t.the_sub_no_inline_1 no_init 0x38121a34978975dd -top.t.the_sub_no_inline_2 no_init 0x9022c84ae0fa3cf6 -rand = 0xe3e54aaa -rand = 0xe85acf2d -rand = 0x15e12c6a -rand = 0x0f7f28c0 -rand = 0xe189c52a -x_assigned = 0x486aeb2d -Last rand = 0xf0700dbf +uninitialized2 = 0xca249856 +big = 0x0d97b7afc0a2ac6784d0eaa74cd8feaf468cf05328c319f1a26fc1b219605edd +random_init = 0x65d066c8 +top.t.the_sub_yes_inline_1 no_init 0x6f6ddbaeadd8dba4 +top.t.the_sub_yes_inline_2 no_init 0xfdf89c0b44e7f5d8 +top.t.the_sub_no_inline_1 no_init 0x76dc510f643e939 +top.t.the_sub_no_inline_2 no_init 0x61a6ab3d0369cf60 +rand = 0xf89a1fb9 +rand = 0x0577f875 +rand = 0x7bc34037 +rand = 0x2027e5c6 +rand = 0xc57ff769 +x_assigned = 0x80742d9b +Last rand = 0x37a9fa91 *-* All Finished *-* diff --git a/test_regress/t/t_x_rand_stability_trace.py b/test_regress/t/t_x_rand_stability_trace.py index 05c2f308d..3ff7d8e20 100755 --- a/test_regress/t/t_x_rand_stability_trace.py +++ b/test_regress/t/t_x_rand_stability_trace.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_x_rand_stability_zeros.out b/test_regress/t/t_x_rand_stability_zeros.out index fe1f4ba0a..f9e43c0b3 100644 --- a/test_regress/t/t_x_rand_stability_zeros.out +++ b/test_regress/t/t_x_rand_stability_zeros.out @@ -2,16 +2,16 @@ uninitialized = 0x00000000 x_assigned (initial) = 0x00000000 uninitialized2 = 0x00000000 big = 0x0000000000000000000000000000000000000000000000000000000000000000 -random_init = 0x952aaa76 +random_init = 0x65d066c8 top.t.the_sub_yes_inline_1 no_init 0x0 top.t.the_sub_yes_inline_2 no_init 0x0 top.t.the_sub_no_inline_1 no_init 0x0 top.t.the_sub_no_inline_2 no_init 0x0 -rand = 0xe3e54aaa -rand = 0xe85acf2d -rand = 0x15e12c6a -rand = 0x0f7f28c0 -rand = 0xe189c52a -x_assigned = 0x486aeb2d -Last rand = 0xf0700dbf +rand = 0xf89a1fb9 +rand = 0x0577f875 +rand = 0x7bc34037 +rand = 0x2027e5c6 +rand = 0xc57ff769 +x_assigned = 0x80742d9b +Last rand = 0x37a9fa91 *-* All Finished *-* diff --git a/test_regress/t/t_x_rand_stability_zeros.py b/test_regress/t/t_x_rand_stability_zeros.py index c872e4dd0..78dac3f86 100755 --- a/test_regress/t/t_x_rand_stability_zeros.py +++ b/test_regress/t/t_x_rand_stability_zeros.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_xml_begin_hier.out b/test_regress/t/t_xml_begin_hier.out deleted file mode 100644 index efb01dd5f..000000000 --- a/test_regress/t/t_xml_begin_hier.out +++ /dev/null @@ -1,82 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_begin_hier.py b/test_regress/t/t_xml_begin_hier.py deleted file mode 100755 index 06a5adc58..000000000 --- a/test_regress/t/t_xml_begin_hier.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_begin_hier.v b/test_regress/t/t_xml_begin_hier.v deleted file mode 100644 index 1e29f0133..000000000 --- a/test_regress/t/t_xml_begin_hier.v +++ /dev/null @@ -1,33 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Risto Pejasinovic. -// SPDX-License-Identifier: CC0-1.0 - -module submod2 (); -endmodule - -module submod #( -)(); - if(1) begin : submod_gen - wire l1_sig; - if(1) begin : nested_gen - submod2 submod_nested(); - end - submod2 submod_l1(); - end - submod2 submod_l0(); -endmodule - -module test( -); - genvar N; - generate for(N=0; N<2; N=N+1) - begin : FOR_GENERATE - submod submod_for(); - if(1) begin - submod submod_2(); - end - submod submod_3(); - end endgenerate -endmodule diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out deleted file mode 100644 index 92e2667ae..000000000 --- a/test_regress/t/t_xml_debugcheck.out +++ /dev/null @@ -1,1854 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_debugcheck.py b/test_regress/t/t_xml_debugcheck.py deleted file mode 100755 index 000592728..000000000 --- a/test_regress/t/t_xml_debugcheck.py +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_enum_type_methods.v" - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '--debug-check', '--flatten', '--inline-cfuncs', '0'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename, 'logfile') - -# make sure that certain tags are present in --debug-check -# that would not be present in --xml-only -test.file_grep(out_filename, r'') # for and -test.file_grep(out_filename, r' signed=') # for -test.file_grep(out_filename, r' func=') # for - -test.passes() diff --git a/test_regress/t/t_xml_deprecated_bad.out b/test_regress/t/t_xml_deprecated_bad.out deleted file mode 100644 index 838a455b0..000000000 --- a/test_regress/t/t_xml_deprecated_bad.out +++ /dev/null @@ -1,4 +0,0 @@ -%Warning-DEPRECATED: Option --xml-only is deprecated, move to --json-only - ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest - ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. -%Error: Exiting due to diff --git a/test_regress/t/t_xml_deprecated_bad.py b/test_regress/t/t_xml_deprecated_bad.py deleted file mode 100755 index 7d78f956d..000000000 --- a/test_regress/t/t_xml_deprecated_bad.py +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = 't/t_EXAMPLE.v' - -test.compile(verilator_flags2=["--xml-only --xml-output /dev/null"], - fails=True, - expect_filename=test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_first.out b/test_regress/t/t_xml_first.out deleted file mode 100644 index b7d6859a7..000000000 --- a/test_regress/t/t_xml_first.out +++ /dev/null @@ -1,88 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_first.py b/test_regress/t/t_xml_first.py deleted file mode 100755 index 06a5adc58..000000000 --- a/test_regress/t/t_xml_first.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_first.v b/test_regress/t/t_xml_first.v deleted file mode 100644 index 7e594036d..000000000 --- a/test_regress/t/t_xml_first.v +++ /dev/null @@ -1,55 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Outputs - q, - // Inputs - clk, d - ); - input clk; - input [3:0] d; - output wire [3:0] q; - - logic [3:0] between; - - mod1 #(.WIDTH(4)) - cell1 (.q(between), - .clk (clk), - .d (d[3:0])); - - mod2 - cell2 (.d(between), - .q (q[3:0]), - .clk (clk)); - -endmodule - -module mod1 - #(parameter WIDTH = 32) - ( - input clk, - input [WIDTH-1:0] d, - output logic [WIDTH-1:0] q - ); - - localparam IGNORED = 1; - - always @(posedge clk) - q <= d; - -endmodule - -module mod2 - ( - input clk, - input [3:0] d, - output wire [3:0] q - ); - - assign q = d; - -endmodule diff --git a/test_regress/t/t_xml_flat.out b/test_regress/t/t_xml_flat.out deleted file mode 100644 index 13058eb77..000000000 --- a/test_regress/t/t_xml_flat.out +++ /dev/null @@ -1,135 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_flat.py b/test_regress/t/t_xml_flat.py deleted file mode 100755 index 5c6842ae3..000000000 --- a/test_regress/t/t_xml_flat.py +++ /dev/null @@ -1,24 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') -test.top_filename = "t/t_xml_first.v" - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_flat_no_inline_mod.out b/test_regress/t/t_xml_flat_no_inline_mod.out deleted file mode 100644 index 64359a65f..000000000 --- a/test_regress/t/t_xml_flat_no_inline_mod.out +++ /dev/null @@ -1,45 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_flat_no_inline_mod.py b/test_regress/t/t_xml_flat_no_inline_mod.py deleted file mode 100755 index 046b5ff50..000000000 --- a/test_regress/t/t_xml_flat_no_inline_mod.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_flat_no_inline_mod.v b/test_regress/t/t_xml_flat_no_inline_mod.v deleted file mode 100644 index cf87b71a0..000000000 --- a/test_regress/t/t_xml_flat_no_inline_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module foo(input logic i_clk); /* verilator no_inline_module */ -endmodule - -// --flatten forces inlining of 'no_inline_module' module foo. -module top(input logic i_clk); - foo f(.*); -endmodule diff --git a/test_regress/t/t_xml_flat_pub_mod.out b/test_regress/t/t_xml_flat_pub_mod.out deleted file mode 100644 index 68288d263..000000000 --- a/test_regress/t/t_xml_flat_pub_mod.out +++ /dev/null @@ -1,45 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_flat_pub_mod.py b/test_regress/t/t_xml_flat_pub_mod.py deleted file mode 100755 index 046b5ff50..000000000 --- a/test_regress/t/t_xml_flat_pub_mod.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_flat_pub_mod.v b/test_regress/t/t_xml_flat_pub_mod.v deleted file mode 100644 index 4fa40e587..000000000 --- a/test_regress/t/t_xml_flat_pub_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2008 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module foo(input logic i_clk); /* verilator public_module */ -endmodule - -// --flatten forces inlining of public module foo. -module top(input logic i_clk); - foo f(.*); -endmodule diff --git a/test_regress/t/t_xml_flat_vlvbound.out b/test_regress/t/t_xml_flat_vlvbound.out deleted file mode 100644 index 61b6d875d..000000000 --- a/test_regress/t/t_xml_flat_vlvbound.out +++ /dev/null @@ -1,220 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_flat_vlvbound.py b/test_regress/t/t_xml_flat_vlvbound.py deleted file mode 100755 index 046b5ff50..000000000 --- a/test_regress/t/t_xml_flat_vlvbound.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_flat_vlvbound.v b/test_regress/t/t_xml_flat_vlvbound.v deleted file mode 100644 index 9ed0db0cf..000000000 --- a/test_regress/t/t_xml_flat_vlvbound.v +++ /dev/null @@ -1,27 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2012 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module vlvbound_test - ( - input logic [15:0] i_a, - input logic [15:0] i_b, - output logic [6:0] o_a, - output logic [6:0] o_b - ); - - function automatic logic [6:0] foo(input logic [15:0] val); - logic [6:0] ret; - integer i; - for (i=0 ; i < 7; i++) begin - ret[i] = (val[i*2 +: 2] == 2'b00); - end - return ret; - endfunction - - assign o_a = foo(i_a); - assign o_b = foo(i_b); - -endmodule diff --git a/test_regress/t/t_xml_output.out b/test_regress/t/t_xml_output.out deleted file mode 100644 index 198efb7bc..000000000 --- a/test_regress/t/t_xml_output.out +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_output.py b/test_regress/t/t_xml_output.py deleted file mode 100755 index 09f0d91b5..000000000 --- a/test_regress/t/t_xml_output.py +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/renamed-" + test.name + ".xml" - -test.compile( - verilator_flags2=["--no-std", "-Wno-DEPRECATED --xml-only --xml-output", out_filename], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -for filename in test.glob_some(test.obj_dir + "/*"): - if (re.search(r'\.log', filename) # Made by driver.py, not Verilator sources - or re.search(r'\.status', filename) # Made by driver.py, not Verilator sources - or re.search(r'renamed-', filename)): # Requested output - continue - test.error("%Error: Created '" + filename + "', but --xml-only shouldn't create files") - -test.passes() diff --git a/test_regress/t/t_xml_primary_io.out b/test_regress/t/t_xml_primary_io.out deleted file mode 100644 index 2b047aa91..000000000 --- a/test_regress/t/t_xml_primary_io.out +++ /dev/null @@ -1,62 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_primary_io.py b/test_regress/t/t_xml_primary_io.py deleted file mode 100755 index 1d5702fef..000000000 --- a/test_regress/t/t_xml_primary_io.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2025 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_primary_io.v b/test_regress/t/t_xml_primary_io.v deleted file mode 100644 index 832cdb87e..000000000 --- a/test_regress/t/t_xml_primary_io.v +++ /dev/null @@ -1,30 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2025 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module top(clk, a1, a2, ready); - input clk; - input a1; - input a2; - output ready; - - wire ready_reg; - - and2_x1 and_cell ( - .a1(a1), - .a2(a2), - .zn(ready_reg) - ); - - assign ready = ready_reg; -endmodule - -module and2_x1 ( - input wire a1, - input wire a2, - output wire zn -); - assign zn = (a1 & a2); -endmodule diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out deleted file mode 100644 index f43c235e8..000000000 --- a/test_regress/t/t_xml_tag.out +++ /dev/null @@ -1,86 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/test_regress/t/t_xml_tag.py b/test_regress/t/t_xml_tag.py deleted file mode 100755 index 06a5adc58..000000000 --- a/test_regress/t/t_xml_tag.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/env python3 -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -import vltest_bootstrap - -test.scenarios('vlt') - -out_filename = test.obj_dir + "/V" + test.name + ".xml" - -test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], - verilator_make_gmake=False, - make_top_shell=False, - make_main=False) - -test.files_identical(out_filename, test.golden_filename) - -test.passes() diff --git a/test_regress/t/t_xml_tag.v b/test_regress/t/t_xml_tag.v deleted file mode 100644 index a47cd18d7..000000000 --- a/test_regress/t/t_xml_tag.v +++ /dev/null @@ -1,44 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Chris Randall. -// SPDX-License-Identifier: CC0-1.0 - -interface ifc; - integer value; - modport out_modport (output value); -endinterface - -module m - ( - input clk_ip, // verilator tag clk_ip - input rst_ip, - output foo_op); // verilator tag foo_op - - // This is a comment - - typedef struct packed { - logic clk; /* verilator tag this is clk */ - logic k; /* verilator lint_off UNUSED */ - logic enable; // verilator tag enable - logic data; // verilator tag data - } my_struct; // verilator tag my_struct - - // This is a comment - - ifc itop(); - - my_struct this_struct [2]; // verilator tag this_struct - - wire [31:0] dotted = itop.value; - - function void f(input string m); - $display("%s", m); - endfunction - - initial begin - // Contains all 256 characters except 0 (null character) - f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff"); - end - -endmodule diff --git a/test_regress/t/tsub/t_flag_f_tsub.v b/test_regress/t/tsub/t_flag_f_tsub.v index 04329e761..fdffb37e4 100644 --- a/test_regress/t/tsub/t_flag_f_tsub.v +++ b/test_regress/t/tsub/t_flag_f_tsub.v @@ -1,3 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2010-2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 `define GOT_DEF6 diff --git a/test_regress/t/tsub/t_flag_f_tsub.vc b/test_regress/t/tsub/t_flag_f_tsub.vc index aa7e76cf1..209d35225 100644 --- a/test_regress/t/tsub/t_flag_f_tsub.vc +++ b/test_regress/t/tsub/t_flag_f_tsub.vc @@ -1,4 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2010-2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 +define+GOT_DEF4=1 +incdir+. diff --git a/test_regress/t/tsub/t_flag_f_tsub_inc.v b/test_regress/t/tsub/t_flag_f_tsub_inc.v index 840561da1..0749780d8 100644 --- a/test_regress/t/tsub/t_flag_f_tsub_inc.v +++ b/test_regress/t/tsub/t_flag_f_tsub_inc.v @@ -1,3 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2010-2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 `define GOT_DEF5 diff --git a/test_regress/t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c b/test_regress/t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c index 2d2c741c9..f4cb9ea7a 100644 --- a/test_regress/t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c +++ b/test_regress/t/uvm/v2017_1_0/dpi/uvm_hdl_verilator.c @@ -135,6 +135,7 @@ static vpiHandle uvm_hdl_handle_by_name_partsel(char *path, int *is_partsel_ptr, { vpiHandle rh; s_vpi_value value; + int req_width_m1; int decl_ranged = 0; int decl_lo; int decl_hi; @@ -162,12 +163,13 @@ static vpiHandle uvm_hdl_handle_by_name_partsel(char *path, int *is_partsel_ptr, } // vpi_printf((PLI_BYTE8 *)"%s:%d: req %d:%d decl %d:%d for '%s'\n", // __FILE__, __LINE__, *hi_ptr, *lo_ptr, decl_left, decl_right, path); - decl_lo = (decl_left < decl_right) ? decl_left : decl_right; + decl_lo = (decl_left > decl_right) ? decl_right : decl_left; decl_hi = (decl_left > decl_right) ? decl_left : decl_right; if (*lo_ptr < decl_lo) return 0; if (*hi_ptr > decl_hi) return 0; - *lo_ptr -= decl_lo; - *hi_ptr -= decl_lo; + req_width_m1 = *hi_ptr - *lo_ptr; + *lo_ptr = (decl_left > decl_right) ? (*lo_ptr - decl_lo) : (decl_right - *hi_ptr); + *hi_ptr = *lo_ptr + req_width_m1; } return r; } @@ -184,13 +186,6 @@ static int uvm_hdl_set_vlog(char *path, p_vpi_vecval value, PLI_INT32 flag) { int size; static int s_maxsize = -1; - if (flag == vpiForceFlag || flag == vpiReleaseFlag) { - // It appears other simulator interfaces likewise don't support this - m_uvm_error("UVM/DPI/VLOG_GET", "Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path '%s'", - path); - return 0; - } - r = uvm_hdl_handle_by_name_partsel(path, &is_partsel, &hi, &lo); if (r == 0) { m_uvm_error("UVM/DPI/HDL_SET", diff --git a/test_regress/t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c b/test_regress/t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c index 2d2c741c9..f4cb9ea7a 100644 --- a/test_regress/t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c +++ b/test_regress/t/uvm/v2020_3_1/dpi/uvm_hdl_verilator.c @@ -135,6 +135,7 @@ static vpiHandle uvm_hdl_handle_by_name_partsel(char *path, int *is_partsel_ptr, { vpiHandle rh; s_vpi_value value; + int req_width_m1; int decl_ranged = 0; int decl_lo; int decl_hi; @@ -162,12 +163,13 @@ static vpiHandle uvm_hdl_handle_by_name_partsel(char *path, int *is_partsel_ptr, } // vpi_printf((PLI_BYTE8 *)"%s:%d: req %d:%d decl %d:%d for '%s'\n", // __FILE__, __LINE__, *hi_ptr, *lo_ptr, decl_left, decl_right, path); - decl_lo = (decl_left < decl_right) ? decl_left : decl_right; + decl_lo = (decl_left > decl_right) ? decl_right : decl_left; decl_hi = (decl_left > decl_right) ? decl_left : decl_right; if (*lo_ptr < decl_lo) return 0; if (*hi_ptr > decl_hi) return 0; - *lo_ptr -= decl_lo; - *hi_ptr -= decl_lo; + req_width_m1 = *hi_ptr - *lo_ptr; + *lo_ptr = (decl_left > decl_right) ? (*lo_ptr - decl_lo) : (decl_right - *hi_ptr); + *hi_ptr = *lo_ptr + req_width_m1; } return r; } @@ -184,13 +186,6 @@ static int uvm_hdl_set_vlog(char *path, p_vpi_vecval value, PLI_INT32 flag) { int size; static int s_maxsize = -1; - if (flag == vpiForceFlag || flag == vpiReleaseFlag) { - // It appears other simulator interfaces likewise don't support this - m_uvm_error("UVM/DPI/VLOG_GET", "Unsupported: uvh_hdl_force/uvm_hdl_release on hdl path '%s'", - path); - return 0; - } - r = uvm_hdl_handle_by_name_partsel(path, &is_partsel, &hi, &lo); if (r == 0) { m_uvm_error("UVM/DPI/HDL_SET", diff --git a/test_regress/t/vltest_bootstrap.py b/test_regress/t/vltest_bootstrap.py index b299e9207..21b29daa2 100755 --- a/test_regress/t/vltest_bootstrap.py +++ b/test_regress/t/vltest_bootstrap.py @@ -1,9 +1,9 @@ # DESCRIPTION: Verilator: Verilog Test bootstrap loader # -# Copyright 2024 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import os diff --git a/verilator-config-version.cmake.in b/verilator-config-version.cmake.in index ece52b650..f4d8e66b3 100644 --- a/verilator-config-version.cmake.in +++ b/verilator-config-version.cmake.in @@ -7,10 +7,10 @@ # # find_package(verilator 4.0) # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in index d5c96372b..2da925698 100644 --- a/verilator-config.cmake.in +++ b/verilator-config.cmake.in @@ -11,10 +11,10 @@ # add_executable(simulator ) # verilate(simulator SOURCES ) # -# Copyright 2003-2026 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025-2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ######################################################################